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Differential D49648

rebased version of D37461
Needs ReviewPublic

Authored by thakis on Jul 22 2018, 11:33 AM.
This revision needs review, but there are no reviewers specified.

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Event Timeline

thakis created this revision.Jul 22 2018, 11:33 AM
Herald added a subscriber: hiraditya. · View Herald TranscriptJul 22 2018, 11:33 AM
thakis updated this revision to Diff 156707.Jul 22 2018, 11:34 AM
thakis updated this revision to Diff 184828.Feb 1 2019, 1:05 PM

rebase

thakis updated this revision to Diff 184829.Feb 1 2019, 1:06 PM

fix assert on

$ cat test.cc
void Int64ShrlMod32(unsigned __int64 Value) {
  __asm {
    mov edx, dword ptr [Value+4]
  }
}
$ out/gn/bin/clang-cl -c test.cc

(also fires a lot during ninja -C out/gn check-clang)

thakis mentioned this in D37461: [X86][AsmParser] re-introduce 'offset' operator.Feb 1 2019, 1:14 PM
thakis updated this revision to Diff 184865.Feb 1 2019, 4:18 PM

make https://bugs.llvm.org/show_bug.cgi?id=36676#c8 work

Revision Contents

PathSize
llvm/
include/
llvm/
MC/
MCParser/
35 lines
lib/
MC/
MCParser/
9 lines
Target/
X86/
AsmParser/
193 lines
test/
CodeGen/
X86/
15 lines
MC/
X86/
13 lines

Diff 184865

llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h

Show First 20 Lines • Show All 57 Lines • ▼ Show 20 Lines
// Represnt the various parts which makes up an intel expression, // Represnt the various parts which makes up an intel expression,
// used for emitting compound intel expressions // used for emitting compound intel expressions
struct IntelExpr { struct IntelExpr {
bool NeedBracs; bool NeedBracs;
int64_t Imm; int64_t Imm;
StringRef BaseReg; StringRef BaseReg;
StringRef IndexReg; StringRef IndexReg;
StringRef OffsetName;
unsigned Scale; unsigned Scale;
IntelExpr(bool needBracs = false) : NeedBracs(needBracs), Imm(0), IntelExpr() : NeedBracs(false), Imm(0), BaseReg(StringRef()),
BaseReg(StringRef()), IndexReg(StringRef()), IndexReg(StringRef()), OffsetName(StringRef()), Scale(1) {}
Scale(1) {} // [BaseReg + IndexReg * ScaleExpression + OFFSET name + ImmediateExpression]
// Compund immediate expression IntelExpr(StringRef baseReg, StringRef indexReg, unsigned scale,
IntelExpr(int64_t imm, bool needBracs) : IntelExpr(needBracs) { StringRef offsetName, int64_t imm, bool needBracs)
Imm = imm; : NeedBracs(needBracs), Imm(imm), BaseReg(baseReg), IndexReg(indexReg),
} OffsetName(offsetName), Scale(1) {
// [Reg + ImmediateExpression]
// We don't bother to emit an immediate expression evaluated to zero
IntelExpr(StringRef reg, int64_t imm = 0, unsigned scale = 0,
bool needBracs = true) :
IntelExpr(imm, needBracs) {
IndexReg = reg;
if (scale) if (scale)
Scale = scale; Scale = scale;
} }
// [BaseReg + IndexReg * ScaleExpression + ImmediateExpression]
IntelExpr(StringRef baseReg, StringRef indexReg, unsigned scale = 0,
int64_t imm = 0, bool needBracs = true) :
IntelExpr(indexReg, imm, scale, needBracs) {
BaseReg = baseReg;
}
bool hasBaseReg() const { bool hasBaseReg() const {
return BaseReg.size(); return BaseReg.size();
} }
bool hasIndexReg() const { bool hasIndexReg() const {
return IndexReg.size(); return IndexReg.size();
} }
bool hasRegs() const { bool hasRegs() const {
return hasBaseReg() || hasIndexReg(); return hasBaseReg() || hasIndexReg();
} }
bool hasOffset() const {
return OffsetName.size();
}
// Normally we won't emit immediates unconditionally,
// unless we've got no other components
bool emitImm() const {
return !(hasRegs() || hasOffset());
}
bool isValid() const { bool isValid() const {
return (Scale == 1) || return (Scale == 1) ||
(hasIndexReg() && (Scale == 2 || Scale == 4 || Scale == 8)); (hasIndexReg() && (Scale == 2 || Scale == 4 || Scale == 8));
} }
}; };
struct AsmRewrite { struct AsmRewrite {
AsmRewriteKind Kind; AsmRewriteKind Kind;
▲ Show 20 Lines • Show All 393 Lines • Show Last 20 Lines

llvm/lib/MC/MCParser/AsmParser.cpp

Show First 20 Lines • Show All 5,780 Lines • ▼ Show 20 Lines case AOK_IntelExpr:
if (AR.IntelExp.NeedBracs) if (AR.IntelExp.NeedBracs)
OS << "["; OS << "[";
if (AR.IntelExp.hasBaseReg()) if (AR.IntelExp.hasBaseReg())
OS << AR.IntelExp.BaseReg; OS << AR.IntelExp.BaseReg;
if (AR.IntelExp.hasIndexReg()) if (AR.IntelExp.hasIndexReg())
OS << (AR.IntelExp.hasBaseReg() ? " + " : "") OS << (AR.IntelExp.hasBaseReg() ? " + " : "")
<< AR.IntelExp.IndexReg; << AR.IntelExp.IndexReg;
if (AR.IntelExp.Scale > 1) if (AR.IntelExp.Scale > 1)
OS << " * $$" << AR.IntelExp.Scale; OS << " * $$" << AR.IntelExp.Scale;
if (AR.IntelExp.Imm || !AR.IntelExp.hasRegs()) if (AR.IntelExp.hasOffset())
OS << (AR.IntelExp.hasRegs() ? " + $$" : "$$") << AR.IntelExp.Imm; OS << (AR.IntelExp.hasRegs() ? " + offset " : "offset ")
<< AR.IntelExp.OffsetName;
if (AR.IntelExp.Imm || AR.IntelExp.emitImm())
OS << (AR.IntelExp.emitImm() ? "$$" : " + $$") << AR.IntelExp.Imm;
if (AR.IntelExp.NeedBracs) if (AR.IntelExp.NeedBracs)
OS << "]"; OS << "]";
break; break;
case AOK_Label: case AOK_Label:
OS << Ctx.getAsmInfo()->getPrivateLabelPrefix() << AR.Label; OS << Ctx.getAsmInfo()->getPrivateLabelPrefix() << AR.Label;
break; break;
case AOK_Input: case AOK_Input:
OS << '$' << InputIdx++; OS << '$' << InputIdx++;
▲ Show 20 Lines • Show All 143 Lines • Show Last 20 Lines

llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp

Show First 20 Lines • Show All 119 Lines • ▼ Show 20 Lines enum InfixCalculatorTok {
IC_REGISTER IC_REGISTER
}; };
enum IntelOperatorKind { enum IntelOperatorKind {
IOK_INVALID = 0, IOK_INVALID = 0,
IOK_LENGTH, IOK_LENGTH,
IOK_SIZE, IOK_SIZE,
IOK_TYPE, IOK_TYPE,
IOK_OFFSET
}; };
class InfixCalculator { class InfixCalculator {
typedef std::pair< InfixCalculatorTok, int64_t > ICToken; typedef std::pair< InfixCalculatorTok, int64_t > ICToken;
SmallVector<InfixCalculatorTok, 4> InfixOperatorStack; SmallVector<InfixCalculatorTok, 4> InfixOperatorStack;
SmallVector<ICToken, 4> PostfixStack; SmallVector<ICToken, 4> PostfixStack;
bool isUnaryOperator(const InfixCalculatorTok Op) { bool isUnaryOperator(const InfixCalculatorTok Op) {
▲ Show 20 Lines • Show All 175 Lines • ▼ Show 20 Lines enum IntelExprState {
IES_INIT, IES_INIT,
IES_OR, IES_OR,
IES_XOR, IES_XOR,
IES_AND, IES_AND,
IES_LSHIFT, IES_LSHIFT,
IES_RSHIFT, IES_RSHIFT,
IES_PLUS, IES_PLUS,
IES_MINUS, IES_MINUS,
IES_OFFSET,
IES_NOT, IES_NOT,
IES_MULTIPLY, IES_MULTIPLY,
IES_DIVIDE, IES_DIVIDE,
IES_MOD, IES_MOD,
IES_LBRAC, IES_LBRAC,
IES_RBRAC, IES_RBRAC,
IES_LPAREN, IES_LPAREN,
IES_RPAREN, IES_RPAREN,
IES_REGISTER, IES_REGISTER,
IES_INTEGER, IES_INTEGER,
IES_IDENTIFIER, IES_IDENTIFIER,
IES_ERROR IES_ERROR
}; };
class IntelExprStateMachine { class IntelExprStateMachine {
IntelExprState State, PrevState; IntelExprState State, PrevState;
unsigned BaseReg, IndexReg, TmpReg, Scale; unsigned BaseReg, IndexReg, TmpReg, Scale;
int64_t Imm; int64_t Imm;
const MCExpr *Sym; const MCExpr *Sym;
StringRef SymName; StringRef SymName;
InfixCalculator IC; InfixCalculator IC;
InlineAsmIdentifierInfo Info; InlineAsmIdentifierInfo Info;
short BracCount; short BracCount;
bool MemExpr; bool MemExpr;
bool OffsetOperator;
bool setSymRef(const MCExpr *Val, StringRef ID, StringRef &ErrMsg) {
if (Sym) {
ErrMsg = "cannot use more than one symbol in memory operand";
return true;
}
Sym = Val;
SymName = ID;
return false;
}
public: public:
IntelExprStateMachine() IntelExprStateMachine()
: State(IES_INIT), PrevState(IES_ERROR), BaseReg(0), IndexReg(0), : State(IES_INIT), PrevState(IES_ERROR), BaseReg(0), IndexReg(0),
TmpReg(0), Scale(0), Imm(0), Sym(nullptr), BracCount(0), TmpReg(0), Scale(0), Imm(0), Sym(nullptr), BracCount(0),
MemExpr(false) {} MemExpr(false), OffsetOperator(false) {}
void addImm(int64_t imm) { Imm += imm; } void addImm(int64_t imm) { Imm += imm; }
short getBracCount() { return BracCount; } short getBracCount() { return BracCount; }
bool isMemExpr() { return MemExpr; } bool isMemExpr() { return MemExpr; }
bool isOffsetOperator() { return OffsetOperator; }
unsigned getBaseReg() { return BaseReg; } unsigned getBaseReg() { return BaseReg; }
unsigned getIndexReg() { return IndexReg; } unsigned getIndexReg() { return IndexReg; }
unsigned getScale() { return Scale; } unsigned getScale() { return Scale; }
const MCExpr *getSym() { return Sym; } const MCExpr *getSym() { return Sym; }
StringRef getSymName() { return SymName; } StringRef getSymName() { return SymName; }
int64_t getImm() { return Imm + IC.execute(); } int64_t getImm() { return Imm + IC.execute(); }
bool isValidEndState() { bool isValidEndState() {
return State == IES_RBRAC || State == IES_INTEGER; return State == IES_RBRAC || State == IES_INTEGER;
▲ Show 20 Lines • Show All 80 Lines • ▼ Show 20 Lines bool onPlus(StringRef &ErrMsg) {
IntelExprState CurrState = State; IntelExprState CurrState = State;
switch (State) { switch (State) {
default: default:
State = IES_ERROR; State = IES_ERROR;
break; break;
case IES_INTEGER: case IES_INTEGER:
case IES_RPAREN: case IES_RPAREN:
case IES_REGISTER: case IES_REGISTER:
case IES_OFFSET:
State = IES_PLUS; State = IES_PLUS;
IC.pushOperator(IC_PLUS); IC.pushOperator(IC_PLUS);
if (CurrState == IES_REGISTER && PrevState != IES_MULTIPLY) { if (CurrState == IES_REGISTER && PrevState != IES_MULTIPLY) {
// If we already have a BaseReg, then assume this is the IndexReg with // If we already have a BaseReg, then assume this is the IndexReg with
// no explicit scale. // no explicit scale.
if (!BaseReg) { if (!BaseReg) {
BaseReg = TmpReg; BaseReg = TmpReg;
} else { } else {
Show All 28 Lines bool onMinus(StringRef &ErrMsg) {
case IES_MOD: case IES_MOD:
case IES_LPAREN: case IES_LPAREN:
case IES_RPAREN: case IES_RPAREN:
case IES_LBRAC: case IES_LBRAC:
case IES_RBRAC: case IES_RBRAC:
case IES_INTEGER: case IES_INTEGER:
case IES_REGISTER: case IES_REGISTER:
case IES_INIT: case IES_INIT:
case IES_OFFSET:
State = IES_MINUS; State = IES_MINUS;
// push minus operator if it is not a negate operator // push minus operator if it is not a negate operator
if (CurrState == IES_REGISTER || CurrState == IES_RPAREN || if (CurrState == IES_REGISTER || CurrState == IES_RPAREN ||
CurrState == IES_INTEGER || CurrState == IES_RBRAC) CurrState == IES_INTEGER || CurrState == IES_RBRAC ||
CurrState == IES_OFFSET)
IC.pushOperator(IC_MINUS); IC.pushOperator(IC_MINUS);
else if (PrevState == IES_REGISTER && CurrState == IES_MULTIPLY) { else if (PrevState == IES_REGISTER && CurrState == IES_MULTIPLY) {
// We have negate operator for Scale: it's illegal // We have negate operator for Scale: it's illegal
ErrMsg = "Scale can't be negative"; ErrMsg = "Scale can't be negative";
return true; return true;
} else } else
IC.pushOperator(IC_NEG); IC.pushOperator(IC_NEG);
if (CurrState == IES_REGISTER && PrevState != IES_MULTIPLY) { if (CurrState == IES_REGISTER && PrevState != IES_MULTIPLY) {
Show All 36 Lines void onNot() {
case IES_LBRAC: case IES_LBRAC:
case IES_INIT: case IES_INIT:
State = IES_NOT; State = IES_NOT;
IC.pushOperator(IC_NOT); IC.pushOperator(IC_NOT);
break; break;
} }
PrevState = CurrState; PrevState = CurrState;
} }
bool onRegister(unsigned Reg, StringRef &ErrMsg) { bool onRegister(unsigned Reg, StringRef &ErrMsg) {
IntelExprState CurrState = State; IntelExprState CurrState = State;
switch (State) { switch (State) {
default: default:
State = IES_ERROR; State = IES_ERROR;
break; break;
case IES_PLUS: case IES_PLUS:
case IES_LPAREN: case IES_LPAREN:
Show All 31 Lines bool onIdentifierExpr(const MCExpr *SymRef, StringRef SymRefName,
// InlineAsm: Treat an enum value as an integer // InlineAsm: Treat an enum value as an integer
if (ParsingInlineAsm) if (ParsingInlineAsm)
if (IDInfo.isKind(InlineAsmIdentifierInfo::IK_EnumVal)) if (IDInfo.isKind(InlineAsmIdentifierInfo::IK_EnumVal))
return onInteger(IDInfo.Enum.EnumVal, ErrMsg); return onInteger(IDInfo.Enum.EnumVal, ErrMsg);
// Treat a symbolic constant like an integer // Treat a symbolic constant like an integer
if (auto *CE = dyn_cast<MCConstantExpr>(SymRef)) if (auto *CE = dyn_cast<MCConstantExpr>(SymRef))
return onInteger(CE->getValue(), ErrMsg); return onInteger(CE->getValue(), ErrMsg);
PrevState = State; PrevState = State;
bool HasSymbol = Sym != nullptr;
switch (State) { switch (State) {
default: default:
State = IES_ERROR; State = IES_ERROR;
break; break;
case IES_PLUS: case IES_PLUS:
case IES_MINUS: case IES_MINUS:
case IES_NOT: case IES_NOT:
case IES_INIT: case IES_INIT:
case IES_LBRAC: case IES_LBRAC:
if (setSymRef(SymRef, SymRefName, ErrMsg))
return true;
MemExpr = true; MemExpr = true;
State = IES_INTEGER; State = IES_INTEGER;
Sym = SymRef;
SymName = SymRefName;
IC.pushOperand(IC_IMM); IC.pushOperand(IC_IMM);
if (ParsingInlineAsm) if (ParsingInlineAsm)
Info = IDInfo; Info = IDInfo;
break; break;
} }
if (HasSymbol) return false;
ErrMsg = "cannot use more than one symbol in memory operand";
return HasSymbol;
} }
bool onInteger(int64_t TmpInt, StringRef &ErrMsg) { bool onInteger(int64_t TmpInt, StringRef &ErrMsg) {
IntelExprState CurrState = State; IntelExprState CurrState = State;
switch (State) { switch (State) {
default: default:
State = IES_ERROR; State = IES_ERROR;
break; break;
case IES_PLUS: case IES_PLUS:
▲ Show 20 Lines • Show All 157 Lines • ▼ Show 20 Lines void onRParen() {
case IES_INTEGER: case IES_INTEGER:
case IES_REGISTER: case IES_REGISTER:
case IES_RPAREN: case IES_RPAREN:
State = IES_RPAREN; State = IES_RPAREN;
IC.pushOperator(IC_RPAREN); IC.pushOperator(IC_RPAREN);
break; break;
} }
} }
bool onOffset(const MCExpr *Val, StringRef ID, StringRef &ErrMsg) {
PrevState = State;
switch (State) {
default:
ErrMsg = "unexpected offset operator expression";
return true;
case IES_PLUS:
case IES_INIT:
case IES_LBRAC:
if (setSymRef(Val, ID, ErrMsg))
return true;
OffsetOperator = true;
State = IES_OFFSET;
// As we cannot yet resolve the actual value (offset), we retain
// the requested semantics by pushing a '0' to the operands stack
IC.pushOperand(IC_IMM);
break;
}
return false;
}
}; };
bool Error(SMLoc L, const Twine &Msg, SMRange Range = None, bool Error(SMLoc L, const Twine &Msg, SMRange Range = None,
bool MatchingInlineAsm = false) { bool MatchingInlineAsm = false) {
MCAsmParser &Parser = getParser(); MCAsmParser &Parser = getParser();
if (MatchingInlineAsm) { if (MatchingInlineAsm) {
if (!getLexer().isAtStartOfStatement()) if (!getLexer().isAtStartOfStatement())
Parser.eatToEndOfStatement(); Parser.eatToEndOfStatement();
Show All 15 Linesprivate:
AddDefaultSrcDestOperands(OperandVector &Operands, AddDefaultSrcDestOperands(OperandVector &Operands,
std::unique_ptr<llvm::MCParsedAsmOperand> &&Src, std::unique_ptr<llvm::MCParsedAsmOperand> &&Src,
std::unique_ptr<llvm::MCParsedAsmOperand> &&Dst); std::unique_ptr<llvm::MCParsedAsmOperand> &&Dst);
bool VerifyAndAdjustOperands(OperandVector &OrigOperands, bool VerifyAndAdjustOperands(OperandVector &OrigOperands,
OperandVector &FinalOperands); OperandVector &FinalOperands);
std::unique_ptr<X86Operand> ParseOperand(); std::unique_ptr<X86Operand> ParseOperand();
std::unique_ptr<X86Operand> ParseATTOperand(); std::unique_ptr<X86Operand> ParseATTOperand();
std::unique_ptr<X86Operand> ParseIntelOperand(); std::unique_ptr<X86Operand> ParseIntelOperand();
std::unique_ptr<X86Operand> ParseIntelOffsetOfOperator(); bool ParseIntelOffsetOperator(const MCExpr *&Val, StringRef &ID, SMLoc &End);
bool ParseIntelDotOperator(IntelExprStateMachine &SM, SMLoc &End); bool ParseIntelDotOperator(IntelExprStateMachine &SM, SMLoc &End);
unsigned IdentifyIntelInlineAsmOperator(StringRef Name); unsigned IdentifyIntelInlineAsmOperator(StringRef Name);
unsigned ParseIntelInlineAsmOperator(unsigned OpKind); unsigned ParseIntelInlineAsmOperator(unsigned OpKind);
std::unique_ptr<X86Operand> ParseRoundingModeOp(SMLoc Start); std::unique_ptr<X86Operand> ParseRoundingModeOp(SMLoc Start);
bool ParseIntelNamedOperator(StringRef Name, IntelExprStateMachine &SM); bool ParseIntelNamedOperator(StringRef Name, IntelExprStateMachine &SM,
bool &ParseError, SMLoc &End);
void RewriteIntelExpression(IntelExprStateMachine &SM, SMLoc Start, void RewriteIntelExpression(IntelExprStateMachine &SM, SMLoc Start,
SMLoc End); SMLoc End);
bool ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End); bool ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End);
bool ParseIntelInlineAsmIdentifier(const MCExpr *&Val, StringRef &Identifier, bool ParseIntelInlineAsmIdentifier(const MCExpr *&Val, StringRef &Identifier,
InlineAsmIdentifierInfo &Info, InlineAsmIdentifierInfo &Info,
bool IsUnevaluatedOperand, SMLoc &End); bool IsUnevaluatedOperand, SMLoc &End,
bool IsParsingOffsetOperator = false);
std::unique_ptr<X86Operand> ParseMemOperand(unsigned SegReg, std::unique_ptr<X86Operand> ParseMemOperand(unsigned SegReg,
const MCExpr *&Disp, const MCExpr *&Disp,
const SMLoc &StartLoc, const SMLoc &StartLoc,
SMLoc &EndLoc); SMLoc &EndLoc);
bool ParseIntelMemoryOperandSize(unsigned &Size); bool ParseIntelMemoryOperandSize(unsigned &Size);
std::unique_ptr<X86Operand> std::unique_ptr<X86Operand>
▲ Show 20 Lines • Show All 542 Lines • ▼ Show 20 Lines return X86Operand::CreateMem(getPointerWidth(), SegReg, Disp, BaseReg,
IndexReg, Scale, Start, End, Size, Identifier, IndexReg, Scale, Start, End, Size, Identifier,
Decl, FrontendSize); Decl, FrontendSize);
} }
} }
// Some binary bitwise operators have a named synonymous // Some binary bitwise operators have a named synonymous
// Query a candidate string for being such a named operator // Query a candidate string for being such a named operator
// and if so - invoke the appropriate handler // and if so - invoke the appropriate handler
bool X86AsmParser::ParseIntelNamedOperator(StringRef Name, IntelExprStateMachine &SM) { bool X86AsmParser::ParseIntelNamedOperator(StringRef Name,
IntelExprStateMachine &SM,
bool &ParseError, SMLoc &End) {
// A named operator should be either lower or upper case, but not a mix // A named operator should be either lower or upper case, but not a mix
if (Name.compare(Name.lower()) && Name.compare(Name.upper())) if (Name.compare(Name.lower()) && Name.compare(Name.upper()))
return false; return false;
if (Name.equals_lower("not")) if (Name.equals_lower("not")) {
SM.onNot(); SM.onNot();
else if (Name.equals_lower("or")) } else if (Name.equals_lower("or")) {
SM.onOr(); SM.onOr();
else if (Name.equals_lower("shl")) } else if (Name.equals_lower("shl")) {
SM.onLShift(); SM.onLShift();
else if (Name.equals_lower("shr")) } else if (Name.equals_lower("shr")) {
SM.onRShift(); SM.onRShift();
else if (Name.equals_lower("xor")) } else if (Name.equals_lower("xor")) {
SM.onXor(); SM.onXor();
else if (Name.equals_lower("and")) } else if (Name.equals_lower("and")) {
SM.onAnd(); SM.onAnd();
else if (Name.equals_lower("mod")) } else if (Name.equals_lower("mod")) {
SM.onMod(); SM.onMod();
else } else if (Name.equals_lower("offset")) {
const MCExpr *Val = nullptr;
StringRef ID;
if ((ParseError = ParseIntelOffsetOperator(Val, ID, End)))
return true;
StringRef ErrMsg;
if ((ParseError = SM.onOffset(Val, ID, ErrMsg)))
return Error(SMLoc::getFromPointer(Name.data()), ErrMsg);
} else {
return false; return false;
}
if (!Name.equals_lower("offset"))
End = consumeToken();
return true; return true;
} }
bool X86AsmParser::ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End) { bool X86AsmParser::ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End) {
MCAsmParser &Parser = getParser(); MCAsmParser &Parser = getParser();
const AsmToken &Tok = Parser.getTok(); const AsmToken &Tok = Parser.getTok();
StringRef ErrMsg; StringRef ErrMsg;
Show All 26 Lines case AsmToken::Identifier: {
// Register // Register
unsigned Reg; unsigned Reg;
if (Tok.is(AsmToken::Identifier) && !ParseRegister(Reg, IdentLoc, End)) { if (Tok.is(AsmToken::Identifier) && !ParseRegister(Reg, IdentLoc, End)) {
if (SM.onRegister(Reg, ErrMsg)) if (SM.onRegister(Reg, ErrMsg))
return Error(Tok.getLoc(), ErrMsg); return Error(Tok.getLoc(), ErrMsg);
break; break;
} }
// Operator synonymous ("not", "or" etc.) // Operator synonymous ("not", "or" etc.)
if ((UpdateLocLex = ParseIntelNamedOperator(Identifier, SM))) bool ParseError = false;
if (ParseIntelNamedOperator(Identifier, SM, ParseError, End)) {
if (ParseError)
return true;
break; break;
}
// Symbol reference, when parsing assembly content // Symbol reference, when parsing assembly content
InlineAsmIdentifierInfo Info; InlineAsmIdentifierInfo Info;
const MCExpr *Val; const MCExpr *Val;
if (!isParsingInlineAsm()) { if (!isParsingInlineAsm()) {
if (getParser().parsePrimaryExpr(Val, End)) { if (getParser().parsePrimaryExpr(Val, End)) {
return Error(Tok.getLoc(), "Unexpected identifier!"); return Error(Tok.getLoc(), "Unexpected identifier!");
} else if (SM.onIdentifierExpr(Val, Identifier, Info, false, ErrMsg)) { } else if (SM.onIdentifierExpr(Val, Identifier, Info, false, ErrMsg)) {
return Error(IdentLoc, ErrMsg); return Error(IdentLoc, ErrMsg);
} else } else
break; break;
} }
// MS InlineAsm operators (TYPE/LENGTH/SIZE) // MS InlineAsm operators (TYPE/LENGTH/SIZE)
if (unsigned OpKind = IdentifyIntelInlineAsmOperator(Identifier)) { if (unsigned OpKind = IdentifyIntelInlineAsmOperator(Identifier)) {
if (OpKind == IOK_OFFSET)
return Error(IdentLoc, "Dealing OFFSET operator as part of"
"a compound immediate expression is yet to be supported");
if (int64_t Val = ParseIntelInlineAsmOperator(OpKind)) { if (int64_t Val = ParseIntelInlineAsmOperator(OpKind)) {
if (SM.onInteger(Val, ErrMsg)) if (SM.onInteger(Val, ErrMsg))
return Error(IdentLoc, ErrMsg); return Error(IdentLoc, ErrMsg);
} else } else
return true; return true;
break; break;
} }
// MS Dot Operator expression // MS Dot Operator expression
▲ Show 20 Lines • Show All 85 Lines • ▼ Show 20 Linesbool X86AsmParser::ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End) {
return false; return false;
} }
void X86AsmParser::RewriteIntelExpression(IntelExprStateMachine &SM, void X86AsmParser::RewriteIntelExpression(IntelExprStateMachine &SM,
SMLoc Start, SMLoc End) { SMLoc Start, SMLoc End) {
SMLoc Loc = Start; SMLoc Loc = Start;
unsigned ExprLen = End.getPointer() - Start.getPointer(); unsigned ExprLen = End.getPointer() - Start.getPointer();
// Skip everything before a symbol displacement (if we have one) // Skip everything before a symbol displacement (if we have one)
if (SM.getSym()) { if (SM.getSym() && !SM.isOffsetOperator()) {
StringRef SymName = SM.getSymName(); StringRef SymName = SM.getSymName();
if (unsigned Len = SymName.data() - Start.getPointer()) if (unsigned Len = SymName.data() - Start.getPointer())
InstInfo->AsmRewrites->emplace_back(AOK_Skip, Start, Len); InstInfo->AsmRewrites->emplace_back(AOK_Skip, Start, Len);
Loc = SMLoc::getFromPointer(SymName.data() + SymName.size()); Loc = SMLoc::getFromPointer(SymName.data() + SymName.size());
ExprLen = End.getPointer() - (SymName.data() + SymName.size()); ExprLen = End.getPointer() - (SymName.data() + SymName.size());
// If we have only a symbol than there's no need for complex rewrite, // If we have only a symbol than there's no need for complex rewrite,
// simply skip everything after it // simply skip everything after it
if (!(SM.getBaseReg() || SM.getIndexReg() || SM.getImm())) { if (!(SM.getBaseReg() || SM.getIndexReg() || SM.getImm())) {
if (ExprLen) if (ExprLen)
InstInfo->AsmRewrites->emplace_back(AOK_Skip, Loc, ExprLen); InstInfo->AsmRewrites->emplace_back(AOK_Skip, Loc, ExprLen);
return; return;
} }
} }
// Build an Intel Expression rewrite // Build an Intel Expression rewrite
StringRef BaseRegStr; StringRef BaseRegStr;
StringRef IndexRegStr; StringRef IndexRegStr;
StringRef OffsetNameStr;
if (SM.getBaseReg()) if (SM.getBaseReg())
BaseRegStr = X86IntelInstPrinter::getRegisterName(SM.getBaseReg()); BaseRegStr = X86IntelInstPrinter::getRegisterName(SM.getBaseReg());
if (SM.getIndexReg()) if (SM.getIndexReg())
IndexRegStr = X86IntelInstPrinter::getRegisterName(SM.getIndexReg()); IndexRegStr = X86IntelInstPrinter::getRegisterName(SM.getIndexReg());
if (SM.isOffsetOperator())
OffsetNameStr = SM.getSymName();
// Emit it // Emit it
IntelExpr Expr(BaseRegStr, IndexRegStr, SM.getScale(), SM.getImm(), SM.isMemExpr()); IntelExpr Expr(BaseRegStr, IndexRegStr, SM.getScale(), OffsetNameStr,
SM.getImm(), SM.isMemExpr());
InstInfo->AsmRewrites->emplace_back(Loc, ExprLen, Expr); InstInfo->AsmRewrites->emplace_back(Loc, ExprLen, Expr);
} }
// Inline assembly may use variable names with namespace alias qualifiers. // Inline assembly may use variable names with namespace alias qualifiers.
bool X86AsmParser::ParseIntelInlineAsmIdentifier(const MCExpr *&Val, bool
X86AsmParser::ParseIntelInlineAsmIdentifier(const MCExpr *&Val,
StringRef &Identifier, StringRef &Identifier,
InlineAsmIdentifierInfo &Info, InlineAsmIdentifierInfo &Info,
bool IsUnevaluatedOperand, bool IsUnevaluatedOperand,
SMLoc &End) { SMLoc &End,
bool IsParsingOffsetOperator) {
MCAsmParser &Parser = getParser(); MCAsmParser &Parser = getParser();
assert(isParsingInlineAsm() && "Expected to be parsing inline assembly."); assert(isParsingInlineAsm() && "Expected to be parsing inline assembly.");
Val = nullptr; Val = nullptr;
StringRef LineBuf(Identifier.data()); StringRef LineBuf(Identifier.data());
SemaCallback->LookupInlineAsmIdentifier(LineBuf, Info, IsUnevaluatedOperand); SemaCallback->LookupInlineAsmIdentifier(LineBuf, Info, IsUnevaluatedOperand);
const AsmToken &Tok = Parser.getTok(); const AsmToken &Tok = Parser.getTok();
Show All 16 LinesX86AsmParser::ParseIntelInlineAsmIdentifier(const MCExpr *&Val,
// If the identifier lookup was unsuccessful, assume that we are dealing with // If the identifier lookup was unsuccessful, assume that we are dealing with
// a label. // a label.
if (Info.isKind(InlineAsmIdentifierInfo::IK_Invalid)) { if (Info.isKind(InlineAsmIdentifierInfo::IK_Invalid)) {
StringRef InternalName = StringRef InternalName =
SemaCallback->LookupInlineAsmLabel(Identifier, getSourceManager(), SemaCallback->LookupInlineAsmLabel(Identifier, getSourceManager(),
Loc, false); Loc, false);
assert(InternalName.size() && "We should have an internal name here."); assert(InternalName.size() && "We should have an internal name here.");
// Push a rewrite for replacing the identifier name with the internal name. // Push a rewrite for replacing the identifier name with the internal name,
// unless we are parsing the operand of an offset operator
if (!IsParsingOffsetOperator)
InstInfo->AsmRewrites->emplace_back(AOK_Label, Loc, Identifier.size(), InstInfo->AsmRewrites->emplace_back(AOK_Label, Loc, Identifier.size(),
InternalName); InternalName);
else
Identifier = InternalName;
} else if (Info.isKind(InlineAsmIdentifierInfo::IK_EnumVal)) } else if (Info.isKind(InlineAsmIdentifierInfo::IK_EnumVal))
return false; return false;
// Create the symbol reference. // Create the symbol reference.
MCSymbol *Sym = getContext().getOrCreateSymbol(Identifier); MCSymbol *Sym = getContext().getOrCreateSymbol(Identifier);
MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None; MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None;
Val = MCSymbolRefExpr::create(Sym, Variant, getParser().getContext()); Val = MCSymbolRefExpr::create(Sym, Variant, getParser().getContext());
return false; return false;
} }
▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Linesbool X86AsmParser::ParseIntelDotOperator(IntelExprStateMachine &SM, SMLoc &End) {
End = SMLoc::getFromPointer(DotDispStr.data()); End = SMLoc::getFromPointer(DotDispStr.data());
const char *DotExprEndLoc = DotDispStr.data() + DotDispStr.size(); const char *DotExprEndLoc = DotDispStr.data() + DotDispStr.size();
while (Tok.getLoc().getPointer() < DotExprEndLoc) while (Tok.getLoc().getPointer() < DotExprEndLoc)
Lex(); Lex();
SM.addImm(Offset); SM.addImm(Offset);
return false; return false;
} }
/// Parse the 'offset' operator. This operator is used to specify the /// Parse the 'offset' operator.
/// location rather then the content of a variable. /// This operator is used to specify the location of a given operand
std::unique_ptr<X86Operand> X86AsmParser::ParseIntelOffsetOfOperator() { bool X86AsmParser::ParseIntelOffsetOperator(const MCExpr *&Val, StringRef &ID,
MCAsmParser &Parser = getParser(); SMLoc &End) {
const AsmToken &Tok = Parser.getTok(); // Eat offset, mark start of identifier.
SMLoc OffsetOfLoc = Tok.getLoc(); SMLoc Start = Lex().getLoc();
Parser.Lex(); // Eat offset. ID = getTok().getString();
const MCExpr *Val;
InlineAsmIdentifierInfo Info; InlineAsmIdentifierInfo Info;
SMLoc Start = Tok.getLoc(), End; if (!isParsingInlineAsm()) {
StringRef Identifier = Tok.getString(); if ((getTok().isNot(AsmToken::Identifier) &&
if (ParseIntelInlineAsmIdentifier(Val, Identifier, Info, getTok().isNot(AsmToken::String)) ||
/*Unevaluated=*/false, End)) getParser().parsePrimaryExpr(Val, End))
return nullptr; return Error(Start, "unexpected token!");
} else if (ParseIntelInlineAsmIdentifier(Val, ID, Info, false, End, true)) {
void *Decl = nullptr; return Error(Start, "unable to lookup expression");
// FIXME: MS evaluates "offset <Constant>" to the underlying integral } else if (Info.isKind(InlineAsmIdentifierInfo::IK_EnumVal)) {
if (Info.isKind(InlineAsmIdentifierInfo::IK_EnumVal)) return Error(Start, "offset operator cannot yet handle constants");
return ErrorOperand(Start, "offset operator cannot yet handle constants"); } else if (Info.isKind(InlineAsmIdentifierInfo::IK_Var) &&
else if (Info.isKind(InlineAsmIdentifierInfo::IK_Var)) !Info.Var.IsGlobalLV) {
Decl = Info.Var.Decl; return Error(SMLoc::getFromPointer(ID.data()), "illegal operand for "
// Don't emit the offset operator. "offset operator");
InstInfo->AsmRewrites->emplace_back(AOK_Skip, OffsetOfLoc, 7); }
return false;
// The offset operator will have an 'r' constraint, thus we need to create
// register operand to ensure proper matching. Just pick a GPR based on
// the size of a pointer.
bool Parse32 = is32BitMode() || Code16GCC;
unsigned RegNo = is64BitMode() ? X86::RBX : (Parse32 ? X86::EBX : X86::BX);
return X86Operand::CreateReg(RegNo, Start, End, /*GetAddress=*/true,
OffsetOfLoc, Identifier, Decl);
} }
// Query a candidate string for being an Intel assembly operator // Query a candidate string for being an Intel assembly operator
// Report back its kind, or IOK_INVALID if does not evaluated as a known one // Report back its kind, or IOK_INVALID if does not evaluated as a known one
unsigned X86AsmParser::IdentifyIntelInlineAsmOperator(StringRef Name) { unsigned X86AsmParser::IdentifyIntelInlineAsmOperator(StringRef Name) {
return StringSwitch<unsigned>(Name) return StringSwitch<unsigned>(Name)
.Cases("TYPE","type",IOK_TYPE) .Cases("TYPE","type",IOK_TYPE)
.Cases("SIZE","size",IOK_SIZE) .Cases("SIZE","size",IOK_SIZE)
.Cases("LENGTH","length",IOK_LENGTH) .Cases("LENGTH","length",IOK_LENGTH)
.Cases("OFFSET","offset",IOK_OFFSET)
.Default(IOK_INVALID); .Default(IOK_INVALID);
} }
/// Parse the 'LENGTH', 'TYPE' and 'SIZE' operators. The LENGTH operator /// Parse the 'LENGTH', 'TYPE' and 'SIZE' operators. The LENGTH operator
/// returns the number of elements in an array. It returns the value 1 for /// returns the number of elements in an array. It returns the value 1 for
/// non-array variables. The SIZE operator returns the size of a C or C++ /// non-array variables. The SIZE operator returns the size of a C or C++
/// variable. A variable's size is the product of its LENGTH and TYPE. The /// variable. A variable's size is the product of its LENGTH and TYPE. The
/// TYPE operator returns the size of a C or C++ type or variable. If the /// TYPE operator returns the size of a C or C++ type or variable. If the
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Linesbool X86AsmParser::ParseIntelMemoryOperandSize(unsigned &Size) {
return false; return false;
} }
std::unique_ptr<X86Operand> X86AsmParser::ParseIntelOperand() { std::unique_ptr<X86Operand> X86AsmParser::ParseIntelOperand() {
MCAsmParser &Parser = getParser(); MCAsmParser &Parser = getParser();
const AsmToken &Tok = Parser.getTok(); const AsmToken &Tok = Parser.getTok();
SMLoc Start, End; SMLoc Start, End;
// FIXME: Offset operator
// Should be handled as part of immediate expression, as other operators
// Currently, only supported as a stand-alone operand
if (isParsingInlineAsm())
if (IdentifyIntelInlineAsmOperator(Tok.getString()) == IOK_OFFSET)
return ParseIntelOffsetOfOperator();
// Parse optional Size directive. // Parse optional Size directive.
unsigned Size; unsigned Size;
if (ParseIntelMemoryOperandSize(Size)) if (ParseIntelMemoryOperandSize(Size))
return nullptr; return nullptr;
bool PtrInOperand = bool(Size); bool PtrInOperand = bool(Size);
Start = Tok.getLoc(); Start = Tok.getLoc();
▲ Show 20 Lines • Show All 1,638 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/offset-operator.ll

  • This file was added.
; RUN: llc -mtriple=x86_64-unknown-linux-gnu -x86-asm-syntax=intel -relocation-model=static < %s | FileCheck %s
; Test we are emitting the 'offset' operator upon an immediate reference of a label:
; The emitted 'att-equivalent' of this one is "movl $.L.str, %eax"
@.str = private unnamed_addr constant [1 x i8] zeroinitializer, align 1
define i8* @test_offset_operator() {
; CHECK-LABEL: test_offset_operator:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: mov eax, offset .L.str
; CHECK-NEXT: ret
entry:
ret i8* getelementptr inbounds ([1 x i8], [1 x i8]* @.str, i64 0, i64 0)
}

llvm/test/MC/X86/pr32530.s

  • This file was added.
// RUN: llvm-mc -triple x86_64-unknown-unknown -x86-asm-syntax=intel %s | FileCheck %s
.text
// CHECK: movq $msg, %rsi
// CHECK: movq $msg+314159, %rax
// CHECK: movq $msg-89793, msg-6535(%rax,%rbx,2)
mov rsi, offset msg
mov rax, offset "msg" + 314159
mov qword ptr [rax + 2*rbx + offset msg - 6535], offset msg - 89793
.data
msg:
.ascii "Hello, world!\n"