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Differential D71436

[X86][AsmParser] re-introduce 'offset' operator
ClosedPublic

Authored by epastor on Dec 12 2019, 2:21 PM.

Details

Reviewers
rnk
Commits
rG4a7aa252a32a: [X86][AsmParser] re-introduce 'offset' operator
Summary

Amend MS offset operator implementation, to more closely fit with its MS counterpart:

  1. InlineAsm: evaluate non-local source entities to their (address) location
  2. Provide a mean with which one may acquire the address of an assembly label via MS syntax, rather than yielding a memory reference (i.e. "offset asm_label" and "$asm_label" should be synonymous
  3. address PR32530

Based on http://llvm.org/D37461

Fix broken test where the break appears unrelated.

  • Set up appropriate memory-input rewrites for variable references.
  • Intel-dialect assembly printing now correctly handles addresses by adding "offset".
  • Pass offsets as immediate operands (using "r" constraint for offsets of locals).

Diff Detail

Event Timeline

epastor created this revision.Dec 12 2019, 2:21 PM
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epastor added a comment.EditedDec 12 2019, 7:29 PM

Note: this currently breaks several test cases, at least some of which are valid.

Example: (minimized from ms-inline-asm-redundant-clobber.ll)
call void asm inteldialect "cmpxchg8b $0", "=*m"(i32* @Bar)
previously emitted
cmpxchg8b Bar(%rip)
and now (after the change to X86AsmPrinter.cpp) emits

<inline asm>:2:29: error: unknown token in expression
        cmpxchg8b [rip + offset Bar]
                                   ^

I'm not sure how to fix this... but among other problems, it seems we've ended up emitting offset even when emitting AT&T-syntax assembly. (The same error occurs if we pass -x86-asm-syntax=intel, too.) This appears to affect all indirect memory operands.

EDIT: This was a bad interpretation; the issue was that the operand was expanded into an inteldialect Intel expression, and the offset was immediately followed by ']'. Making offset legal before ']' and ')' fixes that problem.

epastor updated this revision to Diff 233778.Dec 13 2019, 4:46 AM
  • Allow offsets at the end of parenthesized expressions
epastor added a reviewer: rnk.Dec 13 2019, 5:14 AM

Remaining test failures include:

call void asm sideeffect inteldialect "lea edi, dword ptr $0", "*m,~{edi},~{dirflag},~{fpsr},~{flags}"([2 x i32]* @results) nounwind
previously expanded as
lea edi, dword ptr [_results]
and now expands as
lea edi, dword ptr [offset _results]
This may be correct.

In C & C++,
__asm mov [eax], offset var
is now ambiguous, since "offset var" is not aliased directly to a pointer-sized register. I think this is technically correct, but I don't think I should make that decision without input.

epastor updated this revision to Diff 233786.Dec 13 2019, 5:24 AM
  • Fix tests expecting use of 'r' constraints for offset operands
Herald added a project: Restricted Project. · View Herald TranscriptDec 13 2019, 5:24 AM
Herald added a subscriber: cfe-commits. · View Herald Transcript
epastor updated this revision to Diff 233806.Dec 13 2019, 7:58 AM
  • Fix Intel named operator parsing
merge_guards_bot added a subscriber: merge_guards_bot.Dec 13 2019, 8:15 AM

Unit tests: fail. 60824 tests passed, 4 failed and 726 were skipped.

failed: Clang.CodeGen/ms-inline-asm-64.c
failed: Clang.CodeGen/ms-inline-asm.c
failed: Clang.SemaTemplate/instantiation-depth-default.cpp
failed: LLVM.CodeGen/X86/ms-inline-asm.ll

clang-format: pass.

Build artifacts: console-log.txt, CMakeCache.txt, test-results.xml, diff.json

Harbormaster failed remote builds in B42464: Diff 233806!Dec 13 2019, 8:15 AM
epastor updated this revision to Diff 233813.Dec 13 2019, 8:29 AM
  • Respect correct usage of offset.
  • Don't assume implicit sizing on offset.
  • Check that offset works in compound expressions.
merge_guards_bot added a comment.Dec 13 2019, 8:42 AM

Unit tests: pass. 60854 tests passed, 0 failed and 726 were skipped.

clang-format: fail. Please format your changes with clang-format by running git-clang-format HEAD^ or apply this patch.

Build artifacts: console-log.txt, CMakeCache.txt, clang-format.patch, test-results.xml, diff.json

Harbormaster completed remote builds in B42467: Diff 233813.Dec 13 2019, 8:42 AM
epastor updated this revision to Diff 234067.Dec 16 2019, 8:03 AM
  • Apply formatting fixes where reasonable
merge_guards_bot added a comment.Dec 16 2019, 8:21 AM

Unit tests: pass. 60854 tests passed, 0 failed and 726 were skipped.

clang-format: fail. Please format your changes with clang-format by running git-clang-format HEAD^ or apply this patch.

Build artifacts: diff.json, clang-format.patch, CMakeCache.txt, console-log.txt, test-results.xml

Harbormaster completed remote builds in B42561: Diff 234067.Dec 16 2019, 8:25 AM
rnk added a comment.Dec 16 2019, 4:13 PM

Thanks! I made some comments. This code is convoluted. I don't think I can reason through all the edge cases, but this seems like an improvement. I'd suggest adding the recommended tests and any other corner case inputs you can think of, and after another round of review we can land it.

clang/test/CodeGen/ms-inline-asm-64.c
18

I guess this has the same semantics as it did before.

llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h
74

These explicit empty StringRef initializations seem unnecessary, I'd suggest removing them.

99–100

nit, pack the bool after the unsigned for a smaller struct. Hey, we make a vector of these. :)

llvm/lib/MC/MCParser/AsmParser.cpp
5938–5943

Maybe this would be simpler with

auto rewrite_it = find_if(it, AsmStrRewrites.end(), [&](const AsmRewrite &OffsetAR) {
  // ... conditions below
});
llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
1481

While this doesn't trigger warnings, it seems like it would be simpler to do the assignment as its own statement and then if (ParseErrror) return true;

I see that the local code style uses this pattern already, but I'm not sure that's a good reason to promote it and keep using it.

1484

ditto

1823

Please test this corner case, I imagine it looks like:

mov eax, offset 3
1827

Please add a test for this corner case, I'm curious to see if the error reporting really works.

pengfei added a subscriber: pengfei.Dec 16 2019, 4:50 PM
epastor updated this revision to Diff 234371.Dec 17 2019, 12:59 PM
epastor marked 6 inline comments as done.
  • Address refactoring comments
epastor added a comment.Dec 17 2019, 12:59 PM

Thanks for feedback!

clang/test/CodeGen/ms-inline-asm-64.c
18

It does; this previously resolved to a "qword ptr" mov automatically, since $0 unpacked as a (forced) 64-bit register name. Now we need to specify the size of the move, since the operand is an immediate rather than a register.

llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
1823

Interesting. This corner case didn't trigger in that scenario; we get an "expected identifier" error message with good source location, followed by another error "use of undeclared label '3'" in debug builds... and in release builds, we instead get a crash. On tracing the crash, it's a AsmStrRewrite applying to a SMLoc not coming from the same string...

As near as I can tell, the issue is that we end up trying to parse "3" as a not-yet-declared label, as such expand it to __MSASMLABEL_.${:uid}__3, and then end up in a bad state because the operand rewrite is applying to the expanded symbol... which isn't in the same AsmString. If you use an actual undeclared label, you hit the same crash in release builds.

This is going to take some work; I'll get back to it in a day or two.

1827

This error reporting doesn't work, in fact. We instead get "cannot take the address of an rvalue of type 'int'", with bad source location. Will investigate why we end up there.

merge_guards_bot added a comment.Dec 17 2019, 1:13 PM

Unit tests: pass. 60854 tests passed, 0 failed and 726 were skipped.

clang-tidy: fail. Please fix clang-tidy findings.

clang-format: fail. Please format your changes with clang-format by running git-clang-format HEAD^ or applying this patch.

Build artifacts: diff.json, clang-tidy.txt, clang-format.patch, CMakeCache.txt, console-log.txt, test-results.xml

Harbormaster failed remote builds in B42677: Diff 234371!Dec 17 2019, 1:15 PM
epastor updated this revision to Diff 234566.Dec 18 2019, 10:00 AM
epastor marked 2 inline comments as done.

Fix issues around enum values and labels

  • Only rewrite variables as offset operands; fixes crash due to conflicting rewrites for labels
  • Recognize inline assembly references to enum values
llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
1823

Fixed; we now get the same errors in this scenario as we do in the current LLVM trunk, reporting "expected identifier" and "use of undeclared label '3'".

On the other hand, I'm still working on finding a scenario that DOES trigger this corner case.

1827

Turns out Sema wasn't successfully recognizing inline-assembly references to enum values, so we were processing them through as labels, and only recognizing the problem late in processing. Fixed now, with accurate error reporting; test added.

epastor updated this revision to Diff 234567.Dec 18 2019, 10:04 AM
  • Removing accidental artifacts of local testing...
merge_guards_bot added a comment.Dec 18 2019, 10:15 AM

Unit tests: unknown.

clang-tidy: fail. Please fix clang-tidy findings.

clang-format: fail. Please format your changes with clang-format by running git-clang-format HEAD^ or applying this patch.

Build artifacts: diff.json, clang-tidy.txt, clang-format.patch, CMakeCache.txt, console-log.txt

Harbormaster failed remote builds in B42748: Diff 234566!Dec 18 2019, 10:16 AM
merge_guards_bot added a comment.Dec 18 2019, 10:16 AM

Unit tests: pass. 60854 tests passed, 0 failed and 726 were skipped.

clang-tidy: fail. Please fix clang-tidy findings.

clang-format: fail. Please format your changes with clang-format by running git-clang-format HEAD^ or applying this patch.

Build artifacts: diff.json, clang-tidy.txt, clang-format.patch, CMakeCache.txt, console-log.txt, test-results.xml

Harbormaster failed remote builds in B42749: Diff 234567!Dec 18 2019, 10:19 AM
rnk accepted this revision.Dec 28 2019, 1:04 PM

lgtm, thanks!

llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
1823

I see. Well, it sounds like it was a useful test. :)

This revision is now accepted and ready to land.Dec 28 2019, 1:04 PM
epastor updated this revision to Diff 235617.Dec 30 2019, 10:06 AM

Rebase on top of HEAD

  • Add compatibility with dc5b614fa9a1 (which changed handling for call operands in x86 assembly)
  • Remove another artifact of local testing
epastor updated this revision to Diff 235619.Dec 30 2019, 10:18 AM
epastor marked 5 inline comments as done.
  • Fix a few final issues.
    • Pack the AsmRewrite struct more optimally.
    • Only check if we can fuse rewrites with ones we haven't already reached!
llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
1823

Very useful indeed!

merge_guards_bot added a comment.Dec 30 2019, 10:24 AM

Unit tests: pass. 61144 tests passed, 0 failed and 728 were skipped.

clang-tidy: fail. Please fix clang-tidy findings.

clang-format: fail. Please format your changes with clang-format by running git-clang-format HEAD^ or applying this patch.

Build artifacts: diff.json, clang-tidy.txt, clang-format.patch, CMakeCache.txt, console-log.txt, test-results.xml

Harbormaster failed remote builds in B43056: Diff 235617!Dec 30 2019, 10:24 AM
merge_guards_bot added a comment.Dec 30 2019, 10:26 AM

Unit tests: unknown.

clang-tidy: fail. Please fix clang-tidy findings.

clang-format: fail. Please format your changes with clang-format by running git-clang-format HEAD^ or applying this patch.

Build artifacts: diff.json, clang-tidy.txt, clang-format.patch, CMakeCache.txt, console-log.txt

epastor updated this revision to Diff 235620.Dec 30 2019, 10:30 AM
  • The three-argument version of find_if is std::find_if, and the qualification is required.
Harbormaster failed remote builds in B43058: Diff 235619!Dec 30 2019, 10:33 AM
merge_guards_bot added a comment.Dec 30 2019, 10:43 AM

Unit tests: pass. 61144 tests passed, 0 failed and 728 were skipped.

clang-tidy: fail. Please fix clang-tidy findings.

clang-format: fail. Please format your changes with clang-format by running git-clang-format HEAD^ or applying this patch.

Build artifacts: diff.json, clang-tidy.txt, clang-format.patch, CMakeCache.txt, console-log.txt, test-results.xml

Harbormaster failed remote builds in B43059: Diff 235620!Dec 30 2019, 10:43 AM
Closed by commit rG4a7aa252a32a: [X86][AsmParser] re-introduce 'offset' operator (authored by epastor). · Explain WhyDec 30 2019, 11:47 AM
This revision was automatically updated to reflect the committed changes.
thakis mentioned this in D37461: [X86][AsmParser] re-introduce 'offset' operator.Sep 23 2021, 12:23 PM
alvinhochun mentioned this in D150047: [X86][CodeGen] Do not add `offset` for memory reference using symbol.May 6 2023, 11:39 AM
alvinhochun mentioned this in rG6b996282cee3: [X86][CodeGen] Do not add `offset` for memory reference using symbol.May 8 2023, 9:08 AM

Revision Contents

PathSize
clang/
lib/
Sema/
7 lines
test/
CodeGen/
4 lines
12 lines
2 lines
Parser/
5 lines
llvm/
include/
llvm/
MC/
MCParser/
8 lines
47 lines
lib/
MC/
MCParser/
52 lines
Target/
X86/
AsmParser/
216 lines
20 lines
10 lines
test/
CodeGen/
X86/
2 lines
15 lines
MC/
X86/
13 lines

Diff 235628

clang/lib/Sema/SemaStmtAsm.cpp

Show First 20 Lines • Show All 701 Lines • ▼ Show 20 Lines
void Sema::FillInlineAsmIdentifierInfo(Expr *Res, void Sema::FillInlineAsmIdentifierInfo(Expr *Res,
llvm::InlineAsmIdentifierInfo &Info) { llvm::InlineAsmIdentifierInfo &Info) {
QualType T = Res->getType(); QualType T = Res->getType();
Expr::EvalResult Eval; Expr::EvalResult Eval;
if (T->isFunctionType() || T->isDependentType()) if (T->isFunctionType() || T->isDependentType())
return Info.setLabel(Res); return Info.setLabel(Res);
if (Res->isRValue()) { if (Res->isRValue()) {
if (isa<clang::EnumType>(T) && Res->EvaluateAsRValue(Eval, Context)) bool IsEnum = isa<clang::EnumType>(T);
if (DeclRefExpr *DRE = dyn_cast<clang::DeclRefExpr>(Res))
if (DRE->getDecl()->getKind() == Decl::EnumConstant)
IsEnum = true;
if (IsEnum && Res->EvaluateAsRValue(Eval, Context))
return Info.setEnum(Eval.Val.getInt().getSExtValue()); return Info.setEnum(Eval.Val.getInt().getSExtValue());
return Info.setLabel(Res); return Info.setLabel(Res);
} }
unsigned Size = Context.getTypeSizeInChars(T).getQuantity(); unsigned Size = Context.getTypeSizeInChars(T).getQuantity();
unsigned Type = Size; unsigned Type = Size;
if (const auto *ATy = Context.getAsArrayType(T)) if (const auto *ATy = Context.getAsArrayType(T))
Type = Context.getTypeSizeInChars(ATy->getElementType()).getQuantity(); Type = Context.getTypeSizeInChars(ATy->getElementType()).getQuantity();
bool IsGlobalLV = false; bool IsGlobalLV = false;
if (Res->EvaluateAsLValue(Eval, Context)) if (Res->EvaluateAsLValue(Eval, Context))
▲ Show 20 Lines • Show All 216 Lines • Show Last 20 Lines

clang/test/CodeGen/ms-inline-asm-64.c

// REQUIRES: x86-registered-target // REQUIRES: x86-registered-target
// RUN: %clang_cc1 %s -triple x86_64-apple-darwin10 -fasm-blocks -emit-llvm -o - | FileCheck %s // RUN: %clang_cc1 %s -triple x86_64-apple-darwin10 -fasm-blocks -emit-llvm -o - | FileCheck %s
void t1() { void t1() {
int var = 10; int var = 10;
__asm mov rax, offset var ; rax = address of myvar __asm mov rax, offset var ; rax = address of myvar
// CHECK: t1 // CHECK: t1
// CHECK: call void asm sideeffect inteldialect // CHECK: call void asm sideeffect inteldialect
// CHECK-SAME: mov rax, $0 // CHECK-SAME: mov rax, $0
// CHECK-SAME: "r,~{rax},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}}) // CHECK-SAME: "r,~{rax},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}})
} }
void t2() { void t2() {
int var = 10; int var = 10;
__asm mov [eax], offset var __asm mov qword ptr [eax], offset var
// CHECK: t2 // CHECK: t2
// CHECK: call void asm sideeffect inteldialect // CHECK: call void asm sideeffect inteldialect
// CHECK-SAME: mov [eax], $0 // CHECK-SAME: mov qword ptr [eax], $0
rnkUnsubmitted
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I guess this has the same semantics as it did before.

rnk: I guess this has the same semantics as it did before.
epastorAuthorUnsubmitted
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It does; this previously resolved to a "qword ptr" mov automatically, since $0 unpacked as a (forced) 64-bit register name. Now we need to specify the size of the move, since the operand is an immediate rather than a register.

epastor: It does; this previously resolved to a "qword ptr" mov automatically, since $0 unpacked as a…
// CHECK-SAME: "r,~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}}) // CHECK-SAME: "r,~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}})
} }
struct t3_type { int a, b; }; struct t3_type { int a, b; };
int t3() { int t3() {
struct t3_type foo; struct t3_type foo;
foo.a = 1; foo.a = 1;
Show All 34 Lines

clang/test/CodeGen/ms-inline-asm.c

Show First 20 Lines • Show All 184 Lines • ▼ Show 20 Lines
// CHECK: t15 // CHECK: t15
int lvar = 10; int lvar = 10;
__asm mov eax, lvar ; eax = 10 __asm mov eax, lvar ; eax = 10
// CHECK: mov eax, $0 // CHECK: mov eax, $0
__asm mov eax, offset lvar ; eax = address of lvar __asm mov eax, offset lvar ; eax = address of lvar
// CHECK: mov eax, $1 // CHECK: mov eax, $1
__asm mov eax, offset gvar ; eax = address of gvar __asm mov eax, offset gvar ; eax = address of gvar
// CHECK: mov eax, $2 // CHECK: mov eax, $2
// CHECK: "*m,r,r,~{eax},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}}, i32* %{{.*}}, i32* @{{.*}}) __asm mov eax, offset gvar+1 ; eax = 1 + address of gvar
// CHECK: mov eax, $3 + $$1
__asm mov eax, 1+offset gvar ; eax = 1 + address of gvar
// CHECK: mov eax, $4 + $$1
__asm mov eax, 1+offset gvar+1 ; eax = 2 + address of gvar
// CHECK: mov eax, $5 + $$2
// CHECK: "*m,r,i,i,i,i,~{eax},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}}, i32* %{{.*}}, i32* @{{.*}}, i32* @{{.*}}, i32* @{{.*}}, i32* @{{.*}})
} }
void t16() { void t16() {
int var = 10; int var = 10;
__asm mov [eax], offset var __asm mov dword ptr [eax], offset var
// CHECK: t16 // CHECK: t16
// CHECK: call void asm sideeffect inteldialect "mov [eax], $0", "r,~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}}) // CHECK: call void asm sideeffect inteldialect "mov dword ptr [eax], $0", "r,~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}})
} }
void t17() { void t17() {
// CHECK: t17 // CHECK: t17
__asm _emit 0x4A __asm _emit 0x4A
// CHECK: .byte 0x4A // CHECK: .byte 0x4A
__asm _emit 0x43L __asm _emit 0x43L
// CHECK: .byte 0x43L // CHECK: .byte 0x43L
▲ Show 20 Lines • Show All 585 Lines • Show Last 20 Lines

clang/test/CodeGen/ms-inline-asm.cpp

Show All 34 Lines
void t2() { void t2() {
int lvar = 10; int lvar = 10;
__asm mov eax, offset Foo::ptr __asm mov eax, offset Foo::ptr
__asm mov eax, offset Foo::Bar::ptr __asm mov eax, offset Foo::Bar::ptr
// CHECK-LABEL: define void @_Z2t2v() // CHECK-LABEL: define void @_Z2t2v()
// CHECK: call void asm sideeffect inteldialect // CHECK: call void asm sideeffect inteldialect
// CHECK-SAME: mov eax, $0 // CHECK-SAME: mov eax, $0
// CHECK-SAME: mov eax, $1 // CHECK-SAME: mov eax, $1
// CHECK-SAME: "r,r,~{eax},~{dirflag},~{fpsr},~{flags}"(i32** @_ZN3Foo3ptrE, i32** @_ZN3Foo3Bar3ptrE) // CHECK-SAME: "i,i,~{eax},~{dirflag},~{fpsr},~{flags}"(i32** @_ZN3Foo3ptrE, i32** @_ZN3Foo3Bar3ptrE)
} }
// CHECK-LABEL: define void @_Z2t3v() // CHECK-LABEL: define void @_Z2t3v()
void t3() { void t3() {
__asm mov eax, LENGTH Foo::ptr __asm mov eax, LENGTH Foo::ptr
__asm mov eax, LENGTH Foo::Bar::ptr __asm mov eax, LENGTH Foo::Bar::ptr
__asm mov eax, LENGTH Foo::arr __asm mov eax, LENGTH Foo::arr
__asm mov eax, LENGTH Foo::Bar::arr __asm mov eax, LENGTH Foo::Bar::arr
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clang/test/Parser/ms-inline-asm.c

Show First 20 Lines • Show All 51 Lines • ▼ Show 20 Lines
} }
void t12() { void t12() {
__asm jmp label // expected-error {{use of undeclared label 'label'}} __asm jmp label // expected-error {{use of undeclared label 'label'}}
} }
void t13() { void t13() {
__asm m{o}v eax, ebx // expected-error {{unknown token in expression}} __asm m{o}v eax, ebx // expected-error {{unknown token in expression}}
} }
void t14() {
enum { A = 1, B };
__asm mov eax, offset A // expected-error {{offset operator cannot yet handle constants}}
}
int t_fail() { // expected-note {{to match this}} int t_fail() { // expected-note {{to match this}}
__asm __asm
__asm { // expected-error 3 {{expected}} expected-note {{to match this}} __asm { // expected-error 3 {{expected}} expected-note {{to match this}}

llvm/include/llvm/MC/MCParser/MCParsedAsmOperand.h

Show First 20 Lines • Show All 69 Lines • ▼ Show 20 Linespublic:
/// needAddressOf - Do we need to emit code to get the address of the /// needAddressOf - Do we need to emit code to get the address of the
/// variable/label? Only valid when parsing MS-style inline assembly. /// variable/label? Only valid when parsing MS-style inline assembly.
virtual bool needAddressOf() const { return false; } virtual bool needAddressOf() const { return false; }
/// isCallOperand - Is this an operand of an inline-assembly call instruction? /// isCallOperand - Is this an operand of an inline-assembly call instruction?
/// Only valid when parsing MS-style inline assembly. /// Only valid when parsing MS-style inline assembly.
virtual bool isCallOperand() const { return false; } virtual bool isCallOperand() const { return false; }
/// isOffsetOf - Do we need to emit code to get the offset of the variable, /// isOffsetOfLocal - Do we need to emit code to get the offset of the local
/// rather then the value of the variable? Only valid when parsing MS-style /// variable, rather than its value? Only valid when parsing MS-style inline
/// inline assembly. /// assembly.
virtual bool isOffsetOf() const { return false; } virtual bool isOffsetOfLocal() const { return false; }
/// getOffsetOfLoc - Get the location of the offset operator. /// getOffsetOfLoc - Get the location of the offset operator.
virtual SMLoc getOffsetOfLoc() const { return SMLoc(); } virtual SMLoc getOffsetOfLoc() const { return SMLoc(); }
/// print - Print a debug representation of the operand to the given stream. /// print - Print a debug representation of the operand to the given stream.
virtual void print(raw_ostream &OS) const = 0; virtual void print(raw_ostream &OS) const = 0;
/// dump - Print to the debug stream. /// dump - Print to the debug stream.
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llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h

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// Represnt the various parts which makes up an intel expression, // Represnt the various parts which makes up an intel expression,
// used for emitting compound intel expressions // used for emitting compound intel expressions
struct IntelExpr { struct IntelExpr {
bool NeedBracs; bool NeedBracs;
int64_t Imm; int64_t Imm;
StringRef BaseReg; StringRef BaseReg;
StringRef IndexReg; StringRef IndexReg;
StringRef OffsetName;
unsigned Scale; unsigned Scale;
IntelExpr(bool needBracs = false) : NeedBracs(needBracs), Imm(0), IntelExpr()
BaseReg(StringRef()), IndexReg(StringRef()), : NeedBracs(false), Imm(0), BaseReg(StringRef()), IndexReg(StringRef()),
Scale(1) {} OffsetName(StringRef()), Scale(1) {}
rnkUnsubmitted
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These explicit empty StringRef initializations seem unnecessary, I'd suggest removing them.

rnk: These explicit empty StringRef initializations seem unnecessary, I'd suggest removing them.
// Compund immediate expression // [BaseReg + IndexReg * ScaleExpression + OFFSET name + ImmediateExpression]
IntelExpr(int64_t imm, bool needBracs) : IntelExpr(needBracs) { IntelExpr(StringRef baseReg, StringRef indexReg, unsigned scale,
Imm = imm; StringRef offsetName, int64_t imm, bool needBracs)
} : NeedBracs(needBracs), Imm(imm), BaseReg(baseReg), IndexReg(indexReg),
// [Reg + ImmediateExpression] OffsetName(offsetName), Scale(1) {
// We don't bother to emit an immediate expression evaluated to zero
IntelExpr(StringRef reg, int64_t imm = 0, unsigned scale = 0,
bool needBracs = true) :
IntelExpr(imm, needBracs) {
IndexReg = reg;
if (scale) if (scale)
Scale = scale; Scale = scale;
} }
// [BaseReg + IndexReg * ScaleExpression + ImmediateExpression] bool hasBaseReg() const { return !BaseReg.empty(); }
IntelExpr(StringRef baseReg, StringRef indexReg, unsigned scale = 0, bool hasIndexReg() const { return !IndexReg.empty(); }
int64_t imm = 0, bool needBracs = true) : bool hasRegs() const { return hasBaseReg() || hasIndexReg(); }
IntelExpr(indexReg, imm, scale, needBracs) { bool hasOffset() const { return !OffsetName.empty(); }
BaseReg = baseReg; // Normally we won't emit immediates unconditionally,
} // unless we've got no other components
bool hasBaseReg() const { bool emitImm() const { return !(hasRegs() || hasOffset()); }
return BaseReg.size();
}
bool hasIndexReg() const {
return IndexReg.size();
}
bool hasRegs() const {
return hasBaseReg() || hasIndexReg();
}
bool isValid() const { bool isValid() const {
return (Scale == 1) || return (Scale == 1) ||
(hasIndexReg() && (Scale == 2 || Scale == 4 || Scale == 8)); (hasIndexReg() && (Scale == 2 || Scale == 4 || Scale == 8));
} }
}; };
struct AsmRewrite { struct AsmRewrite {
AsmRewriteKind Kind; AsmRewriteKind Kind;
SMLoc Loc; SMLoc Loc;
unsigned Len; unsigned Len;
bool Done;
rnkUnsubmitted
Done
ReplyInline Actions

nit, pack the bool after the unsigned for a smaller struct. Hey, we make a vector of these. :)

rnk: nit, pack the bool after the unsigned for a smaller struct. Hey, we make a vector of these. :)
int64_t Val; int64_t Val;
StringRef Label; StringRef Label;
IntelExpr IntelExp; IntelExpr IntelExp;
public: public:
AsmRewrite(AsmRewriteKind kind, SMLoc loc, unsigned len = 0, int64_t val = 0) AsmRewrite(AsmRewriteKind kind, SMLoc loc, unsigned len = 0, int64_t val = 0)
: Kind(kind), Loc(loc), Len(len), Val(val) {} : Kind(kind), Loc(loc), Len(len), Done(false), Val(val) {}
AsmRewrite(AsmRewriteKind kind, SMLoc loc, unsigned len, StringRef label) AsmRewrite(AsmRewriteKind kind, SMLoc loc, unsigned len, StringRef label)
: AsmRewrite(kind, loc, len) { Label = label; } : AsmRewrite(kind, loc, len) { Label = label; }
AsmRewrite(SMLoc loc, unsigned len, IntelExpr exp) AsmRewrite(SMLoc loc, unsigned len, IntelExpr exp)
: AsmRewrite(AOK_IntelExpr, loc, len) { IntelExp = exp; } : AsmRewrite(AOK_IntelExpr, loc, len) { IntelExp = exp; }
}; };
struct ParseInstructionInfo { struct ParseInstructionInfo {
SmallVectorImpl<AsmRewrite> *AsmRewrites = nullptr; SmallVectorImpl<AsmRewrite> *AsmRewrites = nullptr;
▲ Show 20 Lines • Show All 378 Lines • Show Last 20 Lines

llvm/lib/MC/MCParser/AsmParser.cpp

Show First 20 Lines • Show All 5,798 Lines • ▼ Show 20 Lines if (Info.Opcode == ~0U)
continue; continue;
const MCInstrDesc &Desc = MII->get(Info.Opcode); const MCInstrDesc &Desc = MII->get(Info.Opcode);
// Build the list of clobbers, outputs and inputs. // Build the list of clobbers, outputs and inputs.
for (unsigned i = 1, e = Info.ParsedOperands.size(); i != e; ++i) { for (unsigned i = 1, e = Info.ParsedOperands.size(); i != e; ++i) {
MCParsedAsmOperand &Operand = *Info.ParsedOperands[i]; MCParsedAsmOperand &Operand = *Info.ParsedOperands[i];
// Immediate.
if (Operand.isImm())
continue;
// Register operand. // Register operand.
if (Operand.isReg() && !Operand.needAddressOf() && if (Operand.isReg() && !Operand.needAddressOf() &&
!getTargetParser().OmitRegisterFromClobberLists(Operand.getReg())) { !getTargetParser().OmitRegisterFromClobberLists(Operand.getReg())) {
unsigned NumDefs = Desc.getNumDefs(); unsigned NumDefs = Desc.getNumDefs();
// Clobber. // Clobber.
if (NumDefs && Operand.getMCOperandNum() < NumDefs) if (NumDefs && Operand.getMCOperandNum() < NumDefs)
ClobberRegs.push_back(Operand.getReg()); ClobberRegs.push_back(Operand.getReg());
continue; continue;
} }
// Expr/Input or Output. // Expr/Input or Output.
StringRef SymName = Operand.getSymName(); StringRef SymName = Operand.getSymName();
if (SymName.empty()) if (SymName.empty())
continue; continue;
void *OpDecl = Operand.getOpDecl(); void *OpDecl = Operand.getOpDecl();
if (!OpDecl) if (!OpDecl)
continue; continue;
StringRef Constraint = Operand.getConstraint();
if (Operand.isImm()) {
// Offset as immediate
if (Operand.isOffsetOfLocal())
Constraint = "r";
else
Constraint = "i";
}
bool isOutput = (i == 1) && Desc.mayStore(); bool isOutput = (i == 1) && Desc.mayStore();
SMLoc Start = SMLoc::getFromPointer(SymName.data()); SMLoc Start = SMLoc::getFromPointer(SymName.data());
if (isOutput) { if (isOutput) {
++InputIdx; ++InputIdx;
OutputDecls.push_back(OpDecl); OutputDecls.push_back(OpDecl);
OutputDeclsAddressOf.push_back(Operand.needAddressOf()); OutputDeclsAddressOf.push_back(Operand.needAddressOf());
OutputConstraints.push_back(("=" + Operand.getConstraint()).str()); OutputConstraints.push_back(("=" + Constraint).str());
AsmStrRewrites.emplace_back(AOK_Output, Start, SymName.size()); AsmStrRewrites.emplace_back(AOK_Output, Start, SymName.size());
} else { } else {
InputDecls.push_back(OpDecl); InputDecls.push_back(OpDecl);
InputDeclsAddressOf.push_back(Operand.needAddressOf()); InputDeclsAddressOf.push_back(Operand.needAddressOf());
InputConstraints.push_back(Operand.getConstraint().str()); InputConstraints.push_back(Constraint.str());
if (Operand.isCallOperand()) if (Operand.isCallOperand())
AsmStrRewrites.emplace_back(AOK_CallInput, Start, SymName.size()); AsmStrRewrites.emplace_back(AOK_CallInput, Start, SymName.size());
else else
AsmStrRewrites.emplace_back(AOK_Input, Start, SymName.size()); AsmStrRewrites.emplace_back(AOK_Input, Start, SymName.size());
} }
} }
// Consider implicit defs to be clobbers. Think of cpuid and push. // Consider implicit defs to be clobbers. Think of cpuid and push.
Show All 34 Linesbool AsmParser::parseMSInlineAsm(
// Build the IR assembly string. // Build the IR assembly string.
std::string AsmStringIR; std::string AsmStringIR;
raw_string_ostream OS(AsmStringIR); raw_string_ostream OS(AsmStringIR);
StringRef ASMString = StringRef ASMString =
SrcMgr.getMemoryBuffer(SrcMgr.getMainFileID())->getBuffer(); SrcMgr.getMemoryBuffer(SrcMgr.getMainFileID())->getBuffer();
const char *AsmStart = ASMString.begin(); const char *AsmStart = ASMString.begin();
const char *AsmEnd = ASMString.end(); const char *AsmEnd = ASMString.end();
array_pod_sort(AsmStrRewrites.begin(), AsmStrRewrites.end(), rewritesSort); array_pod_sort(AsmStrRewrites.begin(), AsmStrRewrites.end(), rewritesSort);
for (const AsmRewrite &AR : AsmStrRewrites) { for (auto it = AsmStrRewrites.begin(); it != AsmStrRewrites.end(); ++it) {
const AsmRewrite &AR = *it;
// Check if this has already been covered by another rewrite...
if (AR.Done)
continue;
AsmRewriteKind Kind = AR.Kind; AsmRewriteKind Kind = AR.Kind;
const char *Loc = AR.Loc.getPointer(); const char *Loc = AR.Loc.getPointer();
assert(Loc >= AsmStart && "Expected Loc to be at or after Start!"); assert(Loc >= AsmStart && "Expected Loc to be at or after Start!");
// Emit everything up to the immediate/expression. // Emit everything up to the immediate/expression.
if (unsigned Len = Loc - AsmStart) if (unsigned Len = Loc - AsmStart)
OS << StringRef(AsmStart, Len); OS << StringRef(AsmStart, Len);
Show All 14 Lines case AOK_IntelExpr:
if (AR.IntelExp.NeedBracs) if (AR.IntelExp.NeedBracs)
OS << "["; OS << "[";
if (AR.IntelExp.hasBaseReg()) if (AR.IntelExp.hasBaseReg())
OS << AR.IntelExp.BaseReg; OS << AR.IntelExp.BaseReg;
if (AR.IntelExp.hasIndexReg()) if (AR.IntelExp.hasIndexReg())
OS << (AR.IntelExp.hasBaseReg() ? " + " : "") OS << (AR.IntelExp.hasBaseReg() ? " + " : "")
<< AR.IntelExp.IndexReg; << AR.IntelExp.IndexReg;
if (AR.IntelExp.Scale > 1) if (AR.IntelExp.Scale > 1)
OS << " * $$" << AR.IntelExp.Scale; OS << " * $$" << AR.IntelExp.Scale;
if (AR.IntelExp.Imm || !AR.IntelExp.hasRegs()) if (AR.IntelExp.hasOffset()) {
OS << (AR.IntelExp.hasRegs() ? " + $$" : "$$") << AR.IntelExp.Imm; if (AR.IntelExp.hasRegs())
OS << " + ";
// Fuse this rewrite with a rewrite of the offset name, if present.
StringRef OffsetName = AR.IntelExp.OffsetName;
SMLoc OffsetLoc = SMLoc::getFromPointer(AR.IntelExp.OffsetName.data());
size_t OffsetLen = OffsetName.size();
auto rewrite_it = std::find_if(
it, AsmStrRewrites.end(), [&](const AsmRewrite &FusingAR) {
return FusingAR.Loc == OffsetLoc && FusingAR.Len == OffsetLen &&
(FusingAR.Kind == AOK_Input ||
rnkUnsubmitted
Done
ReplyInline Actions

Maybe this would be simpler with

auto rewrite_it = find_if(it, AsmStrRewrites.end(), [&](const AsmRewrite &OffsetAR) {
  // ... conditions below
});
rnk: Maybe this would be simpler with auto rewrite_it = find_if(it, AsmStrRewrites.end(), [&]…
FusingAR.Kind == AOK_CallInput);
});
if (rewrite_it == AsmStrRewrites.end()) {
OS << "offset " << OffsetName;
} else if (rewrite_it->Kind == AOK_CallInput) {
OS << "${" << InputIdx++ << ":P}";
rewrite_it->Done = true;
} else {
OS << '$' << InputIdx++;
rewrite_it->Done = true;
}
}
if (AR.IntelExp.Imm || AR.IntelExp.emitImm())
OS << (AR.IntelExp.emitImm() ? "$$" : " + $$") << AR.IntelExp.Imm;
if (AR.IntelExp.NeedBracs) if (AR.IntelExp.NeedBracs)
OS << "]"; OS << "]";
break; break;
case AOK_Label: case AOK_Label:
OS << Ctx.getAsmInfo()->getPrivateLabelPrefix() << AR.Label; OS << Ctx.getAsmInfo()->getPrivateLabelPrefix() << AR.Label;
break; break;
case AOK_Input: case AOK_Input:
OS << '$' << InputIdx++; OS << '$' << InputIdx++;
▲ Show 20 Lines • Show All 146 Lines • Show Last 20 Lines

llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp

Show First 20 Lines • Show All 128 Lines • ▼ Show 20 Lines enum InfixCalculatorTok {
IC_REGISTER IC_REGISTER
}; };
enum IntelOperatorKind { enum IntelOperatorKind {
IOK_INVALID = 0, IOK_INVALID = 0,
IOK_LENGTH, IOK_LENGTH,
IOK_SIZE, IOK_SIZE,
IOK_TYPE, IOK_TYPE,
IOK_OFFSET
}; };
class InfixCalculator { class InfixCalculator {
typedef std::pair< InfixCalculatorTok, int64_t > ICToken; typedef std::pair< InfixCalculatorTok, int64_t > ICToken;
SmallVector<InfixCalculatorTok, 4> InfixOperatorStack; SmallVector<InfixCalculatorTok, 4> InfixOperatorStack;
SmallVector<ICToken, 4> PostfixStack; SmallVector<ICToken, 4> PostfixStack;
bool isUnaryOperator(const InfixCalculatorTok Op) { bool isUnaryOperator(const InfixCalculatorTok Op) {
▲ Show 20 Lines • Show All 175 Lines • ▼ Show 20 Lines enum IntelExprState {
IES_INIT, IES_INIT,
IES_OR, IES_OR,
IES_XOR, IES_XOR,
IES_AND, IES_AND,
IES_LSHIFT, IES_LSHIFT,
IES_RSHIFT, IES_RSHIFT,
IES_PLUS, IES_PLUS,
IES_MINUS, IES_MINUS,
IES_OFFSET,
IES_NOT, IES_NOT,
IES_MULTIPLY, IES_MULTIPLY,
IES_DIVIDE, IES_DIVIDE,
IES_MOD, IES_MOD,
IES_LBRAC, IES_LBRAC,
IES_RBRAC, IES_RBRAC,
IES_LPAREN, IES_LPAREN,
IES_RPAREN, IES_RPAREN,
IES_REGISTER, IES_REGISTER,
IES_INTEGER, IES_INTEGER,
IES_IDENTIFIER, IES_IDENTIFIER,
IES_ERROR IES_ERROR
}; };
class IntelExprStateMachine { class IntelExprStateMachine {
IntelExprState State, PrevState; IntelExprState State, PrevState;
unsigned BaseReg, IndexReg, TmpReg, Scale; unsigned BaseReg, IndexReg, TmpReg, Scale;
int64_t Imm; int64_t Imm;
const MCExpr *Sym; const MCExpr *Sym;
StringRef SymName; StringRef SymName;
InfixCalculator IC; InfixCalculator IC;
InlineAsmIdentifierInfo Info; InlineAsmIdentifierInfo Info;
short BracCount; short BracCount;
bool MemExpr; bool MemExpr;
bool OffsetOperator;
SMLoc OffsetOperatorLoc;
bool setSymRef(const MCExpr *Val, StringRef ID, StringRef &ErrMsg) {
if (Sym) {
ErrMsg = "cannot use more than one symbol in memory operand";
return true;
}
Sym = Val;
SymName = ID;
return false;
}
public: public:
IntelExprStateMachine() IntelExprStateMachine()
: State(IES_INIT), PrevState(IES_ERROR), BaseReg(0), IndexReg(0), : State(IES_INIT), PrevState(IES_ERROR), BaseReg(0), IndexReg(0),
TmpReg(0), Scale(0), Imm(0), Sym(nullptr), BracCount(0), TmpReg(0), Scale(0), Imm(0), Sym(nullptr), BracCount(0),
MemExpr(false) {} MemExpr(false), OffsetOperator(false) {}
void addImm(int64_t imm) { Imm += imm; } void addImm(int64_t imm) { Imm += imm; }
short getBracCount() { return BracCount; } short getBracCount() { return BracCount; }
bool isMemExpr() { return MemExpr; } bool isMemExpr() { return MemExpr; }
bool isOffsetOperator() { return OffsetOperator; }
SMLoc getOffsetLoc() { return OffsetOperatorLoc; }
unsigned getBaseReg() { return BaseReg; } unsigned getBaseReg() { return BaseReg; }
unsigned getIndexReg() { return IndexReg; } unsigned getIndexReg() { return IndexReg; }
unsigned getScale() { return Scale; } unsigned getScale() { return Scale; }
const MCExpr *getSym() { return Sym; } const MCExpr *getSym() { return Sym; }
StringRef getSymName() { return SymName; } StringRef getSymName() { return SymName; }
int64_t getImm() { return Imm + IC.execute(); } int64_t getImm() { return Imm + IC.execute(); }
bool isValidEndState() { bool isValidEndState() {
return State == IES_RBRAC || State == IES_INTEGER; return State == IES_RBRAC || State == IES_INTEGER;
▲ Show 20 Lines • Show All 80 Lines • ▼ Show 20 Lines bool onPlus(StringRef &ErrMsg) {
IntelExprState CurrState = State; IntelExprState CurrState = State;
switch (State) { switch (State) {
default: default:
State = IES_ERROR; State = IES_ERROR;
break; break;
case IES_INTEGER: case IES_INTEGER:
case IES_RPAREN: case IES_RPAREN:
case IES_REGISTER: case IES_REGISTER:
case IES_OFFSET:
State = IES_PLUS; State = IES_PLUS;
IC.pushOperator(IC_PLUS); IC.pushOperator(IC_PLUS);
if (CurrState == IES_REGISTER && PrevState != IES_MULTIPLY) { if (CurrState == IES_REGISTER && PrevState != IES_MULTIPLY) {
// If we already have a BaseReg, then assume this is the IndexReg with // If we already have a BaseReg, then assume this is the IndexReg with
// no explicit scale. // no explicit scale.
if (!BaseReg) { if (!BaseReg) {
BaseReg = TmpReg; BaseReg = TmpReg;
} else { } else {
Show All 28 Lines bool onMinus(StringRef &ErrMsg) {
case IES_MOD: case IES_MOD:
case IES_LPAREN: case IES_LPAREN:
case IES_RPAREN: case IES_RPAREN:
case IES_LBRAC: case IES_LBRAC:
case IES_RBRAC: case IES_RBRAC:
case IES_INTEGER: case IES_INTEGER:
case IES_REGISTER: case IES_REGISTER:
case IES_INIT: case IES_INIT:
case IES_OFFSET:
State = IES_MINUS; State = IES_MINUS;
// push minus operator if it is not a negate operator // push minus operator if it is not a negate operator
if (CurrState == IES_REGISTER || CurrState == IES_RPAREN || if (CurrState == IES_REGISTER || CurrState == IES_RPAREN ||
CurrState == IES_INTEGER || CurrState == IES_RBRAC) CurrState == IES_INTEGER || CurrState == IES_RBRAC ||
CurrState == IES_OFFSET)
IC.pushOperator(IC_MINUS); IC.pushOperator(IC_MINUS);
else if (PrevState == IES_REGISTER && CurrState == IES_MULTIPLY) { else if (PrevState == IES_REGISTER && CurrState == IES_MULTIPLY) {
// We have negate operator for Scale: it's illegal // We have negate operator for Scale: it's illegal
ErrMsg = "Scale can't be negative"; ErrMsg = "Scale can't be negative";
return true; return true;
} else } else
IC.pushOperator(IC_NEG); IC.pushOperator(IC_NEG);
if (CurrState == IES_REGISTER && PrevState != IES_MULTIPLY) { if (CurrState == IES_REGISTER && PrevState != IES_MULTIPLY) {
Show All 36 Lines void onNot() {
case IES_LBRAC: case IES_LBRAC:
case IES_INIT: case IES_INIT:
State = IES_NOT; State = IES_NOT;
IC.pushOperator(IC_NOT); IC.pushOperator(IC_NOT);
break; break;
} }
PrevState = CurrState; PrevState = CurrState;
} }
bool onRegister(unsigned Reg, StringRef &ErrMsg) { bool onRegister(unsigned Reg, StringRef &ErrMsg) {
IntelExprState CurrState = State; IntelExprState CurrState = State;
switch (State) { switch (State) {
default: default:
State = IES_ERROR; State = IES_ERROR;
break; break;
case IES_PLUS: case IES_PLUS:
case IES_LPAREN: case IES_LPAREN:
Show All 31 Lines bool onIdentifierExpr(const MCExpr *SymRef, StringRef SymRefName,
// InlineAsm: Treat an enum value as an integer // InlineAsm: Treat an enum value as an integer
if (ParsingInlineAsm) if (ParsingInlineAsm)
if (IDInfo.isKind(InlineAsmIdentifierInfo::IK_EnumVal)) if (IDInfo.isKind(InlineAsmIdentifierInfo::IK_EnumVal))
return onInteger(IDInfo.Enum.EnumVal, ErrMsg); return onInteger(IDInfo.Enum.EnumVal, ErrMsg);
// Treat a symbolic constant like an integer // Treat a symbolic constant like an integer
if (auto *CE = dyn_cast<MCConstantExpr>(SymRef)) if (auto *CE = dyn_cast<MCConstantExpr>(SymRef))
return onInteger(CE->getValue(), ErrMsg); return onInteger(CE->getValue(), ErrMsg);
PrevState = State; PrevState = State;
bool HasSymbol = Sym != nullptr;
switch (State) { switch (State) {
default: default:
State = IES_ERROR; State = IES_ERROR;
break; break;
case IES_PLUS: case IES_PLUS:
case IES_MINUS: case IES_MINUS:
case IES_NOT: case IES_NOT:
case IES_INIT: case IES_INIT:
case IES_LBRAC: case IES_LBRAC:
if (setSymRef(SymRef, SymRefName, ErrMsg))
return true;
MemExpr = true; MemExpr = true;
State = IES_INTEGER; State = IES_INTEGER;
Sym = SymRef;
SymName = SymRefName;
IC.pushOperand(IC_IMM); IC.pushOperand(IC_IMM);
if (ParsingInlineAsm) if (ParsingInlineAsm)
Info = IDInfo; Info = IDInfo;
break; break;
} }
if (HasSymbol) return false;
ErrMsg = "cannot use more than one symbol in memory operand";
return HasSymbol;
} }
bool onInteger(int64_t TmpInt, StringRef &ErrMsg) { bool onInteger(int64_t TmpInt, StringRef &ErrMsg) {
IntelExprState CurrState = State; IntelExprState CurrState = State;
switch (State) { switch (State) {
default: default:
State = IES_ERROR; State = IES_ERROR;
break; break;
case IES_PLUS: case IES_PLUS:
▲ Show 20 Lines • Show All 96 Lines • ▼ Show 20 Lines public:
} }
bool onRBrac() { bool onRBrac() {
IntelExprState CurrState = State; IntelExprState CurrState = State;
switch (State) { switch (State) {
default: default:
State = IES_ERROR; State = IES_ERROR;
break; break;
case IES_INTEGER: case IES_INTEGER:
case IES_OFFSET:
case IES_REGISTER: case IES_REGISTER:
case IES_RPAREN: case IES_RPAREN:
if (BracCount-- != 1) if (BracCount-- != 1)
return true; return true;
State = IES_RBRAC; State = IES_RBRAC;
if (CurrState == IES_REGISTER && PrevState != IES_MULTIPLY) { if (CurrState == IES_REGISTER && PrevState != IES_MULTIPLY) {
// If we already have a BaseReg, then assume this is the IndexReg with // If we already have a BaseReg, then assume this is the IndexReg with
// no explicit scale. // no explicit scale.
Show All 38 Lines public:
} }
void onRParen() { void onRParen() {
PrevState = State; PrevState = State;
switch (State) { switch (State) {
default: default:
State = IES_ERROR; State = IES_ERROR;
break; break;
case IES_INTEGER: case IES_INTEGER:
case IES_OFFSET:
case IES_REGISTER: case IES_REGISTER:
case IES_RPAREN: case IES_RPAREN:
State = IES_RPAREN; State = IES_RPAREN;
IC.pushOperator(IC_RPAREN); IC.pushOperator(IC_RPAREN);
break; break;
} }
} }
bool onOffset(const MCExpr *Val, SMLoc OffsetLoc, StringRef ID,
const InlineAsmIdentifierInfo &IDInfo, bool ParsingInlineAsm,
StringRef &ErrMsg) {
PrevState = State;
switch (State) {
default:
ErrMsg = "unexpected offset operator expression";
return true;
case IES_PLUS:
case IES_INIT:
case IES_LBRAC:
if (setSymRef(Val, ID, ErrMsg))
return true;
OffsetOperator = true;
OffsetOperatorLoc = OffsetLoc;
State = IES_OFFSET;
// As we cannot yet resolve the actual value (offset), we retain
// the requested semantics by pushing a '0' to the operands stack
IC.pushOperand(IC_IMM);
if (ParsingInlineAsm) {
Info = IDInfo;
}
break;
}
return false;
}
}; };
bool Error(SMLoc L, const Twine &Msg, SMRange Range = None, bool Error(SMLoc L, const Twine &Msg, SMRange Range = None,
bool MatchingInlineAsm = false) { bool MatchingInlineAsm = false) {
MCAsmParser &Parser = getParser(); MCAsmParser &Parser = getParser();
if (MatchingInlineAsm) { if (MatchingInlineAsm) {
if (!getLexer().isAtStartOfStatement()) if (!getLexer().isAtStartOfStatement())
Parser.eatToEndOfStatement(); Parser.eatToEndOfStatement();
Show All 15 Linesprivate:
AddDefaultSrcDestOperands(OperandVector &Operands, AddDefaultSrcDestOperands(OperandVector &Operands,
std::unique_ptr<llvm::MCParsedAsmOperand> &&Src, std::unique_ptr<llvm::MCParsedAsmOperand> &&Src,
std::unique_ptr<llvm::MCParsedAsmOperand> &&Dst); std::unique_ptr<llvm::MCParsedAsmOperand> &&Dst);
bool VerifyAndAdjustOperands(OperandVector &OrigOperands, bool VerifyAndAdjustOperands(OperandVector &OrigOperands,
OperandVector &FinalOperands); OperandVector &FinalOperands);
std::unique_ptr<X86Operand> ParseOperand(); std::unique_ptr<X86Operand> ParseOperand();
std::unique_ptr<X86Operand> ParseATTOperand(); std::unique_ptr<X86Operand> ParseATTOperand();
std::unique_ptr<X86Operand> ParseIntelOperand(); std::unique_ptr<X86Operand> ParseIntelOperand();
std::unique_ptr<X86Operand> ParseIntelOffsetOfOperator(); bool ParseIntelOffsetOperator(const MCExpr *&Val, StringRef &ID,
InlineAsmIdentifierInfo &Info, SMLoc &End);
bool ParseIntelDotOperator(IntelExprStateMachine &SM, SMLoc &End); bool ParseIntelDotOperator(IntelExprStateMachine &SM, SMLoc &End);
unsigned IdentifyIntelInlineAsmOperator(StringRef Name); unsigned IdentifyIntelInlineAsmOperator(StringRef Name);
unsigned ParseIntelInlineAsmOperator(unsigned OpKind); unsigned ParseIntelInlineAsmOperator(unsigned OpKind);
std::unique_ptr<X86Operand> ParseRoundingModeOp(SMLoc Start); std::unique_ptr<X86Operand> ParseRoundingModeOp(SMLoc Start);
bool ParseIntelNamedOperator(StringRef Name, IntelExprStateMachine &SM); bool ParseIntelNamedOperator(StringRef Name, IntelExprStateMachine &SM,
bool &ParseError, SMLoc &End);
void RewriteIntelExpression(IntelExprStateMachine &SM, SMLoc Start, void RewriteIntelExpression(IntelExprStateMachine &SM, SMLoc Start,
SMLoc End); SMLoc End);
bool ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End); bool ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End);
bool ParseIntelInlineAsmIdentifier(const MCExpr *&Val, StringRef &Identifier, bool ParseIntelInlineAsmIdentifier(const MCExpr *&Val, StringRef &Identifier,
InlineAsmIdentifierInfo &Info, InlineAsmIdentifierInfo &Info,
bool IsUnevaluatedOperand, SMLoc &End); bool IsUnevaluatedOperand, SMLoc &End,
bool IsParsingOffsetOperator = false);
std::unique_ptr<X86Operand> ParseMemOperand(unsigned SegReg, std::unique_ptr<X86Operand> ParseMemOperand(unsigned SegReg,
const MCExpr *&Disp, const MCExpr *&Disp,
const SMLoc &StartLoc, const SMLoc &StartLoc,
SMLoc &EndLoc); SMLoc &EndLoc);
X86::CondCode ParseConditionCode(StringRef CCode); X86::CondCode ParseConditionCode(StringRef CCode);
▲ Show 20 Lines • Show All 551 Lines • ▼ Show 20 Lines return X86Operand::CreateMem(getPointerWidth(), SegReg, Disp, BaseReg,
IndexReg, Scale, Start, End, Size, Identifier, IndexReg, Scale, Start, End, Size, Identifier,
Decl, FrontendSize); Decl, FrontendSize);
} }
} }
// Some binary bitwise operators have a named synonymous // Some binary bitwise operators have a named synonymous
// Query a candidate string for being such a named operator // Query a candidate string for being such a named operator
// and if so - invoke the appropriate handler // and if so - invoke the appropriate handler
bool X86AsmParser::ParseIntelNamedOperator(StringRef Name, IntelExprStateMachine &SM) { bool X86AsmParser::ParseIntelNamedOperator(StringRef Name,
IntelExprStateMachine &SM,
bool &ParseError, SMLoc &End) {
// A named operator should be either lower or upper case, but not a mix // A named operator should be either lower or upper case, but not a mix
if (Name.compare(Name.lower()) && Name.compare(Name.upper())) if (Name.compare(Name.lower()) && Name.compare(Name.upper()))
return false; return false;
if (Name.equals_lower("not")) if (Name.equals_lower("not")) {
SM.onNot(); SM.onNot();
else if (Name.equals_lower("or")) } else if (Name.equals_lower("or")) {
SM.onOr(); SM.onOr();
else if (Name.equals_lower("shl")) } else if (Name.equals_lower("shl")) {
SM.onLShift(); SM.onLShift();
else if (Name.equals_lower("shr")) } else if (Name.equals_lower("shr")) {
SM.onRShift(); SM.onRShift();
else if (Name.equals_lower("xor")) } else if (Name.equals_lower("xor")) {
SM.onXor(); SM.onXor();
else if (Name.equals_lower("and")) } else if (Name.equals_lower("and")) {
SM.onAnd(); SM.onAnd();
else if (Name.equals_lower("mod")) } else if (Name.equals_lower("mod")) {
SM.onMod(); SM.onMod();
else } else if (Name.equals_lower("offset")) {
SMLoc OffsetLoc = getTok().getLoc();
const MCExpr *Val = nullptr;
StringRef ID;
InlineAsmIdentifierInfo Info;
ParseError = ParseIntelOffsetOperator(Val, ID, Info, End);
rnkUnsubmitted
Done
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While this doesn't trigger warnings, it seems like it would be simpler to do the assignment as its own statement and then if (ParseErrror) return true;

I see that the local code style uses this pattern already, but I'm not sure that's a good reason to promote it and keep using it.

rnk: While this doesn't trigger warnings, it seems like it would be simpler to do the assignment as…
if (ParseError)
return true;
StringRef ErrMsg;
rnkUnsubmitted
Done
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ditto

rnk: ditto
ParseError =
SM.onOffset(Val, OffsetLoc, ID, Info, isParsingInlineAsm(), ErrMsg);
if (ParseError)
return Error(SMLoc::getFromPointer(Name.data()), ErrMsg);
} else {
return false; return false;
}
if (!Name.equals_lower("offset"))
End = consumeToken();
return true; return true;
} }
bool X86AsmParser::ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End) { bool X86AsmParser::ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End) {
MCAsmParser &Parser = getParser(); MCAsmParser &Parser = getParser();
const AsmToken &Tok = Parser.getTok(); const AsmToken &Tok = Parser.getTok();
StringRef ErrMsg; StringRef ErrMsg;
Show All 26 Lines case AsmToken::Identifier: {
// Register // Register
unsigned Reg; unsigned Reg;
if (Tok.is(AsmToken::Identifier) && !ParseRegister(Reg, IdentLoc, End)) { if (Tok.is(AsmToken::Identifier) && !ParseRegister(Reg, IdentLoc, End)) {
if (SM.onRegister(Reg, ErrMsg)) if (SM.onRegister(Reg, ErrMsg))
return Error(Tok.getLoc(), ErrMsg); return Error(Tok.getLoc(), ErrMsg);
break; break;
} }
// Operator synonymous ("not", "or" etc.) // Operator synonymous ("not", "or" etc.)
if ((UpdateLocLex = ParseIntelNamedOperator(Identifier, SM))) bool ParseError = false;
if (ParseIntelNamedOperator(Identifier, SM, ParseError, End)) {
if (ParseError)
return true;
break; break;
}
// Symbol reference, when parsing assembly content // Symbol reference, when parsing assembly content
InlineAsmIdentifierInfo Info; InlineAsmIdentifierInfo Info;
const MCExpr *Val; const MCExpr *Val;
if (!isParsingInlineAsm()) { if (!isParsingInlineAsm()) {
if (getParser().parsePrimaryExpr(Val, End)) { if (getParser().parsePrimaryExpr(Val, End)) {
return Error(Tok.getLoc(), "Unexpected identifier!"); return Error(Tok.getLoc(), "Unexpected identifier!");
} else if (SM.onIdentifierExpr(Val, Identifier, Info, false, ErrMsg)) { } else if (SM.onIdentifierExpr(Val, Identifier, Info, false, ErrMsg)) {
return Error(IdentLoc, ErrMsg); return Error(IdentLoc, ErrMsg);
} else } else
break; break;
} }
// MS InlineAsm operators (TYPE/LENGTH/SIZE) // MS InlineAsm operators (TYPE/LENGTH/SIZE)
if (unsigned OpKind = IdentifyIntelInlineAsmOperator(Identifier)) { if (unsigned OpKind = IdentifyIntelInlineAsmOperator(Identifier)) {
if (OpKind == IOK_OFFSET)
return Error(IdentLoc, "Dealing OFFSET operator as part of"
"a compound immediate expression is yet to be supported");
if (int64_t Val = ParseIntelInlineAsmOperator(OpKind)) { if (int64_t Val = ParseIntelInlineAsmOperator(OpKind)) {
if (SM.onInteger(Val, ErrMsg)) if (SM.onInteger(Val, ErrMsg))
return Error(IdentLoc, ErrMsg); return Error(IdentLoc, ErrMsg);
} else } else
return true; return true;
break; break;
} }
// MS Dot Operator expression // MS Dot Operator expression
▲ Show 20 Lines • Show All 85 Lines • ▼ Show 20 Linesbool X86AsmParser::ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End) {
return false; return false;
} }
void X86AsmParser::RewriteIntelExpression(IntelExprStateMachine &SM, void X86AsmParser::RewriteIntelExpression(IntelExprStateMachine &SM,
SMLoc Start, SMLoc End) { SMLoc Start, SMLoc End) {
SMLoc Loc = Start; SMLoc Loc = Start;
unsigned ExprLen = End.getPointer() - Start.getPointer(); unsigned ExprLen = End.getPointer() - Start.getPointer();
// Skip everything before a symbol displacement (if we have one) // Skip everything before a symbol displacement (if we have one)
if (SM.getSym()) { if (SM.getSym() && !SM.isOffsetOperator()) {
StringRef SymName = SM.getSymName(); StringRef SymName = SM.getSymName();
if (unsigned Len = SymName.data() - Start.getPointer()) if (unsigned Len = SymName.data() - Start.getPointer())
InstInfo->AsmRewrites->emplace_back(AOK_Skip, Start, Len); InstInfo->AsmRewrites->emplace_back(AOK_Skip, Start, Len);
Loc = SMLoc::getFromPointer(SymName.data() + SymName.size()); Loc = SMLoc::getFromPointer(SymName.data() + SymName.size());
ExprLen = End.getPointer() - (SymName.data() + SymName.size()); ExprLen = End.getPointer() - (SymName.data() + SymName.size());
// If we have only a symbol than there's no need for complex rewrite, // If we have only a symbol than there's no need for complex rewrite,
// simply skip everything after it // simply skip everything after it
if (!(SM.getBaseReg() || SM.getIndexReg() || SM.getImm())) { if (!(SM.getBaseReg() || SM.getIndexReg() || SM.getImm())) {
if (ExprLen) if (ExprLen)
InstInfo->AsmRewrites->emplace_back(AOK_Skip, Loc, ExprLen); InstInfo->AsmRewrites->emplace_back(AOK_Skip, Loc, ExprLen);
return; return;
} }
} }
// Build an Intel Expression rewrite // Build an Intel Expression rewrite
StringRef BaseRegStr; StringRef BaseRegStr;
StringRef IndexRegStr; StringRef IndexRegStr;
StringRef OffsetNameStr;
if (SM.getBaseReg()) if (SM.getBaseReg())
BaseRegStr = X86IntelInstPrinter::getRegisterName(SM.getBaseReg()); BaseRegStr = X86IntelInstPrinter::getRegisterName(SM.getBaseReg());
if (SM.getIndexReg()) if (SM.getIndexReg())
IndexRegStr = X86IntelInstPrinter::getRegisterName(SM.getIndexReg()); IndexRegStr = X86IntelInstPrinter::getRegisterName(SM.getIndexReg());
if (SM.isOffsetOperator())
OffsetNameStr = SM.getSymName();
// Emit it // Emit it
IntelExpr Expr(BaseRegStr, IndexRegStr, SM.getScale(), SM.getImm(), SM.isMemExpr()); IntelExpr Expr(BaseRegStr, IndexRegStr, SM.getScale(), OffsetNameStr,
SM.getImm(), SM.isMemExpr());
InstInfo->AsmRewrites->emplace_back(Loc, ExprLen, Expr); InstInfo->AsmRewrites->emplace_back(Loc, ExprLen, Expr);
} }
// Inline assembly may use variable names with namespace alias qualifiers. // Inline assembly may use variable names with namespace alias qualifiers.
bool X86AsmParser::ParseIntelInlineAsmIdentifier(const MCExpr *&Val, bool X86AsmParser::ParseIntelInlineAsmIdentifier(
StringRef &Identifier, const MCExpr *&Val, StringRef &Identifier, InlineAsmIdentifierInfo &Info,
InlineAsmIdentifierInfo &Info, bool IsUnevaluatedOperand, SMLoc &End, bool IsParsingOffsetOperator) {
bool IsUnevaluatedOperand,
SMLoc &End) {
MCAsmParser &Parser = getParser(); MCAsmParser &Parser = getParser();
assert(isParsingInlineAsm() && "Expected to be parsing inline assembly."); assert(isParsingInlineAsm() && "Expected to be parsing inline assembly.");
Val = nullptr; Val = nullptr;
StringRef LineBuf(Identifier.data()); StringRef LineBuf(Identifier.data());
SemaCallback->LookupInlineAsmIdentifier(LineBuf, Info, IsUnevaluatedOperand); SemaCallback->LookupInlineAsmIdentifier(LineBuf, Info, IsUnevaluatedOperand);
const AsmToken &Tok = Parser.getTok(); const AsmToken &Tok = Parser.getTok();
Show All 16 Linesbool X86AsmParser::ParseIntelInlineAsmIdentifier(
// If the identifier lookup was unsuccessful, assume that we are dealing with // If the identifier lookup was unsuccessful, assume that we are dealing with
// a label. // a label.
if (Info.isKind(InlineAsmIdentifierInfo::IK_Invalid)) { if (Info.isKind(InlineAsmIdentifierInfo::IK_Invalid)) {
StringRef InternalName = StringRef InternalName =
SemaCallback->LookupInlineAsmLabel(Identifier, getSourceManager(), SemaCallback->LookupInlineAsmLabel(Identifier, getSourceManager(),
Loc, false); Loc, false);
assert(InternalName.size() && "We should have an internal name here."); assert(InternalName.size() && "We should have an internal name here.");
// Push a rewrite for replacing the identifier name with the internal name. // Push a rewrite for replacing the identifier name with the internal name,
// unless we are parsing the operand of an offset operator
if (!IsParsingOffsetOperator)
InstInfo->AsmRewrites->emplace_back(AOK_Label, Loc, Identifier.size(), InstInfo->AsmRewrites->emplace_back(AOK_Label, Loc, Identifier.size(),
InternalName); InternalName);
else
Identifier = InternalName;
} else if (Info.isKind(InlineAsmIdentifierInfo::IK_EnumVal)) } else if (Info.isKind(InlineAsmIdentifierInfo::IK_EnumVal))
return false; return false;
// Create the symbol reference. // Create the symbol reference.
MCSymbol *Sym = getContext().getOrCreateSymbol(Identifier); MCSymbol *Sym = getContext().getOrCreateSymbol(Identifier);
MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None; MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None;
Val = MCSymbolRefExpr::create(Sym, Variant, getParser().getContext()); Val = MCSymbolRefExpr::create(Sym, Variant, getParser().getContext());
return false; return false;
} }
▲ Show 20 Lines • Show All 66 Lines • ▼ Show 20 Linesbool X86AsmParser::ParseIntelDotOperator(IntelExprStateMachine &SM, SMLoc &End) {
End = SMLoc::getFromPointer(DotDispStr.data()); End = SMLoc::getFromPointer(DotDispStr.data());
const char *DotExprEndLoc = DotDispStr.data() + DotDispStr.size(); const char *DotExprEndLoc = DotDispStr.data() + DotDispStr.size();
while (Tok.getLoc().getPointer() < DotExprEndLoc) while (Tok.getLoc().getPointer() < DotExprEndLoc)
Lex(); Lex();
SM.addImm(Offset); SM.addImm(Offset);
return false; return false;
} }
/// Parse the 'offset' operator. This operator is used to specify the /// Parse the 'offset' operator.
/// location rather then the content of a variable. /// This operator is used to specify the location of a given operand
std::unique_ptr<X86Operand> X86AsmParser::ParseIntelOffsetOfOperator() { bool X86AsmParser::ParseIntelOffsetOperator(const MCExpr *&Val, StringRef &ID,
MCAsmParser &Parser = getParser(); InlineAsmIdentifierInfo &Info,
const AsmToken &Tok = Parser.getTok(); SMLoc &End) {
SMLoc OffsetOfLoc = Tok.getLoc(); // Eat offset, mark start of identifier.
Parser.Lex(); // Eat offset. SMLoc Start = Lex().getLoc();
ID = getTok().getString();
const MCExpr *Val; if (!isParsingInlineAsm()) {
InlineAsmIdentifierInfo Info; if ((getTok().isNot(AsmToken::Identifier) &&
SMLoc Start = Tok.getLoc(), End; getTok().isNot(AsmToken::String)) ||
StringRef Identifier = Tok.getString(); getParser().parsePrimaryExpr(Val, End))
if (ParseIntelInlineAsmIdentifier(Val, Identifier, Info, return Error(Start, "unexpected token!");
rnkUnsubmitted
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Please test this corner case, I imagine it looks like:

mov eax, offset 3
rnk: Please test this corner case, I imagine it looks like: mov eax, offset 3
epastorAuthorUnsubmitted
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Interesting. This corner case didn't trigger in that scenario; we get an "expected identifier" error message with good source location, followed by another error "use of undeclared label '3'" in debug builds... and in release builds, we instead get a crash. On tracing the crash, it's a AsmStrRewrite applying to a SMLoc not coming from the same string...

As near as I can tell, the issue is that we end up trying to parse "3" as a not-yet-declared label, as such expand it to __MSASMLABEL_.${:uid}__3, and then end up in a bad state because the operand rewrite is applying to the expanded symbol... which isn't in the same AsmString. If you use an actual undeclared label, you hit the same crash in release builds.

This is going to take some work; I'll get back to it in a day or two.

epastor: Interesting. This corner case didn't trigger in that scenario; we get an "expected identifier"…
epastorAuthorUnsubmitted
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Fixed; we now get the same errors in this scenario as we do in the current LLVM trunk, reporting "expected identifier" and "use of undeclared label '3'".

On the other hand, I'm still working on finding a scenario that DOES trigger this corner case.

epastor: Fixed; we now get the same errors in this scenario as we do in the current LLVM trunk…
rnkUnsubmitted
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I see. Well, it sounds like it was a useful test. :)

rnk: I see. Well, it sounds like it was a useful test. :)
epastorAuthorUnsubmitted
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Very useful indeed!

epastor: Very useful indeed!
/*Unevaluated=*/false, End)) } else if (ParseIntelInlineAsmIdentifier(Val, ID, Info, false, End, true)) {
return nullptr; return Error(Start, "unable to lookup expression");
} else if (Info.isKind(InlineAsmIdentifierInfo::IK_EnumVal)) {
void *Decl = nullptr; return Error(Start, "offset operator cannot yet handle constants");
rnkUnsubmitted
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Please add a test for this corner case, I'm curious to see if the error reporting really works.

rnk: Please add a test for this corner case, I'm curious to see if the error reporting really works.
epastorAuthorUnsubmitted
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This error reporting doesn't work, in fact. We instead get "cannot take the address of an rvalue of type 'int'", with bad source location. Will investigate why we end up there.

epastor: This error reporting doesn't work, in fact. We instead get "cannot take the address of an…
epastorAuthorUnsubmitted
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Turns out Sema wasn't successfully recognizing inline-assembly references to enum values, so we were processing them through as labels, and only recognizing the problem late in processing. Fixed now, with accurate error reporting; test added.

epastor: Turns out Sema wasn't successfully recognizing inline-assembly references to enum values, so we…
// FIXME: MS evaluates "offset <Constant>" to the underlying integral }
if (Info.isKind(InlineAsmIdentifierInfo::IK_EnumVal)) return false;
return ErrorOperand(Start, "offset operator cannot yet handle constants");
else if (Info.isKind(InlineAsmIdentifierInfo::IK_Var))
Decl = Info.Var.Decl;
// Don't emit the offset operator.
InstInfo->AsmRewrites->emplace_back(AOK_Skip, OffsetOfLoc, 7);
// The offset operator will have an 'r' constraint, thus we need to create
// register operand to ensure proper matching. Just pick a GPR based on
// the size of a pointer.
bool Parse32 = is32BitMode() || Code16GCC;
unsigned RegNo = is64BitMode() ? X86::RBX : (Parse32 ? X86::EBX : X86::BX);
return X86Operand::CreateReg(RegNo, Start, End, /*GetAddress=*/true,
OffsetOfLoc, Identifier, Decl);
} }
// Query a candidate string for being an Intel assembly operator // Query a candidate string for being an Intel assembly operator
// Report back its kind, or IOK_INVALID if does not evaluated as a known one // Report back its kind, or IOK_INVALID if does not evaluated as a known one
unsigned X86AsmParser::IdentifyIntelInlineAsmOperator(StringRef Name) { unsigned X86AsmParser::IdentifyIntelInlineAsmOperator(StringRef Name) {
return StringSwitch<unsigned>(Name) return StringSwitch<unsigned>(Name)
.Cases("TYPE","type",IOK_TYPE) .Cases("TYPE","type",IOK_TYPE)
.Cases("SIZE","size",IOK_SIZE) .Cases("SIZE","size",IOK_SIZE)
.Cases("LENGTH","length",IOK_LENGTH) .Cases("LENGTH","length",IOK_LENGTH)
.Cases("OFFSET","offset",IOK_OFFSET)
.Default(IOK_INVALID); .Default(IOK_INVALID);
} }
/// Parse the 'LENGTH', 'TYPE' and 'SIZE' operators. The LENGTH operator /// Parse the 'LENGTH', 'TYPE' and 'SIZE' operators. The LENGTH operator
/// returns the number of elements in an array. It returns the value 1 for /// returns the number of elements in an array. It returns the value 1 for
/// non-array variables. The SIZE operator returns the size of a C or C++ /// non-array variables. The SIZE operator returns the size of a C or C++
/// variable. A variable's size is the product of its LENGTH and TYPE. The /// variable. A variable's size is the product of its LENGTH and TYPE. The
/// TYPE operator returns the size of a C or C++ type or variable. If the /// TYPE operator returns the size of a C or C++ type or variable. If the
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Linesbool X86AsmParser::ParseIntelMemoryOperandSize(unsigned &Size) {
return false; return false;
} }
std::unique_ptr<X86Operand> X86AsmParser::ParseIntelOperand() { std::unique_ptr<X86Operand> X86AsmParser::ParseIntelOperand() {
MCAsmParser &Parser = getParser(); MCAsmParser &Parser = getParser();
const AsmToken &Tok = Parser.getTok(); const AsmToken &Tok = Parser.getTok();
SMLoc Start, End; SMLoc Start, End;
// FIXME: Offset operator
// Should be handled as part of immediate expression, as other operators
// Currently, only supported as a stand-alone operand
if (isParsingInlineAsm())
if (IdentifyIntelInlineAsmOperator(Tok.getString()) == IOK_OFFSET)
return ParseIntelOffsetOfOperator();
// Parse optional Size directive. // Parse optional Size directive.
unsigned Size; unsigned Size;
if (ParseIntelMemoryOperandSize(Size)) if (ParseIntelMemoryOperandSize(Size))
return nullptr; return nullptr;
bool PtrInOperand = bool(Size); bool PtrInOperand = bool(Size);
Start = Tok.getLoc(); Start = Tok.getLoc();
Show All 31 Linesstd::unique_ptr<X86Operand> X86AsmParser::ParseIntelOperand() {
const MCExpr *ImmDisp = MCConstantExpr::create(Imm, getContext()); const MCExpr *ImmDisp = MCConstantExpr::create(Imm, getContext());
if (Disp && Imm) if (Disp && Imm)
Disp = MCBinaryExpr::createAdd(Disp, ImmDisp, getContext()); Disp = MCBinaryExpr::createAdd(Disp, ImmDisp, getContext());
if (!Disp) if (!Disp)
Disp = ImmDisp; Disp = ImmDisp;
// RegNo != 0 specifies a valid segment register, // RegNo != 0 specifies a valid segment register,
// and we are parsing a segment override // and we are parsing a segment override
if (!SM.isMemExpr() && !RegNo) if (!SM.isMemExpr() && !RegNo) {
if (isParsingInlineAsm() && SM.isOffsetOperator()) {
const InlineAsmIdentifierInfo Info = SM.getIdentifierInfo();
if (Info.isKind(InlineAsmIdentifierInfo::IK_Var)) {
// Disp includes the address of a variable; make sure this is recorded
// for later handling.
return X86Operand::CreateImm(Disp, Start, End, SM.getSymName(),
Info.Var.Decl, Info.Var.IsGlobalLV);
}
}
return X86Operand::CreateImm(Disp, Start, End); return X86Operand::CreateImm(Disp, Start, End);
}
StringRef ErrMsg; StringRef ErrMsg;
unsigned BaseReg = SM.getBaseReg(); unsigned BaseReg = SM.getBaseReg();
unsigned IndexReg = SM.getIndexReg(); unsigned IndexReg = SM.getIndexReg();
unsigned Scale = SM.getScale(); unsigned Scale = SM.getScale();
if (Scale == 0 && BaseReg != X86::ESP && BaseReg != X86::RSP && if (Scale == 0 && BaseReg != X86::ESP && BaseReg != X86::RSP &&
(IndexReg == X86::ESP || IndexReg == X86::RSP)) (IndexReg == X86::ESP || IndexReg == X86::RSP))
▲ Show 20 Lines • Show All 1,984 Lines • Show Last 20 Lines

llvm/lib/Target/X86/AsmParser/X86Operand.h

Show First 20 Lines • Show All 47 Lines • ▼ Show 20 Linesstruct X86Operand final : public MCParsedAsmOperand {
}; };
struct PrefOp { struct PrefOp {
unsigned Prefixes; unsigned Prefixes;
}; };
struct ImmOp { struct ImmOp {
const MCExpr *Val; const MCExpr *Val;
bool LocalRef;
}; };
struct MemOp { struct MemOp {
unsigned SegReg; unsigned SegReg;
const MCExpr *Disp; const MCExpr *Disp;
unsigned BaseReg; unsigned BaseReg;
unsigned IndexReg; unsigned IndexReg;
unsigned Scale; unsigned Scale;
▲ Show 20 Lines • Show All 210 Lines • ▼ Show 20 Lines bool isImmUnsignedi8() const {
if (!isImm()) return false; if (!isImm()) return false;
// If this isn't a constant expr, just assume it fits and let relaxation // If this isn't a constant expr, just assume it fits and let relaxation
// handle it. // handle it.
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
if (!CE) return true; if (!CE) return true;
return isImmUnsignedi8Value(CE->getValue()); return isImmUnsignedi8Value(CE->getValue());
} }
bool isOffsetOf() const override { bool isOffsetOfLocal() const override { return isImm() && Imm.LocalRef; }
return OffsetOfLoc.getPointer();
}
bool needAddressOf() const override { bool needAddressOf() const override { return AddressOf; }
return AddressOf;
}
bool isCallOperand() const override { return CallOperand; } bool isCallOperand() const override { return CallOperand; }
void setCallOperand(bool IsCallOperand) { CallOperand = IsCallOperand; } void setCallOperand(bool IsCallOperand) { CallOperand = IsCallOperand; }
bool isMem() const override { return Kind == Memory; } bool isMem() const override { return Kind == Memory; }
bool isMemUnsized() const { bool isMemUnsized() const {
return Kind == Memory && Mem.Size == 0; return Kind == Memory && Mem.Size == 0;
} }
▲ Show 20 Lines • Show All 315 Lines • ▼ Show 20 Linesstruct X86Operand final : public MCParsedAsmOperand {
static std::unique_ptr<X86Operand> static std::unique_ptr<X86Operand>
CreatePrefix(unsigned Prefixes, SMLoc StartLoc, SMLoc EndLoc) { CreatePrefix(unsigned Prefixes, SMLoc StartLoc, SMLoc EndLoc) {
auto Res = std::make_unique<X86Operand>(Prefix, StartLoc, EndLoc); auto Res = std::make_unique<X86Operand>(Prefix, StartLoc, EndLoc);
Res->Pref.Prefixes = Prefixes; Res->Pref.Prefixes = Prefixes;
return Res; return Res;
} }
static std::unique_ptr<X86Operand> CreateImm(const MCExpr *Val, static std::unique_ptr<X86Operand> CreateImm(const MCExpr *Val,
SMLoc StartLoc, SMLoc EndLoc) { SMLoc StartLoc, SMLoc EndLoc,
StringRef SymName = StringRef(),
void *OpDecl = nullptr,
bool GlobalRef = true) {
auto Res = std::make_unique<X86Operand>(Immediate, StartLoc, EndLoc); auto Res = std::make_unique<X86Operand>(Immediate, StartLoc, EndLoc);
Res->Imm.Val = Val; Res->Imm.Val = Val;
Res->Imm.LocalRef = !GlobalRef;
Res->SymName = SymName;
Res->OpDecl = OpDecl;
Res->AddressOf = true;
return Res; return Res;
} }
/// Create an absolute memory operand. /// Create an absolute memory operand.
static std::unique_ptr<X86Operand> static std::unique_ptr<X86Operand>
CreateMem(unsigned ModeSize, const MCExpr *Disp, SMLoc StartLoc, SMLoc EndLoc, CreateMem(unsigned ModeSize, const MCExpr *Disp, SMLoc StartLoc, SMLoc EndLoc,
unsigned Size = 0, StringRef SymName = StringRef(), unsigned Size = 0, StringRef SymName = StringRef(),
void *OpDecl = nullptr, unsigned FrontendSize = 0) { void *OpDecl = nullptr, unsigned FrontendSize = 0) {
▲ Show 20 Lines • Show All 47 Lines • Show Last 20 Lines

llvm/lib/Target/X86/X86AsmPrinter.cpp

Show First 20 Lines • Show All 214 Lines • ▼ Show 20 Linesvoid X86AsmPrinter::PrintOperand(const MachineInstr *MI, unsigned OpNo,
case MachineOperand::MO_Immediate: case MachineOperand::MO_Immediate:
if (IsATT) if (IsATT)
O << '$'; O << '$';
O << MO.getImm(); O << MO.getImm();
return; return;
case MachineOperand::MO_ConstantPoolIndex: case MachineOperand::MO_ConstantPoolIndex:
case MachineOperand::MO_GlobalAddress: { case MachineOperand::MO_GlobalAddress: {
if (IsATT) switch (MI->getInlineAsmDialect()) {
default:
llvm_unreachable("unknown assembly dialect!");
case InlineAsm::AD_ATT:
O << '$'; O << '$';
break;
case InlineAsm::AD_Intel:
O << "offset ";
break;
}
PrintSymbolOperand(MO, O); PrintSymbolOperand(MO, O);
break; break;
} }
case MachineOperand::MO_BlockAddress: { case MachineOperand::MO_BlockAddress: {
MCSymbol *Sym = GetBlockAddressSymbol(MO.getBlockAddress()); MCSymbol *Sym = GetBlockAddressSymbol(MO.getBlockAddress());
Sym->print(O, MAI); Sym->print(O, MAI);
break; break;
} }
▲ Show 20 Lines • Show All 517 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/ms-inline-asm.ll

Show First 20 Lines • Show All 86 Lines • ▼ Show 20 Linesentry:
%res = alloca i32*, align 4 %res = alloca i32*, align 4
call void asm sideeffect inteldialect "lea edi, dword ptr $0", "*m,~{edi},~{dirflag},~{fpsr},~{flags}"([2 x i32]* @results) nounwind call void asm sideeffect inteldialect "lea edi, dword ptr $0", "*m,~{edi},~{dirflag},~{fpsr},~{flags}"([2 x i32]* @results) nounwind
call void asm sideeffect inteldialect "mov dword ptr $0, edi", "=*m,~{dirflag},~{fpsr},~{flags}"(i32** %res) nounwind call void asm sideeffect inteldialect "mov dword ptr $0, edi", "=*m,~{dirflag},~{fpsr},~{flags}"(i32** %res) nounwind
%0 = load i32*, i32** %res, align 4 %0 = load i32*, i32** %res, align 4
ret i32* %0 ret i32* %0
; CHECK-LABEL: t30: ; CHECK-LABEL: t30:
; CHECK: {{## InlineAsm Start|#APP}} ; CHECK: {{## InlineAsm Start|#APP}}
; CHECK: .intel_syntax ; CHECK: .intel_syntax
; CHECK: lea edi, dword ptr [{{_?}}results] ; CHECK: lea edi, dword ptr [offset {{_?}}results]
; CHECK: .att_syntax ; CHECK: .att_syntax
; CHECK: {{## InlineAsm End|#NO_APP}} ; CHECK: {{## InlineAsm End|#NO_APP}}
; CHECK: {{## InlineAsm Start|#APP}} ; CHECK: {{## InlineAsm Start|#APP}}
; CHECK: .intel_syntax ; CHECK: .intel_syntax
; CHECK: mov dword ptr [esp], edi ; CHECK: mov dword ptr [esp], edi
; CHECK: .att_syntax ; CHECK: .att_syntax
; CHECK: {{## InlineAsm End|#NO_APP}} ; CHECK: {{## InlineAsm End|#NO_APP}}
; CHECK: movl (%esp), %eax ; CHECK: movl (%esp), %eax
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llvm/test/CodeGen/X86/offset-operator.ll

  • This file was added.
; RUN: llc -mtriple=x86_64-unknown-linux-gnu -x86-asm-syntax=intel -relocation-model=static < %s | FileCheck %s
; Test we are emitting the 'offset' operator upon an immediate reference of a label:
; The emitted 'att-equivalent' of this one is "movl $.L.str, %eax"
@.str = private unnamed_addr constant [1 x i8] zeroinitializer, align 1
define i8* @test_offset_operator() {
; CHECK-LABEL: test_offset_operator:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mov eax, offset .L.str
; CHECK-NEXT: ret
entry:
ret i8* getelementptr inbounds ([1 x i8], [1 x i8]* @.str, i64 0, i64 0)
}

llvm/test/MC/X86/pr32530.s

  • This file was added.
// RUN: llvm-mc -triple x86_64-unknown-unknown -x86-asm-syntax=intel %s | FileCheck %s
.text
// CHECK: movq $msg, %rsi
// CHECK: movq $msg+314159, %rax
// CHECK: movq $msg-89793, msg-6535(%rax,%rbx,2)
mov rsi, offset msg
mov rax, offset "msg" + 314159
mov qword ptr [rax + 2*rbx + offset msg - 6535], offset msg - 89793
.data
msg:
.ascii "Hello, world!\n"