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Differential D72417

[ms] [X86] Use "P" modifier on all branch-target operands in inline X86 assembly.
ClosedPublic

Authored by epastor on Jan 8 2020, 2:50 PM.

Details

Reviewers
thakis
rnk
Commits
rG1c545f6dbcbb: [ms] [X86] Use "P" modifier on all branch-target operands in inline X86…
Summary

Extend D71677 to apply to all branch-target operands, rather than special-casing call instructions.

Also add a regression test for llvm.org/PR44272, since this finishes fixing it.

Diff Detail

Event Timeline

epastor created this revision.Jan 8 2020, 2:50 PM
Herald added projects: Restricted Project, Restricted Project. · View Herald TranscriptJan 8 2020, 2:50 PM
Herald added subscribers: llvm-commits, cfe-commits, hiraditya. · View Herald Transcript
epastor edited the summary of this revision. (Show Details)Jan 8 2020, 2:55 PM
epastor added reviewers: thakis, rnk.
merge_guards_bot added a subscriber: merge_guards_bot.Jan 8 2020, 3:05 PM

Unit tests: pass. 61323 tests passed, 0 failed and 736 were skipped.

clang-tidy: fail. Please fix clang-tidy findings.

clang-format: fail. Please format your changes with clang-format by running git-clang-format HEAD^ or applying this patch.

Build artifacts: diff.json, clang-tidy.txt, clang-format.patch, CMakeCache.txt, console-log.txt, test-results.xml

Harbormaster failed remote builds in B43534: Diff 236912!Jan 8 2020, 3:10 PM
thakis accepted this revision.Jan 8 2020, 6:30 PM
This revision is now accepted and ready to land.Jan 8 2020, 6:30 PM
Closed by commit rG1c545f6dbcbb: [ms] [X86] Use "P" modifier on all branch-target operands in inline X86… (authored by epastor). · Explain WhyJan 9 2020, 12:07 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
clang/
test/
CodeGen/
14 lines
llvm/
include/
llvm/
MC/
10 lines
MCParser/
4 lines
lib/
MC/
MCParser/
2 lines
Target/
X86/
AsmParser/
9 lines
3 lines
23 lines
46 lines
utils/
TableGen/
5 lines
82 lines

Diff 237151

clang/test/CodeGen/ms-inline-asm-64.c

Show First 20 Lines • Show All 52 Lines • ▼ Show 20 Linesint t4() {
return foo.b; return foo.b;
// CHECK: t4 // CHECK: t4
// CHECK: call void asm sideeffect inteldialect // CHECK: call void asm sideeffect inteldialect
// CHECK-SAME: lea ebx, $0 // CHECK-SAME: lea ebx, $0
// CHECK-SAME: mov eax, [ebx] // CHECK-SAME: mov eax, [ebx]
// CHECK-SAME: mov [ebx + $$4], ecx // CHECK-SAME: mov [ebx + $$4], ecx
// CHECK-SAME: "*m,~{eax},~{ebx},~{dirflag},~{fpsr},~{flags}"(%struct.t3_type* %{{.*}}) // CHECK-SAME: "*m,~{eax},~{ebx},~{dirflag},~{fpsr},~{flags}"(%struct.t3_type* %{{.*}})
} }
void bar() {}
void t5() {
__asm {
call bar
jmp bar
}
// CHECK: t5
// CHECK: call void asm sideeffect inteldialect
// CHECK-SAME: call qword ptr ${0:P}
// CHECK-SAME: jmp qword ptr ${1:P}
// CHECK-SAME: "*m,*m,~{dirflag},~{fpsr},~{flags}"(void (...)* bitcast (void ()* @bar to void (...)*), void (...)* bitcast (void ()* @bar to void (...)*))
}

llvm/include/llvm/MC/MCInstrDesc.h

Show All 31 Lines
enum OperandConstraint { enum OperandConstraint {
TIED_TO = 0, // Must be allocated the same register as. TIED_TO = 0, // Must be allocated the same register as.
EARLY_CLOBBER // Operand is an early clobber register operand EARLY_CLOBBER // Operand is an early clobber register operand
}; };
/// These are flags set on operands, but should be considered /// These are flags set on operands, but should be considered
/// private, all access should go through the MCOperandInfo accessors. /// private, all access should go through the MCOperandInfo accessors.
/// See the accessors for a description of what these are. /// See the accessors for a description of what these are.
enum OperandFlags { LookupPtrRegClass = 0, Predicate, OptionalDef }; enum OperandFlags {
LookupPtrRegClass = 0,
Predicate,
OptionalDef,
BranchTarget
};
/// Operands are tagged with one of the values of this enum. /// Operands are tagged with one of the values of this enum.
enum OperandType { enum OperandType {
OPERAND_UNKNOWN = 0, OPERAND_UNKNOWN = 0,
OPERAND_IMMEDIATE = 1, OPERAND_IMMEDIATE = 1,
OPERAND_REGISTER = 2, OPERAND_REGISTER = 2,
OPERAND_MEMORY = 3, OPERAND_MEMORY = 3,
OPERAND_PCREL = 4, OPERAND_PCREL = 4,
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Linespublic:
/// Set if this is one of the operands that made up of the predicate /// Set if this is one of the operands that made up of the predicate
/// operand that controls an isPredicable() instruction. /// operand that controls an isPredicable() instruction.
bool isPredicate() const { return Flags & (1 << MCOI::Predicate); } bool isPredicate() const { return Flags & (1 << MCOI::Predicate); }
/// Set if this operand is a optional def. /// Set if this operand is a optional def.
bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); } bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); }
/// Set if this operand is a branch target.
bool isBranchTarget() const { return Flags & (1 << MCOI::BranchTarget); }
bool isGenericType() const { bool isGenericType() const {
return OperandType >= MCOI::OPERAND_FIRST_GENERIC && return OperandType >= MCOI::OPERAND_FIRST_GENERIC &&
OperandType <= MCOI::OPERAND_LAST_GENERIC; OperandType <= MCOI::OPERAND_LAST_GENERIC;
} }
unsigned getGenericTypeIndex() const { unsigned getGenericTypeIndex() const {
assert(isGenericType() && "non-generic types don't have an index"); assert(isGenericType() && "non-generic types don't have an index");
return OperandType - MCOI::OPERAND_FIRST_GENERIC; return OperandType - MCOI::OPERAND_FIRST_GENERIC;
▲ Show 20 Lines • Show All 519 Lines • Show Last 20 Lines

llvm/include/llvm/MC/MCParser/MCParsedAsmOperand.h

Show First 20 Lines • Show All 65 Lines • ▼ Show 20 Linespublic:
virtual SMLoc getStartLoc() const = 0; virtual SMLoc getStartLoc() const = 0;
/// getEndLoc - Get the location of the last token of this operand. /// getEndLoc - Get the location of the last token of this operand.
virtual SMLoc getEndLoc() const = 0; virtual SMLoc getEndLoc() const = 0;
/// needAddressOf - Do we need to emit code to get the address of the /// needAddressOf - Do we need to emit code to get the address of the
/// variable/label? Only valid when parsing MS-style inline assembly. /// variable/label? Only valid when parsing MS-style inline assembly.
virtual bool needAddressOf() const { return false; } virtual bool needAddressOf() const { return false; }
/// isCallOperand - Is this an operand of an inline-assembly call instruction?
/// Only valid when parsing MS-style inline assembly.
virtual bool isCallOperand() const { return false; }
/// isOffsetOfLocal - Do we need to emit code to get the offset of the local /// isOffsetOfLocal - Do we need to emit code to get the offset of the local
/// variable, rather than its value? Only valid when parsing MS-style inline /// variable, rather than its value? Only valid when parsing MS-style inline
/// assembly. /// assembly.
virtual bool isOffsetOfLocal() const { return false; } virtual bool isOffsetOfLocal() const { return false; }
/// getOffsetOfLoc - Get the location of the offset operator. /// getOffsetOfLoc - Get the location of the offset operator.
virtual SMLoc getOffsetOfLoc() const { return SMLoc(); } virtual SMLoc getOffsetOfLoc() const { return SMLoc(); }
Show All 18 Lines

llvm/lib/MC/MCParser/AsmParser.cpp

Show First 20 Lines • Show All 5,839 Lines • ▼ Show 20 Lines for (unsigned i = 1, e = Info.ParsedOperands.size(); i != e; ++i) {
OutputDecls.push_back(OpDecl); OutputDecls.push_back(OpDecl);
OutputDeclsAddressOf.push_back(Operand.needAddressOf()); OutputDeclsAddressOf.push_back(Operand.needAddressOf());
OutputConstraints.push_back(("=" + Constraint).str()); OutputConstraints.push_back(("=" + Constraint).str());
AsmStrRewrites.emplace_back(AOK_Output, Start, SymName.size()); AsmStrRewrites.emplace_back(AOK_Output, Start, SymName.size());
} else { } else {
InputDecls.push_back(OpDecl); InputDecls.push_back(OpDecl);
InputDeclsAddressOf.push_back(Operand.needAddressOf()); InputDeclsAddressOf.push_back(Operand.needAddressOf());
InputConstraints.push_back(Constraint.str()); InputConstraints.push_back(Constraint.str());
if (Operand.isCallOperand()) if (Desc.OpInfo[i - 1].isBranchTarget())
AsmStrRewrites.emplace_back(AOK_CallInput, Start, SymName.size()); AsmStrRewrites.emplace_back(AOK_CallInput, Start, SymName.size());
else else
AsmStrRewrites.emplace_back(AOK_Input, Start, SymName.size()); AsmStrRewrites.emplace_back(AOK_Input, Start, SymName.size());
} }
} }
// Consider implicit defs to be clobbers. Think of cpuid and push. // Consider implicit defs to be clobbers. Think of cpuid and push.
ArrayRef<MCPhysReg> ImpDefs(Desc.getImplicitDefs(), ArrayRef<MCPhysReg> ImpDefs(Desc.getImplicitDefs(),
▲ Show 20 Lines • Show All 256 Lines • Show Last 20 Lines

llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp

Show First 20 Lines • Show All 2,918 Lines • ▼ Show 20 Lines if ((Name == "xlat" || Name == "xlatb") && Operands.size() == 2) {
if (Op1.isMem8()) { if (Op1.isMem8()) {
Warning(Op1.getStartLoc(), "memory operand is only for determining the " Warning(Op1.getStartLoc(), "memory operand is only for determining the "
"size, (R|E)BX will be used for the location"); "size, (R|E)BX will be used for the location");
Operands.pop_back(); Operands.pop_back();
static_cast<X86Operand &>(*Operands[0]).setTokenValue("xlatb"); static_cast<X86Operand &>(*Operands[0]).setTokenValue("xlatb");
} }
} }
// Mark the operands of a call instruction. These need to be handled
// differently when referenced in MS-style inline assembly.
if (Name.startswith("call") || Name.startswith("lcall")) {
for (size_t i = 1; i < Operands.size(); ++i) {
X86Operand &Op = static_cast<X86Operand &>(*Operands[i]);
Op.setCallOperand(true);
}
}
if (Flags) if (Flags)
Operands.push_back(X86Operand::CreatePrefix(Flags, NameLoc, NameLoc)); Operands.push_back(X86Operand::CreatePrefix(Flags, NameLoc, NameLoc));
return false; return false;
} }
bool X86AsmParser::processInstruction(MCInst &Inst, const OperandVector &Ops) { bool X86AsmParser::processInstruction(MCInst &Inst, const OperandVector &Ops) {
const MCRegisterInfo *MRI = getContext().getRegisterInfo(); const MCRegisterInfo *MRI = getContext().getRegisterInfo();
▲ Show 20 Lines • Show All 1,016 Lines • Show Last 20 Lines

llvm/lib/Target/X86/AsmParser/X86Operand.h

Show First 20 Lines • Show All 278 Lines • ▼ Show 20 Lines bool isImmUnsignedi8() const {
if (!CE) return true; if (!CE) return true;
return isImmUnsignedi8Value(CE->getValue()); return isImmUnsignedi8Value(CE->getValue());
} }
bool isOffsetOfLocal() const override { return isImm() && Imm.LocalRef; } bool isOffsetOfLocal() const override { return isImm() && Imm.LocalRef; }
bool needAddressOf() const override { return AddressOf; } bool needAddressOf() const override { return AddressOf; }
bool isCallOperand() const override { return CallOperand; }
void setCallOperand(bool IsCallOperand) { CallOperand = IsCallOperand; }
bool isMem() const override { return Kind == Memory; } bool isMem() const override { return Kind == Memory; }
bool isMemUnsized() const { bool isMemUnsized() const {
return Kind == Memory && Mem.Size == 0; return Kind == Memory && Mem.Size == 0;
} }
bool isMem8() const { bool isMem8() const {
return Kind == Memory && (!Mem.Size || Mem.Size == 8); return Kind == Memory && (!Mem.Size || Mem.Size == 8);
} }
bool isMem16() const { bool isMem16() const {
▲ Show 20 Lines • Show All 384 Lines • Show Last 20 Lines

llvm/lib/Target/X86/X86InstrControl.td

Show First 20 Lines • Show All 214 Lines • ▼ Show 20 Lines
// //
let isCall = 1 in let isCall = 1 in
// All calls clobber the non-callee saved registers. ESP is marked as // All calls clobber the non-callee saved registers. ESP is marked as
// a use to prevent stack-pointer assignments that appear immediately // a use to prevent stack-pointer assignments that appear immediately
// before calls from potentially appearing dead. Uses for argument // before calls from potentially appearing dead. Uses for argument
// registers are added manually. // registers are added manually.
let Uses = [ESP, SSP] in { let Uses = [ESP, SSP] in {
def CALLpcrel32 : Ii32PCRel<0xE8, RawFrm, def CALLpcrel32 : Ii32PCRel<0xE8, RawFrm,
(outs), (ins i32imm_pcrel:$dst), (outs), (ins i32imm_brtarget:$dst),
"call{l}\t$dst", []>, OpSize32, "call{l}\t$dst", []>, OpSize32,
Requires<[Not64BitMode]>, Sched<[WriteJump]>; Requires<[Not64BitMode]>, Sched<[WriteJump]>;
let hasSideEffects = 0 in let hasSideEffects = 0 in
def CALLpcrel16 : Ii16PCRel<0xE8, RawFrm, def CALLpcrel16 : Ii16PCRel<0xE8, RawFrm,
(outs), (ins i16imm_pcrel:$dst), (outs), (ins i16imm_brtarget:$dst),
"call{w}\t$dst", []>, OpSize16, "call{w}\t$dst", []>, OpSize16,
Sched<[WriteJump]>; Sched<[WriteJump]>;
def CALL16r : I<0xFF, MRM2r, (outs), (ins GR16:$dst), def CALL16r : I<0xFF, MRM2r, (outs), (ins GR16:$dst),
"call{w}\t{*}$dst", [(X86call GR16:$dst)]>, "call{w}\t{*}$dst", [(X86call GR16:$dst)]>,
OpSize16, Requires<[Not64BitMode]>, Sched<[WriteJump]>; OpSize16, Requires<[Not64BitMode]>, Sched<[WriteJump]>;
def CALL16m : I<0xFF, MRM2m, (outs), (ins i16mem:$dst), def CALL16m : I<0xFF, MRM2m, (outs), (ins i16mem:$dst),
"call{w}\t{*}$dst", [(X86call (loadi16 addr:$dst))]>, "call{w}\t{*}$dst", [(X86call (loadi16 addr:$dst))]>,
OpSize16, Requires<[Not64BitMode,FavorMemIndirectCall]>, OpSize16, Requires<[Not64BitMode,FavorMemIndirectCall]>,
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines let Uses = [ESP, SSP] in {
def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaquemem:$dst), def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaquemem:$dst),
"{l}call{l}\t{*}$dst", []>, OpSize32, Sched<[WriteJumpLd]>; "{l}call{l}\t{*}$dst", []>, OpSize32, Sched<[WriteJumpLd]>;
} }
// Tail call stuff. // Tail call stuff.
let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
isCodeGenOnly = 1, Uses = [ESP, SSP] in { isCodeGenOnly = 1, Uses = [ESP, SSP] in {
def TCRETURNdi : PseudoI<(outs), (ins i32imm_pcrel:$dst, i32imm:$offset), def TCRETURNdi : PseudoI<(outs), (ins i32imm_brtarget:$dst, i32imm:$offset),
[]>, Sched<[WriteJump]>, NotMemoryFoldable; []>, Sched<[WriteJump]>, NotMemoryFoldable;
def TCRETURNri : PseudoI<(outs), (ins ptr_rc_tailcall:$dst, i32imm:$offset), def TCRETURNri : PseudoI<(outs), (ins ptr_rc_tailcall:$dst, i32imm:$offset),
[]>, Sched<[WriteJump]>, NotMemoryFoldable; []>, Sched<[WriteJump]>, NotMemoryFoldable;
let mayLoad = 1 in let mayLoad = 1 in
def TCRETURNmi : PseudoI<(outs), (ins i32mem_TC:$dst, i32imm:$offset), def TCRETURNmi : PseudoI<(outs), (ins i32mem_TC:$dst, i32imm:$offset),
[]>, Sched<[WriteJumpLd]>; []>, Sched<[WriteJumpLd]>;
def TAILJMPd : PseudoI<(outs), (ins i32imm_pcrel:$dst), def TAILJMPd : PseudoI<(outs), (ins i32imm_brtarget:$dst),
[]>, Sched<[WriteJump]>; []>, Sched<[WriteJump]>;
def TAILJMPr : PseudoI<(outs), (ins ptr_rc_tailcall:$dst), def TAILJMPr : PseudoI<(outs), (ins ptr_rc_tailcall:$dst),
[]>, Sched<[WriteJump]>; []>, Sched<[WriteJump]>;
let mayLoad = 1 in let mayLoad = 1 in
def TAILJMPm : PseudoI<(outs), (ins i32mem_TC:$dst), def TAILJMPm : PseudoI<(outs), (ins i32mem_TC:$dst),
[]>, Sched<[WriteJumpLd]>; []>, Sched<[WriteJumpLd]>;
} }
// Conditional tail calls are similar to the above, but they are branches // Conditional tail calls are similar to the above, but they are branches
// rather than barriers, and they use EFLAGS. // rather than barriers, and they use EFLAGS.
let isCall = 1, isTerminator = 1, isReturn = 1, isBranch = 1, let isCall = 1, isTerminator = 1, isReturn = 1, isBranch = 1,
isCodeGenOnly = 1, SchedRW = [WriteJump] in isCodeGenOnly = 1, SchedRW = [WriteJump] in
let Uses = [ESP, EFLAGS, SSP] in { let Uses = [ESP, EFLAGS, SSP] in {
def TCRETURNdicc : PseudoI<(outs), def TCRETURNdicc : PseudoI<(outs),
(ins i32imm_pcrel:$dst, i32imm:$offset, i32imm:$cond), []>; (ins i32imm_brtarget:$dst, i32imm:$offset, i32imm:$cond),
[]>;
// This gets substituted to a conditional jump instruction in MC lowering. // This gets substituted to a conditional jump instruction in MC lowering.
def TAILJMPd_CC : PseudoI<(outs), (ins i32imm_pcrel:$dst, i32imm:$cond), []>; def TAILJMPd_CC : PseudoI<(outs), (ins i32imm_brtarget:$dst, i32imm:$cond), []>;
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Call Instructions... // Call Instructions...
// //
// RSP is marked as a use to prevent stack-pointer assignments that appear // RSP is marked as a use to prevent stack-pointer assignments that appear
// immediately before calls from potentially appearing dead. Uses for argument // immediately before calls from potentially appearing dead. Uses for argument
// registers are added manually. // registers are added manually.
let isCall = 1, Uses = [RSP, SSP], SchedRW = [WriteJump] in { let isCall = 1, Uses = [RSP, SSP], SchedRW = [WriteJump] in {
// NOTE: this pattern doesn't match "X86call imm", because we do not know // NOTE: this pattern doesn't match "X86call imm", because we do not know
// that the offset between an arbitrary immediate and the call will fit in // that the offset between an arbitrary immediate and the call will fit in
// the 32-bit pcrel field that we have. // the 32-bit pcrel field that we have.
def CALL64pcrel32 : Ii32PCRel<0xE8, RawFrm, def CALL64pcrel32 : Ii32PCRel<0xE8, RawFrm,
(outs), (ins i64i32imm_pcrel:$dst), (outs), (ins i64i32imm_brtarget:$dst),
"call{q}\t$dst", []>, OpSize32, "call{q}\t$dst", []>, OpSize32,
Requires<[In64BitMode]>; Requires<[In64BitMode]>;
def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst), def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst),
"call{q}\t{*}$dst", [(X86call GR64:$dst)]>, "call{q}\t{*}$dst", [(X86call GR64:$dst)]>,
Requires<[In64BitMode,NotUseRetpolineIndirectCalls]>; Requires<[In64BitMode,NotUseRetpolineIndirectCalls]>;
def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst), def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst),
"call{q}\t{*}$dst", [(X86call (loadi64 addr:$dst))]>, "call{q}\t{*}$dst", [(X86call (loadi64 addr:$dst))]>,
Requires<[In64BitMode,FavorMemIndirectCall, Requires<[In64BitMode,FavorMemIndirectCall,
Show All 12 Lineslet isCall = 1, Uses = [RSP, SSP], SchedRW = [WriteJump] in {
def FARCALL64 : RI<0xFF, MRM3m, (outs), (ins opaquemem:$dst), def FARCALL64 : RI<0xFF, MRM3m, (outs), (ins opaquemem:$dst),
"lcall{q}\t{*}$dst", []>; "lcall{q}\t{*}$dst", []>;
} }
let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
isCodeGenOnly = 1, Uses = [RSP, SSP] in { isCodeGenOnly = 1, Uses = [RSP, SSP] in {
def TCRETURNdi64 : PseudoI<(outs), def TCRETURNdi64 : PseudoI<(outs),
(ins i64i32imm_pcrel:$dst, i32imm:$offset), (ins i64i32imm_brtarget:$dst, i32imm:$offset),
[]>, Sched<[WriteJump]>; []>, Sched<[WriteJump]>;
def TCRETURNri64 : PseudoI<(outs), def TCRETURNri64 : PseudoI<(outs),
(ins ptr_rc_tailcall:$dst, i32imm:$offset), (ins ptr_rc_tailcall:$dst, i32imm:$offset),
[]>, Sched<[WriteJump]>, NotMemoryFoldable; []>, Sched<[WriteJump]>, NotMemoryFoldable;
let mayLoad = 1 in let mayLoad = 1 in
def TCRETURNmi64 : PseudoI<(outs), def TCRETURNmi64 : PseudoI<(outs),
(ins i64mem_TC:$dst, i32imm:$offset), (ins i64mem_TC:$dst, i32imm:$offset),
[]>, Sched<[WriteJumpLd]>, NotMemoryFoldable; []>, Sched<[WriteJumpLd]>, NotMemoryFoldable;
def TAILJMPd64 : PseudoI<(outs), (ins i64i32imm_pcrel:$dst), def TAILJMPd64 : PseudoI<(outs), (ins i64i32imm_brtarget:$dst),
[]>, Sched<[WriteJump]>; []>, Sched<[WriteJump]>;
def TAILJMPr64 : PseudoI<(outs), (ins ptr_rc_tailcall:$dst), def TAILJMPr64 : PseudoI<(outs), (ins ptr_rc_tailcall:$dst),
[]>, Sched<[WriteJump]>; []>, Sched<[WriteJump]>;
let mayLoad = 1 in let mayLoad = 1 in
def TAILJMPm64 : PseudoI<(outs), (ins i64mem_TC:$dst), def TAILJMPm64 : PseudoI<(outs), (ins i64mem_TC:$dst),
[]>, Sched<[WriteJumpLd]>; []>, Sched<[WriteJumpLd]>;
Show All 31 Lines
} }
// Conditional tail calls are similar to the above, but they are branches // Conditional tail calls are similar to the above, but they are branches
// rather than barriers, and they use EFLAGS. // rather than barriers, and they use EFLAGS.
let isCall = 1, isTerminator = 1, isReturn = 1, isBranch = 1, let isCall = 1, isTerminator = 1, isReturn = 1, isBranch = 1,
isCodeGenOnly = 1, SchedRW = [WriteJump] in isCodeGenOnly = 1, SchedRW = [WriteJump] in
let Uses = [RSP, EFLAGS, SSP] in { let Uses = [RSP, EFLAGS, SSP] in {
def TCRETURNdi64cc : PseudoI<(outs), def TCRETURNdi64cc : PseudoI<(outs),
(ins i64i32imm_pcrel:$dst, i32imm:$offset, (ins i64i32imm_brtarget:$dst, i32imm:$offset,
i32imm:$cond), []>; i32imm:$cond), []>;
// This gets substituted to a conditional jump instruction in MC lowering. // This gets substituted to a conditional jump instruction in MC lowering.
def TAILJMPd64_CC : PseudoI<(outs), def TAILJMPd64_CC : PseudoI<(outs),
(ins i64i32imm_pcrel:$dst, i32imm:$cond), []>; (ins i64i32imm_brtarget:$dst, i32imm:$cond), []>;
} }

llvm/lib/Target/X86/X86InstrInfo.td

Show First 20 Lines • Show All 448 Lines • ▼ Show 20 Lines
def i64mem_TC : Operand<i64> { def i64mem_TC : Operand<i64> {
let PrintMethod = "printqwordmem"; let PrintMethod = "printqwordmem";
let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, let MIOperandInfo = (ops ptr_rc_tailcall, i8imm,
ptr_rc_tailcall, i32imm, SEGMENT_REG); ptr_rc_tailcall, i32imm, SEGMENT_REG);
let ParserMatchClass = X86Mem64AsmOperand; let ParserMatchClass = X86Mem64AsmOperand;
let OperandType = "OPERAND_MEMORY"; let OperandType = "OPERAND_MEMORY";
} }
let OperandType = "OPERAND_PCREL",
ParserMatchClass = X86AbsMemAsmOperand,
PrintMethod = "printPCRelImm" in {
def i32imm_pcrel : Operand<i32>;
def i16imm_pcrel : Operand<i16>;
// Branch targets have OtherVT type and print as pc-relative values.
def brtarget : Operand<OtherVT>;
def brtarget8 : Operand<OtherVT>;
}
// Special parser to detect 16-bit mode to select 16-bit displacement. // Special parser to detect 16-bit mode to select 16-bit displacement.
def X86AbsMem16AsmOperand : AsmOperandClass { def X86AbsMem16AsmOperand : AsmOperandClass {
let Name = "AbsMem16"; let Name = "AbsMem16";
let RenderMethod = "addAbsMemOperands"; let RenderMethod = "addAbsMemOperands";
let SuperClasses = [X86AbsMemAsmOperand]; let SuperClasses = [X86AbsMemAsmOperand];
} }
// Branch targets have OtherVT type and print as pc-relative values. // Branch targets print as pc-relative values.
let OperandType = "OPERAND_PCREL", class BranchTargetOperand<ValueType ty> : Operand<ty> {
PrintMethod = "printPCRelImm" in { let OperandType = "OPERAND_PCREL";
let ParserMatchClass = X86AbsMem16AsmOperand in let PrintMethod = "printPCRelImm";
def brtarget16 : Operand<OtherVT>; let ParserMatchClass = X86AbsMemAsmOperand;
let ParserMatchClass = X86AbsMemAsmOperand in
def brtarget32 : Operand<OtherVT>;
} }
def i32imm_brtarget : BranchTargetOperand<i32>;
def i16imm_brtarget : BranchTargetOperand<i16>;
// 64-bits but only 32 bits are significant, and those bits are treated as being
// pc relative.
def i64i32imm_brtarget : BranchTargetOperand<i64>;
def brtarget : BranchTargetOperand<OtherVT>;
def brtarget8 : BranchTargetOperand<OtherVT>;
def brtarget16 : BranchTargetOperand<OtherVT> {
let ParserMatchClass = X86AbsMem16AsmOperand;
}
def brtarget32 : BranchTargetOperand<OtherVT>;
let RenderMethod = "addSrcIdxOperands" in { let RenderMethod = "addSrcIdxOperands" in {
def X86SrcIdx8Operand : AsmOperandClass { def X86SrcIdx8Operand : AsmOperandClass {
let Name = "SrcIdx8"; let Name = "SrcIdx8";
let SuperClasses = [X86Mem8AsmOperand]; let SuperClasses = [X86Mem8AsmOperand];
} }
def X86SrcIdx16Operand : AsmOperandClass { def X86SrcIdx16Operand : AsmOperandClass {
let Name = "SrcIdx16"; let Name = "SrcIdx16";
let SuperClasses = [X86Mem16AsmOperand]; let SuperClasses = [X86Mem16AsmOperand];
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// 64-bit immediate but only 8-bits are significant and they are unsigned. // 64-bit immediate but only 8-bits are significant and they are unsigned.
// Used by BT instructions. // Used by BT instructions.
def i64u8imm : Operand<i64> { def i64u8imm : Operand<i64> {
let PrintMethod = "printU8Imm"; let PrintMethod = "printU8Imm";
let ParserMatchClass = ImmUnsignedi8AsmOperand; let ParserMatchClass = ImmUnsignedi8AsmOperand;
let OperandType = "OPERAND_IMMEDIATE"; let OperandType = "OPERAND_IMMEDIATE";
} }
// 64-bits but only 32 bits are significant, and those bits are treated as being
// pc relative.
def i64i32imm_pcrel : Operand<i64> {
let PrintMethod = "printPCRelImm";
let ParserMatchClass = X86AbsMemAsmOperand;
let OperandType = "OPERAND_PCREL";
}
def lea64_32mem : Operand<i32> { def lea64_32mem : Operand<i32> {
let PrintMethod = "printanymem"; let PrintMethod = "printanymem";
let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, SEGMENT_REG); let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, SEGMENT_REG);
let ParserMatchClass = X86MemAsmOperand; let ParserMatchClass = X86MemAsmOperand;
} }
// Memory operands that use 64-bit pointers in both ILP32 and LP64. // Memory operands that use 64-bit pointers in both ILP32 and LP64.
def lea64mem : Operand<i64> { def lea64mem : Operand<i64> {
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llvm/utils/TableGen/InstrInfoEmitter.cpp

Show First 20 Lines • Show All 158 Lines • ▼ Show 20 Lines for (unsigned j = 0, e = OperandList.size(); j != e; ++j) {
if (Op.Rec->isSubClassOf("PredicateOp")) if (Op.Rec->isSubClassOf("PredicateOp"))
Res += "|(1<<MCOI::Predicate)"; Res += "|(1<<MCOI::Predicate)";
// Optional def operands. Check to see if the original unexpanded operand // Optional def operands. Check to see if the original unexpanded operand
// was of type OptionalDefOperand. // was of type OptionalDefOperand.
if (Op.Rec->isSubClassOf("OptionalDefOperand")) if (Op.Rec->isSubClassOf("OptionalDefOperand"))
Res += "|(1<<MCOI::OptionalDef)"; Res += "|(1<<MCOI::OptionalDef)";
// Branch target operands. Check to see if the original unexpanded
// operand was of type BranchTargetOperand.
if (Op.Rec->isSubClassOf("BranchTargetOperand"))
Res += "|(1<<MCOI::BranchTarget)";
// Fill in operand type. // Fill in operand type.
Res += ", "; Res += ", ";
assert(!Op.OperandType.empty() && "Invalid operand type."); assert(!Op.OperandType.empty() && "Invalid operand type.");
Res += Op.OperandType; Res += Op.OperandType;
// Fill in constraint info. // Fill in constraint info.
Res += ", "; Res += ", ";
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llvm/utils/TableGen/X86RecognizableInstr.cpp

Show First 20 Lines • Show All 873 Lines • ▼ Show 20 LinesOperandType RecognizableInstr::typeFromString(const std::string &s,
TYPE("FR32X", TYPE_XMM) TYPE("FR32X", TYPE_XMM)
TYPE("f32mem", TYPE_M) TYPE("f32mem", TYPE_M)
TYPE("ssmem", TYPE_M) TYPE("ssmem", TYPE_M)
TYPE("RST", TYPE_ST) TYPE("RST", TYPE_ST)
TYPE("RSTi", TYPE_ST) TYPE("RSTi", TYPE_ST)
TYPE("i128mem", TYPE_M) TYPE("i128mem", TYPE_M)
TYPE("i256mem", TYPE_M) TYPE("i256mem", TYPE_M)
TYPE("i512mem", TYPE_M) TYPE("i512mem", TYPE_M)
TYPE("i64i32imm_pcrel", TYPE_REL) TYPE("i64i32imm_brtarget", TYPE_REL)
TYPE("i16imm_pcrel", TYPE_REL) TYPE("i16imm_brtarget", TYPE_REL)
TYPE("i32imm_pcrel", TYPE_REL) TYPE("i32imm_brtarget", TYPE_REL)
TYPE("ccode", TYPE_IMM) TYPE("ccode", TYPE_IMM)
TYPE("AVX512RC", TYPE_IMM) TYPE("AVX512RC", TYPE_IMM)
TYPE("brtarget32", TYPE_REL) TYPE("brtarget32", TYPE_REL)
TYPE("brtarget16", TYPE_REL) TYPE("brtarget16", TYPE_REL)
TYPE("brtarget8", TYPE_REL) TYPE("brtarget8", TYPE_REL)
TYPE("f80mem", TYPE_M) TYPE("f80mem", TYPE_M)
TYPE("lea64_32mem", TYPE_M) TYPE("lea64_32mem", TYPE_M)
TYPE("lea64mem", TYPE_M) TYPE("lea64mem", TYPE_M)
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} }
OperandEncoding OperandEncoding
RecognizableInstr::relocationEncodingFromString(const std::string &s, RecognizableInstr::relocationEncodingFromString(const std::string &s,
uint8_t OpSize) { uint8_t OpSize) {
if(OpSize != X86Local::OpSize16) { if(OpSize != X86Local::OpSize16) {
// For instructions without an OpSize prefix, a declared 16-bit register or // For instructions without an OpSize prefix, a declared 16-bit register or
// immediate encoding is special. // immediate encoding is special.
ENCODING("i16imm", ENCODING_IW) ENCODING("i16imm", ENCODING_IW)
} }
ENCODING("i16imm", ENCODING_Iv) ENCODING("i16imm", ENCODING_Iv)
ENCODING("i16i8imm", ENCODING_IB) ENCODING("i16i8imm", ENCODING_IB)
ENCODING("i32imm", ENCODING_Iv) ENCODING("i32imm", ENCODING_Iv)
ENCODING("i32i8imm", ENCODING_IB) ENCODING("i32i8imm", ENCODING_IB)
ENCODING("i64i32imm", ENCODING_ID) ENCODING("i64i32imm", ENCODING_ID)
ENCODING("i64i8imm", ENCODING_IB) ENCODING("i64i8imm", ENCODING_IB)
ENCODING("i8imm", ENCODING_IB) ENCODING("i8imm", ENCODING_IB)
ENCODING("u8imm", ENCODING_IB) ENCODING("u8imm", ENCODING_IB)
ENCODING("i16u8imm", ENCODING_IB) ENCODING("i16u8imm", ENCODING_IB)
ENCODING("i32u8imm", ENCODING_IB) ENCODING("i32u8imm", ENCODING_IB)
ENCODING("i64u8imm", ENCODING_IB) ENCODING("i64u8imm", ENCODING_IB)
ENCODING("i64i32imm_pcrel", ENCODING_ID) ENCODING("i64i32imm_brtarget", ENCODING_ID)
ENCODING("i16imm_pcrel", ENCODING_IW) ENCODING("i16imm_brtarget", ENCODING_IW)
ENCODING("i32imm_pcrel", ENCODING_ID) ENCODING("i32imm_brtarget", ENCODING_ID)
ENCODING("brtarget32", ENCODING_ID) ENCODING("brtarget32", ENCODING_ID)
ENCODING("brtarget16", ENCODING_IW) ENCODING("brtarget16", ENCODING_IW)
ENCODING("brtarget8", ENCODING_IB) ENCODING("brtarget8", ENCODING_IB)
ENCODING("i64imm", ENCODING_IO) ENCODING("i64imm", ENCODING_IO)
ENCODING("offset16_8", ENCODING_Ia) ENCODING("offset16_8", ENCODING_Ia)
ENCODING("offset16_16", ENCODING_Ia) ENCODING("offset16_16", ENCODING_Ia)
ENCODING("offset16_32", ENCODING_Ia) ENCODING("offset16_32", ENCODING_Ia)
ENCODING("offset32_8", ENCODING_Ia) ENCODING("offset32_8", ENCODING_Ia)
ENCODING("offset32_16", ENCODING_Ia) ENCODING("offset32_16", ENCODING_Ia)
ENCODING("offset32_32", ENCODING_Ia) ENCODING("offset32_32", ENCODING_Ia)
ENCODING("offset32_64", ENCODING_Ia) ENCODING("offset32_64", ENCODING_Ia)
ENCODING("offset64_8", ENCODING_Ia) ENCODING("offset64_8", ENCODING_Ia)
ENCODING("offset64_16", ENCODING_Ia) ENCODING("offset64_16", ENCODING_Ia)
ENCODING("offset64_32", ENCODING_Ia) ENCODING("offset64_32", ENCODING_Ia)
ENCODING("offset64_64", ENCODING_Ia) ENCODING("offset64_64", ENCODING_Ia)
ENCODING("srcidx8", ENCODING_SI) ENCODING("srcidx8", ENCODING_SI)
ENCODING("srcidx16", ENCODING_SI) ENCODING("srcidx16", ENCODING_SI)
ENCODING("srcidx32", ENCODING_SI) ENCODING("srcidx32", ENCODING_SI)
ENCODING("srcidx64", ENCODING_SI) ENCODING("srcidx64", ENCODING_SI)
ENCODING("dstidx8", ENCODING_DI) ENCODING("dstidx8", ENCODING_DI)
ENCODING("dstidx16", ENCODING_DI) ENCODING("dstidx16", ENCODING_DI)
ENCODING("dstidx32", ENCODING_DI) ENCODING("dstidx32", ENCODING_DI)
ENCODING("dstidx64", ENCODING_DI) ENCODING("dstidx64", ENCODING_DI)
errs() << "Unhandled relocation encoding " << s << "\n"; errs() << "Unhandled relocation encoding " << s << "\n";
llvm_unreachable("Unhandled relocation encoding"); llvm_unreachable("Unhandled relocation encoding");
} }
OperandEncoding OperandEncoding
RecognizableInstr::opcodeModifierEncodingFromString(const std::string &s, RecognizableInstr::opcodeModifierEncodingFromString(const std::string &s,
uint8_t OpSize) { uint8_t OpSize) {
ENCODING("GR32", ENCODING_Rv) ENCODING("GR32", ENCODING_Rv)
ENCODING("GR64", ENCODING_RO) ENCODING("GR64", ENCODING_RO)
ENCODING("GR16", ENCODING_Rv) ENCODING("GR16", ENCODING_Rv)
ENCODING("GR8", ENCODING_RB) ENCODING("GR8", ENCODING_RB)
ENCODING("ccode", ENCODING_CC) ENCODING("ccode", ENCODING_CC)
errs() << "Unhandled opcode modifier encoding " << s << "\n"; errs() << "Unhandled opcode modifier encoding " << s << "\n";
llvm_unreachable("Unhandled opcode modifier encoding"); llvm_unreachable("Unhandled opcode modifier encoding");
} }
#undef ENCODING #undef ENCODING