-
Notifications
You must be signed in to change notification settings - Fork 12.7k
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
ScheduleDAG.cpp patch: error message more meaningful. #1556
Comments
Scott, You have a "dump" in there so that entire block needs to be debug guarded. #ifndef NDEBUG including the VRC definition .. its only needed in debug builds. |
Hmm .. actually, you're replacing the assert .. its fine :) |
One would think the author of the build system would have this stuff straight. #ifndef NDEBUG Sorry for the confusion. Better still, figure out how to handle the VRC != RC case :) |
Updated (with NDEBUG) patch |
I applied your patch. Please make sure not to use tabs though :) -Chris |
Extended Description
Small patch to make tracking down (self-inflicted) bugs easier when the
scheduler barfs. The assert() wasn't really helpful at all. At least this patch
tells you which instruction and operand to go look at.
(Note: In the end, yes, it was my fault, but this patch actually helped.)
Index: lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
--- lib/CodeGen/SelectionDAG/ScheduleDAG.cpp (revision 522)
+++ lib/CodeGen/SelectionDAG/ScheduleDAG.cpp (working copy)
@@ -301,9 +301,20 @@
if (II) {
const TargetRegisterClass *RC =
getInstrOperandRegClass(MRI, TII, II, IIOpNum);
} else if (ConstantSDNode *C =
dyn_cast(Op)) {
The text was updated successfully, but these errors were encountered: