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This allows a shift of 32. On PPC, this will produce the same value as shifting by 31. On X86, this
produces the same value as shifting by 0. This is the switch in question:
Sorry for the breakage. I wasn't be able to test things on PowerPC and I cannot
understand PowerPC assembler yet :) Chris, could you please verify?
I also fixed some "latent" bug, which can be only triggered on 64-bit platforms.
Jeff, could you please check, whether this fixes some bugs for you or not.
Extended Description
Shift/And lowering is producing invalid code. I'm not sure but I think that this is the issue:
LBB1_2: ;cond_next67
lbz r2, 0(r29)
li r3, 1
cmplwi cr0, r2, 32
slw r3, r3, r2
bgt cr0, LBB1_4 ;bb101.preheader
This allows a shift of 32. On PPC, this will produce the same value as shifting by 31. On X86, this
produces the same value as shifting by 0. This is the switch in question:
That said, it is an impressive code size win :)
-Chris
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