The cpy instruction is only defined in ARMv6.

A possible solution for this bug is to emit 'mov' instead of 'cpy'. The problem
is that the mov sets the flags and I'm afraid that it can break something in
rematerialization. 

Cheng?

If all mov are changed to cpy, the backend emits wrong code:

        cmp r5, r2
        mov r0, r5
        bgt .LBB1_6     @cond_true99

The proper fix is to model CC as explicit register(s). Then you can fix the
scheduler and register allocator, 
i.e. any machine instruction level module that insert move, load, store ops, to
insert instructions at the 
right spot to avoid clobbering the CC registers. Not only is it useful for this
bug, it also makes it easier to 
implement a pass that optimize away cmp / test, etc.

Perhaps it's ok to just add instruction properties that tells us whether a
instruction sets / reads CC. It's 
hard to say.

removing me from cc list.  I am aka unassignedbugs@nondot, so I'm getting two
copies :)

FWIW, I think that it is about time we start modelling CC's correctly.  This
would require, at the minimum, 
adding a new physreg to represent the CC, then marking each instruction that
sets it as clobbering it.