-
Notifications
You must be signed in to change notification settings - Fork 12.9k
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
Add support to LLVM for alignment specification of memory objects #772
Comments
I smell more bytecode changes coming ... :) Instead of continuing to modify the bytecode format piecemeal, lets acknowledge I'd like to see comments on what bytecode formats are needed to support this bug. |
For the instructions, it shouldn't require any changes: we'll just encode 1 Setting an alignment on a global var/function will require more info: We will -Chris |
Okay, so the bit in the global vars steals away from the maximum number of types Reid. |
Sounds good to me. Define all ones as an extension field (if it's set, there is -Chris |
I'm not grokking this:
What "ones" ?
What's a vpr? |
Sorry. If the type is ((2^24)-1) (all 24 1's), it should be an extension field.
a benchmark. I meant to type vbr :) -chris |
A note: when this PR is implemented, this patch should be reverted: -Chris |
alignment support has been added to globals, functions and allocations. It is currently missing from load/ |
The assembly format for alignment attributes on load/stores will be an optional %tmp5 = load i32* %tmp4, align 4 |
Sounds great to me! |
The bytecode representation for aligned loads and stores will use pseudo ops for 'attributed' load/store |
Support for align attributes on load/store instructions has been added. |
great! should this be closed? |
I'll assume that by 'add support to LLVM' in the bug title it means add to the LLVM language and |
sounds right to me |
It appears that vector loads don't currently have a subclass of SDNode, which is where alignment |
Hmm. Upon further inspection, it appears that ISD::VLOAD gets lowered later in legalization of the DAG, |
The patches have been fixed and reapplied. |
…e one in dialect (llvm#772) This PR remove the header `CIR/CodeGen/CallingConv.h` and migrates all `::cir::CallingConv` stuff to `::mlir::cir::CallingConv` in `CIRGenTypes` and `CIRGenFunctionInfo`. In TargetLowering library, LowerTypes and LowerFunctionInfo basically have the same clangCallConvToLLVMCallConv stuff. The CC there is the LLVM one. But those changes are not included because of the potential conflicts. We can still easily switch to the dialect when it's needed.
…e one in dialect (llvm#772) This PR remove the header `CIR/CodeGen/CallingConv.h` and migrates all `::cir::CallingConv` stuff to `::mlir::cir::CallingConv` in `CIRGenTypes` and `CIRGenFunctionInfo`. In TargetLowering library, LowerTypes and LowerFunctionInfo basically have the same clangCallConvToLLVMCallConv stuff. The CC there is the LLVM one. But those changes are not included because of the potential conflicts. We can still easily switch to the dialect when it's needed.
Extended Description
Also, the alloca and malloc instructions should take an optional alignment
argument, and GlobalValues should allow an explicit alignment constraint to be set.
For malloc, this allows us to represent valloc and memalign directly
in LLVM. For alloca, it allows us to support the alignment attributes in the
GCC front-end directly. Global variables should also be extended to support
alignment attributes. This will be required for vectorization work.
If an alignment is specified as zero, the default, then that means we should
follow the target alignment settings. This should be by far the most common
setting, so we should not even bother encoding this argument into the bytecode
file unless it is nonzero.
This was originally a comment in Bug 122, but it should be it's own bug, so I'm
splitting it out.
-Chris
The text was updated successfully, but these errors were encountered: