Bug 566 – Memory Mapped I/O Intrinsics do not fence memory

Bug 566 - Memory Mapped I/O Intrinsics do not fence memory

Summary:

Memory Mapped I/O Intrinsics do not fence memory

Status:	RESOLVED WONTFIX

Product:	libraries
Classification:	Unclassified
Component:	Backend: X86
Version:	1.5
Platform:	PC Linux

Importance:	P normal
Assigned To:	Unassigned LLVM Bugs

URL:
Keywords:

Depends on:
Blocks:
	Show dependency tree / graph

Reported:	2005-05-18 10:29 CDT by John T. Criswell
Modified:	2010-03-06 14:00 CST (History)
CC List:	1 user (show)

See Also:

Attachments
Add an attachment (proposed patch, testcase, etc.)

Note You need to log in before you can comment on or make changes to this bug.

Description John T. Criswell 2005-05-18 10:29:51 CDT

According to the design in the language reference manual, the LLVM readio and
writeio intrinsics should strongly order I/O memory accesses.

However, the current implementation lowers these intrinsics to volatile loads
and stores on ix86.  These loads and stores may or may not be properly ordered,
depending on the processor on which they run.

The correct solution is not obvious.  Certain fencing instructions are not found
on older Pentium processors, and we will need a general fencing model for SMP
systems anyway.  Such a design has not been discussed, though, as far as I know.

Comment 1 Chris Lattner 2006-03-02 18:17:28 CST

This bug is obsolete.