36 static const unsigned PCRelFlagVal =
42 AArch64AsmBackend(
const Target &
T,
const Triple &TT,
bool IsLittleEndian)
59 {
"fixup_aarch64_pcrel_adr_imm21", 0, 32, PCRelFlagVal},
60 {
"fixup_aarch64_pcrel_adrp_imm21", 0, 32, PCRelFlagVal},
61 {
"fixup_aarch64_add_imm12", 10, 12, 0},
62 {
"fixup_aarch64_ldst_imm12_scale1", 10, 12, 0},
63 {
"fixup_aarch64_ldst_imm12_scale2", 10, 12, 0},
64 {
"fixup_aarch64_ldst_imm12_scale4", 10, 12, 0},
65 {
"fixup_aarch64_ldst_imm12_scale8", 10, 12, 0},
66 {
"fixup_aarch64_ldst_imm12_scale16", 10, 12, 0},
67 {
"fixup_aarch64_ldr_pcrel_imm19", 5, 19, PCRelFlagVal},
68 {
"fixup_aarch64_movw", 5, 16, 0},
69 {
"fixup_aarch64_pcrel_branch14", 5, 14, PCRelFlagVal},
70 {
"fixup_aarch64_pcrel_branch16", 5, 16, PCRelFlagVal},
71 {
"fixup_aarch64_pcrel_branch19", 5, 19, PCRelFlagVal},
72 {
"fixup_aarch64_pcrel_branch26", 0, 26, PCRelFlagVal},
73 {
"fixup_aarch64_pcrel_call26", 0, 26, PCRelFlagVal}};
101 unsigned getFixupKindContainereSizeInBytes(
unsigned Kind)
const;
150 unsigned lo2 =
Value & 0x3;
151 unsigned hi19 = (
Value & 0x1ffffc) >> 2;
152 return (hi19 << 5) | (lo2 << 29);
157 const Triple &TheTriple,
bool IsResolved) {
158 int64_t SignedValue =
static_cast<int64_t
>(
Value);
159 switch (
Fixup.getTargetKind()) {
163 if (!isInt<21>(SignedValue))
169 if (!isInt<21>(SignedValue))
177 if (!isInt<21>(SignedValue))
182 return (
Value >> 2) & 0x7ffff;
188 if (!isUInt<12>(
Value))
195 if (!isUInt<13>(
Value))
204 if (!isUInt<14>(
Value))
213 if (!isUInt<15>(
Value))
222 if (!isUInt<16>(
Value))
234 if (SignedValue > 0xFFFF || SignedValue < -0xFFFF)
236 "fixup value out of range [-0xFFFF, 0xFFFF]");
240 SignedValue = ~SignedValue;
246 "relocation for a thread-local variable points to an "
264 SignedValue = SignedValue >> 16;
267 SignedValue = SignedValue >> 32;
270 SignedValue = SignedValue >> 48;
298 if (SignedValue > 0xFFFF || SignedValue < -0xFFFF)
303 SignedValue = ~SignedValue;
306 else if (
Value > 0xFFFF) {
313 if (!isInt<16>(SignedValue))
318 return (
Value >> 2) & 0x3fff;
321 SignedValue = -SignedValue;
324 if (SignedValue < 0 || SignedValue > ((1 << 18) - 1))
329 return (
Value >> 2) & 0xffff;
336 "cannot perform a PC-relative fixup with a non-zero "
340 if (!isInt<28>(SignedValue))
345 return (
Value >> 2) & 0x3ffffff;
356std::optional<MCFixupKind>
362#define ELF_RELOC(X, Y) .Case(#X, Y)
363#include "llvm/BinaryFormat/ELFRelocs/AArch64.def"
365 .
Case(
"BFD_RELOC_NONE", ELF::R_AARCH64_NONE)
366 .
Case(
"BFD_RELOC_16", ELF::R_AARCH64_ABS16)
367 .
Case(
"BFD_RELOC_32", ELF::R_AARCH64_ABS32)
368 .
Case(
"BFD_RELOC_64", ELF::R_AARCH64_ABS64)
377unsigned AArch64AsmBackend::getFixupKindContainereSizeInBytes(
unsigned Kind)
const {
422 if (SymLoc == AArch64AuthMCExpr::VK_AUTH ||
423 SymLoc == AArch64AuthMCExpr::VK_AUTHADDR) {
425 const auto *Expr = cast<AArch64AuthMCExpr>(
Fixup.getValue());
428 (
uint64_t(Expr->hasAddressDiversity()) << 63);
440 int64_t SignedValue =
static_cast<int64_t
>(
Value);
448 assert(
Offset + NumBytes <= Data.size() &&
"Invalid fixup offset!");
451 unsigned FulleSizeInBytes = getFixupKindContainereSizeInBytes(
Fixup.getKind());
455 if (FulleSizeInBytes == 0) {
457 for (
unsigned i = 0; i != NumBytes; ++i) {
458 Data[
Offset + i] |= uint8_t((
Value >> (i * 8)) & 0xff);
462 assert((
Offset + FulleSizeInBytes) <= Data.size() &&
"Invalid fixup size!");
463 assert(NumBytes <= FulleSizeInBytes &&
"Invalid fixup size!");
464 for (
unsigned i = 0; i != NumBytes; ++i) {
465 unsigned Idx = FulleSizeInBytes - 1 - i;
479 Data[
Offset + 3] &= ~(1 << 6);
481 Data[
Offset + 3] |= (1 << 6);
485bool AArch64AsmBackend::fixupNeedsRelaxation(
const MCFixup &
Fixup,
493 return int64_t(
Value) != int64_t(int8_t(
Value));
496void AArch64AsmBackend::relaxInstruction(
MCInst &Inst,
510 for (
uint64_t i = 0; i != Count; ++i)
511 OS.
write(
"\x1f\x20\x03\xd5", 4);
515bool AArch64AsmBackend::shouldForceRelocation(
const MCAssembler &Asm,
549 UNWIND_ARM64_MODE_FRAMELESS = 0x02000000,
556 UNWIND_ARM64_MODE_DWARF = 0x03000000,
564 UNWIND_ARM64_MODE_FRAME = 0x04000000,
567 UNWIND_ARM64_FRAME_X19_X20_PAIR = 0x00000001,
568 UNWIND_ARM64_FRAME_X21_X22_PAIR = 0x00000002,
569 UNWIND_ARM64_FRAME_X23_X24_PAIR = 0x00000004,
570 UNWIND_ARM64_FRAME_X25_X26_PAIR = 0x00000008,
571 UNWIND_ARM64_FRAME_X27_X28_PAIR = 0x00000010,
572 UNWIND_ARM64_FRAME_D8_D9_PAIR = 0x00000100,
573 UNWIND_ARM64_FRAME_D10_D11_PAIR = 0x00000200,
574 UNWIND_ARM64_FRAME_D12_D13_PAIR = 0x00000400,
575 UNWIND_ARM64_FRAME_D14_D15_PAIR = 0x00000800
581class DarwinAArch64AsmBackend :
public AArch64AsmBackend {
588 return (StackSize / 16) << 12;
596 std::unique_ptr<MCObjectTargetWriter>
597 createObjectTargetWriter()
const override {
609 return CU::UNWIND_ARM64_MODE_FRAMELESS;
610 if (!isDarwinCanonicalPersonality(FI->
Personality) &&
612 return CU::UNWIND_ARM64_MODE_DWARF;
615 unsigned StackSize = 0;
619 for (
size_t i = 0, e = Instrs.
size(); i != e; ++i) {
625 return CU::UNWIND_ARM64_MODE_DWARF;
635 if (XReg != AArch64::FP)
636 return CU::UNWIND_ARM64_MODE_DWARF;
639 return CU::UNWIND_ARM64_MODE_DWARF;
643 return CU::UNWIND_ARM64_MODE_DWARF;
646 return CU::UNWIND_ARM64_MODE_DWARF;
649 return CU::UNWIND_ARM64_MODE_DWARF;
658 if (LRReg != AArch64::LR || FPReg != AArch64::FP)
659 return CU::UNWIND_ARM64_MODE_DWARF;
662 CompactUnwindEncoding |= CU::UNWIND_ARM64_MODE_FRAME;
668 return CU::UNWIND_ARM64_MODE_DWARF;
677 return CU::UNWIND_ARM64_MODE_DWARF;
679 if (CurOffset != 0 && Inst.
getOffset() != CurOffset - 8)
680 return CU::UNWIND_ARM64_MODE_DWARF;
685 return CU::UNWIND_ARM64_MODE_DWARF;
689 return CU::UNWIND_ARM64_MODE_DWARF;
703 if (Reg1 == AArch64::X19 && Reg2 == AArch64::X20 &&
704 (CompactUnwindEncoding & 0xF1E) == 0)
705 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X19_X20_PAIR;
706 else if (Reg1 == AArch64::X21 && Reg2 == AArch64::X22 &&
707 (CompactUnwindEncoding & 0xF1C) == 0)
708 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X21_X22_PAIR;
709 else if (Reg1 == AArch64::X23 && Reg2 == AArch64::X24 &&
710 (CompactUnwindEncoding & 0xF18) == 0)
711 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X23_X24_PAIR;
712 else if (Reg1 == AArch64::X25 && Reg2 == AArch64::X26 &&
713 (CompactUnwindEncoding & 0xF10) == 0)
714 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X25_X26_PAIR;
715 else if (Reg1 == AArch64::X27 && Reg2 == AArch64::X28 &&
716 (CompactUnwindEncoding & 0xF00) == 0)
717 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X27_X28_PAIR;
726 if (Reg1 == AArch64::D8 && Reg2 == AArch64::D9 &&
727 (CompactUnwindEncoding & 0xE00) == 0)
728 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_D8_D9_PAIR;
729 else if (Reg1 == AArch64::D10 && Reg2 == AArch64::D11 &&
730 (CompactUnwindEncoding & 0xC00) == 0)
731 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_D10_D11_PAIR;
732 else if (Reg1 == AArch64::D12 && Reg2 == AArch64::D13 &&
733 (CompactUnwindEncoding & 0x800) == 0)
734 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_D12_D13_PAIR;
735 else if (Reg1 == AArch64::D14 && Reg2 == AArch64::D15)
736 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_D14_D15_PAIR;
739 return CU::UNWIND_ARM64_MODE_DWARF;
750 if (StackSize > 65520)
751 return CU::UNWIND_ARM64_MODE_DWARF;
753 CompactUnwindEncoding |= CU::UNWIND_ARM64_MODE_FRAMELESS;
754 CompactUnwindEncoding |= encodeStackAdjustment(StackSize);
757 return CompactUnwindEncoding;
765class ELFAArch64AsmBackend :
public AArch64AsmBackend {
770 ELFAArch64AsmBackend(
const Target &
T,
const Triple &TT, uint8_t OSABI,
771 bool IsLittleEndian,
bool IsILP32)
772 : AArch64AsmBackend(
T,
TT, IsLittleEndian), OSABI(OSABI),
775 std::unique_ptr<MCObjectTargetWriter>
776 createObjectTargetWriter()
const override {
784class COFFAArch64AsmBackend :
public AArch64AsmBackend {
786 COFFAArch64AsmBackend(
const Target &
T,
const Triple &TheTriple)
787 : AArch64AsmBackend(
T, TheTriple,
true) {}
789 std::unique_ptr<MCObjectTargetWriter>
790 createObjectTargetWriter()
const override {
802 return new DarwinAArch64AsmBackend(
T, TheTriple,
MRI);
806 return new COFFAArch64AsmBackend(
T, TheTriple);
812 return new ELFAArch64AsmBackend(
T, TheTriple, OSABI,
true,
822 "Big endian is only supported for ELF targets!");
825 return new ELFAArch64AsmBackend(
T, TheTriple, OSABI,
false,
unsigned const MachineRegisterInfo * MRI
static unsigned AdrImmBits(unsigned Value)
static unsigned getFixupKindNumBytes(unsigned Kind)
The number of bytes the fixup may change.
static uint64_t adjustFixupValue(const MCFixup &Fixup, const MCValue &Target, uint64_t Value, MCContext &Ctx, const Triple &TheTriple, bool IsResolved)
Analysis containing CSE Info
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
static RegisterPass< DebugifyFunctionPass > DF("debugify-function", "Attach debug info to a function")
PowerPC TLS Dynamic Call Fixup
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static VariantKind getSymbolLoc(VariantKind Kind)
static VariantKind getAddressFrag(VariantKind Kind)
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
bool empty() const
empty - Check if the array is empty.
Generic interface to target specific assembler backends.
virtual bool writeNopData(raw_ostream &OS, uint64_t Count, const MCSubtargetInfo *STI) const =0
Write an (optimal) nop sequence of Count bytes to the given output.
virtual void relaxInstruction(MCInst &Inst, const MCSubtargetInfo &STI) const
Relax the instruction in the given fragment to the next wider instruction.
virtual bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, const MCRelaxableFragment *DF, const MCAsmLayout &Layout) const =0
Simple predicate for targets where !Resolved implies requiring relaxation.
virtual bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, const MCSubtargetInfo *STI)
Hook to check if a relocation is needed for some target specific reason.
virtual unsigned getNumFixupKinds() const =0
Get the number of target specific fixup kinds.
virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const
Get information on a fixup kind.
virtual std::optional< MCFixupKind > getFixupKind(StringRef Name) const
Map a relocation name used in .reloc to a fixup kind.
virtual void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, MutableArrayRef< char > Data, uint64_t Value, bool IsResolved, const MCSubtargetInfo *STI) const =0
Apply the Value for given Fixup into the provided data fragment, at the offset specified by the fixup...
Encapsulates the layout of an assembly file at a particular point in time.
unsigned getRegister() const
OpType getOperation() const
Context object for machine code objects.
bool emitCompactUnwindNonCanonical() const
void reportError(SMLoc L, const Twine &Msg)
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Instances of this class represent a single low-level machine instruction.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
Generic base class for all target subtargets.
const Triple & getTargetTriple() const
This represents an "assembler immediate".
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
StringRef - Represent a constant reference to a string, i.e.
A switch()-like statement whose cases are string literals.
StringSwitch & Case(StringLiteral S, T Value)
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
OSType getOS() const
Get the parsed operating system type of this triple.
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
EnvironmentType getEnvironment() const
Get the parsed environment type of this triple.
bool isArch32Bit() const
Test whether the architecture is 32-bit.
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
The instances of the Type class are immutable: once they are created, they are never changed.
LLVM Value Representation.
This class implements an extremely fast bulk output stream that can only output to a stream.
raw_ostream & write_zeros(unsigned NumZeros)
write_zeros - Insert 'NumZeros' nulls.
raw_ostream & write(unsigned char C)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
CompactUnwindEncodings
Compact unwind encoding values.
@ fixup_aarch64_pcrel_branch16
@ fixup_aarch64_ldst_imm12_scale4
@ fixup_aarch64_pcrel_call26
@ fixup_aarch64_pcrel_branch26
@ fixup_aarch64_pcrel_branch19
@ fixup_aarch64_ldr_pcrel_imm19
@ fixup_aarch64_pcrel_adr_imm21
@ fixup_aarch64_pcrel_branch14
@ fixup_aarch64_ldst_imm12_scale2
@ fixup_aarch64_ldst_imm12_scale16
@ fixup_aarch64_pcrel_adrp_imm21
@ fixup_aarch64_add_imm12
@ fixup_aarch64_ldst_imm12_scale8
@ fixup_aarch64_ldst_imm12_scale1
Expected< uint32_t > getCPUSubType(const Triple &T)
Expected< uint32_t > getCPUType(const Triple &T)
This is an optimization pass for GlobalISel generic memory operations.
std::unique_ptr< MCObjectTargetWriter > createAArch64WinCOFFObjectWriter(const Triple &TheTriple)
static unsigned getXRegFromWReg(unsigned Reg)
MCAsmBackend * createAArch64leAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
static unsigned getDRegFromBReg(unsigned Reg)
MCFixupKind
Extensible enumeration to represent the type of a fixup.
@ FK_SecRel_2
A two-byte section relative fixup.
@ FirstLiteralRelocationKind
The range [FirstLiteralRelocationKind, MaxTargetFixupKind) is used for relocations coming from ....
@ FK_Data_8
A eight-byte fixup.
@ FK_Data_1
A one-byte fixup.
@ FK_Data_4
A four-byte fixup.
@ FK_SecRel_4
A four-byte section relative fixup.
@ FK_Data_2
A two-byte fixup.
void cantFail(Error Err, const char *Msg=nullptr)
Report a fatal error if Err is a failure value.
std::unique_ptr< MCObjectTargetWriter > createAArch64MachObjectWriter(uint32_t CPUType, uint32_t CPUSubtype, bool IsILP32)
MCAsmBackend * createAArch64beAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
std::unique_ptr< MCObjectTargetWriter > createAArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32)
const MCSymbol * Personality
std::vector< MCCFIInstruction > Instructions
Target independent information on a fixup kind.
@ FKF_IsAlignedDownTo32Bits
Should this fixup kind force a 4-byte aligned effective PC value?
@ FKF_IsPCRel
Is this fixup kind PCrelative? This is used by the assembler backend to evaluate fixup values in a ta...