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AArch64BaseInfo.h
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00001 //===-- AArch64BaseInfo.h - Top level definitions for AArch64 ---*- C++ -*-===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file contains small standalone helper functions and enum definitions for
00011 // the AArch64 target useful for the compiler back-end and the MC libraries.
00012 // As such, it deliberately does not include references to LLVM core
00013 // code gen types, passes, etc..
00014 //
00015 //===----------------------------------------------------------------------===//
00016 
00017 #ifndef LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H
00018 #define LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H
00019 
00020 // FIXME: Is it easiest to fix this layering violation by moving the .inc
00021 // #includes from AArch64MCTargetDesc.h to here?
00022 #include "MCTargetDesc/AArch64MCTargetDesc.h" // For AArch64::X0 and friends.
00023 #include "llvm/ADT/STLExtras.h"
00024 #include "llvm/ADT/StringSwitch.h"
00025 #include "llvm/Support/ErrorHandling.h"
00026 
00027 namespace llvm {
00028 
00029 inline static unsigned getWRegFromXReg(unsigned Reg) {
00030   switch (Reg) {
00031   case AArch64::X0: return AArch64::W0;
00032   case AArch64::X1: return AArch64::W1;
00033   case AArch64::X2: return AArch64::W2;
00034   case AArch64::X3: return AArch64::W3;
00035   case AArch64::X4: return AArch64::W4;
00036   case AArch64::X5: return AArch64::W5;
00037   case AArch64::X6: return AArch64::W6;
00038   case AArch64::X7: return AArch64::W7;
00039   case AArch64::X8: return AArch64::W8;
00040   case AArch64::X9: return AArch64::W9;
00041   case AArch64::X10: return AArch64::W10;
00042   case AArch64::X11: return AArch64::W11;
00043   case AArch64::X12: return AArch64::W12;
00044   case AArch64::X13: return AArch64::W13;
00045   case AArch64::X14: return AArch64::W14;
00046   case AArch64::X15: return AArch64::W15;
00047   case AArch64::X16: return AArch64::W16;
00048   case AArch64::X17: return AArch64::W17;
00049   case AArch64::X18: return AArch64::W18;
00050   case AArch64::X19: return AArch64::W19;
00051   case AArch64::X20: return AArch64::W20;
00052   case AArch64::X21: return AArch64::W21;
00053   case AArch64::X22: return AArch64::W22;
00054   case AArch64::X23: return AArch64::W23;
00055   case AArch64::X24: return AArch64::W24;
00056   case AArch64::X25: return AArch64::W25;
00057   case AArch64::X26: return AArch64::W26;
00058   case AArch64::X27: return AArch64::W27;
00059   case AArch64::X28: return AArch64::W28;
00060   case AArch64::FP: return AArch64::W29;
00061   case AArch64::LR: return AArch64::W30;
00062   case AArch64::SP: return AArch64::WSP;
00063   case AArch64::XZR: return AArch64::WZR;
00064   }
00065   // For anything else, return it unchanged.
00066   return Reg;
00067 }
00068 
00069 inline static unsigned getXRegFromWReg(unsigned Reg) {
00070   switch (Reg) {
00071   case AArch64::W0: return AArch64::X0;
00072   case AArch64::W1: return AArch64::X1;
00073   case AArch64::W2: return AArch64::X2;
00074   case AArch64::W3: return AArch64::X3;
00075   case AArch64::W4: return AArch64::X4;
00076   case AArch64::W5: return AArch64::X5;
00077   case AArch64::W6: return AArch64::X6;
00078   case AArch64::W7: return AArch64::X7;
00079   case AArch64::W8: return AArch64::X8;
00080   case AArch64::W9: return AArch64::X9;
00081   case AArch64::W10: return AArch64::X10;
00082   case AArch64::W11: return AArch64::X11;
00083   case AArch64::W12: return AArch64::X12;
00084   case AArch64::W13: return AArch64::X13;
00085   case AArch64::W14: return AArch64::X14;
00086   case AArch64::W15: return AArch64::X15;
00087   case AArch64::W16: return AArch64::X16;
00088   case AArch64::W17: return AArch64::X17;
00089   case AArch64::W18: return AArch64::X18;
00090   case AArch64::W19: return AArch64::X19;
00091   case AArch64::W20: return AArch64::X20;
00092   case AArch64::W21: return AArch64::X21;
00093   case AArch64::W22: return AArch64::X22;
00094   case AArch64::W23: return AArch64::X23;
00095   case AArch64::W24: return AArch64::X24;
00096   case AArch64::W25: return AArch64::X25;
00097   case AArch64::W26: return AArch64::X26;
00098   case AArch64::W27: return AArch64::X27;
00099   case AArch64::W28: return AArch64::X28;
00100   case AArch64::W29: return AArch64::FP;
00101   case AArch64::W30: return AArch64::LR;
00102   case AArch64::WSP: return AArch64::SP;
00103   case AArch64::WZR: return AArch64::XZR;
00104   }
00105   // For anything else, return it unchanged.
00106   return Reg;
00107 }
00108 
00109 static inline unsigned getBRegFromDReg(unsigned Reg) {
00110   switch (Reg) {
00111   case AArch64::D0:  return AArch64::B0;
00112   case AArch64::D1:  return AArch64::B1;
00113   case AArch64::D2:  return AArch64::B2;
00114   case AArch64::D3:  return AArch64::B3;
00115   case AArch64::D4:  return AArch64::B4;
00116   case AArch64::D5:  return AArch64::B5;
00117   case AArch64::D6:  return AArch64::B6;
00118   case AArch64::D7:  return AArch64::B7;
00119   case AArch64::D8:  return AArch64::B8;
00120   case AArch64::D9:  return AArch64::B9;
00121   case AArch64::D10: return AArch64::B10;
00122   case AArch64::D11: return AArch64::B11;
00123   case AArch64::D12: return AArch64::B12;
00124   case AArch64::D13: return AArch64::B13;
00125   case AArch64::D14: return AArch64::B14;
00126   case AArch64::D15: return AArch64::B15;
00127   case AArch64::D16: return AArch64::B16;
00128   case AArch64::D17: return AArch64::B17;
00129   case AArch64::D18: return AArch64::B18;
00130   case AArch64::D19: return AArch64::B19;
00131   case AArch64::D20: return AArch64::B20;
00132   case AArch64::D21: return AArch64::B21;
00133   case AArch64::D22: return AArch64::B22;
00134   case AArch64::D23: return AArch64::B23;
00135   case AArch64::D24: return AArch64::B24;
00136   case AArch64::D25: return AArch64::B25;
00137   case AArch64::D26: return AArch64::B26;
00138   case AArch64::D27: return AArch64::B27;
00139   case AArch64::D28: return AArch64::B28;
00140   case AArch64::D29: return AArch64::B29;
00141   case AArch64::D30: return AArch64::B30;
00142   case AArch64::D31: return AArch64::B31;
00143   }
00144   // For anything else, return it unchanged.
00145   return Reg;
00146 }
00147 
00148 
00149 static inline unsigned getDRegFromBReg(unsigned Reg) {
00150   switch (Reg) {
00151   case AArch64::B0:  return AArch64::D0;
00152   case AArch64::B1:  return AArch64::D1;
00153   case AArch64::B2:  return AArch64::D2;
00154   case AArch64::B3:  return AArch64::D3;
00155   case AArch64::B4:  return AArch64::D4;
00156   case AArch64::B5:  return AArch64::D5;
00157   case AArch64::B6:  return AArch64::D6;
00158   case AArch64::B7:  return AArch64::D7;
00159   case AArch64::B8:  return AArch64::D8;
00160   case AArch64::B9:  return AArch64::D9;
00161   case AArch64::B10: return AArch64::D10;
00162   case AArch64::B11: return AArch64::D11;
00163   case AArch64::B12: return AArch64::D12;
00164   case AArch64::B13: return AArch64::D13;
00165   case AArch64::B14: return AArch64::D14;
00166   case AArch64::B15: return AArch64::D15;
00167   case AArch64::B16: return AArch64::D16;
00168   case AArch64::B17: return AArch64::D17;
00169   case AArch64::B18: return AArch64::D18;
00170   case AArch64::B19: return AArch64::D19;
00171   case AArch64::B20: return AArch64::D20;
00172   case AArch64::B21: return AArch64::D21;
00173   case AArch64::B22: return AArch64::D22;
00174   case AArch64::B23: return AArch64::D23;
00175   case AArch64::B24: return AArch64::D24;
00176   case AArch64::B25: return AArch64::D25;
00177   case AArch64::B26: return AArch64::D26;
00178   case AArch64::B27: return AArch64::D27;
00179   case AArch64::B28: return AArch64::D28;
00180   case AArch64::B29: return AArch64::D29;
00181   case AArch64::B30: return AArch64::D30;
00182   case AArch64::B31: return AArch64::D31;
00183   }
00184   // For anything else, return it unchanged.
00185   return Reg;
00186 }
00187 
00188 namespace AArch64CC {
00189 
00190 // The CondCodes constants map directly to the 4-bit encoding of the condition
00191 // field for predicated instructions.
00192 enum CondCode {  // Meaning (integer)          Meaning (floating-point)
00193   EQ = 0x0,      // Equal                      Equal
00194   NE = 0x1,      // Not equal                  Not equal, or unordered
00195   HS = 0x2,      // Unsigned higher or same    >, ==, or unordered
00196   LO = 0x3,      // Unsigned lower             Less than
00197   MI = 0x4,      // Minus, negative            Less than
00198   PL = 0x5,      // Plus, positive or zero     >, ==, or unordered
00199   VS = 0x6,      // Overflow                   Unordered
00200   VC = 0x7,      // No overflow                Not unordered
00201   HI = 0x8,      // Unsigned higher            Greater than, or unordered
00202   LS = 0x9,      // Unsigned lower or same     Less than or equal
00203   GE = 0xa,      // Greater than or equal      Greater than or equal
00204   LT = 0xb,      // Less than                  Less than, or unordered
00205   GT = 0xc,      // Greater than               Greater than
00206   LE = 0xd,      // Less than or equal         <, ==, or unordered
00207   AL = 0xe,      // Always (unconditional)     Always (unconditional)
00208   NV = 0xf,      // Always (unconditional)     Always (unconditional)
00209   // Note the NV exists purely to disassemble 0b1111. Execution is "always".
00210   Invalid
00211 };
00212 
00213 inline static const char *getCondCodeName(CondCode Code) {
00214   switch (Code) {
00215   default: llvm_unreachable("Unknown condition code");
00216   case EQ:  return "eq";
00217   case NE:  return "ne";
00218   case HS:  return "hs";
00219   case LO:  return "lo";
00220   case MI:  return "mi";
00221   case PL:  return "pl";
00222   case VS:  return "vs";
00223   case VC:  return "vc";
00224   case HI:  return "hi";
00225   case LS:  return "ls";
00226   case GE:  return "ge";
00227   case LT:  return "lt";
00228   case GT:  return "gt";
00229   case LE:  return "le";
00230   case AL:  return "al";
00231   case NV:  return "nv";
00232   }
00233 }
00234 
00235 inline static CondCode getInvertedCondCode(CondCode Code) {
00236   // To reverse a condition it's necessary to only invert the low bit:
00237 
00238   return static_cast<CondCode>(static_cast<unsigned>(Code) ^ 0x1);
00239 }
00240 
00241 /// Given a condition code, return NZCV flags that would satisfy that condition.
00242 /// The flag bits are in the format expected by the ccmp instructions.
00243 /// Note that many different flag settings can satisfy a given condition code,
00244 /// this function just returns one of them.
00245 inline static unsigned getNZCVToSatisfyCondCode(CondCode Code) {
00246   // NZCV flags encoded as expected by ccmp instructions, ARMv8 ISA 5.5.7.
00247   enum { N = 8, Z = 4, C = 2, V = 1 };
00248   switch (Code) {
00249   default: llvm_unreachable("Unknown condition code");
00250   case EQ: return Z; // Z == 1
00251   case NE: return 0; // Z == 0
00252   case HS: return C; // C == 1
00253   case LO: return 0; // C == 0
00254   case MI: return N; // N == 1
00255   case PL: return 0; // N == 0
00256   case VS: return V; // V == 1
00257   case VC: return 0; // V == 0
00258   case HI: return C; // C == 1 && Z == 0
00259   case LS: return 0; // C == 0 || Z == 1
00260   case GE: return 0; // N == V
00261   case LT: return N; // N != V
00262   case GT: return 0; // Z == 0 && N == V
00263   case LE: return Z; // Z == 1 || N != V
00264   }
00265 }
00266 } // end namespace AArch64CC
00267 
00268 /// Instances of this class can perform bidirectional mapping from random
00269 /// identifier strings to operand encodings. For example "MSR" takes a named
00270 /// system-register which must be encoded somehow and decoded for printing. This
00271 /// central location means that the information for those transformations is not
00272 /// duplicated and remains in sync.
00273 ///
00274 /// FIXME: currently the algorithm is a completely unoptimised linear
00275 /// search. Obviously this could be improved, but we would probably want to work
00276 /// out just how often these instructions are emitted before working on it. It
00277 /// might even be optimal to just reorder the tables for the common instructions
00278 /// rather than changing the algorithm.
00279 struct AArch64NamedImmMapper {
00280   struct Mapping {
00281     const char *Name;
00282     uint32_t Value;
00283     uint64_t AvailableForFeatures;
00284     // empty AvailableForFeatures means "always-on"
00285     bool isNameEqual(std::string Other, uint64_t FeatureBits=~0ULL) const {
00286       if (AvailableForFeatures && !(AvailableForFeatures & FeatureBits))
00287         return false;
00288       return Name == Other;
00289     }
00290     bool isValueEqual(uint32_t Other, uint64_t FeatureBits=~0ULL) const {
00291       if (AvailableForFeatures && !(AvailableForFeatures & FeatureBits))
00292         return false;
00293       return Value == Other;
00294     }
00295   };
00296 
00297   template<int N>
00298   AArch64NamedImmMapper(const Mapping (&Mappings)[N], uint32_t TooBigImm)
00299     : Mappings(&Mappings[0]), NumMappings(N), TooBigImm(TooBigImm) {}
00300 
00301   StringRef toString(uint32_t Value, uint64_t FeatureBits, bool &Valid) const;
00302   uint32_t fromString(StringRef Name, uint64_t FeatureBits, bool &Valid) const;
00303 
00304   /// Many of the instructions allow an alternative assembly form consisting of
00305   /// a simple immediate. Currently the only valid forms are ranges [0, N) where
00306   /// N being 0 indicates no immediate syntax-form is allowed.
00307   bool validImm(uint32_t Value) const;
00308 protected:
00309   const Mapping *Mappings;
00310   size_t NumMappings;
00311   uint32_t TooBigImm;
00312 };
00313 
00314 namespace AArch64AT {
00315   enum ATValues {
00316     Invalid = -1,    // Op0 Op1  CRn   CRm   Op2
00317     S1E1R = 0x43c0,  // 01  000  0111  1000  000
00318     S1E2R = 0x63c0,  // 01  100  0111  1000  000
00319     S1E3R = 0x73c0,  // 01  110  0111  1000  000
00320     S1E1W = 0x43c1,  // 01  000  0111  1000  001
00321     S1E2W = 0x63c1,  // 01  100  0111  1000  001
00322     S1E3W = 0x73c1,  // 01  110  0111  1000  001
00323     S1E0R = 0x43c2,  // 01  000  0111  1000  010
00324     S1E0W = 0x43c3,  // 01  000  0111  1000  011
00325     S12E1R = 0x63c4, // 01  100  0111  1000  100
00326     S12E1W = 0x63c5, // 01  100  0111  1000  101
00327     S12E0R = 0x63c6, // 01  100  0111  1000  110
00328     S12E0W = 0x63c7  // 01  100  0111  1000  111
00329   };
00330 
00331   struct ATMapper : AArch64NamedImmMapper {
00332     const static Mapping ATMappings[];
00333 
00334     ATMapper();
00335   };
00336 
00337 }
00338 namespace AArch64DB {
00339   enum DBValues {
00340     Invalid = -1,
00341     OSHLD = 0x1,
00342     OSHST = 0x2,
00343     OSH =   0x3,
00344     NSHLD = 0x5,
00345     NSHST = 0x6,
00346     NSH =   0x7,
00347     ISHLD = 0x9,
00348     ISHST = 0xa,
00349     ISH =   0xb,
00350     LD =    0xd,
00351     ST =    0xe,
00352     SY =    0xf
00353   };
00354 
00355   struct DBarrierMapper : AArch64NamedImmMapper {
00356     const static Mapping DBarrierMappings[];
00357 
00358     DBarrierMapper();
00359   };
00360 }
00361 
00362 namespace  AArch64DC {
00363   enum DCValues {
00364     Invalid = -1,   // Op1  CRn   CRm   Op2
00365     ZVA   = 0x5ba1, // 01  011  0111  0100  001
00366     IVAC  = 0x43b1, // 01  000  0111  0110  001
00367     ISW   = 0x43b2, // 01  000  0111  0110  010
00368     CVAC  = 0x5bd1, // 01  011  0111  1010  001
00369     CSW   = 0x43d2, // 01  000  0111  1010  010
00370     CVAU  = 0x5bd9, // 01  011  0111  1011  001
00371     CIVAC = 0x5bf1, // 01  011  0111  1110  001
00372     CISW  = 0x43f2  // 01  000  0111  1110  010
00373   };
00374 
00375   struct DCMapper : AArch64NamedImmMapper {
00376     const static Mapping DCMappings[];
00377 
00378     DCMapper();
00379   };
00380 
00381 }
00382 
00383 namespace  AArch64IC {
00384   enum ICValues {
00385     Invalid = -1,     // Op1  CRn   CRm   Op2
00386     IALLUIS = 0x0388, // 000  0111  0001  000
00387     IALLU = 0x03a8,   // 000  0111  0101  000
00388     IVAU = 0x1ba9     // 011  0111  0101  001
00389   };
00390 
00391 
00392   struct ICMapper : AArch64NamedImmMapper {
00393     const static Mapping ICMappings[];
00394 
00395     ICMapper();
00396   };
00397 
00398   static inline bool NeedsRegister(ICValues Val) {
00399     return Val == IVAU;
00400   }
00401 }
00402 
00403 namespace  AArch64ISB {
00404   enum ISBValues {
00405     Invalid = -1,
00406     SY = 0xf
00407   };
00408   struct ISBMapper : AArch64NamedImmMapper {
00409     const static Mapping ISBMappings[];
00410 
00411     ISBMapper();
00412   };
00413 }
00414 
00415 namespace AArch64PRFM {
00416   enum PRFMValues {
00417     Invalid = -1,
00418     PLDL1KEEP = 0x00,
00419     PLDL1STRM = 0x01,
00420     PLDL2KEEP = 0x02,
00421     PLDL2STRM = 0x03,
00422     PLDL3KEEP = 0x04,
00423     PLDL3STRM = 0x05,
00424     PLIL1KEEP = 0x08,
00425     PLIL1STRM = 0x09,
00426     PLIL2KEEP = 0x0a,
00427     PLIL2STRM = 0x0b,
00428     PLIL3KEEP = 0x0c,
00429     PLIL3STRM = 0x0d,
00430     PSTL1KEEP = 0x10,
00431     PSTL1STRM = 0x11,
00432     PSTL2KEEP = 0x12,
00433     PSTL2STRM = 0x13,
00434     PSTL3KEEP = 0x14,
00435     PSTL3STRM = 0x15
00436   };
00437 
00438   struct PRFMMapper : AArch64NamedImmMapper {
00439     const static Mapping PRFMMappings[];
00440 
00441     PRFMMapper();
00442   };
00443 }
00444 
00445 namespace AArch64PState {
00446   enum PStateValues {
00447     Invalid = -1,
00448     SPSel = 0x05,
00449     DAIFSet = 0x1e,
00450     DAIFClr = 0x1f,
00451 
00452     // v8.1a "Privileged Access Never" extension-specific PStates
00453     PAN = 0x04,
00454   };
00455 
00456   struct PStateMapper : AArch64NamedImmMapper {
00457     const static Mapping PStateMappings[];
00458 
00459     PStateMapper();
00460   };
00461 
00462 }
00463 
00464 namespace AArch64SE {
00465     enum ShiftExtSpecifiers {
00466         Invalid = -1,
00467         LSL,
00468         MSL,
00469         LSR,
00470         ASR,
00471         ROR,
00472 
00473         UXTB,
00474         UXTH,
00475         UXTW,
00476         UXTX,
00477 
00478         SXTB,
00479         SXTH,
00480         SXTW,
00481         SXTX
00482     };
00483 }
00484 
00485 namespace AArch64Layout {
00486     enum VectorLayout {
00487         Invalid = -1,
00488         VL_8B,
00489         VL_4H,
00490         VL_2S,
00491         VL_1D,
00492 
00493         VL_16B,
00494         VL_8H,
00495         VL_4S,
00496         VL_2D,
00497 
00498         // Bare layout for the 128-bit vector
00499         // (only show ".b", ".h", ".s", ".d" without vector number)
00500         VL_B,
00501         VL_H,
00502         VL_S,
00503         VL_D
00504     };
00505 }
00506 
00507 inline static const char *
00508 AArch64VectorLayoutToString(AArch64Layout::VectorLayout Layout) {
00509   switch (Layout) {
00510   case AArch64Layout::VL_8B:  return ".8b";
00511   case AArch64Layout::VL_4H:  return ".4h";
00512   case AArch64Layout::VL_2S:  return ".2s";
00513   case AArch64Layout::VL_1D:  return ".1d";
00514   case AArch64Layout::VL_16B:  return ".16b";
00515   case AArch64Layout::VL_8H:  return ".8h";
00516   case AArch64Layout::VL_4S:  return ".4s";
00517   case AArch64Layout::VL_2D:  return ".2d";
00518   case AArch64Layout::VL_B:  return ".b";
00519   case AArch64Layout::VL_H:  return ".h";
00520   case AArch64Layout::VL_S:  return ".s";
00521   case AArch64Layout::VL_D:  return ".d";
00522   default: llvm_unreachable("Unknown Vector Layout");
00523   }
00524 }
00525 
00526 inline static AArch64Layout::VectorLayout
00527 AArch64StringToVectorLayout(StringRef LayoutStr) {
00528   return StringSwitch<AArch64Layout::VectorLayout>(LayoutStr)
00529              .Case(".8b", AArch64Layout::VL_8B)
00530              .Case(".4h", AArch64Layout::VL_4H)
00531              .Case(".2s", AArch64Layout::VL_2S)
00532              .Case(".1d", AArch64Layout::VL_1D)
00533              .Case(".16b", AArch64Layout::VL_16B)
00534              .Case(".8h", AArch64Layout::VL_8H)
00535              .Case(".4s", AArch64Layout::VL_4S)
00536              .Case(".2d", AArch64Layout::VL_2D)
00537              .Case(".b", AArch64Layout::VL_B)
00538              .Case(".h", AArch64Layout::VL_H)
00539              .Case(".s", AArch64Layout::VL_S)
00540              .Case(".d", AArch64Layout::VL_D)
00541              .Default(AArch64Layout::Invalid);
00542 }
00543 
00544 namespace AArch64SysReg {
00545   enum SysRegROValues {
00546     MDCCSR_EL0        = 0x9808, // 10  011  0000  0001  000
00547     DBGDTRRX_EL0      = 0x9828, // 10  011  0000  0101  000
00548     MDRAR_EL1         = 0x8080, // 10  000  0001  0000  000
00549     OSLSR_EL1         = 0x808c, // 10  000  0001  0001  100
00550     DBGAUTHSTATUS_EL1 = 0x83f6, // 10  000  0111  1110  110
00551     PMCEID0_EL0       = 0xdce6, // 11  011  1001  1100  110
00552     PMCEID1_EL0       = 0xdce7, // 11  011  1001  1100  111
00553     MIDR_EL1          = 0xc000, // 11  000  0000  0000  000
00554     CCSIDR_EL1        = 0xc800, // 11  001  0000  0000  000
00555     CLIDR_EL1         = 0xc801, // 11  001  0000  0000  001
00556     CTR_EL0           = 0xd801, // 11  011  0000  0000  001
00557     MPIDR_EL1         = 0xc005, // 11  000  0000  0000  101
00558     REVIDR_EL1        = 0xc006, // 11  000  0000  0000  110
00559     AIDR_EL1          = 0xc807, // 11  001  0000  0000  111
00560     DCZID_EL0         = 0xd807, // 11  011  0000  0000  111
00561     ID_PFR0_EL1       = 0xc008, // 11  000  0000  0001  000
00562     ID_PFR1_EL1       = 0xc009, // 11  000  0000  0001  001
00563     ID_DFR0_EL1       = 0xc00a, // 11  000  0000  0001  010
00564     ID_AFR0_EL1       = 0xc00b, // 11  000  0000  0001  011
00565     ID_MMFR0_EL1      = 0xc00c, // 11  000  0000  0001  100
00566     ID_MMFR1_EL1      = 0xc00d, // 11  000  0000  0001  101
00567     ID_MMFR2_EL1      = 0xc00e, // 11  000  0000  0001  110
00568     ID_MMFR3_EL1      = 0xc00f, // 11  000  0000  0001  111
00569     ID_ISAR0_EL1      = 0xc010, // 11  000  0000  0010  000
00570     ID_ISAR1_EL1      = 0xc011, // 11  000  0000  0010  001
00571     ID_ISAR2_EL1      = 0xc012, // 11  000  0000  0010  010
00572     ID_ISAR3_EL1      = 0xc013, // 11  000  0000  0010  011
00573     ID_ISAR4_EL1      = 0xc014, // 11  000  0000  0010  100
00574     ID_ISAR5_EL1      = 0xc015, // 11  000  0000  0010  101
00575     ID_A64PFR0_EL1    = 0xc020, // 11  000  0000  0100  000
00576     ID_A64PFR1_EL1    = 0xc021, // 11  000  0000  0100  001
00577     ID_A64DFR0_EL1    = 0xc028, // 11  000  0000  0101  000
00578     ID_A64DFR1_EL1    = 0xc029, // 11  000  0000  0101  001
00579     ID_A64AFR0_EL1    = 0xc02c, // 11  000  0000  0101  100
00580     ID_A64AFR1_EL1    = 0xc02d, // 11  000  0000  0101  101
00581     ID_A64ISAR0_EL1   = 0xc030, // 11  000  0000  0110  000
00582     ID_A64ISAR1_EL1   = 0xc031, // 11  000  0000  0110  001
00583     ID_A64MMFR0_EL1   = 0xc038, // 11  000  0000  0111  000
00584     ID_A64MMFR1_EL1   = 0xc039, // 11  000  0000  0111  001
00585     MVFR0_EL1         = 0xc018, // 11  000  0000  0011  000
00586     MVFR1_EL1         = 0xc019, // 11  000  0000  0011  001
00587     MVFR2_EL1         = 0xc01a, // 11  000  0000  0011  010
00588     RVBAR_EL1         = 0xc601, // 11  000  1100  0000  001
00589     RVBAR_EL2         = 0xe601, // 11  100  1100  0000  001
00590     RVBAR_EL3         = 0xf601, // 11  110  1100  0000  001
00591     ISR_EL1           = 0xc608, // 11  000  1100  0001  000
00592     CNTPCT_EL0        = 0xdf01, // 11  011  1110  0000  001
00593     CNTVCT_EL0        = 0xdf02,  // 11  011  1110  0000  010
00594 
00595     // Trace registers
00596     TRCSTATR          = 0x8818, // 10  001  0000  0011  000
00597     TRCIDR8           = 0x8806, // 10  001  0000  0000  110
00598     TRCIDR9           = 0x880e, // 10  001  0000  0001  110
00599     TRCIDR10          = 0x8816, // 10  001  0000  0010  110
00600     TRCIDR11          = 0x881e, // 10  001  0000  0011  110
00601     TRCIDR12          = 0x8826, // 10  001  0000  0100  110
00602     TRCIDR13          = 0x882e, // 10  001  0000  0101  110
00603     TRCIDR0           = 0x8847, // 10  001  0000  1000  111
00604     TRCIDR1           = 0x884f, // 10  001  0000  1001  111
00605     TRCIDR2           = 0x8857, // 10  001  0000  1010  111
00606     TRCIDR3           = 0x885f, // 10  001  0000  1011  111
00607     TRCIDR4           = 0x8867, // 10  001  0000  1100  111
00608     TRCIDR5           = 0x886f, // 10  001  0000  1101  111
00609     TRCIDR6           = 0x8877, // 10  001  0000  1110  111
00610     TRCIDR7           = 0x887f, // 10  001  0000  1111  111
00611     TRCOSLSR          = 0x888c, // 10  001  0001  0001  100
00612     TRCPDSR           = 0x88ac, // 10  001  0001  0101  100
00613     TRCDEVAFF0        = 0x8bd6, // 10  001  0111  1010  110
00614     TRCDEVAFF1        = 0x8bde, // 10  001  0111  1011  110
00615     TRCLSR            = 0x8bee, // 10  001  0111  1101  110
00616     TRCAUTHSTATUS     = 0x8bf6, // 10  001  0111  1110  110
00617     TRCDEVARCH        = 0x8bfe, // 10  001  0111  1111  110
00618     TRCDEVID          = 0x8b97, // 10  001  0111  0010  111
00619     TRCDEVTYPE        = 0x8b9f, // 10  001  0111  0011  111
00620     TRCPIDR4          = 0x8ba7, // 10  001  0111  0100  111
00621     TRCPIDR5          = 0x8baf, // 10  001  0111  0101  111
00622     TRCPIDR6          = 0x8bb7, // 10  001  0111  0110  111
00623     TRCPIDR7          = 0x8bbf, // 10  001  0111  0111  111
00624     TRCPIDR0          = 0x8bc7, // 10  001  0111  1000  111
00625     TRCPIDR1          = 0x8bcf, // 10  001  0111  1001  111
00626     TRCPIDR2          = 0x8bd7, // 10  001  0111  1010  111
00627     TRCPIDR3          = 0x8bdf, // 10  001  0111  1011  111
00628     TRCCIDR0          = 0x8be7, // 10  001  0111  1100  111
00629     TRCCIDR1          = 0x8bef, // 10  001  0111  1101  111
00630     TRCCIDR2          = 0x8bf7, // 10  001  0111  1110  111
00631     TRCCIDR3          = 0x8bff, // 10  001  0111  1111  111
00632 
00633     // GICv3 registers
00634     ICC_IAR1_EL1      = 0xc660, // 11  000  1100  1100  000
00635     ICC_IAR0_EL1      = 0xc640, // 11  000  1100  1000  000
00636     ICC_HPPIR1_EL1    = 0xc662, // 11  000  1100  1100  010
00637     ICC_HPPIR0_EL1    = 0xc642, // 11  000  1100  1000  010
00638     ICC_RPR_EL1       = 0xc65b, // 11  000  1100  1011  011
00639     ICH_VTR_EL2       = 0xe659, // 11  100  1100  1011  001
00640     ICH_EISR_EL2      = 0xe65b, // 11  100  1100  1011  011
00641     ICH_ELSR_EL2      = 0xe65d  // 11  100  1100  1011  101
00642   };
00643 
00644   enum SysRegWOValues {
00645     DBGDTRTX_EL0      = 0x9828, // 10  011  0000  0101  000
00646     OSLAR_EL1         = 0x8084, // 10  000  0001  0000  100
00647     PMSWINC_EL0       = 0xdce4,  // 11  011  1001  1100  100
00648 
00649     // Trace Registers
00650     TRCOSLAR          = 0x8884, // 10  001  0001  0000  100
00651     TRCLAR            = 0x8be6, // 10  001  0111  1100  110
00652 
00653     // GICv3 registers
00654     ICC_EOIR1_EL1     = 0xc661, // 11  000  1100  1100  001
00655     ICC_EOIR0_EL1     = 0xc641, // 11  000  1100  1000  001
00656     ICC_DIR_EL1       = 0xc659, // 11  000  1100  1011  001
00657     ICC_SGI1R_EL1     = 0xc65d, // 11  000  1100  1011  101
00658     ICC_ASGI1R_EL1    = 0xc65e, // 11  000  1100  1011  110
00659     ICC_SGI0R_EL1     = 0xc65f  // 11  000  1100  1011  111
00660   };
00661 
00662   enum SysRegValues {
00663     Invalid = -1,               // Op0 Op1  CRn   CRm   Op2
00664     OSDTRRX_EL1       = 0x8002, // 10  000  0000  0000  010
00665     OSDTRTX_EL1       = 0x801a, // 10  000  0000  0011  010
00666     TEECR32_EL1       = 0x9000, // 10  010  0000  0000  000
00667     MDCCINT_EL1       = 0x8010, // 10  000  0000  0010  000
00668     MDSCR_EL1         = 0x8012, // 10  000  0000  0010  010
00669     DBGDTR_EL0        = 0x9820, // 10  011  0000  0100  000
00670     OSECCR_EL1        = 0x8032, // 10  000  0000  0110  010
00671     DBGVCR32_EL2      = 0xa038, // 10  100  0000  0111  000
00672     DBGBVR0_EL1       = 0x8004, // 10  000  0000  0000  100
00673     DBGBVR1_EL1       = 0x800c, // 10  000  0000  0001  100
00674     DBGBVR2_EL1       = 0x8014, // 10  000  0000  0010  100
00675     DBGBVR3_EL1       = 0x801c, // 10  000  0000  0011  100
00676     DBGBVR4_EL1       = 0x8024, // 10  000  0000  0100  100
00677     DBGBVR5_EL1       = 0x802c, // 10  000  0000  0101  100
00678     DBGBVR6_EL1       = 0x8034, // 10  000  0000  0110  100
00679     DBGBVR7_EL1       = 0x803c, // 10  000  0000  0111  100
00680     DBGBVR8_EL1       = 0x8044, // 10  000  0000  1000  100
00681     DBGBVR9_EL1       = 0x804c, // 10  000  0000  1001  100
00682     DBGBVR10_EL1      = 0x8054, // 10  000  0000  1010  100
00683     DBGBVR11_EL1      = 0x805c, // 10  000  0000  1011  100
00684     DBGBVR12_EL1      = 0x8064, // 10  000  0000  1100  100
00685     DBGBVR13_EL1      = 0x806c, // 10  000  0000  1101  100
00686     DBGBVR14_EL1      = 0x8074, // 10  000  0000  1110  100
00687     DBGBVR15_EL1      = 0x807c, // 10  000  0000  1111  100
00688     DBGBCR0_EL1       = 0x8005, // 10  000  0000  0000  101
00689     DBGBCR1_EL1       = 0x800d, // 10  000  0000  0001  101
00690     DBGBCR2_EL1       = 0x8015, // 10  000  0000  0010  101
00691     DBGBCR3_EL1       = 0x801d, // 10  000  0000  0011  101
00692     DBGBCR4_EL1       = 0x8025, // 10  000  0000  0100  101
00693     DBGBCR5_EL1       = 0x802d, // 10  000  0000  0101  101
00694     DBGBCR6_EL1       = 0x8035, // 10  000  0000  0110  101
00695     DBGBCR7_EL1       = 0x803d, // 10  000  0000  0111  101
00696     DBGBCR8_EL1       = 0x8045, // 10  000  0000  1000  101
00697     DBGBCR9_EL1       = 0x804d, // 10  000  0000  1001  101
00698     DBGBCR10_EL1      = 0x8055, // 10  000  0000  1010  101
00699     DBGBCR11_EL1      = 0x805d, // 10  000  0000  1011  101
00700     DBGBCR12_EL1      = 0x8065, // 10  000  0000  1100  101
00701     DBGBCR13_EL1      = 0x806d, // 10  000  0000  1101  101
00702     DBGBCR14_EL1      = 0x8075, // 10  000  0000  1110  101
00703     DBGBCR15_EL1      = 0x807d, // 10  000  0000  1111  101
00704     DBGWVR0_EL1       = 0x8006, // 10  000  0000  0000  110
00705     DBGWVR1_EL1       = 0x800e, // 10  000  0000  0001  110
00706     DBGWVR2_EL1       = 0x8016, // 10  000  0000  0010  110
00707     DBGWVR3_EL1       = 0x801e, // 10  000  0000  0011  110
00708     DBGWVR4_EL1       = 0x8026, // 10  000  0000  0100  110
00709     DBGWVR5_EL1       = 0x802e, // 10  000  0000  0101  110
00710     DBGWVR6_EL1       = 0x8036, // 10  000  0000  0110  110
00711     DBGWVR7_EL1       = 0x803e, // 10  000  0000  0111  110
00712     DBGWVR8_EL1       = 0x8046, // 10  000  0000  1000  110
00713     DBGWVR9_EL1       = 0x804e, // 10  000  0000  1001  110
00714     DBGWVR10_EL1      = 0x8056, // 10  000  0000  1010  110
00715     DBGWVR11_EL1      = 0x805e, // 10  000  0000  1011  110
00716     DBGWVR12_EL1      = 0x8066, // 10  000  0000  1100  110
00717     DBGWVR13_EL1      = 0x806e, // 10  000  0000  1101  110
00718     DBGWVR14_EL1      = 0x8076, // 10  000  0000  1110  110
00719     DBGWVR15_EL1      = 0x807e, // 10  000  0000  1111  110
00720     DBGWCR0_EL1       = 0x8007, // 10  000  0000  0000  111
00721     DBGWCR1_EL1       = 0x800f, // 10  000  0000  0001  111
00722     DBGWCR2_EL1       = 0x8017, // 10  000  0000  0010  111
00723     DBGWCR3_EL1       = 0x801f, // 10  000  0000  0011  111
00724     DBGWCR4_EL1       = 0x8027, // 10  000  0000  0100  111
00725     DBGWCR5_EL1       = 0x802f, // 10  000  0000  0101  111
00726     DBGWCR6_EL1       = 0x8037, // 10  000  0000  0110  111
00727     DBGWCR7_EL1       = 0x803f, // 10  000  0000  0111  111
00728     DBGWCR8_EL1       = 0x8047, // 10  000  0000  1000  111
00729     DBGWCR9_EL1       = 0x804f, // 10  000  0000  1001  111
00730     DBGWCR10_EL1      = 0x8057, // 10  000  0000  1010  111
00731     DBGWCR11_EL1      = 0x805f, // 10  000  0000  1011  111
00732     DBGWCR12_EL1      = 0x8067, // 10  000  0000  1100  111
00733     DBGWCR13_EL1      = 0x806f, // 10  000  0000  1101  111
00734     DBGWCR14_EL1      = 0x8077, // 10  000  0000  1110  111
00735     DBGWCR15_EL1      = 0x807f, // 10  000  0000  1111  111
00736     TEEHBR32_EL1      = 0x9080, // 10  010  0001  0000  000
00737     OSDLR_EL1         = 0x809c, // 10  000  0001  0011  100
00738     DBGPRCR_EL1       = 0x80a4, // 10  000  0001  0100  100
00739     DBGCLAIMSET_EL1   = 0x83c6, // 10  000  0111  1000  110
00740     DBGCLAIMCLR_EL1   = 0x83ce, // 10  000  0111  1001  110
00741     CSSELR_EL1        = 0xd000, // 11  010  0000  0000  000
00742     VPIDR_EL2         = 0xe000, // 11  100  0000  0000  000
00743     VMPIDR_EL2        = 0xe005, // 11  100  0000  0000  101
00744     CPACR_EL1         = 0xc082, // 11  000  0001  0000  010
00745     SCTLR_EL1         = 0xc080, // 11  000  0001  0000  000
00746     SCTLR_EL2         = 0xe080, // 11  100  0001  0000  000
00747     SCTLR_EL3         = 0xf080, // 11  110  0001  0000  000
00748     ACTLR_EL1         = 0xc081, // 11  000  0001  0000  001
00749     ACTLR_EL2         = 0xe081, // 11  100  0001  0000  001
00750     ACTLR_EL3         = 0xf081, // 11  110  0001  0000  001
00751     HCR_EL2           = 0xe088, // 11  100  0001  0001  000
00752     SCR_EL3           = 0xf088, // 11  110  0001  0001  000
00753     MDCR_EL2          = 0xe089, // 11  100  0001  0001  001
00754     SDER32_EL3        = 0xf089, // 11  110  0001  0001  001
00755     CPTR_EL2          = 0xe08a, // 11  100  0001  0001  010
00756     CPTR_EL3          = 0xf08a, // 11  110  0001  0001  010
00757     HSTR_EL2          = 0xe08b, // 11  100  0001  0001  011
00758     HACR_EL2          = 0xe08f, // 11  100  0001  0001  111
00759     MDCR_EL3          = 0xf099, // 11  110  0001  0011  001
00760     TTBR0_EL1         = 0xc100, // 11  000  0010  0000  000
00761     TTBR0_EL2         = 0xe100, // 11  100  0010  0000  000
00762     TTBR0_EL3         = 0xf100, // 11  110  0010  0000  000
00763     TTBR1_EL1         = 0xc101, // 11  000  0010  0000  001
00764     TCR_EL1           = 0xc102, // 11  000  0010  0000  010
00765     TCR_EL2           = 0xe102, // 11  100  0010  0000  010
00766     TCR_EL3           = 0xf102, // 11  110  0010  0000  010
00767     VTTBR_EL2         = 0xe108, // 11  100  0010  0001  000
00768     VTCR_EL2          = 0xe10a, // 11  100  0010  0001  010
00769     DACR32_EL2        = 0xe180, // 11  100  0011  0000  000
00770     SPSR_EL1          = 0xc200, // 11  000  0100  0000  000
00771     SPSR_EL2          = 0xe200, // 11  100  0100  0000  000
00772     SPSR_EL3          = 0xf200, // 11  110  0100  0000  000
00773     ELR_EL1           = 0xc201, // 11  000  0100  0000  001
00774     ELR_EL2           = 0xe201, // 11  100  0100  0000  001
00775     ELR_EL3           = 0xf201, // 11  110  0100  0000  001
00776     SP_EL0            = 0xc208, // 11  000  0100  0001  000
00777     SP_EL1            = 0xe208, // 11  100  0100  0001  000
00778     SP_EL2            = 0xf208, // 11  110  0100  0001  000
00779     SPSel             = 0xc210, // 11  000  0100  0010  000
00780     NZCV              = 0xda10, // 11  011  0100  0010  000
00781     DAIF              = 0xda11, // 11  011  0100  0010  001
00782     CurrentEL         = 0xc212, // 11  000  0100  0010  010
00783     SPSR_irq          = 0xe218, // 11  100  0100  0011  000
00784     SPSR_abt          = 0xe219, // 11  100  0100  0011  001
00785     SPSR_und          = 0xe21a, // 11  100  0100  0011  010
00786     SPSR_fiq          = 0xe21b, // 11  100  0100  0011  011
00787     FPCR              = 0xda20, // 11  011  0100  0100  000
00788     FPSR              = 0xda21, // 11  011  0100  0100  001
00789     DSPSR_EL0         = 0xda28, // 11  011  0100  0101  000
00790     DLR_EL0           = 0xda29, // 11  011  0100  0101  001
00791     IFSR32_EL2        = 0xe281, // 11  100  0101  0000  001
00792     AFSR0_EL1         = 0xc288, // 11  000  0101  0001  000
00793     AFSR0_EL2         = 0xe288, // 11  100  0101  0001  000
00794     AFSR0_EL3         = 0xf288, // 11  110  0101  0001  000
00795     AFSR1_EL1         = 0xc289, // 11  000  0101  0001  001
00796     AFSR1_EL2         = 0xe289, // 11  100  0101  0001  001
00797     AFSR1_EL3         = 0xf289, // 11  110  0101  0001  001
00798     ESR_EL1           = 0xc290, // 11  000  0101  0010  000
00799     ESR_EL2           = 0xe290, // 11  100  0101  0010  000
00800     ESR_EL3           = 0xf290, // 11  110  0101  0010  000
00801     FPEXC32_EL2       = 0xe298, // 11  100  0101  0011  000
00802     FAR_EL1           = 0xc300, // 11  000  0110  0000  000
00803     FAR_EL2           = 0xe300, // 11  100  0110  0000  000
00804     FAR_EL3           = 0xf300, // 11  110  0110  0000  000
00805     HPFAR_EL2         = 0xe304, // 11  100  0110  0000  100
00806     PAR_EL1           = 0xc3a0, // 11  000  0111  0100  000
00807     PMCR_EL0          = 0xdce0, // 11  011  1001  1100  000
00808     PMCNTENSET_EL0    = 0xdce1, // 11  011  1001  1100  001
00809     PMCNTENCLR_EL0    = 0xdce2, // 11  011  1001  1100  010
00810     PMOVSCLR_EL0      = 0xdce3, // 11  011  1001  1100  011
00811     PMSELR_EL0        = 0xdce5, // 11  011  1001  1100  101
00812     PMCCNTR_EL0       = 0xdce8, // 11  011  1001  1101  000
00813     PMXEVTYPER_EL0    = 0xdce9, // 11  011  1001  1101  001
00814     PMXEVCNTR_EL0     = 0xdcea, // 11  011  1001  1101  010
00815     PMUSERENR_EL0     = 0xdcf0, // 11  011  1001  1110  000
00816     PMINTENSET_EL1    = 0xc4f1, // 11  000  1001  1110  001
00817     PMINTENCLR_EL1    = 0xc4f2, // 11  000  1001  1110  010
00818     PMOVSSET_EL0      = 0xdcf3, // 11  011  1001  1110  011
00819     MAIR_EL1          = 0xc510, // 11  000  1010  0010  000
00820     MAIR_EL2          = 0xe510, // 11  100  1010  0010  000
00821     MAIR_EL3          = 0xf510, // 11  110  1010  0010  000
00822     AMAIR_EL1         = 0xc518, // 11  000  1010  0011  000
00823     AMAIR_EL2         = 0xe518, // 11  100  1010  0011  000
00824     AMAIR_EL3         = 0xf518, // 11  110  1010  0011  000
00825     VBAR_EL1          = 0xc600, // 11  000  1100  0000  000
00826     VBAR_EL2          = 0xe600, // 11  100  1100  0000  000
00827     VBAR_EL3          = 0xf600, // 11  110  1100  0000  000
00828     RMR_EL1           = 0xc602, // 11  000  1100  0000  010
00829     RMR_EL2           = 0xe602, // 11  100  1100  0000  010
00830     RMR_EL3           = 0xf602, // 11  110  1100  0000  010
00831     CONTEXTIDR_EL1    = 0xc681, // 11  000  1101  0000  001
00832     TPIDR_EL0         = 0xde82, // 11  011  1101  0000  010
00833     TPIDR_EL2         = 0xe682, // 11  100  1101  0000  010
00834     TPIDR_EL3         = 0xf682, // 11  110  1101  0000  010
00835     TPIDRRO_EL0       = 0xde83, // 11  011  1101  0000  011
00836     TPIDR_EL1         = 0xc684, // 11  000  1101  0000  100
00837     CNTFRQ_EL0        = 0xdf00, // 11  011  1110  0000  000
00838     CNTVOFF_EL2       = 0xe703, // 11  100  1110  0000  011
00839     CNTKCTL_EL1       = 0xc708, // 11  000  1110  0001  000
00840     CNTHCTL_EL2       = 0xe708, // 11  100  1110  0001  000
00841     CNTP_TVAL_EL0     = 0xdf10, // 11  011  1110  0010  000
00842     CNTHP_TVAL_EL2    = 0xe710, // 11  100  1110  0010  000
00843     CNTPS_TVAL_EL1    = 0xff10, // 11  111  1110  0010  000
00844     CNTP_CTL_EL0      = 0xdf11, // 11  011  1110  0010  001
00845     CNTHP_CTL_EL2     = 0xe711, // 11  100  1110  0010  001
00846     CNTPS_CTL_EL1     = 0xff11, // 11  111  1110  0010  001
00847     CNTP_CVAL_EL0     = 0xdf12, // 11  011  1110  0010  010
00848     CNTHP_CVAL_EL2    = 0xe712, // 11  100  1110  0010  010
00849     CNTPS_CVAL_EL1    = 0xff12, // 11  111  1110  0010  010
00850     CNTV_TVAL_EL0     = 0xdf18, // 11  011  1110  0011  000
00851     CNTV_CTL_EL0      = 0xdf19, // 11  011  1110  0011  001
00852     CNTV_CVAL_EL0     = 0xdf1a, // 11  011  1110  0011  010
00853     PMEVCNTR0_EL0     = 0xdf40, // 11  011  1110  1000  000
00854     PMEVCNTR1_EL0     = 0xdf41, // 11  011  1110  1000  001
00855     PMEVCNTR2_EL0     = 0xdf42, // 11  011  1110  1000  010
00856     PMEVCNTR3_EL0     = 0xdf43, // 11  011  1110  1000  011
00857     PMEVCNTR4_EL0     = 0xdf44, // 11  011  1110  1000  100
00858     PMEVCNTR5_EL0     = 0xdf45, // 11  011  1110  1000  101
00859     PMEVCNTR6_EL0     = 0xdf46, // 11  011  1110  1000  110
00860     PMEVCNTR7_EL0     = 0xdf47, // 11  011  1110  1000  111
00861     PMEVCNTR8_EL0     = 0xdf48, // 11  011  1110  1001  000
00862     PMEVCNTR9_EL0     = 0xdf49, // 11  011  1110  1001  001
00863     PMEVCNTR10_EL0    = 0xdf4a, // 11  011  1110  1001  010
00864     PMEVCNTR11_EL0    = 0xdf4b, // 11  011  1110  1001  011
00865     PMEVCNTR12_EL0    = 0xdf4c, // 11  011  1110  1001  100
00866     PMEVCNTR13_EL0    = 0xdf4d, // 11  011  1110  1001  101
00867     PMEVCNTR14_EL0    = 0xdf4e, // 11  011  1110  1001  110
00868     PMEVCNTR15_EL0    = 0xdf4f, // 11  011  1110  1001  111
00869     PMEVCNTR16_EL0    = 0xdf50, // 11  011  1110  1010  000
00870     PMEVCNTR17_EL0    = 0xdf51, // 11  011  1110  1010  001
00871     PMEVCNTR18_EL0    = 0xdf52, // 11  011  1110  1010  010
00872     PMEVCNTR19_EL0    = 0xdf53, // 11  011  1110  1010  011
00873     PMEVCNTR20_EL0    = 0xdf54, // 11  011  1110  1010  100
00874     PMEVCNTR21_EL0    = 0xdf55, // 11  011  1110  1010  101
00875     PMEVCNTR22_EL0    = 0xdf56, // 11  011  1110  1010  110
00876     PMEVCNTR23_EL0    = 0xdf57, // 11  011  1110  1010  111
00877     PMEVCNTR24_EL0    = 0xdf58, // 11  011  1110  1011  000
00878     PMEVCNTR25_EL0    = 0xdf59, // 11  011  1110  1011  001
00879     PMEVCNTR26_EL0    = 0xdf5a, // 11  011  1110  1011  010
00880     PMEVCNTR27_EL0    = 0xdf5b, // 11  011  1110  1011  011
00881     PMEVCNTR28_EL0    = 0xdf5c, // 11  011  1110  1011  100
00882     PMEVCNTR29_EL0    = 0xdf5d, // 11  011  1110  1011  101
00883     PMEVCNTR30_EL0    = 0xdf5e, // 11  011  1110  1011  110
00884     PMCCFILTR_EL0     = 0xdf7f, // 11  011  1110  1111  111
00885     PMEVTYPER0_EL0    = 0xdf60, // 11  011  1110  1100  000
00886     PMEVTYPER1_EL0    = 0xdf61, // 11  011  1110  1100  001
00887     PMEVTYPER2_EL0    = 0xdf62, // 11  011  1110  1100  010
00888     PMEVTYPER3_EL0    = 0xdf63, // 11  011  1110  1100  011
00889     PMEVTYPER4_EL0    = 0xdf64, // 11  011  1110  1100  100
00890     PMEVTYPER5_EL0    = 0xdf65, // 11  011  1110  1100  101
00891     PMEVTYPER6_EL0    = 0xdf66, // 11  011  1110  1100  110
00892     PMEVTYPER7_EL0    = 0xdf67, // 11  011  1110  1100  111
00893     PMEVTYPER8_EL0    = 0xdf68, // 11  011  1110  1101  000
00894     PMEVTYPER9_EL0    = 0xdf69, // 11  011  1110  1101  001
00895     PMEVTYPER10_EL0   = 0xdf6a, // 11  011  1110  1101  010
00896     PMEVTYPER11_EL0   = 0xdf6b, // 11  011  1110  1101  011
00897     PMEVTYPER12_EL0   = 0xdf6c, // 11  011  1110  1101  100
00898     PMEVTYPER13_EL0   = 0xdf6d, // 11  011  1110  1101  101
00899     PMEVTYPER14_EL0   = 0xdf6e, // 11  011  1110  1101  110
00900     PMEVTYPER15_EL0   = 0xdf6f, // 11  011  1110  1101  111
00901     PMEVTYPER16_EL0   = 0xdf70, // 11  011  1110  1110  000
00902     PMEVTYPER17_EL0   = 0xdf71, // 11  011  1110  1110  001
00903     PMEVTYPER18_EL0   = 0xdf72, // 11  011  1110  1110  010
00904     PMEVTYPER19_EL0   = 0xdf73, // 11  011  1110  1110  011
00905     PMEVTYPER20_EL0   = 0xdf74, // 11  011  1110  1110  100
00906     PMEVTYPER21_EL0   = 0xdf75, // 11  011  1110  1110  101
00907     PMEVTYPER22_EL0   = 0xdf76, // 11  011  1110  1110  110
00908     PMEVTYPER23_EL0   = 0xdf77, // 11  011  1110  1110  111
00909     PMEVTYPER24_EL0   = 0xdf78, // 11  011  1110  1111  000
00910     PMEVTYPER25_EL0   = 0xdf79, // 11  011  1110  1111  001
00911     PMEVTYPER26_EL0   = 0xdf7a, // 11  011  1110  1111  010
00912     PMEVTYPER27_EL0   = 0xdf7b, // 11  011  1110  1111  011
00913     PMEVTYPER28_EL0   = 0xdf7c, // 11  011  1110  1111  100
00914     PMEVTYPER29_EL0   = 0xdf7d, // 11  011  1110  1111  101
00915     PMEVTYPER30_EL0   = 0xdf7e, // 11  011  1110  1111  110
00916 
00917     // Trace registers
00918     TRCPRGCTLR        = 0x8808, // 10  001  0000  0001  000
00919     TRCPROCSELR       = 0x8810, // 10  001  0000  0010  000
00920     TRCCONFIGR        = 0x8820, // 10  001  0000  0100  000
00921     TRCAUXCTLR        = 0x8830, // 10  001  0000  0110  000
00922     TRCEVENTCTL0R     = 0x8840, // 10  001  0000  1000  000
00923     TRCEVENTCTL1R     = 0x8848, // 10  001  0000  1001  000
00924     TRCSTALLCTLR      = 0x8858, // 10  001  0000  1011  000
00925     TRCTSCTLR         = 0x8860, // 10  001  0000  1100  000
00926     TRCSYNCPR         = 0x8868, // 10  001  0000  1101  000
00927     TRCCCCTLR         = 0x8870, // 10  001  0000  1110  000
00928     TRCBBCTLR         = 0x8878, // 10  001  0000  1111  000
00929     TRCTRACEIDR       = 0x8801, // 10  001  0000  0000  001
00930     TRCQCTLR          = 0x8809, // 10  001  0000  0001  001
00931     TRCVICTLR         = 0x8802, // 10  001  0000  0000  010
00932     TRCVIIECTLR       = 0x880a, // 10  001  0000  0001  010
00933     TRCVISSCTLR       = 0x8812, // 10  001  0000  0010  010
00934     TRCVIPCSSCTLR     = 0x881a, // 10  001  0000  0011  010
00935     TRCVDCTLR         = 0x8842, // 10  001  0000  1000  010
00936     TRCVDSACCTLR      = 0x884a, // 10  001  0000  1001  010
00937     TRCVDARCCTLR      = 0x8852, // 10  001  0000  1010  010
00938     TRCSEQEVR0        = 0x8804, // 10  001  0000  0000  100
00939     TRCSEQEVR1        = 0x880c, // 10  001  0000  0001  100
00940     TRCSEQEVR2        = 0x8814, // 10  001  0000  0010  100
00941     TRCSEQRSTEVR      = 0x8834, // 10  001  0000  0110  100
00942     TRCSEQSTR         = 0x883c, // 10  001  0000  0111  100
00943     TRCEXTINSELR      = 0x8844, // 10  001  0000  1000  100
00944     TRCCNTRLDVR0      = 0x8805, // 10  001  0000  0000  101
00945     TRCCNTRLDVR1      = 0x880d, // 10  001  0000  0001  101
00946     TRCCNTRLDVR2      = 0x8815, // 10  001  0000  0010  101
00947     TRCCNTRLDVR3      = 0x881d, // 10  001  0000  0011  101
00948     TRCCNTCTLR0       = 0x8825, // 10  001  0000  0100  101
00949     TRCCNTCTLR1       = 0x882d, // 10  001  0000  0101  101
00950     TRCCNTCTLR2       = 0x8835, // 10  001  0000  0110  101
00951     TRCCNTCTLR3       = 0x883d, // 10  001  0000  0111  101
00952     TRCCNTVR0         = 0x8845, // 10  001  0000  1000  101
00953     TRCCNTVR1         = 0x884d, // 10  001  0000  1001  101
00954     TRCCNTVR2         = 0x8855, // 10  001  0000  1010  101
00955     TRCCNTVR3         = 0x885d, // 10  001  0000  1011  101
00956     TRCIMSPEC0        = 0x8807, // 10  001  0000  0000  111
00957     TRCIMSPEC1        = 0x880f, // 10  001  0000  0001  111
00958     TRCIMSPEC2        = 0x8817, // 10  001  0000  0010  111
00959     TRCIMSPEC3        = 0x881f, // 10  001  0000  0011  111
00960     TRCIMSPEC4        = 0x8827, // 10  001  0000  0100  111
00961     TRCIMSPEC5        = 0x882f, // 10  001  0000  0101  111
00962     TRCIMSPEC6        = 0x8837, // 10  001  0000  0110  111
00963     TRCIMSPEC7        = 0x883f, // 10  001  0000  0111  111
00964     TRCRSCTLR2        = 0x8890, // 10  001  0001  0010  000
00965     TRCRSCTLR3        = 0x8898, // 10  001  0001  0011  000
00966     TRCRSCTLR4        = 0x88a0, // 10  001  0001  0100  000
00967     TRCRSCTLR5        = 0x88a8, // 10  001  0001  0101  000
00968     TRCRSCTLR6        = 0x88b0, // 10  001  0001  0110  000
00969     TRCRSCTLR7        = 0x88b8, // 10  001  0001  0111  000
00970     TRCRSCTLR8        = 0x88c0, // 10  001  0001  1000  000
00971     TRCRSCTLR9        = 0x88c8, // 10  001  0001  1001  000
00972     TRCRSCTLR10       = 0x88d0, // 10  001  0001  1010  000
00973     TRCRSCTLR11       = 0x88d8, // 10  001  0001  1011  000
00974     TRCRSCTLR12       = 0x88e0, // 10  001  0001  1100  000
00975     TRCRSCTLR13       = 0x88e8, // 10  001  0001  1101  000
00976     TRCRSCTLR14       = 0x88f0, // 10  001  0001  1110  000
00977     TRCRSCTLR15       = 0x88f8, // 10  001  0001  1111  000
00978     TRCRSCTLR16       = 0x8881, // 10  001  0001  0000  001
00979     TRCRSCTLR17       = 0x8889, // 10  001  0001  0001  001
00980     TRCRSCTLR18       = 0x8891, // 10  001  0001  0010  001
00981     TRCRSCTLR19       = 0x8899, // 10  001  0001  0011  001
00982     TRCRSCTLR20       = 0x88a1, // 10  001  0001  0100  001
00983     TRCRSCTLR21       = 0x88a9, // 10  001  0001  0101  001
00984     TRCRSCTLR22       = 0x88b1, // 10  001  0001  0110  001
00985     TRCRSCTLR23       = 0x88b9, // 10  001  0001  0111  001
00986     TRCRSCTLR24       = 0x88c1, // 10  001  0001  1000  001
00987     TRCRSCTLR25       = 0x88c9, // 10  001  0001  1001  001
00988     TRCRSCTLR26       = 0x88d1, // 10  001  0001  1010  001
00989     TRCRSCTLR27       = 0x88d9, // 10  001  0001  1011  001
00990     TRCRSCTLR28       = 0x88e1, // 10  001  0001  1100  001
00991     TRCRSCTLR29       = 0x88e9, // 10  001  0001  1101  001
00992     TRCRSCTLR30       = 0x88f1, // 10  001  0001  1110  001
00993     TRCRSCTLR31       = 0x88f9, // 10  001  0001  1111  001
00994     TRCSSCCR0         = 0x8882, // 10  001  0001  0000  010
00995     TRCSSCCR1         = 0x888a, // 10  001  0001  0001  010
00996     TRCSSCCR2         = 0x8892, // 10  001  0001  0010  010
00997     TRCSSCCR3         = 0x889a, // 10  001  0001  0011  010
00998     TRCSSCCR4         = 0x88a2, // 10  001  0001  0100  010
00999     TRCSSCCR5         = 0x88aa, // 10  001  0001  0101  010
01000     TRCSSCCR6         = 0x88b2, // 10  001  0001  0110  010
01001     TRCSSCCR7         = 0x88ba, // 10  001  0001  0111  010
01002     TRCSSCSR0         = 0x88c2, // 10  001  0001  1000  010
01003     TRCSSCSR1         = 0x88ca, // 10  001  0001  1001  010
01004     TRCSSCSR2         = 0x88d2, // 10  001  0001  1010  010
01005     TRCSSCSR3         = 0x88da, // 10  001  0001  1011  010
01006     TRCSSCSR4         = 0x88e2, // 10  001  0001  1100  010
01007     TRCSSCSR5         = 0x88ea, // 10  001  0001  1101  010
01008     TRCSSCSR6         = 0x88f2, // 10  001  0001  1110  010
01009     TRCSSCSR7         = 0x88fa, // 10  001  0001  1111  010
01010     TRCSSPCICR0       = 0x8883, // 10  001  0001  0000  011
01011     TRCSSPCICR1       = 0x888b, // 10  001  0001  0001  011
01012     TRCSSPCICR2       = 0x8893, // 10  001  0001  0010  011
01013     TRCSSPCICR3       = 0x889b, // 10  001  0001  0011  011
01014     TRCSSPCICR4       = 0x88a3, // 10  001  0001  0100  011
01015     TRCSSPCICR5       = 0x88ab, // 10  001  0001  0101  011
01016     TRCSSPCICR6       = 0x88b3, // 10  001  0001  0110  011
01017     TRCSSPCICR7       = 0x88bb, // 10  001  0001  0111  011
01018     TRCPDCR           = 0x88a4, // 10  001  0001  0100  100
01019     TRCACVR0          = 0x8900, // 10  001  0010  0000  000
01020     TRCACVR1          = 0x8910, // 10  001  0010  0010  000
01021     TRCACVR2          = 0x8920, // 10  001  0010  0100  000
01022     TRCACVR3          = 0x8930, // 10  001  0010  0110  000
01023     TRCACVR4          = 0x8940, // 10  001  0010  1000  000
01024     TRCACVR5          = 0x8950, // 10  001  0010  1010  000
01025     TRCACVR6          = 0x8960, // 10  001  0010  1100  000
01026     TRCACVR7          = 0x8970, // 10  001  0010  1110  000
01027     TRCACVR8          = 0x8901, // 10  001  0010  0000  001
01028     TRCACVR9          = 0x8911, // 10  001  0010  0010  001
01029     TRCACVR10         = 0x8921, // 10  001  0010  0100  001
01030     TRCACVR11         = 0x8931, // 10  001  0010  0110  001
01031     TRCACVR12         = 0x8941, // 10  001  0010  1000  001
01032     TRCACVR13         = 0x8951, // 10  001  0010  1010  001
01033     TRCACVR14         = 0x8961, // 10  001  0010  1100  001
01034     TRCACVR15         = 0x8971, // 10  001  0010  1110  001
01035     TRCACATR0         = 0x8902, // 10  001  0010  0000  010
01036     TRCACATR1         = 0x8912, // 10  001  0010  0010  010
01037     TRCACATR2         = 0x8922, // 10  001  0010  0100  010
01038     TRCACATR3         = 0x8932, // 10  001  0010  0110  010
01039     TRCACATR4         = 0x8942, // 10  001  0010  1000  010
01040     TRCACATR5         = 0x8952, // 10  001  0010  1010  010
01041     TRCACATR6         = 0x8962, // 10  001  0010  1100  010
01042     TRCACATR7         = 0x8972, // 10  001  0010  1110  010
01043     TRCACATR8         = 0x8903, // 10  001  0010  0000  011
01044     TRCACATR9         = 0x8913, // 10  001  0010  0010  011
01045     TRCACATR10        = 0x8923, // 10  001  0010  0100  011
01046     TRCACATR11        = 0x8933, // 10  001  0010  0110  011
01047     TRCACATR12        = 0x8943, // 10  001  0010  1000  011
01048     TRCACATR13        = 0x8953, // 10  001  0010  1010  011
01049     TRCACATR14        = 0x8963, // 10  001  0010  1100  011
01050     TRCACATR15        = 0x8973, // 10  001  0010  1110  011
01051     TRCDVCVR0         = 0x8904, // 10  001  0010  0000  100
01052     TRCDVCVR1         = 0x8924, // 10  001  0010  0100  100
01053     TRCDVCVR2         = 0x8944, // 10  001  0010  1000  100
01054     TRCDVCVR3         = 0x8964, // 10  001  0010  1100  100
01055     TRCDVCVR4         = 0x8905, // 10  001  0010  0000  101
01056     TRCDVCVR5         = 0x8925, // 10  001  0010  0100  101
01057     TRCDVCVR6         = 0x8945, // 10  001  0010  1000  101
01058     TRCDVCVR7         = 0x8965, // 10  001  0010  1100  101
01059     TRCDVCMR0         = 0x8906, // 10  001  0010  0000  110
01060     TRCDVCMR1         = 0x8926, // 10  001  0010  0100  110
01061     TRCDVCMR2         = 0x8946, // 10  001  0010  1000  110
01062     TRCDVCMR3         = 0x8966, // 10  001  0010  1100  110
01063     TRCDVCMR4         = 0x8907, // 10  001  0010  0000  111
01064     TRCDVCMR5         = 0x8927, // 10  001  0010  0100  111
01065     TRCDVCMR6         = 0x8947, // 10  001  0010  1000  111
01066     TRCDVCMR7         = 0x8967, // 10  001  0010  1100  111
01067     TRCCIDCVR0        = 0x8980, // 10  001  0011  0000  000
01068     TRCCIDCVR1        = 0x8990, // 10  001  0011  0010  000
01069     TRCCIDCVR2        = 0x89a0, // 10  001  0011  0100  000
01070     TRCCIDCVR3        = 0x89b0, // 10  001  0011  0110  000
01071     TRCCIDCVR4        = 0x89c0, // 10  001  0011  1000  000
01072     TRCCIDCVR5        = 0x89d0, // 10  001  0011  1010  000
01073     TRCCIDCVR6        = 0x89e0, // 10  001  0011  1100  000
01074     TRCCIDCVR7        = 0x89f0, // 10  001  0011  1110  000
01075     TRCVMIDCVR0       = 0x8981, // 10  001  0011  0000  001
01076     TRCVMIDCVR1       = 0x8991, // 10  001  0011  0010  001
01077     TRCVMIDCVR2       = 0x89a1, // 10  001  0011  0100  001
01078     TRCVMIDCVR3       = 0x89b1, // 10  001  0011  0110  001
01079     TRCVMIDCVR4       = 0x89c1, // 10  001  0011  1000  001
01080     TRCVMIDCVR5       = 0x89d1, // 10  001  0011  1010  001
01081     TRCVMIDCVR6       = 0x89e1, // 10  001  0011  1100  001
01082     TRCVMIDCVR7       = 0x89f1, // 10  001  0011  1110  001
01083     TRCCIDCCTLR0      = 0x8982, // 10  001  0011  0000  010
01084     TRCCIDCCTLR1      = 0x898a, // 10  001  0011  0001  010
01085     TRCVMIDCCTLR0     = 0x8992, // 10  001  0011  0010  010
01086     TRCVMIDCCTLR1     = 0x899a, // 10  001  0011  0011  010
01087     TRCITCTRL         = 0x8b84, // 10  001  0111  0000  100
01088     TRCCLAIMSET       = 0x8bc6, // 10  001  0111  1000  110
01089     TRCCLAIMCLR       = 0x8bce, // 10  001  0111  1001  110
01090 
01091     // GICv3 registers
01092     ICC_BPR1_EL1      = 0xc663, // 11  000  1100  1100  011
01093     ICC_BPR0_EL1      = 0xc643, // 11  000  1100  1000  011
01094     ICC_PMR_EL1       = 0xc230, // 11  000  0100  0110  000
01095     ICC_CTLR_EL1      = 0xc664, // 11  000  1100  1100  100
01096     ICC_CTLR_EL3      = 0xf664, // 11  110  1100  1100  100
01097     ICC_SRE_EL1       = 0xc665, // 11  000  1100  1100  101
01098     ICC_SRE_EL2       = 0xe64d, // 11  100  1100  1001  101
01099     ICC_SRE_EL3       = 0xf665, // 11  110  1100  1100  101
01100     ICC_IGRPEN0_EL1   = 0xc666, // 11  000  1100  1100  110
01101     ICC_IGRPEN1_EL1   = 0xc667, // 11  000  1100  1100  111
01102     ICC_IGRPEN1_EL3   = 0xf667, // 11  110  1100  1100  111
01103     ICC_SEIEN_EL1     = 0xc668, // 11  000  1100  1101  000
01104     ICC_AP0R0_EL1     = 0xc644, // 11  000  1100  1000  100
01105     ICC_AP0R1_EL1     = 0xc645, // 11  000  1100  1000  101
01106     ICC_AP0R2_EL1     = 0xc646, // 11  000  1100  1000  110
01107     ICC_AP0R3_EL1     = 0xc647, // 11  000  1100  1000  111
01108     ICC_AP1R0_EL1     = 0xc648, // 11  000  1100  1001  000
01109     ICC_AP1R1_EL1     = 0xc649, // 11  000  1100  1001  001
01110     ICC_AP1R2_EL1     = 0xc64a, // 11  000  1100  1001  010
01111     ICC_AP1R3_EL1     = 0xc64b, // 11  000  1100  1001  011
01112     ICH_AP0R0_EL2     = 0xe640, // 11  100  1100  1000  000
01113     ICH_AP0R1_EL2     = 0xe641, // 11  100  1100  1000  001
01114     ICH_AP0R2_EL2     = 0xe642, // 11  100  1100  1000  010
01115     ICH_AP0R3_EL2     = 0xe643, // 11  100  1100  1000  011
01116     ICH_AP1R0_EL2     = 0xe648, // 11  100  1100  1001  000
01117     ICH_AP1R1_EL2     = 0xe649, // 11  100  1100  1001  001
01118     ICH_AP1R2_EL2     = 0xe64a, // 11  100  1100  1001  010
01119     ICH_AP1R3_EL2     = 0xe64b, // 11  100  1100  1001  011
01120     ICH_HCR_EL2       = 0xe658, // 11  100  1100  1011  000
01121     ICH_MISR_EL2      = 0xe65a, // 11  100  1100  1011  010
01122     ICH_VMCR_EL2      = 0xe65f, // 11  100  1100  1011  111
01123     ICH_VSEIR_EL2     = 0xe64c, // 11  100  1100  1001  100
01124     ICH_LR0_EL2       = 0xe660, // 11  100  1100  1100  000
01125     ICH_LR1_EL2       = 0xe661, // 11  100  1100  1100  001
01126     ICH_LR2_EL2       = 0xe662, // 11  100  1100  1100  010
01127     ICH_LR3_EL2       = 0xe663, // 11  100  1100  1100  011
01128     ICH_LR4_EL2       = 0xe664, // 11  100  1100  1100  100
01129     ICH_LR5_EL2       = 0xe665, // 11  100  1100  1100  101
01130     ICH_LR6_EL2       = 0xe666, // 11  100  1100  1100  110
01131     ICH_LR7_EL2       = 0xe667, // 11  100  1100  1100  111
01132     ICH_LR8_EL2       = 0xe668, // 11  100  1100  1101  000
01133     ICH_LR9_EL2       = 0xe669, // 11  100  1100  1101  001
01134     ICH_LR10_EL2      = 0xe66a, // 11  100  1100  1101  010
01135     ICH_LR11_EL2      = 0xe66b, // 11  100  1100  1101  011
01136     ICH_LR12_EL2      = 0xe66c, // 11  100  1100  1101  100
01137     ICH_LR13_EL2      = 0xe66d, // 11  100  1100  1101  101
01138     ICH_LR14_EL2      = 0xe66e, // 11  100  1100  1101  110
01139     ICH_LR15_EL2      = 0xe66f, // 11  100  1100  1101  111
01140 
01141     // v8.1a "Privileged Access Never" extension-specific system registers
01142     PAN               = 0xc213, // 11  000  0100  0010  011
01143 
01144     // v8.1a "Limited Ordering Regions" extension-specific system registers
01145     LORSA_EL1         = 0xc520, // 11  000  1010  0100  000
01146     LOREA_EL1         = 0xc521, // 11  000  1010  0100  001
01147     LORN_EL1          = 0xc522, // 11  000  1010  0100  010
01148     LORC_EL1          = 0xc523, // 11  000  1010  0100  011
01149     LORID_EL1         = 0xc527, // 11  000  1010  0100  111
01150 
01151     // v8.1a "Virtualization host extensions" system registers
01152     TTBR1_EL2         = 0xe101, // 11  100  0010  0000  001
01153     CONTEXTIDR_EL2    = 0xe681, // 11  100  1101  0000  001
01154     CNTHV_TVAL_EL2    = 0xe718, // 11  100  1110  0011  000
01155     CNTHV_CVAL_EL2    = 0xe71a, // 11  100  1110  0011  010
01156     CNTHV_CTL_EL2     = 0xe719, // 11  100  1110  0011  001
01157     SCTLR_EL12        = 0xe880, // 11  101  0001  0000  000
01158     CPACR_EL12        = 0xe882, // 11  101  0001  0000  010
01159     TTBR0_EL12        = 0xe900, // 11  101  0010  0000  000
01160     TTBR1_EL12        = 0xe901, // 11  101  0010  0000  001
01161     TCR_EL12          = 0xe902, // 11  101  0010  0000  010
01162     AFSR0_EL12        = 0xea88, // 11  101  0101  0001  000
01163     AFSR1_EL12        = 0xea89, // 11  101  0101  0001  001
01164     ESR_EL12          = 0xea90, // 11  101  0101  0010  000
01165     FAR_EL12          = 0xeb00, // 11  101  0110  0000  000
01166     MAIR_EL12         = 0xed10, // 11  101  1010  0010  000
01167     AMAIR_EL12        = 0xed18, // 11  101  1010  0011  000
01168     VBAR_EL12         = 0xee00, // 11  101  1100  0000  000
01169     CONTEXTIDR_EL12   = 0xee81, // 11  101  1101  0000  001
01170     CNTKCTL_EL12      = 0xef08, // 11  101  1110  0001  000
01171     CNTP_TVAL_EL02    = 0xef10, // 11  101  1110  0010  000
01172     CNTP_CTL_EL02     = 0xef11, // 11  101  1110  0010  001
01173     CNTP_CVAL_EL02    = 0xef12, // 11  101  1110  0010  010
01174     CNTV_TVAL_EL02    = 0xef18, // 11  101  1110  0011  000
01175     CNTV_CTL_EL02     = 0xef19, // 11  101  1110  0011  001
01176     CNTV_CVAL_EL02    = 0xef1a, // 11  101  1110  0011  010
01177     SPSR_EL12         = 0xea00, // 11  101  0100  0000  000
01178     ELR_EL12          = 0xea01, // 11  101  0100  0000  001
01179 
01180     // Cyclone specific system registers
01181     CPM_IOACC_CTL_EL3 = 0xff90,
01182   };
01183 
01184   // Note that these do not inherit from AArch64NamedImmMapper. This class is
01185   // sufficiently different in its behaviour that I don't believe it's worth
01186   // burdening the common AArch64NamedImmMapper with abstractions only needed in
01187   // this one case.
01188   struct SysRegMapper {
01189     static const AArch64NamedImmMapper::Mapping SysRegMappings[];
01190 
01191     const AArch64NamedImmMapper::Mapping *InstMappings;
01192     size_t NumInstMappings;
01193 
01194     SysRegMapper() { }
01195     uint32_t fromString(StringRef Name, uint64_t FeatureBits, bool &Valid) const;
01196     std::string toString(uint32_t Bits, uint64_t FeatureBits) const;
01197   };
01198 
01199   struct MSRMapper : SysRegMapper {
01200     static const AArch64NamedImmMapper::Mapping MSRMappings[];
01201     MSRMapper();
01202   };
01203 
01204   struct MRSMapper : SysRegMapper {
01205     static const AArch64NamedImmMapper::Mapping MRSMappings[];
01206     MRSMapper();
01207   };
01208 
01209   uint32_t ParseGenericRegister(StringRef Name, bool &Valid);
01210 }
01211 
01212 namespace AArch64TLBI {
01213   enum TLBIValues {
01214     Invalid = -1,          // Op0 Op1  CRn   CRm   Op2
01215     IPAS2E1IS    = 0x6401, // 01  100  1000  0000  001
01216     IPAS2LE1IS   = 0x6405, // 01  100  1000  0000  101
01217     VMALLE1IS    = 0x4418, // 01  000  1000  0011  000
01218     ALLE2IS      = 0x6418, // 01  100  1000  0011  000
01219     ALLE3IS      = 0x7418, // 01  110  1000  0011  000
01220     VAE1IS       = 0x4419, // 01  000  1000  0011  001
01221     VAE2IS       = 0x6419, // 01  100  1000  0011  001
01222     VAE3IS       = 0x7419, // 01  110  1000  0011  001
01223     ASIDE1IS     = 0x441a, // 01  000  1000  0011  010
01224     VAAE1IS      = 0x441b, // 01  000  1000  0011  011
01225     ALLE1IS      = 0x641c, // 01  100  1000  0011  100
01226     VALE1IS      = 0x441d, // 01  000  1000  0011  101
01227     VALE2IS      = 0x641d, // 01  100  1000  0011  101
01228     VALE3IS      = 0x741d, // 01  110  1000  0011  101
01229     VMALLS12E1IS = 0x641e, // 01  100  1000  0011  110
01230     VAALE1IS     = 0x441f, // 01  000  1000  0011  111
01231     IPAS2E1      = 0x6421, // 01  100  1000  0100  001
01232     IPAS2LE1     = 0x6425, // 01  100  1000  0100  101
01233     VMALLE1      = 0x4438, // 01  000  1000  0111  000
01234     ALLE2        = 0x6438, // 01  100  1000  0111  000
01235     ALLE3        = 0x7438, // 01  110  1000  0111  000
01236     VAE1         = 0x4439, // 01  000  1000  0111  001
01237     VAE2         = 0x6439, // 01  100  1000  0111  001
01238     VAE3         = 0x7439, // 01  110  1000  0111  001
01239     ASIDE1       = 0x443a, // 01  000  1000  0111  010
01240     VAAE1        = 0x443b, // 01  000  1000  0111  011
01241     ALLE1        = 0x643c, // 01  100  1000  0111  100
01242     VALE1        = 0x443d, // 01  000  1000  0111  101
01243     VALE2        = 0x643d, // 01  100  1000  0111  101
01244     VALE3        = 0x743d, // 01  110  1000  0111  101
01245     VMALLS12E1   = 0x643e, // 01  100  1000  0111  110
01246     VAALE1       = 0x443f  // 01  000  1000  0111  111
01247   };
01248 
01249   struct TLBIMapper : AArch64NamedImmMapper {
01250     const static Mapping TLBIMappings[];
01251 
01252     TLBIMapper();
01253   };
01254 
01255   static inline bool NeedsRegister(TLBIValues Val) {
01256     switch (Val) {
01257     case VMALLE1IS:
01258     case ALLE2IS:
01259     case ALLE3IS:
01260     case ALLE1IS:
01261     case VMALLS12E1IS:
01262     case VMALLE1:
01263     case ALLE2:
01264     case ALLE3:
01265     case ALLE1:
01266     case VMALLS12E1:
01267       return false;
01268     default:
01269       return true;
01270     }
01271   }
01272 } 
01273 
01274 namespace AArch64II {
01275   /// Target Operand Flag enum.
01276   enum TOF {
01277     //===------------------------------------------------------------------===//
01278     // AArch64 Specific MachineOperand flags.
01279 
01280     MO_NO_FLAG,
01281 
01282     MO_FRAGMENT = 0xf,
01283 
01284     /// MO_PAGE - A symbol operand with this flag represents the pc-relative
01285     /// offset of the 4K page containing the symbol.  This is used with the
01286     /// ADRP instruction.
01287     MO_PAGE = 1,
01288 
01289     /// MO_PAGEOFF - A symbol operand with this flag represents the offset of
01290     /// that symbol within a 4K page.  This offset is added to the page address
01291     /// to produce the complete address.
01292     MO_PAGEOFF = 2,
01293 
01294     /// MO_G3 - A symbol operand with this flag (granule 3) represents the high
01295     /// 16-bits of a 64-bit address, used in a MOVZ or MOVK instruction
01296     MO_G3 = 3,
01297 
01298     /// MO_G2 - A symbol operand with this flag (granule 2) represents the bits
01299     /// 32-47 of a 64-bit address, used in a MOVZ or MOVK instruction
01300     MO_G2 = 4,
01301 
01302     /// MO_G1 - A symbol operand with this flag (granule 1) represents the bits
01303     /// 16-31 of a 64-bit address, used in a MOVZ or MOVK instruction
01304     MO_G1 = 5,
01305 
01306     /// MO_G0 - A symbol operand with this flag (granule 0) represents the bits
01307     /// 0-15 of a 64-bit address, used in a MOVZ or MOVK instruction
01308     MO_G0 = 6,
01309 
01310     /// MO_HI12 - This flag indicates that a symbol operand represents the bits
01311     /// 13-24 of a 64-bit address, used in a arithmetic immediate-shifted-left-
01312     /// by-12-bits instruction.
01313     MO_HI12 = 7,
01314 
01315     /// MO_GOT - This flag indicates that a symbol operand represents the
01316     /// address of the GOT entry for the symbol, rather than the address of
01317     /// the symbol itself.
01318     MO_GOT = 0x10,
01319 
01320     /// MO_NC - Indicates whether the linker is expected to check the symbol
01321     /// reference for overflow. For example in an ADRP/ADD pair of relocations
01322     /// the ADRP usually does check, but not the ADD.
01323     MO_NC = 0x20,
01324 
01325     /// MO_TLS - Indicates that the operand being accessed is some kind of
01326     /// thread-local symbol. On Darwin, only one type of thread-local access
01327     /// exists (pre linker-relaxation), but on ELF the TLSModel used for the
01328     /// referee will affect interpretation.
01329     MO_TLS = 0x40,
01330 
01331     /// MO_CONSTPOOL - This flag indicates that a symbol operand represents
01332     /// the address of a constant pool entry for the symbol, rather than the
01333     /// address of the symbol itself.
01334     MO_CONSTPOOL = 0x80
01335   };
01336 } // end namespace AArch64II
01337 
01338 } // end namespace llvm
01339 
01340 #endif