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AArch64BaseInfo.h
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00001 //===-- AArch64BaseInfo.h - Top level definitions for AArch64 ---*- C++ -*-===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file contains small standalone helper functions and enum definitions for
00011 // the AArch64 target useful for the compiler back-end and the MC libraries.
00012 // As such, it deliberately does not include references to LLVM core
00013 // code gen types, passes, etc..
00014 //
00015 //===----------------------------------------------------------------------===//
00016 
00017 #ifndef LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H
00018 #define LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H
00019 
00020 // FIXME: Is it easiest to fix this layering violation by moving the .inc
00021 // #includes from AArch64MCTargetDesc.h to here?
00022 #include "MCTargetDesc/AArch64MCTargetDesc.h" // For AArch64::X0 and friends.
00023 #include "llvm/ADT/STLExtras.h"
00024 #include "llvm/ADT/StringSwitch.h"
00025 #include "llvm/MC/SubtargetFeature.h"
00026 #include "llvm/Support/ErrorHandling.h"
00027 
00028 namespace llvm {
00029 
00030 inline static unsigned getWRegFromXReg(unsigned Reg) {
00031   switch (Reg) {
00032   case AArch64::X0: return AArch64::W0;
00033   case AArch64::X1: return AArch64::W1;
00034   case AArch64::X2: return AArch64::W2;
00035   case AArch64::X3: return AArch64::W3;
00036   case AArch64::X4: return AArch64::W4;
00037   case AArch64::X5: return AArch64::W5;
00038   case AArch64::X6: return AArch64::W6;
00039   case AArch64::X7: return AArch64::W7;
00040   case AArch64::X8: return AArch64::W8;
00041   case AArch64::X9: return AArch64::W9;
00042   case AArch64::X10: return AArch64::W10;
00043   case AArch64::X11: return AArch64::W11;
00044   case AArch64::X12: return AArch64::W12;
00045   case AArch64::X13: return AArch64::W13;
00046   case AArch64::X14: return AArch64::W14;
00047   case AArch64::X15: return AArch64::W15;
00048   case AArch64::X16: return AArch64::W16;
00049   case AArch64::X17: return AArch64::W17;
00050   case AArch64::X18: return AArch64::W18;
00051   case AArch64::X19: return AArch64::W19;
00052   case AArch64::X20: return AArch64::W20;
00053   case AArch64::X21: return AArch64::W21;
00054   case AArch64::X22: return AArch64::W22;
00055   case AArch64::X23: return AArch64::W23;
00056   case AArch64::X24: return AArch64::W24;
00057   case AArch64::X25: return AArch64::W25;
00058   case AArch64::X26: return AArch64::W26;
00059   case AArch64::X27: return AArch64::W27;
00060   case AArch64::X28: return AArch64::W28;
00061   case AArch64::FP: return AArch64::W29;
00062   case AArch64::LR: return AArch64::W30;
00063   case AArch64::SP: return AArch64::WSP;
00064   case AArch64::XZR: return AArch64::WZR;
00065   }
00066   // For anything else, return it unchanged.
00067   return Reg;
00068 }
00069 
00070 inline static unsigned getXRegFromWReg(unsigned Reg) {
00071   switch (Reg) {
00072   case AArch64::W0: return AArch64::X0;
00073   case AArch64::W1: return AArch64::X1;
00074   case AArch64::W2: return AArch64::X2;
00075   case AArch64::W3: return AArch64::X3;
00076   case AArch64::W4: return AArch64::X4;
00077   case AArch64::W5: return AArch64::X5;
00078   case AArch64::W6: return AArch64::X6;
00079   case AArch64::W7: return AArch64::X7;
00080   case AArch64::W8: return AArch64::X8;
00081   case AArch64::W9: return AArch64::X9;
00082   case AArch64::W10: return AArch64::X10;
00083   case AArch64::W11: return AArch64::X11;
00084   case AArch64::W12: return AArch64::X12;
00085   case AArch64::W13: return AArch64::X13;
00086   case AArch64::W14: return AArch64::X14;
00087   case AArch64::W15: return AArch64::X15;
00088   case AArch64::W16: return AArch64::X16;
00089   case AArch64::W17: return AArch64::X17;
00090   case AArch64::W18: return AArch64::X18;
00091   case AArch64::W19: return AArch64::X19;
00092   case AArch64::W20: return AArch64::X20;
00093   case AArch64::W21: return AArch64::X21;
00094   case AArch64::W22: return AArch64::X22;
00095   case AArch64::W23: return AArch64::X23;
00096   case AArch64::W24: return AArch64::X24;
00097   case AArch64::W25: return AArch64::X25;
00098   case AArch64::W26: return AArch64::X26;
00099   case AArch64::W27: return AArch64::X27;
00100   case AArch64::W28: return AArch64::X28;
00101   case AArch64::W29: return AArch64::FP;
00102   case AArch64::W30: return AArch64::LR;
00103   case AArch64::WSP: return AArch64::SP;
00104   case AArch64::WZR: return AArch64::XZR;
00105   }
00106   // For anything else, return it unchanged.
00107   return Reg;
00108 }
00109 
00110 static inline unsigned getBRegFromDReg(unsigned Reg) {
00111   switch (Reg) {
00112   case AArch64::D0:  return AArch64::B0;
00113   case AArch64::D1:  return AArch64::B1;
00114   case AArch64::D2:  return AArch64::B2;
00115   case AArch64::D3:  return AArch64::B3;
00116   case AArch64::D4:  return AArch64::B4;
00117   case AArch64::D5:  return AArch64::B5;
00118   case AArch64::D6:  return AArch64::B6;
00119   case AArch64::D7:  return AArch64::B7;
00120   case AArch64::D8:  return AArch64::B8;
00121   case AArch64::D9:  return AArch64::B9;
00122   case AArch64::D10: return AArch64::B10;
00123   case AArch64::D11: return AArch64::B11;
00124   case AArch64::D12: return AArch64::B12;
00125   case AArch64::D13: return AArch64::B13;
00126   case AArch64::D14: return AArch64::B14;
00127   case AArch64::D15: return AArch64::B15;
00128   case AArch64::D16: return AArch64::B16;
00129   case AArch64::D17: return AArch64::B17;
00130   case AArch64::D18: return AArch64::B18;
00131   case AArch64::D19: return AArch64::B19;
00132   case AArch64::D20: return AArch64::B20;
00133   case AArch64::D21: return AArch64::B21;
00134   case AArch64::D22: return AArch64::B22;
00135   case AArch64::D23: return AArch64::B23;
00136   case AArch64::D24: return AArch64::B24;
00137   case AArch64::D25: return AArch64::B25;
00138   case AArch64::D26: return AArch64::B26;
00139   case AArch64::D27: return AArch64::B27;
00140   case AArch64::D28: return AArch64::B28;
00141   case AArch64::D29: return AArch64::B29;
00142   case AArch64::D30: return AArch64::B30;
00143   case AArch64::D31: return AArch64::B31;
00144   }
00145   // For anything else, return it unchanged.
00146   return Reg;
00147 }
00148 
00149 
00150 static inline unsigned getDRegFromBReg(unsigned Reg) {
00151   switch (Reg) {
00152   case AArch64::B0:  return AArch64::D0;
00153   case AArch64::B1:  return AArch64::D1;
00154   case AArch64::B2:  return AArch64::D2;
00155   case AArch64::B3:  return AArch64::D3;
00156   case AArch64::B4:  return AArch64::D4;
00157   case AArch64::B5:  return AArch64::D5;
00158   case AArch64::B6:  return AArch64::D6;
00159   case AArch64::B7:  return AArch64::D7;
00160   case AArch64::B8:  return AArch64::D8;
00161   case AArch64::B9:  return AArch64::D9;
00162   case AArch64::B10: return AArch64::D10;
00163   case AArch64::B11: return AArch64::D11;
00164   case AArch64::B12: return AArch64::D12;
00165   case AArch64::B13: return AArch64::D13;
00166   case AArch64::B14: return AArch64::D14;
00167   case AArch64::B15: return AArch64::D15;
00168   case AArch64::B16: return AArch64::D16;
00169   case AArch64::B17: return AArch64::D17;
00170   case AArch64::B18: return AArch64::D18;
00171   case AArch64::B19: return AArch64::D19;
00172   case AArch64::B20: return AArch64::D20;
00173   case AArch64::B21: return AArch64::D21;
00174   case AArch64::B22: return AArch64::D22;
00175   case AArch64::B23: return AArch64::D23;
00176   case AArch64::B24: return AArch64::D24;
00177   case AArch64::B25: return AArch64::D25;
00178   case AArch64::B26: return AArch64::D26;
00179   case AArch64::B27: return AArch64::D27;
00180   case AArch64::B28: return AArch64::D28;
00181   case AArch64::B29: return AArch64::D29;
00182   case AArch64::B30: return AArch64::D30;
00183   case AArch64::B31: return AArch64::D31;
00184   }
00185   // For anything else, return it unchanged.
00186   return Reg;
00187 }
00188 
00189 namespace AArch64CC {
00190 
00191 // The CondCodes constants map directly to the 4-bit encoding of the condition
00192 // field for predicated instructions.
00193 enum CondCode {  // Meaning (integer)          Meaning (floating-point)
00194   EQ = 0x0,      // Equal                      Equal
00195   NE = 0x1,      // Not equal                  Not equal, or unordered
00196   HS = 0x2,      // Unsigned higher or same    >, ==, or unordered
00197   LO = 0x3,      // Unsigned lower             Less than
00198   MI = 0x4,      // Minus, negative            Less than
00199   PL = 0x5,      // Plus, positive or zero     >, ==, or unordered
00200   VS = 0x6,      // Overflow                   Unordered
00201   VC = 0x7,      // No overflow                Not unordered
00202   HI = 0x8,      // Unsigned higher            Greater than, or unordered
00203   LS = 0x9,      // Unsigned lower or same     Less than or equal
00204   GE = 0xa,      // Greater than or equal      Greater than or equal
00205   LT = 0xb,      // Less than                  Less than, or unordered
00206   GT = 0xc,      // Greater than               Greater than
00207   LE = 0xd,      // Less than or equal         <, ==, or unordered
00208   AL = 0xe,      // Always (unconditional)     Always (unconditional)
00209   NV = 0xf,      // Always (unconditional)     Always (unconditional)
00210   // Note the NV exists purely to disassemble 0b1111. Execution is "always".
00211   Invalid
00212 };
00213 
00214 inline static const char *getCondCodeName(CondCode Code) {
00215   switch (Code) {
00216   default: llvm_unreachable("Unknown condition code");
00217   case EQ:  return "eq";
00218   case NE:  return "ne";
00219   case HS:  return "hs";
00220   case LO:  return "lo";
00221   case MI:  return "mi";
00222   case PL:  return "pl";
00223   case VS:  return "vs";
00224   case VC:  return "vc";
00225   case HI:  return "hi";
00226   case LS:  return "ls";
00227   case GE:  return "ge";
00228   case LT:  return "lt";
00229   case GT:  return "gt";
00230   case LE:  return "le";
00231   case AL:  return "al";
00232   case NV:  return "nv";
00233   }
00234 }
00235 
00236 inline static CondCode getInvertedCondCode(CondCode Code) {
00237   // To reverse a condition it's necessary to only invert the low bit:
00238 
00239   return static_cast<CondCode>(static_cast<unsigned>(Code) ^ 0x1);
00240 }
00241 
00242 /// Given a condition code, return NZCV flags that would satisfy that condition.
00243 /// The flag bits are in the format expected by the ccmp instructions.
00244 /// Note that many different flag settings can satisfy a given condition code,
00245 /// this function just returns one of them.
00246 inline static unsigned getNZCVToSatisfyCondCode(CondCode Code) {
00247   // NZCV flags encoded as expected by ccmp instructions, ARMv8 ISA 5.5.7.
00248   enum { N = 8, Z = 4, C = 2, V = 1 };
00249   switch (Code) {
00250   default: llvm_unreachable("Unknown condition code");
00251   case EQ: return Z; // Z == 1
00252   case NE: return 0; // Z == 0
00253   case HS: return C; // C == 1
00254   case LO: return 0; // C == 0
00255   case MI: return N; // N == 1
00256   case PL: return 0; // N == 0
00257   case VS: return V; // V == 1
00258   case VC: return 0; // V == 0
00259   case HI: return C; // C == 1 && Z == 0
00260   case LS: return 0; // C == 0 || Z == 1
00261   case GE: return 0; // N == V
00262   case LT: return N; // N != V
00263   case GT: return 0; // Z == 0 && N == V
00264   case LE: return Z; // Z == 1 || N != V
00265   }
00266 }
00267 } // end namespace AArch64CC
00268 
00269 /// Instances of this class can perform bidirectional mapping from random
00270 /// identifier strings to operand encodings. For example "MSR" takes a named
00271 /// system-register which must be encoded somehow and decoded for printing. This
00272 /// central location means that the information for those transformations is not
00273 /// duplicated and remains in sync.
00274 ///
00275 /// FIXME: currently the algorithm is a completely unoptimised linear
00276 /// search. Obviously this could be improved, but we would probably want to work
00277 /// out just how often these instructions are emitted before working on it. It
00278 /// might even be optimal to just reorder the tables for the common instructions
00279 /// rather than changing the algorithm.
00280 struct AArch64NamedImmMapper {
00281   struct Mapping {
00282     const char *Name;
00283     uint32_t Value;
00284     // Set of features this mapping is available for
00285     // Zero value of FeatureBitSet means the mapping is always available
00286     FeatureBitset FeatureBitSet;
00287 
00288     bool isNameEqual(std::string Other, 
00289                      const FeatureBitset& FeatureBits) const {
00290       if (FeatureBitSet.any() && 
00291           (FeatureBitSet & FeatureBits).none())
00292         return false;
00293       return Name == Other;
00294     }
00295 
00296     bool isValueEqual(uint32_t Other, 
00297                       const FeatureBitset& FeatureBits) const {
00298       if (FeatureBitSet.any() && 
00299           (FeatureBitSet & FeatureBits).none())
00300         return false;
00301       return Value == Other;
00302     }
00303   };
00304 
00305   template<int N>
00306   AArch64NamedImmMapper(const Mapping (&Mappings)[N], uint32_t TooBigImm)
00307     : Mappings(&Mappings[0]), NumMappings(N), TooBigImm(TooBigImm) {}
00308 
00309   // Maps value to string, depending on availability for FeatureBits given
00310   StringRef toString(uint32_t Value, const FeatureBitset& FeatureBits,
00311                      bool &Valid) const;
00312   // Maps string to value, depending on availability for FeatureBits given
00313   uint32_t fromString(StringRef Name, const FeatureBitset& FeatureBits, 
00314                      bool &Valid) const;
00315 
00316   /// Many of the instructions allow an alternative assembly form consisting of
00317   /// a simple immediate. Currently the only valid forms are ranges [0, N) where
00318   /// N being 0 indicates no immediate syntax-form is allowed.
00319   bool validImm(uint32_t Value) const;
00320 protected:
00321   const Mapping *Mappings;
00322   size_t NumMappings;
00323   uint32_t TooBigImm;
00324 };
00325 
00326 namespace AArch64AT {
00327   enum ATValues {
00328     Invalid = -1,    // Op0 Op1  CRn   CRm   Op2
00329     S1E1R = 0x43c0,  // 01  000  0111  1000  000
00330     S1E2R = 0x63c0,  // 01  100  0111  1000  000
00331     S1E3R = 0x73c0,  // 01  110  0111  1000  000
00332     S1E1W = 0x43c1,  // 01  000  0111  1000  001
00333     S1E2W = 0x63c1,  // 01  100  0111  1000  001
00334     S1E3W = 0x73c1,  // 01  110  0111  1000  001
00335     S1E0R = 0x43c2,  // 01  000  0111  1000  010
00336     S1E0W = 0x43c3,  // 01  000  0111  1000  011
00337     S12E1R = 0x63c4, // 01  100  0111  1000  100
00338     S12E1W = 0x63c5, // 01  100  0111  1000  101
00339     S12E0R = 0x63c6, // 01  100  0111  1000  110
00340     S12E0W = 0x63c7  // 01  100  0111  1000  111
00341   };
00342 
00343   struct ATMapper : AArch64NamedImmMapper {
00344     const static Mapping ATMappings[];
00345 
00346     ATMapper();
00347   };
00348 
00349 }
00350 namespace AArch64DB {
00351   enum DBValues {
00352     Invalid = -1,
00353     OSHLD = 0x1,
00354     OSHST = 0x2,
00355     OSH =   0x3,
00356     NSHLD = 0x5,
00357     NSHST = 0x6,
00358     NSH =   0x7,
00359     ISHLD = 0x9,
00360     ISHST = 0xa,
00361     ISH =   0xb,
00362     LD =    0xd,
00363     ST =    0xe,
00364     SY =    0xf
00365   };
00366 
00367   struct DBarrierMapper : AArch64NamedImmMapper {
00368     const static Mapping DBarrierMappings[];
00369 
00370     DBarrierMapper();
00371   };
00372 }
00373 
00374 namespace  AArch64DC {
00375   enum DCValues {
00376     Invalid = -1,   // Op1  CRn   CRm   Op2
00377     ZVA   = 0x5ba1, // 01  011  0111  0100  001
00378     IVAC  = 0x43b1, // 01  000  0111  0110  001
00379     ISW   = 0x43b2, // 01  000  0111  0110  010
00380     CVAC  = 0x5bd1, // 01  011  0111  1010  001
00381     CSW   = 0x43d2, // 01  000  0111  1010  010
00382     CVAU  = 0x5bd9, // 01  011  0111  1011  001
00383     CIVAC = 0x5bf1, // 01  011  0111  1110  001
00384     CISW  = 0x43f2  // 01  000  0111  1110  010
00385   };
00386 
00387   struct DCMapper : AArch64NamedImmMapper {
00388     const static Mapping DCMappings[];
00389 
00390     DCMapper();
00391   };
00392 
00393 }
00394 
00395 namespace  AArch64IC {
00396   enum ICValues {
00397     Invalid = -1,     // Op1  CRn   CRm   Op2
00398     IALLUIS = 0x0388, // 000  0111  0001  000
00399     IALLU = 0x03a8,   // 000  0111  0101  000
00400     IVAU = 0x1ba9     // 011  0111  0101  001
00401   };
00402 
00403 
00404   struct ICMapper : AArch64NamedImmMapper {
00405     const static Mapping ICMappings[];
00406 
00407     ICMapper();
00408   };
00409 
00410   static inline bool NeedsRegister(ICValues Val) {
00411     return Val == IVAU;
00412   }
00413 }
00414 
00415 namespace  AArch64ISB {
00416   enum ISBValues {
00417     Invalid = -1,
00418     SY = 0xf
00419   };
00420   struct ISBMapper : AArch64NamedImmMapper {
00421     const static Mapping ISBMappings[];
00422 
00423     ISBMapper();
00424   };
00425 }
00426 
00427 namespace AArch64PRFM {
00428   enum PRFMValues {
00429     Invalid = -1,
00430     PLDL1KEEP = 0x00,
00431     PLDL1STRM = 0x01,
00432     PLDL2KEEP = 0x02,
00433     PLDL2STRM = 0x03,
00434     PLDL3KEEP = 0x04,
00435     PLDL3STRM = 0x05,
00436     PLIL1KEEP = 0x08,
00437     PLIL1STRM = 0x09,
00438     PLIL2KEEP = 0x0a,
00439     PLIL2STRM = 0x0b,
00440     PLIL3KEEP = 0x0c,
00441     PLIL3STRM = 0x0d,
00442     PSTL1KEEP = 0x10,
00443     PSTL1STRM = 0x11,
00444     PSTL2KEEP = 0x12,
00445     PSTL2STRM = 0x13,
00446     PSTL3KEEP = 0x14,
00447     PSTL3STRM = 0x15
00448   };
00449 
00450   struct PRFMMapper : AArch64NamedImmMapper {
00451     const static Mapping PRFMMappings[];
00452 
00453     PRFMMapper();
00454   };
00455 }
00456 
00457 namespace AArch64PState {
00458   enum PStateValues {
00459     Invalid = -1,
00460     SPSel = 0x05,
00461     DAIFSet = 0x1e,
00462     DAIFClr = 0x1f,
00463 
00464     // v8.1a "Privileged Access Never" extension-specific PStates
00465     PAN = 0x04,
00466   };
00467 
00468   struct PStateMapper : AArch64NamedImmMapper {
00469     const static Mapping PStateMappings[];
00470 
00471     PStateMapper();
00472   };
00473 
00474 }
00475 
00476 namespace AArch64SE {
00477     enum ShiftExtSpecifiers {
00478         Invalid = -1,
00479         LSL,
00480         MSL,
00481         LSR,
00482         ASR,
00483         ROR,
00484 
00485         UXTB,
00486         UXTH,
00487         UXTW,
00488         UXTX,
00489 
00490         SXTB,
00491         SXTH,
00492         SXTW,
00493         SXTX
00494     };
00495 }
00496 
00497 namespace AArch64Layout {
00498     enum VectorLayout {
00499         Invalid = -1,
00500         VL_8B,
00501         VL_4H,
00502         VL_2S,
00503         VL_1D,
00504 
00505         VL_16B,
00506         VL_8H,
00507         VL_4S,
00508         VL_2D,
00509 
00510         // Bare layout for the 128-bit vector
00511         // (only show ".b", ".h", ".s", ".d" without vector number)
00512         VL_B,
00513         VL_H,
00514         VL_S,
00515         VL_D
00516     };
00517 }
00518 
00519 inline static const char *
00520 AArch64VectorLayoutToString(AArch64Layout::VectorLayout Layout) {
00521   switch (Layout) {
00522   case AArch64Layout::VL_8B:  return ".8b";
00523   case AArch64Layout::VL_4H:  return ".4h";
00524   case AArch64Layout::VL_2S:  return ".2s";
00525   case AArch64Layout::VL_1D:  return ".1d";
00526   case AArch64Layout::VL_16B:  return ".16b";
00527   case AArch64Layout::VL_8H:  return ".8h";
00528   case AArch64Layout::VL_4S:  return ".4s";
00529   case AArch64Layout::VL_2D:  return ".2d";
00530   case AArch64Layout::VL_B:  return ".b";
00531   case AArch64Layout::VL_H:  return ".h";
00532   case AArch64Layout::VL_S:  return ".s";
00533   case AArch64Layout::VL_D:  return ".d";
00534   default: llvm_unreachable("Unknown Vector Layout");
00535   }
00536 }
00537 
00538 inline static AArch64Layout::VectorLayout
00539 AArch64StringToVectorLayout(StringRef LayoutStr) {
00540   return StringSwitch<AArch64Layout::VectorLayout>(LayoutStr)
00541              .Case(".8b", AArch64Layout::VL_8B)
00542              .Case(".4h", AArch64Layout::VL_4H)
00543              .Case(".2s", AArch64Layout::VL_2S)
00544              .Case(".1d", AArch64Layout::VL_1D)
00545              .Case(".16b", AArch64Layout::VL_16B)
00546              .Case(".8h", AArch64Layout::VL_8H)
00547              .Case(".4s", AArch64Layout::VL_4S)
00548              .Case(".2d", AArch64Layout::VL_2D)
00549              .Case(".b", AArch64Layout::VL_B)
00550              .Case(".h", AArch64Layout::VL_H)
00551              .Case(".s", AArch64Layout::VL_S)
00552              .Case(".d", AArch64Layout::VL_D)
00553              .Default(AArch64Layout::Invalid);
00554 }
00555 
00556 namespace AArch64SysReg {
00557   enum SysRegROValues {
00558     MDCCSR_EL0        = 0x9808, // 10  011  0000  0001  000
00559     DBGDTRRX_EL0      = 0x9828, // 10  011  0000  0101  000
00560     MDRAR_EL1         = 0x8080, // 10  000  0001  0000  000
00561     OSLSR_EL1         = 0x808c, // 10  000  0001  0001  100
00562     DBGAUTHSTATUS_EL1 = 0x83f6, // 10  000  0111  1110  110
00563     PMCEID0_EL0       = 0xdce6, // 11  011  1001  1100  110
00564     PMCEID1_EL0       = 0xdce7, // 11  011  1001  1100  111
00565     MIDR_EL1          = 0xc000, // 11  000  0000  0000  000
00566     CCSIDR_EL1        = 0xc800, // 11  001  0000  0000  000
00567     CLIDR_EL1         = 0xc801, // 11  001  0000  0000  001
00568     CTR_EL0           = 0xd801, // 11  011  0000  0000  001
00569     MPIDR_EL1         = 0xc005, // 11  000  0000  0000  101
00570     REVIDR_EL1        = 0xc006, // 11  000  0000  0000  110
00571     AIDR_EL1          = 0xc807, // 11  001  0000  0000  111
00572     DCZID_EL0         = 0xd807, // 11  011  0000  0000  111
00573     ID_PFR0_EL1       = 0xc008, // 11  000  0000  0001  000
00574     ID_PFR1_EL1       = 0xc009, // 11  000  0000  0001  001
00575     ID_DFR0_EL1       = 0xc00a, // 11  000  0000  0001  010
00576     ID_AFR0_EL1       = 0xc00b, // 11  000  0000  0001  011
00577     ID_MMFR0_EL1      = 0xc00c, // 11  000  0000  0001  100
00578     ID_MMFR1_EL1      = 0xc00d, // 11  000  0000  0001  101
00579     ID_MMFR2_EL1      = 0xc00e, // 11  000  0000  0001  110
00580     ID_MMFR3_EL1      = 0xc00f, // 11  000  0000  0001  111
00581     ID_ISAR0_EL1      = 0xc010, // 11  000  0000  0010  000
00582     ID_ISAR1_EL1      = 0xc011, // 11  000  0000  0010  001
00583     ID_ISAR2_EL1      = 0xc012, // 11  000  0000  0010  010
00584     ID_ISAR3_EL1      = 0xc013, // 11  000  0000  0010  011
00585     ID_ISAR4_EL1      = 0xc014, // 11  000  0000  0010  100
00586     ID_ISAR5_EL1      = 0xc015, // 11  000  0000  0010  101
00587     ID_A64PFR0_EL1    = 0xc020, // 11  000  0000  0100  000
00588     ID_A64PFR1_EL1    = 0xc021, // 11  000  0000  0100  001
00589     ID_A64DFR0_EL1    = 0xc028, // 11  000  0000  0101  000
00590     ID_A64DFR1_EL1    = 0xc029, // 11  000  0000  0101  001
00591     ID_A64AFR0_EL1    = 0xc02c, // 11  000  0000  0101  100
00592     ID_A64AFR1_EL1    = 0xc02d, // 11  000  0000  0101  101
00593     ID_A64ISAR0_EL1   = 0xc030, // 11  000  0000  0110  000
00594     ID_A64ISAR1_EL1   = 0xc031, // 11  000  0000  0110  001
00595     ID_A64MMFR0_EL1   = 0xc038, // 11  000  0000  0111  000
00596     ID_A64MMFR1_EL1   = 0xc039, // 11  000  0000  0111  001
00597     MVFR0_EL1         = 0xc018, // 11  000  0000  0011  000
00598     MVFR1_EL1         = 0xc019, // 11  000  0000  0011  001
00599     MVFR2_EL1         = 0xc01a, // 11  000  0000  0011  010
00600     RVBAR_EL1         = 0xc601, // 11  000  1100  0000  001
00601     RVBAR_EL2         = 0xe601, // 11  100  1100  0000  001
00602     RVBAR_EL3         = 0xf601, // 11  110  1100  0000  001
00603     ISR_EL1           = 0xc608, // 11  000  1100  0001  000
00604     CNTPCT_EL0        = 0xdf01, // 11  011  1110  0000  001
00605     CNTVCT_EL0        = 0xdf02,  // 11  011  1110  0000  010
00606     ID_MMFR4_EL1      = 0xc016,  // 11  000  0000  0010  110
00607 
00608     // Trace registers
00609     TRCSTATR          = 0x8818, // 10  001  0000  0011  000
00610     TRCIDR8           = 0x8806, // 10  001  0000  0000  110
00611     TRCIDR9           = 0x880e, // 10  001  0000  0001  110
00612     TRCIDR10          = 0x8816, // 10  001  0000  0010  110
00613     TRCIDR11          = 0x881e, // 10  001  0000  0011  110
00614     TRCIDR12          = 0x8826, // 10  001  0000  0100  110
00615     TRCIDR13          = 0x882e, // 10  001  0000  0101  110
00616     TRCIDR0           = 0x8847, // 10  001  0000  1000  111
00617     TRCIDR1           = 0x884f, // 10  001  0000  1001  111
00618     TRCIDR2           = 0x8857, // 10  001  0000  1010  111
00619     TRCIDR3           = 0x885f, // 10  001  0000  1011  111
00620     TRCIDR4           = 0x8867, // 10  001  0000  1100  111
00621     TRCIDR5           = 0x886f, // 10  001  0000  1101  111
00622     TRCIDR6           = 0x8877, // 10  001  0000  1110  111
00623     TRCIDR7           = 0x887f, // 10  001  0000  1111  111
00624     TRCOSLSR          = 0x888c, // 10  001  0001  0001  100
00625     TRCPDSR           = 0x88ac, // 10  001  0001  0101  100
00626     TRCDEVAFF0        = 0x8bd6, // 10  001  0111  1010  110
00627     TRCDEVAFF1        = 0x8bde, // 10  001  0111  1011  110
00628     TRCLSR            = 0x8bee, // 10  001  0111  1101  110
00629     TRCAUTHSTATUS     = 0x8bf6, // 10  001  0111  1110  110
00630     TRCDEVARCH        = 0x8bfe, // 10  001  0111  1111  110
00631     TRCDEVID          = 0x8b97, // 10  001  0111  0010  111
00632     TRCDEVTYPE        = 0x8b9f, // 10  001  0111  0011  111
00633     TRCPIDR4          = 0x8ba7, // 10  001  0111  0100  111
00634     TRCPIDR5          = 0x8baf, // 10  001  0111  0101  111
00635     TRCPIDR6          = 0x8bb7, // 10  001  0111  0110  111
00636     TRCPIDR7          = 0x8bbf, // 10  001  0111  0111  111
00637     TRCPIDR0          = 0x8bc7, // 10  001  0111  1000  111
00638     TRCPIDR1          = 0x8bcf, // 10  001  0111  1001  111
00639     TRCPIDR2          = 0x8bd7, // 10  001  0111  1010  111
00640     TRCPIDR3          = 0x8bdf, // 10  001  0111  1011  111
00641     TRCCIDR0          = 0x8be7, // 10  001  0111  1100  111
00642     TRCCIDR1          = 0x8bef, // 10  001  0111  1101  111
00643     TRCCIDR2          = 0x8bf7, // 10  001  0111  1110  111
00644     TRCCIDR3          = 0x8bff, // 10  001  0111  1111  111
00645 
00646     // GICv3 registers
00647     ICC_IAR1_EL1      = 0xc660, // 11  000  1100  1100  000
00648     ICC_IAR0_EL1      = 0xc640, // 11  000  1100  1000  000
00649     ICC_HPPIR1_EL1    = 0xc662, // 11  000  1100  1100  010
00650     ICC_HPPIR0_EL1    = 0xc642, // 11  000  1100  1000  010
00651     ICC_RPR_EL1       = 0xc65b, // 11  000  1100  1011  011
00652     ICH_VTR_EL2       = 0xe659, // 11  100  1100  1011  001
00653     ICH_EISR_EL2      = 0xe65b, // 11  100  1100  1011  011
00654     ICH_ELSR_EL2      = 0xe65d  // 11  100  1100  1011  101
00655   };
00656 
00657   enum SysRegWOValues {
00658     DBGDTRTX_EL0      = 0x9828, // 10  011  0000  0101  000
00659     OSLAR_EL1         = 0x8084, // 10  000  0001  0000  100
00660     PMSWINC_EL0       = 0xdce4,  // 11  011  1001  1100  100
00661 
00662     // Trace Registers
00663     TRCOSLAR          = 0x8884, // 10  001  0001  0000  100
00664     TRCLAR            = 0x8be6, // 10  001  0111  1100  110
00665 
00666     // GICv3 registers
00667     ICC_EOIR1_EL1     = 0xc661, // 11  000  1100  1100  001
00668     ICC_EOIR0_EL1     = 0xc641, // 11  000  1100  1000  001
00669     ICC_DIR_EL1       = 0xc659, // 11  000  1100  1011  001
00670     ICC_SGI1R_EL1     = 0xc65d, // 11  000  1100  1011  101
00671     ICC_ASGI1R_EL1    = 0xc65e, // 11  000  1100  1011  110
00672     ICC_SGI0R_EL1     = 0xc65f  // 11  000  1100  1011  111
00673   };
00674 
00675   enum SysRegValues {
00676     Invalid = -1,               // Op0 Op1  CRn   CRm   Op2
00677     OSDTRRX_EL1       = 0x8002, // 10  000  0000  0000  010
00678     OSDTRTX_EL1       = 0x801a, // 10  000  0000  0011  010
00679     TEECR32_EL1       = 0x9000, // 10  010  0000  0000  000
00680     MDCCINT_EL1       = 0x8010, // 10  000  0000  0010  000
00681     MDSCR_EL1         = 0x8012, // 10  000  0000  0010  010
00682     DBGDTR_EL0        = 0x9820, // 10  011  0000  0100  000
00683     OSECCR_EL1        = 0x8032, // 10  000  0000  0110  010
00684     DBGVCR32_EL2      = 0xa038, // 10  100  0000  0111  000
00685     DBGBVR0_EL1       = 0x8004, // 10  000  0000  0000  100
00686     DBGBVR1_EL1       = 0x800c, // 10  000  0000  0001  100
00687     DBGBVR2_EL1       = 0x8014, // 10  000  0000  0010  100
00688     DBGBVR3_EL1       = 0x801c, // 10  000  0000  0011  100
00689     DBGBVR4_EL1       = 0x8024, // 10  000  0000  0100  100
00690     DBGBVR5_EL1       = 0x802c, // 10  000  0000  0101  100
00691     DBGBVR6_EL1       = 0x8034, // 10  000  0000  0110  100
00692     DBGBVR7_EL1       = 0x803c, // 10  000  0000  0111  100
00693     DBGBVR8_EL1       = 0x8044, // 10  000  0000  1000  100
00694     DBGBVR9_EL1       = 0x804c, // 10  000  0000  1001  100
00695     DBGBVR10_EL1      = 0x8054, // 10  000  0000  1010  100
00696     DBGBVR11_EL1      = 0x805c, // 10  000  0000  1011  100
00697     DBGBVR12_EL1      = 0x8064, // 10  000  0000  1100  100
00698     DBGBVR13_EL1      = 0x806c, // 10  000  0000  1101  100
00699     DBGBVR14_EL1      = 0x8074, // 10  000  0000  1110  100
00700     DBGBVR15_EL1      = 0x807c, // 10  000  0000  1111  100
00701     DBGBCR0_EL1       = 0x8005, // 10  000  0000  0000  101
00702     DBGBCR1_EL1       = 0x800d, // 10  000  0000  0001  101
00703     DBGBCR2_EL1       = 0x8015, // 10  000  0000  0010  101
00704     DBGBCR3_EL1       = 0x801d, // 10  000  0000  0011  101
00705     DBGBCR4_EL1       = 0x8025, // 10  000  0000  0100  101
00706     DBGBCR5_EL1       = 0x802d, // 10  000  0000  0101  101
00707     DBGBCR6_EL1       = 0x8035, // 10  000  0000  0110  101
00708     DBGBCR7_EL1       = 0x803d, // 10  000  0000  0111  101
00709     DBGBCR8_EL1       = 0x8045, // 10  000  0000  1000  101
00710     DBGBCR9_EL1       = 0x804d, // 10  000  0000  1001  101
00711     DBGBCR10_EL1      = 0x8055, // 10  000  0000  1010  101
00712     DBGBCR11_EL1      = 0x805d, // 10  000  0000  1011  101
00713     DBGBCR12_EL1      = 0x8065, // 10  000  0000  1100  101
00714     DBGBCR13_EL1      = 0x806d, // 10  000  0000  1101  101
00715     DBGBCR14_EL1      = 0x8075, // 10  000  0000  1110  101
00716     DBGBCR15_EL1      = 0x807d, // 10  000  0000  1111  101
00717     DBGWVR0_EL1       = 0x8006, // 10  000  0000  0000  110
00718     DBGWVR1_EL1       = 0x800e, // 10  000  0000  0001  110
00719     DBGWVR2_EL1       = 0x8016, // 10  000  0000  0010  110
00720     DBGWVR3_EL1       = 0x801e, // 10  000  0000  0011  110
00721     DBGWVR4_EL1       = 0x8026, // 10  000  0000  0100  110
00722     DBGWVR5_EL1       = 0x802e, // 10  000  0000  0101  110
00723     DBGWVR6_EL1       = 0x8036, // 10  000  0000  0110  110
00724     DBGWVR7_EL1       = 0x803e, // 10  000  0000  0111  110
00725     DBGWVR8_EL1       = 0x8046, // 10  000  0000  1000  110
00726     DBGWVR9_EL1       = 0x804e, // 10  000  0000  1001  110
00727     DBGWVR10_EL1      = 0x8056, // 10  000  0000  1010  110
00728     DBGWVR11_EL1      = 0x805e, // 10  000  0000  1011  110
00729     DBGWVR12_EL1      = 0x8066, // 10  000  0000  1100  110
00730     DBGWVR13_EL1      = 0x806e, // 10  000  0000  1101  110
00731     DBGWVR14_EL1      = 0x8076, // 10  000  0000  1110  110
00732     DBGWVR15_EL1      = 0x807e, // 10  000  0000  1111  110
00733     DBGWCR0_EL1       = 0x8007, // 10  000  0000  0000  111
00734     DBGWCR1_EL1       = 0x800f, // 10  000  0000  0001  111
00735     DBGWCR2_EL1       = 0x8017, // 10  000  0000  0010  111
00736     DBGWCR3_EL1       = 0x801f, // 10  000  0000  0011  111
00737     DBGWCR4_EL1       = 0x8027, // 10  000  0000  0100  111
00738     DBGWCR5_EL1       = 0x802f, // 10  000  0000  0101  111
00739     DBGWCR6_EL1       = 0x8037, // 10  000  0000  0110  111
00740     DBGWCR7_EL1       = 0x803f, // 10  000  0000  0111  111
00741     DBGWCR8_EL1       = 0x8047, // 10  000  0000  1000  111
00742     DBGWCR9_EL1       = 0x804f, // 10  000  0000  1001  111
00743     DBGWCR10_EL1      = 0x8057, // 10  000  0000  1010  111
00744     DBGWCR11_EL1      = 0x805f, // 10  000  0000  1011  111
00745     DBGWCR12_EL1      = 0x8067, // 10  000  0000  1100  111
00746     DBGWCR13_EL1      = 0x806f, // 10  000  0000  1101  111
00747     DBGWCR14_EL1      = 0x8077, // 10  000  0000  1110  111
00748     DBGWCR15_EL1      = 0x807f, // 10  000  0000  1111  111
00749     TEEHBR32_EL1      = 0x9080, // 10  010  0001  0000  000
00750     OSDLR_EL1         = 0x809c, // 10  000  0001  0011  100
00751     DBGPRCR_EL1       = 0x80a4, // 10  000  0001  0100  100
00752     DBGCLAIMSET_EL1   = 0x83c6, // 10  000  0111  1000  110
00753     DBGCLAIMCLR_EL1   = 0x83ce, // 10  000  0111  1001  110
00754     CSSELR_EL1        = 0xd000, // 11  010  0000  0000  000
00755     VPIDR_EL2         = 0xe000, // 11  100  0000  0000  000
00756     VMPIDR_EL2        = 0xe005, // 11  100  0000  0000  101
00757     CPACR_EL1         = 0xc082, // 11  000  0001  0000  010
00758     SCTLR_EL1         = 0xc080, // 11  000  0001  0000  000
00759     SCTLR_EL2         = 0xe080, // 11  100  0001  0000  000
00760     SCTLR_EL3         = 0xf080, // 11  110  0001  0000  000
00761     ACTLR_EL1         = 0xc081, // 11  000  0001  0000  001
00762     ACTLR_EL2         = 0xe081, // 11  100  0001  0000  001
00763     ACTLR_EL3         = 0xf081, // 11  110  0001  0000  001
00764     HCR_EL2           = 0xe088, // 11  100  0001  0001  000
00765     SCR_EL3           = 0xf088, // 11  110  0001  0001  000
00766     MDCR_EL2          = 0xe089, // 11  100  0001  0001  001
00767     SDER32_EL3        = 0xf089, // 11  110  0001  0001  001
00768     CPTR_EL2          = 0xe08a, // 11  100  0001  0001  010
00769     CPTR_EL3          = 0xf08a, // 11  110  0001  0001  010
00770     HSTR_EL2          = 0xe08b, // 11  100  0001  0001  011
00771     HACR_EL2          = 0xe08f, // 11  100  0001  0001  111
00772     MDCR_EL3          = 0xf099, // 11  110  0001  0011  001
00773     TTBR0_EL1         = 0xc100, // 11  000  0010  0000  000
00774     TTBR0_EL2         = 0xe100, // 11  100  0010  0000  000
00775     TTBR0_EL3         = 0xf100, // 11  110  0010  0000  000
00776     TTBR1_EL1         = 0xc101, // 11  000  0010  0000  001
00777     TCR_EL1           = 0xc102, // 11  000  0010  0000  010
00778     TCR_EL2           = 0xe102, // 11  100  0010  0000  010
00779     TCR_EL3           = 0xf102, // 11  110  0010  0000  010
00780     VTTBR_EL2         = 0xe108, // 11  100  0010  0001  000
00781     VTCR_EL2          = 0xe10a, // 11  100  0010  0001  010
00782     DACR32_EL2        = 0xe180, // 11  100  0011  0000  000
00783     SPSR_EL1          = 0xc200, // 11  000  0100  0000  000
00784     SPSR_EL2          = 0xe200, // 11  100  0100  0000  000
00785     SPSR_EL3          = 0xf200, // 11  110  0100  0000  000
00786     ELR_EL1           = 0xc201, // 11  000  0100  0000  001
00787     ELR_EL2           = 0xe201, // 11  100  0100  0000  001
00788     ELR_EL3           = 0xf201, // 11  110  0100  0000  001
00789     SP_EL0            = 0xc208, // 11  000  0100  0001  000
00790     SP_EL1            = 0xe208, // 11  100  0100  0001  000
00791     SP_EL2            = 0xf208, // 11  110  0100  0001  000
00792     SPSel             = 0xc210, // 11  000  0100  0010  000
00793     NZCV              = 0xda10, // 11  011  0100  0010  000
00794     DAIF              = 0xda11, // 11  011  0100  0010  001
00795     CurrentEL         = 0xc212, // 11  000  0100  0010  010
00796     SPSR_irq          = 0xe218, // 11  100  0100  0011  000
00797     SPSR_abt          = 0xe219, // 11  100  0100  0011  001
00798     SPSR_und          = 0xe21a, // 11  100  0100  0011  010
00799     SPSR_fiq          = 0xe21b, // 11  100  0100  0011  011
00800     FPCR              = 0xda20, // 11  011  0100  0100  000
00801     FPSR              = 0xda21, // 11  011  0100  0100  001
00802     DSPSR_EL0         = 0xda28, // 11  011  0100  0101  000
00803     DLR_EL0           = 0xda29, // 11  011  0100  0101  001
00804     IFSR32_EL2        = 0xe281, // 11  100  0101  0000  001
00805     AFSR0_EL1         = 0xc288, // 11  000  0101  0001  000
00806     AFSR0_EL2         = 0xe288, // 11  100  0101  0001  000
00807     AFSR0_EL3         = 0xf288, // 11  110  0101  0001  000
00808     AFSR1_EL1         = 0xc289, // 11  000  0101  0001  001
00809     AFSR1_EL2         = 0xe289, // 11  100  0101  0001  001
00810     AFSR1_EL3         = 0xf289, // 11  110  0101  0001  001
00811     ESR_EL1           = 0xc290, // 11  000  0101  0010  000
00812     ESR_EL2           = 0xe290, // 11  100  0101  0010  000
00813     ESR_EL3           = 0xf290, // 11  110  0101  0010  000
00814     FPEXC32_EL2       = 0xe298, // 11  100  0101  0011  000
00815     FAR_EL1           = 0xc300, // 11  000  0110  0000  000
00816     FAR_EL2           = 0xe300, // 11  100  0110  0000  000
00817     FAR_EL3           = 0xf300, // 11  110  0110  0000  000
00818     HPFAR_EL2         = 0xe304, // 11  100  0110  0000  100
00819     PAR_EL1           = 0xc3a0, // 11  000  0111  0100  000
00820     PMCR_EL0          = 0xdce0, // 11  011  1001  1100  000
00821     PMCNTENSET_EL0    = 0xdce1, // 11  011  1001  1100  001
00822     PMCNTENCLR_EL0    = 0xdce2, // 11  011  1001  1100  010
00823     PMOVSCLR_EL0      = 0xdce3, // 11  011  1001  1100  011
00824     PMSELR_EL0        = 0xdce5, // 11  011  1001  1100  101
00825     PMCCNTR_EL0       = 0xdce8, // 11  011  1001  1101  000
00826     PMXEVTYPER_EL0    = 0xdce9, // 11  011  1001  1101  001
00827     PMXEVCNTR_EL0     = 0xdcea, // 11  011  1001  1101  010
00828     PMUSERENR_EL0     = 0xdcf0, // 11  011  1001  1110  000
00829     PMINTENSET_EL1    = 0xc4f1, // 11  000  1001  1110  001
00830     PMINTENCLR_EL1    = 0xc4f2, // 11  000  1001  1110  010
00831     PMOVSSET_EL0      = 0xdcf3, // 11  011  1001  1110  011
00832     MAIR_EL1          = 0xc510, // 11  000  1010  0010  000
00833     MAIR_EL2          = 0xe510, // 11  100  1010  0010  000
00834     MAIR_EL3          = 0xf510, // 11  110  1010  0010  000
00835     AMAIR_EL1         = 0xc518, // 11  000  1010  0011  000
00836     AMAIR_EL2         = 0xe518, // 11  100  1010  0011  000
00837     AMAIR_EL3         = 0xf518, // 11  110  1010  0011  000
00838     VBAR_EL1          = 0xc600, // 11  000  1100  0000  000
00839     VBAR_EL2          = 0xe600, // 11  100  1100  0000  000
00840     VBAR_EL3          = 0xf600, // 11  110  1100  0000  000
00841     RMR_EL1           = 0xc602, // 11  000  1100  0000  010
00842     RMR_EL2           = 0xe602, // 11  100  1100  0000  010
00843     RMR_EL3           = 0xf602, // 11  110  1100  0000  010
00844     CONTEXTIDR_EL1    = 0xc681, // 11  000  1101  0000  001
00845     TPIDR_EL0         = 0xde82, // 11  011  1101  0000  010
00846     TPIDR_EL2         = 0xe682, // 11  100  1101  0000  010
00847     TPIDR_EL3         = 0xf682, // 11  110  1101  0000  010
00848     TPIDRRO_EL0       = 0xde83, // 11  011  1101  0000  011
00849     TPIDR_EL1         = 0xc684, // 11  000  1101  0000  100
00850     CNTFRQ_EL0        = 0xdf00, // 11  011  1110  0000  000
00851     CNTVOFF_EL2       = 0xe703, // 11  100  1110  0000  011
00852     CNTKCTL_EL1       = 0xc708, // 11  000  1110  0001  000
00853     CNTHCTL_EL2       = 0xe708, // 11  100  1110  0001  000
00854     CNTP_TVAL_EL0     = 0xdf10, // 11  011  1110  0010  000
00855     CNTHP_TVAL_EL2    = 0xe710, // 11  100  1110  0010  000
00856     CNTPS_TVAL_EL1    = 0xff10, // 11  111  1110  0010  000
00857     CNTP_CTL_EL0      = 0xdf11, // 11  011  1110  0010  001
00858     CNTHP_CTL_EL2     = 0xe711, // 11  100  1110  0010  001
00859     CNTPS_CTL_EL1     = 0xff11, // 11  111  1110  0010  001
00860     CNTP_CVAL_EL0     = 0xdf12, // 11  011  1110  0010  010
00861     CNTHP_CVAL_EL2    = 0xe712, // 11  100  1110  0010  010
00862     CNTPS_CVAL_EL1    = 0xff12, // 11  111  1110  0010  010
00863     CNTV_TVAL_EL0     = 0xdf18, // 11  011  1110  0011  000
00864     CNTV_CTL_EL0      = 0xdf19, // 11  011  1110  0011  001
00865     CNTV_CVAL_EL0     = 0xdf1a, // 11  011  1110  0011  010
00866     PMEVCNTR0_EL0     = 0xdf40, // 11  011  1110  1000  000
00867     PMEVCNTR1_EL0     = 0xdf41, // 11  011  1110  1000  001
00868     PMEVCNTR2_EL0     = 0xdf42, // 11  011  1110  1000  010
00869     PMEVCNTR3_EL0     = 0xdf43, // 11  011  1110  1000  011
00870     PMEVCNTR4_EL0     = 0xdf44, // 11  011  1110  1000  100
00871     PMEVCNTR5_EL0     = 0xdf45, // 11  011  1110  1000  101
00872     PMEVCNTR6_EL0     = 0xdf46, // 11  011  1110  1000  110
00873     PMEVCNTR7_EL0     = 0xdf47, // 11  011  1110  1000  111
00874     PMEVCNTR8_EL0     = 0xdf48, // 11  011  1110  1001  000
00875     PMEVCNTR9_EL0     = 0xdf49, // 11  011  1110  1001  001
00876     PMEVCNTR10_EL0    = 0xdf4a, // 11  011  1110  1001  010
00877     PMEVCNTR11_EL0    = 0xdf4b, // 11  011  1110  1001  011
00878     PMEVCNTR12_EL0    = 0xdf4c, // 11  011  1110  1001  100
00879     PMEVCNTR13_EL0    = 0xdf4d, // 11  011  1110  1001  101
00880     PMEVCNTR14_EL0    = 0xdf4e, // 11  011  1110  1001  110
00881     PMEVCNTR15_EL0    = 0xdf4f, // 11  011  1110  1001  111
00882     PMEVCNTR16_EL0    = 0xdf50, // 11  011  1110  1010  000
00883     PMEVCNTR17_EL0    = 0xdf51, // 11  011  1110  1010  001
00884     PMEVCNTR18_EL0    = 0xdf52, // 11  011  1110  1010  010
00885     PMEVCNTR19_EL0    = 0xdf53, // 11  011  1110  1010  011
00886     PMEVCNTR20_EL0    = 0xdf54, // 11  011  1110  1010  100
00887     PMEVCNTR21_EL0    = 0xdf55, // 11  011  1110  1010  101
00888     PMEVCNTR22_EL0    = 0xdf56, // 11  011  1110  1010  110
00889     PMEVCNTR23_EL0    = 0xdf57, // 11  011  1110  1010  111
00890     PMEVCNTR24_EL0    = 0xdf58, // 11  011  1110  1011  000
00891     PMEVCNTR25_EL0    = 0xdf59, // 11  011  1110  1011  001
00892     PMEVCNTR26_EL0    = 0xdf5a, // 11  011  1110  1011  010
00893     PMEVCNTR27_EL0    = 0xdf5b, // 11  011  1110  1011  011
00894     PMEVCNTR28_EL0    = 0xdf5c, // 11  011  1110  1011  100
00895     PMEVCNTR29_EL0    = 0xdf5d, // 11  011  1110  1011  101
00896     PMEVCNTR30_EL0    = 0xdf5e, // 11  011  1110  1011  110
00897     PMCCFILTR_EL0     = 0xdf7f, // 11  011  1110  1111  111
00898     PMEVTYPER0_EL0    = 0xdf60, // 11  011  1110  1100  000
00899     PMEVTYPER1_EL0    = 0xdf61, // 11  011  1110  1100  001
00900     PMEVTYPER2_EL0    = 0xdf62, // 11  011  1110  1100  010
00901     PMEVTYPER3_EL0    = 0xdf63, // 11  011  1110  1100  011
00902     PMEVTYPER4_EL0    = 0xdf64, // 11  011  1110  1100  100
00903     PMEVTYPER5_EL0    = 0xdf65, // 11  011  1110  1100  101
00904     PMEVTYPER6_EL0    = 0xdf66, // 11  011  1110  1100  110
00905     PMEVTYPER7_EL0    = 0xdf67, // 11  011  1110  1100  111
00906     PMEVTYPER8_EL0    = 0xdf68, // 11  011  1110  1101  000
00907     PMEVTYPER9_EL0    = 0xdf69, // 11  011  1110  1101  001
00908     PMEVTYPER10_EL0   = 0xdf6a, // 11  011  1110  1101  010
00909     PMEVTYPER11_EL0   = 0xdf6b, // 11  011  1110  1101  011
00910     PMEVTYPER12_EL0   = 0xdf6c, // 11  011  1110  1101  100
00911     PMEVTYPER13_EL0   = 0xdf6d, // 11  011  1110  1101  101
00912     PMEVTYPER14_EL0   = 0xdf6e, // 11  011  1110  1101  110
00913     PMEVTYPER15_EL0   = 0xdf6f, // 11  011  1110  1101  111
00914     PMEVTYPER16_EL0   = 0xdf70, // 11  011  1110  1110  000
00915     PMEVTYPER17_EL0   = 0xdf71, // 11  011  1110  1110  001
00916     PMEVTYPER18_EL0   = 0xdf72, // 11  011  1110  1110  010
00917     PMEVTYPER19_EL0   = 0xdf73, // 11  011  1110  1110  011
00918     PMEVTYPER20_EL0   = 0xdf74, // 11  011  1110  1110  100
00919     PMEVTYPER21_EL0   = 0xdf75, // 11  011  1110  1110  101
00920     PMEVTYPER22_EL0   = 0xdf76, // 11  011  1110  1110  110
00921     PMEVTYPER23_EL0   = 0xdf77, // 11  011  1110  1110  111
00922     PMEVTYPER24_EL0   = 0xdf78, // 11  011  1110  1111  000
00923     PMEVTYPER25_EL0   = 0xdf79, // 11  011  1110  1111  001
00924     PMEVTYPER26_EL0   = 0xdf7a, // 11  011  1110  1111  010
00925     PMEVTYPER27_EL0   = 0xdf7b, // 11  011  1110  1111  011
00926     PMEVTYPER28_EL0   = 0xdf7c, // 11  011  1110  1111  100
00927     PMEVTYPER29_EL0   = 0xdf7d, // 11  011  1110  1111  101
00928     PMEVTYPER30_EL0   = 0xdf7e, // 11  011  1110  1111  110
00929 
00930     // Trace registers
00931     TRCPRGCTLR        = 0x8808, // 10  001  0000  0001  000
00932     TRCPROCSELR       = 0x8810, // 10  001  0000  0010  000
00933     TRCCONFIGR        = 0x8820, // 10  001  0000  0100  000
00934     TRCAUXCTLR        = 0x8830, // 10  001  0000  0110  000
00935     TRCEVENTCTL0R     = 0x8840, // 10  001  0000  1000  000
00936     TRCEVENTCTL1R     = 0x8848, // 10  001  0000  1001  000
00937     TRCSTALLCTLR      = 0x8858, // 10  001  0000  1011  000
00938     TRCTSCTLR         = 0x8860, // 10  001  0000  1100  000
00939     TRCSYNCPR         = 0x8868, // 10  001  0000  1101  000
00940     TRCCCCTLR         = 0x8870, // 10  001  0000  1110  000
00941     TRCBBCTLR         = 0x8878, // 10  001  0000  1111  000
00942     TRCTRACEIDR       = 0x8801, // 10  001  0000  0000  001
00943     TRCQCTLR          = 0x8809, // 10  001  0000  0001  001
00944     TRCVICTLR         = 0x8802, // 10  001  0000  0000  010
00945     TRCVIIECTLR       = 0x880a, // 10  001  0000  0001  010
00946     TRCVISSCTLR       = 0x8812, // 10  001  0000  0010  010
00947     TRCVIPCSSCTLR     = 0x881a, // 10  001  0000  0011  010
00948     TRCVDCTLR         = 0x8842, // 10  001  0000  1000  010
00949     TRCVDSACCTLR      = 0x884a, // 10  001  0000  1001  010
00950     TRCVDARCCTLR      = 0x8852, // 10  001  0000  1010  010
00951     TRCSEQEVR0        = 0x8804, // 10  001  0000  0000  100
00952     TRCSEQEVR1        = 0x880c, // 10  001  0000  0001  100
00953     TRCSEQEVR2        = 0x8814, // 10  001  0000  0010  100
00954     TRCSEQRSTEVR      = 0x8834, // 10  001  0000  0110  100
00955     TRCSEQSTR         = 0x883c, // 10  001  0000  0111  100
00956     TRCEXTINSELR      = 0x8844, // 10  001  0000  1000  100
00957     TRCCNTRLDVR0      = 0x8805, // 10  001  0000  0000  101
00958     TRCCNTRLDVR1      = 0x880d, // 10  001  0000  0001  101
00959     TRCCNTRLDVR2      = 0x8815, // 10  001  0000  0010  101
00960     TRCCNTRLDVR3      = 0x881d, // 10  001  0000  0011  101
00961     TRCCNTCTLR0       = 0x8825, // 10  001  0000  0100  101
00962     TRCCNTCTLR1       = 0x882d, // 10  001  0000  0101  101
00963     TRCCNTCTLR2       = 0x8835, // 10  001  0000  0110  101
00964     TRCCNTCTLR3       = 0x883d, // 10  001  0000  0111  101
00965     TRCCNTVR0         = 0x8845, // 10  001  0000  1000  101
00966     TRCCNTVR1         = 0x884d, // 10  001  0000  1001  101
00967     TRCCNTVR2         = 0x8855, // 10  001  0000  1010  101
00968     TRCCNTVR3         = 0x885d, // 10  001  0000  1011  101
00969     TRCIMSPEC0        = 0x8807, // 10  001  0000  0000  111
00970     TRCIMSPEC1        = 0x880f, // 10  001  0000  0001  111
00971     TRCIMSPEC2        = 0x8817, // 10  001  0000  0010  111
00972     TRCIMSPEC3        = 0x881f, // 10  001  0000  0011  111
00973     TRCIMSPEC4        = 0x8827, // 10  001  0000  0100  111
00974     TRCIMSPEC5        = 0x882f, // 10  001  0000  0101  111
00975     TRCIMSPEC6        = 0x8837, // 10  001  0000  0110  111
00976     TRCIMSPEC7        = 0x883f, // 10  001  0000  0111  111
00977     TRCRSCTLR2        = 0x8890, // 10  001  0001  0010  000
00978     TRCRSCTLR3        = 0x8898, // 10  001  0001  0011  000
00979     TRCRSCTLR4        = 0x88a0, // 10  001  0001  0100  000
00980     TRCRSCTLR5        = 0x88a8, // 10  001  0001  0101  000
00981     TRCRSCTLR6        = 0x88b0, // 10  001  0001  0110  000
00982     TRCRSCTLR7        = 0x88b8, // 10  001  0001  0111  000
00983     TRCRSCTLR8        = 0x88c0, // 10  001  0001  1000  000
00984     TRCRSCTLR9        = 0x88c8, // 10  001  0001  1001  000
00985     TRCRSCTLR10       = 0x88d0, // 10  001  0001  1010  000
00986     TRCRSCTLR11       = 0x88d8, // 10  001  0001  1011  000
00987     TRCRSCTLR12       = 0x88e0, // 10  001  0001  1100  000
00988     TRCRSCTLR13       = 0x88e8, // 10  001  0001  1101  000
00989     TRCRSCTLR14       = 0x88f0, // 10  001  0001  1110  000
00990     TRCRSCTLR15       = 0x88f8, // 10  001  0001  1111  000
00991     TRCRSCTLR16       = 0x8881, // 10  001  0001  0000  001
00992     TRCRSCTLR17       = 0x8889, // 10  001  0001  0001  001
00993     TRCRSCTLR18       = 0x8891, // 10  001  0001  0010  001
00994     TRCRSCTLR19       = 0x8899, // 10  001  0001  0011  001
00995     TRCRSCTLR20       = 0x88a1, // 10  001  0001  0100  001
00996     TRCRSCTLR21       = 0x88a9, // 10  001  0001  0101  001
00997     TRCRSCTLR22       = 0x88b1, // 10  001  0001  0110  001
00998     TRCRSCTLR23       = 0x88b9, // 10  001  0001  0111  001
00999     TRCRSCTLR24       = 0x88c1, // 10  001  0001  1000  001
01000     TRCRSCTLR25       = 0x88c9, // 10  001  0001  1001  001
01001     TRCRSCTLR26       = 0x88d1, // 10  001  0001  1010  001
01002     TRCRSCTLR27       = 0x88d9, // 10  001  0001  1011  001
01003     TRCRSCTLR28       = 0x88e1, // 10  001  0001  1100  001
01004     TRCRSCTLR29       = 0x88e9, // 10  001  0001  1101  001
01005     TRCRSCTLR30       = 0x88f1, // 10  001  0001  1110  001
01006     TRCRSCTLR31       = 0x88f9, // 10  001  0001  1111  001
01007     TRCSSCCR0         = 0x8882, // 10  001  0001  0000  010
01008     TRCSSCCR1         = 0x888a, // 10  001  0001  0001  010
01009     TRCSSCCR2         = 0x8892, // 10  001  0001  0010  010
01010     TRCSSCCR3         = 0x889a, // 10  001  0001  0011  010
01011     TRCSSCCR4         = 0x88a2, // 10  001  0001  0100  010
01012     TRCSSCCR5         = 0x88aa, // 10  001  0001  0101  010
01013     TRCSSCCR6         = 0x88b2, // 10  001  0001  0110  010
01014     TRCSSCCR7         = 0x88ba, // 10  001  0001  0111  010
01015     TRCSSCSR0         = 0x88c2, // 10  001  0001  1000  010
01016     TRCSSCSR1         = 0x88ca, // 10  001  0001  1001  010
01017     TRCSSCSR2         = 0x88d2, // 10  001  0001  1010  010
01018     TRCSSCSR3         = 0x88da, // 10  001  0001  1011  010
01019     TRCSSCSR4         = 0x88e2, // 10  001  0001  1100  010
01020     TRCSSCSR5         = 0x88ea, // 10  001  0001  1101  010
01021     TRCSSCSR6         = 0x88f2, // 10  001  0001  1110  010
01022     TRCSSCSR7         = 0x88fa, // 10  001  0001  1111  010
01023     TRCSSPCICR0       = 0x8883, // 10  001  0001  0000  011
01024     TRCSSPCICR1       = 0x888b, // 10  001  0001  0001  011
01025     TRCSSPCICR2       = 0x8893, // 10  001  0001  0010  011
01026     TRCSSPCICR3       = 0x889b, // 10  001  0001  0011  011
01027     TRCSSPCICR4       = 0x88a3, // 10  001  0001  0100  011
01028     TRCSSPCICR5       = 0x88ab, // 10  001  0001  0101  011
01029     TRCSSPCICR6       = 0x88b3, // 10  001  0001  0110  011
01030     TRCSSPCICR7       = 0x88bb, // 10  001  0001  0111  011
01031     TRCPDCR           = 0x88a4, // 10  001  0001  0100  100
01032     TRCACVR0          = 0x8900, // 10  001  0010  0000  000
01033     TRCACVR1          = 0x8910, // 10  001  0010  0010  000
01034     TRCACVR2          = 0x8920, // 10  001  0010  0100  000
01035     TRCACVR3          = 0x8930, // 10  001  0010  0110  000
01036     TRCACVR4          = 0x8940, // 10  001  0010  1000  000
01037     TRCACVR5          = 0x8950, // 10  001  0010  1010  000
01038     TRCACVR6          = 0x8960, // 10  001  0010  1100  000
01039     TRCACVR7          = 0x8970, // 10  001  0010  1110  000
01040     TRCACVR8          = 0x8901, // 10  001  0010  0000  001
01041     TRCACVR9          = 0x8911, // 10  001  0010  0010  001
01042     TRCACVR10         = 0x8921, // 10  001  0010  0100  001
01043     TRCACVR11         = 0x8931, // 10  001  0010  0110  001
01044     TRCACVR12         = 0x8941, // 10  001  0010  1000  001
01045     TRCACVR13         = 0x8951, // 10  001  0010  1010  001
01046     TRCACVR14         = 0x8961, // 10  001  0010  1100  001
01047     TRCACVR15         = 0x8971, // 10  001  0010  1110  001
01048     TRCACATR0         = 0x8902, // 10  001  0010  0000  010
01049     TRCACATR1         = 0x8912, // 10  001  0010  0010  010
01050     TRCACATR2         = 0x8922, // 10  001  0010  0100  010
01051     TRCACATR3         = 0x8932, // 10  001  0010  0110  010
01052     TRCACATR4         = 0x8942, // 10  001  0010  1000  010
01053     TRCACATR5         = 0x8952, // 10  001  0010  1010  010
01054     TRCACATR6         = 0x8962, // 10  001  0010  1100  010
01055     TRCACATR7         = 0x8972, // 10  001  0010  1110  010
01056     TRCACATR8         = 0x8903, // 10  001  0010  0000  011
01057     TRCACATR9         = 0x8913, // 10  001  0010  0010  011
01058     TRCACATR10        = 0x8923, // 10  001  0010  0100  011
01059     TRCACATR11        = 0x8933, // 10  001  0010  0110  011
01060     TRCACATR12        = 0x8943, // 10  001  0010  1000  011
01061     TRCACATR13        = 0x8953, // 10  001  0010  1010  011
01062     TRCACATR14        = 0x8963, // 10  001  0010  1100  011
01063     TRCACATR15        = 0x8973, // 10  001  0010  1110  011
01064     TRCDVCVR0         = 0x8904, // 10  001  0010  0000  100
01065     TRCDVCVR1         = 0x8924, // 10  001  0010  0100  100
01066     TRCDVCVR2         = 0x8944, // 10  001  0010  1000  100
01067     TRCDVCVR3         = 0x8964, // 10  001  0010  1100  100
01068     TRCDVCVR4         = 0x8905, // 10  001  0010  0000  101
01069     TRCDVCVR5         = 0x8925, // 10  001  0010  0100  101
01070     TRCDVCVR6         = 0x8945, // 10  001  0010  1000  101
01071     TRCDVCVR7         = 0x8965, // 10  001  0010  1100  101
01072     TRCDVCMR0         = 0x8906, // 10  001  0010  0000  110
01073     TRCDVCMR1         = 0x8926, // 10  001  0010  0100  110
01074     TRCDVCMR2         = 0x8946, // 10  001  0010  1000  110
01075     TRCDVCMR3         = 0x8966, // 10  001  0010  1100  110
01076     TRCDVCMR4         = 0x8907, // 10  001  0010  0000  111
01077     TRCDVCMR5         = 0x8927, // 10  001  0010  0100  111
01078     TRCDVCMR6         = 0x8947, // 10  001  0010  1000  111
01079     TRCDVCMR7         = 0x8967, // 10  001  0010  1100  111
01080     TRCCIDCVR0        = 0x8980, // 10  001  0011  0000  000
01081     TRCCIDCVR1        = 0x8990, // 10  001  0011  0010  000
01082     TRCCIDCVR2        = 0x89a0, // 10  001  0011  0100  000
01083     TRCCIDCVR3        = 0x89b0, // 10  001  0011  0110  000
01084     TRCCIDCVR4        = 0x89c0, // 10  001  0011  1000  000
01085     TRCCIDCVR5        = 0x89d0, // 10  001  0011  1010  000
01086     TRCCIDCVR6        = 0x89e0, // 10  001  0011  1100  000
01087     TRCCIDCVR7        = 0x89f0, // 10  001  0011  1110  000
01088     TRCVMIDCVR0       = 0x8981, // 10  001  0011  0000  001
01089     TRCVMIDCVR1       = 0x8991, // 10  001  0011  0010  001
01090     TRCVMIDCVR2       = 0x89a1, // 10  001  0011  0100  001
01091     TRCVMIDCVR3       = 0x89b1, // 10  001  0011  0110  001
01092     TRCVMIDCVR4       = 0x89c1, // 10  001  0011  1000  001
01093     TRCVMIDCVR5       = 0x89d1, // 10  001  0011  1010  001
01094     TRCVMIDCVR6       = 0x89e1, // 10  001  0011  1100  001
01095     TRCVMIDCVR7       = 0x89f1, // 10  001  0011  1110  001
01096     TRCCIDCCTLR0      = 0x8982, // 10  001  0011  0000  010
01097     TRCCIDCCTLR1      = 0x898a, // 10  001  0011  0001  010
01098     TRCVMIDCCTLR0     = 0x8992, // 10  001  0011  0010  010
01099     TRCVMIDCCTLR1     = 0x899a, // 10  001  0011  0011  010
01100     TRCITCTRL         = 0x8b84, // 10  001  0111  0000  100
01101     TRCCLAIMSET       = 0x8bc6, // 10  001  0111  1000  110
01102     TRCCLAIMCLR       = 0x8bce, // 10  001  0111  1001  110
01103 
01104     // GICv3 registers
01105     ICC_BPR1_EL1      = 0xc663, // 11  000  1100  1100  011
01106     ICC_BPR0_EL1      = 0xc643, // 11  000  1100  1000  011
01107     ICC_PMR_EL1       = 0xc230, // 11  000  0100  0110  000
01108     ICC_CTLR_EL1      = 0xc664, // 11  000  1100  1100  100
01109     ICC_CTLR_EL3      = 0xf664, // 11  110  1100  1100  100
01110     ICC_SRE_EL1       = 0xc665, // 11  000  1100  1100  101
01111     ICC_SRE_EL2       = 0xe64d, // 11  100  1100  1001  101
01112     ICC_SRE_EL3       = 0xf665, // 11  110  1100  1100  101
01113     ICC_IGRPEN0_EL1   = 0xc666, // 11  000  1100  1100  110
01114     ICC_IGRPEN1_EL1   = 0xc667, // 11  000  1100  1100  111
01115     ICC_IGRPEN1_EL3   = 0xf667, // 11  110  1100  1100  111
01116     ICC_SEIEN_EL1     = 0xc668, // 11  000  1100  1101  000
01117     ICC_AP0R0_EL1     = 0xc644, // 11  000  1100  1000  100
01118     ICC_AP0R1_EL1     = 0xc645, // 11  000  1100  1000  101
01119     ICC_AP0R2_EL1     = 0xc646, // 11  000  1100  1000  110
01120     ICC_AP0R3_EL1     = 0xc647, // 11  000  1100  1000  111
01121     ICC_AP1R0_EL1     = 0xc648, // 11  000  1100  1001  000
01122     ICC_AP1R1_EL1     = 0xc649, // 11  000  1100  1001  001
01123     ICC_AP1R2_EL1     = 0xc64a, // 11  000  1100  1001  010
01124     ICC_AP1R3_EL1     = 0xc64b, // 11  000  1100  1001  011
01125     ICH_AP0R0_EL2     = 0xe640, // 11  100  1100  1000  000
01126     ICH_AP0R1_EL2     = 0xe641, // 11  100  1100  1000  001
01127     ICH_AP0R2_EL2     = 0xe642, // 11  100  1100  1000  010
01128     ICH_AP0R3_EL2     = 0xe643, // 11  100  1100  1000  011
01129     ICH_AP1R0_EL2     = 0xe648, // 11  100  1100  1001  000
01130     ICH_AP1R1_EL2     = 0xe649, // 11  100  1100  1001  001
01131     ICH_AP1R2_EL2     = 0xe64a, // 11  100  1100  1001  010
01132     ICH_AP1R3_EL2     = 0xe64b, // 11  100  1100  1001  011
01133     ICH_HCR_EL2       = 0xe658, // 11  100  1100  1011  000
01134     ICH_MISR_EL2      = 0xe65a, // 11  100  1100  1011  010
01135     ICH_VMCR_EL2      = 0xe65f, // 11  100  1100  1011  111
01136     ICH_VSEIR_EL2     = 0xe64c, // 11  100  1100  1001  100
01137     ICH_LR0_EL2       = 0xe660, // 11  100  1100  1100  000
01138     ICH_LR1_EL2       = 0xe661, // 11  100  1100  1100  001
01139     ICH_LR2_EL2       = 0xe662, // 11  100  1100  1100  010
01140     ICH_LR3_EL2       = 0xe663, // 11  100  1100  1100  011
01141     ICH_LR4_EL2       = 0xe664, // 11  100  1100  1100  100
01142     ICH_LR5_EL2       = 0xe665, // 11  100  1100  1100  101
01143     ICH_LR6_EL2       = 0xe666, // 11  100  1100  1100  110
01144     ICH_LR7_EL2       = 0xe667, // 11  100  1100  1100  111
01145     ICH_LR8_EL2       = 0xe668, // 11  100  1100  1101  000
01146     ICH_LR9_EL2       = 0xe669, // 11  100  1100  1101  001
01147     ICH_LR10_EL2      = 0xe66a, // 11  100  1100  1101  010
01148     ICH_LR11_EL2      = 0xe66b, // 11  100  1100  1101  011
01149     ICH_LR12_EL2      = 0xe66c, // 11  100  1100  1101  100
01150     ICH_LR13_EL2      = 0xe66d, // 11  100  1100  1101  101
01151     ICH_LR14_EL2      = 0xe66e, // 11  100  1100  1101  110
01152     ICH_LR15_EL2      = 0xe66f, // 11  100  1100  1101  111
01153 
01154     // v8.1a "Privileged Access Never" extension-specific system registers
01155     PAN               = 0xc213, // 11  000  0100  0010  011
01156 
01157     // v8.1a "Limited Ordering Regions" extension-specific system registers
01158     LORSA_EL1         = 0xc520, // 11  000  1010  0100  000
01159     LOREA_EL1         = 0xc521, // 11  000  1010  0100  001
01160     LORN_EL1          = 0xc522, // 11  000  1010  0100  010
01161     LORC_EL1          = 0xc523, // 11  000  1010  0100  011
01162     LORID_EL1         = 0xc527, // 11  000  1010  0100  111
01163 
01164     // v8.1a "Virtualization host extensions" system registers
01165     TTBR1_EL2         = 0xe101, // 11  100  0010  0000  001
01166     CONTEXTIDR_EL2    = 0xe681, // 11  100  1101  0000  001
01167     CNTHV_TVAL_EL2    = 0xe718, // 11  100  1110  0011  000
01168     CNTHV_CVAL_EL2    = 0xe71a, // 11  100  1110  0011  010
01169     CNTHV_CTL_EL2     = 0xe719, // 11  100  1110  0011  001
01170     SCTLR_EL12        = 0xe880, // 11  101  0001  0000  000
01171     CPACR_EL12        = 0xe882, // 11  101  0001  0000  010
01172     TTBR0_EL12        = 0xe900, // 11  101  0010  0000  000
01173     TTBR1_EL12        = 0xe901, // 11  101  0010  0000  001
01174     TCR_EL12          = 0xe902, // 11  101  0010  0000  010
01175     AFSR0_EL12        = 0xea88, // 11  101  0101  0001  000
01176     AFSR1_EL12        = 0xea89, // 11  101  0101  0001  001
01177     ESR_EL12          = 0xea90, // 11  101  0101  0010  000
01178     FAR_EL12          = 0xeb00, // 11  101  0110  0000  000
01179     MAIR_EL12         = 0xed10, // 11  101  1010  0010  000
01180     AMAIR_EL12        = 0xed18, // 11  101  1010  0011  000
01181     VBAR_EL12         = 0xee00, // 11  101  1100  0000  000
01182     CONTEXTIDR_EL12   = 0xee81, // 11  101  1101  0000  001
01183     CNTKCTL_EL12      = 0xef08, // 11  101  1110  0001  000
01184     CNTP_TVAL_EL02    = 0xef10, // 11  101  1110  0010  000
01185     CNTP_CTL_EL02     = 0xef11, // 11  101  1110  0010  001
01186     CNTP_CVAL_EL02    = 0xef12, // 11  101  1110  0010  010
01187     CNTV_TVAL_EL02    = 0xef18, // 11  101  1110  0011  000
01188     CNTV_CTL_EL02     = 0xef19, // 11  101  1110  0011  001
01189     CNTV_CVAL_EL02    = 0xef1a, // 11  101  1110  0011  010
01190     SPSR_EL12         = 0xea00, // 11  101  0100  0000  000
01191     ELR_EL12          = 0xea01, // 11  101  0100  0000  001
01192 
01193     // Cyclone specific system registers
01194     CPM_IOACC_CTL_EL3 = 0xff90,
01195   };
01196 
01197   // Note that these do not inherit from AArch64NamedImmMapper. This class is
01198   // sufficiently different in its behaviour that I don't believe it's worth
01199   // burdening the common AArch64NamedImmMapper with abstractions only needed in
01200   // this one case.
01201   struct SysRegMapper {
01202     static const AArch64NamedImmMapper::Mapping SysRegMappings[];
01203 
01204     const AArch64NamedImmMapper::Mapping *InstMappings;
01205     size_t NumInstMappings;
01206 
01207     SysRegMapper() { }
01208     uint32_t fromString(StringRef Name, const FeatureBitset& FeatureBits,
01209                         bool &Valid) const;
01210     std::string toString(uint32_t Bits, const FeatureBitset& FeatureBits) const;
01211   };
01212 
01213   struct MSRMapper : SysRegMapper {
01214     static const AArch64NamedImmMapper::Mapping MSRMappings[];
01215     MSRMapper();
01216   };
01217 
01218   struct MRSMapper : SysRegMapper {
01219     static const AArch64NamedImmMapper::Mapping MRSMappings[];
01220     MRSMapper();
01221   };
01222 
01223   uint32_t ParseGenericRegister(StringRef Name, bool &Valid);
01224 }
01225 
01226 namespace AArch64TLBI {
01227   enum TLBIValues {
01228     Invalid = -1,          // Op0 Op1  CRn   CRm   Op2
01229     IPAS2E1IS    = 0x6401, // 01  100  1000  0000  001
01230     IPAS2LE1IS   = 0x6405, // 01  100  1000  0000  101
01231     VMALLE1IS    = 0x4418, // 01  000  1000  0011  000
01232     ALLE2IS      = 0x6418, // 01  100  1000  0011  000
01233     ALLE3IS      = 0x7418, // 01  110  1000  0011  000
01234     VAE1IS       = 0x4419, // 01  000  1000  0011  001
01235     VAE2IS       = 0x6419, // 01  100  1000  0011  001
01236     VAE3IS       = 0x7419, // 01  110  1000  0011  001
01237     ASIDE1IS     = 0x441a, // 01  000  1000  0011  010
01238     VAAE1IS      = 0x441b, // 01  000  1000  0011  011
01239     ALLE1IS      = 0x641c, // 01  100  1000  0011  100
01240     VALE1IS      = 0x441d, // 01  000  1000  0011  101
01241     VALE2IS      = 0x641d, // 01  100  1000  0011  101
01242     VALE3IS      = 0x741d, // 01  110  1000  0011  101
01243     VMALLS12E1IS = 0x641e, // 01  100  1000  0011  110
01244     VAALE1IS     = 0x441f, // 01  000  1000  0011  111
01245     IPAS2E1      = 0x6421, // 01  100  1000  0100  001
01246     IPAS2LE1     = 0x6425, // 01  100  1000  0100  101
01247     VMALLE1      = 0x4438, // 01  000  1000  0111  000
01248     ALLE2        = 0x6438, // 01  100  1000  0111  000
01249     ALLE3        = 0x7438, // 01  110  1000  0111  000
01250     VAE1         = 0x4439, // 01  000  1000  0111  001
01251     VAE2         = 0x6439, // 01  100  1000  0111  001
01252     VAE3         = 0x7439, // 01  110  1000  0111  001
01253     ASIDE1       = 0x443a, // 01  000  1000  0111  010
01254     VAAE1        = 0x443b, // 01  000  1000  0111  011
01255     ALLE1        = 0x643c, // 01  100  1000  0111  100
01256     VALE1        = 0x443d, // 01  000  1000  0111  101
01257     VALE2        = 0x643d, // 01  100  1000  0111  101
01258     VALE3        = 0x743d, // 01  110  1000  0111  101
01259     VMALLS12E1   = 0x643e, // 01  100  1000  0111  110
01260     VAALE1       = 0x443f  // 01  000  1000  0111  111
01261   };
01262 
01263   struct TLBIMapper : AArch64NamedImmMapper {
01264     const static Mapping TLBIMappings[];
01265 
01266     TLBIMapper();
01267   };
01268 
01269   static inline bool NeedsRegister(TLBIValues Val) {
01270     switch (Val) {
01271     case VMALLE1IS:
01272     case ALLE2IS:
01273     case ALLE3IS:
01274     case ALLE1IS:
01275     case VMALLS12E1IS:
01276     case VMALLE1:
01277     case ALLE2:
01278     case ALLE3:
01279     case ALLE1:
01280     case VMALLS12E1:
01281       return false;
01282     default:
01283       return true;
01284     }
01285   }
01286 } 
01287 
01288 namespace AArch64II {
01289   /// Target Operand Flag enum.
01290   enum TOF {
01291     //===------------------------------------------------------------------===//
01292     // AArch64 Specific MachineOperand flags.
01293 
01294     MO_NO_FLAG,
01295 
01296     MO_FRAGMENT = 0xf,
01297 
01298     /// MO_PAGE - A symbol operand with this flag represents the pc-relative
01299     /// offset of the 4K page containing the symbol.  This is used with the
01300     /// ADRP instruction.
01301     MO_PAGE = 1,
01302 
01303     /// MO_PAGEOFF - A symbol operand with this flag represents the offset of
01304     /// that symbol within a 4K page.  This offset is added to the page address
01305     /// to produce the complete address.
01306     MO_PAGEOFF = 2,
01307 
01308     /// MO_G3 - A symbol operand with this flag (granule 3) represents the high
01309     /// 16-bits of a 64-bit address, used in a MOVZ or MOVK instruction
01310     MO_G3 = 3,
01311 
01312     /// MO_G2 - A symbol operand with this flag (granule 2) represents the bits
01313     /// 32-47 of a 64-bit address, used in a MOVZ or MOVK instruction
01314     MO_G2 = 4,
01315 
01316     /// MO_G1 - A symbol operand with this flag (granule 1) represents the bits
01317     /// 16-31 of a 64-bit address, used in a MOVZ or MOVK instruction
01318     MO_G1 = 5,
01319 
01320     /// MO_G0 - A symbol operand with this flag (granule 0) represents the bits
01321     /// 0-15 of a 64-bit address, used in a MOVZ or MOVK instruction
01322     MO_G0 = 6,
01323 
01324     /// MO_HI12 - This flag indicates that a symbol operand represents the bits
01325     /// 13-24 of a 64-bit address, used in a arithmetic immediate-shifted-left-
01326     /// by-12-bits instruction.
01327     MO_HI12 = 7,
01328 
01329     /// MO_GOT - This flag indicates that a symbol operand represents the
01330     /// address of the GOT entry for the symbol, rather than the address of
01331     /// the symbol itself.
01332     MO_GOT = 0x10,
01333 
01334     /// MO_NC - Indicates whether the linker is expected to check the symbol
01335     /// reference for overflow. For example in an ADRP/ADD pair of relocations
01336     /// the ADRP usually does check, but not the ADD.
01337     MO_NC = 0x20,
01338 
01339     /// MO_TLS - Indicates that the operand being accessed is some kind of
01340     /// thread-local symbol. On Darwin, only one type of thread-local access
01341     /// exists (pre linker-relaxation), but on ELF the TLSModel used for the
01342     /// referee will affect interpretation.
01343     MO_TLS = 0x40,
01344 
01345     /// MO_CONSTPOOL - This flag indicates that a symbol operand represents
01346     /// the address of a constant pool entry for the symbol, rather than the
01347     /// address of the symbol itself.
01348     MO_CONSTPOOL = 0x80
01349   };
01350 } // end namespace AArch64II
01351 
01352 } // end namespace llvm
01353 
01354 #endif