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AArch64BaseInfo.h
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00001 //===-- AArch64BaseInfo.h - Top level definitions for AArch64 ---*- C++ -*-===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file contains small standalone helper functions and enum definitions for
00011 // the AArch64 target useful for the compiler back-end and the MC libraries.
00012 // As such, it deliberately does not include references to LLVM core
00013 // code gen types, passes, etc..
00014 //
00015 //===----------------------------------------------------------------------===//
00016 
00017 #ifndef LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H
00018 #define LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H
00019 
00020 // FIXME: Is it easiest to fix this layering violation by moving the .inc
00021 // #includes from AArch64MCTargetDesc.h to here?
00022 #include "MCTargetDesc/AArch64MCTargetDesc.h" // For AArch64::X0 and friends.
00023 #include "llvm/ADT/STLExtras.h"
00024 #include "llvm/ADT/StringSwitch.h"
00025 #include "llvm/MC/SubtargetFeature.h"
00026 #include "llvm/Support/ErrorHandling.h"
00027 
00028 namespace llvm {
00029 
00030 inline static unsigned getWRegFromXReg(unsigned Reg) {
00031   switch (Reg) {
00032   case AArch64::X0: return AArch64::W0;
00033   case AArch64::X1: return AArch64::W1;
00034   case AArch64::X2: return AArch64::W2;
00035   case AArch64::X3: return AArch64::W3;
00036   case AArch64::X4: return AArch64::W4;
00037   case AArch64::X5: return AArch64::W5;
00038   case AArch64::X6: return AArch64::W6;
00039   case AArch64::X7: return AArch64::W7;
00040   case AArch64::X8: return AArch64::W8;
00041   case AArch64::X9: return AArch64::W9;
00042   case AArch64::X10: return AArch64::W10;
00043   case AArch64::X11: return AArch64::W11;
00044   case AArch64::X12: return AArch64::W12;
00045   case AArch64::X13: return AArch64::W13;
00046   case AArch64::X14: return AArch64::W14;
00047   case AArch64::X15: return AArch64::W15;
00048   case AArch64::X16: return AArch64::W16;
00049   case AArch64::X17: return AArch64::W17;
00050   case AArch64::X18: return AArch64::W18;
00051   case AArch64::X19: return AArch64::W19;
00052   case AArch64::X20: return AArch64::W20;
00053   case AArch64::X21: return AArch64::W21;
00054   case AArch64::X22: return AArch64::W22;
00055   case AArch64::X23: return AArch64::W23;
00056   case AArch64::X24: return AArch64::W24;
00057   case AArch64::X25: return AArch64::W25;
00058   case AArch64::X26: return AArch64::W26;
00059   case AArch64::X27: return AArch64::W27;
00060   case AArch64::X28: return AArch64::W28;
00061   case AArch64::FP: return AArch64::W29;
00062   case AArch64::LR: return AArch64::W30;
00063   case AArch64::SP: return AArch64::WSP;
00064   case AArch64::XZR: return AArch64::WZR;
00065   }
00066   // For anything else, return it unchanged.
00067   return Reg;
00068 }
00069 
00070 inline static unsigned getXRegFromWReg(unsigned Reg) {
00071   switch (Reg) {
00072   case AArch64::W0: return AArch64::X0;
00073   case AArch64::W1: return AArch64::X1;
00074   case AArch64::W2: return AArch64::X2;
00075   case AArch64::W3: return AArch64::X3;
00076   case AArch64::W4: return AArch64::X4;
00077   case AArch64::W5: return AArch64::X5;
00078   case AArch64::W6: return AArch64::X6;
00079   case AArch64::W7: return AArch64::X7;
00080   case AArch64::W8: return AArch64::X8;
00081   case AArch64::W9: return AArch64::X9;
00082   case AArch64::W10: return AArch64::X10;
00083   case AArch64::W11: return AArch64::X11;
00084   case AArch64::W12: return AArch64::X12;
00085   case AArch64::W13: return AArch64::X13;
00086   case AArch64::W14: return AArch64::X14;
00087   case AArch64::W15: return AArch64::X15;
00088   case AArch64::W16: return AArch64::X16;
00089   case AArch64::W17: return AArch64::X17;
00090   case AArch64::W18: return AArch64::X18;
00091   case AArch64::W19: return AArch64::X19;
00092   case AArch64::W20: return AArch64::X20;
00093   case AArch64::W21: return AArch64::X21;
00094   case AArch64::W22: return AArch64::X22;
00095   case AArch64::W23: return AArch64::X23;
00096   case AArch64::W24: return AArch64::X24;
00097   case AArch64::W25: return AArch64::X25;
00098   case AArch64::W26: return AArch64::X26;
00099   case AArch64::W27: return AArch64::X27;
00100   case AArch64::W28: return AArch64::X28;
00101   case AArch64::W29: return AArch64::FP;
00102   case AArch64::W30: return AArch64::LR;
00103   case AArch64::WSP: return AArch64::SP;
00104   case AArch64::WZR: return AArch64::XZR;
00105   }
00106   // For anything else, return it unchanged.
00107   return Reg;
00108 }
00109 
00110 static inline unsigned getBRegFromDReg(unsigned Reg) {
00111   switch (Reg) {
00112   case AArch64::D0:  return AArch64::B0;
00113   case AArch64::D1:  return AArch64::B1;
00114   case AArch64::D2:  return AArch64::B2;
00115   case AArch64::D3:  return AArch64::B3;
00116   case AArch64::D4:  return AArch64::B4;
00117   case AArch64::D5:  return AArch64::B5;
00118   case AArch64::D6:  return AArch64::B6;
00119   case AArch64::D7:  return AArch64::B7;
00120   case AArch64::D8:  return AArch64::B8;
00121   case AArch64::D9:  return AArch64::B9;
00122   case AArch64::D10: return AArch64::B10;
00123   case AArch64::D11: return AArch64::B11;
00124   case AArch64::D12: return AArch64::B12;
00125   case AArch64::D13: return AArch64::B13;
00126   case AArch64::D14: return AArch64::B14;
00127   case AArch64::D15: return AArch64::B15;
00128   case AArch64::D16: return AArch64::B16;
00129   case AArch64::D17: return AArch64::B17;
00130   case AArch64::D18: return AArch64::B18;
00131   case AArch64::D19: return AArch64::B19;
00132   case AArch64::D20: return AArch64::B20;
00133   case AArch64::D21: return AArch64::B21;
00134   case AArch64::D22: return AArch64::B22;
00135   case AArch64::D23: return AArch64::B23;
00136   case AArch64::D24: return AArch64::B24;
00137   case AArch64::D25: return AArch64::B25;
00138   case AArch64::D26: return AArch64::B26;
00139   case AArch64::D27: return AArch64::B27;
00140   case AArch64::D28: return AArch64::B28;
00141   case AArch64::D29: return AArch64::B29;
00142   case AArch64::D30: return AArch64::B30;
00143   case AArch64::D31: return AArch64::B31;
00144   }
00145   // For anything else, return it unchanged.
00146   return Reg;
00147 }
00148 
00149 
00150 static inline unsigned getDRegFromBReg(unsigned Reg) {
00151   switch (Reg) {
00152   case AArch64::B0:  return AArch64::D0;
00153   case AArch64::B1:  return AArch64::D1;
00154   case AArch64::B2:  return AArch64::D2;
00155   case AArch64::B3:  return AArch64::D3;
00156   case AArch64::B4:  return AArch64::D4;
00157   case AArch64::B5:  return AArch64::D5;
00158   case AArch64::B6:  return AArch64::D6;
00159   case AArch64::B7:  return AArch64::D7;
00160   case AArch64::B8:  return AArch64::D8;
00161   case AArch64::B9:  return AArch64::D9;
00162   case AArch64::B10: return AArch64::D10;
00163   case AArch64::B11: return AArch64::D11;
00164   case AArch64::B12: return AArch64::D12;
00165   case AArch64::B13: return AArch64::D13;
00166   case AArch64::B14: return AArch64::D14;
00167   case AArch64::B15: return AArch64::D15;
00168   case AArch64::B16: return AArch64::D16;
00169   case AArch64::B17: return AArch64::D17;
00170   case AArch64::B18: return AArch64::D18;
00171   case AArch64::B19: return AArch64::D19;
00172   case AArch64::B20: return AArch64::D20;
00173   case AArch64::B21: return AArch64::D21;
00174   case AArch64::B22: return AArch64::D22;
00175   case AArch64::B23: return AArch64::D23;
00176   case AArch64::B24: return AArch64::D24;
00177   case AArch64::B25: return AArch64::D25;
00178   case AArch64::B26: return AArch64::D26;
00179   case AArch64::B27: return AArch64::D27;
00180   case AArch64::B28: return AArch64::D28;
00181   case AArch64::B29: return AArch64::D29;
00182   case AArch64::B30: return AArch64::D30;
00183   case AArch64::B31: return AArch64::D31;
00184   }
00185   // For anything else, return it unchanged.
00186   return Reg;
00187 }
00188 
00189 namespace AArch64CC {
00190 
00191 // The CondCodes constants map directly to the 4-bit encoding of the condition
00192 // field for predicated instructions.
00193 enum CondCode {  // Meaning (integer)          Meaning (floating-point)
00194   EQ = 0x0,      // Equal                      Equal
00195   NE = 0x1,      // Not equal                  Not equal, or unordered
00196   HS = 0x2,      // Unsigned higher or same    >, ==, or unordered
00197   LO = 0x3,      // Unsigned lower             Less than
00198   MI = 0x4,      // Minus, negative            Less than
00199   PL = 0x5,      // Plus, positive or zero     >, ==, or unordered
00200   VS = 0x6,      // Overflow                   Unordered
00201   VC = 0x7,      // No overflow                Not unordered
00202   HI = 0x8,      // Unsigned higher            Greater than, or unordered
00203   LS = 0x9,      // Unsigned lower or same     Less than or equal
00204   GE = 0xa,      // Greater than or equal      Greater than or equal
00205   LT = 0xb,      // Less than                  Less than, or unordered
00206   GT = 0xc,      // Greater than               Greater than
00207   LE = 0xd,      // Less than or equal         <, ==, or unordered
00208   AL = 0xe,      // Always (unconditional)     Always (unconditional)
00209   NV = 0xf,      // Always (unconditional)     Always (unconditional)
00210   // Note the NV exists purely to disassemble 0b1111. Execution is "always".
00211   Invalid
00212 };
00213 
00214 inline static const char *getCondCodeName(CondCode Code) {
00215   switch (Code) {
00216   default: llvm_unreachable("Unknown condition code");
00217   case EQ:  return "eq";
00218   case NE:  return "ne";
00219   case HS:  return "hs";
00220   case LO:  return "lo";
00221   case MI:  return "mi";
00222   case PL:  return "pl";
00223   case VS:  return "vs";
00224   case VC:  return "vc";
00225   case HI:  return "hi";
00226   case LS:  return "ls";
00227   case GE:  return "ge";
00228   case LT:  return "lt";
00229   case GT:  return "gt";
00230   case LE:  return "le";
00231   case AL:  return "al";
00232   case NV:  return "nv";
00233   }
00234 }
00235 
00236 inline static CondCode getInvertedCondCode(CondCode Code) {
00237   // To reverse a condition it's necessary to only invert the low bit:
00238 
00239   return static_cast<CondCode>(static_cast<unsigned>(Code) ^ 0x1);
00240 }
00241 
00242 /// Given a condition code, return NZCV flags that would satisfy that condition.
00243 /// The flag bits are in the format expected by the ccmp instructions.
00244 /// Note that many different flag settings can satisfy a given condition code,
00245 /// this function just returns one of them.
00246 inline static unsigned getNZCVToSatisfyCondCode(CondCode Code) {
00247   // NZCV flags encoded as expected by ccmp instructions, ARMv8 ISA 5.5.7.
00248   enum { N = 8, Z = 4, C = 2, V = 1 };
00249   switch (Code) {
00250   default: llvm_unreachable("Unknown condition code");
00251   case EQ: return Z; // Z == 1
00252   case NE: return 0; // Z == 0
00253   case HS: return C; // C == 1
00254   case LO: return 0; // C == 0
00255   case MI: return N; // N == 1
00256   case PL: return 0; // N == 0
00257   case VS: return V; // V == 1
00258   case VC: return 0; // V == 0
00259   case HI: return C; // C == 1 && Z == 0
00260   case LS: return 0; // C == 0 || Z == 1
00261   case GE: return 0; // N == V
00262   case LT: return N; // N != V
00263   case GT: return 0; // Z == 0 && N == V
00264   case LE: return Z; // Z == 1 || N != V
00265   }
00266 }
00267 } // end namespace AArch64CC
00268 
00269 /// Instances of this class can perform bidirectional mapping from random
00270 /// identifier strings to operand encodings. For example "MSR" takes a named
00271 /// system-register which must be encoded somehow and decoded for printing. This
00272 /// central location means that the information for those transformations is not
00273 /// duplicated and remains in sync.
00274 ///
00275 /// FIXME: currently the algorithm is a completely unoptimised linear
00276 /// search. Obviously this could be improved, but we would probably want to work
00277 /// out just how often these instructions are emitted before working on it. It
00278 /// might even be optimal to just reorder the tables for the common instructions
00279 /// rather than changing the algorithm.
00280 struct AArch64NamedImmMapper {
00281   struct Mapping {
00282     const char *Name;
00283     uint32_t Value;
00284     // Set of features this mapping is available for
00285     // Zero value of FeatureBitSet means the mapping is always available
00286     FeatureBitset FeatureBitSet;
00287 
00288     bool isNameEqual(std::string Other,
00289                      const FeatureBitset& FeatureBits) const {
00290       if (FeatureBitSet.any() &&
00291           (FeatureBitSet & FeatureBits).none())
00292         return false;
00293       return Name == Other;
00294     }
00295 
00296     bool isValueEqual(uint32_t Other,
00297                       const FeatureBitset& FeatureBits) const {
00298       if (FeatureBitSet.any() &&
00299           (FeatureBitSet & FeatureBits).none())
00300         return false;
00301       return Value == Other;
00302     }
00303   };
00304 
00305   template<int N>
00306   AArch64NamedImmMapper(const Mapping (&Mappings)[N], uint32_t TooBigImm)
00307     : Mappings(&Mappings[0]), NumMappings(N), TooBigImm(TooBigImm) {}
00308 
00309   // Maps value to string, depending on availability for FeatureBits given
00310   StringRef toString(uint32_t Value, const FeatureBitset& FeatureBits,
00311                      bool &Valid) const;
00312   // Maps string to value, depending on availability for FeatureBits given
00313   uint32_t fromString(StringRef Name, const FeatureBitset& FeatureBits,
00314                      bool &Valid) const;
00315 
00316   /// Many of the instructions allow an alternative assembly form consisting of
00317   /// a simple immediate. Currently the only valid forms are ranges [0, N) where
00318   /// N being 0 indicates no immediate syntax-form is allowed.
00319   bool validImm(uint32_t Value) const;
00320 protected:
00321   const Mapping *Mappings;
00322   size_t NumMappings;
00323   uint32_t TooBigImm;
00324 };
00325 
00326 namespace AArch64AT {
00327   enum ATValues {
00328     Invalid = -1,    // Op0 Op1  CRn   CRm   Op2
00329     S1E1R = 0x43c0,  // 01  000  0111  1000  000
00330     S1E2R = 0x63c0,  // 01  100  0111  1000  000
00331     S1E3R = 0x73c0,  // 01  110  0111  1000  000
00332     S1E1W = 0x43c1,  // 01  000  0111  1000  001
00333     S1E2W = 0x63c1,  // 01  100  0111  1000  001
00334     S1E3W = 0x73c1,  // 01  110  0111  1000  001
00335     S1E0R = 0x43c2,  // 01  000  0111  1000  010
00336     S1E0W = 0x43c3,  // 01  000  0111  1000  011
00337     S12E1R = 0x63c4, // 01  100  0111  1000  100
00338     S12E1W = 0x63c5, // 01  100  0111  1000  101
00339     S12E0R = 0x63c6, // 01  100  0111  1000  110
00340     S12E0W = 0x63c7, // 01  100  0111  1000  111
00341     S1E1RP = 0x43c8, // 01  000  0111  1001  000
00342     S1E1WP = 0x43c9  // 01  000  0111  1001  001
00343   };
00344 
00345   struct ATMapper : AArch64NamedImmMapper {
00346     const static Mapping ATMappings[];
00347 
00348     ATMapper();
00349   };
00350 
00351 }
00352 namespace AArch64DB {
00353   enum DBValues {
00354     Invalid = -1,
00355     OSHLD = 0x1,
00356     OSHST = 0x2,
00357     OSH =   0x3,
00358     NSHLD = 0x5,
00359     NSHST = 0x6,
00360     NSH =   0x7,
00361     ISHLD = 0x9,
00362     ISHST = 0xa,
00363     ISH =   0xb,
00364     LD =    0xd,
00365     ST =    0xe,
00366     SY =    0xf
00367   };
00368 
00369   struct DBarrierMapper : AArch64NamedImmMapper {
00370     const static Mapping DBarrierMappings[];
00371 
00372     DBarrierMapper();
00373   };
00374 }
00375 
00376 namespace  AArch64DC {
00377   enum DCValues {
00378     Invalid = -1,   // Op1  CRn   CRm   Op2
00379     ZVA   = 0x5ba1, // 01  011  0111  0100  001
00380     IVAC  = 0x43b1, // 01  000  0111  0110  001
00381     ISW   = 0x43b2, // 01  000  0111  0110  010
00382     CVAC  = 0x5bd1, // 01  011  0111  1010  001
00383     CSW   = 0x43d2, // 01  000  0111  1010  010
00384     CVAU  = 0x5bd9, // 01  011  0111  1011  001
00385     CIVAC = 0x5bf1, // 01  011  0111  1110  001
00386     CISW  = 0x43f2  // 01  000  0111  1110  010
00387   };
00388 
00389   struct DCMapper : AArch64NamedImmMapper {
00390     const static Mapping DCMappings[];
00391 
00392     DCMapper();
00393   };
00394 
00395 }
00396 
00397 namespace  AArch64IC {
00398   enum ICValues {
00399     Invalid = -1,     // Op1  CRn   CRm   Op2
00400     IALLUIS = 0x0388, // 000  0111  0001  000
00401     IALLU = 0x03a8,   // 000  0111  0101  000
00402     IVAU = 0x1ba9     // 011  0111  0101  001
00403   };
00404 
00405 
00406   struct ICMapper : AArch64NamedImmMapper {
00407     const static Mapping ICMappings[];
00408 
00409     ICMapper();
00410   };
00411 
00412   static inline bool NeedsRegister(ICValues Val) {
00413     return Val == IVAU;
00414   }
00415 }
00416 
00417 namespace  AArch64ISB {
00418   enum ISBValues {
00419     Invalid = -1,
00420     SY = 0xf
00421   };
00422   struct ISBMapper : AArch64NamedImmMapper {
00423     const static Mapping ISBMappings[];
00424 
00425     ISBMapper();
00426   };
00427 }
00428 
00429 namespace AArch64PRFM {
00430   enum PRFMValues {
00431     Invalid = -1,
00432     PLDL1KEEP = 0x00,
00433     PLDL1STRM = 0x01,
00434     PLDL2KEEP = 0x02,
00435     PLDL2STRM = 0x03,
00436     PLDL3KEEP = 0x04,
00437     PLDL3STRM = 0x05,
00438     PLIL1KEEP = 0x08,
00439     PLIL1STRM = 0x09,
00440     PLIL2KEEP = 0x0a,
00441     PLIL2STRM = 0x0b,
00442     PLIL3KEEP = 0x0c,
00443     PLIL3STRM = 0x0d,
00444     PSTL1KEEP = 0x10,
00445     PSTL1STRM = 0x11,
00446     PSTL2KEEP = 0x12,
00447     PSTL2STRM = 0x13,
00448     PSTL3KEEP = 0x14,
00449     PSTL3STRM = 0x15
00450   };
00451 
00452   struct PRFMMapper : AArch64NamedImmMapper {
00453     const static Mapping PRFMMappings[];
00454 
00455     PRFMMapper();
00456   };
00457 }
00458 
00459 namespace AArch64PState {
00460   enum PStateValues {
00461     Invalid = -1,
00462     SPSel = 0x05,
00463     DAIFSet = 0x1e,
00464     DAIFClr = 0x1f,
00465 
00466     // v8.1a "Privileged Access Never" extension-specific PStates
00467     PAN = 0x04,
00468 
00469     // v8.2a "User Access Override" extension-specific PStates
00470     UAO = 0x03
00471   };
00472 
00473   struct PStateMapper : AArch64NamedImmMapper {
00474     const static Mapping PStateMappings[];
00475 
00476     PStateMapper();
00477   };
00478 
00479 }
00480 
00481 namespace AArch64PSBHint {
00482   enum PSBHintValues {
00483     Invalid = -1,
00484     // v8.2a "Statistical Profiling" extension-specific PSB operands
00485     CSync = 0x11,  // psb csync = hint #0x11
00486   };
00487 
00488   struct PSBHintMapper : AArch64NamedImmMapper {
00489     const static Mapping PSBHintMappings[];
00490 
00491     PSBHintMapper();
00492   };
00493 
00494 }
00495 
00496 namespace AArch64SE {
00497     enum ShiftExtSpecifiers {
00498         Invalid = -1,
00499         LSL,
00500         MSL,
00501         LSR,
00502         ASR,
00503         ROR,
00504 
00505         UXTB,
00506         UXTH,
00507         UXTW,
00508         UXTX,
00509 
00510         SXTB,
00511         SXTH,
00512         SXTW,
00513         SXTX
00514     };
00515 }
00516 
00517 namespace AArch64Layout {
00518     enum VectorLayout {
00519         Invalid = -1,
00520         VL_8B,
00521         VL_4H,
00522         VL_2S,
00523         VL_1D,
00524 
00525         VL_16B,
00526         VL_8H,
00527         VL_4S,
00528         VL_2D,
00529 
00530         // Bare layout for the 128-bit vector
00531         // (only show ".b", ".h", ".s", ".d" without vector number)
00532         VL_B,
00533         VL_H,
00534         VL_S,
00535         VL_D
00536     };
00537 }
00538 
00539 inline static const char *
00540 AArch64VectorLayoutToString(AArch64Layout::VectorLayout Layout) {
00541   switch (Layout) {
00542   case AArch64Layout::VL_8B:  return ".8b";
00543   case AArch64Layout::VL_4H:  return ".4h";
00544   case AArch64Layout::VL_2S:  return ".2s";
00545   case AArch64Layout::VL_1D:  return ".1d";
00546   case AArch64Layout::VL_16B:  return ".16b";
00547   case AArch64Layout::VL_8H:  return ".8h";
00548   case AArch64Layout::VL_4S:  return ".4s";
00549   case AArch64Layout::VL_2D:  return ".2d";
00550   case AArch64Layout::VL_B:  return ".b";
00551   case AArch64Layout::VL_H:  return ".h";
00552   case AArch64Layout::VL_S:  return ".s";
00553   case AArch64Layout::VL_D:  return ".d";
00554   default: llvm_unreachable("Unknown Vector Layout");
00555   }
00556 }
00557 
00558 inline static AArch64Layout::VectorLayout
00559 AArch64StringToVectorLayout(StringRef LayoutStr) {
00560   return StringSwitch<AArch64Layout::VectorLayout>(LayoutStr)
00561              .Case(".8b", AArch64Layout::VL_8B)
00562              .Case(".4h", AArch64Layout::VL_4H)
00563              .Case(".2s", AArch64Layout::VL_2S)
00564              .Case(".1d", AArch64Layout::VL_1D)
00565              .Case(".16b", AArch64Layout::VL_16B)
00566              .Case(".8h", AArch64Layout::VL_8H)
00567              .Case(".4s", AArch64Layout::VL_4S)
00568              .Case(".2d", AArch64Layout::VL_2D)
00569              .Case(".b", AArch64Layout::VL_B)
00570              .Case(".h", AArch64Layout::VL_H)
00571              .Case(".s", AArch64Layout::VL_S)
00572              .Case(".d", AArch64Layout::VL_D)
00573              .Default(AArch64Layout::Invalid);
00574 }
00575 
00576 namespace AArch64SysReg {
00577   enum SysRegROValues {
00578     MDCCSR_EL0        = 0x9808, // 10  011  0000  0001  000
00579     DBGDTRRX_EL0      = 0x9828, // 10  011  0000  0101  000
00580     MDRAR_EL1         = 0x8080, // 10  000  0001  0000  000
00581     OSLSR_EL1         = 0x808c, // 10  000  0001  0001  100
00582     DBGAUTHSTATUS_EL1 = 0x83f6, // 10  000  0111  1110  110
00583     PMCEID0_EL0       = 0xdce6, // 11  011  1001  1100  110
00584     PMCEID1_EL0       = 0xdce7, // 11  011  1001  1100  111
00585     MIDR_EL1          = 0xc000, // 11  000  0000  0000  000
00586     CCSIDR_EL1        = 0xc800, // 11  001  0000  0000  000
00587     CLIDR_EL1         = 0xc801, // 11  001  0000  0000  001
00588     CTR_EL0           = 0xd801, // 11  011  0000  0000  001
00589     MPIDR_EL1         = 0xc005, // 11  000  0000  0000  101
00590     REVIDR_EL1        = 0xc006, // 11  000  0000  0000  110
00591     AIDR_EL1          = 0xc807, // 11  001  0000  0000  111
00592     DCZID_EL0         = 0xd807, // 11  011  0000  0000  111
00593     ID_PFR0_EL1       = 0xc008, // 11  000  0000  0001  000
00594     ID_PFR1_EL1       = 0xc009, // 11  000  0000  0001  001
00595     ID_DFR0_EL1       = 0xc00a, // 11  000  0000  0001  010
00596     ID_AFR0_EL1       = 0xc00b, // 11  000  0000  0001  011
00597     ID_MMFR0_EL1      = 0xc00c, // 11  000  0000  0001  100
00598     ID_MMFR1_EL1      = 0xc00d, // 11  000  0000  0001  101
00599     ID_MMFR2_EL1      = 0xc00e, // 11  000  0000  0001  110
00600     ID_MMFR3_EL1      = 0xc00f, // 11  000  0000  0001  111
00601     ID_ISAR0_EL1      = 0xc010, // 11  000  0000  0010  000
00602     ID_ISAR1_EL1      = 0xc011, // 11  000  0000  0010  001
00603     ID_ISAR2_EL1      = 0xc012, // 11  000  0000  0010  010
00604     ID_ISAR3_EL1      = 0xc013, // 11  000  0000  0010  011
00605     ID_ISAR4_EL1      = 0xc014, // 11  000  0000  0010  100
00606     ID_ISAR5_EL1      = 0xc015, // 11  000  0000  0010  101
00607     ID_A64PFR0_EL1    = 0xc020, // 11  000  0000  0100  000
00608     ID_A64PFR1_EL1    = 0xc021, // 11  000  0000  0100  001
00609     ID_A64DFR0_EL1    = 0xc028, // 11  000  0000  0101  000
00610     ID_A64DFR1_EL1    = 0xc029, // 11  000  0000  0101  001
00611     ID_A64AFR0_EL1    = 0xc02c, // 11  000  0000  0101  100
00612     ID_A64AFR1_EL1    = 0xc02d, // 11  000  0000  0101  101
00613     ID_A64ISAR0_EL1   = 0xc030, // 11  000  0000  0110  000
00614     ID_A64ISAR1_EL1   = 0xc031, // 11  000  0000  0110  001
00615     ID_A64MMFR0_EL1   = 0xc038, // 11  000  0000  0111  000
00616     ID_A64MMFR1_EL1   = 0xc039, // 11  000  0000  0111  001
00617     ID_A64MMFR2_EL1   = 0xc03a, // 11  000  0000  0111  010
00618     MVFR0_EL1         = 0xc018, // 11  000  0000  0011  000
00619     MVFR1_EL1         = 0xc019, // 11  000  0000  0011  001
00620     MVFR2_EL1         = 0xc01a, // 11  000  0000  0011  010
00621     RVBAR_EL1         = 0xc601, // 11  000  1100  0000  001
00622     RVBAR_EL2         = 0xe601, // 11  100  1100  0000  001
00623     RVBAR_EL3         = 0xf601, // 11  110  1100  0000  001
00624     ISR_EL1           = 0xc608, // 11  000  1100  0001  000
00625     CNTPCT_EL0        = 0xdf01, // 11  011  1110  0000  001
00626     CNTVCT_EL0        = 0xdf02,  // 11  011  1110  0000  010
00627     ID_MMFR4_EL1      = 0xc016,  // 11  000  0000  0010  110
00628 
00629     // Trace registers
00630     TRCSTATR          = 0x8818, // 10  001  0000  0011  000
00631     TRCIDR8           = 0x8806, // 10  001  0000  0000  110
00632     TRCIDR9           = 0x880e, // 10  001  0000  0001  110
00633     TRCIDR10          = 0x8816, // 10  001  0000  0010  110
00634     TRCIDR11          = 0x881e, // 10  001  0000  0011  110
00635     TRCIDR12          = 0x8826, // 10  001  0000  0100  110
00636     TRCIDR13          = 0x882e, // 10  001  0000  0101  110
00637     TRCIDR0           = 0x8847, // 10  001  0000  1000  111
00638     TRCIDR1           = 0x884f, // 10  001  0000  1001  111
00639     TRCIDR2           = 0x8857, // 10  001  0000  1010  111
00640     TRCIDR3           = 0x885f, // 10  001  0000  1011  111
00641     TRCIDR4           = 0x8867, // 10  001  0000  1100  111
00642     TRCIDR5           = 0x886f, // 10  001  0000  1101  111
00643     TRCIDR6           = 0x8877, // 10  001  0000  1110  111
00644     TRCIDR7           = 0x887f, // 10  001  0000  1111  111
00645     TRCOSLSR          = 0x888c, // 10  001  0001  0001  100
00646     TRCPDSR           = 0x88ac, // 10  001  0001  0101  100
00647     TRCDEVAFF0        = 0x8bd6, // 10  001  0111  1010  110
00648     TRCDEVAFF1        = 0x8bde, // 10  001  0111  1011  110
00649     TRCLSR            = 0x8bee, // 10  001  0111  1101  110
00650     TRCAUTHSTATUS     = 0x8bf6, // 10  001  0111  1110  110
00651     TRCDEVARCH        = 0x8bfe, // 10  001  0111  1111  110
00652     TRCDEVID          = 0x8b97, // 10  001  0111  0010  111
00653     TRCDEVTYPE        = 0x8b9f, // 10  001  0111  0011  111
00654     TRCPIDR4          = 0x8ba7, // 10  001  0111  0100  111
00655     TRCPIDR5          = 0x8baf, // 10  001  0111  0101  111
00656     TRCPIDR6          = 0x8bb7, // 10  001  0111  0110  111
00657     TRCPIDR7          = 0x8bbf, // 10  001  0111  0111  111
00658     TRCPIDR0          = 0x8bc7, // 10  001  0111  1000  111
00659     TRCPIDR1          = 0x8bcf, // 10  001  0111  1001  111
00660     TRCPIDR2          = 0x8bd7, // 10  001  0111  1010  111
00661     TRCPIDR3          = 0x8bdf, // 10  001  0111  1011  111
00662     TRCCIDR0          = 0x8be7, // 10  001  0111  1100  111
00663     TRCCIDR1          = 0x8bef, // 10  001  0111  1101  111
00664     TRCCIDR2          = 0x8bf7, // 10  001  0111  1110  111
00665     TRCCIDR3          = 0x8bff, // 10  001  0111  1111  111
00666 
00667     // GICv3 registers
00668     ICC_IAR1_EL1      = 0xc660, // 11  000  1100  1100  000
00669     ICC_IAR0_EL1      = 0xc640, // 11  000  1100  1000  000
00670     ICC_HPPIR1_EL1    = 0xc662, // 11  000  1100  1100  010
00671     ICC_HPPIR0_EL1    = 0xc642, // 11  000  1100  1000  010
00672     ICC_RPR_EL1       = 0xc65b, // 11  000  1100  1011  011
00673     ICH_VTR_EL2       = 0xe659, // 11  100  1100  1011  001
00674     ICH_EISR_EL2      = 0xe65b, // 11  100  1100  1011  011
00675     ICH_ELSR_EL2      = 0xe65d  // 11  100  1100  1011  101
00676   };
00677 
00678   enum SysRegWOValues {
00679     DBGDTRTX_EL0      = 0x9828, // 10  011  0000  0101  000
00680     OSLAR_EL1         = 0x8084, // 10  000  0001  0000  100
00681     PMSWINC_EL0       = 0xdce4,  // 11  011  1001  1100  100
00682 
00683     // Trace Registers
00684     TRCOSLAR          = 0x8884, // 10  001  0001  0000  100
00685     TRCLAR            = 0x8be6, // 10  001  0111  1100  110
00686 
00687     // GICv3 registers
00688     ICC_EOIR1_EL1     = 0xc661, // 11  000  1100  1100  001
00689     ICC_EOIR0_EL1     = 0xc641, // 11  000  1100  1000  001
00690     ICC_DIR_EL1       = 0xc659, // 11  000  1100  1011  001
00691     ICC_SGI1R_EL1     = 0xc65d, // 11  000  1100  1011  101
00692     ICC_ASGI1R_EL1    = 0xc65e, // 11  000  1100  1011  110
00693     ICC_SGI0R_EL1     = 0xc65f  // 11  000  1100  1011  111
00694   };
00695 
00696   enum SysRegValues {
00697     Invalid = -1,               // Op0 Op1  CRn   CRm   Op2
00698     OSDTRRX_EL1       = 0x8002, // 10  000  0000  0000  010
00699     OSDTRTX_EL1       = 0x801a, // 10  000  0000  0011  010
00700     TEECR32_EL1       = 0x9000, // 10  010  0000  0000  000
00701     MDCCINT_EL1       = 0x8010, // 10  000  0000  0010  000
00702     MDSCR_EL1         = 0x8012, // 10  000  0000  0010  010
00703     DBGDTR_EL0        = 0x9820, // 10  011  0000  0100  000
00704     OSECCR_EL1        = 0x8032, // 10  000  0000  0110  010
00705     DBGVCR32_EL2      = 0xa038, // 10  100  0000  0111  000
00706     DBGBVR0_EL1       = 0x8004, // 10  000  0000  0000  100
00707     DBGBVR1_EL1       = 0x800c, // 10  000  0000  0001  100
00708     DBGBVR2_EL1       = 0x8014, // 10  000  0000  0010  100
00709     DBGBVR3_EL1       = 0x801c, // 10  000  0000  0011  100
00710     DBGBVR4_EL1       = 0x8024, // 10  000  0000  0100  100
00711     DBGBVR5_EL1       = 0x802c, // 10  000  0000  0101  100
00712     DBGBVR6_EL1       = 0x8034, // 10  000  0000  0110  100
00713     DBGBVR7_EL1       = 0x803c, // 10  000  0000  0111  100
00714     DBGBVR8_EL1       = 0x8044, // 10  000  0000  1000  100
00715     DBGBVR9_EL1       = 0x804c, // 10  000  0000  1001  100
00716     DBGBVR10_EL1      = 0x8054, // 10  000  0000  1010  100
00717     DBGBVR11_EL1      = 0x805c, // 10  000  0000  1011  100
00718     DBGBVR12_EL1      = 0x8064, // 10  000  0000  1100  100
00719     DBGBVR13_EL1      = 0x806c, // 10  000  0000  1101  100
00720     DBGBVR14_EL1      = 0x8074, // 10  000  0000  1110  100
00721     DBGBVR15_EL1      = 0x807c, // 10  000  0000  1111  100
00722     DBGBCR0_EL1       = 0x8005, // 10  000  0000  0000  101
00723     DBGBCR1_EL1       = 0x800d, // 10  000  0000  0001  101
00724     DBGBCR2_EL1       = 0x8015, // 10  000  0000  0010  101
00725     DBGBCR3_EL1       = 0x801d, // 10  000  0000  0011  101
00726     DBGBCR4_EL1       = 0x8025, // 10  000  0000  0100  101
00727     DBGBCR5_EL1       = 0x802d, // 10  000  0000  0101  101
00728     DBGBCR6_EL1       = 0x8035, // 10  000  0000  0110  101
00729     DBGBCR7_EL1       = 0x803d, // 10  000  0000  0111  101
00730     DBGBCR8_EL1       = 0x8045, // 10  000  0000  1000  101
00731     DBGBCR9_EL1       = 0x804d, // 10  000  0000  1001  101
00732     DBGBCR10_EL1      = 0x8055, // 10  000  0000  1010  101
00733     DBGBCR11_EL1      = 0x805d, // 10  000  0000  1011  101
00734     DBGBCR12_EL1      = 0x8065, // 10  000  0000  1100  101
00735     DBGBCR13_EL1      = 0x806d, // 10  000  0000  1101  101
00736     DBGBCR14_EL1      = 0x8075, // 10  000  0000  1110  101
00737     DBGBCR15_EL1      = 0x807d, // 10  000  0000  1111  101
00738     DBGWVR0_EL1       = 0x8006, // 10  000  0000  0000  110
00739     DBGWVR1_EL1       = 0x800e, // 10  000  0000  0001  110
00740     DBGWVR2_EL1       = 0x8016, // 10  000  0000  0010  110
00741     DBGWVR3_EL1       = 0x801e, // 10  000  0000  0011  110
00742     DBGWVR4_EL1       = 0x8026, // 10  000  0000  0100  110
00743     DBGWVR5_EL1       = 0x802e, // 10  000  0000  0101  110
00744     DBGWVR6_EL1       = 0x8036, // 10  000  0000  0110  110
00745     DBGWVR7_EL1       = 0x803e, // 10  000  0000  0111  110
00746     DBGWVR8_EL1       = 0x8046, // 10  000  0000  1000  110
00747     DBGWVR9_EL1       = 0x804e, // 10  000  0000  1001  110
00748     DBGWVR10_EL1      = 0x8056, // 10  000  0000  1010  110
00749     DBGWVR11_EL1      = 0x805e, // 10  000  0000  1011  110
00750     DBGWVR12_EL1      = 0x8066, // 10  000  0000  1100  110
00751     DBGWVR13_EL1      = 0x806e, // 10  000  0000  1101  110
00752     DBGWVR14_EL1      = 0x8076, // 10  000  0000  1110  110
00753     DBGWVR15_EL1      = 0x807e, // 10  000  0000  1111  110
00754     DBGWCR0_EL1       = 0x8007, // 10  000  0000  0000  111
00755     DBGWCR1_EL1       = 0x800f, // 10  000  0000  0001  111
00756     DBGWCR2_EL1       = 0x8017, // 10  000  0000  0010  111
00757     DBGWCR3_EL1       = 0x801f, // 10  000  0000  0011  111
00758     DBGWCR4_EL1       = 0x8027, // 10  000  0000  0100  111
00759     DBGWCR5_EL1       = 0x802f, // 10  000  0000  0101  111
00760     DBGWCR6_EL1       = 0x8037, // 10  000  0000  0110  111
00761     DBGWCR7_EL1       = 0x803f, // 10  000  0000  0111  111
00762     DBGWCR8_EL1       = 0x8047, // 10  000  0000  1000  111
00763     DBGWCR9_EL1       = 0x804f, // 10  000  0000  1001  111
00764     DBGWCR10_EL1      = 0x8057, // 10  000  0000  1010  111
00765     DBGWCR11_EL1      = 0x805f, // 10  000  0000  1011  111
00766     DBGWCR12_EL1      = 0x8067, // 10  000  0000  1100  111
00767     DBGWCR13_EL1      = 0x806f, // 10  000  0000  1101  111
00768     DBGWCR14_EL1      = 0x8077, // 10  000  0000  1110  111
00769     DBGWCR15_EL1      = 0x807f, // 10  000  0000  1111  111
00770     TEEHBR32_EL1      = 0x9080, // 10  010  0001  0000  000
00771     OSDLR_EL1         = 0x809c, // 10  000  0001  0011  100
00772     DBGPRCR_EL1       = 0x80a4, // 10  000  0001  0100  100
00773     DBGCLAIMSET_EL1   = 0x83c6, // 10  000  0111  1000  110
00774     DBGCLAIMCLR_EL1   = 0x83ce, // 10  000  0111  1001  110
00775     CSSELR_EL1        = 0xd000, // 11  010  0000  0000  000
00776     VPIDR_EL2         = 0xe000, // 11  100  0000  0000  000
00777     VMPIDR_EL2        = 0xe005, // 11  100  0000  0000  101
00778     CPACR_EL1         = 0xc082, // 11  000  0001  0000  010
00779     SCTLR_EL1         = 0xc080, // 11  000  0001  0000  000
00780     SCTLR_EL2         = 0xe080, // 11  100  0001  0000  000
00781     SCTLR_EL3         = 0xf080, // 11  110  0001  0000  000
00782     ACTLR_EL1         = 0xc081, // 11  000  0001  0000  001
00783     ACTLR_EL2         = 0xe081, // 11  100  0001  0000  001
00784     ACTLR_EL3         = 0xf081, // 11  110  0001  0000  001
00785     HCR_EL2           = 0xe088, // 11  100  0001  0001  000
00786     SCR_EL3           = 0xf088, // 11  110  0001  0001  000
00787     MDCR_EL2          = 0xe089, // 11  100  0001  0001  001
00788     SDER32_EL3        = 0xf089, // 11  110  0001  0001  001
00789     CPTR_EL2          = 0xe08a, // 11  100  0001  0001  010
00790     CPTR_EL3          = 0xf08a, // 11  110  0001  0001  010
00791     HSTR_EL2          = 0xe08b, // 11  100  0001  0001  011
00792     HACR_EL2          = 0xe08f, // 11  100  0001  0001  111
00793     MDCR_EL3          = 0xf099, // 11  110  0001  0011  001
00794     TTBR0_EL1         = 0xc100, // 11  000  0010  0000  000
00795     TTBR0_EL2         = 0xe100, // 11  100  0010  0000  000
00796     TTBR0_EL3         = 0xf100, // 11  110  0010  0000  000
00797     TTBR1_EL1         = 0xc101, // 11  000  0010  0000  001
00798     TCR_EL1           = 0xc102, // 11  000  0010  0000  010
00799     TCR_EL2           = 0xe102, // 11  100  0010  0000  010
00800     TCR_EL3           = 0xf102, // 11  110  0010  0000  010
00801     VTTBR_EL2         = 0xe108, // 11  100  0010  0001  000
00802     VTCR_EL2          = 0xe10a, // 11  100  0010  0001  010
00803     DACR32_EL2        = 0xe180, // 11  100  0011  0000  000
00804     SPSR_EL1          = 0xc200, // 11  000  0100  0000  000
00805     SPSR_EL2          = 0xe200, // 11  100  0100  0000  000
00806     SPSR_EL3          = 0xf200, // 11  110  0100  0000  000
00807     ELR_EL1           = 0xc201, // 11  000  0100  0000  001
00808     ELR_EL2           = 0xe201, // 11  100  0100  0000  001
00809     ELR_EL3           = 0xf201, // 11  110  0100  0000  001
00810     SP_EL0            = 0xc208, // 11  000  0100  0001  000
00811     SP_EL1            = 0xe208, // 11  100  0100  0001  000
00812     SP_EL2            = 0xf208, // 11  110  0100  0001  000
00813     SPSel             = 0xc210, // 11  000  0100  0010  000
00814     NZCV              = 0xda10, // 11  011  0100  0010  000
00815     DAIF              = 0xda11, // 11  011  0100  0010  001
00816     CurrentEL         = 0xc212, // 11  000  0100  0010  010
00817     SPSR_irq          = 0xe218, // 11  100  0100  0011  000
00818     SPSR_abt          = 0xe219, // 11  100  0100  0011  001
00819     SPSR_und          = 0xe21a, // 11  100  0100  0011  010
00820     SPSR_fiq          = 0xe21b, // 11  100  0100  0011  011
00821     FPCR              = 0xda20, // 11  011  0100  0100  000
00822     FPSR              = 0xda21, // 11  011  0100  0100  001
00823     DSPSR_EL0         = 0xda28, // 11  011  0100  0101  000
00824     DLR_EL0           = 0xda29, // 11  011  0100  0101  001
00825     IFSR32_EL2        = 0xe281, // 11  100  0101  0000  001
00826     AFSR0_EL1         = 0xc288, // 11  000  0101  0001  000
00827     AFSR0_EL2         = 0xe288, // 11  100  0101  0001  000
00828     AFSR0_EL3         = 0xf288, // 11  110  0101  0001  000
00829     AFSR1_EL1         = 0xc289, // 11  000  0101  0001  001
00830     AFSR1_EL2         = 0xe289, // 11  100  0101  0001  001
00831     AFSR1_EL3         = 0xf289, // 11  110  0101  0001  001
00832     ESR_EL1           = 0xc290, // 11  000  0101  0010  000
00833     ESR_EL2           = 0xe290, // 11  100  0101  0010  000
00834     ESR_EL3           = 0xf290, // 11  110  0101  0010  000
00835     FPEXC32_EL2       = 0xe298, // 11  100  0101  0011  000
00836     FAR_EL1           = 0xc300, // 11  000  0110  0000  000
00837     FAR_EL2           = 0xe300, // 11  100  0110  0000  000
00838     FAR_EL3           = 0xf300, // 11  110  0110  0000  000
00839     HPFAR_EL2         = 0xe304, // 11  100  0110  0000  100
00840     PAR_EL1           = 0xc3a0, // 11  000  0111  0100  000
00841     PMCR_EL0          = 0xdce0, // 11  011  1001  1100  000
00842     PMCNTENSET_EL0    = 0xdce1, // 11  011  1001  1100  001
00843     PMCNTENCLR_EL0    = 0xdce2, // 11  011  1001  1100  010
00844     PMOVSCLR_EL0      = 0xdce3, // 11  011  1001  1100  011
00845     PMSELR_EL0        = 0xdce5, // 11  011  1001  1100  101
00846     PMCCNTR_EL0       = 0xdce8, // 11  011  1001  1101  000
00847     PMXEVTYPER_EL0    = 0xdce9, // 11  011  1001  1101  001
00848     PMXEVCNTR_EL0     = 0xdcea, // 11  011  1001  1101  010
00849     PMUSERENR_EL0     = 0xdcf0, // 11  011  1001  1110  000
00850     PMINTENSET_EL1    = 0xc4f1, // 11  000  1001  1110  001
00851     PMINTENCLR_EL1    = 0xc4f2, // 11  000  1001  1110  010
00852     PMOVSSET_EL0      = 0xdcf3, // 11  011  1001  1110  011
00853     MAIR_EL1          = 0xc510, // 11  000  1010  0010  000
00854     MAIR_EL2          = 0xe510, // 11  100  1010  0010  000
00855     MAIR_EL3          = 0xf510, // 11  110  1010  0010  000
00856     AMAIR_EL1         = 0xc518, // 11  000  1010  0011  000
00857     AMAIR_EL2         = 0xe518, // 11  100  1010  0011  000
00858     AMAIR_EL3         = 0xf518, // 11  110  1010  0011  000
00859     VBAR_EL1          = 0xc600, // 11  000  1100  0000  000
00860     VBAR_EL2          = 0xe600, // 11  100  1100  0000  000
00861     VBAR_EL3          = 0xf600, // 11  110  1100  0000  000
00862     RMR_EL1           = 0xc602, // 11  000  1100  0000  010
00863     RMR_EL2           = 0xe602, // 11  100  1100  0000  010
00864     RMR_EL3           = 0xf602, // 11  110  1100  0000  010
00865     CONTEXTIDR_EL1    = 0xc681, // 11  000  1101  0000  001
00866     TPIDR_EL0         = 0xde82, // 11  011  1101  0000  010
00867     TPIDR_EL2         = 0xe682, // 11  100  1101  0000  010
00868     TPIDR_EL3         = 0xf682, // 11  110  1101  0000  010
00869     TPIDRRO_EL0       = 0xde83, // 11  011  1101  0000  011
00870     TPIDR_EL1         = 0xc684, // 11  000  1101  0000  100
00871     CNTFRQ_EL0        = 0xdf00, // 11  011  1110  0000  000
00872     CNTVOFF_EL2       = 0xe703, // 11  100  1110  0000  011
00873     CNTKCTL_EL1       = 0xc708, // 11  000  1110  0001  000
00874     CNTHCTL_EL2       = 0xe708, // 11  100  1110  0001  000
00875     CNTP_TVAL_EL0     = 0xdf10, // 11  011  1110  0010  000
00876     CNTHP_TVAL_EL2    = 0xe710, // 11  100  1110  0010  000
00877     CNTPS_TVAL_EL1    = 0xff10, // 11  111  1110  0010  000
00878     CNTP_CTL_EL0      = 0xdf11, // 11  011  1110  0010  001
00879     CNTHP_CTL_EL2     = 0xe711, // 11  100  1110  0010  001
00880     CNTPS_CTL_EL1     = 0xff11, // 11  111  1110  0010  001
00881     CNTP_CVAL_EL0     = 0xdf12, // 11  011  1110  0010  010
00882     CNTHP_CVAL_EL2    = 0xe712, // 11  100  1110  0010  010
00883     CNTPS_CVAL_EL1    = 0xff12, // 11  111  1110  0010  010
00884     CNTV_TVAL_EL0     = 0xdf18, // 11  011  1110  0011  000
00885     CNTV_CTL_EL0      = 0xdf19, // 11  011  1110  0011  001
00886     CNTV_CVAL_EL0     = 0xdf1a, // 11  011  1110  0011  010
00887     PMEVCNTR0_EL0     = 0xdf40, // 11  011  1110  1000  000
00888     PMEVCNTR1_EL0     = 0xdf41, // 11  011  1110  1000  001
00889     PMEVCNTR2_EL0     = 0xdf42, // 11  011  1110  1000  010
00890     PMEVCNTR3_EL0     = 0xdf43, // 11  011  1110  1000  011
00891     PMEVCNTR4_EL0     = 0xdf44, // 11  011  1110  1000  100
00892     PMEVCNTR5_EL0     = 0xdf45, // 11  011  1110  1000  101
00893     PMEVCNTR6_EL0     = 0xdf46, // 11  011  1110  1000  110
00894     PMEVCNTR7_EL0     = 0xdf47, // 11  011  1110  1000  111
00895     PMEVCNTR8_EL0     = 0xdf48, // 11  011  1110  1001  000
00896     PMEVCNTR9_EL0     = 0xdf49, // 11  011  1110  1001  001
00897     PMEVCNTR10_EL0    = 0xdf4a, // 11  011  1110  1001  010
00898     PMEVCNTR11_EL0    = 0xdf4b, // 11  011  1110  1001  011
00899     PMEVCNTR12_EL0    = 0xdf4c, // 11  011  1110  1001  100
00900     PMEVCNTR13_EL0    = 0xdf4d, // 11  011  1110  1001  101
00901     PMEVCNTR14_EL0    = 0xdf4e, // 11  011  1110  1001  110
00902     PMEVCNTR15_EL0    = 0xdf4f, // 11  011  1110  1001  111
00903     PMEVCNTR16_EL0    = 0xdf50, // 11  011  1110  1010  000
00904     PMEVCNTR17_EL0    = 0xdf51, // 11  011  1110  1010  001
00905     PMEVCNTR18_EL0    = 0xdf52, // 11  011  1110  1010  010
00906     PMEVCNTR19_EL0    = 0xdf53, // 11  011  1110  1010  011
00907     PMEVCNTR20_EL0    = 0xdf54, // 11  011  1110  1010  100
00908     PMEVCNTR21_EL0    = 0xdf55, // 11  011  1110  1010  101
00909     PMEVCNTR22_EL0    = 0xdf56, // 11  011  1110  1010  110
00910     PMEVCNTR23_EL0    = 0xdf57, // 11  011  1110  1010  111
00911     PMEVCNTR24_EL0    = 0xdf58, // 11  011  1110  1011  000
00912     PMEVCNTR25_EL0    = 0xdf59, // 11  011  1110  1011  001
00913     PMEVCNTR26_EL0    = 0xdf5a, // 11  011  1110  1011  010
00914     PMEVCNTR27_EL0    = 0xdf5b, // 11  011  1110  1011  011
00915     PMEVCNTR28_EL0    = 0xdf5c, // 11  011  1110  1011  100
00916     PMEVCNTR29_EL0    = 0xdf5d, // 11  011  1110  1011  101
00917     PMEVCNTR30_EL0    = 0xdf5e, // 11  011  1110  1011  110
00918     PMCCFILTR_EL0     = 0xdf7f, // 11  011  1110  1111  111
00919     PMEVTYPER0_EL0    = 0xdf60, // 11  011  1110  1100  000
00920     PMEVTYPER1_EL0    = 0xdf61, // 11  011  1110  1100  001
00921     PMEVTYPER2_EL0    = 0xdf62, // 11  011  1110  1100  010
00922     PMEVTYPER3_EL0    = 0xdf63, // 11  011  1110  1100  011
00923     PMEVTYPER4_EL0    = 0xdf64, // 11  011  1110  1100  100
00924     PMEVTYPER5_EL0    = 0xdf65, // 11  011  1110  1100  101
00925     PMEVTYPER6_EL0    = 0xdf66, // 11  011  1110  1100  110
00926     PMEVTYPER7_EL0    = 0xdf67, // 11  011  1110  1100  111
00927     PMEVTYPER8_EL0    = 0xdf68, // 11  011  1110  1101  000
00928     PMEVTYPER9_EL0    = 0xdf69, // 11  011  1110  1101  001
00929     PMEVTYPER10_EL0   = 0xdf6a, // 11  011  1110  1101  010
00930     PMEVTYPER11_EL0   = 0xdf6b, // 11  011  1110  1101  011
00931     PMEVTYPER12_EL0   = 0xdf6c, // 11  011  1110  1101  100
00932     PMEVTYPER13_EL0   = 0xdf6d, // 11  011  1110  1101  101
00933     PMEVTYPER14_EL0   = 0xdf6e, // 11  011  1110  1101  110
00934     PMEVTYPER15_EL0   = 0xdf6f, // 11  011  1110  1101  111
00935     PMEVTYPER16_EL0   = 0xdf70, // 11  011  1110  1110  000
00936     PMEVTYPER17_EL0   = 0xdf71, // 11  011  1110  1110  001
00937     PMEVTYPER18_EL0   = 0xdf72, // 11  011  1110  1110  010
00938     PMEVTYPER19_EL0   = 0xdf73, // 11  011  1110  1110  011
00939     PMEVTYPER20_EL0   = 0xdf74, // 11  011  1110  1110  100
00940     PMEVTYPER21_EL0   = 0xdf75, // 11  011  1110  1110  101
00941     PMEVTYPER22_EL0   = 0xdf76, // 11  011  1110  1110  110
00942     PMEVTYPER23_EL0   = 0xdf77, // 11  011  1110  1110  111
00943     PMEVTYPER24_EL0   = 0xdf78, // 11  011  1110  1111  000
00944     PMEVTYPER25_EL0   = 0xdf79, // 11  011  1110  1111  001
00945     PMEVTYPER26_EL0   = 0xdf7a, // 11  011  1110  1111  010
00946     PMEVTYPER27_EL0   = 0xdf7b, // 11  011  1110  1111  011
00947     PMEVTYPER28_EL0   = 0xdf7c, // 11  011  1110  1111  100
00948     PMEVTYPER29_EL0   = 0xdf7d, // 11  011  1110  1111  101
00949     PMEVTYPER30_EL0   = 0xdf7e, // 11  011  1110  1111  110
00950 
00951     // Trace registers
00952     TRCPRGCTLR        = 0x8808, // 10  001  0000  0001  000
00953     TRCPROCSELR       = 0x8810, // 10  001  0000  0010  000
00954     TRCCONFIGR        = 0x8820, // 10  001  0000  0100  000
00955     TRCAUXCTLR        = 0x8830, // 10  001  0000  0110  000
00956     TRCEVENTCTL0R     = 0x8840, // 10  001  0000  1000  000
00957     TRCEVENTCTL1R     = 0x8848, // 10  001  0000  1001  000
00958     TRCSTALLCTLR      = 0x8858, // 10  001  0000  1011  000
00959     TRCTSCTLR         = 0x8860, // 10  001  0000  1100  000
00960     TRCSYNCPR         = 0x8868, // 10  001  0000  1101  000
00961     TRCCCCTLR         = 0x8870, // 10  001  0000  1110  000
00962     TRCBBCTLR         = 0x8878, // 10  001  0000  1111  000
00963     TRCTRACEIDR       = 0x8801, // 10  001  0000  0000  001
00964     TRCQCTLR          = 0x8809, // 10  001  0000  0001  001
00965     TRCVICTLR         = 0x8802, // 10  001  0000  0000  010
00966     TRCVIIECTLR       = 0x880a, // 10  001  0000  0001  010
00967     TRCVISSCTLR       = 0x8812, // 10  001  0000  0010  010
00968     TRCVIPCSSCTLR     = 0x881a, // 10  001  0000  0011  010
00969     TRCVDCTLR         = 0x8842, // 10  001  0000  1000  010
00970     TRCVDSACCTLR      = 0x884a, // 10  001  0000  1001  010
00971     TRCVDARCCTLR      = 0x8852, // 10  001  0000  1010  010
00972     TRCSEQEVR0        = 0x8804, // 10  001  0000  0000  100
00973     TRCSEQEVR1        = 0x880c, // 10  001  0000  0001  100
00974     TRCSEQEVR2        = 0x8814, // 10  001  0000  0010  100
00975     TRCSEQRSTEVR      = 0x8834, // 10  001  0000  0110  100
00976     TRCSEQSTR         = 0x883c, // 10  001  0000  0111  100
00977     TRCEXTINSELR      = 0x8844, // 10  001  0000  1000  100
00978     TRCCNTRLDVR0      = 0x8805, // 10  001  0000  0000  101
00979     TRCCNTRLDVR1      = 0x880d, // 10  001  0000  0001  101
00980     TRCCNTRLDVR2      = 0x8815, // 10  001  0000  0010  101
00981     TRCCNTRLDVR3      = 0x881d, // 10  001  0000  0011  101
00982     TRCCNTCTLR0       = 0x8825, // 10  001  0000  0100  101
00983     TRCCNTCTLR1       = 0x882d, // 10  001  0000  0101  101
00984     TRCCNTCTLR2       = 0x8835, // 10  001  0000  0110  101
00985     TRCCNTCTLR3       = 0x883d, // 10  001  0000  0111  101
00986     TRCCNTVR0         = 0x8845, // 10  001  0000  1000  101
00987     TRCCNTVR1         = 0x884d, // 10  001  0000  1001  101
00988     TRCCNTVR2         = 0x8855, // 10  001  0000  1010  101
00989     TRCCNTVR3         = 0x885d, // 10  001  0000  1011  101
00990     TRCIMSPEC0        = 0x8807, // 10  001  0000  0000  111
00991     TRCIMSPEC1        = 0x880f, // 10  001  0000  0001  111
00992     TRCIMSPEC2        = 0x8817, // 10  001  0000  0010  111
00993     TRCIMSPEC3        = 0x881f, // 10  001  0000  0011  111
00994     TRCIMSPEC4        = 0x8827, // 10  001  0000  0100  111
00995     TRCIMSPEC5        = 0x882f, // 10  001  0000  0101  111
00996     TRCIMSPEC6        = 0x8837, // 10  001  0000  0110  111
00997     TRCIMSPEC7        = 0x883f, // 10  001  0000  0111  111
00998     TRCRSCTLR2        = 0x8890, // 10  001  0001  0010  000
00999     TRCRSCTLR3        = 0x8898, // 10  001  0001  0011  000
01000     TRCRSCTLR4        = 0x88a0, // 10  001  0001  0100  000
01001     TRCRSCTLR5        = 0x88a8, // 10  001  0001  0101  000
01002     TRCRSCTLR6        = 0x88b0, // 10  001  0001  0110  000
01003     TRCRSCTLR7        = 0x88b8, // 10  001  0001  0111  000
01004     TRCRSCTLR8        = 0x88c0, // 10  001  0001  1000  000
01005     TRCRSCTLR9        = 0x88c8, // 10  001  0001  1001  000
01006     TRCRSCTLR10       = 0x88d0, // 10  001  0001  1010  000
01007     TRCRSCTLR11       = 0x88d8, // 10  001  0001  1011  000
01008     TRCRSCTLR12       = 0x88e0, // 10  001  0001  1100  000
01009     TRCRSCTLR13       = 0x88e8, // 10  001  0001  1101  000
01010     TRCRSCTLR14       = 0x88f0, // 10  001  0001  1110  000
01011     TRCRSCTLR15       = 0x88f8, // 10  001  0001  1111  000
01012     TRCRSCTLR16       = 0x8881, // 10  001  0001  0000  001
01013     TRCRSCTLR17       = 0x8889, // 10  001  0001  0001  001
01014     TRCRSCTLR18       = 0x8891, // 10  001  0001  0010  001
01015     TRCRSCTLR19       = 0x8899, // 10  001  0001  0011  001
01016     TRCRSCTLR20       = 0x88a1, // 10  001  0001  0100  001
01017     TRCRSCTLR21       = 0x88a9, // 10  001  0001  0101  001
01018     TRCRSCTLR22       = 0x88b1, // 10  001  0001  0110  001
01019     TRCRSCTLR23       = 0x88b9, // 10  001  0001  0111  001
01020     TRCRSCTLR24       = 0x88c1, // 10  001  0001  1000  001
01021     TRCRSCTLR25       = 0x88c9, // 10  001  0001  1001  001
01022     TRCRSCTLR26       = 0x88d1, // 10  001  0001  1010  001
01023     TRCRSCTLR27       = 0x88d9, // 10  001  0001  1011  001
01024     TRCRSCTLR28       = 0x88e1, // 10  001  0001  1100  001
01025     TRCRSCTLR29       = 0x88e9, // 10  001  0001  1101  001
01026     TRCRSCTLR30       = 0x88f1, // 10  001  0001  1110  001
01027     TRCRSCTLR31       = 0x88f9, // 10  001  0001  1111  001
01028     TRCSSCCR0         = 0x8882, // 10  001  0001  0000  010
01029     TRCSSCCR1         = 0x888a, // 10  001  0001  0001  010
01030     TRCSSCCR2         = 0x8892, // 10  001  0001  0010  010
01031     TRCSSCCR3         = 0x889a, // 10  001  0001  0011  010
01032     TRCSSCCR4         = 0x88a2, // 10  001  0001  0100  010
01033     TRCSSCCR5         = 0x88aa, // 10  001  0001  0101  010
01034     TRCSSCCR6         = 0x88b2, // 10  001  0001  0110  010
01035     TRCSSCCR7         = 0x88ba, // 10  001  0001  0111  010
01036     TRCSSCSR0         = 0x88c2, // 10  001  0001  1000  010
01037     TRCSSCSR1         = 0x88ca, // 10  001  0001  1001  010
01038     TRCSSCSR2         = 0x88d2, // 10  001  0001  1010  010
01039     TRCSSCSR3         = 0x88da, // 10  001  0001  1011  010
01040     TRCSSCSR4         = 0x88e2, // 10  001  0001  1100  010
01041     TRCSSCSR5         = 0x88ea, // 10  001  0001  1101  010
01042     TRCSSCSR6         = 0x88f2, // 10  001  0001  1110  010
01043     TRCSSCSR7         = 0x88fa, // 10  001  0001  1111  010
01044     TRCSSPCICR0       = 0x8883, // 10  001  0001  0000  011
01045     TRCSSPCICR1       = 0x888b, // 10  001  0001  0001  011
01046     TRCSSPCICR2       = 0x8893, // 10  001  0001  0010  011
01047     TRCSSPCICR3       = 0x889b, // 10  001  0001  0011  011
01048     TRCSSPCICR4       = 0x88a3, // 10  001  0001  0100  011
01049     TRCSSPCICR5       = 0x88ab, // 10  001  0001  0101  011
01050     TRCSSPCICR6       = 0x88b3, // 10  001  0001  0110  011
01051     TRCSSPCICR7       = 0x88bb, // 10  001  0001  0111  011
01052     TRCPDCR           = 0x88a4, // 10  001  0001  0100  100
01053     TRCACVR0          = 0x8900, // 10  001  0010  0000  000
01054     TRCACVR1          = 0x8910, // 10  001  0010  0010  000
01055     TRCACVR2          = 0x8920, // 10  001  0010  0100  000
01056     TRCACVR3          = 0x8930, // 10  001  0010  0110  000
01057     TRCACVR4          = 0x8940, // 10  001  0010  1000  000
01058     TRCACVR5          = 0x8950, // 10  001  0010  1010  000
01059     TRCACVR6          = 0x8960, // 10  001  0010  1100  000
01060     TRCACVR7          = 0x8970, // 10  001  0010  1110  000
01061     TRCACVR8          = 0x8901, // 10  001  0010  0000  001
01062     TRCACVR9          = 0x8911, // 10  001  0010  0010  001
01063     TRCACVR10         = 0x8921, // 10  001  0010  0100  001
01064     TRCACVR11         = 0x8931, // 10  001  0010  0110  001
01065     TRCACVR12         = 0x8941, // 10  001  0010  1000  001
01066     TRCACVR13         = 0x8951, // 10  001  0010  1010  001
01067     TRCACVR14         = 0x8961, // 10  001  0010  1100  001
01068     TRCACVR15         = 0x8971, // 10  001  0010  1110  001
01069     TRCACATR0         = 0x8902, // 10  001  0010  0000  010
01070     TRCACATR1         = 0x8912, // 10  001  0010  0010  010
01071     TRCACATR2         = 0x8922, // 10  001  0010  0100  010
01072     TRCACATR3         = 0x8932, // 10  001  0010  0110  010
01073     TRCACATR4         = 0x8942, // 10  001  0010  1000  010
01074     TRCACATR5         = 0x8952, // 10  001  0010  1010  010
01075     TRCACATR6         = 0x8962, // 10  001  0010  1100  010
01076     TRCACATR7         = 0x8972, // 10  001  0010  1110  010
01077     TRCACATR8         = 0x8903, // 10  001  0010  0000  011
01078     TRCACATR9         = 0x8913, // 10  001  0010  0010  011
01079     TRCACATR10        = 0x8923, // 10  001  0010  0100  011
01080     TRCACATR11        = 0x8933, // 10  001  0010  0110  011
01081     TRCACATR12        = 0x8943, // 10  001  0010  1000  011
01082     TRCACATR13        = 0x8953, // 10  001  0010  1010  011
01083     TRCACATR14        = 0x8963, // 10  001  0010  1100  011
01084     TRCACATR15        = 0x8973, // 10  001  0010  1110  011
01085     TRCDVCVR0         = 0x8904, // 10  001  0010  0000  100
01086     TRCDVCVR1         = 0x8924, // 10  001  0010  0100  100
01087     TRCDVCVR2         = 0x8944, // 10  001  0010  1000  100
01088     TRCDVCVR3         = 0x8964, // 10  001  0010  1100  100
01089     TRCDVCVR4         = 0x8905, // 10  001  0010  0000  101
01090     TRCDVCVR5         = 0x8925, // 10  001  0010  0100  101
01091     TRCDVCVR6         = 0x8945, // 10  001  0010  1000  101
01092     TRCDVCVR7         = 0x8965, // 10  001  0010  1100  101
01093     TRCDVCMR0         = 0x8906, // 10  001  0010  0000  110
01094     TRCDVCMR1         = 0x8926, // 10  001  0010  0100  110
01095     TRCDVCMR2         = 0x8946, // 10  001  0010  1000  110
01096     TRCDVCMR3         = 0x8966, // 10  001  0010  1100  110
01097     TRCDVCMR4         = 0x8907, // 10  001  0010  0000  111
01098     TRCDVCMR5         = 0x8927, // 10  001  0010  0100  111
01099     TRCDVCMR6         = 0x8947, // 10  001  0010  1000  111
01100     TRCDVCMR7         = 0x8967, // 10  001  0010  1100  111
01101     TRCCIDCVR0        = 0x8980, // 10  001  0011  0000  000
01102     TRCCIDCVR1        = 0x8990, // 10  001  0011  0010  000
01103     TRCCIDCVR2        = 0x89a0, // 10  001  0011  0100  000
01104     TRCCIDCVR3        = 0x89b0, // 10  001  0011  0110  000
01105     TRCCIDCVR4        = 0x89c0, // 10  001  0011  1000  000
01106     TRCCIDCVR5        = 0x89d0, // 10  001  0011  1010  000
01107     TRCCIDCVR6        = 0x89e0, // 10  001  0011  1100  000
01108     TRCCIDCVR7        = 0x89f0, // 10  001  0011  1110  000
01109     TRCVMIDCVR0       = 0x8981, // 10  001  0011  0000  001
01110     TRCVMIDCVR1       = 0x8991, // 10  001  0011  0010  001
01111     TRCVMIDCVR2       = 0x89a1, // 10  001  0011  0100  001
01112     TRCVMIDCVR3       = 0x89b1, // 10  001  0011  0110  001
01113     TRCVMIDCVR4       = 0x89c1, // 10  001  0011  1000  001
01114     TRCVMIDCVR5       = 0x89d1, // 10  001  0011  1010  001
01115     TRCVMIDCVR6       = 0x89e1, // 10  001  0011  1100  001
01116     TRCVMIDCVR7       = 0x89f1, // 10  001  0011  1110  001
01117     TRCCIDCCTLR0      = 0x8982, // 10  001  0011  0000  010
01118     TRCCIDCCTLR1      = 0x898a, // 10  001  0011  0001  010
01119     TRCVMIDCCTLR0     = 0x8992, // 10  001  0011  0010  010
01120     TRCVMIDCCTLR1     = 0x899a, // 10  001  0011  0011  010
01121     TRCITCTRL         = 0x8b84, // 10  001  0111  0000  100
01122     TRCCLAIMSET       = 0x8bc6, // 10  001  0111  1000  110
01123     TRCCLAIMCLR       = 0x8bce, // 10  001  0111  1001  110
01124 
01125     // GICv3 registers
01126     ICC_BPR1_EL1      = 0xc663, // 11  000  1100  1100  011
01127     ICC_BPR0_EL1      = 0xc643, // 11  000  1100  1000  011
01128     ICC_PMR_EL1       = 0xc230, // 11  000  0100  0110  000
01129     ICC_CTLR_EL1      = 0xc664, // 11  000  1100  1100  100
01130     ICC_CTLR_EL3      = 0xf664, // 11  110  1100  1100  100
01131     ICC_SRE_EL1       = 0xc665, // 11  000  1100  1100  101
01132     ICC_SRE_EL2       = 0xe64d, // 11  100  1100  1001  101
01133     ICC_SRE_EL3       = 0xf665, // 11  110  1100  1100  101
01134     ICC_IGRPEN0_EL1   = 0xc666, // 11  000  1100  1100  110
01135     ICC_IGRPEN1_EL1   = 0xc667, // 11  000  1100  1100  111
01136     ICC_IGRPEN1_EL3   = 0xf667, // 11  110  1100  1100  111
01137     ICC_SEIEN_EL1     = 0xc668, // 11  000  1100  1101  000
01138     ICC_AP0R0_EL1     = 0xc644, // 11  000  1100  1000  100
01139     ICC_AP0R1_EL1     = 0xc645, // 11  000  1100  1000  101
01140     ICC_AP0R2_EL1     = 0xc646, // 11  000  1100  1000  110
01141     ICC_AP0R3_EL1     = 0xc647, // 11  000  1100  1000  111
01142     ICC_AP1R0_EL1     = 0xc648, // 11  000  1100  1001  000
01143     ICC_AP1R1_EL1     = 0xc649, // 11  000  1100  1001  001
01144     ICC_AP1R2_EL1     = 0xc64a, // 11  000  1100  1001  010
01145     ICC_AP1R3_EL1     = 0xc64b, // 11  000  1100  1001  011
01146     ICH_AP0R0_EL2     = 0xe640, // 11  100  1100  1000  000
01147     ICH_AP0R1_EL2     = 0xe641, // 11  100  1100  1000  001
01148     ICH_AP0R2_EL2     = 0xe642, // 11  100  1100  1000  010
01149     ICH_AP0R3_EL2     = 0xe643, // 11  100  1100  1000  011
01150     ICH_AP1R0_EL2     = 0xe648, // 11  100  1100  1001  000
01151     ICH_AP1R1_EL2     = 0xe649, // 11  100  1100  1001  001
01152     ICH_AP1R2_EL2     = 0xe64a, // 11  100  1100  1001  010
01153     ICH_AP1R3_EL2     = 0xe64b, // 11  100  1100  1001  011
01154     ICH_HCR_EL2       = 0xe658, // 11  100  1100  1011  000
01155     ICH_MISR_EL2      = 0xe65a, // 11  100  1100  1011  010
01156     ICH_VMCR_EL2      = 0xe65f, // 11  100  1100  1011  111
01157     ICH_VSEIR_EL2     = 0xe64c, // 11  100  1100  1001  100
01158     ICH_LR0_EL2       = 0xe660, // 11  100  1100  1100  000
01159     ICH_LR1_EL2       = 0xe661, // 11  100  1100  1100  001
01160     ICH_LR2_EL2       = 0xe662, // 11  100  1100  1100  010
01161     ICH_LR3_EL2       = 0xe663, // 11  100  1100  1100  011
01162     ICH_LR4_EL2       = 0xe664, // 11  100  1100  1100  100
01163     ICH_LR5_EL2       = 0xe665, // 11  100  1100  1100  101
01164     ICH_LR6_EL2       = 0xe666, // 11  100  1100  1100  110
01165     ICH_LR7_EL2       = 0xe667, // 11  100  1100  1100  111
01166     ICH_LR8_EL2       = 0xe668, // 11  100  1100  1101  000
01167     ICH_LR9_EL2       = 0xe669, // 11  100  1100  1101  001
01168     ICH_LR10_EL2      = 0xe66a, // 11  100  1100  1101  010
01169     ICH_LR11_EL2      = 0xe66b, // 11  100  1100  1101  011
01170     ICH_LR12_EL2      = 0xe66c, // 11  100  1100  1101  100
01171     ICH_LR13_EL2      = 0xe66d, // 11  100  1100  1101  101
01172     ICH_LR14_EL2      = 0xe66e, // 11  100  1100  1101  110
01173     ICH_LR15_EL2      = 0xe66f, // 11  100  1100  1101  111
01174 
01175     // v8.1a "Privileged Access Never" extension-specific system registers
01176     PAN               = 0xc213, // 11  000  0100  0010  011
01177 
01178     // v8.1a "Limited Ordering Regions" extension-specific system registers
01179     LORSA_EL1         = 0xc520, // 11  000  1010  0100  000
01180     LOREA_EL1         = 0xc521, // 11  000  1010  0100  001
01181     LORN_EL1          = 0xc522, // 11  000  1010  0100  010
01182     LORC_EL1          = 0xc523, // 11  000  1010  0100  011
01183     LORID_EL1         = 0xc527, // 11  000  1010  0100  111
01184 
01185     // v8.1a "Virtualization host extensions" system registers
01186     TTBR1_EL2         = 0xe101, // 11  100  0010  0000  001
01187     CONTEXTIDR_EL2    = 0xe681, // 11  100  1101  0000  001
01188     CNTHV_TVAL_EL2    = 0xe718, // 11  100  1110  0011  000
01189     CNTHV_CVAL_EL2    = 0xe71a, // 11  100  1110  0011  010
01190     CNTHV_CTL_EL2     = 0xe719, // 11  100  1110  0011  001
01191     SCTLR_EL12        = 0xe880, // 11  101  0001  0000  000
01192     CPACR_EL12        = 0xe882, // 11  101  0001  0000  010
01193     TTBR0_EL12        = 0xe900, // 11  101  0010  0000  000
01194     TTBR1_EL12        = 0xe901, // 11  101  0010  0000  001
01195     TCR_EL12          = 0xe902, // 11  101  0010  0000  010
01196     AFSR0_EL12        = 0xea88, // 11  101  0101  0001  000
01197     AFSR1_EL12        = 0xea89, // 11  101  0101  0001  001
01198     ESR_EL12          = 0xea90, // 11  101  0101  0010  000
01199     FAR_EL12          = 0xeb00, // 11  101  0110  0000  000
01200     MAIR_EL12         = 0xed10, // 11  101  1010  0010  000
01201     AMAIR_EL12        = 0xed18, // 11  101  1010  0011  000
01202     VBAR_EL12         = 0xee00, // 11  101  1100  0000  000
01203     CONTEXTIDR_EL12   = 0xee81, // 11  101  1101  0000  001
01204     CNTKCTL_EL12      = 0xef08, // 11  101  1110  0001  000
01205     CNTP_TVAL_EL02    = 0xef10, // 11  101  1110  0010  000
01206     CNTP_CTL_EL02     = 0xef11, // 11  101  1110  0010  001
01207     CNTP_CVAL_EL02    = 0xef12, // 11  101  1110  0010  010
01208     CNTV_TVAL_EL02    = 0xef18, // 11  101  1110  0011  000
01209     CNTV_CTL_EL02     = 0xef19, // 11  101  1110  0011  001
01210     CNTV_CVAL_EL02    = 0xef1a, // 11  101  1110  0011  010
01211     SPSR_EL12         = 0xea00, // 11  101  0100  0000  000
01212     ELR_EL12          = 0xea01, // 11  101  0100  0000  001
01213 
01214     // v8.2a registers
01215     UAO               = 0xc214, // 11  000  0100  0010  100
01216 
01217     // v8.2a "Statistical Profiling extension" registers
01218     PMBLIMITR_EL1     = 0xc4d0, // 11  000  1001  1010  000
01219     PMBPTR_EL1        = 0xc4d1, // 11  000  1001  1010  001
01220     PMBSR_EL1         = 0xc4d3, // 11  000  1001  1010  011
01221     PMBIDR_EL1        = 0xc4d7, // 11  000  1001  1010  111
01222     PMSCR_EL2         = 0xe4c8, // 11  100  1001  1001  000
01223     PMSCR_EL12        = 0xecc8, // 11  101  1001  1001  000
01224     PMSCR_EL1         = 0xc4c8, // 11  000  1001  1001  000
01225     PMSICR_EL1        = 0xc4ca, // 11  000  1001  1001  010
01226     PMSIRR_EL1        = 0xc4cb, // 11  000  1001  1001  011
01227     PMSFCR_EL1        = 0xc4cc, // 11  000  1001  1001  100
01228     PMSEVFR_EL1       = 0xc4cd, // 11  000  1001  1001  101
01229     PMSLATFR_EL1      = 0xc4ce, // 11  000  1001  1001  110
01230     PMSIDR_EL1        = 0xc4cf, // 11  000  1001  1001  111
01231 
01232     // Cyclone specific system registers
01233     CPM_IOACC_CTL_EL3 = 0xff90,
01234   };
01235 
01236   // Note that these do not inherit from AArch64NamedImmMapper. This class is
01237   // sufficiently different in its behaviour that I don't believe it's worth
01238   // burdening the common AArch64NamedImmMapper with abstractions only needed in
01239   // this one case.
01240   struct SysRegMapper {
01241     static const AArch64NamedImmMapper::Mapping SysRegMappings[];
01242 
01243     const AArch64NamedImmMapper::Mapping *InstMappings;
01244     size_t NumInstMappings;
01245 
01246     SysRegMapper() { }
01247     uint32_t fromString(StringRef Name, const FeatureBitset& FeatureBits,
01248                         bool &Valid) const;
01249     std::string toString(uint32_t Bits, const FeatureBitset& FeatureBits) const;
01250   };
01251 
01252   struct MSRMapper : SysRegMapper {
01253     static const AArch64NamedImmMapper::Mapping MSRMappings[];
01254     MSRMapper();
01255   };
01256 
01257   struct MRSMapper : SysRegMapper {
01258     static const AArch64NamedImmMapper::Mapping MRSMappings[];
01259     MRSMapper();
01260   };
01261 
01262   uint32_t ParseGenericRegister(StringRef Name, bool &Valid);
01263 }
01264 
01265 namespace AArch64TLBI {
01266   enum TLBIValues {
01267     Invalid = -1,          // Op0 Op1  CRn   CRm   Op2
01268     IPAS2E1IS    = 0x6401, // 01  100  1000  0000  001
01269     IPAS2LE1IS   = 0x6405, // 01  100  1000  0000  101
01270     VMALLE1IS    = 0x4418, // 01  000  1000  0011  000
01271     ALLE2IS      = 0x6418, // 01  100  1000  0011  000
01272     ALLE3IS      = 0x7418, // 01  110  1000  0011  000
01273     VAE1IS       = 0x4419, // 01  000  1000  0011  001
01274     VAE2IS       = 0x6419, // 01  100  1000  0011  001
01275     VAE3IS       = 0x7419, // 01  110  1000  0011  001
01276     ASIDE1IS     = 0x441a, // 01  000  1000  0011  010
01277     VAAE1IS      = 0x441b, // 01  000  1000  0011  011
01278     ALLE1IS      = 0x641c, // 01  100  1000  0011  100
01279     VALE1IS      = 0x441d, // 01  000  1000  0011  101
01280     VALE2IS      = 0x641d, // 01  100  1000  0011  101
01281     VALE3IS      = 0x741d, // 01  110  1000  0011  101
01282     VMALLS12E1IS = 0x641e, // 01  100  1000  0011  110
01283     VAALE1IS     = 0x441f, // 01  000  1000  0011  111
01284     IPAS2E1      = 0x6421, // 01  100  1000  0100  001
01285     IPAS2LE1     = 0x6425, // 01  100  1000  0100  101
01286     VMALLE1      = 0x4438, // 01  000  1000  0111  000
01287     ALLE2        = 0x6438, // 01  100  1000  0111  000
01288     ALLE3        = 0x7438, // 01  110  1000  0111  000
01289     VAE1         = 0x4439, // 01  000  1000  0111  001
01290     VAE2         = 0x6439, // 01  100  1000  0111  001
01291     VAE3         = 0x7439, // 01  110  1000  0111  001
01292     ASIDE1       = 0x443a, // 01  000  1000  0111  010
01293     VAAE1        = 0x443b, // 01  000  1000  0111  011
01294     ALLE1        = 0x643c, // 01  100  1000  0111  100
01295     VALE1        = 0x443d, // 01  000  1000  0111  101
01296     VALE2        = 0x643d, // 01  100  1000  0111  101
01297     VALE3        = 0x743d, // 01  110  1000  0111  101
01298     VMALLS12E1   = 0x643e, // 01  100  1000  0111  110
01299     VAALE1       = 0x443f  // 01  000  1000  0111  111
01300   };
01301 
01302   struct TLBIMapper : AArch64NamedImmMapper {
01303     const static Mapping TLBIMappings[];
01304 
01305     TLBIMapper();
01306   };
01307 
01308   static inline bool NeedsRegister(TLBIValues Val) {
01309     switch (Val) {
01310     case VMALLE1IS:
01311     case ALLE2IS:
01312     case ALLE3IS:
01313     case ALLE1IS:
01314     case VMALLS12E1IS:
01315     case VMALLE1:
01316     case ALLE2:
01317     case ALLE3:
01318     case ALLE1:
01319     case VMALLS12E1:
01320       return false;
01321     default:
01322       return true;
01323     }
01324   }
01325 }
01326 
01327 namespace AArch64II {
01328   /// Target Operand Flag enum.
01329   enum TOF {
01330     //===------------------------------------------------------------------===//
01331     // AArch64 Specific MachineOperand flags.
01332 
01333     MO_NO_FLAG,
01334 
01335     MO_FRAGMENT = 0xf,
01336 
01337     /// MO_PAGE - A symbol operand with this flag represents the pc-relative
01338     /// offset of the 4K page containing the symbol.  This is used with the
01339     /// ADRP instruction.
01340     MO_PAGE = 1,
01341 
01342     /// MO_PAGEOFF - A symbol operand with this flag represents the offset of
01343     /// that symbol within a 4K page.  This offset is added to the page address
01344     /// to produce the complete address.
01345     MO_PAGEOFF = 2,
01346 
01347     /// MO_G3 - A symbol operand with this flag (granule 3) represents the high
01348     /// 16-bits of a 64-bit address, used in a MOVZ or MOVK instruction
01349     MO_G3 = 3,
01350 
01351     /// MO_G2 - A symbol operand with this flag (granule 2) represents the bits
01352     /// 32-47 of a 64-bit address, used in a MOVZ or MOVK instruction
01353     MO_G2 = 4,
01354 
01355     /// MO_G1 - A symbol operand with this flag (granule 1) represents the bits
01356     /// 16-31 of a 64-bit address, used in a MOVZ or MOVK instruction
01357     MO_G1 = 5,
01358 
01359     /// MO_G0 - A symbol operand with this flag (granule 0) represents the bits
01360     /// 0-15 of a 64-bit address, used in a MOVZ or MOVK instruction
01361     MO_G0 = 6,
01362 
01363     /// MO_HI12 - This flag indicates that a symbol operand represents the bits
01364     /// 13-24 of a 64-bit address, used in a arithmetic immediate-shifted-left-
01365     /// by-12-bits instruction.
01366     MO_HI12 = 7,
01367 
01368     /// MO_GOT - This flag indicates that a symbol operand represents the
01369     /// address of the GOT entry for the symbol, rather than the address of
01370     /// the symbol itself.
01371     MO_GOT = 0x10,
01372 
01373     /// MO_NC - Indicates whether the linker is expected to check the symbol
01374     /// reference for overflow. For example in an ADRP/ADD pair of relocations
01375     /// the ADRP usually does check, but not the ADD.
01376     MO_NC = 0x20,
01377 
01378     /// MO_TLS - Indicates that the operand being accessed is some kind of
01379     /// thread-local symbol. On Darwin, only one type of thread-local access
01380     /// exists (pre linker-relaxation), but on ELF the TLSModel used for the
01381     /// referee will affect interpretation.
01382     MO_TLS = 0x40,
01383 
01384     /// MO_CONSTPOOL - This flag indicates that a symbol operand represents
01385     /// the address of a constant pool entry for the symbol, rather than the
01386     /// address of the symbol itself.
01387     MO_CONSTPOOL = 0x80
01388   };
01389 } // end namespace AArch64II
01390 
01391 } // end namespace llvm
01392 
01393 #endif