LLVM 19.0.0git
AMDGPUTargetStreamer.cpp
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1//===-- AMDGPUTargetStreamer.cpp - Mips Target Streamer Methods -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file provides AMDGPU specific target streamer methods.
10//
11//===----------------------------------------------------------------------===//
12
15#include "AMDGPUPTNote.h"
16#include "AMDKernelCodeT.h"
21#include "llvm/MC/MCAssembler.h"
22#include "llvm/MC/MCContext.h"
33
34using namespace llvm;
35using namespace llvm::AMDGPU;
36
37//===----------------------------------------------------------------------===//
38// AMDGPUTargetStreamer
39//===----------------------------------------------------------------------===//
40
42 ForceGenericVersion("amdgpu-force-generic-version",
43 cl::desc("Force a specific generic_v<N> flag to be "
44 "added. For testing purposes only."),
46
48 msgpack::Document HSAMetadataDoc;
49 if (!HSAMetadataDoc.fromYAML(HSAMetadataString))
50 return false;
51 return EmitHSAMetadata(HSAMetadataDoc, false);
52}
53
56
57 // clang-format off
58 switch (ElfMach) {
59 case ELF::EF_AMDGPU_MACH_R600_R600: AK = GK_R600; break;
60 case ELF::EF_AMDGPU_MACH_R600_R630: AK = GK_R630; break;
70 case ELF::EF_AMDGPU_MACH_R600_SUMO: AK = GK_SUMO; break;
123 case ELF::EF_AMDGPU_MACH_NONE: AK = GK_NONE; break;
124 default: AK = GK_NONE; break;
125 }
126 // clang-format on
127
128 StringRef GPUName = getArchNameAMDGCN(AK);
129 if (GPUName != "")
130 return GPUName;
131 return getArchNameR600(AK);
132}
133
136 if (AK == AMDGPU::GPUKind::GK_NONE)
137 AK = parseArchR600(GPU);
138
139 // clang-format off
140 switch (AK) {
206 }
207 // clang-format on
208
209 llvm_unreachable("unknown GPU");
210}
211
212//===----------------------------------------------------------------------===//
213// AMDGPUTargetAsmStreamer
214//===----------------------------------------------------------------------===//
215
218 : AMDGPUTargetStreamer(S), OS(OS) { }
219
220// A hook for emitting stuff at the end.
221// We use it for emitting the accumulated PAL metadata as directives.
222// The PAL metadata is reset after it is emitted.
224 std::string S;
226 OS << S;
227
228 // Reset the pal metadata so its data will not affect a compilation that
229 // reuses this object.
231}
232
234 OS << "\t.amdgcn_target \"" << getTargetID()->toString() << "\"\n";
235}
236
238 unsigned COV) {
240 OS << "\t.amdhsa_code_object_version " << COV << '\n';
241}
242
243void
245 OS << "\t.amd_kernel_code_t\n";
246 dumpAmdKernelCode(&Header, OS, "\t\t");
247 OS << "\t.end_amd_kernel_code_t\n";
248}
249
251 unsigned Type) {
252 switch (Type) {
253 default: llvm_unreachable("Invalid AMDGPU symbol type");
255 OS << "\t.amdgpu_hsa_kernel " << SymbolName << '\n' ;
256 break;
257 }
258}
259
261 Align Alignment) {
262 OS << "\t.amdgpu_lds " << Symbol->getName() << ", " << Size << ", "
263 << Alignment.value() << '\n';
264}
265
267 OS << "\t.amd_amdgpu_isa \"" << getTargetID()->toString() << "\"\n";
268 return true;
269}
270
272 msgpack::Document &HSAMetadataDoc, bool Strict) {
274 if (!Verifier.verify(HSAMetadataDoc.getRoot()))
275 return false;
276
277 std::string HSAMetadataString;
278 raw_string_ostream StrOS(HSAMetadataString);
279 HSAMetadataDoc.toYAML(StrOS);
280
281 OS << '\t' << HSAMD::V3::AssemblerDirectiveBegin << '\n';
282 OS << StrOS.str() << '\n';
283 OS << '\t' << HSAMD::V3::AssemblerDirectiveEnd << '\n';
284 return true;
285}
286
288 const uint32_t Encoded_s_code_end = 0xbf9f0000;
289 const uint32_t Encoded_s_nop = 0xbf800000;
290 uint32_t Encoded_pad = Encoded_s_code_end;
291
292 // Instruction cache line size in bytes.
293 const unsigned Log2CacheLineSize = AMDGPU::isGFX11Plus(STI) ? 7 : 6;
294 const unsigned CacheLineSize = 1u << Log2CacheLineSize;
295
296 // Extra padding amount in bytes to support prefetch mode 3.
297 unsigned FillSize = 3 * CacheLineSize;
298
299 if (AMDGPU::isGFX90A(STI)) {
300 Encoded_pad = Encoded_s_nop;
301 FillSize = 16 * CacheLineSize;
302 }
303
304 OS << "\t.p2alignl " << Log2CacheLineSize << ", " << Encoded_pad << '\n';
305 OS << "\t.fill " << (FillSize / 4) << ", 4, " << Encoded_pad << '\n';
306 return true;
307}
308
310 const MCSubtargetInfo &STI, StringRef KernelName,
311 const MCKernelDescriptor &KD, uint64_t NextVGPR, uint64_t NextSGPR,
312 bool ReserveVCC, bool ReserveFlatScr) {
313 IsaVersion IVersion = getIsaVersion(STI.getCPU());
314 const MCAsmInfo *MAI = getContext().getAsmInfo();
315
316 OS << "\t.amdhsa_kernel " << KernelName << '\n';
317
318 auto PrintField = [&](const MCExpr *Expr, uint32_t Shift, uint32_t Mask,
320 int64_t IVal;
321 OS << "\t\t" << Directive << ' ';
322 const MCExpr *pgm_rsrc1_bits =
323 MCKernelDescriptor::bits_get(Expr, Shift, Mask, getContext());
324 if (pgm_rsrc1_bits->evaluateAsAbsolute(IVal))
325 OS << static_cast<uint64_t>(IVal);
326 else
327 pgm_rsrc1_bits->print(OS, MAI);
328 OS << '\n';
329 };
330
331 OS << "\t\t.amdhsa_group_segment_fixed_size ";
332 KD.group_segment_fixed_size->print(OS, MAI);
333 OS << '\n';
334
335 OS << "\t\t.amdhsa_private_segment_fixed_size ";
337 OS << '\n';
338
339 OS << "\t\t.amdhsa_kernarg_size ";
340 KD.kernarg_size->print(OS, MAI);
341 OS << '\n';
342
343 PrintField(
344 KD.compute_pgm_rsrc2, amdhsa::COMPUTE_PGM_RSRC2_USER_SGPR_COUNT_SHIFT,
345 amdhsa::COMPUTE_PGM_RSRC2_USER_SGPR_COUNT, ".amdhsa_user_sgpr_count");
346
348 PrintField(
350 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER_SHIFT,
351 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER,
352 ".amdhsa_user_sgpr_private_segment_buffer");
353 PrintField(KD.kernel_code_properties,
354 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR_SHIFT,
355 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR,
356 ".amdhsa_user_sgpr_dispatch_ptr");
357 PrintField(KD.kernel_code_properties,
358 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR_SHIFT,
359 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR,
360 ".amdhsa_user_sgpr_queue_ptr");
361 PrintField(KD.kernel_code_properties,
362 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR_SHIFT,
363 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR,
364 ".amdhsa_user_sgpr_kernarg_segment_ptr");
365 PrintField(KD.kernel_code_properties,
366 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID_SHIFT,
367 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID,
368 ".amdhsa_user_sgpr_dispatch_id");
370 PrintField(KD.kernel_code_properties,
371 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT_SHIFT,
372 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT,
373 ".amdhsa_user_sgpr_flat_scratch_init");
374 if (hasKernargPreload(STI)) {
375 PrintField(KD.kernarg_preload, amdhsa::KERNARG_PRELOAD_SPEC_LENGTH_SHIFT,
376 amdhsa::KERNARG_PRELOAD_SPEC_LENGTH,
377 ".amdhsa_user_sgpr_kernarg_preload_length");
378 PrintField(KD.kernarg_preload, amdhsa::KERNARG_PRELOAD_SPEC_OFFSET_SHIFT,
379 amdhsa::KERNARG_PRELOAD_SPEC_OFFSET,
380 ".amdhsa_user_sgpr_kernarg_preload_offset");
381 }
382 PrintField(
384 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE_SHIFT,
385 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE,
386 ".amdhsa_user_sgpr_private_segment_size");
387 if (IVersion.Major >= 10)
388 PrintField(KD.kernel_code_properties,
389 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32_SHIFT,
390 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32,
391 ".amdhsa_wavefront_size32");
393 PrintField(KD.kernel_code_properties,
394 amdhsa::KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK_SHIFT,
395 amdhsa::KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK,
396 ".amdhsa_uses_dynamic_stack");
397 PrintField(KD.compute_pgm_rsrc2,
398 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT_SHIFT,
399 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT,
401 ? ".amdhsa_enable_private_segment"
402 : ".amdhsa_system_sgpr_private_segment_wavefront_offset"));
403 PrintField(KD.compute_pgm_rsrc2,
404 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X_SHIFT,
405 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X,
406 ".amdhsa_system_sgpr_workgroup_id_x");
407 PrintField(KD.compute_pgm_rsrc2,
408 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y_SHIFT,
409 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y,
410 ".amdhsa_system_sgpr_workgroup_id_y");
411 PrintField(KD.compute_pgm_rsrc2,
412 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z_SHIFT,
413 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z,
414 ".amdhsa_system_sgpr_workgroup_id_z");
415 PrintField(KD.compute_pgm_rsrc2,
416 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO_SHIFT,
417 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO,
418 ".amdhsa_system_sgpr_workgroup_info");
419 PrintField(KD.compute_pgm_rsrc2,
420 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID_SHIFT,
421 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID,
422 ".amdhsa_system_vgpr_workitem_id");
423
424 // These directives are required.
425 OS << "\t\t.amdhsa_next_free_vgpr " << NextVGPR << '\n';
426 OS << "\t\t.amdhsa_next_free_sgpr " << NextSGPR << '\n';
427
428 if (AMDGPU::isGFX90A(STI)) {
429 // MCExpr equivalent of taking the (accum_offset + 1) * 4.
430 const MCExpr *accum_bits = MCKernelDescriptor::bits_get(
432 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET_SHIFT,
433 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET, getContext());
434 accum_bits = MCBinaryExpr::createAdd(
435 accum_bits, MCConstantExpr::create(1, getContext()), getContext());
436 accum_bits = MCBinaryExpr::createMul(
437 accum_bits, MCConstantExpr::create(4, getContext()), getContext());
438 OS << "\t\t.amdhsa_accum_offset ";
439 int64_t IVal;
440 if (accum_bits->evaluateAsAbsolute(IVal)) {
441 OS << static_cast<uint64_t>(IVal);
442 } else {
443 accum_bits->print(OS, MAI);
444 }
445 OS << '\n';
446 }
447
448 if (!ReserveVCC)
449 OS << "\t\t.amdhsa_reserve_vcc " << ReserveVCC << '\n';
450 if (IVersion.Major >= 7 && !ReserveFlatScr && !hasArchitectedFlatScratch(STI))
451 OS << "\t\t.amdhsa_reserve_flat_scratch " << ReserveFlatScr << '\n';
452
453 switch (CodeObjectVersion) {
454 default:
455 break;
458 if (getTargetID()->isXnackSupported())
459 OS << "\t\t.amdhsa_reserve_xnack_mask " << getTargetID()->isXnackOnOrAny() << '\n';
460 break;
461 }
462
463 PrintField(KD.compute_pgm_rsrc1,
464 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32_SHIFT,
465 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32,
466 ".amdhsa_float_round_mode_32");
467 PrintField(KD.compute_pgm_rsrc1,
468 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64_SHIFT,
469 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64,
470 ".amdhsa_float_round_mode_16_64");
471 PrintField(KD.compute_pgm_rsrc1,
472 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32_SHIFT,
473 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32,
474 ".amdhsa_float_denorm_mode_32");
475 PrintField(KD.compute_pgm_rsrc1,
476 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64_SHIFT,
477 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64,
478 ".amdhsa_float_denorm_mode_16_64");
479 if (IVersion.Major < 12) {
480 PrintField(KD.compute_pgm_rsrc1,
481 amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_DX10_CLAMP_SHIFT,
482 amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_DX10_CLAMP,
483 ".amdhsa_dx10_clamp");
484 PrintField(KD.compute_pgm_rsrc1,
485 amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_IEEE_MODE_SHIFT,
486 amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_IEEE_MODE,
487 ".amdhsa_ieee_mode");
488 }
489 if (IVersion.Major >= 9) {
490 PrintField(KD.compute_pgm_rsrc1,
491 amdhsa::COMPUTE_PGM_RSRC1_GFX9_PLUS_FP16_OVFL_SHIFT,
492 amdhsa::COMPUTE_PGM_RSRC1_GFX9_PLUS_FP16_OVFL,
493 ".amdhsa_fp16_overflow");
494 }
495 if (AMDGPU::isGFX90A(STI))
496 PrintField(KD.compute_pgm_rsrc3,
497 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT_SHIFT,
498 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT, ".amdhsa_tg_split");
499 if (IVersion.Major >= 10) {
500 PrintField(KD.compute_pgm_rsrc1,
501 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_WGP_MODE_SHIFT,
502 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_WGP_MODE,
503 ".amdhsa_workgroup_processor_mode");
504 PrintField(KD.compute_pgm_rsrc1,
505 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_MEM_ORDERED_SHIFT,
506 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_MEM_ORDERED,
507 ".amdhsa_memory_ordered");
508 PrintField(KD.compute_pgm_rsrc1,
509 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_FWD_PROGRESS_SHIFT,
510 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_FWD_PROGRESS,
511 ".amdhsa_forward_progress");
512 }
513 if (IVersion.Major >= 10 && IVersion.Major < 12) {
514 PrintField(KD.compute_pgm_rsrc3,
515 amdhsa::COMPUTE_PGM_RSRC3_GFX10_GFX11_SHARED_VGPR_COUNT_SHIFT,
516 amdhsa::COMPUTE_PGM_RSRC3_GFX10_GFX11_SHARED_VGPR_COUNT,
517 ".amdhsa_shared_vgpr_count");
518 }
519 if (IVersion.Major >= 12) {
520 PrintField(KD.compute_pgm_rsrc1,
521 amdhsa::COMPUTE_PGM_RSRC1_GFX12_PLUS_ENABLE_WG_RR_EN_SHIFT,
522 amdhsa::COMPUTE_PGM_RSRC1_GFX12_PLUS_ENABLE_WG_RR_EN,
523 ".amdhsa_round_robin_scheduling");
524 }
525 PrintField(
527 amdhsa::
528 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION_SHIFT,
529 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION,
530 ".amdhsa_exception_fp_ieee_invalid_op");
531 PrintField(
533 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE_SHIFT,
534 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE,
535 ".amdhsa_exception_fp_denorm_src");
536 PrintField(
538 amdhsa::
539 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO_SHIFT,
540 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO,
541 ".amdhsa_exception_fp_ieee_div_zero");
542 PrintField(
544 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW_SHIFT,
545 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW,
546 ".amdhsa_exception_fp_ieee_overflow");
547 PrintField(
549 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW_SHIFT,
550 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW,
551 ".amdhsa_exception_fp_ieee_underflow");
552 PrintField(
554 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT_SHIFT,
555 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT,
556 ".amdhsa_exception_fp_ieee_inexact");
557 PrintField(
559 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO_SHIFT,
560 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO,
561 ".amdhsa_exception_int_div_zero");
562
563 OS << "\t.end_amdhsa_kernel\n";
564}
565
566//===----------------------------------------------------------------------===//
567// AMDGPUTargetELFStreamer
568//===----------------------------------------------------------------------===//
569
571 const MCSubtargetInfo &STI)
572 : AMDGPUTargetStreamer(S), STI(STI), Streamer(S) {}
573
575 return static_cast<MCELFStreamer &>(Streamer);
576}
577
578// A hook for emitting stuff at the end.
579// We use it for emitting the accumulated PAL metadata as a .note record.
580// The PAL metadata is reset after it is emitted.
583 MCA.setELFHeaderEFlags(getEFlags());
586
587 std::string Blob;
588 const char *Vendor = getPALMetadata()->getVendor();
589 unsigned Type = getPALMetadata()->getType();
590 getPALMetadata()->toBlob(Type, Blob);
591 if (Blob.empty())
592 return;
593 EmitNote(Vendor, MCConstantExpr::create(Blob.size(), getContext()), Type,
594 [&](MCELFStreamer &OS) { OS.emitBytes(Blob); });
595
596 // Reset the pal metadata so its data will not affect a compilation that
597 // reuses this object.
599}
600
601void AMDGPUTargetELFStreamer::EmitNote(
602 StringRef Name, const MCExpr *DescSZ, unsigned NoteType,
603 function_ref<void(MCELFStreamer &)> EmitDesc) {
604 auto &S = getStreamer();
605 auto &Context = S.getContext();
606
607 auto NameSZ = Name.size() + 1;
608
609 unsigned NoteFlags = 0;
610 // TODO Apparently, this is currently needed for OpenCL as mentioned in
611 // https://reviews.llvm.org/D74995
612 if (isHsaAbi(STI))
613 NoteFlags = ELF::SHF_ALLOC;
614
615 S.pushSection();
616 S.switchSection(
617 Context.getELFSection(ElfNote::SectionName, ELF::SHT_NOTE, NoteFlags));
618 S.emitInt32(NameSZ); // namesz
619 S.emitValue(DescSZ, 4); // descz
620 S.emitInt32(NoteType); // type
621 S.emitBytes(Name); // name
622 S.emitValueToAlignment(Align(4), 0, 1, 0); // padding 0
623 EmitDesc(S); // desc
624 S.emitValueToAlignment(Align(4), 0, 1, 0); // padding 0
625 S.popSection();
626}
627
628unsigned AMDGPUTargetELFStreamer::getEFlags() {
629 switch (STI.getTargetTriple().getArch()) {
630 default:
631 llvm_unreachable("Unsupported Arch");
632 case Triple::r600:
633 return getEFlagsR600();
634 case Triple::amdgcn:
635 return getEFlagsAMDGCN();
636 }
637}
638
639unsigned AMDGPUTargetELFStreamer::getEFlagsR600() {
641
642 return getElfMach(STI.getCPU());
643}
644
645unsigned AMDGPUTargetELFStreamer::getEFlagsAMDGCN() {
647
648 switch (STI.getTargetTriple().getOS()) {
649 default:
650 // TODO: Why are some tests have "mingw" listed as OS?
651 // llvm_unreachable("Unsupported OS");
653 return getEFlagsUnknownOS();
654 case Triple::AMDHSA:
655 return getEFlagsAMDHSA();
656 case Triple::AMDPAL:
657 return getEFlagsAMDPAL();
658 case Triple::Mesa3D:
659 return getEFlagsMesa3D();
660 }
661}
662
663unsigned AMDGPUTargetELFStreamer::getEFlagsUnknownOS() {
664 // TODO: Why are some tests have "mingw" listed as OS?
665 // assert(STI.getTargetTriple().getOS() == Triple::UnknownOS);
666
667 return getEFlagsV3();
668}
669
670unsigned AMDGPUTargetELFStreamer::getEFlagsAMDHSA() {
671 assert(isHsaAbi(STI));
672
673 if (CodeObjectVersion >= 6)
674 return getEFlagsV6();
675 return getEFlagsV4();
676}
677
678unsigned AMDGPUTargetELFStreamer::getEFlagsAMDPAL() {
680
681 return getEFlagsV3();
682}
683
684unsigned AMDGPUTargetELFStreamer::getEFlagsMesa3D() {
686
687 return getEFlagsV3();
688}
689
690unsigned AMDGPUTargetELFStreamer::getEFlagsV3() {
691 unsigned EFlagsV3 = 0;
692
693 // mach.
694 EFlagsV3 |= getElfMach(STI.getCPU());
695
696 // xnack.
697 if (getTargetID()->isXnackOnOrAny())
699 // sramecc.
700 if (getTargetID()->isSramEccOnOrAny())
702
703 return EFlagsV3;
704}
705
706unsigned AMDGPUTargetELFStreamer::getEFlagsV4() {
707 unsigned EFlagsV4 = 0;
708
709 // mach.
710 EFlagsV4 |= getElfMach(STI.getCPU());
711
712 // xnack.
713 switch (getTargetID()->getXnackSetting()) {
716 break;
719 break;
722 break;
725 break;
726 }
727 // sramecc.
728 switch (getTargetID()->getSramEccSetting()) {
731 break;
734 break;
737 break;
740 break;
741 }
742
743 return EFlagsV4;
744}
745
746unsigned AMDGPUTargetELFStreamer::getEFlagsV6() {
747 unsigned Flags = getEFlagsV4();
748
749 unsigned Version = ForceGenericVersion;
750 if (!Version) {
751 switch (parseArchAMDGCN(STI.getCPU())) {
754 break;
757 break;
760 break;
763 break;
764 default:
765 break;
766 }
767 }
768
769 // Versions start at 1.
770 if (Version) {
772 report_fatal_error("Cannot encode generic code object version " +
773 Twine(Version) +
774 " - no ELF flag can represent this version!");
776 }
777
778 return Flags;
779}
780
782
783void
785
787 OS.pushSection();
788 OS.emitBytes(StringRef((const char*)&Header, sizeof(Header)));
789 OS.popSection();
790}
791
793 unsigned Type) {
794 MCSymbolELF *Symbol = cast<MCSymbolELF>(
795 getStreamer().getContext().getOrCreateSymbol(SymbolName));
796 Symbol->setType(Type);
797}
798
800 Align Alignment) {
801 MCSymbolELF *SymbolELF = cast<MCSymbolELF>(Symbol);
802 SymbolELF->setType(ELF::STT_OBJECT);
803
804 if (!SymbolELF->isBindingSet()) {
805 SymbolELF->setBinding(ELF::STB_GLOBAL);
806 SymbolELF->setExternal(true);
807 }
808
809 if (SymbolELF->declareCommon(Size, Alignment, true)) {
810 report_fatal_error("Symbol: " + Symbol->getName() +
811 " redeclared as different type");
812 }
813
814 SymbolELF->setIndex(ELF::SHN_AMDGPU_LDS);
816}
817
819 // Create two labels to mark the beginning and end of the desc field
820 // and a MCExpr to calculate the size of the desc field.
821 auto &Context = getContext();
822 auto *DescBegin = Context.createTempSymbol();
823 auto *DescEnd = Context.createTempSymbol();
824 auto *DescSZ = MCBinaryExpr::createSub(
827
829 [&](MCELFStreamer &OS) {
830 OS.emitLabel(DescBegin);
831 OS.emitBytes(getTargetID()->toString());
832 OS.emitLabel(DescEnd);
833 });
834 return true;
835}
836
838 bool Strict) {
840 if (!Verifier.verify(HSAMetadataDoc.getRoot()))
841 return false;
842
843 std::string HSAMetadataString;
844 HSAMetadataDoc.writeToBlob(HSAMetadataString);
845
846 // Create two labels to mark the beginning and end of the desc field
847 // and a MCExpr to calculate the size of the desc field.
848 auto &Context = getContext();
849 auto *DescBegin = Context.createTempSymbol();
850 auto *DescEnd = Context.createTempSymbol();
851 auto *DescSZ = MCBinaryExpr::createSub(
854
856 [&](MCELFStreamer &OS) {
857 OS.emitLabel(DescBegin);
858 OS.emitBytes(HSAMetadataString);
859 OS.emitLabel(DescEnd);
860 });
861 return true;
862}
863
865 const MCSubtargetInfo &STI, bool TrapEnabled) {
866 const char *TrapInstr = TrapEnabled ? "\ts_trap 2" : "\ts_endpgm";
867 OS << TrapInstr
868 << " ; Trap with incompatible firmware that doesn't "
869 "support preloading kernel arguments.\n";
870 for (int i = 0; i < 63; ++i) {
871 OS << "\ts_nop 0\n";
872 }
873 return true;
874}
875
877 const MCSubtargetInfo &STI, bool TrapEnabled) {
878 const uint32_t Encoded_s_nop = 0xbf800000;
879 const uint32_t Encoded_s_trap = 0xbf920002;
880 const uint32_t Encoded_s_endpgm = 0xbf810000;
881 const uint32_t TrapInstr = TrapEnabled ? Encoded_s_trap : Encoded_s_endpgm;
883 OS.emitInt32(TrapInstr);
884 for (int i = 0; i < 63; ++i) {
885 OS.emitInt32(Encoded_s_nop);
886 }
887 return true;
888}
889
891 const uint32_t Encoded_s_code_end = 0xbf9f0000;
892 const uint32_t Encoded_s_nop = 0xbf800000;
893 uint32_t Encoded_pad = Encoded_s_code_end;
894
895 // Instruction cache line size in bytes.
896 const unsigned Log2CacheLineSize = AMDGPU::isGFX11Plus(STI) ? 7 : 6;
897 const unsigned CacheLineSize = 1u << Log2CacheLineSize;
898
899 // Extra padding amount in bytes to support prefetch mode 3.
900 unsigned FillSize = 3 * CacheLineSize;
901
902 if (AMDGPU::isGFX90A(STI)) {
903 Encoded_pad = Encoded_s_nop;
904 FillSize = 16 * CacheLineSize;
905 }
906
908 OS.pushSection();
909 OS.emitValueToAlignment(Align(CacheLineSize), Encoded_pad, 4);
910 for (unsigned I = 0; I < FillSize; I += 4)
911 OS.emitInt32(Encoded_pad);
912 OS.popSection();
913 return true;
914}
915
917 const MCSubtargetInfo &STI, StringRef KernelName,
918 const MCKernelDescriptor &KernelDescriptor, uint64_t NextVGPR,
919 uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr) {
920 auto &Streamer = getStreamer();
921 auto &Context = Streamer.getContext();
922
923 MCSymbolELF *KernelCodeSymbol = cast<MCSymbolELF>(
924 Context.getOrCreateSymbol(Twine(KernelName)));
925 MCSymbolELF *KernelDescriptorSymbol = cast<MCSymbolELF>(
926 Context.getOrCreateSymbol(Twine(KernelName) + Twine(".kd")));
927
928 // Copy kernel descriptor symbol's binding, other and visibility from the
929 // kernel code symbol.
930 KernelDescriptorSymbol->setBinding(KernelCodeSymbol->getBinding());
931 KernelDescriptorSymbol->setOther(KernelCodeSymbol->getOther());
932 KernelDescriptorSymbol->setVisibility(KernelCodeSymbol->getVisibility());
933 // Kernel descriptor symbol's type and size are fixed.
934 KernelDescriptorSymbol->setType(ELF::STT_OBJECT);
935 KernelDescriptorSymbol->setSize(
937
938 // The visibility of the kernel code symbol must be protected or less to allow
939 // static relocations from the kernel descriptor to be used.
940 if (KernelCodeSymbol->getVisibility() == ELF::STV_DEFAULT)
941 KernelCodeSymbol->setVisibility(ELF::STV_PROTECTED);
942
943 Streamer.emitLabel(KernelDescriptorSymbol);
944 Streamer.emitValue(
945 KernelDescriptor.group_segment_fixed_size,
947 Streamer.emitValue(
948 KernelDescriptor.private_segment_fixed_size,
950 Streamer.emitValue(KernelDescriptor.kernarg_size,
952
953 for (uint32_t i = 0; i < sizeof(amdhsa::kernel_descriptor_t::reserved0); ++i)
954 Streamer.emitInt8(0u);
955
956 // FIXME: Remove the use of VK_AMDGPU_REL64 in the expression below. The
957 // expression being created is:
958 // (start of kernel code) - (start of kernel descriptor)
959 // It implies R_AMDGPU_REL64, but ends up being R_AMDGPU_ABS64.
960 Streamer.emitValue(
962 MCSymbolRefExpr::create(KernelCodeSymbol,
964 MCSymbolRefExpr::create(KernelDescriptorSymbol,
966 Context),
968 for (uint32_t i = 0; i < sizeof(amdhsa::kernel_descriptor_t::reserved1); ++i)
969 Streamer.emitInt8(0u);
970 Streamer.emitValue(KernelDescriptor.compute_pgm_rsrc3,
972 Streamer.emitValue(KernelDescriptor.compute_pgm_rsrc1,
974 Streamer.emitValue(KernelDescriptor.compute_pgm_rsrc2,
976 Streamer.emitValue(
977 KernelDescriptor.kernel_code_properties,
979 Streamer.emitValue(KernelDescriptor.kernarg_preload,
981 for (uint32_t i = 0; i < sizeof(amdhsa::kernel_descriptor_t::reserved3); ++i)
982 Streamer.emitInt8(0u);
983}
AMDHSA kernel descriptor MCExpr struct for use in MC layer.
This is a verifier for AMDGPU HSA metadata, which can verify both well-typed metadata and untyped met...
AMDGPU metadata definitions and in-memory representations.
Enums and constants for AMDGPU PT_NOTE sections.
static cl::opt< unsigned > ForceGenericVersion("amdgpu-force-generic-version", cl::desc("Force a specific generic_v<N> flag to be " "added. For testing purposes only."), cl::ReallyHidden, cl::init(0))
AMDHSA kernel descriptor definitions.
std::string Name
uint64_t Size
#define I(x, y, z)
Definition: MD5.cpp:58
LLVMContext & Context
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
verify safepoint Safepoint IR Verifier
raw_pwrite_stream & OS
static cl::opt< unsigned > CacheLineSize("cache-line-size", cl::init(0), cl::Hidden, cl::desc("Use this to override the target cache line size when " "specified by the user."))
const char * getVendor() const
void toBlob(unsigned Type, std::string &S)
void toString(std::string &S)
void EmitAMDKernelCodeT(const amd_kernel_code_t &Header) override
AMDGPUTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS)
bool EmitHSAMetadata(msgpack::Document &HSAMetadata, bool Strict) override
void EmitAMDGPUSymbolType(StringRef SymbolName, unsigned Type) override
void EmitDirectiveAMDHSACodeObjectVersion(unsigned COV) override
void EmitAmdhsaKernelDescriptor(const MCSubtargetInfo &STI, StringRef KernelName, const AMDGPU::MCKernelDescriptor &KernelDescriptor, uint64_t NextVGPR, uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr) override
bool EmitKernargPreloadHeader(const MCSubtargetInfo &STI, bool TrapEnabled) override
bool EmitCodeEnd(const MCSubtargetInfo &STI) override
void emitAMDGPULDS(MCSymbol *Sym, unsigned Size, Align Alignment) override
bool EmitCodeEnd(const MCSubtargetInfo &STI) override
void EmitAMDKernelCodeT(const amd_kernel_code_t &Header) override
bool EmitHSAMetadata(msgpack::Document &HSAMetadata, bool Strict) override
AMDGPUTargetELFStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
void emitAMDGPULDS(MCSymbol *Sym, unsigned Size, Align Alignment) override
void EmitAmdhsaKernelDescriptor(const MCSubtargetInfo &STI, StringRef KernelName, const AMDGPU::MCKernelDescriptor &KernelDescriptor, uint64_t NextVGPR, uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr) override
void EmitAMDGPUSymbolType(StringRef SymbolName, unsigned Type) override
bool EmitKernargPreloadHeader(const MCSubtargetInfo &STI, bool TrapEnabled) override
virtual bool EmitHSAMetadata(msgpack::Document &HSAMetadata, bool Strict)
Emit HSA Metadata.
AMDGPUPALMetadata * getPALMetadata()
virtual void EmitDirectiveAMDHSACodeObjectVersion(unsigned COV)
virtual bool EmitHSAMetadataV3(StringRef HSAMetadataString)
static unsigned getElfMach(StringRef GPU)
MCContext & getContext() const
static StringRef getArchNameFromElfMach(unsigned ElfMach)
const std::optional< AMDGPU::IsaInfo::AMDGPUTargetID > & getTargetID() const
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
MCObjectWriter & getWriter() const
Definition: MCAssembler.h:338
void setELFHeaderEFlags(unsigned Flags)
Definition: MCAssembler.h:282
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:536
static const MCBinaryExpr * createMul(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:591
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
Definition: MCExpr.h:621
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Definition: MCExpr.cpp:194
const MCAsmInfo * getAsmInfo() const
Definition: MCContext.h:446
Base class for the full range of assembler expressions which are needed for parsing.
Definition: MCExpr.h:35
void print(raw_ostream &OS, const MCAsmInfo *MAI, bool InParens=false) const
Definition: MCExpr.cpp:41
MCAssembler & getAssembler()
virtual void setOverrideABIVersion(uint8_t ABIVersion)
ELF only, override the default ABIVersion in the ELF header.
Streaming machine code generation interface.
Definition: MCStreamer.h:212
MCContext & getContext() const
Definition: MCStreamer.h:297
void emitValue(const MCExpr *Value, unsigned Size, SMLoc Loc=SMLoc())
Definition: MCStreamer.cpp:180
virtual void emitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc())
Emit a label for Symbol into the current section.
Definition: MCStreamer.cpp:424
void emitInt8(uint64_t Value)
Definition: MCStreamer.h:752
Generic base class for all target subtargets.
const Triple & getTargetTriple() const
StringRef getCPU() const
unsigned getOther() const
void setVisibility(unsigned Visibility)
void setSize(const MCExpr *SS)
Definition: MCSymbolELF.h:22
bool isBindingSet() const
void setBinding(unsigned Binding) const
Definition: MCSymbolELF.cpp:43
unsigned getVisibility() const
unsigned getBinding() const
Definition: MCSymbolELF.cpp:66
void setType(unsigned Type) const
Definition: MCSymbolELF.cpp:94
void setOther(unsigned Other)
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
Definition: MCExpr.h:397
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
Definition: MCSymbol.h:40
void setExternal(bool Value) const
Definition: MCSymbol.h:407
void setIndex(uint32_t Value) const
Set the (implementation defined) index.
Definition: MCSymbol.h:321
bool declareCommon(uint64_t Size, Align Alignment, bool Target=false)
Declare this symbol as being 'common'.
Definition: MCSymbol.h:375
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
OSType getOS() const
Get the parsed operating system type of this triple.
Definition: Triple.h:370
ArchType getArch() const
Get the parsed architecture type of this triple.
Definition: Triple.h:361
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
formatted_raw_ostream - A raw_ostream that wraps another one and keeps track of line and column posit...
An efficient, type-erasing, non-owning reference to a callable.
Simple in-memory representation of a document of msgpack objects with ability to find and create arra...
DocNode & getRoot()
Get ref to the document's root element.
void toYAML(raw_ostream &OS)
Convert MsgPack Document to YAML text.
void writeToBlob(std::string &Blob)
Write a MsgPack document to a binary MsgPack blob.
bool fromYAML(StringRef S)
Read YAML text into the MsgPack document. Returns false on failure.
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:660
std::string & str()
Returns the string's reference.
Definition: raw_ostream.h:678
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const char NoteNameV2[]
Definition: AMDGPUPTNote.h:26
const char SectionName[]
Definition: AMDGPUPTNote.h:24
const char NoteNameV3[]
Definition: AMDGPUPTNote.h:27
static constexpr unsigned GFX10_1
static constexpr unsigned GFX10_3
static constexpr unsigned GFX11
static constexpr unsigned GFX9
constexpr char AssemblerDirectiveBegin[]
HSA metadata beginning assembler directive.
constexpr char AssemblerDirectiveEnd[]
HSA metadata ending assembler directive.
StringRef getArchNameR600(GPUKind AK)
GPUKind
GPU kinds supported by the AMDGPU target.
Definition: TargetParser.h:35
bool isHsaAbi(const MCSubtargetInfo &STI)
IsaVersion getIsaVersion(StringRef GPU)
bool isGFX90A(const MCSubtargetInfo &STI)
GPUKind parseArchAMDGCN(StringRef CPU)
bool hasArchitectedFlatScratch(const MCSubtargetInfo &STI)
bool isGFX11Plus(const MCSubtargetInfo &STI)
StringRef getArchNameAMDGCN(GPUKind AK)
unsigned hasKernargPreload(const MCSubtargetInfo &STI)
uint8_t getELFABIVersion(const Triple &T, unsigned CodeObjectVersion)
GPUKind parseArchR600(StringRef CPU)
@ SHF_ALLOC
Definition: ELF.h:1157
@ STV_PROTECTED
Definition: ELF.h:1343
@ STV_DEFAULT
Definition: ELF.h:1340
@ SHN_AMDGPU_LDS
Definition: ELF.h:1834
@ EF_AMDGPU_GENERIC_VERSION_MAX
Definition: ELF.h:857
@ EF_AMDGPU_FEATURE_XNACK_ANY_V4
Definition: ELF.h:834
@ EF_AMDGPU_MACH_AMDGCN_GFX703
Definition: ELF.h:750
@ EF_AMDGPU_MACH_AMDGCN_GFX1035
Definition: ELF.h:774
@ EF_AMDGPU_FEATURE_SRAMECC_V3
Definition: ELF.h:825
@ EF_AMDGPU_MACH_AMDGCN_GFX1031
Definition: ELF.h:768
@ EF_AMDGPU_GENERIC_VERSION_OFFSET
Definition: ELF.h:855
@ EF_AMDGPU_MACH_R600_CAYMAN
Definition: ELF.h:732
@ EF_AMDGPU_FEATURE_SRAMECC_UNSUPPORTED_V4
Definition: ELF.h:845
@ EF_AMDGPU_MACH_AMDGCN_GFX704
Definition: ELF.h:751
@ EF_AMDGPU_MACH_AMDGCN_GFX902
Definition: ELF.h:758
@ EF_AMDGPU_MACH_AMDGCN_GFX810
Definition: ELF.h:756
@ EF_AMDGPU_MACH_AMDGCN_GFX1036
Definition: ELF.h:782
@ EF_AMDGPU_MACH_AMDGCN_GFX1102
Definition: ELF.h:784
@ EF_AMDGPU_MACH_R600_RV730
Definition: ELF.h:721
@ EF_AMDGPU_MACH_R600_RV710
Definition: ELF.h:720
@ EF_AMDGPU_MACH_AMDGCN_GFX908
Definition: ELF.h:761
@ EF_AMDGPU_MACH_AMDGCN_GFX1011
Definition: ELF.h:765
@ EF_AMDGPU_MACH_R600_CYPRESS
Definition: ELF.h:725
@ EF_AMDGPU_MACH_AMDGCN_GFX1032
Definition: ELF.h:769
@ EF_AMDGPU_MACH_R600_R600
Definition: ELF.h:715
@ EF_AMDGPU_MACH_AMDGCN_GFX940
Definition: ELF.h:777
@ EF_AMDGPU_MACH_AMDGCN_GFX941
Definition: ELF.h:788
@ EF_AMDGPU_MACH_R600_TURKS
Definition: ELF.h:733
@ EF_AMDGPU_MACH_R600_JUNIPER
Definition: ELF.h:726
@ EF_AMDGPU_FEATURE_SRAMECC_OFF_V4
Definition: ELF.h:849
@ EF_AMDGPU_FEATURE_XNACK_UNSUPPORTED_V4
Definition: ELF.h:832
@ EF_AMDGPU_MACH_AMDGCN_GFX601
Definition: ELF.h:746
@ EF_AMDGPU_MACH_AMDGCN_GFX942
Definition: ELF.h:789
@ EF_AMDGPU_MACH_R600_R630
Definition: ELF.h:716
@ EF_AMDGPU_MACH_R600_REDWOOD
Definition: ELF.h:727
@ EF_AMDGPU_MACH_R600_RV770
Definition: ELF.h:722
@ EF_AMDGPU_FEATURE_XNACK_OFF_V4
Definition: ELF.h:836
@ EF_AMDGPU_MACH_AMDGCN_GFX600
Definition: ELF.h:745
@ EF_AMDGPU_FEATURE_XNACK_V3
Definition: ELF.h:820
@ EF_AMDGPU_MACH_AMDGCN_GFX602
Definition: ELF.h:771
@ EF_AMDGPU_MACH_AMDGCN_GFX1101
Definition: ELF.h:783
@ EF_AMDGPU_MACH_AMDGCN_GFX1100
Definition: ELF.h:778
@ EF_AMDGPU_MACH_AMDGCN_GFX1033
Definition: ELF.h:770
@ EF_AMDGPU_MACH_AMDGCN_GFX801
Definition: ELF.h:753
@ EF_AMDGPU_MACH_AMDGCN_GFX705
Definition: ELF.h:772
@ EF_AMDGPU_MACH_AMDGCN_GFX1010
Definition: ELF.h:764
@ EF_AMDGPU_MACH_R600_RV670
Definition: ELF.h:718
@ EF_AMDGPU_MACH_AMDGCN_GFX701
Definition: ELF.h:748
@ EF_AMDGPU_MACH_AMDGCN_GFX10_3_GENERIC
Definition: ELF.h:796
@ EF_AMDGPU_MACH_AMDGCN_GFX1012
Definition: ELF.h:766
@ EF_AMDGPU_MACH_AMDGCN_GFX1151
Definition: ELF.h:787
@ EF_AMDGPU_MACH_AMDGCN_GFX1030
Definition: ELF.h:767
@ EF_AMDGPU_MACH_R600_CEDAR
Definition: ELF.h:724
@ EF_AMDGPU_MACH_AMDGCN_GFX1200
Definition: ELF.h:785
@ EF_AMDGPU_MACH_AMDGCN_GFX700
Definition: ELF.h:747
@ EF_AMDGPU_MACH_AMDGCN_GFX11_GENERIC
Definition: ELF.h:797
@ EF_AMDGPU_MACH_AMDGCN_GFX803
Definition: ELF.h:755
@ EF_AMDGPU_MACH_AMDGCN_GFX802
Definition: ELF.h:754
@ EF_AMDGPU_MACH_AMDGCN_GFX90C
Definition: ELF.h:763
@ EF_AMDGPU_FEATURE_XNACK_ON_V4
Definition: ELF.h:838
@ EF_AMDGPU_MACH_AMDGCN_GFX900
Definition: ELF.h:757
@ EF_AMDGPU_MACH_AMDGCN_GFX909
Definition: ELF.h:762
@ EF_AMDGPU_MACH_AMDGCN_GFX906
Definition: ELF.h:760
@ EF_AMDGPU_MACH_NONE
Definition: ELF.h:710
@ EF_AMDGPU_MACH_AMDGCN_GFX9_GENERIC
Definition: ELF.h:794
@ EF_AMDGPU_MACH_AMDGCN_GFX1103
Definition: ELF.h:781
@ EF_AMDGPU_MACH_R600_CAICOS
Definition: ELF.h:731
@ EF_AMDGPU_MACH_AMDGCN_GFX90A
Definition: ELF.h:776
@ EF_AMDGPU_MACH_AMDGCN_GFX1034
Definition: ELF.h:775
@ EF_AMDGPU_MACH_AMDGCN_GFX1013
Definition: ELF.h:779
@ EF_AMDGPU_MACH_AMDGCN_GFX10_1_GENERIC
Definition: ELF.h:795
@ EF_AMDGPU_MACH_AMDGCN_GFX904
Definition: ELF.h:759
@ EF_AMDGPU_MACH_R600_RS880
Definition: ELF.h:717
@ EF_AMDGPU_MACH_AMDGCN_GFX805
Definition: ELF.h:773
@ EF_AMDGPU_MACH_AMDGCN_GFX1201
Definition: ELF.h:791
@ EF_AMDGPU_MACH_AMDGCN_GFX1150
Definition: ELF.h:780
@ EF_AMDGPU_MACH_R600_SUMO
Definition: ELF.h:728
@ EF_AMDGPU_MACH_R600_BARTS
Definition: ELF.h:730
@ EF_AMDGPU_FEATURE_SRAMECC_ANY_V4
Definition: ELF.h:847
@ EF_AMDGPU_FEATURE_SRAMECC_ON_V4
Definition: ELF.h:851
@ EF_AMDGPU_MACH_AMDGCN_GFX702
Definition: ELF.h:749
@ SHT_NOTE
Definition: ELF.h:1069
@ NT_AMDGPU_METADATA
Definition: ELF.h:1851
@ STB_GLOBAL
Definition: ELF.h:1311
@ NT_AMD_HSA_ISA_NAME
Definition: ELF.h:1844
@ STT_AMDGPU_HSA_KERNEL
Definition: ELF.h:1336
@ STT_OBJECT
Definition: ELF.h:1323
const uint64_t Version
Definition: InstrProf.h:1047
@ ReallyHidden
Definition: CommandLine.h:139
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:450
std::optional< const char * > toString(const std::optional< DWARFFormValue > &V)
Take an optional DWARFFormValue and try to extract a string value from it.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:156
void dumpAmdKernelCode(const amd_kernel_code_t *C, raw_ostream &OS, const char *tab)
AMD Kernel Code Object (amd_kernel_code_t).
Instruction set architecture version.
Definition: TargetParser.h:125
static const MCExpr * bits_get(const MCExpr *Src, uint32_t Shift, uint32_t Mask, MCContext &Ctx)
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
uint64_t value() const
This is a hole in the type system and should not be abused.
Definition: Alignment.h:85