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ARMAsmPrinter.cpp
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00001 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file contains a printer that converts from our internal representation
00011 // of machine-dependent LLVM code to GAS-format ARM assembly language.
00012 //
00013 //===----------------------------------------------------------------------===//
00014 
00015 #include "ARMAsmPrinter.h"
00016 #include "ARM.h"
00017 #include "ARMConstantPoolValue.h"
00018 #include "ARMFPUName.h"
00019 #include "ARMMachineFunctionInfo.h"
00020 #include "ARMTargetMachine.h"
00021 #include "ARMTargetObjectFile.h"
00022 #include "InstPrinter/ARMInstPrinter.h"
00023 #include "MCTargetDesc/ARMAddressingModes.h"
00024 #include "MCTargetDesc/ARMMCExpr.h"
00025 #include "llvm/ADT/SetVector.h"
00026 #include "llvm/ADT/SmallString.h"
00027 #include "llvm/CodeGen/MachineFunctionPass.h"
00028 #include "llvm/CodeGen/MachineJumpTableInfo.h"
00029 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
00030 #include "llvm/IR/Constants.h"
00031 #include "llvm/IR/DataLayout.h"
00032 #include "llvm/IR/DebugInfo.h"
00033 #include "llvm/IR/Mangler.h"
00034 #include "llvm/IR/Module.h"
00035 #include "llvm/IR/Type.h"
00036 #include "llvm/MC/MCAsmInfo.h"
00037 #include "llvm/MC/MCAssembler.h"
00038 #include "llvm/MC/MCContext.h"
00039 #include "llvm/MC/MCELFStreamer.h"
00040 #include "llvm/MC/MCInst.h"
00041 #include "llvm/MC/MCInstBuilder.h"
00042 #include "llvm/MC/MCObjectStreamer.h"
00043 #include "llvm/MC/MCSectionMachO.h"
00044 #include "llvm/MC/MCStreamer.h"
00045 #include "llvm/MC/MCSymbol.h"
00046 #include "llvm/Support/ARMBuildAttributes.h"
00047 #include "llvm/Support/COFF.h"
00048 #include "llvm/Support/CommandLine.h"
00049 #include "llvm/Support/Debug.h"
00050 #include "llvm/Support/ELF.h"
00051 #include "llvm/Support/ErrorHandling.h"
00052 #include "llvm/Support/TargetRegistry.h"
00053 #include "llvm/Support/raw_ostream.h"
00054 #include "llvm/Target/TargetMachine.h"
00055 #include <cctype>
00056 using namespace llvm;
00057 
00058 #define DEBUG_TYPE "asm-printer"
00059 
00060 void ARMAsmPrinter::EmitFunctionBodyEnd() {
00061   // Make sure to terminate any constant pools that were at the end
00062   // of the function.
00063   if (!InConstantPool)
00064     return;
00065   InConstantPool = false;
00066   OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
00067 }
00068 
00069 void ARMAsmPrinter::EmitFunctionEntryLabel() {
00070   if (AFI->isThumbFunction()) {
00071     OutStreamer.EmitAssemblerFlag(MCAF_Code16);
00072     OutStreamer.EmitThumbFunc(CurrentFnSym);
00073   }
00074 
00075   OutStreamer.EmitLabel(CurrentFnSym);
00076 }
00077 
00078 void ARMAsmPrinter::EmitXXStructor(const Constant *CV) {
00079   uint64_t Size =
00080       TM.getSubtargetImpl()->getDataLayout()->getTypeAllocSize(CV->getType());
00081   assert(Size && "C++ constructor pointer had zero size!");
00082 
00083   const GlobalValue *GV = dyn_cast<GlobalValue>(CV->stripPointerCasts());
00084   assert(GV && "C++ constructor pointer was not a GlobalValue!");
00085 
00086   const MCExpr *E = MCSymbolRefExpr::Create(GetARMGVSymbol(GV,
00087                                                            ARMII::MO_NO_FLAG),
00088                                             (Subtarget->isTargetELF()
00089                                              ? MCSymbolRefExpr::VK_ARM_TARGET1
00090                                              : MCSymbolRefExpr::VK_None),
00091                                             OutContext);
00092 
00093   OutStreamer.EmitValue(E, Size);
00094 }
00095 
00096 /// runOnMachineFunction - This uses the EmitInstruction()
00097 /// method to print assembly for each instruction.
00098 ///
00099 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
00100   AFI = MF.getInfo<ARMFunctionInfo>();
00101   MCP = MF.getConstantPool();
00102 
00103   SetupMachineFunction(MF);
00104 
00105   if (Subtarget->isTargetCOFF()) {
00106     bool Internal = MF.getFunction()->hasInternalLinkage();
00107     COFF::SymbolStorageClass Scl = Internal ? COFF::IMAGE_SYM_CLASS_STATIC
00108                                             : COFF::IMAGE_SYM_CLASS_EXTERNAL;
00109     int Type = COFF::IMAGE_SYM_DTYPE_FUNCTION << COFF::SCT_COMPLEX_TYPE_SHIFT;
00110 
00111     OutStreamer.BeginCOFFSymbolDef(CurrentFnSym);
00112     OutStreamer.EmitCOFFSymbolStorageClass(Scl);
00113     OutStreamer.EmitCOFFSymbolType(Type);
00114     OutStreamer.EndCOFFSymbolDef();
00115   }
00116 
00117   // Have common code print out the function header with linkage info etc.
00118   EmitFunctionHeader();
00119 
00120   // Emit the rest of the function body.
00121   EmitFunctionBody();
00122 
00123   // We didn't modify anything.
00124   return false;
00125 }
00126 
00127 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
00128                                  raw_ostream &O, const char *Modifier) {
00129   const MachineOperand &MO = MI->getOperand(OpNum);
00130   unsigned TF = MO.getTargetFlags();
00131 
00132   switch (MO.getType()) {
00133   default: llvm_unreachable("<unknown operand type>");
00134   case MachineOperand::MO_Register: {
00135     unsigned Reg = MO.getReg();
00136     assert(TargetRegisterInfo::isPhysicalRegister(Reg));
00137     assert(!MO.getSubReg() && "Subregs should be eliminated!");
00138     if(ARM::GPRPairRegClass.contains(Reg)) {
00139       const MachineFunction &MF = *MI->getParent()->getParent();
00140       const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
00141       Reg = TRI->getSubReg(Reg, ARM::gsub_0);
00142     }
00143     O << ARMInstPrinter::getRegisterName(Reg);
00144     break;
00145   }
00146   case MachineOperand::MO_Immediate: {
00147     int64_t Imm = MO.getImm();
00148     O << '#';
00149     if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
00150         (TF == ARMII::MO_LO16))
00151       O << ":lower16:";
00152     else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
00153              (TF == ARMII::MO_HI16))
00154       O << ":upper16:";
00155     O << Imm;
00156     break;
00157   }
00158   case MachineOperand::MO_MachineBasicBlock:
00159     O << *MO.getMBB()->getSymbol();
00160     return;
00161   case MachineOperand::MO_GlobalAddress: {
00162     const GlobalValue *GV = MO.getGlobal();
00163     if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
00164         (TF & ARMII::MO_LO16))
00165       O << ":lower16:";
00166     else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
00167              (TF & ARMII::MO_HI16))
00168       O << ":upper16:";
00169     O << *GetARMGVSymbol(GV, TF);
00170 
00171     printOffset(MO.getOffset(), O);
00172     if (TF == ARMII::MO_PLT)
00173       O << "(PLT)";
00174     break;
00175   }
00176   case MachineOperand::MO_ConstantPoolIndex:
00177     O << *GetCPISymbol(MO.getIndex());
00178     break;
00179   }
00180 }
00181 
00182 //===--------------------------------------------------------------------===//
00183 
00184 MCSymbol *ARMAsmPrinter::
00185 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
00186   const DataLayout *DL = TM.getSubtargetImpl()->getDataLayout();
00187   SmallString<60> Name;
00188   raw_svector_ostream(Name) << DL->getPrivateGlobalPrefix() << "JTI"
00189     << getFunctionNumber() << '_' << uid << '_' << uid2;
00190   return OutContext.GetOrCreateSymbol(Name.str());
00191 }
00192 
00193 
00194 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel() const {
00195   const DataLayout *DL = TM.getSubtargetImpl()->getDataLayout();
00196   SmallString<60> Name;
00197   raw_svector_ostream(Name) << DL->getPrivateGlobalPrefix() << "SJLJEH"
00198     << getFunctionNumber();
00199   return OutContext.GetOrCreateSymbol(Name.str());
00200 }
00201 
00202 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
00203                                     unsigned AsmVariant, const char *ExtraCode,
00204                                     raw_ostream &O) {
00205   // Does this asm operand have a single letter operand modifier?
00206   if (ExtraCode && ExtraCode[0]) {
00207     if (ExtraCode[1] != 0) return true; // Unknown modifier.
00208 
00209     switch (ExtraCode[0]) {
00210     default:
00211       // See if this is a generic print operand
00212       return AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O);
00213     case 'a': // Print as a memory address.
00214       if (MI->getOperand(OpNum).isReg()) {
00215         O << "["
00216           << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
00217           << "]";
00218         return false;
00219       }
00220       // Fallthrough
00221     case 'c': // Don't print "#" before an immediate operand.
00222       if (!MI->getOperand(OpNum).isImm())
00223         return true;
00224       O << MI->getOperand(OpNum).getImm();
00225       return false;
00226     case 'P': // Print a VFP double precision register.
00227     case 'q': // Print a NEON quad precision register.
00228       printOperand(MI, OpNum, O);
00229       return false;
00230     case 'y': // Print a VFP single precision register as indexed double.
00231       if (MI->getOperand(OpNum).isReg()) {
00232         unsigned Reg = MI->getOperand(OpNum).getReg();
00233         const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
00234         // Find the 'd' register that has this 's' register as a sub-register,
00235         // and determine the lane number.
00236         for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
00237           if (!ARM::DPRRegClass.contains(*SR))
00238             continue;
00239           bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
00240           O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");
00241           return false;
00242         }
00243       }
00244       return true;
00245     case 'B': // Bitwise inverse of integer or symbol without a preceding #.
00246       if (!MI->getOperand(OpNum).isImm())
00247         return true;
00248       O << ~(MI->getOperand(OpNum).getImm());
00249       return false;
00250     case 'L': // The low 16 bits of an immediate constant.
00251       if (!MI->getOperand(OpNum).isImm())
00252         return true;
00253       O << (MI->getOperand(OpNum).getImm() & 0xffff);
00254       return false;
00255     case 'M': { // A register range suitable for LDM/STM.
00256       if (!MI->getOperand(OpNum).isReg())
00257         return true;
00258       const MachineOperand &MO = MI->getOperand(OpNum);
00259       unsigned RegBegin = MO.getReg();
00260       // This takes advantage of the 2 operand-ness of ldm/stm and that we've
00261       // already got the operands in registers that are operands to the
00262       // inline asm statement.
00263       O << "{";
00264       if (ARM::GPRPairRegClass.contains(RegBegin)) {
00265         const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
00266         unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
00267         O << ARMInstPrinter::getRegisterName(Reg0) << ", ";
00268         RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1);
00269       }
00270       O << ARMInstPrinter::getRegisterName(RegBegin);
00271 
00272       // FIXME: The register allocator not only may not have given us the
00273       // registers in sequence, but may not be in ascending registers. This
00274       // will require changes in the register allocator that'll need to be
00275       // propagated down here if the operands change.
00276       unsigned RegOps = OpNum + 1;
00277       while (MI->getOperand(RegOps).isReg()) {
00278         O << ", "
00279           << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
00280         RegOps++;
00281       }
00282 
00283       O << "}";
00284 
00285       return false;
00286     }
00287     case 'R': // The most significant register of a pair.
00288     case 'Q': { // The least significant register of a pair.
00289       if (OpNum == 0)
00290         return true;
00291       const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
00292       if (!FlagsOP.isImm())
00293         return true;
00294       unsigned Flags = FlagsOP.getImm();
00295 
00296       // This operand may not be the one that actually provides the register. If
00297       // it's tied to a previous one then we should refer instead to that one
00298       // for registers and their classes.
00299       unsigned TiedIdx;
00300       if (InlineAsm::isUseOperandTiedToDef(Flags, TiedIdx)) {
00301         for (OpNum = InlineAsm::MIOp_FirstOperand; TiedIdx; --TiedIdx) {
00302           unsigned OpFlags = MI->getOperand(OpNum).getImm();
00303           OpNum += InlineAsm::getNumOperandRegisters(OpFlags) + 1;
00304         }
00305         Flags = MI->getOperand(OpNum).getImm();
00306 
00307         // Later code expects OpNum to be pointing at the register rather than
00308         // the flags.
00309         OpNum += 1;
00310       }
00311 
00312       unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
00313       unsigned RC;
00314       InlineAsm::hasRegClassConstraint(Flags, RC);
00315       if (RC == ARM::GPRPairRegClassID) {
00316         if (NumVals != 1)
00317           return true;
00318         const MachineOperand &MO = MI->getOperand(OpNum);
00319         if (!MO.isReg())
00320           return true;
00321         const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
00322         unsigned Reg = TRI->getSubReg(MO.getReg(), ExtraCode[0] == 'Q' ?
00323             ARM::gsub_0 : ARM::gsub_1);
00324         O << ARMInstPrinter::getRegisterName(Reg);
00325         return false;
00326       }
00327       if (NumVals != 2)
00328         return true;
00329       unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
00330       if (RegOp >= MI->getNumOperands())
00331         return true;
00332       const MachineOperand &MO = MI->getOperand(RegOp);
00333       if (!MO.isReg())
00334         return true;
00335       unsigned Reg = MO.getReg();
00336       O << ARMInstPrinter::getRegisterName(Reg);
00337       return false;
00338     }
00339 
00340     case 'e': // The low doubleword register of a NEON quad register.
00341     case 'f': { // The high doubleword register of a NEON quad register.
00342       if (!MI->getOperand(OpNum).isReg())
00343         return true;
00344       unsigned Reg = MI->getOperand(OpNum).getReg();
00345       if (!ARM::QPRRegClass.contains(Reg))
00346         return true;
00347       const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
00348       unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
00349                                        ARM::dsub_0 : ARM::dsub_1);
00350       O << ARMInstPrinter::getRegisterName(SubReg);
00351       return false;
00352     }
00353 
00354     // This modifier is not yet supported.
00355     case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
00356       return true;
00357     case 'H': { // The highest-numbered register of a pair.
00358       const MachineOperand &MO = MI->getOperand(OpNum);
00359       if (!MO.isReg())
00360         return true;
00361       const MachineFunction &MF = *MI->getParent()->getParent();
00362       const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
00363       unsigned Reg = MO.getReg();
00364       if(!ARM::GPRPairRegClass.contains(Reg))
00365         return false;
00366       Reg = TRI->getSubReg(Reg, ARM::gsub_1);
00367       O << ARMInstPrinter::getRegisterName(Reg);
00368       return false;
00369     }
00370     }
00371   }
00372 
00373   printOperand(MI, OpNum, O);
00374   return false;
00375 }
00376 
00377 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
00378                                           unsigned OpNum, unsigned AsmVariant,
00379                                           const char *ExtraCode,
00380                                           raw_ostream &O) {
00381   // Does this asm operand have a single letter operand modifier?
00382   if (ExtraCode && ExtraCode[0]) {
00383     if (ExtraCode[1] != 0) return true; // Unknown modifier.
00384 
00385     switch (ExtraCode[0]) {
00386       case 'A': // A memory operand for a VLD1/VST1 instruction.
00387       default: return true;  // Unknown modifier.
00388       case 'm': // The base register of a memory operand.
00389         if (!MI->getOperand(OpNum).isReg())
00390           return true;
00391         O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
00392         return false;
00393     }
00394   }
00395 
00396   const MachineOperand &MO = MI->getOperand(OpNum);
00397   assert(MO.isReg() && "unexpected inline asm memory operand");
00398   O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
00399   return false;
00400 }
00401 
00402 static bool isThumb(const MCSubtargetInfo& STI) {
00403   return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
00404 }
00405 
00406 void ARMAsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo &StartInfo,
00407                                      const MCSubtargetInfo *EndInfo) const {
00408   // If either end mode is unknown (EndInfo == NULL) or different than
00409   // the start mode, then restore the start mode.
00410   const bool WasThumb = isThumb(StartInfo);
00411   if (!EndInfo || WasThumb != isThumb(*EndInfo)) {
00412     OutStreamer.EmitAssemblerFlag(WasThumb ? MCAF_Code16 : MCAF_Code32);
00413   }
00414 }
00415 
00416 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
00417   if (Subtarget->isTargetMachO()) {
00418     Reloc::Model RelocM = TM.getRelocationModel();
00419     if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
00420       // Declare all the text sections up front (before the DWARF sections
00421       // emitted by AsmPrinter::doInitialization) so the assembler will keep
00422       // them together at the beginning of the object file.  This helps
00423       // avoid out-of-range branches that are due a fundamental limitation of
00424       // the way symbol offsets are encoded with the current Darwin ARM
00425       // relocations.
00426       const TargetLoweringObjectFileMachO &TLOFMacho =
00427         static_cast<const TargetLoweringObjectFileMachO &>(
00428           getObjFileLowering());
00429 
00430       // Collect the set of sections our functions will go into.
00431       SetVector<const MCSection *, SmallVector<const MCSection *, 8>,
00432         SmallPtrSet<const MCSection *, 8> > TextSections;
00433       // Default text section comes first.
00434       TextSections.insert(TLOFMacho.getTextSection());
00435       // Now any user defined text sections from function attributes.
00436       for (Module::iterator F = M.begin(), e = M.end(); F != e; ++F)
00437         if (!F->isDeclaration() && !F->hasAvailableExternallyLinkage())
00438           TextSections.insert(TLOFMacho.SectionForGlobal(F, *Mang, TM));
00439       // Now the coalescable sections.
00440       TextSections.insert(TLOFMacho.getTextCoalSection());
00441       TextSections.insert(TLOFMacho.getConstTextCoalSection());
00442 
00443       // Emit the sections in the .s file header to fix the order.
00444       for (unsigned i = 0, e = TextSections.size(); i != e; ++i)
00445         OutStreamer.SwitchSection(TextSections[i]);
00446 
00447       if (RelocM == Reloc::DynamicNoPIC) {
00448         const MCSection *sect =
00449           OutContext.getMachOSection("__TEXT", "__symbol_stub4",
00450                                      MachO::S_SYMBOL_STUBS,
00451                                      12, SectionKind::getText());
00452         OutStreamer.SwitchSection(sect);
00453       } else {
00454         const MCSection *sect =
00455           OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
00456                                      MachO::S_SYMBOL_STUBS,
00457                                      16, SectionKind::getText());
00458         OutStreamer.SwitchSection(sect);
00459       }
00460       const MCSection *StaticInitSect =
00461         OutContext.getMachOSection("__TEXT", "__StaticInit",
00462                                    MachO::S_REGULAR |
00463                                    MachO::S_ATTR_PURE_INSTRUCTIONS,
00464                                    SectionKind::getText());
00465       OutStreamer.SwitchSection(StaticInitSect);
00466     }
00467 
00468     // Compiling with debug info should not affect the code
00469     // generation.  Ensure the cstring section comes before the
00470     // optional __DWARF secion. Otherwise, PC-relative loads would
00471     // have to use different instruction sequences at "-g" in order to
00472     // reach global data in the same object file.
00473     OutStreamer.SwitchSection(getObjFileLowering().getCStringSection());
00474   }
00475 
00476   // Use unified assembler syntax.
00477   OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
00478 
00479   // Emit ARM Build Attributes
00480   if (Subtarget->isTargetELF())
00481     emitAttributes();
00482 
00483   if (!M.getModuleInlineAsm().empty() && Subtarget->isThumb())
00484     OutStreamer.EmitAssemblerFlag(MCAF_Code16);
00485 }
00486 
00487 static void
00488 emitNonLazySymbolPointer(MCStreamer &OutStreamer, MCSymbol *StubLabel,
00489                          MachineModuleInfoImpl::StubValueTy &MCSym) {
00490   // L_foo$stub:
00491   OutStreamer.EmitLabel(StubLabel);
00492   //   .indirect_symbol _foo
00493   OutStreamer.EmitSymbolAttribute(MCSym.getPointer(), MCSA_IndirectSymbol);
00494 
00495   if (MCSym.getInt())
00496     // External to current translation unit.
00497     OutStreamer.EmitIntValue(0, 4/*size*/);
00498   else
00499     // Internal to current translation unit.
00500     //
00501     // When we place the LSDA into the TEXT section, the type info
00502     // pointers need to be indirect and pc-rel. We accomplish this by
00503     // using NLPs; however, sometimes the types are local to the file.
00504     // We need to fill in the value for the NLP in those cases.
00505     OutStreamer.EmitValue(
00506         MCSymbolRefExpr::Create(MCSym.getPointer(), OutStreamer.getContext()),
00507         4 /*size*/);
00508 }
00509 
00510 
00511 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
00512   if (Subtarget->isTargetMachO()) {
00513     // All darwin targets use mach-o.
00514     const TargetLoweringObjectFileMachO &TLOFMacho =
00515       static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
00516     MachineModuleInfoMachO &MMIMacho =
00517       MMI->getObjFileInfo<MachineModuleInfoMachO>();
00518 
00519     // Output non-lazy-pointers for external and common global variables.
00520     MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
00521 
00522     if (!Stubs.empty()) {
00523       // Switch with ".non_lazy_symbol_pointer" directive.
00524       OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
00525       EmitAlignment(2);
00526 
00527       for (auto &Stub : Stubs)
00528         emitNonLazySymbolPointer(OutStreamer, Stub.first, Stub.second);
00529 
00530       Stubs.clear();
00531       OutStreamer.AddBlankLine();
00532     }
00533 
00534     Stubs = MMIMacho.GetHiddenGVStubList();
00535     if (!Stubs.empty()) {
00536       OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
00537       EmitAlignment(2);
00538 
00539       for (auto &Stub : Stubs)
00540         emitNonLazySymbolPointer(OutStreamer, Stub.first, Stub.second);
00541 
00542       Stubs.clear();
00543       OutStreamer.AddBlankLine();
00544     }
00545 
00546     // Funny Darwin hack: This flag tells the linker that no global symbols
00547     // contain code that falls through to other global symbols (e.g. the obvious
00548     // implementation of multiple entry points).  If this doesn't occur, the
00549     // linker can safely perform dead code stripping.  Since LLVM never
00550     // generates code that does this, it is always safe to set.
00551     OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
00552   }
00553 
00554   // Emit a .data.rel section containing any stubs that were created.
00555   if (Subtarget->isTargetELF()) {
00556     const TargetLoweringObjectFileELF &TLOFELF =
00557       static_cast<const TargetLoweringObjectFileELF &>(getObjFileLowering());
00558 
00559     MachineModuleInfoELF &MMIELF = MMI->getObjFileInfo<MachineModuleInfoELF>();
00560 
00561     // Output stubs for external and common global variables.
00562     MachineModuleInfoELF::SymbolListTy Stubs = MMIELF.GetGVStubList();
00563     if (!Stubs.empty()) {
00564       OutStreamer.SwitchSection(TLOFELF.getDataRelSection());
00565       const DataLayout *TD = TM.getSubtargetImpl()->getDataLayout();
00566 
00567       for (auto &stub: Stubs) {
00568         OutStreamer.EmitLabel(stub.first);
00569         OutStreamer.EmitSymbolValue(stub.second.getPointer(),
00570                                     TD->getPointerSize(0));
00571       }
00572       Stubs.clear();
00573     }
00574   }
00575 }
00576 
00577 //===----------------------------------------------------------------------===//
00578 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
00579 // FIXME:
00580 // The following seem like one-off assembler flags, but they actually need
00581 // to appear in the .ARM.attributes section in ELF.
00582 // Instead of subclassing the MCELFStreamer, we do the work here.
00583 
00584 static ARMBuildAttrs::CPUArch getArchForCPU(StringRef CPU,
00585                                             const ARMSubtarget *Subtarget) {
00586   if (CPU == "xscale")
00587     return ARMBuildAttrs::v5TEJ;
00588 
00589   if (Subtarget->hasV8Ops())
00590     return ARMBuildAttrs::v8;
00591   else if (Subtarget->hasV7Ops()) {
00592     if (Subtarget->isMClass() && Subtarget->hasThumb2DSP())
00593       return ARMBuildAttrs::v7E_M;
00594     return ARMBuildAttrs::v7;
00595   } else if (Subtarget->hasV6T2Ops())
00596     return ARMBuildAttrs::v6T2;
00597   else if (Subtarget->hasV6MOps())
00598     return ARMBuildAttrs::v6S_M;
00599   else if (Subtarget->hasV6Ops())
00600     return ARMBuildAttrs::v6;
00601   else if (Subtarget->hasV5TEOps())
00602     return ARMBuildAttrs::v5TE;
00603   else if (Subtarget->hasV5TOps())
00604     return ARMBuildAttrs::v5T;
00605   else if (Subtarget->hasV4TOps())
00606     return ARMBuildAttrs::v4T;
00607   else
00608     return ARMBuildAttrs::v4;
00609 }
00610 
00611 void ARMAsmPrinter::emitAttributes() {
00612   MCTargetStreamer &TS = *OutStreamer.getTargetStreamer();
00613   ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
00614 
00615   ATS.switchVendor("aeabi");
00616 
00617   std::string CPUString = Subtarget->getCPUString();
00618 
00619   // FIXME: remove krait check when GNU tools support krait cpu
00620   if (CPUString != "generic" && CPUString != "krait")
00621     ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, CPUString);
00622 
00623   ATS.emitAttribute(ARMBuildAttrs::CPU_arch,
00624                     getArchForCPU(CPUString, Subtarget));
00625 
00626   // Tag_CPU_arch_profile must have the default value of 0 when "Architecture
00627   // profile is not applicable (e.g. pre v7, or cross-profile code)".
00628   if (Subtarget->hasV7Ops()) {
00629     if (Subtarget->isAClass()) {
00630       ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
00631                         ARMBuildAttrs::ApplicationProfile);
00632     } else if (Subtarget->isRClass()) {
00633       ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
00634                         ARMBuildAttrs::RealTimeProfile);
00635     } else if (Subtarget->isMClass()) {
00636       ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
00637                         ARMBuildAttrs::MicroControllerProfile);
00638     }
00639   }
00640 
00641   ATS.emitAttribute(ARMBuildAttrs::ARM_ISA_use, Subtarget->hasARMOps() ?
00642                       ARMBuildAttrs::Allowed : ARMBuildAttrs::Not_Allowed);
00643   if (Subtarget->isThumb1Only()) {
00644     ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
00645                       ARMBuildAttrs::Allowed);
00646   } else if (Subtarget->hasThumb2()) {
00647     ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
00648                       ARMBuildAttrs::AllowThumb32);
00649   }
00650 
00651   if (Subtarget->hasNEON()) {
00652     /* NEON is not exactly a VFP architecture, but GAS emit one of
00653      * neon/neon-fp-armv8/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
00654     if (Subtarget->hasFPARMv8()) {
00655       if (Subtarget->hasCrypto())
00656         ATS.emitFPU(ARM::CRYPTO_NEON_FP_ARMV8);
00657       else
00658         ATS.emitFPU(ARM::NEON_FP_ARMV8);
00659     }
00660     else if (Subtarget->hasVFP4())
00661       ATS.emitFPU(ARM::NEON_VFPV4);
00662     else
00663       ATS.emitFPU(ARM::NEON);
00664     // Emit Tag_Advanced_SIMD_arch for ARMv8 architecture
00665     if (Subtarget->hasV8Ops())
00666       ATS.emitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
00667                         ARMBuildAttrs::AllowNeonARMv8);
00668   } else {
00669     if (Subtarget->hasFPARMv8())
00670       // FPv5 and FP-ARMv8 have the same instructions, so are modeled as one
00671       // FPU, but there are two different names for it depending on the CPU.
00672       ATS.emitFPU(Subtarget->hasD16() ? ARM::FPV5_D16 : ARM::FP_ARMV8);
00673     else if (Subtarget->hasVFP4())
00674       ATS.emitFPU(Subtarget->hasD16() ? ARM::VFPV4_D16 : ARM::VFPV4);
00675     else if (Subtarget->hasVFP3())
00676       ATS.emitFPU(Subtarget->hasD16() ? ARM::VFPV3_D16 : ARM::VFPV3);
00677     else if (Subtarget->hasVFP2())
00678       ATS.emitFPU(ARM::VFPV2);
00679   }
00680 
00681   if (TM.getRelocationModel() == Reloc::PIC_) {
00682     // PIC specific attributes.
00683     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RW_data,
00684                       ARMBuildAttrs::AddressRWPCRel);
00685     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RO_data,
00686                       ARMBuildAttrs::AddressROPCRel);
00687     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_GOT_use,
00688                       ARMBuildAttrs::AddressGOT);
00689   } else {
00690     // Allow direct addressing of imported data for all other relocation models.
00691     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_GOT_use,
00692                       ARMBuildAttrs::AddressDirect);
00693   }
00694 
00695   // Signal various FP modes.
00696   if (!TM.Options.UnsafeFPMath) {
00697     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal, ARMBuildAttrs::Allowed);
00698     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
00699                       ARMBuildAttrs::Allowed);
00700   }
00701 
00702   if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
00703     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
00704                       ARMBuildAttrs::Allowed);
00705   else
00706     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
00707                       ARMBuildAttrs::AllowIEE754);
00708 
00709   if (Subtarget->allowsUnalignedMem())
00710     ATS.emitAttribute(ARMBuildAttrs::CPU_unaligned_access,
00711                       ARMBuildAttrs::Allowed);
00712   else
00713     ATS.emitAttribute(ARMBuildAttrs::CPU_unaligned_access,
00714                       ARMBuildAttrs::Not_Allowed);
00715 
00716   // FIXME: add more flags to ARMBuildAttributes.h
00717   // 8-bytes alignment stuff.
00718   ATS.emitAttribute(ARMBuildAttrs::ABI_align_needed, 1);
00719   ATS.emitAttribute(ARMBuildAttrs::ABI_align_preserved, 1);
00720 
00721   // ABI_HardFP_use attribute to indicate single precision FP.
00722   if (Subtarget->isFPOnlySP())
00723     ATS.emitAttribute(ARMBuildAttrs::ABI_HardFP_use,
00724                       ARMBuildAttrs::HardFPSinglePrecision);
00725 
00726   // Hard float.  Use both S and D registers and conform to AAPCS-VFP.
00727   if (Subtarget->isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard)
00728     ATS.emitAttribute(ARMBuildAttrs::ABI_VFP_args, ARMBuildAttrs::HardFPAAPCS);
00729 
00730   // FIXME: Should we signal R9 usage?
00731 
00732   if (Subtarget->hasFP16())
00733       ATS.emitAttribute(ARMBuildAttrs::FP_HP_extension, ARMBuildAttrs::AllowHPFP);
00734 
00735   if (Subtarget->hasMPExtension())
00736       ATS.emitAttribute(ARMBuildAttrs::MPextension_use, ARMBuildAttrs::AllowMP);
00737 
00738   // Hardware divide in ARM mode is part of base arch, starting from ARMv8.
00739   // If only Thumb hwdiv is present, it must also be in base arch (ARMv7-R/M).
00740   // It is not possible to produce DisallowDIV: if hwdiv is present in the base
00741   // arch, supplying -hwdiv downgrades the effective arch, via ClearImpliedBits.
00742   // AllowDIVExt is only emitted if hwdiv isn't available in the base arch;
00743   // otherwise, the default value (AllowDIVIfExists) applies.
00744   if (Subtarget->hasDivideInARMMode() && !Subtarget->hasV8Ops())
00745       ATS.emitAttribute(ARMBuildAttrs::DIV_use, ARMBuildAttrs::AllowDIVExt);
00746 
00747   if (MMI) {
00748     if (const Module *SourceModule = MMI->getModule()) {
00749       // ABI_PCS_wchar_t to indicate wchar_t width
00750       // FIXME: There is no way to emit value 0 (wchar_t prohibited).
00751       if (auto WCharWidthValue = cast_or_null<ConstantInt>(
00752               SourceModule->getModuleFlag("wchar_size"))) {
00753         int WCharWidth = WCharWidthValue->getZExtValue();
00754         assert((WCharWidth == 2 || WCharWidth == 4) &&
00755                "wchar_t width must be 2 or 4 bytes");
00756         ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_wchar_t, WCharWidth);
00757       }
00758 
00759       // ABI_enum_size to indicate enum width
00760       // FIXME: There is no way to emit value 0 (enums prohibited) or value 3
00761       //        (all enums contain a value needing 32 bits to encode).
00762       if (auto EnumWidthValue = cast_or_null<ConstantInt>(
00763               SourceModule->getModuleFlag("min_enum_size"))) {
00764         int EnumWidth = EnumWidthValue->getZExtValue();
00765         assert((EnumWidth == 1 || EnumWidth == 4) &&
00766                "Minimum enum width must be 1 or 4 bytes");
00767         int EnumBuildAttr = EnumWidth == 1 ? 1 : 2;
00768         ATS.emitAttribute(ARMBuildAttrs::ABI_enum_size, EnumBuildAttr);
00769       }
00770     }
00771   }
00772 
00773   // TODO: We currently only support either reserving the register, or treating
00774   // it as another callee-saved register, but not as SB or a TLS pointer; It
00775   // would instead be nicer to push this from the frontend as metadata, as we do
00776   // for the wchar and enum size tags
00777   if (Subtarget->isR9Reserved())
00778       ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use,
00779                         ARMBuildAttrs::R9Reserved);
00780   else
00781       ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use,
00782                         ARMBuildAttrs::R9IsGPR);
00783 
00784   if (Subtarget->hasTrustZone() && Subtarget->hasVirtualization())
00785       ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
00786                         ARMBuildAttrs::AllowTZVirtualization);
00787   else if (Subtarget->hasTrustZone())
00788       ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
00789                         ARMBuildAttrs::AllowTZ);
00790   else if (Subtarget->hasVirtualization())
00791       ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
00792                         ARMBuildAttrs::AllowVirtualization);
00793 
00794   ATS.finishAttributeSection();
00795 }
00796 
00797 //===----------------------------------------------------------------------===//
00798 
00799 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
00800                              unsigned LabelId, MCContext &Ctx) {
00801 
00802   MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
00803                        + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
00804   return Label;
00805 }
00806 
00807 static MCSymbolRefExpr::VariantKind
00808 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
00809   switch (Modifier) {
00810   case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
00811   case ARMCP::TLSGD:       return MCSymbolRefExpr::VK_TLSGD;
00812   case ARMCP::TPOFF:       return MCSymbolRefExpr::VK_TPOFF;
00813   case ARMCP::GOTTPOFF:    return MCSymbolRefExpr::VK_GOTTPOFF;
00814   case ARMCP::GOT:         return MCSymbolRefExpr::VK_GOT;
00815   case ARMCP::GOTOFF:      return MCSymbolRefExpr::VK_GOTOFF;
00816   }
00817   llvm_unreachable("Invalid ARMCPModifier!");
00818 }
00819 
00820 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV,
00821                                         unsigned char TargetFlags) {
00822   if (Subtarget->isTargetMachO()) {
00823     bool IsIndirect = (TargetFlags & ARMII::MO_NONLAZY) &&
00824       Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
00825 
00826     if (!IsIndirect)
00827       return getSymbol(GV);
00828 
00829     // FIXME: Remove this when Darwin transition to @GOT like syntax.
00830     MCSymbol *MCSym = getSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
00831     MachineModuleInfoMachO &MMIMachO =
00832       MMI->getObjFileInfo<MachineModuleInfoMachO>();
00833     MachineModuleInfoImpl::StubValueTy &StubSym =
00834       GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym)
00835                                 : MMIMachO.getGVStubEntry(MCSym);
00836     if (!StubSym.getPointer())
00837       StubSym = MachineModuleInfoImpl::StubValueTy(getSymbol(GV),
00838                                                    !GV->hasInternalLinkage());
00839     return MCSym;
00840   } else if (Subtarget->isTargetCOFF()) {
00841     assert(Subtarget->isTargetWindows() &&
00842            "Windows is the only supported COFF target");
00843 
00844     bool IsIndirect = (TargetFlags & ARMII::MO_DLLIMPORT);
00845     if (!IsIndirect)
00846       return getSymbol(GV);
00847 
00848     SmallString<128> Name;
00849     Name = "__imp_";
00850     getNameWithPrefix(Name, GV);
00851 
00852     return OutContext.GetOrCreateSymbol(Name);
00853   } else if (Subtarget->isTargetELF()) {
00854     return getSymbol(GV);
00855   }
00856   llvm_unreachable("unexpected target");
00857 }
00858 
00859 void ARMAsmPrinter::
00860 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
00861   const DataLayout *DL = TM.getSubtargetImpl()->getDataLayout();
00862   int Size =
00863       TM.getSubtargetImpl()->getDataLayout()->getTypeAllocSize(MCPV->getType());
00864 
00865   ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
00866 
00867   MCSymbol *MCSym;
00868   if (ACPV->isLSDA()) {
00869     SmallString<128> Str;
00870     raw_svector_ostream OS(Str);
00871     OS << DL->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
00872     MCSym = OutContext.GetOrCreateSymbol(OS.str());
00873   } else if (ACPV->isBlockAddress()) {
00874     const BlockAddress *BA =
00875       cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
00876     MCSym = GetBlockAddressSymbol(BA);
00877   } else if (ACPV->isGlobalValue()) {
00878     const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
00879 
00880     // On Darwin, const-pool entries may get the "FOO$non_lazy_ptr" mangling, so
00881     // flag the global as MO_NONLAZY.
00882     unsigned char TF = Subtarget->isTargetMachO() ? ARMII::MO_NONLAZY : 0;
00883     MCSym = GetARMGVSymbol(GV, TF);
00884   } else if (ACPV->isMachineBasicBlock()) {
00885     const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
00886     MCSym = MBB->getSymbol();
00887   } else {
00888     assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
00889     const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
00890     MCSym = GetExternalSymbolSymbol(Sym);
00891   }
00892 
00893   // Create an MCSymbol for the reference.
00894   const MCExpr *Expr =
00895     MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
00896                             OutContext);
00897 
00898   if (ACPV->getPCAdjustment()) {
00899     MCSymbol *PCLabel = getPICLabel(DL->getPrivateGlobalPrefix(),
00900                                     getFunctionNumber(),
00901                                     ACPV->getLabelId(),
00902                                     OutContext);
00903     const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
00904     PCRelExpr =
00905       MCBinaryExpr::CreateAdd(PCRelExpr,
00906                               MCConstantExpr::Create(ACPV->getPCAdjustment(),
00907                                                      OutContext),
00908                               OutContext);
00909     if (ACPV->mustAddCurrentAddress()) {
00910       // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
00911       // label, so just emit a local label end reference that instead.
00912       MCSymbol *DotSym = OutContext.CreateTempSymbol();
00913       OutStreamer.EmitLabel(DotSym);
00914       const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
00915       PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
00916     }
00917     Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
00918   }
00919   OutStreamer.EmitValue(Expr, Size);
00920 }
00921 
00922 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
00923   unsigned Opcode = MI->getOpcode();
00924   int OpNum = 1;
00925   if (Opcode == ARM::BR_JTadd)
00926     OpNum = 2;
00927   else if (Opcode == ARM::BR_JTm)
00928     OpNum = 3;
00929 
00930   const MachineOperand &MO1 = MI->getOperand(OpNum);
00931   const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
00932   unsigned JTI = MO1.getIndex();
00933 
00934   // Emit a label for the jump table.
00935   MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
00936   OutStreamer.EmitLabel(JTISymbol);
00937 
00938   // Mark the jump table as data-in-code.
00939   OutStreamer.EmitDataRegion(MCDR_DataRegionJT32);
00940 
00941   // Emit each entry of the table.
00942   const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
00943   const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
00944   const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
00945 
00946   for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
00947     MachineBasicBlock *MBB = JTBBs[i];
00948     // Construct an MCExpr for the entry. We want a value of the form:
00949     // (BasicBlockAddr - TableBeginAddr)
00950     //
00951     // For example, a table with entries jumping to basic blocks BB0 and BB1
00952     // would look like:
00953     // LJTI_0_0:
00954     //    .word (LBB0 - LJTI_0_0)
00955     //    .word (LBB1 - LJTI_0_0)
00956     const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
00957 
00958     if (TM.getRelocationModel() == Reloc::PIC_)
00959       Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
00960                                                                    OutContext),
00961                                      OutContext);
00962     // If we're generating a table of Thumb addresses in static relocation
00963     // model, we need to add one to keep interworking correctly.
00964     else if (AFI->isThumbFunction())
00965       Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(1,OutContext),
00966                                      OutContext);
00967     OutStreamer.EmitValue(Expr, 4);
00968   }
00969   // Mark the end of jump table data-in-code region.
00970   OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
00971 }
00972 
00973 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
00974   unsigned Opcode = MI->getOpcode();
00975   int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
00976   const MachineOperand &MO1 = MI->getOperand(OpNum);
00977   const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
00978   unsigned JTI = MO1.getIndex();
00979 
00980   MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
00981   OutStreamer.EmitLabel(JTISymbol);
00982 
00983   // Emit each entry of the table.
00984   const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
00985   const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
00986   const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
00987   unsigned OffsetWidth = 4;
00988   if (MI->getOpcode() == ARM::t2TBB_JT) {
00989     OffsetWidth = 1;
00990     // Mark the jump table as data-in-code.
00991     OutStreamer.EmitDataRegion(MCDR_DataRegionJT8);
00992   } else if (MI->getOpcode() == ARM::t2TBH_JT) {
00993     OffsetWidth = 2;
00994     // Mark the jump table as data-in-code.
00995     OutStreamer.EmitDataRegion(MCDR_DataRegionJT16);
00996   }
00997 
00998   for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
00999     MachineBasicBlock *MBB = JTBBs[i];
01000     const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
01001                                                           OutContext);
01002     // If this isn't a TBB or TBH, the entries are direct branch instructions.
01003     if (OffsetWidth == 4) {
01004       EmitToStreamer(OutStreamer, MCInstBuilder(ARM::t2B)
01005         .addExpr(MBBSymbolExpr)
01006         .addImm(ARMCC::AL)
01007         .addReg(0));
01008       continue;
01009     }
01010     // Otherwise it's an offset from the dispatch instruction. Construct an
01011     // MCExpr for the entry. We want a value of the form:
01012     // (BasicBlockAddr - TableBeginAddr) / 2
01013     //
01014     // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
01015     // would look like:
01016     // LJTI_0_0:
01017     //    .byte (LBB0 - LJTI_0_0) / 2
01018     //    .byte (LBB1 - LJTI_0_0) / 2
01019     const MCExpr *Expr =
01020       MCBinaryExpr::CreateSub(MBBSymbolExpr,
01021                               MCSymbolRefExpr::Create(JTISymbol, OutContext),
01022                               OutContext);
01023     Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
01024                                    OutContext);
01025     OutStreamer.EmitValue(Expr, OffsetWidth);
01026   }
01027   // Mark the end of jump table data-in-code region. 32-bit offsets use
01028   // actual branch instructions here, so we don't mark those as a data-region
01029   // at all.
01030   if (OffsetWidth != 4)
01031     OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
01032 }
01033 
01034 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
01035   assert(MI->getFlag(MachineInstr::FrameSetup) &&
01036       "Only instruction which are involved into frame setup code are allowed");
01037 
01038   MCTargetStreamer &TS = *OutStreamer.getTargetStreamer();
01039   ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
01040   const MachineFunction &MF = *MI->getParent()->getParent();
01041   const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
01042   const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
01043 
01044   unsigned FramePtr = RegInfo->getFrameRegister(MF);
01045   unsigned Opc = MI->getOpcode();
01046   unsigned SrcReg, DstReg;
01047 
01048   if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
01049     // Two special cases:
01050     // 1) tPUSH does not have src/dst regs.
01051     // 2) for Thumb1 code we sometimes materialize the constant via constpool
01052     // load. Yes, this is pretty fragile, but for now I don't see better
01053     // way... :(
01054     SrcReg = DstReg = ARM::SP;
01055   } else {
01056     SrcReg = MI->getOperand(1).getReg();
01057     DstReg = MI->getOperand(0).getReg();
01058   }
01059 
01060   // Try to figure out the unwinding opcode out of src / dst regs.
01061   if (MI->mayStore()) {
01062     // Register saves.
01063     assert(DstReg == ARM::SP &&
01064            "Only stack pointer as a destination reg is supported");
01065 
01066     SmallVector<unsigned, 4> RegList;
01067     // Skip src & dst reg, and pred ops.
01068     unsigned StartOp = 2 + 2;
01069     // Use all the operands.
01070     unsigned NumOffset = 0;
01071 
01072     switch (Opc) {
01073     default:
01074       MI->dump();
01075       llvm_unreachable("Unsupported opcode for unwinding information");
01076     case ARM::tPUSH:
01077       // Special case here: no src & dst reg, but two extra imp ops.
01078       StartOp = 2; NumOffset = 2;
01079     case ARM::STMDB_UPD:
01080     case ARM::t2STMDB_UPD:
01081     case ARM::VSTMDDB_UPD:
01082       assert(SrcReg == ARM::SP &&
01083              "Only stack pointer as a source reg is supported");
01084       for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
01085            i != NumOps; ++i) {
01086         const MachineOperand &MO = MI->getOperand(i);
01087         // Actually, there should never be any impdef stuff here. Skip it
01088         // temporary to workaround PR11902.
01089         if (MO.isImplicit())
01090           continue;
01091         RegList.push_back(MO.getReg());
01092       }
01093       break;
01094     case ARM::STR_PRE_IMM:
01095     case ARM::STR_PRE_REG:
01096     case ARM::t2STR_PRE:
01097       assert(MI->getOperand(2).getReg() == ARM::SP &&
01098              "Only stack pointer as a source reg is supported");
01099       RegList.push_back(SrcReg);
01100       break;
01101     }
01102     if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM)
01103       ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
01104   } else {
01105     // Changes of stack / frame pointer.
01106     if (SrcReg == ARM::SP) {
01107       int64_t Offset = 0;
01108       switch (Opc) {
01109       default:
01110         MI->dump();
01111         llvm_unreachable("Unsupported opcode for unwinding information");
01112       case ARM::MOVr:
01113       case ARM::tMOVr:
01114         Offset = 0;
01115         break;
01116       case ARM::ADDri:
01117         Offset = -MI->getOperand(2).getImm();
01118         break;
01119       case ARM::SUBri:
01120       case ARM::t2SUBri:
01121         Offset = MI->getOperand(2).getImm();
01122         break;
01123       case ARM::tSUBspi:
01124         Offset = MI->getOperand(2).getImm()*4;
01125         break;
01126       case ARM::tADDspi:
01127       case ARM::tADDrSPi:
01128         Offset = -MI->getOperand(2).getImm()*4;
01129         break;
01130       case ARM::tLDRpci: {
01131         // Grab the constpool index and check, whether it corresponds to
01132         // original or cloned constpool entry.
01133         unsigned CPI = MI->getOperand(1).getIndex();
01134         const MachineConstantPool *MCP = MF.getConstantPool();
01135         if (CPI >= MCP->getConstants().size())
01136           CPI = AFI.getOriginalCPIdx(CPI);
01137         assert(CPI != -1U && "Invalid constpool index");
01138 
01139         // Derive the actual offset.
01140         const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
01141         assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
01142         // FIXME: Check for user, it should be "add" instruction!
01143         Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
01144         break;
01145       }
01146       }
01147 
01148       if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM) {
01149         if (DstReg == FramePtr && FramePtr != ARM::SP)
01150           // Set-up of the frame pointer. Positive values correspond to "add"
01151           // instruction.
01152           ATS.emitSetFP(FramePtr, ARM::SP, -Offset);
01153         else if (DstReg == ARM::SP) {
01154           // Change of SP by an offset. Positive values correspond to "sub"
01155           // instruction.
01156           ATS.emitPad(Offset);
01157         } else {
01158           // Move of SP to a register.  Positive values correspond to an "add"
01159           // instruction.
01160           ATS.emitMovSP(DstReg, -Offset);
01161         }
01162       }
01163     } else if (DstReg == ARM::SP) {
01164       MI->dump();
01165       llvm_unreachable("Unsupported opcode for unwinding information");
01166     }
01167     else {
01168       MI->dump();
01169       llvm_unreachable("Unsupported opcode for unwinding information");
01170     }
01171   }
01172 }
01173 
01174 // Simple pseudo-instructions have their lowering (with expansion to real
01175 // instructions) auto-generated.
01176 #include "ARMGenMCPseudoLowering.inc"
01177 
01178 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
01179   const DataLayout *DL = TM.getSubtargetImpl()->getDataLayout();
01180 
01181   // If we just ended a constant pool, mark it as such.
01182   if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
01183     OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
01184     InConstantPool = false;
01185   }
01186 
01187   // Emit unwinding stuff for frame-related instructions
01188   if (Subtarget->isTargetEHABICompatible() &&
01189        MI->getFlag(MachineInstr::FrameSetup))
01190     EmitUnwindingInstruction(MI);
01191 
01192   // Do any auto-generated pseudo lowerings.
01193   if (emitPseudoExpansionLowering(OutStreamer, MI))
01194     return;
01195 
01196   assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
01197          "Pseudo flag setting opcode should be expanded early");
01198 
01199   // Check for manual lowerings.
01200   unsigned Opc = MI->getOpcode();
01201   switch (Opc) {
01202   case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
01203   case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing");
01204   case ARM::LEApcrel:
01205   case ARM::tLEApcrel:
01206   case ARM::t2LEApcrel: {
01207     // FIXME: Need to also handle globals and externals
01208     MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex());
01209     EmitToStreamer(OutStreamer, MCInstBuilder(MI->getOpcode() ==
01210                                               ARM::t2LEApcrel ? ARM::t2ADR
01211                   : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
01212                      : ARM::ADR))
01213       .addReg(MI->getOperand(0).getReg())
01214       .addExpr(MCSymbolRefExpr::Create(CPISymbol, OutContext))
01215       // Add predicate operands.
01216       .addImm(MI->getOperand(2).getImm())
01217       .addReg(MI->getOperand(3).getReg()));
01218     return;
01219   }
01220   case ARM::LEApcrelJT:
01221   case ARM::tLEApcrelJT:
01222   case ARM::t2LEApcrelJT: {
01223     MCSymbol *JTIPICSymbol =
01224       GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
01225                                   MI->getOperand(2).getImm());
01226     EmitToStreamer(OutStreamer, MCInstBuilder(MI->getOpcode() ==
01227                                               ARM::t2LEApcrelJT ? ARM::t2ADR
01228                   : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
01229                      : ARM::ADR))
01230       .addReg(MI->getOperand(0).getReg())
01231       .addExpr(MCSymbolRefExpr::Create(JTIPICSymbol, OutContext))
01232       // Add predicate operands.
01233       .addImm(MI->getOperand(3).getImm())
01234       .addReg(MI->getOperand(4).getReg()));
01235     return;
01236   }
01237   // Darwin call instructions are just normal call instructions with different
01238   // clobber semantics (they clobber R9).
01239   case ARM::BX_CALL: {
01240     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
01241       .addReg(ARM::LR)
01242       .addReg(ARM::PC)
01243       // Add predicate operands.
01244       .addImm(ARMCC::AL)
01245       .addReg(0)
01246       // Add 's' bit operand (always reg0 for this)
01247       .addReg(0));
01248 
01249     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::BX)
01250       .addReg(MI->getOperand(0).getReg()));
01251     return;
01252   }
01253   case ARM::tBX_CALL: {
01254     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
01255       .addReg(ARM::LR)
01256       .addReg(ARM::PC)
01257       // Add predicate operands.
01258       .addImm(ARMCC::AL)
01259       .addReg(0));
01260 
01261     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tBX)
01262       .addReg(MI->getOperand(0).getReg())
01263       // Add predicate operands.
01264       .addImm(ARMCC::AL)
01265       .addReg(0));
01266     return;
01267   }
01268   case ARM::BMOVPCRX_CALL: {
01269     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
01270       .addReg(ARM::LR)
01271       .addReg(ARM::PC)
01272       // Add predicate operands.
01273       .addImm(ARMCC::AL)
01274       .addReg(0)
01275       // Add 's' bit operand (always reg0 for this)
01276       .addReg(0));
01277 
01278     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
01279       .addReg(ARM::PC)
01280       .addReg(MI->getOperand(0).getReg())
01281       // Add predicate operands.
01282       .addImm(ARMCC::AL)
01283       .addReg(0)
01284       // Add 's' bit operand (always reg0 for this)
01285       .addReg(0));
01286     return;
01287   }
01288   case ARM::BMOVPCB_CALL: {
01289     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
01290       .addReg(ARM::LR)
01291       .addReg(ARM::PC)
01292       // Add predicate operands.
01293       .addImm(ARMCC::AL)
01294       .addReg(0)
01295       // Add 's' bit operand (always reg0 for this)
01296       .addReg(0));
01297 
01298     const MachineOperand &Op = MI->getOperand(0);
01299     const GlobalValue *GV = Op.getGlobal();
01300     const unsigned TF = Op.getTargetFlags();
01301     MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
01302     const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
01303     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::Bcc)
01304       .addExpr(GVSymExpr)
01305       // Add predicate operands.
01306       .addImm(ARMCC::AL)
01307       .addReg(0));
01308     return;
01309   }
01310   case ARM::MOVi16_ga_pcrel:
01311   case ARM::t2MOVi16_ga_pcrel: {
01312     MCInst TmpInst;
01313     TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
01314     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
01315 
01316     unsigned TF = MI->getOperand(1).getTargetFlags();
01317     const GlobalValue *GV = MI->getOperand(1).getGlobal();
01318     MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
01319     const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
01320 
01321     MCSymbol *LabelSym = getPICLabel(DL->getPrivateGlobalPrefix(),
01322                                      getFunctionNumber(),
01323                                      MI->getOperand(2).getImm(), OutContext);
01324     const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
01325     unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
01326     const MCExpr *PCRelExpr =
01327       ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
01328                                       MCBinaryExpr::CreateAdd(LabelSymExpr,
01329                                       MCConstantExpr::Create(PCAdj, OutContext),
01330                                       OutContext), OutContext), OutContext);
01331       TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
01332 
01333     // Add predicate operands.
01334     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
01335     TmpInst.addOperand(MCOperand::CreateReg(0));
01336     // Add 's' bit operand (always reg0 for this)
01337     TmpInst.addOperand(MCOperand::CreateReg(0));
01338     EmitToStreamer(OutStreamer, TmpInst);
01339     return;
01340   }
01341   case ARM::MOVTi16_ga_pcrel:
01342   case ARM::t2MOVTi16_ga_pcrel: {
01343     MCInst TmpInst;
01344     TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
01345                       ? ARM::MOVTi16 : ARM::t2MOVTi16);
01346     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
01347     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
01348 
01349     unsigned TF = MI->getOperand(2).getTargetFlags();
01350     const GlobalValue *GV = MI->getOperand(2).getGlobal();
01351     MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
01352     const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
01353 
01354     MCSymbol *LabelSym = getPICLabel(DL->getPrivateGlobalPrefix(),
01355                                      getFunctionNumber(),
01356                                      MI->getOperand(3).getImm(), OutContext);
01357     const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
01358     unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
01359     const MCExpr *PCRelExpr =
01360         ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
01361                                    MCBinaryExpr::CreateAdd(LabelSymExpr,
01362                                       MCConstantExpr::Create(PCAdj, OutContext),
01363                                           OutContext), OutContext), OutContext);
01364       TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
01365     // Add predicate operands.
01366     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
01367     TmpInst.addOperand(MCOperand::CreateReg(0));
01368     // Add 's' bit operand (always reg0 for this)
01369     TmpInst.addOperand(MCOperand::CreateReg(0));
01370     EmitToStreamer(OutStreamer, TmpInst);
01371     return;
01372   }
01373   case ARM::tPICADD: {
01374     // This is a pseudo op for a label + instruction sequence, which looks like:
01375     // LPC0:
01376     //     add r0, pc
01377     // This adds the address of LPC0 to r0.
01378 
01379     // Emit the label.
01380     OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
01381                           getFunctionNumber(), MI->getOperand(2).getImm(),
01382                           OutContext));
01383 
01384     // Form and emit the add.
01385     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tADDhirr)
01386       .addReg(MI->getOperand(0).getReg())
01387       .addReg(MI->getOperand(0).getReg())
01388       .addReg(ARM::PC)
01389       // Add predicate operands.
01390       .addImm(ARMCC::AL)
01391       .addReg(0));
01392     return;
01393   }
01394   case ARM::PICADD: {
01395     // This is a pseudo op for a label + instruction sequence, which looks like:
01396     // LPC0:
01397     //     add r0, pc, r0
01398     // This adds the address of LPC0 to r0.
01399 
01400     // Emit the label.
01401     OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
01402                           getFunctionNumber(), MI->getOperand(2).getImm(),
01403                           OutContext));
01404 
01405     // Form and emit the add.
01406     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDrr)
01407       .addReg(MI->getOperand(0).getReg())
01408       .addReg(ARM::PC)
01409       .addReg(MI->getOperand(1).getReg())
01410       // Add predicate operands.
01411       .addImm(MI->getOperand(3).getImm())
01412       .addReg(MI->getOperand(4).getReg())
01413       // Add 's' bit operand (always reg0 for this)
01414       .addReg(0));
01415     return;
01416   }
01417   case ARM::PICSTR:
01418   case ARM::PICSTRB:
01419   case ARM::PICSTRH:
01420   case ARM::PICLDR:
01421   case ARM::PICLDRB:
01422   case ARM::PICLDRH:
01423   case ARM::PICLDRSB:
01424   case ARM::PICLDRSH: {
01425     // This is a pseudo op for a label + instruction sequence, which looks like:
01426     // LPC0:
01427     //     OP r0, [pc, r0]
01428     // The LCP0 label is referenced by a constant pool entry in order to get
01429     // a PC-relative address at the ldr instruction.
01430 
01431     // Emit the label.
01432     OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
01433                           getFunctionNumber(), MI->getOperand(2).getImm(),
01434                           OutContext));
01435 
01436     // Form and emit the load
01437     unsigned Opcode;
01438     switch (MI->getOpcode()) {
01439     default:
01440       llvm_unreachable("Unexpected opcode!");
01441     case ARM::PICSTR:   Opcode = ARM::STRrs; break;
01442     case ARM::PICSTRB:  Opcode = ARM::STRBrs; break;
01443     case ARM::PICSTRH:  Opcode = ARM::STRH; break;
01444     case ARM::PICLDR:   Opcode = ARM::LDRrs; break;
01445     case ARM::PICLDRB:  Opcode = ARM::LDRBrs; break;
01446     case ARM::PICLDRH:  Opcode = ARM::LDRH; break;
01447     case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
01448     case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
01449     }
01450     EmitToStreamer(OutStreamer, MCInstBuilder(Opcode)
01451       .addReg(MI->getOperand(0).getReg())
01452       .addReg(ARM::PC)
01453       .addReg(MI->getOperand(1).getReg())
01454       .addImm(0)
01455       // Add predicate operands.
01456       .addImm(MI->getOperand(3).getImm())
01457       .addReg(MI->getOperand(4).getReg()));
01458 
01459     return;
01460   }
01461   case ARM::CONSTPOOL_ENTRY: {
01462     /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
01463     /// in the function.  The first operand is the ID# for this instruction, the
01464     /// second is the index into the MachineConstantPool that this is, the third
01465     /// is the size in bytes of this constant pool entry.
01466     /// The required alignment is specified on the basic block holding this MI.
01467     unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
01468     unsigned CPIdx   = (unsigned)MI->getOperand(1).getIndex();
01469 
01470     // If this is the first entry of the pool, mark it.
01471     if (!InConstantPool) {
01472       OutStreamer.EmitDataRegion(MCDR_DataRegion);
01473       InConstantPool = true;
01474     }
01475 
01476     OutStreamer.EmitLabel(GetCPISymbol(LabelId));
01477 
01478     const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
01479     if (MCPE.isMachineConstantPoolEntry())
01480       EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
01481     else
01482       EmitGlobalConstant(MCPE.Val.ConstVal);
01483     return;
01484   }
01485   case ARM::t2BR_JT: {
01486     // Lower and emit the instruction itself, then the jump table following it.
01487     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
01488       .addReg(ARM::PC)
01489       .addReg(MI->getOperand(0).getReg())
01490       // Add predicate operands.
01491       .addImm(ARMCC::AL)
01492       .addReg(0));
01493 
01494     // Output the data for the jump table itself
01495     EmitJump2Table(MI);
01496     return;
01497   }
01498   case ARM::t2TBB_JT: {
01499     // Lower and emit the instruction itself, then the jump table following it.
01500     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::t2TBB)
01501       .addReg(ARM::PC)
01502       .addReg(MI->getOperand(0).getReg())
01503       // Add predicate operands.
01504       .addImm(ARMCC::AL)
01505       .addReg(0));
01506 
01507     // Output the data for the jump table itself
01508     EmitJump2Table(MI);
01509     // Make sure the next instruction is 2-byte aligned.
01510     EmitAlignment(1);
01511     return;
01512   }
01513   case ARM::t2TBH_JT: {
01514     // Lower and emit the instruction itself, then the jump table following it.
01515     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::t2TBH)
01516       .addReg(ARM::PC)
01517       .addReg(MI->getOperand(0).getReg())
01518       // Add predicate operands.
01519       .addImm(ARMCC::AL)
01520       .addReg(0));
01521 
01522     // Output the data for the jump table itself
01523     EmitJump2Table(MI);
01524     return;
01525   }
01526   case ARM::tBR_JTr:
01527   case ARM::BR_JTr: {
01528     // Lower and emit the instruction itself, then the jump table following it.
01529     // mov pc, target
01530     MCInst TmpInst;
01531     unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
01532       ARM::MOVr : ARM::tMOVr;
01533     TmpInst.setOpcode(Opc);
01534     TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
01535     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
01536     // Add predicate operands.
01537     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
01538     TmpInst.addOperand(MCOperand::CreateReg(0));
01539     // Add 's' bit operand (always reg0 for this)
01540     if (Opc == ARM::MOVr)
01541       TmpInst.addOperand(MCOperand::CreateReg(0));
01542     EmitToStreamer(OutStreamer, TmpInst);
01543 
01544     // Make sure the Thumb jump table is 4-byte aligned.
01545     if (Opc == ARM::tMOVr)
01546       EmitAlignment(2);
01547 
01548     // Output the data for the jump table itself
01549     EmitJumpTable(MI);
01550     return;
01551   }
01552   case ARM::BR_JTm: {
01553     // Lower and emit the instruction itself, then the jump table following it.
01554     // ldr pc, target
01555     MCInst TmpInst;
01556     if (MI->getOperand(1).getReg() == 0) {
01557       // literal offset
01558       TmpInst.setOpcode(ARM::LDRi12);
01559       TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
01560       TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
01561       TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
01562     } else {
01563       TmpInst.setOpcode(ARM::LDRrs);
01564       TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
01565       TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
01566       TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
01567       TmpInst.addOperand(MCOperand::CreateImm(0));
01568     }
01569     // Add predicate operands.
01570     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
01571     TmpInst.addOperand(MCOperand::CreateReg(0));
01572     EmitToStreamer(OutStreamer, TmpInst);
01573 
01574     // Output the data for the jump table itself
01575     EmitJumpTable(MI);
01576     return;
01577   }
01578   case ARM::BR_JTadd: {
01579     // Lower and emit the instruction itself, then the jump table following it.
01580     // add pc, target, idx
01581     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDrr)
01582       .addReg(ARM::PC)
01583       .addReg(MI->getOperand(0).getReg())
01584       .addReg(MI->getOperand(1).getReg())
01585       // Add predicate operands.
01586       .addImm(ARMCC::AL)
01587       .addReg(0)
01588       // Add 's' bit operand (always reg0 for this)
01589       .addReg(0));
01590 
01591     // Output the data for the jump table itself
01592     EmitJumpTable(MI);
01593     return;
01594   }
01595   case ARM::SPACE:
01596     OutStreamer.EmitZeros(MI->getOperand(1).getImm());
01597     return;
01598   case ARM::TRAP: {
01599     // Non-Darwin binutils don't yet support the "trap" mnemonic.
01600     // FIXME: Remove this special case when they do.
01601     if (!Subtarget->isTargetMachO()) {
01602       //.long 0xe7ffdefe @ trap
01603       uint32_t Val = 0xe7ffdefeUL;
01604       OutStreamer.AddComment("trap");
01605       OutStreamer.EmitIntValue(Val, 4);
01606       return;
01607     }
01608     break;
01609   }
01610   case ARM::TRAPNaCl: {
01611     //.long 0xe7fedef0 @ trap
01612     uint32_t Val = 0xe7fedef0UL;
01613     OutStreamer.AddComment("trap");
01614     OutStreamer.EmitIntValue(Val, 4);
01615     return;
01616   }
01617   case ARM::tTRAP: {
01618     // Non-Darwin binutils don't yet support the "trap" mnemonic.
01619     // FIXME: Remove this special case when they do.
01620     if (!Subtarget->isTargetMachO()) {
01621       //.short 57086 @ trap
01622       uint16_t Val = 0xdefe;
01623       OutStreamer.AddComment("trap");
01624       OutStreamer.EmitIntValue(Val, 2);
01625       return;
01626     }
01627     break;
01628   }
01629   case ARM::t2Int_eh_sjlj_setjmp:
01630   case ARM::t2Int_eh_sjlj_setjmp_nofp:
01631   case ARM::tInt_eh_sjlj_setjmp: {
01632     // Two incoming args: GPR:$src, GPR:$val
01633     // mov $val, pc
01634     // adds $val, #7
01635     // str $val, [$src, #4]
01636     // movs r0, #0
01637     // b 1f
01638     // movs r0, #1
01639     // 1:
01640     unsigned SrcReg = MI->getOperand(0).getReg();
01641     unsigned ValReg = MI->getOperand(1).getReg();
01642     MCSymbol *Label = GetARMSJLJEHLabel();
01643     OutStreamer.AddComment("eh_setjmp begin");
01644     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
01645       .addReg(ValReg)
01646       .addReg(ARM::PC)
01647       // Predicate.
01648       .addImm(ARMCC::AL)
01649       .addReg(0));
01650 
01651     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tADDi3)
01652       .addReg(ValReg)
01653       // 's' bit operand
01654       .addReg(ARM::CPSR)
01655       .addReg(ValReg)
01656       .addImm(7)
01657       // Predicate.
01658       .addImm(ARMCC::AL)
01659       .addReg(0));
01660 
01661     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tSTRi)
01662       .addReg(ValReg)
01663       .addReg(SrcReg)
01664       // The offset immediate is #4. The operand value is scaled by 4 for the
01665       // tSTR instruction.
01666       .addImm(1)
01667       // Predicate.
01668       .addImm(ARMCC::AL)
01669       .addReg(0));
01670 
01671     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVi8)
01672       .addReg(ARM::R0)
01673       .addReg(ARM::CPSR)
01674       .addImm(0)
01675       // Predicate.
01676       .addImm(ARMCC::AL)
01677       .addReg(0));
01678 
01679     const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
01680     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tB)
01681       .addExpr(SymbolExpr)
01682       .addImm(ARMCC::AL)
01683       .addReg(0));
01684 
01685     OutStreamer.AddComment("eh_setjmp end");
01686     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVi8)
01687       .addReg(ARM::R0)
01688       .addReg(ARM::CPSR)
01689       .addImm(1)
01690       // Predicate.
01691       .addImm(ARMCC::AL)
01692       .addReg(0));
01693 
01694     OutStreamer.EmitLabel(Label);
01695     return;
01696   }
01697 
01698   case ARM::Int_eh_sjlj_setjmp_nofp:
01699   case ARM::Int_eh_sjlj_setjmp: {
01700     // Two incoming args: GPR:$src, GPR:$val
01701     // add $val, pc, #8
01702     // str $val, [$src, #+4]
01703     // mov r0, #0
01704     // add pc, pc, #0
01705     // mov r0, #1
01706     unsigned SrcReg = MI->getOperand(0).getReg();
01707     unsigned ValReg = MI->getOperand(1).getReg();
01708 
01709     OutStreamer.AddComment("eh_setjmp begin");
01710     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDri)
01711       .addReg(ValReg)
01712       .addReg(ARM::PC)
01713       .addImm(8)
01714       // Predicate.
01715       .addImm(ARMCC::AL)
01716       .addReg(0)
01717       // 's' bit operand (always reg0 for this).
01718       .addReg(0));
01719 
01720     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::STRi12)
01721       .addReg(ValReg)
01722       .addReg(SrcReg)
01723       .addImm(4)
01724       // Predicate.
01725       .addImm(ARMCC::AL)
01726       .addReg(0));
01727 
01728     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVi)
01729       .addReg(ARM::R0)
01730       .addImm(0)
01731       // Predicate.
01732       .addImm(ARMCC::AL)
01733       .addReg(0)
01734       // 's' bit operand (always reg0 for this).
01735       .addReg(0));
01736 
01737     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDri)
01738       .addReg(ARM::PC)
01739       .addReg(ARM::PC)
01740       .addImm(0)
01741       // Predicate.
01742       .addImm(ARMCC::AL)
01743       .addReg(0)
01744       // 's' bit operand (always reg0 for this).
01745       .addReg(0));
01746 
01747     OutStreamer.AddComment("eh_setjmp end");
01748     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVi)
01749       .addReg(ARM::R0)
01750       .addImm(1)
01751       // Predicate.
01752       .addImm(ARMCC::AL)
01753       .addReg(0)
01754       // 's' bit operand (always reg0 for this).
01755       .addReg(0));
01756     return;
01757   }
01758   case ARM::Int_eh_sjlj_longjmp: {
01759     // ldr sp, [$src, #8]
01760     // ldr $scratch, [$src, #4]
01761     // ldr r7, [$src]
01762     // bx $scratch
01763     unsigned SrcReg = MI->getOperand(0).getReg();
01764     unsigned ScratchReg = MI->getOperand(1).getReg();
01765     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::LDRi12)
01766       .addReg(ARM::SP)
01767       .addReg(SrcReg)
01768       .addImm(8)
01769       // Predicate.
01770       .addImm(ARMCC::AL)
01771       .addReg(0));
01772 
01773     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::LDRi12)
01774       .addReg(ScratchReg)
01775       .addReg(SrcReg)
01776       .addImm(4)
01777       // Predicate.
01778       .addImm(ARMCC::AL)
01779       .addReg(0));
01780 
01781     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::LDRi12)
01782       .addReg(ARM::R7)
01783       .addReg(SrcReg)
01784       .addImm(0)
01785       // Predicate.
01786       .addImm(ARMCC::AL)
01787       .addReg(0));
01788 
01789     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::BX)
01790       .addReg(ScratchReg)
01791       // Predicate.
01792       .addImm(ARMCC::AL)
01793       .addReg(0));
01794     return;
01795   }
01796   case ARM::tInt_eh_sjlj_longjmp: {
01797     // ldr $scratch, [$src, #8]
01798     // mov sp, $scratch
01799     // ldr $scratch, [$src, #4]
01800     // ldr r7, [$src]
01801     // bx $scratch
01802     unsigned SrcReg = MI->getOperand(0).getReg();
01803     unsigned ScratchReg = MI->getOperand(1).getReg();
01804     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tLDRi)
01805       .addReg(ScratchReg)
01806       .addReg(SrcReg)
01807       // The offset immediate is #8. The operand value is scaled by 4 for the
01808       // tLDR instruction.
01809       .addImm(2)
01810       // Predicate.
01811       .addImm(ARMCC::AL)
01812       .addReg(0));
01813 
01814     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
01815       .addReg(ARM::SP)
01816       .addReg(ScratchReg)
01817       // Predicate.
01818       .addImm(ARMCC::AL)
01819       .addReg(0));
01820 
01821     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tLDRi)
01822       .addReg(ScratchReg)
01823       .addReg(SrcReg)
01824       .addImm(1)
01825       // Predicate.
01826       .addImm(ARMCC::AL)
01827       .addReg(0));
01828 
01829     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tLDRi)
01830       .addReg(ARM::R7)
01831       .addReg(SrcReg)
01832       .addImm(0)
01833       // Predicate.
01834       .addImm(ARMCC::AL)
01835       .addReg(0));
01836 
01837     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tBX)
01838       .addReg(ScratchReg)
01839       // Predicate.
01840       .addImm(ARMCC::AL)
01841       .addReg(0));
01842     return;
01843   }
01844   }
01845 
01846   MCInst TmpInst;
01847   LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
01848 
01849   EmitToStreamer(OutStreamer, TmpInst);
01850 }
01851 
01852 //===----------------------------------------------------------------------===//
01853 // Target Registry Stuff
01854 //===----------------------------------------------------------------------===//
01855 
01856 // Force static initialization.
01857 extern "C" void LLVMInitializeARMAsmPrinter() {
01858   RegisterAsmPrinter<ARMAsmPrinter> X(TheARMLETarget);
01859   RegisterAsmPrinter<ARMAsmPrinter> Y(TheARMBETarget);
01860   RegisterAsmPrinter<ARMAsmPrinter> A(TheThumbLETarget);
01861   RegisterAsmPrinter<ARMAsmPrinter> B(TheThumbBETarget);
01862 }