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ARMAsmPrinter.cpp
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00001 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file contains a printer that converts from our internal representation
00011 // of machine-dependent LLVM code to GAS-format ARM assembly language.
00012 //
00013 //===----------------------------------------------------------------------===//
00014 
00015 #include "ARMAsmPrinter.h"
00016 #include "ARM.h"
00017 #include "ARMConstantPoolValue.h"
00018 #include "ARMFPUName.h"
00019 #include "ARMMachineFunctionInfo.h"
00020 #include "ARMTargetMachine.h"
00021 #include "ARMTargetObjectFile.h"
00022 #include "InstPrinter/ARMInstPrinter.h"
00023 #include "MCTargetDesc/ARMAddressingModes.h"
00024 #include "MCTargetDesc/ARMMCExpr.h"
00025 #include "llvm/ADT/SetVector.h"
00026 #include "llvm/ADT/SmallString.h"
00027 #include "llvm/CodeGen/MachineFunctionPass.h"
00028 #include "llvm/CodeGen/MachineJumpTableInfo.h"
00029 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
00030 #include "llvm/IR/Constants.h"
00031 #include "llvm/IR/DataLayout.h"
00032 #include "llvm/IR/DebugInfo.h"
00033 #include "llvm/IR/Mangler.h"
00034 #include "llvm/IR/Module.h"
00035 #include "llvm/IR/Type.h"
00036 #include "llvm/MC/MCAsmInfo.h"
00037 #include "llvm/MC/MCAssembler.h"
00038 #include "llvm/MC/MCContext.h"
00039 #include "llvm/MC/MCELFStreamer.h"
00040 #include "llvm/MC/MCInst.h"
00041 #include "llvm/MC/MCInstBuilder.h"
00042 #include "llvm/MC/MCObjectStreamer.h"
00043 #include "llvm/MC/MCSectionMachO.h"
00044 #include "llvm/MC/MCStreamer.h"
00045 #include "llvm/MC/MCSymbol.h"
00046 #include "llvm/Support/ARMBuildAttributes.h"
00047 #include "llvm/Support/COFF.h"
00048 #include "llvm/Support/CommandLine.h"
00049 #include "llvm/Support/Debug.h"
00050 #include "llvm/Support/ELF.h"
00051 #include "llvm/Support/ErrorHandling.h"
00052 #include "llvm/Support/TargetRegistry.h"
00053 #include "llvm/Support/raw_ostream.h"
00054 #include "llvm/Target/TargetMachine.h"
00055 #include <cctype>
00056 using namespace llvm;
00057 
00058 #define DEBUG_TYPE "asm-printer"
00059 
00060 ARMAsmPrinter::ARMAsmPrinter(TargetMachine &TM,
00061                              std::unique_ptr<MCStreamer> Streamer)
00062     : AsmPrinter(TM, std::move(Streamer)), AFI(nullptr), MCP(nullptr),
00063       InConstantPool(false) {
00064   Subtarget = &TM.getSubtarget<ARMSubtarget>();
00065 }
00066 
00067 void ARMAsmPrinter::EmitFunctionBodyEnd() {
00068   // Make sure to terminate any constant pools that were at the end
00069   // of the function.
00070   if (!InConstantPool)
00071     return;
00072   InConstantPool = false;
00073   OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
00074 }
00075 
00076 void ARMAsmPrinter::EmitFunctionEntryLabel() {
00077   if (AFI->isThumbFunction()) {
00078     OutStreamer.EmitAssemblerFlag(MCAF_Code16);
00079     OutStreamer.EmitThumbFunc(CurrentFnSym);
00080   }
00081 
00082   OutStreamer.EmitLabel(CurrentFnSym);
00083 }
00084 
00085 void ARMAsmPrinter::EmitXXStructor(const Constant *CV) {
00086   uint64_t Size =
00087       TM.getSubtargetImpl()->getDataLayout()->getTypeAllocSize(CV->getType());
00088   assert(Size && "C++ constructor pointer had zero size!");
00089 
00090   const GlobalValue *GV = dyn_cast<GlobalValue>(CV->stripPointerCasts());
00091   assert(GV && "C++ constructor pointer was not a GlobalValue!");
00092 
00093   const MCExpr *E = MCSymbolRefExpr::Create(GetARMGVSymbol(GV,
00094                                                            ARMII::MO_NO_FLAG),
00095                                             (Subtarget->isTargetELF()
00096                                              ? MCSymbolRefExpr::VK_ARM_TARGET1
00097                                              : MCSymbolRefExpr::VK_None),
00098                                             OutContext);
00099 
00100   OutStreamer.EmitValue(E, Size);
00101 }
00102 
00103 /// runOnMachineFunction - This uses the EmitInstruction()
00104 /// method to print assembly for each instruction.
00105 ///
00106 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
00107   AFI = MF.getInfo<ARMFunctionInfo>();
00108   MCP = MF.getConstantPool();
00109 
00110   SetupMachineFunction(MF);
00111 
00112   if (Subtarget->isTargetCOFF()) {
00113     bool Internal = MF.getFunction()->hasInternalLinkage();
00114     COFF::SymbolStorageClass Scl = Internal ? COFF::IMAGE_SYM_CLASS_STATIC
00115                                             : COFF::IMAGE_SYM_CLASS_EXTERNAL;
00116     int Type = COFF::IMAGE_SYM_DTYPE_FUNCTION << COFF::SCT_COMPLEX_TYPE_SHIFT;
00117 
00118     OutStreamer.BeginCOFFSymbolDef(CurrentFnSym);
00119     OutStreamer.EmitCOFFSymbolStorageClass(Scl);
00120     OutStreamer.EmitCOFFSymbolType(Type);
00121     OutStreamer.EndCOFFSymbolDef();
00122   }
00123 
00124   // Have common code print out the function header with linkage info etc.
00125   EmitFunctionHeader();
00126 
00127   // Emit the rest of the function body.
00128   EmitFunctionBody();
00129 
00130   // If we need V4T thumb mode Register Indirect Jump pads, emit them.
00131   // These are created per function, rather than per TU, since it's
00132   // relatively easy to exceed the thumb branch range within a TU.
00133   if (! ThumbIndirectPads.empty()) {
00134     OutStreamer.EmitAssemblerFlag(MCAF_Code16);
00135     EmitAlignment(1);
00136     for (unsigned i = 0, e = ThumbIndirectPads.size(); i < e; i++) {
00137       OutStreamer.EmitLabel(ThumbIndirectPads[i].second);
00138       EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tBX)
00139         .addReg(ThumbIndirectPads[i].first)
00140         // Add predicate operands.
00141         .addImm(ARMCC::AL)
00142         .addReg(0));
00143     }
00144     ThumbIndirectPads.clear();
00145   }
00146 
00147   // We didn't modify anything.
00148   return false;
00149 }
00150 
00151 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
00152                                  raw_ostream &O, const char *Modifier) {
00153   const MachineOperand &MO = MI->getOperand(OpNum);
00154   unsigned TF = MO.getTargetFlags();
00155 
00156   switch (MO.getType()) {
00157   default: llvm_unreachable("<unknown operand type>");
00158   case MachineOperand::MO_Register: {
00159     unsigned Reg = MO.getReg();
00160     assert(TargetRegisterInfo::isPhysicalRegister(Reg));
00161     assert(!MO.getSubReg() && "Subregs should be eliminated!");
00162     if(ARM::GPRPairRegClass.contains(Reg)) {
00163       const MachineFunction &MF = *MI->getParent()->getParent();
00164       const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
00165       Reg = TRI->getSubReg(Reg, ARM::gsub_0);
00166     }
00167     O << ARMInstPrinter::getRegisterName(Reg);
00168     break;
00169   }
00170   case MachineOperand::MO_Immediate: {
00171     int64_t Imm = MO.getImm();
00172     O << '#';
00173     if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
00174         (TF == ARMII::MO_LO16))
00175       O << ":lower16:";
00176     else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
00177              (TF == ARMII::MO_HI16))
00178       O << ":upper16:";
00179     O << Imm;
00180     break;
00181   }
00182   case MachineOperand::MO_MachineBasicBlock:
00183     O << *MO.getMBB()->getSymbol();
00184     return;
00185   case MachineOperand::MO_GlobalAddress: {
00186     const GlobalValue *GV = MO.getGlobal();
00187     if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
00188         (TF & ARMII::MO_LO16))
00189       O << ":lower16:";
00190     else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
00191              (TF & ARMII::MO_HI16))
00192       O << ":upper16:";
00193     O << *GetARMGVSymbol(GV, TF);
00194 
00195     printOffset(MO.getOffset(), O);
00196     if (TF == ARMII::MO_PLT)
00197       O << "(PLT)";
00198     break;
00199   }
00200   case MachineOperand::MO_ConstantPoolIndex:
00201     O << *GetCPISymbol(MO.getIndex());
00202     break;
00203   }
00204 }
00205 
00206 //===--------------------------------------------------------------------===//
00207 
00208 MCSymbol *ARMAsmPrinter::
00209 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
00210   const DataLayout *DL = TM.getSubtargetImpl()->getDataLayout();
00211   SmallString<60> Name;
00212   raw_svector_ostream(Name) << DL->getPrivateGlobalPrefix() << "JTI"
00213     << getFunctionNumber() << '_' << uid << '_' << uid2;
00214   return OutContext.GetOrCreateSymbol(Name.str());
00215 }
00216 
00217 
00218 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel() const {
00219   const DataLayout *DL = TM.getSubtargetImpl()->getDataLayout();
00220   SmallString<60> Name;
00221   raw_svector_ostream(Name) << DL->getPrivateGlobalPrefix() << "SJLJEH"
00222     << getFunctionNumber();
00223   return OutContext.GetOrCreateSymbol(Name.str());
00224 }
00225 
00226 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
00227                                     unsigned AsmVariant, const char *ExtraCode,
00228                                     raw_ostream &O) {
00229   // Does this asm operand have a single letter operand modifier?
00230   if (ExtraCode && ExtraCode[0]) {
00231     if (ExtraCode[1] != 0) return true; // Unknown modifier.
00232 
00233     switch (ExtraCode[0]) {
00234     default:
00235       // See if this is a generic print operand
00236       return AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O);
00237     case 'a': // Print as a memory address.
00238       if (MI->getOperand(OpNum).isReg()) {
00239         O << "["
00240           << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
00241           << "]";
00242         return false;
00243       }
00244       // Fallthrough
00245     case 'c': // Don't print "#" before an immediate operand.
00246       if (!MI->getOperand(OpNum).isImm())
00247         return true;
00248       O << MI->getOperand(OpNum).getImm();
00249       return false;
00250     case 'P': // Print a VFP double precision register.
00251     case 'q': // Print a NEON quad precision register.
00252       printOperand(MI, OpNum, O);
00253       return false;
00254     case 'y': // Print a VFP single precision register as indexed double.
00255       if (MI->getOperand(OpNum).isReg()) {
00256         unsigned Reg = MI->getOperand(OpNum).getReg();
00257         const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
00258         // Find the 'd' register that has this 's' register as a sub-register,
00259         // and determine the lane number.
00260         for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
00261           if (!ARM::DPRRegClass.contains(*SR))
00262             continue;
00263           bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
00264           O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");
00265           return false;
00266         }
00267       }
00268       return true;
00269     case 'B': // Bitwise inverse of integer or symbol without a preceding #.
00270       if (!MI->getOperand(OpNum).isImm())
00271         return true;
00272       O << ~(MI->getOperand(OpNum).getImm());
00273       return false;
00274     case 'L': // The low 16 bits of an immediate constant.
00275       if (!MI->getOperand(OpNum).isImm())
00276         return true;
00277       O << (MI->getOperand(OpNum).getImm() & 0xffff);
00278       return false;
00279     case 'M': { // A register range suitable for LDM/STM.
00280       if (!MI->getOperand(OpNum).isReg())
00281         return true;
00282       const MachineOperand &MO = MI->getOperand(OpNum);
00283       unsigned RegBegin = MO.getReg();
00284       // This takes advantage of the 2 operand-ness of ldm/stm and that we've
00285       // already got the operands in registers that are operands to the
00286       // inline asm statement.
00287       O << "{";
00288       if (ARM::GPRPairRegClass.contains(RegBegin)) {
00289         const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
00290         unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
00291         O << ARMInstPrinter::getRegisterName(Reg0) << ", ";
00292         RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1);
00293       }
00294       O << ARMInstPrinter::getRegisterName(RegBegin);
00295 
00296       // FIXME: The register allocator not only may not have given us the
00297       // registers in sequence, but may not be in ascending registers. This
00298       // will require changes in the register allocator that'll need to be
00299       // propagated down here if the operands change.
00300       unsigned RegOps = OpNum + 1;
00301       while (MI->getOperand(RegOps).isReg()) {
00302         O << ", "
00303           << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
00304         RegOps++;
00305       }
00306 
00307       O << "}";
00308 
00309       return false;
00310     }
00311     case 'R': // The most significant register of a pair.
00312     case 'Q': { // The least significant register of a pair.
00313       if (OpNum == 0)
00314         return true;
00315       const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
00316       if (!FlagsOP.isImm())
00317         return true;
00318       unsigned Flags = FlagsOP.getImm();
00319 
00320       // This operand may not be the one that actually provides the register. If
00321       // it's tied to a previous one then we should refer instead to that one
00322       // for registers and their classes.
00323       unsigned TiedIdx;
00324       if (InlineAsm::isUseOperandTiedToDef(Flags, TiedIdx)) {
00325         for (OpNum = InlineAsm::MIOp_FirstOperand; TiedIdx; --TiedIdx) {
00326           unsigned OpFlags = MI->getOperand(OpNum).getImm();
00327           OpNum += InlineAsm::getNumOperandRegisters(OpFlags) + 1;
00328         }
00329         Flags = MI->getOperand(OpNum).getImm();
00330 
00331         // Later code expects OpNum to be pointing at the register rather than
00332         // the flags.
00333         OpNum += 1;
00334       }
00335 
00336       unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
00337       unsigned RC;
00338       InlineAsm::hasRegClassConstraint(Flags, RC);
00339       if (RC == ARM::GPRPairRegClassID) {
00340         if (NumVals != 1)
00341           return true;
00342         const MachineOperand &MO = MI->getOperand(OpNum);
00343         if (!MO.isReg())
00344           return true;
00345         const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
00346         unsigned Reg = TRI->getSubReg(MO.getReg(), ExtraCode[0] == 'Q' ?
00347             ARM::gsub_0 : ARM::gsub_1);
00348         O << ARMInstPrinter::getRegisterName(Reg);
00349         return false;
00350       }
00351       if (NumVals != 2)
00352         return true;
00353       unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
00354       if (RegOp >= MI->getNumOperands())
00355         return true;
00356       const MachineOperand &MO = MI->getOperand(RegOp);
00357       if (!MO.isReg())
00358         return true;
00359       unsigned Reg = MO.getReg();
00360       O << ARMInstPrinter::getRegisterName(Reg);
00361       return false;
00362     }
00363 
00364     case 'e': // The low doubleword register of a NEON quad register.
00365     case 'f': { // The high doubleword register of a NEON quad register.
00366       if (!MI->getOperand(OpNum).isReg())
00367         return true;
00368       unsigned Reg = MI->getOperand(OpNum).getReg();
00369       if (!ARM::QPRRegClass.contains(Reg))
00370         return true;
00371       const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
00372       unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
00373                                        ARM::dsub_0 : ARM::dsub_1);
00374       O << ARMInstPrinter::getRegisterName(SubReg);
00375       return false;
00376     }
00377 
00378     // This modifier is not yet supported.
00379     case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
00380       return true;
00381     case 'H': { // The highest-numbered register of a pair.
00382       const MachineOperand &MO = MI->getOperand(OpNum);
00383       if (!MO.isReg())
00384         return true;
00385       const MachineFunction &MF = *MI->getParent()->getParent();
00386       const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
00387       unsigned Reg = MO.getReg();
00388       if(!ARM::GPRPairRegClass.contains(Reg))
00389         return false;
00390       Reg = TRI->getSubReg(Reg, ARM::gsub_1);
00391       O << ARMInstPrinter::getRegisterName(Reg);
00392       return false;
00393     }
00394     }
00395   }
00396 
00397   printOperand(MI, OpNum, O);
00398   return false;
00399 }
00400 
00401 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
00402                                           unsigned OpNum, unsigned AsmVariant,
00403                                           const char *ExtraCode,
00404                                           raw_ostream &O) {
00405   // Does this asm operand have a single letter operand modifier?
00406   if (ExtraCode && ExtraCode[0]) {
00407     if (ExtraCode[1] != 0) return true; // Unknown modifier.
00408 
00409     switch (ExtraCode[0]) {
00410       case 'A': // A memory operand for a VLD1/VST1 instruction.
00411       default: return true;  // Unknown modifier.
00412       case 'm': // The base register of a memory operand.
00413         if (!MI->getOperand(OpNum).isReg())
00414           return true;
00415         O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
00416         return false;
00417     }
00418   }
00419 
00420   const MachineOperand &MO = MI->getOperand(OpNum);
00421   assert(MO.isReg() && "unexpected inline asm memory operand");
00422   O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
00423   return false;
00424 }
00425 
00426 static bool isThumb(const MCSubtargetInfo& STI) {
00427   return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
00428 }
00429 
00430 void ARMAsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo &StartInfo,
00431                                      const MCSubtargetInfo *EndInfo) const {
00432   // If either end mode is unknown (EndInfo == NULL) or different than
00433   // the start mode, then restore the start mode.
00434   const bool WasThumb = isThumb(StartInfo);
00435   if (!EndInfo || WasThumb != isThumb(*EndInfo)) {
00436     OutStreamer.EmitAssemblerFlag(WasThumb ? MCAF_Code16 : MCAF_Code32);
00437   }
00438 }
00439 
00440 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
00441   if (Subtarget->isTargetMachO()) {
00442     Reloc::Model RelocM = TM.getRelocationModel();
00443     if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
00444       // Declare all the text sections up front (before the DWARF sections
00445       // emitted by AsmPrinter::doInitialization) so the assembler will keep
00446       // them together at the beginning of the object file.  This helps
00447       // avoid out-of-range branches that are due a fundamental limitation of
00448       // the way symbol offsets are encoded with the current Darwin ARM
00449       // relocations.
00450       const TargetLoweringObjectFileMachO &TLOFMacho =
00451         static_cast<const TargetLoweringObjectFileMachO &>(
00452           getObjFileLowering());
00453 
00454       // Collect the set of sections our functions will go into.
00455       SetVector<const MCSection *, SmallVector<const MCSection *, 8>,
00456         SmallPtrSet<const MCSection *, 8> > TextSections;
00457       // Default text section comes first.
00458       TextSections.insert(TLOFMacho.getTextSection());
00459       // Now any user defined text sections from function attributes.
00460       for (Module::iterator F = M.begin(), e = M.end(); F != e; ++F)
00461         if (!F->isDeclaration() && !F->hasAvailableExternallyLinkage())
00462           TextSections.insert(TLOFMacho.SectionForGlobal(F, *Mang, TM));
00463       // Now the coalescable sections.
00464       TextSections.insert(TLOFMacho.getTextCoalSection());
00465       TextSections.insert(TLOFMacho.getConstTextCoalSection());
00466 
00467       // Emit the sections in the .s file header to fix the order.
00468       for (unsigned i = 0, e = TextSections.size(); i != e; ++i)
00469         OutStreamer.SwitchSection(TextSections[i]);
00470 
00471       if (RelocM == Reloc::DynamicNoPIC) {
00472         const MCSection *sect =
00473           OutContext.getMachOSection("__TEXT", "__symbol_stub4",
00474                                      MachO::S_SYMBOL_STUBS,
00475                                      12, SectionKind::getText());
00476         OutStreamer.SwitchSection(sect);
00477       } else {
00478         const MCSection *sect =
00479           OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
00480                                      MachO::S_SYMBOL_STUBS,
00481                                      16, SectionKind::getText());
00482         OutStreamer.SwitchSection(sect);
00483       }
00484       const MCSection *StaticInitSect =
00485         OutContext.getMachOSection("__TEXT", "__StaticInit",
00486                                    MachO::S_REGULAR |
00487                                    MachO::S_ATTR_PURE_INSTRUCTIONS,
00488                                    SectionKind::getText());
00489       OutStreamer.SwitchSection(StaticInitSect);
00490     }
00491 
00492     // Compiling with debug info should not affect the code
00493     // generation.  Ensure the cstring section comes before the
00494     // optional __DWARF secion. Otherwise, PC-relative loads would
00495     // have to use different instruction sequences at "-g" in order to
00496     // reach global data in the same object file.
00497     OutStreamer.SwitchSection(getObjFileLowering().getCStringSection());
00498   }
00499 
00500   // Use unified assembler syntax.
00501   OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
00502 
00503   // Emit ARM Build Attributes
00504   if (Subtarget->isTargetELF())
00505     emitAttributes();
00506 
00507   if (!M.getModuleInlineAsm().empty() && Subtarget->isThumb())
00508     OutStreamer.EmitAssemblerFlag(MCAF_Code16);
00509 }
00510 
00511 static void
00512 emitNonLazySymbolPointer(MCStreamer &OutStreamer, MCSymbol *StubLabel,
00513                          MachineModuleInfoImpl::StubValueTy &MCSym) {
00514   // L_foo$stub:
00515   OutStreamer.EmitLabel(StubLabel);
00516   //   .indirect_symbol _foo
00517   OutStreamer.EmitSymbolAttribute(MCSym.getPointer(), MCSA_IndirectSymbol);
00518 
00519   if (MCSym.getInt())
00520     // External to current translation unit.
00521     OutStreamer.EmitIntValue(0, 4/*size*/);
00522   else
00523     // Internal to current translation unit.
00524     //
00525     // When we place the LSDA into the TEXT section, the type info
00526     // pointers need to be indirect and pc-rel. We accomplish this by
00527     // using NLPs; however, sometimes the types are local to the file.
00528     // We need to fill in the value for the NLP in those cases.
00529     OutStreamer.EmitValue(
00530         MCSymbolRefExpr::Create(MCSym.getPointer(), OutStreamer.getContext()),
00531         4 /*size*/);
00532 }
00533 
00534 
00535 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
00536   if (Subtarget->isTargetMachO()) {
00537     // All darwin targets use mach-o.
00538     const TargetLoweringObjectFileMachO &TLOFMacho =
00539       static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
00540     MachineModuleInfoMachO &MMIMacho =
00541       MMI->getObjFileInfo<MachineModuleInfoMachO>();
00542 
00543     // Output non-lazy-pointers for external and common global variables.
00544     MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
00545 
00546     if (!Stubs.empty()) {
00547       // Switch with ".non_lazy_symbol_pointer" directive.
00548       OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
00549       EmitAlignment(2);
00550 
00551       for (auto &Stub : Stubs)
00552         emitNonLazySymbolPointer(OutStreamer, Stub.first, Stub.second);
00553 
00554       Stubs.clear();
00555       OutStreamer.AddBlankLine();
00556     }
00557 
00558     Stubs = MMIMacho.GetHiddenGVStubList();
00559     if (!Stubs.empty()) {
00560       OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
00561       EmitAlignment(2);
00562 
00563       for (auto &Stub : Stubs)
00564         emitNonLazySymbolPointer(OutStreamer, Stub.first, Stub.second);
00565 
00566       Stubs.clear();
00567       OutStreamer.AddBlankLine();
00568     }
00569 
00570     // Funny Darwin hack: This flag tells the linker that no global symbols
00571     // contain code that falls through to other global symbols (e.g. the obvious
00572     // implementation of multiple entry points).  If this doesn't occur, the
00573     // linker can safely perform dead code stripping.  Since LLVM never
00574     // generates code that does this, it is always safe to set.
00575     OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
00576   }
00577 
00578   // Emit a .data.rel section containing any stubs that were created.
00579   if (Subtarget->isTargetELF()) {
00580     const TargetLoweringObjectFileELF &TLOFELF =
00581       static_cast<const TargetLoweringObjectFileELF &>(getObjFileLowering());
00582 
00583     MachineModuleInfoELF &MMIELF = MMI->getObjFileInfo<MachineModuleInfoELF>();
00584 
00585     // Output stubs for external and common global variables.
00586     MachineModuleInfoELF::SymbolListTy Stubs = MMIELF.GetGVStubList();
00587     if (!Stubs.empty()) {
00588       OutStreamer.SwitchSection(TLOFELF.getDataRelSection());
00589       const DataLayout *TD = TM.getSubtargetImpl()->getDataLayout();
00590 
00591       for (auto &stub: Stubs) {
00592         OutStreamer.EmitLabel(stub.first);
00593         OutStreamer.EmitSymbolValue(stub.second.getPointer(),
00594                                     TD->getPointerSize(0));
00595       }
00596       Stubs.clear();
00597     }
00598   }
00599 }
00600 
00601 //===----------------------------------------------------------------------===//
00602 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
00603 // FIXME:
00604 // The following seem like one-off assembler flags, but they actually need
00605 // to appear in the .ARM.attributes section in ELF.
00606 // Instead of subclassing the MCELFStreamer, we do the work here.
00607 
00608 static ARMBuildAttrs::CPUArch getArchForCPU(StringRef CPU,
00609                                             const ARMSubtarget *Subtarget) {
00610   if (CPU == "xscale")
00611     return ARMBuildAttrs::v5TEJ;
00612 
00613   if (Subtarget->hasV8Ops())
00614     return ARMBuildAttrs::v8;
00615   else if (Subtarget->hasV7Ops()) {
00616     if (Subtarget->isMClass() && Subtarget->hasThumb2DSP())
00617       return ARMBuildAttrs::v7E_M;
00618     return ARMBuildAttrs::v7;
00619   } else if (Subtarget->hasV6T2Ops())
00620     return ARMBuildAttrs::v6T2;
00621   else if (Subtarget->hasV6MOps())
00622     return ARMBuildAttrs::v6S_M;
00623   else if (Subtarget->hasV6Ops())
00624     return ARMBuildAttrs::v6;
00625   else if (Subtarget->hasV5TEOps())
00626     return ARMBuildAttrs::v5TE;
00627   else if (Subtarget->hasV5TOps())
00628     return ARMBuildAttrs::v5T;
00629   else if (Subtarget->hasV4TOps())
00630     return ARMBuildAttrs::v4T;
00631   else
00632     return ARMBuildAttrs::v4;
00633 }
00634 
00635 void ARMAsmPrinter::emitAttributes() {
00636   MCTargetStreamer &TS = *OutStreamer.getTargetStreamer();
00637   ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
00638 
00639   ATS.emitTextAttribute(ARMBuildAttrs::conformance, "2.09");
00640 
00641   ATS.switchVendor("aeabi");
00642 
00643   std::string CPUString = Subtarget->getCPUString();
00644 
00645   // FIXME: remove krait check when GNU tools support krait cpu
00646   if (CPUString != "generic" && CPUString != "krait")
00647     ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, CPUString);
00648 
00649   ATS.emitAttribute(ARMBuildAttrs::CPU_arch,
00650                     getArchForCPU(CPUString, Subtarget));
00651 
00652   // Tag_CPU_arch_profile must have the default value of 0 when "Architecture
00653   // profile is not applicable (e.g. pre v7, or cross-profile code)".
00654   if (Subtarget->hasV7Ops()) {
00655     if (Subtarget->isAClass()) {
00656       ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
00657                         ARMBuildAttrs::ApplicationProfile);
00658     } else if (Subtarget->isRClass()) {
00659       ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
00660                         ARMBuildAttrs::RealTimeProfile);
00661     } else if (Subtarget->isMClass()) {
00662       ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
00663                         ARMBuildAttrs::MicroControllerProfile);
00664     }
00665   }
00666 
00667   ATS.emitAttribute(ARMBuildAttrs::ARM_ISA_use, Subtarget->hasARMOps() ?
00668                       ARMBuildAttrs::Allowed : ARMBuildAttrs::Not_Allowed);
00669   if (Subtarget->isThumb1Only()) {
00670     ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
00671                       ARMBuildAttrs::Allowed);
00672   } else if (Subtarget->hasThumb2()) {
00673     ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
00674                       ARMBuildAttrs::AllowThumb32);
00675   }
00676 
00677   if (Subtarget->hasNEON()) {
00678     /* NEON is not exactly a VFP architecture, but GAS emit one of
00679      * neon/neon-fp-armv8/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
00680     if (Subtarget->hasFPARMv8()) {
00681       if (Subtarget->hasCrypto())
00682         ATS.emitFPU(ARM::CRYPTO_NEON_FP_ARMV8);
00683       else
00684         ATS.emitFPU(ARM::NEON_FP_ARMV8);
00685     }
00686     else if (Subtarget->hasVFP4())
00687       ATS.emitFPU(ARM::NEON_VFPV4);
00688     else
00689       ATS.emitFPU(ARM::NEON);
00690     // Emit Tag_Advanced_SIMD_arch for ARMv8 architecture
00691     if (Subtarget->hasV8Ops())
00692       ATS.emitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
00693                         ARMBuildAttrs::AllowNeonARMv8);
00694   } else {
00695     if (Subtarget->hasFPARMv8())
00696       // FPv5 and FP-ARMv8 have the same instructions, so are modeled as one
00697       // FPU, but there are two different names for it depending on the CPU.
00698       ATS.emitFPU(Subtarget->hasD16() ? ARM::FPV5_D16 : ARM::FP_ARMV8);
00699     else if (Subtarget->hasVFP4())
00700       ATS.emitFPU(Subtarget->hasD16() ? ARM::VFPV4_D16 : ARM::VFPV4);
00701     else if (Subtarget->hasVFP3())
00702       ATS.emitFPU(Subtarget->hasD16() ? ARM::VFPV3_D16 : ARM::VFPV3);
00703     else if (Subtarget->hasVFP2())
00704       ATS.emitFPU(ARM::VFPV2);
00705   }
00706 
00707   if (TM.getRelocationModel() == Reloc::PIC_) {
00708     // PIC specific attributes.
00709     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RW_data,
00710                       ARMBuildAttrs::AddressRWPCRel);
00711     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RO_data,
00712                       ARMBuildAttrs::AddressROPCRel);
00713     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_GOT_use,
00714                       ARMBuildAttrs::AddressGOT);
00715   } else {
00716     // Allow direct addressing of imported data for all other relocation models.
00717     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_GOT_use,
00718                       ARMBuildAttrs::AddressDirect);
00719   }
00720 
00721   // Signal various FP modes.
00722   if (!TM.Options.UnsafeFPMath) {
00723     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
00724                       ARMBuildAttrs::IEEEDenormals);
00725     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
00726                       ARMBuildAttrs::Allowed);
00727 
00728     // If the user has permitted this code to choose the IEEE 754
00729     // rounding at run-time, emit the rounding attribute.
00730     if (TM.Options.HonorSignDependentRoundingFPMathOption)
00731       ATS.emitAttribute(ARMBuildAttrs::ABI_FP_rounding,
00732                         ARMBuildAttrs::Allowed);
00733   } else {
00734     if (!Subtarget->hasVFP2()) {
00735       // When the target doesn't have an FPU (by design or
00736       // intention), the assumptions made on the software support
00737       // mirror that of the equivalent hardware support *if it
00738       // existed*. For v7 and better we indicate that denormals are
00739       // flushed preserving sign, and for V6 we indicate that
00740       // denormals are flushed to positive zero.
00741       if (Subtarget->hasV7Ops())
00742         ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
00743                           ARMBuildAttrs::PreserveFPSign);
00744     } else if (Subtarget->hasVFP3()) {
00745       // In VFPv4, VFPv4U, VFPv3, or VFPv3U, it is preserved. That is,
00746       // the sign bit of the zero matches the sign bit of the input or
00747       // result that is being flushed to zero.
00748       ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
00749                         ARMBuildAttrs::PreserveFPSign);
00750     }
00751     // For VFPv2 implementations it is implementation defined as
00752     // to whether denormals are flushed to positive zero or to
00753     // whatever the sign of zero is (ARM v7AR ARM 2.7.5). Historically
00754     // LLVM has chosen to flush this to positive zero (most likely for
00755     // GCC compatibility), so that's the chosen value here (the
00756     // absence of its emission implies zero).
00757   }
00758 
00759   // TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath is the
00760   // equivalent of GCC's -ffinite-math-only flag.
00761   if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
00762     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
00763                       ARMBuildAttrs::Allowed);
00764   else
00765     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
00766                       ARMBuildAttrs::AllowIEE754);
00767 
00768   if (Subtarget->allowsUnalignedMem())
00769     ATS.emitAttribute(ARMBuildAttrs::CPU_unaligned_access,
00770                       ARMBuildAttrs::Allowed);
00771   else
00772     ATS.emitAttribute(ARMBuildAttrs::CPU_unaligned_access,
00773                       ARMBuildAttrs::Not_Allowed);
00774 
00775   // FIXME: add more flags to ARMBuildAttributes.h
00776   // 8-bytes alignment stuff.
00777   ATS.emitAttribute(ARMBuildAttrs::ABI_align_needed, 1);
00778   ATS.emitAttribute(ARMBuildAttrs::ABI_align_preserved, 1);
00779 
00780   // ABI_HardFP_use attribute to indicate single precision FP.
00781   if (Subtarget->isFPOnlySP())
00782     ATS.emitAttribute(ARMBuildAttrs::ABI_HardFP_use,
00783                       ARMBuildAttrs::HardFPSinglePrecision);
00784 
00785   // Hard float.  Use both S and D registers and conform to AAPCS-VFP.
00786   if (Subtarget->isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard)
00787     ATS.emitAttribute(ARMBuildAttrs::ABI_VFP_args, ARMBuildAttrs::HardFPAAPCS);
00788 
00789   // FIXME: Should we signal R9 usage?
00790 
00791   if (Subtarget->hasFP16())
00792       ATS.emitAttribute(ARMBuildAttrs::FP_HP_extension, ARMBuildAttrs::AllowHPFP);
00793 
00794   // FIXME: To support emitting this build attribute as GCC does, the
00795   // -mfp16-format option and associated plumbing must be
00796   // supported. For now the __fp16 type is exposed by default, so this
00797   // attribute should be emitted with value 1.
00798   ATS.emitAttribute(ARMBuildAttrs::ABI_FP_16bit_format,
00799                     ARMBuildAttrs::FP16FormatIEEE);
00800 
00801   if (Subtarget->hasMPExtension())
00802       ATS.emitAttribute(ARMBuildAttrs::MPextension_use, ARMBuildAttrs::AllowMP);
00803 
00804   // Hardware divide in ARM mode is part of base arch, starting from ARMv8.
00805   // If only Thumb hwdiv is present, it must also be in base arch (ARMv7-R/M).
00806   // It is not possible to produce DisallowDIV: if hwdiv is present in the base
00807   // arch, supplying -hwdiv downgrades the effective arch, via ClearImpliedBits.
00808   // AllowDIVExt is only emitted if hwdiv isn't available in the base arch;
00809   // otherwise, the default value (AllowDIVIfExists) applies.
00810   if (Subtarget->hasDivideInARMMode() && !Subtarget->hasV8Ops())
00811       ATS.emitAttribute(ARMBuildAttrs::DIV_use, ARMBuildAttrs::AllowDIVExt);
00812 
00813   if (MMI) {
00814     if (const Module *SourceModule = MMI->getModule()) {
00815       // ABI_PCS_wchar_t to indicate wchar_t width
00816       // FIXME: There is no way to emit value 0 (wchar_t prohibited).
00817       if (auto WCharWidthValue = mdconst::extract_or_null<ConstantInt>(
00818               SourceModule->getModuleFlag("wchar_size"))) {
00819         int WCharWidth = WCharWidthValue->getZExtValue();
00820         assert((WCharWidth == 2 || WCharWidth == 4) &&
00821                "wchar_t width must be 2 or 4 bytes");
00822         ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_wchar_t, WCharWidth);
00823       }
00824 
00825       // ABI_enum_size to indicate enum width
00826       // FIXME: There is no way to emit value 0 (enums prohibited) or value 3
00827       //        (all enums contain a value needing 32 bits to encode).
00828       if (auto EnumWidthValue = mdconst::extract_or_null<ConstantInt>(
00829               SourceModule->getModuleFlag("min_enum_size"))) {
00830         int EnumWidth = EnumWidthValue->getZExtValue();
00831         assert((EnumWidth == 1 || EnumWidth == 4) &&
00832                "Minimum enum width must be 1 or 4 bytes");
00833         int EnumBuildAttr = EnumWidth == 1 ? 1 : 2;
00834         ATS.emitAttribute(ARMBuildAttrs::ABI_enum_size, EnumBuildAttr);
00835       }
00836     }
00837   }
00838 
00839   // TODO: We currently only support either reserving the register, or treating
00840   // it as another callee-saved register, but not as SB or a TLS pointer; It
00841   // would instead be nicer to push this from the frontend as metadata, as we do
00842   // for the wchar and enum size tags
00843   if (Subtarget->isR9Reserved())
00844       ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use,
00845                         ARMBuildAttrs::R9Reserved);
00846   else
00847       ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use,
00848                         ARMBuildAttrs::R9IsGPR);
00849 
00850   if (Subtarget->hasTrustZone() && Subtarget->hasVirtualization())
00851       ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
00852                         ARMBuildAttrs::AllowTZVirtualization);
00853   else if (Subtarget->hasTrustZone())
00854       ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
00855                         ARMBuildAttrs::AllowTZ);
00856   else if (Subtarget->hasVirtualization())
00857       ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
00858                         ARMBuildAttrs::AllowVirtualization);
00859 
00860   ATS.finishAttributeSection();
00861 }
00862 
00863 //===----------------------------------------------------------------------===//
00864 
00865 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
00866                              unsigned LabelId, MCContext &Ctx) {
00867 
00868   MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
00869                        + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
00870   return Label;
00871 }
00872 
00873 static MCSymbolRefExpr::VariantKind
00874 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
00875   switch (Modifier) {
00876   case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
00877   case ARMCP::TLSGD:       return MCSymbolRefExpr::VK_TLSGD;
00878   case ARMCP::TPOFF:       return MCSymbolRefExpr::VK_TPOFF;
00879   case ARMCP::GOTTPOFF:    return MCSymbolRefExpr::VK_GOTTPOFF;
00880   case ARMCP::GOT:         return MCSymbolRefExpr::VK_GOT;
00881   case ARMCP::GOTOFF:      return MCSymbolRefExpr::VK_GOTOFF;
00882   }
00883   llvm_unreachable("Invalid ARMCPModifier!");
00884 }
00885 
00886 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV,
00887                                         unsigned char TargetFlags) {
00888   if (Subtarget->isTargetMachO()) {
00889     bool IsIndirect = (TargetFlags & ARMII::MO_NONLAZY) &&
00890       Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
00891 
00892     if (!IsIndirect)
00893       return getSymbol(GV);
00894 
00895     // FIXME: Remove this when Darwin transition to @GOT like syntax.
00896     MCSymbol *MCSym = getSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
00897     MachineModuleInfoMachO &MMIMachO =
00898       MMI->getObjFileInfo<MachineModuleInfoMachO>();
00899     MachineModuleInfoImpl::StubValueTy &StubSym =
00900       GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym)
00901                                 : MMIMachO.getGVStubEntry(MCSym);
00902     if (!StubSym.getPointer())
00903       StubSym = MachineModuleInfoImpl::StubValueTy(getSymbol(GV),
00904                                                    !GV->hasInternalLinkage());
00905     return MCSym;
00906   } else if (Subtarget->isTargetCOFF()) {
00907     assert(Subtarget->isTargetWindows() &&
00908            "Windows is the only supported COFF target");
00909 
00910     bool IsIndirect = (TargetFlags & ARMII::MO_DLLIMPORT);
00911     if (!IsIndirect)
00912       return getSymbol(GV);
00913 
00914     SmallString<128> Name;
00915     Name = "__imp_";
00916     getNameWithPrefix(Name, GV);
00917 
00918     return OutContext.GetOrCreateSymbol(Name);
00919   } else if (Subtarget->isTargetELF()) {
00920     return getSymbol(GV);
00921   }
00922   llvm_unreachable("unexpected target");
00923 }
00924 
00925 void ARMAsmPrinter::
00926 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
00927   const DataLayout *DL = TM.getSubtargetImpl()->getDataLayout();
00928   int Size =
00929       TM.getSubtargetImpl()->getDataLayout()->getTypeAllocSize(MCPV->getType());
00930 
00931   ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
00932 
00933   MCSymbol *MCSym;
00934   if (ACPV->isLSDA()) {
00935     SmallString<128> Str;
00936     raw_svector_ostream OS(Str);
00937     OS << DL->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
00938     MCSym = OutContext.GetOrCreateSymbol(OS.str());
00939   } else if (ACPV->isBlockAddress()) {
00940     const BlockAddress *BA =
00941       cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
00942     MCSym = GetBlockAddressSymbol(BA);
00943   } else if (ACPV->isGlobalValue()) {
00944     const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
00945 
00946     // On Darwin, const-pool entries may get the "FOO$non_lazy_ptr" mangling, so
00947     // flag the global as MO_NONLAZY.
00948     unsigned char TF = Subtarget->isTargetMachO() ? ARMII::MO_NONLAZY : 0;
00949     MCSym = GetARMGVSymbol(GV, TF);
00950   } else if (ACPV->isMachineBasicBlock()) {
00951     const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
00952     MCSym = MBB->getSymbol();
00953   } else {
00954     assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
00955     const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
00956     MCSym = GetExternalSymbolSymbol(Sym);
00957   }
00958 
00959   // Create an MCSymbol for the reference.
00960   const MCExpr *Expr =
00961     MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
00962                             OutContext);
00963 
00964   if (ACPV->getPCAdjustment()) {
00965     MCSymbol *PCLabel = getPICLabel(DL->getPrivateGlobalPrefix(),
00966                                     getFunctionNumber(),
00967                                     ACPV->getLabelId(),
00968                                     OutContext);
00969     const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
00970     PCRelExpr =
00971       MCBinaryExpr::CreateAdd(PCRelExpr,
00972                               MCConstantExpr::Create(ACPV->getPCAdjustment(),
00973                                                      OutContext),
00974                               OutContext);
00975     if (ACPV->mustAddCurrentAddress()) {
00976       // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
00977       // label, so just emit a local label end reference that instead.
00978       MCSymbol *DotSym = OutContext.CreateTempSymbol();
00979       OutStreamer.EmitLabel(DotSym);
00980       const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
00981       PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
00982     }
00983     Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
00984   }
00985   OutStreamer.EmitValue(Expr, Size);
00986 }
00987 
00988 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
00989   unsigned Opcode = MI->getOpcode();
00990   int OpNum = 1;
00991   if (Opcode == ARM::BR_JTadd)
00992     OpNum = 2;
00993   else if (Opcode == ARM::BR_JTm)
00994     OpNum = 3;
00995 
00996   const MachineOperand &MO1 = MI->getOperand(OpNum);
00997   const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
00998   unsigned JTI = MO1.getIndex();
00999 
01000   // Emit a label for the jump table.
01001   MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
01002   OutStreamer.EmitLabel(JTISymbol);
01003 
01004   // Mark the jump table as data-in-code.
01005   OutStreamer.EmitDataRegion(MCDR_DataRegionJT32);
01006 
01007   // Emit each entry of the table.
01008   const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
01009   const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
01010   const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
01011 
01012   for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
01013     MachineBasicBlock *MBB = JTBBs[i];
01014     // Construct an MCExpr for the entry. We want a value of the form:
01015     // (BasicBlockAddr - TableBeginAddr)
01016     //
01017     // For example, a table with entries jumping to basic blocks BB0 and BB1
01018     // would look like:
01019     // LJTI_0_0:
01020     //    .word (LBB0 - LJTI_0_0)
01021     //    .word (LBB1 - LJTI_0_0)
01022     const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
01023 
01024     if (TM.getRelocationModel() == Reloc::PIC_)
01025       Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
01026                                                                    OutContext),
01027                                      OutContext);
01028     // If we're generating a table of Thumb addresses in static relocation
01029     // model, we need to add one to keep interworking correctly.
01030     else if (AFI->isThumbFunction())
01031       Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(1,OutContext),
01032                                      OutContext);
01033     OutStreamer.EmitValue(Expr, 4);
01034   }
01035   // Mark the end of jump table data-in-code region.
01036   OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
01037 }
01038 
01039 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
01040   unsigned Opcode = MI->getOpcode();
01041   int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
01042   const MachineOperand &MO1 = MI->getOperand(OpNum);
01043   const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
01044   unsigned JTI = MO1.getIndex();
01045 
01046   MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
01047   OutStreamer.EmitLabel(JTISymbol);
01048 
01049   // Emit each entry of the table.
01050   const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
01051   const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
01052   const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
01053   unsigned OffsetWidth = 4;
01054   if (MI->getOpcode() == ARM::t2TBB_JT) {
01055     OffsetWidth = 1;
01056     // Mark the jump table as data-in-code.
01057     OutStreamer.EmitDataRegion(MCDR_DataRegionJT8);
01058   } else if (MI->getOpcode() == ARM::t2TBH_JT) {
01059     OffsetWidth = 2;
01060     // Mark the jump table as data-in-code.
01061     OutStreamer.EmitDataRegion(MCDR_DataRegionJT16);
01062   }
01063 
01064   for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
01065     MachineBasicBlock *MBB = JTBBs[i];
01066     const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
01067                                                           OutContext);
01068     // If this isn't a TBB or TBH, the entries are direct branch instructions.
01069     if (OffsetWidth == 4) {
01070       EmitToStreamer(OutStreamer, MCInstBuilder(ARM::t2B)
01071         .addExpr(MBBSymbolExpr)
01072         .addImm(ARMCC::AL)
01073         .addReg(0));
01074       continue;
01075     }
01076     // Otherwise it's an offset from the dispatch instruction. Construct an
01077     // MCExpr for the entry. We want a value of the form:
01078     // (BasicBlockAddr - TableBeginAddr) / 2
01079     //
01080     // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
01081     // would look like:
01082     // LJTI_0_0:
01083     //    .byte (LBB0 - LJTI_0_0) / 2
01084     //    .byte (LBB1 - LJTI_0_0) / 2
01085     const MCExpr *Expr =
01086       MCBinaryExpr::CreateSub(MBBSymbolExpr,
01087                               MCSymbolRefExpr::Create(JTISymbol, OutContext),
01088                               OutContext);
01089     Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
01090                                    OutContext);
01091     OutStreamer.EmitValue(Expr, OffsetWidth);
01092   }
01093   // Mark the end of jump table data-in-code region. 32-bit offsets use
01094   // actual branch instructions here, so we don't mark those as a data-region
01095   // at all.
01096   if (OffsetWidth != 4)
01097     OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
01098 }
01099 
01100 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
01101   assert(MI->getFlag(MachineInstr::FrameSetup) &&
01102       "Only instruction which are involved into frame setup code are allowed");
01103 
01104   MCTargetStreamer &TS = *OutStreamer.getTargetStreamer();
01105   ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
01106   const MachineFunction &MF = *MI->getParent()->getParent();
01107   const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
01108   const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
01109 
01110   unsigned FramePtr = RegInfo->getFrameRegister(MF);
01111   unsigned Opc = MI->getOpcode();
01112   unsigned SrcReg, DstReg;
01113 
01114   if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
01115     // Two special cases:
01116     // 1) tPUSH does not have src/dst regs.
01117     // 2) for Thumb1 code we sometimes materialize the constant via constpool
01118     // load. Yes, this is pretty fragile, but for now I don't see better
01119     // way... :(
01120     SrcReg = DstReg = ARM::SP;
01121   } else {
01122     SrcReg = MI->getOperand(1).getReg();
01123     DstReg = MI->getOperand(0).getReg();
01124   }
01125 
01126   // Try to figure out the unwinding opcode out of src / dst regs.
01127   if (MI->mayStore()) {
01128     // Register saves.
01129     assert(DstReg == ARM::SP &&
01130            "Only stack pointer as a destination reg is supported");
01131 
01132     SmallVector<unsigned, 4> RegList;
01133     // Skip src & dst reg, and pred ops.
01134     unsigned StartOp = 2 + 2;
01135     // Use all the operands.
01136     unsigned NumOffset = 0;
01137 
01138     switch (Opc) {
01139     default:
01140       MI->dump();
01141       llvm_unreachable("Unsupported opcode for unwinding information");
01142     case ARM::tPUSH:
01143       // Special case here: no src & dst reg, but two extra imp ops.
01144       StartOp = 2; NumOffset = 2;
01145     case ARM::STMDB_UPD:
01146     case ARM::t2STMDB_UPD:
01147     case ARM::VSTMDDB_UPD:
01148       assert(SrcReg == ARM::SP &&
01149              "Only stack pointer as a source reg is supported");
01150       for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
01151            i != NumOps; ++i) {
01152         const MachineOperand &MO = MI->getOperand(i);
01153         // Actually, there should never be any impdef stuff here. Skip it
01154         // temporary to workaround PR11902.
01155         if (MO.isImplicit())
01156           continue;
01157         RegList.push_back(MO.getReg());
01158       }
01159       break;
01160     case ARM::STR_PRE_IMM:
01161     case ARM::STR_PRE_REG:
01162     case ARM::t2STR_PRE:
01163       assert(MI->getOperand(2).getReg() == ARM::SP &&
01164              "Only stack pointer as a source reg is supported");
01165       RegList.push_back(SrcReg);
01166       break;
01167     }
01168     if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM)
01169       ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
01170   } else {
01171     // Changes of stack / frame pointer.
01172     if (SrcReg == ARM::SP) {
01173       int64_t Offset = 0;
01174       switch (Opc) {
01175       default:
01176         MI->dump();
01177         llvm_unreachable("Unsupported opcode for unwinding information");
01178       case ARM::MOVr:
01179       case ARM::tMOVr:
01180         Offset = 0;
01181         break;
01182       case ARM::ADDri:
01183         Offset = -MI->getOperand(2).getImm();
01184         break;
01185       case ARM::SUBri:
01186       case ARM::t2SUBri:
01187         Offset = MI->getOperand(2).getImm();
01188         break;
01189       case ARM::tSUBspi:
01190         Offset = MI->getOperand(2).getImm()*4;
01191         break;
01192       case ARM::tADDspi:
01193       case ARM::tADDrSPi:
01194         Offset = -MI->getOperand(2).getImm()*4;
01195         break;
01196       case ARM::tLDRpci: {
01197         // Grab the constpool index and check, whether it corresponds to
01198         // original or cloned constpool entry.
01199         unsigned CPI = MI->getOperand(1).getIndex();
01200         const MachineConstantPool *MCP = MF.getConstantPool();
01201         if (CPI >= MCP->getConstants().size())
01202           CPI = AFI.getOriginalCPIdx(CPI);
01203         assert(CPI != -1U && "Invalid constpool index");
01204 
01205         // Derive the actual offset.
01206         const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
01207         assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
01208         // FIXME: Check for user, it should be "add" instruction!
01209         Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
01210         break;
01211       }
01212       }
01213 
01214       if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM) {
01215         if (DstReg == FramePtr && FramePtr != ARM::SP)
01216           // Set-up of the frame pointer. Positive values correspond to "add"
01217           // instruction.
01218           ATS.emitSetFP(FramePtr, ARM::SP, -Offset);
01219         else if (DstReg == ARM::SP) {
01220           // Change of SP by an offset. Positive values correspond to "sub"
01221           // instruction.
01222           ATS.emitPad(Offset);
01223         } else {
01224           // Move of SP to a register.  Positive values correspond to an "add"
01225           // instruction.
01226           ATS.emitMovSP(DstReg, -Offset);
01227         }
01228       }
01229     } else if (DstReg == ARM::SP) {
01230       MI->dump();
01231       llvm_unreachable("Unsupported opcode for unwinding information");
01232     }
01233     else {
01234       MI->dump();
01235       llvm_unreachable("Unsupported opcode for unwinding information");
01236     }
01237   }
01238 }
01239 
01240 // Simple pseudo-instructions have their lowering (with expansion to real
01241 // instructions) auto-generated.
01242 #include "ARMGenMCPseudoLowering.inc"
01243 
01244 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
01245   const DataLayout *DL = TM.getSubtargetImpl()->getDataLayout();
01246 
01247   // If we just ended a constant pool, mark it as such.
01248   if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
01249     OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
01250     InConstantPool = false;
01251   }
01252 
01253   // Emit unwinding stuff for frame-related instructions
01254   if (Subtarget->isTargetEHABICompatible() &&
01255        MI->getFlag(MachineInstr::FrameSetup))
01256     EmitUnwindingInstruction(MI);
01257 
01258   // Do any auto-generated pseudo lowerings.
01259   if (emitPseudoExpansionLowering(OutStreamer, MI))
01260     return;
01261 
01262   assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
01263          "Pseudo flag setting opcode should be expanded early");
01264 
01265   // Check for manual lowerings.
01266   unsigned Opc = MI->getOpcode();
01267   switch (Opc) {
01268   case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
01269   case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing");
01270   case ARM::LEApcrel:
01271   case ARM::tLEApcrel:
01272   case ARM::t2LEApcrel: {
01273     // FIXME: Need to also handle globals and externals
01274     MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex());
01275     EmitToStreamer(OutStreamer, MCInstBuilder(MI->getOpcode() ==
01276                                               ARM::t2LEApcrel ? ARM::t2ADR
01277                   : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
01278                      : ARM::ADR))
01279       .addReg(MI->getOperand(0).getReg())
01280       .addExpr(MCSymbolRefExpr::Create(CPISymbol, OutContext))
01281       // Add predicate operands.
01282       .addImm(MI->getOperand(2).getImm())
01283       .addReg(MI->getOperand(3).getReg()));
01284     return;
01285   }
01286   case ARM::LEApcrelJT:
01287   case ARM::tLEApcrelJT:
01288   case ARM::t2LEApcrelJT: {
01289     MCSymbol *JTIPICSymbol =
01290       GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
01291                                   MI->getOperand(2).getImm());
01292     EmitToStreamer(OutStreamer, MCInstBuilder(MI->getOpcode() ==
01293                                               ARM::t2LEApcrelJT ? ARM::t2ADR
01294                   : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
01295                      : ARM::ADR))
01296       .addReg(MI->getOperand(0).getReg())
01297       .addExpr(MCSymbolRefExpr::Create(JTIPICSymbol, OutContext))
01298       // Add predicate operands.
01299       .addImm(MI->getOperand(3).getImm())
01300       .addReg(MI->getOperand(4).getReg()));
01301     return;
01302   }
01303   // Darwin call instructions are just normal call instructions with different
01304   // clobber semantics (they clobber R9).
01305   case ARM::BX_CALL: {
01306     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
01307       .addReg(ARM::LR)
01308       .addReg(ARM::PC)
01309       // Add predicate operands.
01310       .addImm(ARMCC::AL)
01311       .addReg(0)
01312       // Add 's' bit operand (always reg0 for this)
01313       .addReg(0));
01314 
01315     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::BX)
01316       .addReg(MI->getOperand(0).getReg()));
01317     return;
01318   }
01319   case ARM::tBX_CALL: {
01320     if (Subtarget->hasV5TOps())
01321       llvm_unreachable("Expected BLX to be selected for v5t+");
01322 
01323     // On ARM v4t, when doing a call from thumb mode, we need to ensure
01324     // that the saved lr has its LSB set correctly (the arch doesn't
01325     // have blx).
01326     // So here we generate a bl to a small jump pad that does bx rN.
01327     // The jump pads are emitted after the function body.
01328 
01329     unsigned TReg = MI->getOperand(0).getReg();
01330     MCSymbol *TRegSym = nullptr;
01331     for (unsigned i = 0, e = ThumbIndirectPads.size(); i < e; i++) {
01332       if (ThumbIndirectPads[i].first == TReg) {
01333         TRegSym = ThumbIndirectPads[i].second;
01334         break;
01335       }
01336     }
01337 
01338     if (!TRegSym) {
01339       TRegSym = OutContext.CreateTempSymbol();
01340       ThumbIndirectPads.push_back(std::make_pair(TReg, TRegSym));
01341     }
01342 
01343     // Create a link-saving branch to the Reg Indirect Jump Pad.
01344     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tBL)
01345         // Predicate comes first here.
01346         .addImm(ARMCC::AL).addReg(0)
01347         .addExpr(MCSymbolRefExpr::Create(TRegSym, OutContext)));
01348     return;
01349   }
01350   case ARM::BMOVPCRX_CALL: {
01351     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
01352       .addReg(ARM::LR)
01353       .addReg(ARM::PC)
01354       // Add predicate operands.
01355       .addImm(ARMCC::AL)
01356       .addReg(0)
01357       // Add 's' bit operand (always reg0 for this)
01358       .addReg(0));
01359 
01360     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
01361       .addReg(ARM::PC)
01362       .addReg(MI->getOperand(0).getReg())
01363       // Add predicate operands.
01364       .addImm(ARMCC::AL)
01365       .addReg(0)
01366       // Add 's' bit operand (always reg0 for this)
01367       .addReg(0));
01368     return;
01369   }
01370   case ARM::BMOVPCB_CALL: {
01371     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
01372       .addReg(ARM::LR)
01373       .addReg(ARM::PC)
01374       // Add predicate operands.
01375       .addImm(ARMCC::AL)
01376       .addReg(0)
01377       // Add 's' bit operand (always reg0 for this)
01378       .addReg(0));
01379 
01380     const MachineOperand &Op = MI->getOperand(0);
01381     const GlobalValue *GV = Op.getGlobal();
01382     const unsigned TF = Op.getTargetFlags();
01383     MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
01384     const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
01385     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::Bcc)
01386       .addExpr(GVSymExpr)
01387       // Add predicate operands.
01388       .addImm(ARMCC::AL)
01389       .addReg(0));
01390     return;
01391   }
01392   case ARM::MOVi16_ga_pcrel:
01393   case ARM::t2MOVi16_ga_pcrel: {
01394     MCInst TmpInst;
01395     TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
01396     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
01397 
01398     unsigned TF = MI->getOperand(1).getTargetFlags();
01399     const GlobalValue *GV = MI->getOperand(1).getGlobal();
01400     MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
01401     const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
01402 
01403     MCSymbol *LabelSym = getPICLabel(DL->getPrivateGlobalPrefix(),
01404                                      getFunctionNumber(),
01405                                      MI->getOperand(2).getImm(), OutContext);
01406     const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
01407     unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
01408     const MCExpr *PCRelExpr =
01409       ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
01410                                       MCBinaryExpr::CreateAdd(LabelSymExpr,
01411                                       MCConstantExpr::Create(PCAdj, OutContext),
01412                                       OutContext), OutContext), OutContext);
01413       TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
01414 
01415     // Add predicate operands.
01416     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
01417     TmpInst.addOperand(MCOperand::CreateReg(0));
01418     // Add 's' bit operand (always reg0 for this)
01419     TmpInst.addOperand(MCOperand::CreateReg(0));
01420     EmitToStreamer(OutStreamer, TmpInst);
01421     return;
01422   }
01423   case ARM::MOVTi16_ga_pcrel:
01424   case ARM::t2MOVTi16_ga_pcrel: {
01425     MCInst TmpInst;
01426     TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
01427                       ? ARM::MOVTi16 : ARM::t2MOVTi16);
01428     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
01429     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
01430 
01431     unsigned TF = MI->getOperand(2).getTargetFlags();
01432     const GlobalValue *GV = MI->getOperand(2).getGlobal();
01433     MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
01434     const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
01435 
01436     MCSymbol *LabelSym = getPICLabel(DL->getPrivateGlobalPrefix(),
01437                                      getFunctionNumber(),
01438                                      MI->getOperand(3).getImm(), OutContext);
01439     const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
01440     unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
01441     const MCExpr *PCRelExpr =
01442         ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
01443                                    MCBinaryExpr::CreateAdd(LabelSymExpr,
01444                                       MCConstantExpr::Create(PCAdj, OutContext),
01445                                           OutContext), OutContext), OutContext);
01446       TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
01447     // Add predicate operands.
01448     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
01449     TmpInst.addOperand(MCOperand::CreateReg(0));
01450     // Add 's' bit operand (always reg0 for this)
01451     TmpInst.addOperand(MCOperand::CreateReg(0));
01452     EmitToStreamer(OutStreamer, TmpInst);
01453     return;
01454   }
01455   case ARM::tPICADD: {
01456     // This is a pseudo op for a label + instruction sequence, which looks like:
01457     // LPC0:
01458     //     add r0, pc
01459     // This adds the address of LPC0 to r0.
01460 
01461     // Emit the label.
01462     OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
01463                           getFunctionNumber(), MI->getOperand(2).getImm(),
01464                           OutContext));
01465 
01466     // Form and emit the add.
01467     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tADDhirr)
01468       .addReg(MI->getOperand(0).getReg())
01469       .addReg(MI->getOperand(0).getReg())
01470       .addReg(ARM::PC)
01471       // Add predicate operands.
01472       .addImm(ARMCC::AL)
01473       .addReg(0));
01474     return;
01475   }
01476   case ARM::PICADD: {
01477     // This is a pseudo op for a label + instruction sequence, which looks like:
01478     // LPC0:
01479     //     add r0, pc, r0
01480     // This adds the address of LPC0 to r0.
01481 
01482     // Emit the label.
01483     OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
01484                           getFunctionNumber(), MI->getOperand(2).getImm(),
01485                           OutContext));
01486 
01487     // Form and emit the add.
01488     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDrr)
01489       .addReg(MI->getOperand(0).getReg())
01490       .addReg(ARM::PC)
01491       .addReg(MI->getOperand(1).getReg())
01492       // Add predicate operands.
01493       .addImm(MI->getOperand(3).getImm())
01494       .addReg(MI->getOperand(4).getReg())
01495       // Add 's' bit operand (always reg0 for this)
01496       .addReg(0));
01497     return;
01498   }
01499   case ARM::PICSTR:
01500   case ARM::PICSTRB:
01501   case ARM::PICSTRH:
01502   case ARM::PICLDR:
01503   case ARM::PICLDRB:
01504   case ARM::PICLDRH:
01505   case ARM::PICLDRSB:
01506   case ARM::PICLDRSH: {
01507     // This is a pseudo op for a label + instruction sequence, which looks like:
01508     // LPC0:
01509     //     OP r0, [pc, r0]
01510     // The LCP0 label is referenced by a constant pool entry in order to get
01511     // a PC-relative address at the ldr instruction.
01512 
01513     // Emit the label.
01514     OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
01515                           getFunctionNumber(), MI->getOperand(2).getImm(),
01516                           OutContext));
01517 
01518     // Form and emit the load
01519     unsigned Opcode;
01520     switch (MI->getOpcode()) {
01521     default:
01522       llvm_unreachable("Unexpected opcode!");
01523     case ARM::PICSTR:   Opcode = ARM::STRrs; break;
01524     case ARM::PICSTRB:  Opcode = ARM::STRBrs; break;
01525     case ARM::PICSTRH:  Opcode = ARM::STRH; break;
01526     case ARM::PICLDR:   Opcode = ARM::LDRrs; break;
01527     case ARM::PICLDRB:  Opcode = ARM::LDRBrs; break;
01528     case ARM::PICLDRH:  Opcode = ARM::LDRH; break;
01529     case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
01530     case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
01531     }
01532     EmitToStreamer(OutStreamer, MCInstBuilder(Opcode)
01533       .addReg(MI->getOperand(0).getReg())
01534       .addReg(ARM::PC)
01535       .addReg(MI->getOperand(1).getReg())
01536       .addImm(0)
01537       // Add predicate operands.
01538       .addImm(MI->getOperand(3).getImm())
01539       .addReg(MI->getOperand(4).getReg()));
01540 
01541     return;
01542   }
01543   case ARM::CONSTPOOL_ENTRY: {
01544     /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
01545     /// in the function.  The first operand is the ID# for this instruction, the
01546     /// second is the index into the MachineConstantPool that this is, the third
01547     /// is the size in bytes of this constant pool entry.
01548     /// The required alignment is specified on the basic block holding this MI.
01549     unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
01550     unsigned CPIdx   = (unsigned)MI->getOperand(1).getIndex();
01551 
01552     // If this is the first entry of the pool, mark it.
01553     if (!InConstantPool) {
01554       OutStreamer.EmitDataRegion(MCDR_DataRegion);
01555       InConstantPool = true;
01556     }
01557 
01558     OutStreamer.EmitLabel(GetCPISymbol(LabelId));
01559 
01560     const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
01561     if (MCPE.isMachineConstantPoolEntry())
01562       EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
01563     else
01564       EmitGlobalConstant(MCPE.Val.ConstVal);
01565     return;
01566   }
01567   case ARM::t2BR_JT: {
01568     // Lower and emit the instruction itself, then the jump table following it.
01569     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
01570       .addReg(ARM::PC)
01571       .addReg(MI->getOperand(0).getReg())
01572       // Add predicate operands.
01573       .addImm(ARMCC::AL)
01574       .addReg(0));
01575 
01576     // Output the data for the jump table itself
01577     EmitJump2Table(MI);
01578     return;
01579   }
01580   case ARM::t2TBB_JT: {
01581     // Lower and emit the instruction itself, then the jump table following it.
01582     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::t2TBB)
01583       .addReg(ARM::PC)
01584       .addReg(MI->getOperand(0).getReg())
01585       // Add predicate operands.
01586       .addImm(ARMCC::AL)
01587       .addReg(0));
01588 
01589     // Output the data for the jump table itself
01590     EmitJump2Table(MI);
01591     // Make sure the next instruction is 2-byte aligned.
01592     EmitAlignment(1);
01593     return;
01594   }
01595   case ARM::t2TBH_JT: {
01596     // Lower and emit the instruction itself, then the jump table following it.
01597     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::t2TBH)
01598       .addReg(ARM::PC)
01599       .addReg(MI->getOperand(0).getReg())
01600       // Add predicate operands.
01601       .addImm(ARMCC::AL)
01602       .addReg(0));
01603 
01604     // Output the data for the jump table itself
01605     EmitJump2Table(MI);
01606     return;
01607   }
01608   case ARM::tBR_JTr:
01609   case ARM::BR_JTr: {
01610     // Lower and emit the instruction itself, then the jump table following it.
01611     // mov pc, target
01612     MCInst TmpInst;
01613     unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
01614       ARM::MOVr : ARM::tMOVr;
01615     TmpInst.setOpcode(Opc);
01616     TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
01617     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
01618     // Add predicate operands.
01619     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
01620     TmpInst.addOperand(MCOperand::CreateReg(0));
01621     // Add 's' bit operand (always reg0 for this)
01622     if (Opc == ARM::MOVr)
01623       TmpInst.addOperand(MCOperand::CreateReg(0));
01624     EmitToStreamer(OutStreamer, TmpInst);
01625 
01626     // Make sure the Thumb jump table is 4-byte aligned.
01627     if (Opc == ARM::tMOVr)
01628       EmitAlignment(2);
01629 
01630     // Output the data for the jump table itself
01631     EmitJumpTable(MI);
01632     return;
01633   }
01634   case ARM::BR_JTm: {
01635     // Lower and emit the instruction itself, then the jump table following it.
01636     // ldr pc, target
01637     MCInst TmpInst;
01638     if (MI->getOperand(1).getReg() == 0) {
01639       // literal offset
01640       TmpInst.setOpcode(ARM::LDRi12);
01641       TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
01642       TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
01643       TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
01644     } else {
01645       TmpInst.setOpcode(ARM::LDRrs);
01646       TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
01647       TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
01648       TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
01649       TmpInst.addOperand(MCOperand::CreateImm(0));
01650     }
01651     // Add predicate operands.
01652     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
01653     TmpInst.addOperand(MCOperand::CreateReg(0));
01654     EmitToStreamer(OutStreamer, TmpInst);
01655 
01656     // Output the data for the jump table itself
01657     EmitJumpTable(MI);
01658     return;
01659   }
01660   case ARM::BR_JTadd: {
01661     // Lower and emit the instruction itself, then the jump table following it.
01662     // add pc, target, idx
01663     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDrr)
01664       .addReg(ARM::PC)
01665       .addReg(MI->getOperand(0).getReg())
01666       .addReg(MI->getOperand(1).getReg())
01667       // Add predicate operands.
01668       .addImm(ARMCC::AL)
01669       .addReg(0)
01670       // Add 's' bit operand (always reg0 for this)
01671       .addReg(0));
01672 
01673     // Output the data for the jump table itself
01674     EmitJumpTable(MI);
01675     return;
01676   }
01677   case ARM::SPACE:
01678     OutStreamer.EmitZeros(MI->getOperand(1).getImm());
01679     return;
01680   case ARM::TRAP: {
01681     // Non-Darwin binutils don't yet support the "trap" mnemonic.
01682     // FIXME: Remove this special case when they do.
01683     if (!Subtarget->isTargetMachO()) {
01684       //.long 0xe7ffdefe @ trap
01685       uint32_t Val = 0xe7ffdefeUL;
01686       OutStreamer.AddComment("trap");
01687       OutStreamer.EmitIntValue(Val, 4);
01688       return;
01689     }
01690     break;
01691   }
01692   case ARM::TRAPNaCl: {
01693     //.long 0xe7fedef0 @ trap
01694     uint32_t Val = 0xe7fedef0UL;
01695     OutStreamer.AddComment("trap");
01696     OutStreamer.EmitIntValue(Val, 4);
01697     return;
01698   }
01699   case ARM::tTRAP: {
01700     // Non-Darwin binutils don't yet support the "trap" mnemonic.
01701     // FIXME: Remove this special case when they do.
01702     if (!Subtarget->isTargetMachO()) {
01703       //.short 57086 @ trap
01704       uint16_t Val = 0xdefe;
01705       OutStreamer.AddComment("trap");
01706       OutStreamer.EmitIntValue(Val, 2);
01707       return;
01708     }
01709     break;
01710   }
01711   case ARM::t2Int_eh_sjlj_setjmp:
01712   case ARM::t2Int_eh_sjlj_setjmp_nofp:
01713   case ARM::tInt_eh_sjlj_setjmp: {
01714     // Two incoming args: GPR:$src, GPR:$val
01715     // mov $val, pc
01716     // adds $val, #7
01717     // str $val, [$src, #4]
01718     // movs r0, #0
01719     // b 1f
01720     // movs r0, #1
01721     // 1:
01722     unsigned SrcReg = MI->getOperand(0).getReg();
01723     unsigned ValReg = MI->getOperand(1).getReg();
01724     MCSymbol *Label = GetARMSJLJEHLabel();
01725     OutStreamer.AddComment("eh_setjmp begin");
01726     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
01727       .addReg(ValReg)
01728       .addReg(ARM::PC)
01729       // Predicate.
01730       .addImm(ARMCC::AL)
01731       .addReg(0));
01732 
01733     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tADDi3)
01734       .addReg(ValReg)
01735       // 's' bit operand
01736       .addReg(ARM::CPSR)
01737       .addReg(ValReg)
01738       .addImm(7)
01739       // Predicate.
01740       .addImm(ARMCC::AL)
01741       .addReg(0));
01742 
01743     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tSTRi)
01744       .addReg(ValReg)
01745       .addReg(SrcReg)
01746       // The offset immediate is #4. The operand value is scaled by 4 for the
01747       // tSTR instruction.
01748       .addImm(1)
01749       // Predicate.
01750       .addImm(ARMCC::AL)
01751       .addReg(0));
01752 
01753     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVi8)
01754       .addReg(ARM::R0)
01755       .addReg(ARM::CPSR)
01756       .addImm(0)
01757       // Predicate.
01758       .addImm(ARMCC::AL)
01759       .addReg(0));
01760 
01761     const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
01762     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tB)
01763       .addExpr(SymbolExpr)
01764       .addImm(ARMCC::AL)
01765       .addReg(0));
01766 
01767     OutStreamer.AddComment("eh_setjmp end");
01768     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVi8)
01769       .addReg(ARM::R0)
01770       .addReg(ARM::CPSR)
01771       .addImm(1)
01772       // Predicate.
01773       .addImm(ARMCC::AL)
01774       .addReg(0));
01775 
01776     OutStreamer.EmitLabel(Label);
01777     return;
01778   }
01779 
01780   case ARM::Int_eh_sjlj_setjmp_nofp:
01781   case ARM::Int_eh_sjlj_setjmp: {
01782     // Two incoming args: GPR:$src, GPR:$val
01783     // add $val, pc, #8
01784     // str $val, [$src, #+4]
01785     // mov r0, #0
01786     // add pc, pc, #0
01787     // mov r0, #1
01788     unsigned SrcReg = MI->getOperand(0).getReg();
01789     unsigned ValReg = MI->getOperand(1).getReg();
01790 
01791     OutStreamer.AddComment("eh_setjmp begin");
01792     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDri)
01793       .addReg(ValReg)
01794       .addReg(ARM::PC)
01795       .addImm(8)
01796       // Predicate.
01797       .addImm(ARMCC::AL)
01798       .addReg(0)
01799       // 's' bit operand (always reg0 for this).
01800       .addReg(0));
01801 
01802     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::STRi12)
01803       .addReg(ValReg)
01804       .addReg(SrcReg)
01805       .addImm(4)
01806       // Predicate.
01807       .addImm(ARMCC::AL)
01808       .addReg(0));
01809 
01810     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVi)
01811       .addReg(ARM::R0)
01812       .addImm(0)
01813       // Predicate.
01814       .addImm(ARMCC::AL)
01815       .addReg(0)
01816       // 's' bit operand (always reg0 for this).
01817       .addReg(0));
01818 
01819     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDri)
01820       .addReg(ARM::PC)
01821       .addReg(ARM::PC)
01822       .addImm(0)
01823       // Predicate.
01824       .addImm(ARMCC::AL)
01825       .addReg(0)
01826       // 's' bit operand (always reg0 for this).
01827       .addReg(0));
01828 
01829     OutStreamer.AddComment("eh_setjmp end");
01830     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVi)
01831       .addReg(ARM::R0)
01832       .addImm(1)
01833       // Predicate.
01834       .addImm(ARMCC::AL)
01835       .addReg(0)
01836       // 's' bit operand (always reg0 for this).
01837       .addReg(0));
01838     return;
01839   }
01840   case ARM::Int_eh_sjlj_longjmp: {
01841     // ldr sp, [$src, #8]
01842     // ldr $scratch, [$src, #4]
01843     // ldr r7, [$src]
01844     // bx $scratch
01845     unsigned SrcReg = MI->getOperand(0).getReg();
01846     unsigned ScratchReg = MI->getOperand(1).getReg();
01847     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::LDRi12)
01848       .addReg(ARM::SP)
01849       .addReg(SrcReg)
01850       .addImm(8)
01851       // Predicate.
01852       .addImm(ARMCC::AL)
01853       .addReg(0));
01854 
01855     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::LDRi12)
01856       .addReg(ScratchReg)
01857       .addReg(SrcReg)
01858       .addImm(4)
01859       // Predicate.
01860       .addImm(ARMCC::AL)
01861       .addReg(0));
01862 
01863     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::LDRi12)
01864       .addReg(ARM::R7)
01865       .addReg(SrcReg)
01866       .addImm(0)
01867       // Predicate.
01868       .addImm(ARMCC::AL)
01869       .addReg(0));
01870 
01871     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::BX)
01872       .addReg(ScratchReg)
01873       // Predicate.
01874       .addImm(ARMCC::AL)
01875       .addReg(0));
01876     return;
01877   }
01878   case ARM::tInt_eh_sjlj_longjmp: {
01879     // ldr $scratch, [$src, #8]
01880     // mov sp, $scratch
01881     // ldr $scratch, [$src, #4]
01882     // ldr r7, [$src]
01883     // bx $scratch
01884     unsigned SrcReg = MI->getOperand(0).getReg();
01885     unsigned ScratchReg = MI->getOperand(1).getReg();
01886     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tLDRi)
01887       .addReg(ScratchReg)
01888       .addReg(SrcReg)
01889       // The offset immediate is #8. The operand value is scaled by 4 for the
01890       // tLDR instruction.
01891       .addImm(2)
01892       // Predicate.
01893       .addImm(ARMCC::AL)
01894       .addReg(0));
01895 
01896     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
01897       .addReg(ARM::SP)
01898       .addReg(ScratchReg)
01899       // Predicate.
01900       .addImm(ARMCC::AL)
01901       .addReg(0));
01902 
01903     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tLDRi)
01904       .addReg(ScratchReg)
01905       .addReg(SrcReg)
01906       .addImm(1)
01907       // Predicate.
01908       .addImm(ARMCC::AL)
01909       .addReg(0));
01910 
01911     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tLDRi)
01912       .addReg(ARM::R7)
01913       .addReg(SrcReg)
01914       .addImm(0)
01915       // Predicate.
01916       .addImm(ARMCC::AL)
01917       .addReg(0));
01918 
01919     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tBX)
01920       .addReg(ScratchReg)
01921       // Predicate.
01922       .addImm(ARMCC::AL)
01923       .addReg(0));
01924     return;
01925   }
01926   }
01927 
01928   MCInst TmpInst;
01929   LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
01930 
01931   EmitToStreamer(OutStreamer, TmpInst);
01932 }
01933 
01934 //===----------------------------------------------------------------------===//
01935 // Target Registry Stuff
01936 //===----------------------------------------------------------------------===//
01937 
01938 // Force static initialization.
01939 extern "C" void LLVMInitializeARMAsmPrinter() {
01940   RegisterAsmPrinter<ARMAsmPrinter> X(TheARMLETarget);
01941   RegisterAsmPrinter<ARMAsmPrinter> Y(TheARMBETarget);
01942   RegisterAsmPrinter<ARMAsmPrinter> A(TheThumbLETarget);
01943   RegisterAsmPrinter<ARMAsmPrinter> B(TheThumbBETarget);
01944 }