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ARMAsmPrinter.cpp
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00001 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file contains a printer that converts from our internal representation
00011 // of machine-dependent LLVM code to GAS-format ARM assembly language.
00012 //
00013 //===----------------------------------------------------------------------===//
00014 
00015 #include "ARMAsmPrinter.h"
00016 #include "ARM.h"
00017 #include "ARMConstantPoolValue.h"
00018 #include "ARMMachineFunctionInfo.h"
00019 #include "ARMTargetMachine.h"
00020 #include "ARMTargetObjectFile.h"
00021 #include "InstPrinter/ARMInstPrinter.h"
00022 #include "MCTargetDesc/ARMAddressingModes.h"
00023 #include "MCTargetDesc/ARMMCExpr.h"
00024 #include "llvm/ADT/SetVector.h"
00025 #include "llvm/ADT/SmallString.h"
00026 #include "llvm/CodeGen/MachineFunctionPass.h"
00027 #include "llvm/CodeGen/MachineJumpTableInfo.h"
00028 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
00029 #include "llvm/IR/Constants.h"
00030 #include "llvm/IR/DataLayout.h"
00031 #include "llvm/IR/DebugInfo.h"
00032 #include "llvm/IR/Mangler.h"
00033 #include "llvm/IR/Module.h"
00034 #include "llvm/IR/Type.h"
00035 #include "llvm/MC/MCAsmInfo.h"
00036 #include "llvm/MC/MCAssembler.h"
00037 #include "llvm/MC/MCContext.h"
00038 #include "llvm/MC/MCELFStreamer.h"
00039 #include "llvm/MC/MCInst.h"
00040 #include "llvm/MC/MCInstBuilder.h"
00041 #include "llvm/MC/MCObjectStreamer.h"
00042 #include "llvm/MC/MCSectionMachO.h"
00043 #include "llvm/MC/MCStreamer.h"
00044 #include "llvm/MC/MCSymbol.h"
00045 #include "llvm/Support/ARMBuildAttributes.h"
00046 #include "llvm/Support/TargetParser.h"
00047 #include "llvm/Support/COFF.h"
00048 #include "llvm/Support/CommandLine.h"
00049 #include "llvm/Support/Debug.h"
00050 #include "llvm/Support/ELF.h"
00051 #include "llvm/Support/ErrorHandling.h"
00052 #include "llvm/Support/TargetRegistry.h"
00053 #include "llvm/Support/raw_ostream.h"
00054 #include "llvm/Target/TargetMachine.h"
00055 #include <cctype>
00056 using namespace llvm;
00057 
00058 #define DEBUG_TYPE "asm-printer"
00059 
00060 ARMAsmPrinter::ARMAsmPrinter(TargetMachine &TM,
00061                              std::unique_ptr<MCStreamer> Streamer)
00062     : AsmPrinter(TM, std::move(Streamer)), AFI(nullptr), MCP(nullptr),
00063       InConstantPool(false) {}
00064 
00065 void ARMAsmPrinter::EmitFunctionBodyEnd() {
00066   // Make sure to terminate any constant pools that were at the end
00067   // of the function.
00068   if (!InConstantPool)
00069     return;
00070   InConstantPool = false;
00071   OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
00072 }
00073 
00074 void ARMAsmPrinter::EmitFunctionEntryLabel() {
00075   if (AFI->isThumbFunction()) {
00076     OutStreamer->EmitAssemblerFlag(MCAF_Code16);
00077     OutStreamer->EmitThumbFunc(CurrentFnSym);
00078   }
00079 
00080   OutStreamer->EmitLabel(CurrentFnSym);
00081 }
00082 
00083 void ARMAsmPrinter::EmitXXStructor(const Constant *CV) {
00084   uint64_t Size = TM.getDataLayout()->getTypeAllocSize(CV->getType());
00085   assert(Size && "C++ constructor pointer had zero size!");
00086 
00087   const GlobalValue *GV = dyn_cast<GlobalValue>(CV->stripPointerCasts());
00088   assert(GV && "C++ constructor pointer was not a GlobalValue!");
00089 
00090   const MCExpr *E = MCSymbolRefExpr::Create(GetARMGVSymbol(GV,
00091                                                            ARMII::MO_NO_FLAG),
00092                                             (Subtarget->isTargetELF()
00093                                              ? MCSymbolRefExpr::VK_ARM_TARGET1
00094                                              : MCSymbolRefExpr::VK_None),
00095                                             OutContext);
00096 
00097   OutStreamer->EmitValue(E, Size);
00098 }
00099 
00100 /// runOnMachineFunction - This uses the EmitInstruction()
00101 /// method to print assembly for each instruction.
00102 ///
00103 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
00104   AFI = MF.getInfo<ARMFunctionInfo>();
00105   MCP = MF.getConstantPool();
00106   Subtarget = &MF.getSubtarget<ARMSubtarget>();
00107 
00108   SetupMachineFunction(MF);
00109 
00110   if (Subtarget->isTargetCOFF()) {
00111     bool Internal = MF.getFunction()->hasInternalLinkage();
00112     COFF::SymbolStorageClass Scl = Internal ? COFF::IMAGE_SYM_CLASS_STATIC
00113                                             : COFF::IMAGE_SYM_CLASS_EXTERNAL;
00114     int Type = COFF::IMAGE_SYM_DTYPE_FUNCTION << COFF::SCT_COMPLEX_TYPE_SHIFT;
00115 
00116     OutStreamer->BeginCOFFSymbolDef(CurrentFnSym);
00117     OutStreamer->EmitCOFFSymbolStorageClass(Scl);
00118     OutStreamer->EmitCOFFSymbolType(Type);
00119     OutStreamer->EndCOFFSymbolDef();
00120   }
00121 
00122   // Emit the rest of the function body.
00123   EmitFunctionBody();
00124 
00125   // If we need V4T thumb mode Register Indirect Jump pads, emit them.
00126   // These are created per function, rather than per TU, since it's
00127   // relatively easy to exceed the thumb branch range within a TU.
00128   if (! ThumbIndirectPads.empty()) {
00129     OutStreamer->EmitAssemblerFlag(MCAF_Code16);
00130     EmitAlignment(1);
00131     for (unsigned i = 0, e = ThumbIndirectPads.size(); i < e; i++) {
00132       OutStreamer->EmitLabel(ThumbIndirectPads[i].second);
00133       EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tBX)
00134         .addReg(ThumbIndirectPads[i].first)
00135         // Add predicate operands.
00136         .addImm(ARMCC::AL)
00137         .addReg(0));
00138     }
00139     ThumbIndirectPads.clear();
00140   }
00141 
00142   // We didn't modify anything.
00143   return false;
00144 }
00145 
00146 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
00147                                  raw_ostream &O) {
00148   const MachineOperand &MO = MI->getOperand(OpNum);
00149   unsigned TF = MO.getTargetFlags();
00150 
00151   switch (MO.getType()) {
00152   default: llvm_unreachable("<unknown operand type>");
00153   case MachineOperand::MO_Register: {
00154     unsigned Reg = MO.getReg();
00155     assert(TargetRegisterInfo::isPhysicalRegister(Reg));
00156     assert(!MO.getSubReg() && "Subregs should be eliminated!");
00157     if(ARM::GPRPairRegClass.contains(Reg)) {
00158       const MachineFunction &MF = *MI->getParent()->getParent();
00159       const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
00160       Reg = TRI->getSubReg(Reg, ARM::gsub_0);
00161     }
00162     O << ARMInstPrinter::getRegisterName(Reg);
00163     break;
00164   }
00165   case MachineOperand::MO_Immediate: {
00166     int64_t Imm = MO.getImm();
00167     O << '#';
00168     if (TF == ARMII::MO_LO16)
00169       O << ":lower16:";
00170     else if (TF == ARMII::MO_HI16)
00171       O << ":upper16:";
00172     O << Imm;
00173     break;
00174   }
00175   case MachineOperand::MO_MachineBasicBlock:
00176     O << *MO.getMBB()->getSymbol();
00177     return;
00178   case MachineOperand::MO_GlobalAddress: {
00179     const GlobalValue *GV = MO.getGlobal();
00180     if (TF & ARMII::MO_LO16)
00181       O << ":lower16:";
00182     else if (TF & ARMII::MO_HI16)
00183       O << ":upper16:";
00184     O << *GetARMGVSymbol(GV, TF);
00185 
00186     printOffset(MO.getOffset(), O);
00187     if (TF == ARMII::MO_PLT)
00188       O << "(PLT)";
00189     break;
00190   }
00191   case MachineOperand::MO_ConstantPoolIndex:
00192     O << *GetCPISymbol(MO.getIndex());
00193     break;
00194   }
00195 }
00196 
00197 //===--------------------------------------------------------------------===//
00198 
00199 MCSymbol *ARMAsmPrinter::
00200 GetARMJTIPICJumpTableLabel(unsigned uid) const {
00201   const DataLayout *DL = TM.getDataLayout();
00202   SmallString<60> Name;
00203   raw_svector_ostream(Name) << DL->getPrivateGlobalPrefix() << "JTI"
00204                             << getFunctionNumber() << '_' << uid;
00205   return OutContext.getOrCreateSymbol(Name);
00206 }
00207 
00208 
00209 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel() const {
00210   const DataLayout *DL = TM.getDataLayout();
00211   SmallString<60> Name;
00212   raw_svector_ostream(Name) << DL->getPrivateGlobalPrefix() << "SJLJEH"
00213     << getFunctionNumber();
00214   return OutContext.getOrCreateSymbol(Name);
00215 }
00216 
00217 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
00218                                     unsigned AsmVariant, const char *ExtraCode,
00219                                     raw_ostream &O) {
00220   // Does this asm operand have a single letter operand modifier?
00221   if (ExtraCode && ExtraCode[0]) {
00222     if (ExtraCode[1] != 0) return true; // Unknown modifier.
00223 
00224     switch (ExtraCode[0]) {
00225     default:
00226       // See if this is a generic print operand
00227       return AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O);
00228     case 'a': // Print as a memory address.
00229       if (MI->getOperand(OpNum).isReg()) {
00230         O << "["
00231           << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
00232           << "]";
00233         return false;
00234       }
00235       // Fallthrough
00236     case 'c': // Don't print "#" before an immediate operand.
00237       if (!MI->getOperand(OpNum).isImm())
00238         return true;
00239       O << MI->getOperand(OpNum).getImm();
00240       return false;
00241     case 'P': // Print a VFP double precision register.
00242     case 'q': // Print a NEON quad precision register.
00243       printOperand(MI, OpNum, O);
00244       return false;
00245     case 'y': // Print a VFP single precision register as indexed double.
00246       if (MI->getOperand(OpNum).isReg()) {
00247         unsigned Reg = MI->getOperand(OpNum).getReg();
00248         const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
00249         // Find the 'd' register that has this 's' register as a sub-register,
00250         // and determine the lane number.
00251         for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
00252           if (!ARM::DPRRegClass.contains(*SR))
00253             continue;
00254           bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
00255           O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");
00256           return false;
00257         }
00258       }
00259       return true;
00260     case 'B': // Bitwise inverse of integer or symbol without a preceding #.
00261       if (!MI->getOperand(OpNum).isImm())
00262         return true;
00263       O << ~(MI->getOperand(OpNum).getImm());
00264       return false;
00265     case 'L': // The low 16 bits of an immediate constant.
00266       if (!MI->getOperand(OpNum).isImm())
00267         return true;
00268       O << (MI->getOperand(OpNum).getImm() & 0xffff);
00269       return false;
00270     case 'M': { // A register range suitable for LDM/STM.
00271       if (!MI->getOperand(OpNum).isReg())
00272         return true;
00273       const MachineOperand &MO = MI->getOperand(OpNum);
00274       unsigned RegBegin = MO.getReg();
00275       // This takes advantage of the 2 operand-ness of ldm/stm and that we've
00276       // already got the operands in registers that are operands to the
00277       // inline asm statement.
00278       O << "{";
00279       if (ARM::GPRPairRegClass.contains(RegBegin)) {
00280         const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
00281         unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
00282         O << ARMInstPrinter::getRegisterName(Reg0) << ", ";
00283         RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1);
00284       }
00285       O << ARMInstPrinter::getRegisterName(RegBegin);
00286 
00287       // FIXME: The register allocator not only may not have given us the
00288       // registers in sequence, but may not be in ascending registers. This
00289       // will require changes in the register allocator that'll need to be
00290       // propagated down here if the operands change.
00291       unsigned RegOps = OpNum + 1;
00292       while (MI->getOperand(RegOps).isReg()) {
00293         O << ", "
00294           << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
00295         RegOps++;
00296       }
00297 
00298       O << "}";
00299 
00300       return false;
00301     }
00302     case 'R': // The most significant register of a pair.
00303     case 'Q': { // The least significant register of a pair.
00304       if (OpNum == 0)
00305         return true;
00306       const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
00307       if (!FlagsOP.isImm())
00308         return true;
00309       unsigned Flags = FlagsOP.getImm();
00310 
00311       // This operand may not be the one that actually provides the register. If
00312       // it's tied to a previous one then we should refer instead to that one
00313       // for registers and their classes.
00314       unsigned TiedIdx;
00315       if (InlineAsm::isUseOperandTiedToDef(Flags, TiedIdx)) {
00316         for (OpNum = InlineAsm::MIOp_FirstOperand; TiedIdx; --TiedIdx) {
00317           unsigned OpFlags = MI->getOperand(OpNum).getImm();
00318           OpNum += InlineAsm::getNumOperandRegisters(OpFlags) + 1;
00319         }
00320         Flags = MI->getOperand(OpNum).getImm();
00321 
00322         // Later code expects OpNum to be pointing at the register rather than
00323         // the flags.
00324         OpNum += 1;
00325       }
00326 
00327       unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
00328       unsigned RC;
00329       InlineAsm::hasRegClassConstraint(Flags, RC);
00330       if (RC == ARM::GPRPairRegClassID) {
00331         if (NumVals != 1)
00332           return true;
00333         const MachineOperand &MO = MI->getOperand(OpNum);
00334         if (!MO.isReg())
00335           return true;
00336         const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
00337         unsigned Reg = TRI->getSubReg(MO.getReg(), ExtraCode[0] == 'Q' ?
00338             ARM::gsub_0 : ARM::gsub_1);
00339         O << ARMInstPrinter::getRegisterName(Reg);
00340         return false;
00341       }
00342       if (NumVals != 2)
00343         return true;
00344       unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
00345       if (RegOp >= MI->getNumOperands())
00346         return true;
00347       const MachineOperand &MO = MI->getOperand(RegOp);
00348       if (!MO.isReg())
00349         return true;
00350       unsigned Reg = MO.getReg();
00351       O << ARMInstPrinter::getRegisterName(Reg);
00352       return false;
00353     }
00354 
00355     case 'e': // The low doubleword register of a NEON quad register.
00356     case 'f': { // The high doubleword register of a NEON quad register.
00357       if (!MI->getOperand(OpNum).isReg())
00358         return true;
00359       unsigned Reg = MI->getOperand(OpNum).getReg();
00360       if (!ARM::QPRRegClass.contains(Reg))
00361         return true;
00362       const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
00363       unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
00364                                        ARM::dsub_0 : ARM::dsub_1);
00365       O << ARMInstPrinter::getRegisterName(SubReg);
00366       return false;
00367     }
00368 
00369     // This modifier is not yet supported.
00370     case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
00371       return true;
00372     case 'H': { // The highest-numbered register of a pair.
00373       const MachineOperand &MO = MI->getOperand(OpNum);
00374       if (!MO.isReg())
00375         return true;
00376       const MachineFunction &MF = *MI->getParent()->getParent();
00377       const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
00378       unsigned Reg = MO.getReg();
00379       if(!ARM::GPRPairRegClass.contains(Reg))
00380         return false;
00381       Reg = TRI->getSubReg(Reg, ARM::gsub_1);
00382       O << ARMInstPrinter::getRegisterName(Reg);
00383       return false;
00384     }
00385     }
00386   }
00387 
00388   printOperand(MI, OpNum, O);
00389   return false;
00390 }
00391 
00392 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
00393                                           unsigned OpNum, unsigned AsmVariant,
00394                                           const char *ExtraCode,
00395                                           raw_ostream &O) {
00396   // Does this asm operand have a single letter operand modifier?
00397   if (ExtraCode && ExtraCode[0]) {
00398     if (ExtraCode[1] != 0) return true; // Unknown modifier.
00399 
00400     switch (ExtraCode[0]) {
00401       case 'A': // A memory operand for a VLD1/VST1 instruction.
00402       default: return true;  // Unknown modifier.
00403       case 'm': // The base register of a memory operand.
00404         if (!MI->getOperand(OpNum).isReg())
00405           return true;
00406         O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
00407         return false;
00408     }
00409   }
00410 
00411   const MachineOperand &MO = MI->getOperand(OpNum);
00412   assert(MO.isReg() && "unexpected inline asm memory operand");
00413   O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
00414   return false;
00415 }
00416 
00417 static bool isThumb(const MCSubtargetInfo& STI) {
00418   return STI.getFeatureBits()[ARM::ModeThumb];
00419 }
00420 
00421 void ARMAsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo &StartInfo,
00422                                      const MCSubtargetInfo *EndInfo) const {
00423   // If either end mode is unknown (EndInfo == NULL) or different than
00424   // the start mode, then restore the start mode.
00425   const bool WasThumb = isThumb(StartInfo);
00426   if (!EndInfo || WasThumb != isThumb(*EndInfo)) {
00427     OutStreamer->EmitAssemblerFlag(WasThumb ? MCAF_Code16 : MCAF_Code32);
00428   }
00429 }
00430 
00431 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
00432   Triple TT(TM.getTargetTriple());
00433   // Use unified assembler syntax.
00434   OutStreamer->EmitAssemblerFlag(MCAF_SyntaxUnified);
00435 
00436   // Emit ARM Build Attributes
00437   if (TT.isOSBinFormatELF())
00438     emitAttributes();
00439 
00440   // Use the triple's architecture and subarchitecture to determine
00441   // if we're thumb for the purposes of the top level code16 assembler
00442   // flag.
00443   bool isThumb = TT.getArch() == Triple::thumb ||
00444                  TT.getArch() == Triple::thumbeb ||
00445                  TT.getSubArch() == Triple::ARMSubArch_v7m ||
00446                  TT.getSubArch() == Triple::ARMSubArch_v6m;
00447   if (!M.getModuleInlineAsm().empty() && isThumb)
00448     OutStreamer->EmitAssemblerFlag(MCAF_Code16);
00449 }
00450 
00451 static void
00452 emitNonLazySymbolPointer(MCStreamer &OutStreamer, MCSymbol *StubLabel,
00453                          MachineModuleInfoImpl::StubValueTy &MCSym) {
00454   // L_foo$stub:
00455   OutStreamer.EmitLabel(StubLabel);
00456   //   .indirect_symbol _foo
00457   OutStreamer.EmitSymbolAttribute(MCSym.getPointer(), MCSA_IndirectSymbol);
00458 
00459   if (MCSym.getInt())
00460     // External to current translation unit.
00461     OutStreamer.EmitIntValue(0, 4/*size*/);
00462   else
00463     // Internal to current translation unit.
00464     //
00465     // When we place the LSDA into the TEXT section, the type info
00466     // pointers need to be indirect and pc-rel. We accomplish this by
00467     // using NLPs; however, sometimes the types are local to the file.
00468     // We need to fill in the value for the NLP in those cases.
00469     OutStreamer.EmitValue(
00470         MCSymbolRefExpr::Create(MCSym.getPointer(), OutStreamer.getContext()),
00471         4 /*size*/);
00472 }
00473 
00474 
00475 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
00476   Triple TT(TM.getTargetTriple());
00477   if (TT.isOSBinFormatMachO()) {
00478     // All darwin targets use mach-o.
00479     const TargetLoweringObjectFileMachO &TLOFMacho =
00480       static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
00481     MachineModuleInfoMachO &MMIMacho =
00482       MMI->getObjFileInfo<MachineModuleInfoMachO>();
00483 
00484     // Output non-lazy-pointers for external and common global variables.
00485     MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
00486 
00487     if (!Stubs.empty()) {
00488       // Switch with ".non_lazy_symbol_pointer" directive.
00489       OutStreamer->SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
00490       EmitAlignment(2);
00491 
00492       for (auto &Stub : Stubs)
00493         emitNonLazySymbolPointer(*OutStreamer, Stub.first, Stub.second);
00494 
00495       Stubs.clear();
00496       OutStreamer->AddBlankLine();
00497     }
00498 
00499     Stubs = MMIMacho.GetHiddenGVStubList();
00500     if (!Stubs.empty()) {
00501       OutStreamer->SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
00502       EmitAlignment(2);
00503 
00504       for (auto &Stub : Stubs)
00505         emitNonLazySymbolPointer(*OutStreamer, Stub.first, Stub.second);
00506 
00507       Stubs.clear();
00508       OutStreamer->AddBlankLine();
00509     }
00510 
00511     // Funny Darwin hack: This flag tells the linker that no global symbols
00512     // contain code that falls through to other global symbols (e.g. the obvious
00513     // implementation of multiple entry points).  If this doesn't occur, the
00514     // linker can safely perform dead code stripping.  Since LLVM never
00515     // generates code that does this, it is always safe to set.
00516     OutStreamer->EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
00517   }
00518 }
00519 
00520 //===----------------------------------------------------------------------===//
00521 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
00522 // FIXME:
00523 // The following seem like one-off assembler flags, but they actually need
00524 // to appear in the .ARM.attributes section in ELF.
00525 // Instead of subclassing the MCELFStreamer, we do the work here.
00526 
00527 static ARMBuildAttrs::CPUArch getArchForCPU(StringRef CPU,
00528                                             const ARMSubtarget *Subtarget) {
00529   if (CPU == "xscale")
00530     return ARMBuildAttrs::v5TEJ;
00531 
00532   if (Subtarget->hasV8Ops())
00533     return ARMBuildAttrs::v8;
00534   else if (Subtarget->hasV7Ops()) {
00535     if (Subtarget->isMClass() && Subtarget->hasThumb2DSP())
00536       return ARMBuildAttrs::v7E_M;
00537     return ARMBuildAttrs::v7;
00538   } else if (Subtarget->hasV6T2Ops())
00539     return ARMBuildAttrs::v6T2;
00540   else if (Subtarget->hasV6MOps())
00541     return ARMBuildAttrs::v6S_M;
00542   else if (Subtarget->hasV6Ops())
00543     return ARMBuildAttrs::v6;
00544   else if (Subtarget->hasV5TEOps())
00545     return ARMBuildAttrs::v5TE;
00546   else if (Subtarget->hasV5TOps())
00547     return ARMBuildAttrs::v5T;
00548   else if (Subtarget->hasV4TOps())
00549     return ARMBuildAttrs::v4T;
00550   else
00551     return ARMBuildAttrs::v4;
00552 }
00553 
00554 void ARMAsmPrinter::emitAttributes() {
00555   MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
00556   ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
00557 
00558   ATS.emitTextAttribute(ARMBuildAttrs::conformance, "2.09");
00559 
00560   ATS.switchVendor("aeabi");
00561 
00562   // Compute ARM ELF Attributes based on the default subtarget that
00563   // we'd have constructed. The existing ARM behavior isn't LTO clean
00564   // anyhow.
00565   // FIXME: For ifunc related functions we could iterate over and look
00566   // for a feature string that doesn't match the default one.
00567   StringRef TT = TM.getTargetTriple();
00568   StringRef CPU = TM.getTargetCPU();
00569   StringRef FS = TM.getTargetFeatureString();
00570   std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
00571   if (!FS.empty()) {
00572     if (!ArchFS.empty())
00573       ArchFS = (Twine(ArchFS) + "," + FS).str();
00574     else
00575       ArchFS = FS;
00576   }
00577   const ARMBaseTargetMachine &ATM =
00578       static_cast<const ARMBaseTargetMachine &>(TM);
00579   const ARMSubtarget STI(TT, CPU, ArchFS, ATM, ATM.isLittleEndian());
00580 
00581   std::string CPUString = STI.getCPUString();
00582 
00583   if (CPUString.find("generic") != 0) { //CPUString doesn't start with "generic"
00584     // FIXME: remove krait check when GNU tools support krait cpu
00585     if (STI.isKrait()) {
00586       ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a9");
00587       // We consider krait as a "cortex-a9" + hwdiv CPU
00588       // Enable hwdiv through ".arch_extension idiv"
00589       if (STI.hasDivide() || STI.hasDivideInARMMode())
00590         ATS.emitArchExtension(ARM::AEK_HWDIV);
00591     } else
00592       ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, CPUString);
00593   }
00594 
00595   ATS.emitAttribute(ARMBuildAttrs::CPU_arch, getArchForCPU(CPUString, &STI));
00596 
00597   // Tag_CPU_arch_profile must have the default value of 0 when "Architecture
00598   // profile is not applicable (e.g. pre v7, or cross-profile code)".
00599   if (STI.hasV7Ops()) {
00600     if (STI.isAClass()) {
00601       ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
00602                         ARMBuildAttrs::ApplicationProfile);
00603     } else if (STI.isRClass()) {
00604       ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
00605                         ARMBuildAttrs::RealTimeProfile);
00606     } else if (STI.isMClass()) {
00607       ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
00608                         ARMBuildAttrs::MicroControllerProfile);
00609     }
00610   }
00611 
00612   ATS.emitAttribute(ARMBuildAttrs::ARM_ISA_use,
00613                     STI.hasARMOps() ? ARMBuildAttrs::Allowed
00614                                     : ARMBuildAttrs::Not_Allowed);
00615   if (STI.isThumb1Only()) {
00616     ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use, ARMBuildAttrs::Allowed);
00617   } else if (STI.hasThumb2()) {
00618     ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
00619                       ARMBuildAttrs::AllowThumb32);
00620   }
00621 
00622   if (STI.hasNEON()) {
00623     /* NEON is not exactly a VFP architecture, but GAS emit one of
00624      * neon/neon-fp-armv8/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
00625     if (STI.hasFPARMv8()) {
00626       if (STI.hasCrypto())
00627         ATS.emitFPU(ARM::FK_CRYPTO_NEON_FP_ARMV8);
00628       else
00629         ATS.emitFPU(ARM::FK_NEON_FP_ARMV8);
00630     } else if (STI.hasVFP4())
00631       ATS.emitFPU(ARM::FK_NEON_VFPV4);
00632     else
00633       ATS.emitFPU(ARM::FK_NEON);
00634     // Emit Tag_Advanced_SIMD_arch for ARMv8 architecture
00635     if (STI.hasV8Ops())
00636       ATS.emitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
00637                         STI.hasV8_1aOps() ? ARMBuildAttrs::AllowNeonARMv8_1a:
00638                                             ARMBuildAttrs::AllowNeonARMv8);
00639   } else {
00640     if (STI.hasFPARMv8())
00641       // FPv5 and FP-ARMv8 have the same instructions, so are modeled as one
00642       // FPU, but there are two different names for it depending on the CPU.
00643       ATS.emitFPU(STI.hasD16() ? ARM::FK_FPV5_D16 : ARM::FK_FP_ARMV8);
00644     else if (STI.hasVFP4())
00645       ATS.emitFPU(STI.hasD16() ? ARM::FK_VFPV4_D16 : ARM::FK_VFPV4);
00646     else if (STI.hasVFP3())
00647       ATS.emitFPU(STI.hasD16() ? ARM::FK_VFPV3_D16 : ARM::FK_VFPV3);
00648     else if (STI.hasVFP2())
00649       ATS.emitFPU(ARM::FK_VFPV2);
00650   }
00651 
00652   if (TM.getRelocationModel() == Reloc::PIC_) {
00653     // PIC specific attributes.
00654     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RW_data,
00655                       ARMBuildAttrs::AddressRWPCRel);
00656     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RO_data,
00657                       ARMBuildAttrs::AddressROPCRel);
00658     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_GOT_use,
00659                       ARMBuildAttrs::AddressGOT);
00660   } else {
00661     // Allow direct addressing of imported data for all other relocation models.
00662     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_GOT_use,
00663                       ARMBuildAttrs::AddressDirect);
00664   }
00665 
00666   // Signal various FP modes.
00667   if (!TM.Options.UnsafeFPMath) {
00668     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
00669                       ARMBuildAttrs::IEEEDenormals);
00670     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_exceptions, ARMBuildAttrs::Allowed);
00671 
00672     // If the user has permitted this code to choose the IEEE 754
00673     // rounding at run-time, emit the rounding attribute.
00674     if (TM.Options.HonorSignDependentRoundingFPMathOption)
00675       ATS.emitAttribute(ARMBuildAttrs::ABI_FP_rounding, ARMBuildAttrs::Allowed);
00676   } else {
00677     if (!STI.hasVFP2()) {
00678       // When the target doesn't have an FPU (by design or
00679       // intention), the assumptions made on the software support
00680       // mirror that of the equivalent hardware support *if it
00681       // existed*. For v7 and better we indicate that denormals are
00682       // flushed preserving sign, and for V6 we indicate that
00683       // denormals are flushed to positive zero.
00684       if (STI.hasV7Ops())
00685         ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
00686                           ARMBuildAttrs::PreserveFPSign);
00687     } else if (STI.hasVFP3()) {
00688       // In VFPv4, VFPv4U, VFPv3, or VFPv3U, it is preserved. That is,
00689       // the sign bit of the zero matches the sign bit of the input or
00690       // result that is being flushed to zero.
00691       ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
00692                         ARMBuildAttrs::PreserveFPSign);
00693     }
00694     // For VFPv2 implementations it is implementation defined as
00695     // to whether denormals are flushed to positive zero or to
00696     // whatever the sign of zero is (ARM v7AR ARM 2.7.5). Historically
00697     // LLVM has chosen to flush this to positive zero (most likely for
00698     // GCC compatibility), so that's the chosen value here (the
00699     // absence of its emission implies zero).
00700   }
00701 
00702   // TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath is the
00703   // equivalent of GCC's -ffinite-math-only flag.
00704   if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
00705     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
00706                       ARMBuildAttrs::Allowed);
00707   else
00708     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
00709                       ARMBuildAttrs::AllowIEE754);
00710 
00711   if (STI.allowsUnalignedMem())
00712     ATS.emitAttribute(ARMBuildAttrs::CPU_unaligned_access,
00713                       ARMBuildAttrs::Allowed);
00714   else
00715     ATS.emitAttribute(ARMBuildAttrs::CPU_unaligned_access,
00716                       ARMBuildAttrs::Not_Allowed);
00717 
00718   // FIXME: add more flags to ARMBuildAttributes.h
00719   // 8-bytes alignment stuff.
00720   ATS.emitAttribute(ARMBuildAttrs::ABI_align_needed, 1);
00721   ATS.emitAttribute(ARMBuildAttrs::ABI_align_preserved, 1);
00722 
00723   // ABI_HardFP_use attribute to indicate single precision FP.
00724   if (STI.isFPOnlySP())
00725     ATS.emitAttribute(ARMBuildAttrs::ABI_HardFP_use,
00726                       ARMBuildAttrs::HardFPSinglePrecision);
00727 
00728   // Hard float.  Use both S and D registers and conform to AAPCS-VFP.
00729   if (STI.isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard)
00730     ATS.emitAttribute(ARMBuildAttrs::ABI_VFP_args, ARMBuildAttrs::HardFPAAPCS);
00731 
00732   // FIXME: Should we signal R9 usage?
00733 
00734   if (STI.hasFP16())
00735     ATS.emitAttribute(ARMBuildAttrs::FP_HP_extension, ARMBuildAttrs::AllowHPFP);
00736 
00737   // FIXME: To support emitting this build attribute as GCC does, the
00738   // -mfp16-format option and associated plumbing must be
00739   // supported. For now the __fp16 type is exposed by default, so this
00740   // attribute should be emitted with value 1.
00741   ATS.emitAttribute(ARMBuildAttrs::ABI_FP_16bit_format,
00742                     ARMBuildAttrs::FP16FormatIEEE);
00743 
00744   if (STI.hasMPExtension())
00745     ATS.emitAttribute(ARMBuildAttrs::MPextension_use, ARMBuildAttrs::AllowMP);
00746 
00747   // Hardware divide in ARM mode is part of base arch, starting from ARMv8.
00748   // If only Thumb hwdiv is present, it must also be in base arch (ARMv7-R/M).
00749   // It is not possible to produce DisallowDIV: if hwdiv is present in the base
00750   // arch, supplying -hwdiv downgrades the effective arch, via ClearImpliedBits.
00751   // AllowDIVExt is only emitted if hwdiv isn't available in the base arch;
00752   // otherwise, the default value (AllowDIVIfExists) applies.
00753   if (STI.hasDivideInARMMode() && !STI.hasV8Ops())
00754     ATS.emitAttribute(ARMBuildAttrs::DIV_use, ARMBuildAttrs::AllowDIVExt);
00755 
00756   if (MMI) {
00757     if (const Module *SourceModule = MMI->getModule()) {
00758       // ABI_PCS_wchar_t to indicate wchar_t width
00759       // FIXME: There is no way to emit value 0 (wchar_t prohibited).
00760       if (auto WCharWidthValue = mdconst::extract_or_null<ConstantInt>(
00761               SourceModule->getModuleFlag("wchar_size"))) {
00762         int WCharWidth = WCharWidthValue->getZExtValue();
00763         assert((WCharWidth == 2 || WCharWidth == 4) &&
00764                "wchar_t width must be 2 or 4 bytes");
00765         ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_wchar_t, WCharWidth);
00766       }
00767 
00768       // ABI_enum_size to indicate enum width
00769       // FIXME: There is no way to emit value 0 (enums prohibited) or value 3
00770       //        (all enums contain a value needing 32 bits to encode).
00771       if (auto EnumWidthValue = mdconst::extract_or_null<ConstantInt>(
00772               SourceModule->getModuleFlag("min_enum_size"))) {
00773         int EnumWidth = EnumWidthValue->getZExtValue();
00774         assert((EnumWidth == 1 || EnumWidth == 4) &&
00775                "Minimum enum width must be 1 or 4 bytes");
00776         int EnumBuildAttr = EnumWidth == 1 ? 1 : 2;
00777         ATS.emitAttribute(ARMBuildAttrs::ABI_enum_size, EnumBuildAttr);
00778       }
00779     }
00780   }
00781 
00782   // TODO: We currently only support either reserving the register, or treating
00783   // it as another callee-saved register, but not as SB or a TLS pointer; It
00784   // would instead be nicer to push this from the frontend as metadata, as we do
00785   // for the wchar and enum size tags
00786   if (STI.isR9Reserved())
00787     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use, ARMBuildAttrs::R9Reserved);
00788   else
00789     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use, ARMBuildAttrs::R9IsGPR);
00790 
00791   if (STI.hasTrustZone() && STI.hasVirtualization())
00792     ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
00793                       ARMBuildAttrs::AllowTZVirtualization);
00794   else if (STI.hasTrustZone())
00795     ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
00796                       ARMBuildAttrs::AllowTZ);
00797   else if (STI.hasVirtualization())
00798     ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
00799                       ARMBuildAttrs::AllowVirtualization);
00800 
00801   ATS.finishAttributeSection();
00802 }
00803 
00804 //===----------------------------------------------------------------------===//
00805 
00806 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
00807                              unsigned LabelId, MCContext &Ctx) {
00808 
00809   MCSymbol *Label = Ctx.getOrCreateSymbol(Twine(Prefix)
00810                        + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
00811   return Label;
00812 }
00813 
00814 static MCSymbolRefExpr::VariantKind
00815 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
00816   switch (Modifier) {
00817   case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
00818   case ARMCP::TLSGD:       return MCSymbolRefExpr::VK_TLSGD;
00819   case ARMCP::TPOFF:       return MCSymbolRefExpr::VK_TPOFF;
00820   case ARMCP::GOTTPOFF:    return MCSymbolRefExpr::VK_GOTTPOFF;
00821   case ARMCP::GOT:         return MCSymbolRefExpr::VK_GOT;
00822   case ARMCP::GOTOFF:      return MCSymbolRefExpr::VK_GOTOFF;
00823   }
00824   llvm_unreachable("Invalid ARMCPModifier!");
00825 }
00826 
00827 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV,
00828                                         unsigned char TargetFlags) {
00829   if (Subtarget->isTargetMachO()) {
00830     bool IsIndirect = (TargetFlags & ARMII::MO_NONLAZY) &&
00831       Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
00832 
00833     if (!IsIndirect)
00834       return getSymbol(GV);
00835 
00836     // FIXME: Remove this when Darwin transition to @GOT like syntax.
00837     MCSymbol *MCSym = getSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
00838     MachineModuleInfoMachO &MMIMachO =
00839       MMI->getObjFileInfo<MachineModuleInfoMachO>();
00840     MachineModuleInfoImpl::StubValueTy &StubSym =
00841       GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym)
00842                                 : MMIMachO.getGVStubEntry(MCSym);
00843     if (!StubSym.getPointer())
00844       StubSym = MachineModuleInfoImpl::StubValueTy(getSymbol(GV),
00845                                                    !GV->hasInternalLinkage());
00846     return MCSym;
00847   } else if (Subtarget->isTargetCOFF()) {
00848     assert(Subtarget->isTargetWindows() &&
00849            "Windows is the only supported COFF target");
00850 
00851     bool IsIndirect = (TargetFlags & ARMII::MO_DLLIMPORT);
00852     if (!IsIndirect)
00853       return getSymbol(GV);
00854 
00855     SmallString<128> Name;
00856     Name = "__imp_";
00857     getNameWithPrefix(Name, GV);
00858 
00859     return OutContext.getOrCreateSymbol(Name);
00860   } else if (Subtarget->isTargetELF()) {
00861     return getSymbol(GV);
00862   }
00863   llvm_unreachable("unexpected target");
00864 }
00865 
00866 void ARMAsmPrinter::
00867 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
00868   const DataLayout *DL = TM.getDataLayout();
00869   int Size = TM.getDataLayout()->getTypeAllocSize(MCPV->getType());
00870 
00871   ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
00872 
00873   MCSymbol *MCSym;
00874   if (ACPV->isLSDA()) {
00875     MCSym = getCurExceptionSym();
00876   } else if (ACPV->isBlockAddress()) {
00877     const BlockAddress *BA =
00878       cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
00879     MCSym = GetBlockAddressSymbol(BA);
00880   } else if (ACPV->isGlobalValue()) {
00881     const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
00882 
00883     // On Darwin, const-pool entries may get the "FOO$non_lazy_ptr" mangling, so
00884     // flag the global as MO_NONLAZY.
00885     unsigned char TF = Subtarget->isTargetMachO() ? ARMII::MO_NONLAZY : 0;
00886     MCSym = GetARMGVSymbol(GV, TF);
00887   } else if (ACPV->isMachineBasicBlock()) {
00888     const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
00889     MCSym = MBB->getSymbol();
00890   } else {
00891     assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
00892     const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
00893     MCSym = GetExternalSymbolSymbol(Sym);
00894   }
00895 
00896   // Create an MCSymbol for the reference.
00897   const MCExpr *Expr =
00898     MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
00899                             OutContext);
00900 
00901   if (ACPV->getPCAdjustment()) {
00902     MCSymbol *PCLabel = getPICLabel(DL->getPrivateGlobalPrefix(),
00903                                     getFunctionNumber(),
00904                                     ACPV->getLabelId(),
00905                                     OutContext);
00906     const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
00907     PCRelExpr =
00908       MCBinaryExpr::CreateAdd(PCRelExpr,
00909                               MCConstantExpr::Create(ACPV->getPCAdjustment(),
00910                                                      OutContext),
00911                               OutContext);
00912     if (ACPV->mustAddCurrentAddress()) {
00913       // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
00914       // label, so just emit a local label end reference that instead.
00915       MCSymbol *DotSym = OutContext.createTempSymbol();
00916       OutStreamer->EmitLabel(DotSym);
00917       const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
00918       PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
00919     }
00920     Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
00921   }
00922   OutStreamer->EmitValue(Expr, Size);
00923 }
00924 
00925 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
00926   unsigned Opcode = MI->getOpcode();
00927   int OpNum = 1;
00928   if (Opcode == ARM::BR_JTadd)
00929     OpNum = 2;
00930   else if (Opcode == ARM::BR_JTm)
00931     OpNum = 3;
00932 
00933   const MachineOperand &MO1 = MI->getOperand(OpNum);
00934   unsigned JTI = MO1.getIndex();
00935 
00936   // Emit a label for the jump table.
00937   MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
00938   OutStreamer->EmitLabel(JTISymbol);
00939 
00940   // Mark the jump table as data-in-code.
00941   OutStreamer->EmitDataRegion(MCDR_DataRegionJT32);
00942 
00943   // Emit each entry of the table.
00944   const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
00945   const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
00946   const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
00947 
00948   for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
00949     MachineBasicBlock *MBB = JTBBs[i];
00950     // Construct an MCExpr for the entry. We want a value of the form:
00951     // (BasicBlockAddr - TableBeginAddr)
00952     //
00953     // For example, a table with entries jumping to basic blocks BB0 and BB1
00954     // would look like:
00955     // LJTI_0_0:
00956     //    .word (LBB0 - LJTI_0_0)
00957     //    .word (LBB1 - LJTI_0_0)
00958     const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
00959 
00960     if (TM.getRelocationModel() == Reloc::PIC_)
00961       Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
00962                                                                    OutContext),
00963                                      OutContext);
00964     // If we're generating a table of Thumb addresses in static relocation
00965     // model, we need to add one to keep interworking correctly.
00966     else if (AFI->isThumbFunction())
00967       Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(1,OutContext),
00968                                      OutContext);
00969     OutStreamer->EmitValue(Expr, 4);
00970   }
00971   // Mark the end of jump table data-in-code region.
00972   OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
00973 }
00974 
00975 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
00976   unsigned Opcode = MI->getOpcode();
00977   int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
00978   const MachineOperand &MO1 = MI->getOperand(OpNum);
00979   unsigned JTI = MO1.getIndex();
00980 
00981   MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
00982   OutStreamer->EmitLabel(JTISymbol);
00983 
00984   // Emit each entry of the table.
00985   const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
00986   const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
00987   const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
00988   unsigned OffsetWidth = 4;
00989   if (MI->getOpcode() == ARM::t2TBB_JT) {
00990     OffsetWidth = 1;
00991     // Mark the jump table as data-in-code.
00992     OutStreamer->EmitDataRegion(MCDR_DataRegionJT8);
00993   } else if (MI->getOpcode() == ARM::t2TBH_JT) {
00994     OffsetWidth = 2;
00995     // Mark the jump table as data-in-code.
00996     OutStreamer->EmitDataRegion(MCDR_DataRegionJT16);
00997   }
00998 
00999   for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
01000     MachineBasicBlock *MBB = JTBBs[i];
01001     const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
01002                                                           OutContext);
01003     // If this isn't a TBB or TBH, the entries are direct branch instructions.
01004     if (OffsetWidth == 4) {
01005       EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2B)
01006         .addExpr(MBBSymbolExpr)
01007         .addImm(ARMCC::AL)
01008         .addReg(0));
01009       continue;
01010     }
01011     // Otherwise it's an offset from the dispatch instruction. Construct an
01012     // MCExpr for the entry. We want a value of the form:
01013     // (BasicBlockAddr - TableBeginAddr) / 2
01014     //
01015     // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
01016     // would look like:
01017     // LJTI_0_0:
01018     //    .byte (LBB0 - LJTI_0_0) / 2
01019     //    .byte (LBB1 - LJTI_0_0) / 2
01020     const MCExpr *Expr =
01021       MCBinaryExpr::CreateSub(MBBSymbolExpr,
01022                               MCSymbolRefExpr::Create(JTISymbol, OutContext),
01023                               OutContext);
01024     Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
01025                                    OutContext);
01026     OutStreamer->EmitValue(Expr, OffsetWidth);
01027   }
01028   // Mark the end of jump table data-in-code region. 32-bit offsets use
01029   // actual branch instructions here, so we don't mark those as a data-region
01030   // at all.
01031   if (OffsetWidth != 4)
01032     OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
01033 }
01034 
01035 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
01036   assert(MI->getFlag(MachineInstr::FrameSetup) &&
01037       "Only instruction which are involved into frame setup code are allowed");
01038 
01039   MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
01040   ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
01041   const MachineFunction &MF = *MI->getParent()->getParent();
01042   const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
01043   const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
01044 
01045   unsigned FramePtr = RegInfo->getFrameRegister(MF);
01046   unsigned Opc = MI->getOpcode();
01047   unsigned SrcReg, DstReg;
01048 
01049   if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
01050     // Two special cases:
01051     // 1) tPUSH does not have src/dst regs.
01052     // 2) for Thumb1 code we sometimes materialize the constant via constpool
01053     // load. Yes, this is pretty fragile, but for now I don't see better
01054     // way... :(
01055     SrcReg = DstReg = ARM::SP;
01056   } else {
01057     SrcReg = MI->getOperand(1).getReg();
01058     DstReg = MI->getOperand(0).getReg();
01059   }
01060 
01061   // Try to figure out the unwinding opcode out of src / dst regs.
01062   if (MI->mayStore()) {
01063     // Register saves.
01064     assert(DstReg == ARM::SP &&
01065            "Only stack pointer as a destination reg is supported");
01066 
01067     SmallVector<unsigned, 4> RegList;
01068     // Skip src & dst reg, and pred ops.
01069     unsigned StartOp = 2 + 2;
01070     // Use all the operands.
01071     unsigned NumOffset = 0;
01072 
01073     switch (Opc) {
01074     default:
01075       MI->dump();
01076       llvm_unreachable("Unsupported opcode for unwinding information");
01077     case ARM::tPUSH:
01078       // Special case here: no src & dst reg, but two extra imp ops.
01079       StartOp = 2; NumOffset = 2;
01080     case ARM::STMDB_UPD:
01081     case ARM::t2STMDB_UPD:
01082     case ARM::VSTMDDB_UPD:
01083       assert(SrcReg == ARM::SP &&
01084              "Only stack pointer as a source reg is supported");
01085       for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
01086            i != NumOps; ++i) {
01087         const MachineOperand &MO = MI->getOperand(i);
01088         // Actually, there should never be any impdef stuff here. Skip it
01089         // temporary to workaround PR11902.
01090         if (MO.isImplicit())
01091           continue;
01092         RegList.push_back(MO.getReg());
01093       }
01094       break;
01095     case ARM::STR_PRE_IMM:
01096     case ARM::STR_PRE_REG:
01097     case ARM::t2STR_PRE:
01098       assert(MI->getOperand(2).getReg() == ARM::SP &&
01099              "Only stack pointer as a source reg is supported");
01100       RegList.push_back(SrcReg);
01101       break;
01102     }
01103     if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM)
01104       ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
01105   } else {
01106     // Changes of stack / frame pointer.
01107     if (SrcReg == ARM::SP) {
01108       int64_t Offset = 0;
01109       switch (Opc) {
01110       default:
01111         MI->dump();
01112         llvm_unreachable("Unsupported opcode for unwinding information");
01113       case ARM::MOVr:
01114       case ARM::tMOVr:
01115         Offset = 0;
01116         break;
01117       case ARM::ADDri:
01118         Offset = -MI->getOperand(2).getImm();
01119         break;
01120       case ARM::SUBri:
01121       case ARM::t2SUBri:
01122         Offset = MI->getOperand(2).getImm();
01123         break;
01124       case ARM::tSUBspi:
01125         Offset = MI->getOperand(2).getImm()*4;
01126         break;
01127       case ARM::tADDspi:
01128       case ARM::tADDrSPi:
01129         Offset = -MI->getOperand(2).getImm()*4;
01130         break;
01131       case ARM::tLDRpci: {
01132         // Grab the constpool index and check, whether it corresponds to
01133         // original or cloned constpool entry.
01134         unsigned CPI = MI->getOperand(1).getIndex();
01135         const MachineConstantPool *MCP = MF.getConstantPool();
01136         if (CPI >= MCP->getConstants().size())
01137           CPI = AFI.getOriginalCPIdx(CPI);
01138         assert(CPI != -1U && "Invalid constpool index");
01139 
01140         // Derive the actual offset.
01141         const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
01142         assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
01143         // FIXME: Check for user, it should be "add" instruction!
01144         Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
01145         break;
01146       }
01147       }
01148 
01149       if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM) {
01150         if (DstReg == FramePtr && FramePtr != ARM::SP)
01151           // Set-up of the frame pointer. Positive values correspond to "add"
01152           // instruction.
01153           ATS.emitSetFP(FramePtr, ARM::SP, -Offset);
01154         else if (DstReg == ARM::SP) {
01155           // Change of SP by an offset. Positive values correspond to "sub"
01156           // instruction.
01157           ATS.emitPad(Offset);
01158         } else {
01159           // Move of SP to a register.  Positive values correspond to an "add"
01160           // instruction.
01161           ATS.emitMovSP(DstReg, -Offset);
01162         }
01163       }
01164     } else if (DstReg == ARM::SP) {
01165       MI->dump();
01166       llvm_unreachable("Unsupported opcode for unwinding information");
01167     }
01168     else {
01169       MI->dump();
01170       llvm_unreachable("Unsupported opcode for unwinding information");
01171     }
01172   }
01173 }
01174 
01175 // Simple pseudo-instructions have their lowering (with expansion to real
01176 // instructions) auto-generated.
01177 #include "ARMGenMCPseudoLowering.inc"
01178 
01179 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
01180   const DataLayout *DL = TM.getDataLayout();
01181 
01182   // If we just ended a constant pool, mark it as such.
01183   if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
01184     OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
01185     InConstantPool = false;
01186   }
01187 
01188   // Emit unwinding stuff for frame-related instructions
01189   if (Subtarget->isTargetEHABICompatible() &&
01190        MI->getFlag(MachineInstr::FrameSetup))
01191     EmitUnwindingInstruction(MI);
01192 
01193   // Do any auto-generated pseudo lowerings.
01194   if (emitPseudoExpansionLowering(*OutStreamer, MI))
01195     return;
01196 
01197   assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
01198          "Pseudo flag setting opcode should be expanded early");
01199 
01200   // Check for manual lowerings.
01201   unsigned Opc = MI->getOpcode();
01202   switch (Opc) {
01203   case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
01204   case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing");
01205   case ARM::LEApcrel:
01206   case ARM::tLEApcrel:
01207   case ARM::t2LEApcrel: {
01208     // FIXME: Need to also handle globals and externals
01209     MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex());
01210     EmitToStreamer(*OutStreamer, MCInstBuilder(MI->getOpcode() ==
01211                                                ARM::t2LEApcrel ? ARM::t2ADR
01212                   : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
01213                      : ARM::ADR))
01214       .addReg(MI->getOperand(0).getReg())
01215       .addExpr(MCSymbolRefExpr::Create(CPISymbol, OutContext))
01216       // Add predicate operands.
01217       .addImm(MI->getOperand(2).getImm())
01218       .addReg(MI->getOperand(3).getReg()));
01219     return;
01220   }
01221   case ARM::LEApcrelJT:
01222   case ARM::tLEApcrelJT:
01223   case ARM::t2LEApcrelJT: {
01224     MCSymbol *JTIPICSymbol =
01225       GetARMJTIPICJumpTableLabel(MI->getOperand(1).getIndex());
01226     EmitToStreamer(*OutStreamer, MCInstBuilder(MI->getOpcode() ==
01227                                                ARM::t2LEApcrelJT ? ARM::t2ADR
01228                   : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
01229                      : ARM::ADR))
01230       .addReg(MI->getOperand(0).getReg())
01231       .addExpr(MCSymbolRefExpr::Create(JTIPICSymbol, OutContext))
01232       // Add predicate operands.
01233       .addImm(MI->getOperand(2).getImm())
01234       .addReg(MI->getOperand(3).getReg()));
01235     return;
01236   }
01237   // Darwin call instructions are just normal call instructions with different
01238   // clobber semantics (they clobber R9).
01239   case ARM::BX_CALL: {
01240     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr)
01241       .addReg(ARM::LR)
01242       .addReg(ARM::PC)
01243       // Add predicate operands.
01244       .addImm(ARMCC::AL)
01245       .addReg(0)
01246       // Add 's' bit operand (always reg0 for this)
01247       .addReg(0));
01248 
01249     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::BX)
01250       .addReg(MI->getOperand(0).getReg()));
01251     return;
01252   }
01253   case ARM::tBX_CALL: {
01254     if (Subtarget->hasV5TOps())
01255       llvm_unreachable("Expected BLX to be selected for v5t+");
01256 
01257     // On ARM v4t, when doing a call from thumb mode, we need to ensure
01258     // that the saved lr has its LSB set correctly (the arch doesn't
01259     // have blx).
01260     // So here we generate a bl to a small jump pad that does bx rN.
01261     // The jump pads are emitted after the function body.
01262 
01263     unsigned TReg = MI->getOperand(0).getReg();
01264     MCSymbol *TRegSym = nullptr;
01265     for (unsigned i = 0, e = ThumbIndirectPads.size(); i < e; i++) {
01266       if (ThumbIndirectPads[i].first == TReg) {
01267         TRegSym = ThumbIndirectPads[i].second;
01268         break;
01269       }
01270     }
01271 
01272     if (!TRegSym) {
01273       TRegSym = OutContext.createTempSymbol();
01274       ThumbIndirectPads.push_back(std::make_pair(TReg, TRegSym));
01275     }
01276 
01277     // Create a link-saving branch to the Reg Indirect Jump Pad.
01278     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tBL)
01279         // Predicate comes first here.
01280         .addImm(ARMCC::AL).addReg(0)
01281         .addExpr(MCSymbolRefExpr::Create(TRegSym, OutContext)));
01282     return;
01283   }
01284   case ARM::BMOVPCRX_CALL: {
01285     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr)
01286       .addReg(ARM::LR)
01287       .addReg(ARM::PC)
01288       // Add predicate operands.
01289       .addImm(ARMCC::AL)
01290       .addReg(0)
01291       // Add 's' bit operand (always reg0 for this)
01292       .addReg(0));
01293 
01294     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr)
01295       .addReg(ARM::PC)
01296       .addReg(MI->getOperand(0).getReg())
01297       // Add predicate operands.
01298       .addImm(ARMCC::AL)
01299       .addReg(0)
01300       // Add 's' bit operand (always reg0 for this)
01301       .addReg(0));
01302     return;
01303   }
01304   case ARM::BMOVPCB_CALL: {
01305     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr)
01306       .addReg(ARM::LR)
01307       .addReg(ARM::PC)
01308       // Add predicate operands.
01309       .addImm(ARMCC::AL)
01310       .addReg(0)
01311       // Add 's' bit operand (always reg0 for this)
01312       .addReg(0));
01313 
01314     const MachineOperand &Op = MI->getOperand(0);
01315     const GlobalValue *GV = Op.getGlobal();
01316     const unsigned TF = Op.getTargetFlags();
01317     MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
01318     const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
01319     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::Bcc)
01320       .addExpr(GVSymExpr)
01321       // Add predicate operands.
01322       .addImm(ARMCC::AL)
01323       .addReg(0));
01324     return;
01325   }
01326   case ARM::MOVi16_ga_pcrel:
01327   case ARM::t2MOVi16_ga_pcrel: {
01328     MCInst TmpInst;
01329     TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
01330     TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
01331 
01332     unsigned TF = MI->getOperand(1).getTargetFlags();
01333     const GlobalValue *GV = MI->getOperand(1).getGlobal();
01334     MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
01335     const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
01336 
01337     MCSymbol *LabelSym = getPICLabel(DL->getPrivateGlobalPrefix(),
01338                                      getFunctionNumber(),
01339                                      MI->getOperand(2).getImm(), OutContext);
01340     const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
01341     unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
01342     const MCExpr *PCRelExpr =
01343       ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
01344                                       MCBinaryExpr::CreateAdd(LabelSymExpr,
01345                                       MCConstantExpr::Create(PCAdj, OutContext),
01346                                       OutContext), OutContext), OutContext);
01347       TmpInst.addOperand(MCOperand::createExpr(PCRelExpr));
01348 
01349     // Add predicate operands.
01350     TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
01351     TmpInst.addOperand(MCOperand::createReg(0));
01352     // Add 's' bit operand (always reg0 for this)
01353     TmpInst.addOperand(MCOperand::createReg(0));
01354     EmitToStreamer(*OutStreamer, TmpInst);
01355     return;
01356   }
01357   case ARM::MOVTi16_ga_pcrel:
01358   case ARM::t2MOVTi16_ga_pcrel: {
01359     MCInst TmpInst;
01360     TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
01361                       ? ARM::MOVTi16 : ARM::t2MOVTi16);
01362     TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
01363     TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg()));
01364 
01365     unsigned TF = MI->getOperand(2).getTargetFlags();
01366     const GlobalValue *GV = MI->getOperand(2).getGlobal();
01367     MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
01368     const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
01369 
01370     MCSymbol *LabelSym = getPICLabel(DL->getPrivateGlobalPrefix(),
01371                                      getFunctionNumber(),
01372                                      MI->getOperand(3).getImm(), OutContext);
01373     const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
01374     unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
01375     const MCExpr *PCRelExpr =
01376         ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
01377                                    MCBinaryExpr::CreateAdd(LabelSymExpr,
01378                                       MCConstantExpr::Create(PCAdj, OutContext),
01379                                           OutContext), OutContext), OutContext);
01380       TmpInst.addOperand(MCOperand::createExpr(PCRelExpr));
01381     // Add predicate operands.
01382     TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
01383     TmpInst.addOperand(MCOperand::createReg(0));
01384     // Add 's' bit operand (always reg0 for this)
01385     TmpInst.addOperand(MCOperand::createReg(0));
01386     EmitToStreamer(*OutStreamer, TmpInst);
01387     return;
01388   }
01389   case ARM::tPICADD: {
01390     // This is a pseudo op for a label + instruction sequence, which looks like:
01391     // LPC0:
01392     //     add r0, pc
01393     // This adds the address of LPC0 to r0.
01394 
01395     // Emit the label.
01396     OutStreamer->EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
01397                                        getFunctionNumber(),
01398                                        MI->getOperand(2).getImm(),
01399                                        OutContext));
01400 
01401     // Form and emit the add.
01402     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDhirr)
01403       .addReg(MI->getOperand(0).getReg())
01404       .addReg(MI->getOperand(0).getReg())
01405       .addReg(ARM::PC)
01406       // Add predicate operands.
01407       .addImm(ARMCC::AL)
01408       .addReg(0));
01409     return;
01410   }
01411   case ARM::PICADD: {
01412     // This is a pseudo op for a label + instruction sequence, which looks like:
01413     // LPC0:
01414     //     add r0, pc, r0
01415     // This adds the address of LPC0 to r0.
01416 
01417     // Emit the label.
01418     OutStreamer->EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
01419                                        getFunctionNumber(),
01420                                        MI->getOperand(2).getImm(),
01421                                        OutContext));
01422 
01423     // Form and emit the add.
01424     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDrr)
01425       .addReg(MI->getOperand(0).getReg())
01426       .addReg(ARM::PC)
01427       .addReg(MI->getOperand(1).getReg())
01428       // Add predicate operands.
01429       .addImm(MI->getOperand(3).getImm())
01430       .addReg(MI->getOperand(4).getReg())
01431       // Add 's' bit operand (always reg0 for this)
01432       .addReg(0));
01433     return;
01434   }
01435   case ARM::PICSTR:
01436   case ARM::PICSTRB:
01437   case ARM::PICSTRH:
01438   case ARM::PICLDR:
01439   case ARM::PICLDRB:
01440   case ARM::PICLDRH:
01441   case ARM::PICLDRSB:
01442   case ARM::PICLDRSH: {
01443     // This is a pseudo op for a label + instruction sequence, which looks like:
01444     // LPC0:
01445     //     OP r0, [pc, r0]
01446     // The LCP0 label is referenced by a constant pool entry in order to get
01447     // a PC-relative address at the ldr instruction.
01448 
01449     // Emit the label.
01450     OutStreamer->EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
01451                                        getFunctionNumber(),
01452                                        MI->getOperand(2).getImm(),
01453                                        OutContext));
01454 
01455     // Form and emit the load
01456     unsigned Opcode;
01457     switch (MI->getOpcode()) {
01458     default:
01459       llvm_unreachable("Unexpected opcode!");
01460     case ARM::PICSTR:   Opcode = ARM::STRrs; break;
01461     case ARM::PICSTRB:  Opcode = ARM::STRBrs; break;
01462     case ARM::PICSTRH:  Opcode = ARM::STRH; break;
01463     case ARM::PICLDR:   Opcode = ARM::LDRrs; break;
01464     case ARM::PICLDRB:  Opcode = ARM::LDRBrs; break;
01465     case ARM::PICLDRH:  Opcode = ARM::LDRH; break;
01466     case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
01467     case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
01468     }
01469     EmitToStreamer(*OutStreamer, MCInstBuilder(Opcode)
01470       .addReg(MI->getOperand(0).getReg())
01471       .addReg(ARM::PC)
01472       .addReg(MI->getOperand(1).getReg())
01473       .addImm(0)
01474       // Add predicate operands.
01475       .addImm(MI->getOperand(3).getImm())
01476       .addReg(MI->getOperand(4).getReg()));
01477 
01478     return;
01479   }
01480   case ARM::CONSTPOOL_ENTRY: {
01481     /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
01482     /// in the function.  The first operand is the ID# for this instruction, the
01483     /// second is the index into the MachineConstantPool that this is, the third
01484     /// is the size in bytes of this constant pool entry.
01485     /// The required alignment is specified on the basic block holding this MI.
01486     unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
01487     unsigned CPIdx   = (unsigned)MI->getOperand(1).getIndex();
01488 
01489     // If this is the first entry of the pool, mark it.
01490     if (!InConstantPool) {
01491       OutStreamer->EmitDataRegion(MCDR_DataRegion);
01492       InConstantPool = true;
01493     }
01494 
01495     OutStreamer->EmitLabel(GetCPISymbol(LabelId));
01496 
01497     const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
01498     if (MCPE.isMachineConstantPoolEntry())
01499       EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
01500     else
01501       EmitGlobalConstant(MCPE.Val.ConstVal);
01502     return;
01503   }
01504   case ARM::t2BR_JT: {
01505     // Lower and emit the instruction itself, then the jump table following it.
01506     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVr)
01507       .addReg(ARM::PC)
01508       .addReg(MI->getOperand(0).getReg())
01509       // Add predicate operands.
01510       .addImm(ARMCC::AL)
01511       .addReg(0));
01512 
01513     // Output the data for the jump table itself
01514     EmitJump2Table(MI);
01515     return;
01516   }
01517   case ARM::t2TBB_JT: {
01518     // Lower and emit the instruction itself, then the jump table following it.
01519     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2TBB)
01520       .addReg(ARM::PC)
01521       .addReg(MI->getOperand(0).getReg())
01522       // Add predicate operands.
01523       .addImm(ARMCC::AL)
01524       .addReg(0));
01525 
01526     // Output the data for the jump table itself
01527     EmitJump2Table(MI);
01528     // Make sure the next instruction is 2-byte aligned.
01529     EmitAlignment(1);
01530     return;
01531   }
01532   case ARM::t2TBH_JT: {
01533     // Lower and emit the instruction itself, then the jump table following it.
01534     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2TBH)
01535       .addReg(ARM::PC)
01536       .addReg(MI->getOperand(0).getReg())
01537       // Add predicate operands.
01538       .addImm(ARMCC::AL)
01539       .addReg(0));
01540 
01541     // Output the data for the jump table itself
01542     EmitJump2Table(MI);
01543     return;
01544   }
01545   case ARM::tBR_JTr:
01546   case ARM::BR_JTr: {
01547     // Lower and emit the instruction itself, then the jump table following it.
01548     // mov pc, target
01549     MCInst TmpInst;
01550     unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
01551       ARM::MOVr : ARM::tMOVr;
01552     TmpInst.setOpcode(Opc);
01553     TmpInst.addOperand(MCOperand::createReg(ARM::PC));
01554     TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
01555     // Add predicate operands.
01556     TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
01557     TmpInst.addOperand(MCOperand::createReg(0));
01558     // Add 's' bit operand (always reg0 for this)
01559     if (Opc == ARM::MOVr)
01560       TmpInst.addOperand(MCOperand::createReg(0));
01561     EmitToStreamer(*OutStreamer, TmpInst);
01562 
01563     // Make sure the Thumb jump table is 4-byte aligned.
01564     if (Opc == ARM::tMOVr)
01565       EmitAlignment(2);
01566 
01567     // Output the data for the jump table itself
01568     EmitJumpTable(MI);
01569     return;
01570   }
01571   case ARM::BR_JTm: {
01572     // Lower and emit the instruction itself, then the jump table following it.
01573     // ldr pc, target
01574     MCInst TmpInst;
01575     if (MI->getOperand(1).getReg() == 0) {
01576       // literal offset
01577       TmpInst.setOpcode(ARM::LDRi12);
01578       TmpInst.addOperand(MCOperand::createReg(ARM::PC));
01579       TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
01580       TmpInst.addOperand(MCOperand::createImm(MI->getOperand(2).getImm()));
01581     } else {
01582       TmpInst.setOpcode(ARM::LDRrs);
01583       TmpInst.addOperand(MCOperand::createReg(ARM::PC));
01584       TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
01585       TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg()));
01586       TmpInst.addOperand(MCOperand::createImm(0));
01587     }
01588     // Add predicate operands.
01589     TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
01590     TmpInst.addOperand(MCOperand::createReg(0));
01591     EmitToStreamer(*OutStreamer, TmpInst);
01592 
01593     // Output the data for the jump table itself
01594     EmitJumpTable(MI);
01595     return;
01596   }
01597   case ARM::BR_JTadd: {
01598     // Lower and emit the instruction itself, then the jump table following it.
01599     // add pc, target, idx
01600     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDrr)
01601       .addReg(ARM::PC)
01602       .addReg(MI->getOperand(0).getReg())
01603       .addReg(MI->getOperand(1).getReg())
01604       // Add predicate operands.
01605       .addImm(ARMCC::AL)
01606       .addReg(0)
01607       // Add 's' bit operand (always reg0 for this)
01608       .addReg(0));
01609 
01610     // Output the data for the jump table itself
01611     EmitJumpTable(MI);
01612     return;
01613   }
01614   case ARM::SPACE:
01615     OutStreamer->EmitZeros(MI->getOperand(1).getImm());
01616     return;
01617   case ARM::TRAP: {
01618     // Non-Darwin binutils don't yet support the "trap" mnemonic.
01619     // FIXME: Remove this special case when they do.
01620     if (!Subtarget->isTargetMachO()) {
01621       //.long 0xe7ffdefe @ trap
01622       uint32_t Val = 0xe7ffdefeUL;
01623       OutStreamer->AddComment("trap");
01624       OutStreamer->EmitIntValue(Val, 4);
01625       return;
01626     }
01627     break;
01628   }
01629   case ARM::TRAPNaCl: {
01630     //.long 0xe7fedef0 @ trap
01631     uint32_t Val = 0xe7fedef0UL;
01632     OutStreamer->AddComment("trap");
01633     OutStreamer->EmitIntValue(Val, 4);
01634     return;
01635   }
01636   case ARM::tTRAP: {
01637     // Non-Darwin binutils don't yet support the "trap" mnemonic.
01638     // FIXME: Remove this special case when they do.
01639     if (!Subtarget->isTargetMachO()) {
01640       //.short 57086 @ trap
01641       uint16_t Val = 0xdefe;
01642       OutStreamer->AddComment("trap");
01643       OutStreamer->EmitIntValue(Val, 2);
01644       return;
01645     }
01646     break;
01647   }
01648   case ARM::t2Int_eh_sjlj_setjmp:
01649   case ARM::t2Int_eh_sjlj_setjmp_nofp:
01650   case ARM::tInt_eh_sjlj_setjmp: {
01651     // Two incoming args: GPR:$src, GPR:$val
01652     // mov $val, pc
01653     // adds $val, #7
01654     // str $val, [$src, #4]
01655     // movs r0, #0
01656     // b 1f
01657     // movs r0, #1
01658     // 1:
01659     unsigned SrcReg = MI->getOperand(0).getReg();
01660     unsigned ValReg = MI->getOperand(1).getReg();
01661     MCSymbol *Label = GetARMSJLJEHLabel();
01662     OutStreamer->AddComment("eh_setjmp begin");
01663     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVr)
01664       .addReg(ValReg)
01665       .addReg(ARM::PC)
01666       // Predicate.
01667       .addImm(ARMCC::AL)
01668       .addReg(0));
01669 
01670     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDi3)
01671       .addReg(ValReg)
01672       // 's' bit operand
01673       .addReg(ARM::CPSR)
01674       .addReg(ValReg)
01675       .addImm(7)
01676       // Predicate.
01677       .addImm(ARMCC::AL)
01678       .addReg(0));
01679 
01680     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tSTRi)
01681       .addReg(ValReg)
01682       .addReg(SrcReg)
01683       // The offset immediate is #4. The operand value is scaled by 4 for the
01684       // tSTR instruction.
01685       .addImm(1)
01686       // Predicate.
01687       .addImm(ARMCC::AL)
01688       .addReg(0));
01689 
01690     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVi8)
01691       .addReg(ARM::R0)
01692       .addReg(ARM::CPSR)
01693       .addImm(0)
01694       // Predicate.
01695       .addImm(ARMCC::AL)
01696       .addReg(0));
01697 
01698     const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
01699     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tB)
01700       .addExpr(SymbolExpr)
01701       .addImm(ARMCC::AL)
01702       .addReg(0));
01703 
01704     OutStreamer->AddComment("eh_setjmp end");
01705     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVi8)
01706       .addReg(ARM::R0)
01707       .addReg(ARM::CPSR)
01708       .addImm(1)
01709       // Predicate.
01710       .addImm(ARMCC::AL)
01711       .addReg(0));
01712 
01713     OutStreamer->EmitLabel(Label);
01714     return;
01715   }
01716 
01717   case ARM::Int_eh_sjlj_setjmp_nofp:
01718   case ARM::Int_eh_sjlj_setjmp: {
01719     // Two incoming args: GPR:$src, GPR:$val
01720     // add $val, pc, #8
01721     // str $val, [$src, #+4]
01722     // mov r0, #0
01723     // add pc, pc, #0
01724     // mov r0, #1
01725     unsigned SrcReg = MI->getOperand(0).getReg();
01726     unsigned ValReg = MI->getOperand(1).getReg();
01727 
01728     OutStreamer->AddComment("eh_setjmp begin");
01729     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDri)
01730       .addReg(ValReg)
01731       .addReg(ARM::PC)
01732       .addImm(8)
01733       // Predicate.
01734       .addImm(ARMCC::AL)
01735       .addReg(0)
01736       // 's' bit operand (always reg0 for this).
01737       .addReg(0));
01738 
01739     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::STRi12)
01740       .addReg(ValReg)
01741       .addReg(SrcReg)
01742       .addImm(4)
01743       // Predicate.
01744       .addImm(ARMCC::AL)
01745       .addReg(0));
01746 
01747     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVi)
01748       .addReg(ARM::R0)
01749       .addImm(0)
01750       // Predicate.
01751       .addImm(ARMCC::AL)
01752       .addReg(0)
01753       // 's' bit operand (always reg0 for this).
01754       .addReg(0));
01755 
01756     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDri)
01757       .addReg(ARM::PC)
01758       .addReg(ARM::PC)
01759       .addImm(0)
01760       // Predicate.
01761       .addImm(ARMCC::AL)
01762       .addReg(0)
01763       // 's' bit operand (always reg0 for this).
01764       .addReg(0));
01765 
01766     OutStreamer->AddComment("eh_setjmp end");
01767     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVi)
01768       .addReg(ARM::R0)
01769       .addImm(1)
01770       // Predicate.
01771       .addImm(ARMCC::AL)
01772       .addReg(0)
01773       // 's' bit operand (always reg0 for this).
01774       .addReg(0));
01775     return;
01776   }
01777   case ARM::Int_eh_sjlj_longjmp: {
01778     // ldr sp, [$src, #8]
01779     // ldr $scratch, [$src, #4]
01780     // ldr r7, [$src]
01781     // bx $scratch
01782     unsigned SrcReg = MI->getOperand(0).getReg();
01783     unsigned ScratchReg = MI->getOperand(1).getReg();
01784     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12)
01785       .addReg(ARM::SP)
01786       .addReg(SrcReg)
01787       .addImm(8)
01788       // Predicate.
01789       .addImm(ARMCC::AL)
01790       .addReg(0));
01791 
01792     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12)
01793       .addReg(ScratchReg)
01794       .addReg(SrcReg)
01795       .addImm(4)
01796       // Predicate.
01797       .addImm(ARMCC::AL)
01798       .addReg(0));
01799 
01800     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12)
01801       .addReg(ARM::R7)
01802       .addReg(SrcReg)
01803       .addImm(0)
01804       // Predicate.
01805       .addImm(ARMCC::AL)
01806       .addReg(0));
01807 
01808     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::BX)
01809       .addReg(ScratchReg)
01810       // Predicate.
01811       .addImm(ARMCC::AL)
01812       .addReg(0));
01813     return;
01814   }
01815   case ARM::tInt_eh_sjlj_longjmp: {
01816     // ldr $scratch, [$src, #8]
01817     // mov sp, $scratch
01818     // ldr $scratch, [$src, #4]
01819     // ldr r7, [$src]
01820     // bx $scratch
01821     unsigned SrcReg = MI->getOperand(0).getReg();
01822     unsigned ScratchReg = MI->getOperand(1).getReg();
01823     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi)
01824       .addReg(ScratchReg)
01825       .addReg(SrcReg)
01826       // The offset immediate is #8. The operand value is scaled by 4 for the
01827       // tLDR instruction.
01828       .addImm(2)
01829       // Predicate.
01830       .addImm(ARMCC::AL)
01831       .addReg(0));
01832 
01833     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVr)
01834       .addReg(ARM::SP)
01835       .addReg(ScratchReg)
01836       // Predicate.
01837       .addImm(ARMCC::AL)
01838       .addReg(0));
01839 
01840     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi)
01841       .addReg(ScratchReg)
01842       .addReg(SrcReg)
01843       .addImm(1)
01844       // Predicate.
01845       .addImm(ARMCC::AL)
01846       .addReg(0));
01847 
01848     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi)
01849       .addReg(ARM::R7)
01850       .addReg(SrcReg)
01851       .addImm(0)
01852       // Predicate.
01853       .addImm(ARMCC::AL)
01854       .addReg(0));
01855 
01856     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tBX)
01857       .addReg(ScratchReg)
01858       // Predicate.
01859       .addImm(ARMCC::AL)
01860       .addReg(0));
01861     return;
01862   }
01863   }
01864 
01865   MCInst TmpInst;
01866   LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
01867 
01868   EmitToStreamer(*OutStreamer, TmpInst);
01869 }
01870 
01871 //===----------------------------------------------------------------------===//
01872 // Target Registry Stuff
01873 //===----------------------------------------------------------------------===//
01874 
01875 // Force static initialization.
01876 extern "C" void LLVMInitializeARMAsmPrinter() {
01877   RegisterAsmPrinter<ARMAsmPrinter> X(TheARMLETarget);
01878   RegisterAsmPrinter<ARMAsmPrinter> Y(TheARMBETarget);
01879   RegisterAsmPrinter<ARMAsmPrinter> A(TheThumbLETarget);
01880   RegisterAsmPrinter<ARMAsmPrinter> B(TheThumbBETarget);
01881 }