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ARMAsmPrinter.cpp
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00001 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file contains a printer that converts from our internal representation
00011 // of machine-dependent LLVM code to GAS-format ARM assembly language.
00012 //
00013 //===----------------------------------------------------------------------===//
00014 
00015 #include "ARMAsmPrinter.h"
00016 #include "ARM.h"
00017 #include "ARMConstantPoolValue.h"
00018 #include "ARMMachineFunctionInfo.h"
00019 #include "ARMTargetMachine.h"
00020 #include "ARMTargetObjectFile.h"
00021 #include "InstPrinter/ARMInstPrinter.h"
00022 #include "MCTargetDesc/ARMAddressingModes.h"
00023 #include "MCTargetDesc/ARMMCExpr.h"
00024 #include "llvm/ADT/SetVector.h"
00025 #include "llvm/ADT/SmallString.h"
00026 #include "llvm/CodeGen/MachineFunctionPass.h"
00027 #include "llvm/CodeGen/MachineJumpTableInfo.h"
00028 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
00029 #include "llvm/IR/Constants.h"
00030 #include "llvm/IR/DataLayout.h"
00031 #include "llvm/IR/DebugInfo.h"
00032 #include "llvm/IR/Mangler.h"
00033 #include "llvm/IR/Module.h"
00034 #include "llvm/IR/Type.h"
00035 #include "llvm/MC/MCAsmInfo.h"
00036 #include "llvm/MC/MCAssembler.h"
00037 #include "llvm/MC/MCContext.h"
00038 #include "llvm/MC/MCELFStreamer.h"
00039 #include "llvm/MC/MCInst.h"
00040 #include "llvm/MC/MCInstBuilder.h"
00041 #include "llvm/MC/MCObjectStreamer.h"
00042 #include "llvm/MC/MCSectionMachO.h"
00043 #include "llvm/MC/MCStreamer.h"
00044 #include "llvm/MC/MCSymbol.h"
00045 #include "llvm/Support/ARMBuildAttributes.h"
00046 #include "llvm/Support/TargetParser.h"
00047 #include "llvm/Support/COFF.h"
00048 #include "llvm/Support/CommandLine.h"
00049 #include "llvm/Support/Debug.h"
00050 #include "llvm/Support/ELF.h"
00051 #include "llvm/Support/ErrorHandling.h"
00052 #include "llvm/Support/TargetRegistry.h"
00053 #include "llvm/Support/raw_ostream.h"
00054 #include "llvm/Target/TargetMachine.h"
00055 #include <cctype>
00056 using namespace llvm;
00057 
00058 #define DEBUG_TYPE "asm-printer"
00059 
00060 ARMAsmPrinter::ARMAsmPrinter(TargetMachine &TM,
00061                              std::unique_ptr<MCStreamer> Streamer)
00062     : AsmPrinter(TM, std::move(Streamer)), AFI(nullptr), MCP(nullptr),
00063       InConstantPool(false), OptimizationGoals(-1) {}
00064 
00065 void ARMAsmPrinter::EmitFunctionBodyEnd() {
00066   // Make sure to terminate any constant pools that were at the end
00067   // of the function.
00068   if (!InConstantPool)
00069     return;
00070   InConstantPool = false;
00071   OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
00072 }
00073 
00074 void ARMAsmPrinter::EmitFunctionEntryLabel() {
00075   if (AFI->isThumbFunction()) {
00076     OutStreamer->EmitAssemblerFlag(MCAF_Code16);
00077     OutStreamer->EmitThumbFunc(CurrentFnSym);
00078   }
00079 
00080   OutStreamer->EmitLabel(CurrentFnSym);
00081 }
00082 
00083 void ARMAsmPrinter::EmitXXStructor(const DataLayout &DL, const Constant *CV) {
00084   uint64_t Size = getDataLayout().getTypeAllocSize(CV->getType());
00085   assert(Size && "C++ constructor pointer had zero size!");
00086 
00087   const GlobalValue *GV = dyn_cast<GlobalValue>(CV->stripPointerCasts());
00088   assert(GV && "C++ constructor pointer was not a GlobalValue!");
00089 
00090   const MCExpr *E = MCSymbolRefExpr::create(GetARMGVSymbol(GV,
00091                                                            ARMII::MO_NO_FLAG),
00092                                             (Subtarget->isTargetELF()
00093                                              ? MCSymbolRefExpr::VK_ARM_TARGET1
00094                                              : MCSymbolRefExpr::VK_None),
00095                                             OutContext);
00096 
00097   OutStreamer->EmitValue(E, Size);
00098 }
00099 
00100 /// runOnMachineFunction - This uses the EmitInstruction()
00101 /// method to print assembly for each instruction.
00102 ///
00103 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
00104   AFI = MF.getInfo<ARMFunctionInfo>();
00105   MCP = MF.getConstantPool();
00106   Subtarget = &MF.getSubtarget<ARMSubtarget>();
00107 
00108   SetupMachineFunction(MF);
00109   const Function* F = MF.getFunction();
00110   const TargetMachine& TM = MF.getTarget();
00111 
00112   // Calculate this function's optimization goal.
00113   unsigned OptimizationGoal;
00114   if (F->hasFnAttribute(Attribute::OptimizeNone))
00115     // For best debugging illusion, speed and small size sacrificed
00116     OptimizationGoal = 6;
00117   else if (F->optForMinSize())
00118     // Aggressively for small size, speed and debug illusion sacrificed
00119     OptimizationGoal = 4;
00120   else if (F->optForSize())
00121     // For small size, but speed and debugging illusion preserved
00122     OptimizationGoal = 3;
00123   else if (TM.getOptLevel() == CodeGenOpt::Aggressive)
00124     // Aggressively for speed, small size and debug illusion sacrificed
00125     OptimizationGoal = 2;
00126   else if (TM.getOptLevel() > CodeGenOpt::None)
00127     // For speed, but small size and good debug illusion preserved
00128     OptimizationGoal = 1;
00129   else // TM.getOptLevel() == CodeGenOpt::None
00130     // For good debugging, but speed and small size preserved
00131     OptimizationGoal = 5;
00132 
00133   // Combine a new optimization goal with existing ones.
00134   if (OptimizationGoals == -1) // uninitialized goals
00135     OptimizationGoals = OptimizationGoal;
00136   else if (OptimizationGoals != (int)OptimizationGoal) // conflicting goals
00137     OptimizationGoals = 0;
00138 
00139   if (Subtarget->isTargetCOFF()) {
00140     bool Internal = F->hasInternalLinkage();
00141     COFF::SymbolStorageClass Scl = Internal ? COFF::IMAGE_SYM_CLASS_STATIC
00142                                             : COFF::IMAGE_SYM_CLASS_EXTERNAL;
00143     int Type = COFF::IMAGE_SYM_DTYPE_FUNCTION << COFF::SCT_COMPLEX_TYPE_SHIFT;
00144 
00145     OutStreamer->BeginCOFFSymbolDef(CurrentFnSym);
00146     OutStreamer->EmitCOFFSymbolStorageClass(Scl);
00147     OutStreamer->EmitCOFFSymbolType(Type);
00148     OutStreamer->EndCOFFSymbolDef();
00149   }
00150 
00151   // Emit the rest of the function body.
00152   EmitFunctionBody();
00153 
00154   // If we need V4T thumb mode Register Indirect Jump pads, emit them.
00155   // These are created per function, rather than per TU, since it's
00156   // relatively easy to exceed the thumb branch range within a TU.
00157   if (! ThumbIndirectPads.empty()) {
00158     OutStreamer->EmitAssemblerFlag(MCAF_Code16);
00159     EmitAlignment(1);
00160     for (unsigned i = 0, e = ThumbIndirectPads.size(); i < e; i++) {
00161       OutStreamer->EmitLabel(ThumbIndirectPads[i].second);
00162       EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tBX)
00163         .addReg(ThumbIndirectPads[i].first)
00164         // Add predicate operands.
00165         .addImm(ARMCC::AL)
00166         .addReg(0));
00167     }
00168     ThumbIndirectPads.clear();
00169   }
00170 
00171   // We didn't modify anything.
00172   return false;
00173 }
00174 
00175 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
00176                                  raw_ostream &O) {
00177   const MachineOperand &MO = MI->getOperand(OpNum);
00178   unsigned TF = MO.getTargetFlags();
00179 
00180   switch (MO.getType()) {
00181   default: llvm_unreachable("<unknown operand type>");
00182   case MachineOperand::MO_Register: {
00183     unsigned Reg = MO.getReg();
00184     assert(TargetRegisterInfo::isPhysicalRegister(Reg));
00185     assert(!MO.getSubReg() && "Subregs should be eliminated!");
00186     if(ARM::GPRPairRegClass.contains(Reg)) {
00187       const MachineFunction &MF = *MI->getParent()->getParent();
00188       const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
00189       Reg = TRI->getSubReg(Reg, ARM::gsub_0);
00190     }
00191     O << ARMInstPrinter::getRegisterName(Reg);
00192     break;
00193   }
00194   case MachineOperand::MO_Immediate: {
00195     int64_t Imm = MO.getImm();
00196     O << '#';
00197     if (TF == ARMII::MO_LO16)
00198       O << ":lower16:";
00199     else if (TF == ARMII::MO_HI16)
00200       O << ":upper16:";
00201     O << Imm;
00202     break;
00203   }
00204   case MachineOperand::MO_MachineBasicBlock:
00205     MO.getMBB()->getSymbol()->print(O, MAI);
00206     return;
00207   case MachineOperand::MO_GlobalAddress: {
00208     const GlobalValue *GV = MO.getGlobal();
00209     if (TF & ARMII::MO_LO16)
00210       O << ":lower16:";
00211     else if (TF & ARMII::MO_HI16)
00212       O << ":upper16:";
00213     GetARMGVSymbol(GV, TF)->print(O, MAI);
00214 
00215     printOffset(MO.getOffset(), O);
00216     if (TF == ARMII::MO_PLT)
00217       O << "(PLT)";
00218     break;
00219   }
00220   case MachineOperand::MO_ConstantPoolIndex:
00221     GetCPISymbol(MO.getIndex())->print(O, MAI);
00222     break;
00223   }
00224 }
00225 
00226 //===--------------------------------------------------------------------===//
00227 
00228 MCSymbol *ARMAsmPrinter::
00229 GetARMJTIPICJumpTableLabel(unsigned uid) const {
00230   const DataLayout &DL = getDataLayout();
00231   SmallString<60> Name;
00232   raw_svector_ostream(Name) << DL.getPrivateGlobalPrefix() << "JTI"
00233                             << getFunctionNumber() << '_' << uid;
00234   return OutContext.getOrCreateSymbol(Name);
00235 }
00236 
00237 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
00238                                     unsigned AsmVariant, const char *ExtraCode,
00239                                     raw_ostream &O) {
00240   // Does this asm operand have a single letter operand modifier?
00241   if (ExtraCode && ExtraCode[0]) {
00242     if (ExtraCode[1] != 0) return true; // Unknown modifier.
00243 
00244     switch (ExtraCode[0]) {
00245     default:
00246       // See if this is a generic print operand
00247       return AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O);
00248     case 'a': // Print as a memory address.
00249       if (MI->getOperand(OpNum).isReg()) {
00250         O << "["
00251           << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
00252           << "]";
00253         return false;
00254       }
00255       // Fallthrough
00256     case 'c': // Don't print "#" before an immediate operand.
00257       if (!MI->getOperand(OpNum).isImm())
00258         return true;
00259       O << MI->getOperand(OpNum).getImm();
00260       return false;
00261     case 'P': // Print a VFP double precision register.
00262     case 'q': // Print a NEON quad precision register.
00263       printOperand(MI, OpNum, O);
00264       return false;
00265     case 'y': // Print a VFP single precision register as indexed double.
00266       if (MI->getOperand(OpNum).isReg()) {
00267         unsigned Reg = MI->getOperand(OpNum).getReg();
00268         const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
00269         // Find the 'd' register that has this 's' register as a sub-register,
00270         // and determine the lane number.
00271         for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
00272           if (!ARM::DPRRegClass.contains(*SR))
00273             continue;
00274           bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
00275           O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");
00276           return false;
00277         }
00278       }
00279       return true;
00280     case 'B': // Bitwise inverse of integer or symbol without a preceding #.
00281       if (!MI->getOperand(OpNum).isImm())
00282         return true;
00283       O << ~(MI->getOperand(OpNum).getImm());
00284       return false;
00285     case 'L': // The low 16 bits of an immediate constant.
00286       if (!MI->getOperand(OpNum).isImm())
00287         return true;
00288       O << (MI->getOperand(OpNum).getImm() & 0xffff);
00289       return false;
00290     case 'M': { // A register range suitable for LDM/STM.
00291       if (!MI->getOperand(OpNum).isReg())
00292         return true;
00293       const MachineOperand &MO = MI->getOperand(OpNum);
00294       unsigned RegBegin = MO.getReg();
00295       // This takes advantage of the 2 operand-ness of ldm/stm and that we've
00296       // already got the operands in registers that are operands to the
00297       // inline asm statement.
00298       O << "{";
00299       if (ARM::GPRPairRegClass.contains(RegBegin)) {
00300         const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
00301         unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
00302         O << ARMInstPrinter::getRegisterName(Reg0) << ", ";
00303         RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1);
00304       }
00305       O << ARMInstPrinter::getRegisterName(RegBegin);
00306 
00307       // FIXME: The register allocator not only may not have given us the
00308       // registers in sequence, but may not be in ascending registers. This
00309       // will require changes in the register allocator that'll need to be
00310       // propagated down here if the operands change.
00311       unsigned RegOps = OpNum + 1;
00312       while (MI->getOperand(RegOps).isReg()) {
00313         O << ", "
00314           << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
00315         RegOps++;
00316       }
00317 
00318       O << "}";
00319 
00320       return false;
00321     }
00322     case 'R': // The most significant register of a pair.
00323     case 'Q': { // The least significant register of a pair.
00324       if (OpNum == 0)
00325         return true;
00326       const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
00327       if (!FlagsOP.isImm())
00328         return true;
00329       unsigned Flags = FlagsOP.getImm();
00330 
00331       // This operand may not be the one that actually provides the register. If
00332       // it's tied to a previous one then we should refer instead to that one
00333       // for registers and their classes.
00334       unsigned TiedIdx;
00335       if (InlineAsm::isUseOperandTiedToDef(Flags, TiedIdx)) {
00336         for (OpNum = InlineAsm::MIOp_FirstOperand; TiedIdx; --TiedIdx) {
00337           unsigned OpFlags = MI->getOperand(OpNum).getImm();
00338           OpNum += InlineAsm::getNumOperandRegisters(OpFlags) + 1;
00339         }
00340         Flags = MI->getOperand(OpNum).getImm();
00341 
00342         // Later code expects OpNum to be pointing at the register rather than
00343         // the flags.
00344         OpNum += 1;
00345       }
00346 
00347       unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
00348       unsigned RC;
00349       InlineAsm::hasRegClassConstraint(Flags, RC);
00350       if (RC == ARM::GPRPairRegClassID) {
00351         if (NumVals != 1)
00352           return true;
00353         const MachineOperand &MO = MI->getOperand(OpNum);
00354         if (!MO.isReg())
00355           return true;
00356         const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
00357         unsigned Reg = TRI->getSubReg(MO.getReg(), ExtraCode[0] == 'Q' ?
00358             ARM::gsub_0 : ARM::gsub_1);
00359         O << ARMInstPrinter::getRegisterName(Reg);
00360         return false;
00361       }
00362       if (NumVals != 2)
00363         return true;
00364       unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
00365       if (RegOp >= MI->getNumOperands())
00366         return true;
00367       const MachineOperand &MO = MI->getOperand(RegOp);
00368       if (!MO.isReg())
00369         return true;
00370       unsigned Reg = MO.getReg();
00371       O << ARMInstPrinter::getRegisterName(Reg);
00372       return false;
00373     }
00374 
00375     case 'e': // The low doubleword register of a NEON quad register.
00376     case 'f': { // The high doubleword register of a NEON quad register.
00377       if (!MI->getOperand(OpNum).isReg())
00378         return true;
00379       unsigned Reg = MI->getOperand(OpNum).getReg();
00380       if (!ARM::QPRRegClass.contains(Reg))
00381         return true;
00382       const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
00383       unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
00384                                        ARM::dsub_0 : ARM::dsub_1);
00385       O << ARMInstPrinter::getRegisterName(SubReg);
00386       return false;
00387     }
00388 
00389     // This modifier is not yet supported.
00390     case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
00391       return true;
00392     case 'H': { // The highest-numbered register of a pair.
00393       const MachineOperand &MO = MI->getOperand(OpNum);
00394       if (!MO.isReg())
00395         return true;
00396       const MachineFunction &MF = *MI->getParent()->getParent();
00397       const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
00398       unsigned Reg = MO.getReg();
00399       if(!ARM::GPRPairRegClass.contains(Reg))
00400         return false;
00401       Reg = TRI->getSubReg(Reg, ARM::gsub_1);
00402       O << ARMInstPrinter::getRegisterName(Reg);
00403       return false;
00404     }
00405     }
00406   }
00407 
00408   printOperand(MI, OpNum, O);
00409   return false;
00410 }
00411 
00412 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
00413                                           unsigned OpNum, unsigned AsmVariant,
00414                                           const char *ExtraCode,
00415                                           raw_ostream &O) {
00416   // Does this asm operand have a single letter operand modifier?
00417   if (ExtraCode && ExtraCode[0]) {
00418     if (ExtraCode[1] != 0) return true; // Unknown modifier.
00419 
00420     switch (ExtraCode[0]) {
00421       case 'A': // A memory operand for a VLD1/VST1 instruction.
00422       default: return true;  // Unknown modifier.
00423       case 'm': // The base register of a memory operand.
00424         if (!MI->getOperand(OpNum).isReg())
00425           return true;
00426         O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
00427         return false;
00428     }
00429   }
00430 
00431   const MachineOperand &MO = MI->getOperand(OpNum);
00432   assert(MO.isReg() && "unexpected inline asm memory operand");
00433   O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
00434   return false;
00435 }
00436 
00437 static bool isThumb(const MCSubtargetInfo& STI) {
00438   return STI.getFeatureBits()[ARM::ModeThumb];
00439 }
00440 
00441 void ARMAsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo &StartInfo,
00442                                      const MCSubtargetInfo *EndInfo) const {
00443   // If either end mode is unknown (EndInfo == NULL) or different than
00444   // the start mode, then restore the start mode.
00445   const bool WasThumb = isThumb(StartInfo);
00446   if (!EndInfo || WasThumb != isThumb(*EndInfo)) {
00447     OutStreamer->EmitAssemblerFlag(WasThumb ? MCAF_Code16 : MCAF_Code32);
00448   }
00449 }
00450 
00451 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
00452   const Triple &TT = TM.getTargetTriple();
00453   // Use unified assembler syntax.
00454   OutStreamer->EmitAssemblerFlag(MCAF_SyntaxUnified);
00455 
00456   // Emit ARM Build Attributes
00457   if (TT.isOSBinFormatELF())
00458     emitAttributes();
00459 
00460   // Use the triple's architecture and subarchitecture to determine
00461   // if we're thumb for the purposes of the top level code16 assembler
00462   // flag.
00463   bool isThumb = TT.getArch() == Triple::thumb ||
00464                  TT.getArch() == Triple::thumbeb ||
00465                  TT.getSubArch() == Triple::ARMSubArch_v7m ||
00466                  TT.getSubArch() == Triple::ARMSubArch_v6m;
00467   if (!M.getModuleInlineAsm().empty() && isThumb)
00468     OutStreamer->EmitAssemblerFlag(MCAF_Code16);
00469 }
00470 
00471 static void
00472 emitNonLazySymbolPointer(MCStreamer &OutStreamer, MCSymbol *StubLabel,
00473                          MachineModuleInfoImpl::StubValueTy &MCSym) {
00474   // L_foo$stub:
00475   OutStreamer.EmitLabel(StubLabel);
00476   //   .indirect_symbol _foo
00477   OutStreamer.EmitSymbolAttribute(MCSym.getPointer(), MCSA_IndirectSymbol);
00478 
00479   if (MCSym.getInt())
00480     // External to current translation unit.
00481     OutStreamer.EmitIntValue(0, 4/*size*/);
00482   else
00483     // Internal to current translation unit.
00484     //
00485     // When we place the LSDA into the TEXT section, the type info
00486     // pointers need to be indirect and pc-rel. We accomplish this by
00487     // using NLPs; however, sometimes the types are local to the file.
00488     // We need to fill in the value for the NLP in those cases.
00489     OutStreamer.EmitValue(
00490         MCSymbolRefExpr::create(MCSym.getPointer(), OutStreamer.getContext()),
00491         4 /*size*/);
00492 }
00493 
00494 
00495 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
00496   const Triple &TT = TM.getTargetTriple();
00497   if (TT.isOSBinFormatMachO()) {
00498     // All darwin targets use mach-o.
00499     const TargetLoweringObjectFileMachO &TLOFMacho =
00500       static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
00501     MachineModuleInfoMachO &MMIMacho =
00502       MMI->getObjFileInfo<MachineModuleInfoMachO>();
00503 
00504     // Output non-lazy-pointers for external and common global variables.
00505     MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
00506 
00507     if (!Stubs.empty()) {
00508       // Switch with ".non_lazy_symbol_pointer" directive.
00509       OutStreamer->SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
00510       EmitAlignment(2);
00511 
00512       for (auto &Stub : Stubs)
00513         emitNonLazySymbolPointer(*OutStreamer, Stub.first, Stub.second);
00514 
00515       Stubs.clear();
00516       OutStreamer->AddBlankLine();
00517     }
00518 
00519     Stubs = MMIMacho.GetHiddenGVStubList();
00520     if (!Stubs.empty()) {
00521       OutStreamer->SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
00522       EmitAlignment(2);
00523 
00524       for (auto &Stub : Stubs)
00525         emitNonLazySymbolPointer(*OutStreamer, Stub.first, Stub.second);
00526 
00527       Stubs.clear();
00528       OutStreamer->AddBlankLine();
00529     }
00530 
00531     // Funny Darwin hack: This flag tells the linker that no global symbols
00532     // contain code that falls through to other global symbols (e.g. the obvious
00533     // implementation of multiple entry points).  If this doesn't occur, the
00534     // linker can safely perform dead code stripping.  Since LLVM never
00535     // generates code that does this, it is always safe to set.
00536     OutStreamer->EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
00537   }
00538 
00539   // The last attribute to be emitted is ABI_optimization_goals
00540   MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
00541   ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
00542 
00543   if (OptimizationGoals > 0 &&
00544       (Subtarget->isTargetAEABI() || Subtarget->isTargetGNUAEABI()))
00545     ATS.emitAttribute(ARMBuildAttrs::ABI_optimization_goals, OptimizationGoals);
00546   OptimizationGoals = -1;
00547 
00548   ATS.finishAttributeSection();
00549 }
00550 
00551 static bool isV8M(const ARMSubtarget *Subtarget) {
00552   // Note that v8M Baseline is a subset of v6T2!
00553   return (Subtarget->hasV8MBaselineOps() && !Subtarget->hasV6T2Ops()) ||
00554          Subtarget->hasV8MMainlineOps();
00555 }
00556 
00557 //===----------------------------------------------------------------------===//
00558 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
00559 // FIXME:
00560 // The following seem like one-off assembler flags, but they actually need
00561 // to appear in the .ARM.attributes section in ELF.
00562 // Instead of subclassing the MCELFStreamer, we do the work here.
00563 
00564 static ARMBuildAttrs::CPUArch getArchForCPU(StringRef CPU,
00565                                             const ARMSubtarget *Subtarget) {
00566   if (CPU == "xscale")
00567     return ARMBuildAttrs::v5TEJ;
00568 
00569   if (Subtarget->hasV8Ops())
00570     return ARMBuildAttrs::v8_A;
00571   else if (Subtarget->hasV8MMainlineOps())
00572     return ARMBuildAttrs::v8_M_Main;
00573   else if (Subtarget->hasV7Ops()) {
00574     if (Subtarget->isMClass() && Subtarget->hasDSP())
00575       return ARMBuildAttrs::v7E_M;
00576     return ARMBuildAttrs::v7;
00577   } else if (Subtarget->hasV6T2Ops())
00578     return ARMBuildAttrs::v6T2;
00579   else if (Subtarget->hasV8MBaselineOps())
00580     return ARMBuildAttrs::v8_M_Base;
00581   else if (Subtarget->hasV6MOps())
00582     return ARMBuildAttrs::v6S_M;
00583   else if (Subtarget->hasV6Ops())
00584     return ARMBuildAttrs::v6;
00585   else if (Subtarget->hasV5TEOps())
00586     return ARMBuildAttrs::v5TE;
00587   else if (Subtarget->hasV5TOps())
00588     return ARMBuildAttrs::v5T;
00589   else if (Subtarget->hasV4TOps())
00590     return ARMBuildAttrs::v4T;
00591   else
00592     return ARMBuildAttrs::v4;
00593 }
00594 
00595 void ARMAsmPrinter::emitAttributes() {
00596   MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
00597   ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
00598 
00599   ATS.emitTextAttribute(ARMBuildAttrs::conformance, "2.09");
00600 
00601   ATS.switchVendor("aeabi");
00602 
00603   // Compute ARM ELF Attributes based on the default subtarget that
00604   // we'd have constructed. The existing ARM behavior isn't LTO clean
00605   // anyhow.
00606   // FIXME: For ifunc related functions we could iterate over and look
00607   // for a feature string that doesn't match the default one.
00608   const Triple &TT = TM.getTargetTriple();
00609   StringRef CPU = TM.getTargetCPU();
00610   StringRef FS = TM.getTargetFeatureString();
00611   std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
00612   if (!FS.empty()) {
00613     if (!ArchFS.empty())
00614       ArchFS = (Twine(ArchFS) + "," + FS).str();
00615     else
00616       ArchFS = FS;
00617   }
00618   const ARMBaseTargetMachine &ATM =
00619       static_cast<const ARMBaseTargetMachine &>(TM);
00620   const ARMSubtarget STI(TT, CPU, ArchFS, ATM, ATM.isLittleEndian());
00621 
00622   std::string CPUString = STI.getCPUString();
00623 
00624   if (CPUString.find("generic") != 0) { //CPUString doesn't start with "generic"
00625     // FIXME: remove krait check when GNU tools support krait cpu
00626     if (STI.isKrait()) {
00627       ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a9");
00628       // We consider krait as a "cortex-a9" + hwdiv CPU
00629       // Enable hwdiv through ".arch_extension idiv"
00630       if (STI.hasDivide() || STI.hasDivideInARMMode())
00631         ATS.emitArchExtension(ARM::AEK_HWDIV | ARM::AEK_HWDIVARM);
00632     } else
00633       ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, CPUString);
00634   }
00635 
00636   ATS.emitAttribute(ARMBuildAttrs::CPU_arch, getArchForCPU(CPUString, &STI));
00637 
00638   // Tag_CPU_arch_profile must have the default value of 0 when "Architecture
00639   // profile is not applicable (e.g. pre v7, or cross-profile code)".
00640   if (STI.hasV7Ops() || isV8M(&STI)) {
00641     if (STI.isAClass()) {
00642       ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
00643                         ARMBuildAttrs::ApplicationProfile);
00644     } else if (STI.isRClass()) {
00645       ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
00646                         ARMBuildAttrs::RealTimeProfile);
00647     } else if (STI.isMClass()) {
00648       ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
00649                         ARMBuildAttrs::MicroControllerProfile);
00650     }
00651   }
00652 
00653   ATS.emitAttribute(ARMBuildAttrs::ARM_ISA_use,
00654                     STI.hasARMOps() ? ARMBuildAttrs::Allowed
00655                                     : ARMBuildAttrs::Not_Allowed);
00656   if (isV8M(&STI)) {
00657     ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
00658                       ARMBuildAttrs::AllowThumbDerived);
00659   } else if (STI.isThumb1Only()) {
00660     ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use, ARMBuildAttrs::Allowed);
00661   } else if (STI.hasThumb2()) {
00662     ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
00663                       ARMBuildAttrs::AllowThumb32);
00664   }
00665 
00666   if (STI.hasNEON()) {
00667     /* NEON is not exactly a VFP architecture, but GAS emit one of
00668      * neon/neon-fp-armv8/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
00669     if (STI.hasFPARMv8()) {
00670       if (STI.hasCrypto())
00671         ATS.emitFPU(ARM::FK_CRYPTO_NEON_FP_ARMV8);
00672       else
00673         ATS.emitFPU(ARM::FK_NEON_FP_ARMV8);
00674     } else if (STI.hasVFP4())
00675       ATS.emitFPU(ARM::FK_NEON_VFPV4);
00676     else
00677       ATS.emitFPU(STI.hasFP16() ? ARM::FK_NEON_FP16 : ARM::FK_NEON);
00678     // Emit Tag_Advanced_SIMD_arch for ARMv8 architecture
00679     if (STI.hasV8Ops())
00680       ATS.emitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
00681                         STI.hasV8_1aOps() ? ARMBuildAttrs::AllowNeonARMv8_1a:
00682                                             ARMBuildAttrs::AllowNeonARMv8);
00683   } else {
00684     if (STI.hasFPARMv8())
00685       // FPv5 and FP-ARMv8 have the same instructions, so are modeled as one
00686       // FPU, but there are two different names for it depending on the CPU.
00687       ATS.emitFPU(STI.hasD16()
00688                   ? (STI.isFPOnlySP() ? ARM::FK_FPV5_SP_D16 : ARM::FK_FPV5_D16)
00689                   : ARM::FK_FP_ARMV8);
00690     else if (STI.hasVFP4())
00691       ATS.emitFPU(STI.hasD16()
00692                   ? (STI.isFPOnlySP() ? ARM::FK_FPV4_SP_D16 : ARM::FK_VFPV4_D16)
00693                   : ARM::FK_VFPV4);
00694     else if (STI.hasVFP3())
00695       ATS.emitFPU(STI.hasD16()
00696                   // +d16
00697                   ? (STI.isFPOnlySP()
00698                      ? (STI.hasFP16() ? ARM::FK_VFPV3XD_FP16 : ARM::FK_VFPV3XD)
00699                      : (STI.hasFP16() ? ARM::FK_VFPV3_D16_FP16 : ARM::FK_VFPV3_D16))
00700                   // -d16
00701                   : (STI.hasFP16() ? ARM::FK_VFPV3_FP16 : ARM::FK_VFPV3));
00702     else if (STI.hasVFP2())
00703       ATS.emitFPU(ARM::FK_VFPV2);
00704   }
00705 
00706   if (TM.getRelocationModel() == Reloc::PIC_) {
00707     // PIC specific attributes.
00708     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RW_data,
00709                       ARMBuildAttrs::AddressRWPCRel);
00710     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RO_data,
00711                       ARMBuildAttrs::AddressROPCRel);
00712     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_GOT_use,
00713                       ARMBuildAttrs::AddressGOT);
00714   } else {
00715     // Allow direct addressing of imported data for all other relocation models.
00716     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_GOT_use,
00717                       ARMBuildAttrs::AddressDirect);
00718   }
00719 
00720   // Signal various FP modes.
00721   if (!TM.Options.UnsafeFPMath) {
00722     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
00723                       ARMBuildAttrs::IEEEDenormals);
00724     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_exceptions, ARMBuildAttrs::Allowed);
00725 
00726     // If the user has permitted this code to choose the IEEE 754
00727     // rounding at run-time, emit the rounding attribute.
00728     if (TM.Options.HonorSignDependentRoundingFPMathOption)
00729       ATS.emitAttribute(ARMBuildAttrs::ABI_FP_rounding, ARMBuildAttrs::Allowed);
00730   } else {
00731     if (!STI.hasVFP2()) {
00732       // When the target doesn't have an FPU (by design or
00733       // intention), the assumptions made on the software support
00734       // mirror that of the equivalent hardware support *if it
00735       // existed*. For v7 and better we indicate that denormals are
00736       // flushed preserving sign, and for V6 we indicate that
00737       // denormals are flushed to positive zero.
00738       if (STI.hasV7Ops())
00739         ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
00740                           ARMBuildAttrs::PreserveFPSign);
00741     } else if (STI.hasVFP3()) {
00742       // In VFPv4, VFPv4U, VFPv3, or VFPv3U, it is preserved. That is,
00743       // the sign bit of the zero matches the sign bit of the input or
00744       // result that is being flushed to zero.
00745       ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
00746                         ARMBuildAttrs::PreserveFPSign);
00747     }
00748     // For VFPv2 implementations it is implementation defined as
00749     // to whether denormals are flushed to positive zero or to
00750     // whatever the sign of zero is (ARM v7AR ARM 2.7.5). Historically
00751     // LLVM has chosen to flush this to positive zero (most likely for
00752     // GCC compatibility), so that's the chosen value here (the
00753     // absence of its emission implies zero).
00754   }
00755 
00756   // TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath is the
00757   // equivalent of GCC's -ffinite-math-only flag.
00758   if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
00759     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
00760                       ARMBuildAttrs::Allowed);
00761   else
00762     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
00763                       ARMBuildAttrs::AllowIEE754);
00764 
00765   if (STI.allowsUnalignedMem())
00766     ATS.emitAttribute(ARMBuildAttrs::CPU_unaligned_access,
00767                       ARMBuildAttrs::Allowed);
00768   else
00769     ATS.emitAttribute(ARMBuildAttrs::CPU_unaligned_access,
00770                       ARMBuildAttrs::Not_Allowed);
00771 
00772   // FIXME: add more flags to ARMBuildAttributes.h
00773   // 8-bytes alignment stuff.
00774   ATS.emitAttribute(ARMBuildAttrs::ABI_align_needed, 1);
00775   ATS.emitAttribute(ARMBuildAttrs::ABI_align_preserved, 1);
00776 
00777   // ABI_HardFP_use attribute to indicate single precision FP.
00778   if (STI.isFPOnlySP())
00779     ATS.emitAttribute(ARMBuildAttrs::ABI_HardFP_use,
00780                       ARMBuildAttrs::HardFPSinglePrecision);
00781 
00782   // Hard float.  Use both S and D registers and conform to AAPCS-VFP.
00783   if (STI.isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard)
00784     ATS.emitAttribute(ARMBuildAttrs::ABI_VFP_args, ARMBuildAttrs::HardFPAAPCS);
00785 
00786   // FIXME: Should we signal R9 usage?
00787 
00788   if (STI.hasFP16())
00789     ATS.emitAttribute(ARMBuildAttrs::FP_HP_extension, ARMBuildAttrs::AllowHPFP);
00790 
00791   // FIXME: To support emitting this build attribute as GCC does, the
00792   // -mfp16-format option and associated plumbing must be
00793   // supported. For now the __fp16 type is exposed by default, so this
00794   // attribute should be emitted with value 1.
00795   ATS.emitAttribute(ARMBuildAttrs::ABI_FP_16bit_format,
00796                     ARMBuildAttrs::FP16FormatIEEE);
00797 
00798   if (STI.hasMPExtension())
00799     ATS.emitAttribute(ARMBuildAttrs::MPextension_use, ARMBuildAttrs::AllowMP);
00800 
00801   // Hardware divide in ARM mode is part of base arch, starting from ARMv8.
00802   // If only Thumb hwdiv is present, it must also be in base arch (ARMv7-R/M).
00803   // It is not possible to produce DisallowDIV: if hwdiv is present in the base
00804   // arch, supplying -hwdiv downgrades the effective arch, via ClearImpliedBits.
00805   // AllowDIVExt is only emitted if hwdiv isn't available in the base arch;
00806   // otherwise, the default value (AllowDIVIfExists) applies.
00807   if (STI.hasDivideInARMMode() && !STI.hasV8Ops())
00808     ATS.emitAttribute(ARMBuildAttrs::DIV_use, ARMBuildAttrs::AllowDIVExt);
00809 
00810   if (STI.hasDSP() && isV8M(&STI))
00811     ATS.emitAttribute(ARMBuildAttrs::DSP_extension, ARMBuildAttrs::Allowed);
00812 
00813   if (MMI) {
00814     if (const Module *SourceModule = MMI->getModule()) {
00815       // ABI_PCS_wchar_t to indicate wchar_t width
00816       // FIXME: There is no way to emit value 0 (wchar_t prohibited).
00817       if (auto WCharWidthValue = mdconst::extract_or_null<ConstantInt>(
00818               SourceModule->getModuleFlag("wchar_size"))) {
00819         int WCharWidth = WCharWidthValue->getZExtValue();
00820         assert((WCharWidth == 2 || WCharWidth == 4) &&
00821                "wchar_t width must be 2 or 4 bytes");
00822         ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_wchar_t, WCharWidth);
00823       }
00824 
00825       // ABI_enum_size to indicate enum width
00826       // FIXME: There is no way to emit value 0 (enums prohibited) or value 3
00827       //        (all enums contain a value needing 32 bits to encode).
00828       if (auto EnumWidthValue = mdconst::extract_or_null<ConstantInt>(
00829               SourceModule->getModuleFlag("min_enum_size"))) {
00830         int EnumWidth = EnumWidthValue->getZExtValue();
00831         assert((EnumWidth == 1 || EnumWidth == 4) &&
00832                "Minimum enum width must be 1 or 4 bytes");
00833         int EnumBuildAttr = EnumWidth == 1 ? 1 : 2;
00834         ATS.emitAttribute(ARMBuildAttrs::ABI_enum_size, EnumBuildAttr);
00835       }
00836     }
00837   }
00838 
00839   // TODO: We currently only support either reserving the register, or treating
00840   // it as another callee-saved register, but not as SB or a TLS pointer; It
00841   // would instead be nicer to push this from the frontend as metadata, as we do
00842   // for the wchar and enum size tags
00843   if (STI.isR9Reserved())
00844     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use, ARMBuildAttrs::R9Reserved);
00845   else
00846     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use, ARMBuildAttrs::R9IsGPR);
00847 
00848   if (STI.hasTrustZone() && STI.hasVirtualization())
00849     ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
00850                       ARMBuildAttrs::AllowTZVirtualization);
00851   else if (STI.hasTrustZone())
00852     ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
00853                       ARMBuildAttrs::AllowTZ);
00854   else if (STI.hasVirtualization())
00855     ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
00856                       ARMBuildAttrs::AllowVirtualization);
00857 }
00858 
00859 //===----------------------------------------------------------------------===//
00860 
00861 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
00862                              unsigned LabelId, MCContext &Ctx) {
00863 
00864   MCSymbol *Label = Ctx.getOrCreateSymbol(Twine(Prefix)
00865                        + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
00866   return Label;
00867 }
00868 
00869 static MCSymbolRefExpr::VariantKind
00870 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
00871   switch (Modifier) {
00872   case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
00873   case ARMCP::TLSGD:       return MCSymbolRefExpr::VK_TLSGD;
00874   case ARMCP::TPOFF:       return MCSymbolRefExpr::VK_TPOFF;
00875   case ARMCP::GOTTPOFF:    return MCSymbolRefExpr::VK_GOTTPOFF;
00876   case ARMCP::GOT_PREL:    return MCSymbolRefExpr::VK_ARM_GOT_PREL;
00877   }
00878   llvm_unreachable("Invalid ARMCPModifier!");
00879 }
00880 
00881 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV,
00882                                         unsigned char TargetFlags) {
00883   if (Subtarget->isTargetMachO()) {
00884     bool IsIndirect = (TargetFlags & ARMII::MO_NONLAZY) &&
00885       Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
00886 
00887     if (!IsIndirect)
00888       return getSymbol(GV);
00889 
00890     // FIXME: Remove this when Darwin transition to @GOT like syntax.
00891     MCSymbol *MCSym = getSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
00892     MachineModuleInfoMachO &MMIMachO =
00893       MMI->getObjFileInfo<MachineModuleInfoMachO>();
00894     MachineModuleInfoImpl::StubValueTy &StubSym =
00895       GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym)
00896                                 : MMIMachO.getGVStubEntry(MCSym);
00897     if (!StubSym.getPointer())
00898       StubSym = MachineModuleInfoImpl::StubValueTy(getSymbol(GV),
00899                                                    !GV->hasInternalLinkage());
00900     return MCSym;
00901   } else if (Subtarget->isTargetCOFF()) {
00902     assert(Subtarget->isTargetWindows() &&
00903            "Windows is the only supported COFF target");
00904 
00905     bool IsIndirect = (TargetFlags & ARMII::MO_DLLIMPORT);
00906     if (!IsIndirect)
00907       return getSymbol(GV);
00908 
00909     SmallString<128> Name;
00910     Name = "__imp_";
00911     getNameWithPrefix(Name, GV);
00912 
00913     return OutContext.getOrCreateSymbol(Name);
00914   } else if (Subtarget->isTargetELF()) {
00915     return getSymbol(GV);
00916   }
00917   llvm_unreachable("unexpected target");
00918 }
00919 
00920 void ARMAsmPrinter::
00921 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
00922   const DataLayout &DL = getDataLayout();
00923   int Size = DL.getTypeAllocSize(MCPV->getType());
00924 
00925   ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
00926 
00927   MCSymbol *MCSym;
00928   if (ACPV->isLSDA()) {
00929     MCSym = getCurExceptionSym();
00930   } else if (ACPV->isBlockAddress()) {
00931     const BlockAddress *BA =
00932       cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
00933     MCSym = GetBlockAddressSymbol(BA);
00934   } else if (ACPV->isGlobalValue()) {
00935     const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
00936 
00937     // On Darwin, const-pool entries may get the "FOO$non_lazy_ptr" mangling, so
00938     // flag the global as MO_NONLAZY.
00939     unsigned char TF = Subtarget->isTargetMachO() ? ARMII::MO_NONLAZY : 0;
00940     MCSym = GetARMGVSymbol(GV, TF);
00941   } else if (ACPV->isMachineBasicBlock()) {
00942     const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
00943     MCSym = MBB->getSymbol();
00944   } else {
00945     assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
00946     const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
00947     MCSym = GetExternalSymbolSymbol(Sym);
00948   }
00949 
00950   // Create an MCSymbol for the reference.
00951   const MCExpr *Expr =
00952     MCSymbolRefExpr::create(MCSym, getModifierVariantKind(ACPV->getModifier()),
00953                             OutContext);
00954 
00955   if (ACPV->getPCAdjustment()) {
00956     MCSymbol *PCLabel =
00957         getPICLabel(DL.getPrivateGlobalPrefix(), getFunctionNumber(),
00958                     ACPV->getLabelId(), OutContext);
00959     const MCExpr *PCRelExpr = MCSymbolRefExpr::create(PCLabel, OutContext);
00960     PCRelExpr =
00961       MCBinaryExpr::createAdd(PCRelExpr,
00962                               MCConstantExpr::create(ACPV->getPCAdjustment(),
00963                                                      OutContext),
00964                               OutContext);
00965     if (ACPV->mustAddCurrentAddress()) {
00966       // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
00967       // label, so just emit a local label end reference that instead.
00968       MCSymbol *DotSym = OutContext.createTempSymbol();
00969       OutStreamer->EmitLabel(DotSym);
00970       const MCExpr *DotExpr = MCSymbolRefExpr::create(DotSym, OutContext);
00971       PCRelExpr = MCBinaryExpr::createSub(PCRelExpr, DotExpr, OutContext);
00972     }
00973     Expr = MCBinaryExpr::createSub(Expr, PCRelExpr, OutContext);
00974   }
00975   OutStreamer->EmitValue(Expr, Size);
00976 }
00977 
00978 void ARMAsmPrinter::EmitJumpTableAddrs(const MachineInstr *MI) {
00979   const MachineOperand &MO1 = MI->getOperand(1);
00980   unsigned JTI = MO1.getIndex();
00981 
00982   // Make sure the Thumb jump table is 4-byte aligned. This will be a nop for
00983   // ARM mode tables.
00984   EmitAlignment(2);
00985 
00986   // Emit a label for the jump table.
00987   MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
00988   OutStreamer->EmitLabel(JTISymbol);
00989 
00990   // Mark the jump table as data-in-code.
00991   OutStreamer->EmitDataRegion(MCDR_DataRegionJT32);
00992 
00993   // Emit each entry of the table.
00994   const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
00995   const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
00996   const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
00997 
00998   for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
00999     MachineBasicBlock *MBB = JTBBs[i];
01000     // Construct an MCExpr for the entry. We want a value of the form:
01001     // (BasicBlockAddr - TableBeginAddr)
01002     //
01003     // For example, a table with entries jumping to basic blocks BB0 and BB1
01004     // would look like:
01005     // LJTI_0_0:
01006     //    .word (LBB0 - LJTI_0_0)
01007     //    .word (LBB1 - LJTI_0_0)
01008     const MCExpr *Expr = MCSymbolRefExpr::create(MBB->getSymbol(), OutContext);
01009 
01010     if (TM.getRelocationModel() == Reloc::PIC_)
01011       Expr = MCBinaryExpr::createSub(Expr, MCSymbolRefExpr::create(JTISymbol,
01012                                                                    OutContext),
01013                                      OutContext);
01014     // If we're generating a table of Thumb addresses in static relocation
01015     // model, we need to add one to keep interworking correctly.
01016     else if (AFI->isThumbFunction())
01017       Expr = MCBinaryExpr::createAdd(Expr, MCConstantExpr::create(1,OutContext),
01018                                      OutContext);
01019     OutStreamer->EmitValue(Expr, 4);
01020   }
01021   // Mark the end of jump table data-in-code region.
01022   OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
01023 }
01024 
01025 void ARMAsmPrinter::EmitJumpTableInsts(const MachineInstr *MI) {
01026   const MachineOperand &MO1 = MI->getOperand(1);
01027   unsigned JTI = MO1.getIndex();
01028 
01029   MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
01030   OutStreamer->EmitLabel(JTISymbol);
01031 
01032   // Emit each entry of the table.
01033   const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
01034   const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
01035   const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
01036 
01037   for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
01038     MachineBasicBlock *MBB = JTBBs[i];
01039     const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::create(MBB->getSymbol(),
01040                                                           OutContext);
01041     // If this isn't a TBB or TBH, the entries are direct branch instructions.
01042     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2B)
01043         .addExpr(MBBSymbolExpr)
01044         .addImm(ARMCC::AL)
01045         .addReg(0));
01046   }
01047 }
01048 
01049 void ARMAsmPrinter::EmitJumpTableTBInst(const MachineInstr *MI,
01050                                         unsigned OffsetWidth) {
01051   assert((OffsetWidth == 1 || OffsetWidth == 2) && "invalid tbb/tbh width");
01052   const MachineOperand &MO1 = MI->getOperand(1);
01053   unsigned JTI = MO1.getIndex();
01054 
01055   MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
01056   OutStreamer->EmitLabel(JTISymbol);
01057 
01058   // Emit each entry of the table.
01059   const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
01060   const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
01061   const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
01062 
01063   // Mark the jump table as data-in-code.
01064   OutStreamer->EmitDataRegion(OffsetWidth == 1 ? MCDR_DataRegionJT8
01065                                                : MCDR_DataRegionJT16);
01066 
01067   for (auto MBB : JTBBs) {
01068     const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::create(MBB->getSymbol(),
01069                                                           OutContext);
01070     // Otherwise it's an offset from the dispatch instruction. Construct an
01071     // MCExpr for the entry. We want a value of the form:
01072     // (BasicBlockAddr - TBBInstAddr + 4) / 2
01073     //
01074     // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
01075     // would look like:
01076     // LJTI_0_0:
01077     //    .byte (LBB0 - (LCPI0_0 + 4)) / 2
01078     //    .byte (LBB1 - (LCPI0_0 + 4)) / 2
01079     // where LCPI0_0 is a label defined just before the TBB instruction using
01080     // this table.
01081     MCSymbol *TBInstPC = GetCPISymbol(MI->getOperand(0).getImm());
01082     const MCExpr *Expr = MCBinaryExpr::createAdd(
01083         MCSymbolRefExpr::create(TBInstPC, OutContext),
01084         MCConstantExpr::create(4, OutContext), OutContext);
01085     Expr = MCBinaryExpr::createSub(MBBSymbolExpr, Expr, OutContext);
01086     Expr = MCBinaryExpr::createDiv(Expr, MCConstantExpr::create(2, OutContext),
01087                                    OutContext);
01088     OutStreamer->EmitValue(Expr, OffsetWidth);
01089   }
01090   // Mark the end of jump table data-in-code region. 32-bit offsets use
01091   // actual branch instructions here, so we don't mark those as a data-region
01092   // at all.
01093   OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
01094 
01095   // Make sure the next instruction is 2-byte aligned.
01096   EmitAlignment(1);
01097 }
01098 
01099 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
01100   assert(MI->getFlag(MachineInstr::FrameSetup) &&
01101       "Only instruction which are involved into frame setup code are allowed");
01102 
01103   MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
01104   ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
01105   const MachineFunction &MF = *MI->getParent()->getParent();
01106   const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
01107   const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
01108 
01109   unsigned FramePtr = RegInfo->getFrameRegister(MF);
01110   unsigned Opc = MI->getOpcode();
01111   unsigned SrcReg, DstReg;
01112 
01113   if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
01114     // Two special cases:
01115     // 1) tPUSH does not have src/dst regs.
01116     // 2) for Thumb1 code we sometimes materialize the constant via constpool
01117     // load. Yes, this is pretty fragile, but for now I don't see better
01118     // way... :(
01119     SrcReg = DstReg = ARM::SP;
01120   } else {
01121     SrcReg = MI->getOperand(1).getReg();
01122     DstReg = MI->getOperand(0).getReg();
01123   }
01124 
01125   // Try to figure out the unwinding opcode out of src / dst regs.
01126   if (MI->mayStore()) {
01127     // Register saves.
01128     assert(DstReg == ARM::SP &&
01129            "Only stack pointer as a destination reg is supported");
01130 
01131     SmallVector<unsigned, 4> RegList;
01132     // Skip src & dst reg, and pred ops.
01133     unsigned StartOp = 2 + 2;
01134     // Use all the operands.
01135     unsigned NumOffset = 0;
01136 
01137     switch (Opc) {
01138     default:
01139       MI->dump();
01140       llvm_unreachable("Unsupported opcode for unwinding information");
01141     case ARM::tPUSH:
01142       // Special case here: no src & dst reg, but two extra imp ops.
01143       StartOp = 2; NumOffset = 2;
01144     case ARM::STMDB_UPD:
01145     case ARM::t2STMDB_UPD:
01146     case ARM::VSTMDDB_UPD:
01147       assert(SrcReg == ARM::SP &&
01148              "Only stack pointer as a source reg is supported");
01149       for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
01150            i != NumOps; ++i) {
01151         const MachineOperand &MO = MI->getOperand(i);
01152         // Actually, there should never be any impdef stuff here. Skip it
01153         // temporary to workaround PR11902.
01154         if (MO.isImplicit())
01155           continue;
01156         RegList.push_back(MO.getReg());
01157       }
01158       break;
01159     case ARM::STR_PRE_IMM:
01160     case ARM::STR_PRE_REG:
01161     case ARM::t2STR_PRE:
01162       assert(MI->getOperand(2).getReg() == ARM::SP &&
01163              "Only stack pointer as a source reg is supported");
01164       RegList.push_back(SrcReg);
01165       break;
01166     }
01167     if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM)
01168       ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
01169   } else {
01170     // Changes of stack / frame pointer.
01171     if (SrcReg == ARM::SP) {
01172       int64_t Offset = 0;
01173       switch (Opc) {
01174       default:
01175         MI->dump();
01176         llvm_unreachable("Unsupported opcode for unwinding information");
01177       case ARM::MOVr:
01178       case ARM::tMOVr:
01179         Offset = 0;
01180         break;
01181       case ARM::ADDri:
01182       case ARM::t2ADDri:
01183         Offset = -MI->getOperand(2).getImm();
01184         break;
01185       case ARM::SUBri:
01186       case ARM::t2SUBri:
01187         Offset = MI->getOperand(2).getImm();
01188         break;
01189       case ARM::tSUBspi:
01190         Offset = MI->getOperand(2).getImm()*4;
01191         break;
01192       case ARM::tADDspi:
01193       case ARM::tADDrSPi:
01194         Offset = -MI->getOperand(2).getImm()*4;
01195         break;
01196       case ARM::tLDRpci: {
01197         // Grab the constpool index and check, whether it corresponds to
01198         // original or cloned constpool entry.
01199         unsigned CPI = MI->getOperand(1).getIndex();
01200         const MachineConstantPool *MCP = MF.getConstantPool();
01201         if (CPI >= MCP->getConstants().size())
01202           CPI = AFI.getOriginalCPIdx(CPI);
01203         assert(CPI != -1U && "Invalid constpool index");
01204 
01205         // Derive the actual offset.
01206         const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
01207         assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
01208         // FIXME: Check for user, it should be "add" instruction!
01209         Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
01210         break;
01211       }
01212       }
01213 
01214       if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM) {
01215         if (DstReg == FramePtr && FramePtr != ARM::SP)
01216           // Set-up of the frame pointer. Positive values correspond to "add"
01217           // instruction.
01218           ATS.emitSetFP(FramePtr, ARM::SP, -Offset);
01219         else if (DstReg == ARM::SP) {
01220           // Change of SP by an offset. Positive values correspond to "sub"
01221           // instruction.
01222           ATS.emitPad(Offset);
01223         } else {
01224           // Move of SP to a register.  Positive values correspond to an "add"
01225           // instruction.
01226           ATS.emitMovSP(DstReg, -Offset);
01227         }
01228       }
01229     } else if (DstReg == ARM::SP) {
01230       MI->dump();
01231       llvm_unreachable("Unsupported opcode for unwinding information");
01232     }
01233     else {
01234       MI->dump();
01235       llvm_unreachable("Unsupported opcode for unwinding information");
01236     }
01237   }
01238 }
01239 
01240 // Simple pseudo-instructions have their lowering (with expansion to real
01241 // instructions) auto-generated.
01242 #include "ARMGenMCPseudoLowering.inc"
01243 
01244 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
01245   const DataLayout &DL = getDataLayout();
01246 
01247   // If we just ended a constant pool, mark it as such.
01248   if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
01249     OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
01250     InConstantPool = false;
01251   }
01252 
01253   // Emit unwinding stuff for frame-related instructions
01254   if (Subtarget->isTargetEHABICompatible() &&
01255        MI->getFlag(MachineInstr::FrameSetup))
01256     EmitUnwindingInstruction(MI);
01257 
01258   // Do any auto-generated pseudo lowerings.
01259   if (emitPseudoExpansionLowering(*OutStreamer, MI))
01260     return;
01261 
01262   assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
01263          "Pseudo flag setting opcode should be expanded early");
01264 
01265   // Check for manual lowerings.
01266   unsigned Opc = MI->getOpcode();
01267   switch (Opc) {
01268   case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
01269   case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing");
01270   case ARM::LEApcrel:
01271   case ARM::tLEApcrel:
01272   case ARM::t2LEApcrel: {
01273     // FIXME: Need to also handle globals and externals
01274     MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex());
01275     EmitToStreamer(*OutStreamer, MCInstBuilder(MI->getOpcode() ==
01276                                                ARM::t2LEApcrel ? ARM::t2ADR
01277                   : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
01278                      : ARM::ADR))
01279       .addReg(MI->getOperand(0).getReg())
01280       .addExpr(MCSymbolRefExpr::create(CPISymbol, OutContext))
01281       // Add predicate operands.
01282       .addImm(MI->getOperand(2).getImm())
01283       .addReg(MI->getOperand(3).getReg()));
01284     return;
01285   }
01286   case ARM::LEApcrelJT:
01287   case ARM::tLEApcrelJT:
01288   case ARM::t2LEApcrelJT: {
01289     MCSymbol *JTIPICSymbol =
01290       GetARMJTIPICJumpTableLabel(MI->getOperand(1).getIndex());
01291     EmitToStreamer(*OutStreamer, MCInstBuilder(MI->getOpcode() ==
01292                                                ARM::t2LEApcrelJT ? ARM::t2ADR
01293                   : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
01294                      : ARM::ADR))
01295       .addReg(MI->getOperand(0).getReg())
01296       .addExpr(MCSymbolRefExpr::create(JTIPICSymbol, OutContext))
01297       // Add predicate operands.
01298       .addImm(MI->getOperand(2).getImm())
01299       .addReg(MI->getOperand(3).getReg()));
01300     return;
01301   }
01302   // Darwin call instructions are just normal call instructions with different
01303   // clobber semantics (they clobber R9).
01304   case ARM::BX_CALL: {
01305     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr)
01306       .addReg(ARM::LR)
01307       .addReg(ARM::PC)
01308       // Add predicate operands.
01309       .addImm(ARMCC::AL)
01310       .addReg(0)
01311       // Add 's' bit operand (always reg0 for this)
01312       .addReg(0));
01313 
01314     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::BX)
01315       .addReg(MI->getOperand(0).getReg()));
01316     return;
01317   }
01318   case ARM::tBX_CALL: {
01319     if (Subtarget->hasV5TOps())
01320       llvm_unreachable("Expected BLX to be selected for v5t+");
01321 
01322     // On ARM v4t, when doing a call from thumb mode, we need to ensure
01323     // that the saved lr has its LSB set correctly (the arch doesn't
01324     // have blx).
01325     // So here we generate a bl to a small jump pad that does bx rN.
01326     // The jump pads are emitted after the function body.
01327 
01328     unsigned TReg = MI->getOperand(0).getReg();
01329     MCSymbol *TRegSym = nullptr;
01330     for (unsigned i = 0, e = ThumbIndirectPads.size(); i < e; i++) {
01331       if (ThumbIndirectPads[i].first == TReg) {
01332         TRegSym = ThumbIndirectPads[i].second;
01333         break;
01334       }
01335     }
01336 
01337     if (!TRegSym) {
01338       TRegSym = OutContext.createTempSymbol();
01339       ThumbIndirectPads.push_back(std::make_pair(TReg, TRegSym));
01340     }
01341 
01342     // Create a link-saving branch to the Reg Indirect Jump Pad.
01343     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tBL)
01344         // Predicate comes first here.
01345         .addImm(ARMCC::AL).addReg(0)
01346         .addExpr(MCSymbolRefExpr::create(TRegSym, OutContext)));
01347     return;
01348   }
01349   case ARM::BMOVPCRX_CALL: {
01350     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr)
01351       .addReg(ARM::LR)
01352       .addReg(ARM::PC)
01353       // Add predicate operands.
01354       .addImm(ARMCC::AL)
01355       .addReg(0)
01356       // Add 's' bit operand (always reg0 for this)
01357       .addReg(0));
01358 
01359     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr)
01360       .addReg(ARM::PC)
01361       .addReg(MI->getOperand(0).getReg())
01362       // Add predicate operands.
01363       .addImm(ARMCC::AL)
01364       .addReg(0)
01365       // Add 's' bit operand (always reg0 for this)
01366       .addReg(0));
01367     return;
01368   }
01369   case ARM::BMOVPCB_CALL: {
01370     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr)
01371       .addReg(ARM::LR)
01372       .addReg(ARM::PC)
01373       // Add predicate operands.
01374       .addImm(ARMCC::AL)
01375       .addReg(0)
01376       // Add 's' bit operand (always reg0 for this)
01377       .addReg(0));
01378 
01379     const MachineOperand &Op = MI->getOperand(0);
01380     const GlobalValue *GV = Op.getGlobal();
01381     const unsigned TF = Op.getTargetFlags();
01382     MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
01383     const MCExpr *GVSymExpr = MCSymbolRefExpr::create(GVSym, OutContext);
01384     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::Bcc)
01385       .addExpr(GVSymExpr)
01386       // Add predicate operands.
01387       .addImm(ARMCC::AL)
01388       .addReg(0));
01389     return;
01390   }
01391   case ARM::MOVi16_ga_pcrel:
01392   case ARM::t2MOVi16_ga_pcrel: {
01393     MCInst TmpInst;
01394     TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
01395     TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
01396 
01397     unsigned TF = MI->getOperand(1).getTargetFlags();
01398     const GlobalValue *GV = MI->getOperand(1).getGlobal();
01399     MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
01400     const MCExpr *GVSymExpr = MCSymbolRefExpr::create(GVSym, OutContext);
01401 
01402     MCSymbol *LabelSym =
01403         getPICLabel(DL.getPrivateGlobalPrefix(), getFunctionNumber(),
01404                     MI->getOperand(2).getImm(), OutContext);
01405     const MCExpr *LabelSymExpr= MCSymbolRefExpr::create(LabelSym, OutContext);
01406     unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
01407     const MCExpr *PCRelExpr =
01408       ARMMCExpr::createLower16(MCBinaryExpr::createSub(GVSymExpr,
01409                                       MCBinaryExpr::createAdd(LabelSymExpr,
01410                                       MCConstantExpr::create(PCAdj, OutContext),
01411                                       OutContext), OutContext), OutContext);
01412       TmpInst.addOperand(MCOperand::createExpr(PCRelExpr));
01413 
01414     // Add predicate operands.
01415     TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
01416     TmpInst.addOperand(MCOperand::createReg(0));
01417     // Add 's' bit operand (always reg0 for this)
01418     TmpInst.addOperand(MCOperand::createReg(0));
01419     EmitToStreamer(*OutStreamer, TmpInst);
01420     return;
01421   }
01422   case ARM::MOVTi16_ga_pcrel:
01423   case ARM::t2MOVTi16_ga_pcrel: {
01424     MCInst TmpInst;
01425     TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
01426                       ? ARM::MOVTi16 : ARM::t2MOVTi16);
01427     TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
01428     TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg()));
01429 
01430     unsigned TF = MI->getOperand(2).getTargetFlags();
01431     const GlobalValue *GV = MI->getOperand(2).getGlobal();
01432     MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
01433     const MCExpr *GVSymExpr = MCSymbolRefExpr::create(GVSym, OutContext);
01434 
01435     MCSymbol *LabelSym =
01436         getPICLabel(DL.getPrivateGlobalPrefix(), getFunctionNumber(),
01437                     MI->getOperand(3).getImm(), OutContext);
01438     const MCExpr *LabelSymExpr= MCSymbolRefExpr::create(LabelSym, OutContext);
01439     unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
01440     const MCExpr *PCRelExpr =
01441         ARMMCExpr::createUpper16(MCBinaryExpr::createSub(GVSymExpr,
01442                                    MCBinaryExpr::createAdd(LabelSymExpr,
01443                                       MCConstantExpr::create(PCAdj, OutContext),
01444                                           OutContext), OutContext), OutContext);
01445       TmpInst.addOperand(MCOperand::createExpr(PCRelExpr));
01446     // Add predicate operands.
01447     TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
01448     TmpInst.addOperand(MCOperand::createReg(0));
01449     // Add 's' bit operand (always reg0 for this)
01450     TmpInst.addOperand(MCOperand::createReg(0));
01451     EmitToStreamer(*OutStreamer, TmpInst);
01452     return;
01453   }
01454   case ARM::tPICADD: {
01455     // This is a pseudo op for a label + instruction sequence, which looks like:
01456     // LPC0:
01457     //     add r0, pc
01458     // This adds the address of LPC0 to r0.
01459 
01460     // Emit the label.
01461     OutStreamer->EmitLabel(getPICLabel(DL.getPrivateGlobalPrefix(),
01462                                        getFunctionNumber(),
01463                                        MI->getOperand(2).getImm(), OutContext));
01464 
01465     // Form and emit the add.
01466     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDhirr)
01467       .addReg(MI->getOperand(0).getReg())
01468       .addReg(MI->getOperand(0).getReg())
01469       .addReg(ARM::PC)
01470       // Add predicate operands.
01471       .addImm(ARMCC::AL)
01472       .addReg(0));
01473     return;
01474   }
01475   case ARM::PICADD: {
01476     // This is a pseudo op for a label + instruction sequence, which looks like:
01477     // LPC0:
01478     //     add r0, pc, r0
01479     // This adds the address of LPC0 to r0.
01480 
01481     // Emit the label.
01482     OutStreamer->EmitLabel(getPICLabel(DL.getPrivateGlobalPrefix(),
01483                                        getFunctionNumber(),
01484                                        MI->getOperand(2).getImm(), OutContext));
01485 
01486     // Form and emit the add.
01487     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDrr)
01488       .addReg(MI->getOperand(0).getReg())
01489       .addReg(ARM::PC)
01490       .addReg(MI->getOperand(1).getReg())
01491       // Add predicate operands.
01492       .addImm(MI->getOperand(3).getImm())
01493       .addReg(MI->getOperand(4).getReg())
01494       // Add 's' bit operand (always reg0 for this)
01495       .addReg(0));
01496     return;
01497   }
01498   case ARM::PICSTR:
01499   case ARM::PICSTRB:
01500   case ARM::PICSTRH:
01501   case ARM::PICLDR:
01502   case ARM::PICLDRB:
01503   case ARM::PICLDRH:
01504   case ARM::PICLDRSB:
01505   case ARM::PICLDRSH: {
01506     // This is a pseudo op for a label + instruction sequence, which looks like:
01507     // LPC0:
01508     //     OP r0, [pc, r0]
01509     // The LCP0 label is referenced by a constant pool entry in order to get
01510     // a PC-relative address at the ldr instruction.
01511 
01512     // Emit the label.
01513     OutStreamer->EmitLabel(getPICLabel(DL.getPrivateGlobalPrefix(),
01514                                        getFunctionNumber(),
01515                                        MI->getOperand(2).getImm(), OutContext));
01516 
01517     // Form and emit the load
01518     unsigned Opcode;
01519     switch (MI->getOpcode()) {
01520     default:
01521       llvm_unreachable("Unexpected opcode!");
01522     case ARM::PICSTR:   Opcode = ARM::STRrs; break;
01523     case ARM::PICSTRB:  Opcode = ARM::STRBrs; break;
01524     case ARM::PICSTRH:  Opcode = ARM::STRH; break;
01525     case ARM::PICLDR:   Opcode = ARM::LDRrs; break;
01526     case ARM::PICLDRB:  Opcode = ARM::LDRBrs; break;
01527     case ARM::PICLDRH:  Opcode = ARM::LDRH; break;
01528     case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
01529     case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
01530     }
01531     EmitToStreamer(*OutStreamer, MCInstBuilder(Opcode)
01532       .addReg(MI->getOperand(0).getReg())
01533       .addReg(ARM::PC)
01534       .addReg(MI->getOperand(1).getReg())
01535       .addImm(0)
01536       // Add predicate operands.
01537       .addImm(MI->getOperand(3).getImm())
01538       .addReg(MI->getOperand(4).getReg()));
01539 
01540     return;
01541   }
01542   case ARM::CONSTPOOL_ENTRY: {
01543     /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
01544     /// in the function.  The first operand is the ID# for this instruction, the
01545     /// second is the index into the MachineConstantPool that this is, the third
01546     /// is the size in bytes of this constant pool entry.
01547     /// The required alignment is specified on the basic block holding this MI.
01548     unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
01549     unsigned CPIdx   = (unsigned)MI->getOperand(1).getIndex();
01550 
01551     // If this is the first entry of the pool, mark it.
01552     if (!InConstantPool) {
01553       OutStreamer->EmitDataRegion(MCDR_DataRegion);
01554       InConstantPool = true;
01555     }
01556 
01557     OutStreamer->EmitLabel(GetCPISymbol(LabelId));
01558 
01559     const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
01560     if (MCPE.isMachineConstantPoolEntry())
01561       EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
01562     else
01563       EmitGlobalConstant(DL, MCPE.Val.ConstVal);
01564     return;
01565   }
01566   case ARM::JUMPTABLE_ADDRS:
01567     EmitJumpTableAddrs(MI);
01568     return;
01569   case ARM::JUMPTABLE_INSTS:
01570     EmitJumpTableInsts(MI);
01571     return;
01572   case ARM::JUMPTABLE_TBB:
01573   case ARM::JUMPTABLE_TBH:
01574     EmitJumpTableTBInst(MI, MI->getOpcode() == ARM::JUMPTABLE_TBB ? 1 : 2);
01575     return;
01576   case ARM::t2BR_JT: {
01577     // Lower and emit the instruction itself, then the jump table following it.
01578     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVr)
01579       .addReg(ARM::PC)
01580       .addReg(MI->getOperand(0).getReg())
01581       // Add predicate operands.
01582       .addImm(ARMCC::AL)
01583       .addReg(0));
01584     return;
01585   }
01586   case ARM::t2TBB_JT:
01587   case ARM::t2TBH_JT: {
01588     unsigned Opc = MI->getOpcode() == ARM::t2TBB_JT ? ARM::t2TBB : ARM::t2TBH;
01589     // Lower and emit the PC label, then the instruction itself.
01590     OutStreamer->EmitLabel(GetCPISymbol(MI->getOperand(3).getImm()));
01591     EmitToStreamer(*OutStreamer, MCInstBuilder(Opc)
01592                                      .addReg(MI->getOperand(0).getReg())
01593                                      .addReg(MI->getOperand(1).getReg())
01594                                      // Add predicate operands.
01595                                      .addImm(ARMCC::AL)
01596                                      .addReg(0));
01597     return;
01598   }
01599   case ARM::tBR_JTr:
01600   case ARM::BR_JTr: {
01601     // Lower and emit the instruction itself, then the jump table following it.
01602     // mov pc, target
01603     MCInst TmpInst;
01604     unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
01605       ARM::MOVr : ARM::tMOVr;
01606     TmpInst.setOpcode(Opc);
01607     TmpInst.addOperand(MCOperand::createReg(ARM::PC));
01608     TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
01609     // Add predicate operands.
01610     TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
01611     TmpInst.addOperand(MCOperand::createReg(0));
01612     // Add 's' bit operand (always reg0 for this)
01613     if (Opc == ARM::MOVr)
01614       TmpInst.addOperand(MCOperand::createReg(0));
01615     EmitToStreamer(*OutStreamer, TmpInst);
01616     return;
01617   }
01618   case ARM::BR_JTm: {
01619     // Lower and emit the instruction itself, then the jump table following it.
01620     // ldr pc, target
01621     MCInst TmpInst;
01622     if (MI->getOperand(1).getReg() == 0) {
01623       // literal offset
01624       TmpInst.setOpcode(ARM::LDRi12);
01625       TmpInst.addOperand(MCOperand::createReg(ARM::PC));
01626       TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
01627       TmpInst.addOperand(MCOperand::createImm(MI->getOperand(2).getImm()));
01628     } else {
01629       TmpInst.setOpcode(ARM::LDRrs);
01630       TmpInst.addOperand(MCOperand::createReg(ARM::PC));
01631       TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
01632       TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg()));
01633       TmpInst.addOperand(MCOperand::createImm(0));
01634     }
01635     // Add predicate operands.
01636     TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
01637     TmpInst.addOperand(MCOperand::createReg(0));
01638     EmitToStreamer(*OutStreamer, TmpInst);
01639     return;
01640   }
01641   case ARM::BR_JTadd: {
01642     // Lower and emit the instruction itself, then the jump table following it.
01643     // add pc, target, idx
01644     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDrr)
01645       .addReg(ARM::PC)
01646       .addReg(MI->getOperand(0).getReg())
01647       .addReg(MI->getOperand(1).getReg())
01648       // Add predicate operands.
01649       .addImm(ARMCC::AL)
01650       .addReg(0)
01651       // Add 's' bit operand (always reg0 for this)
01652       .addReg(0));
01653     return;
01654   }
01655   case ARM::SPACE:
01656     OutStreamer->EmitZeros(MI->getOperand(1).getImm());
01657     return;
01658   case ARM::TRAP: {
01659     // Non-Darwin binutils don't yet support the "trap" mnemonic.
01660     // FIXME: Remove this special case when they do.
01661     if (!Subtarget->isTargetMachO()) {
01662       //.long 0xe7ffdefe @ trap
01663       uint32_t Val = 0xe7ffdefeUL;
01664       OutStreamer->AddComment("trap");
01665       OutStreamer->EmitIntValue(Val, 4);
01666       return;
01667     }
01668     break;
01669   }
01670   case ARM::TRAPNaCl: {
01671     //.long 0xe7fedef0 @ trap
01672     uint32_t Val = 0xe7fedef0UL;
01673     OutStreamer->AddComment("trap");
01674     OutStreamer->EmitIntValue(Val, 4);
01675     return;
01676   }
01677   case ARM::tTRAP: {
01678     // Non-Darwin binutils don't yet support the "trap" mnemonic.
01679     // FIXME: Remove this special case when they do.
01680     if (!Subtarget->isTargetMachO()) {
01681       //.short 57086 @ trap
01682       uint16_t Val = 0xdefe;
01683       OutStreamer->AddComment("trap");
01684       OutStreamer->EmitIntValue(Val, 2);
01685       return;
01686     }
01687     break;
01688   }
01689   case ARM::t2Int_eh_sjlj_setjmp:
01690   case ARM::t2Int_eh_sjlj_setjmp_nofp:
01691   case ARM::tInt_eh_sjlj_setjmp: {
01692     // Two incoming args: GPR:$src, GPR:$val
01693     // mov $val, pc
01694     // adds $val, #7
01695     // str $val, [$src, #4]
01696     // movs r0, #0
01697     // b LSJLJEH
01698     // movs r0, #1
01699     // LSJLJEH:
01700     unsigned SrcReg = MI->getOperand(0).getReg();
01701     unsigned ValReg = MI->getOperand(1).getReg();
01702     MCSymbol *Label = OutContext.createTempSymbol("SJLJEH", false, true);
01703     OutStreamer->AddComment("eh_setjmp begin");
01704     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVr)
01705       .addReg(ValReg)
01706       .addReg(ARM::PC)
01707       // Predicate.
01708       .addImm(ARMCC::AL)
01709       .addReg(0));
01710 
01711     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDi3)
01712       .addReg(ValReg)
01713       // 's' bit operand
01714       .addReg(ARM::CPSR)
01715       .addReg(ValReg)
01716       .addImm(7)
01717       // Predicate.
01718       .addImm(ARMCC::AL)
01719       .addReg(0));
01720 
01721     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tSTRi)
01722       .addReg(ValReg)
01723       .addReg(SrcReg)
01724       // The offset immediate is #4. The operand value is scaled by 4 for the
01725       // tSTR instruction.
01726       .addImm(1)
01727       // Predicate.
01728       .addImm(ARMCC::AL)
01729       .addReg(0));
01730 
01731     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVi8)
01732       .addReg(ARM::R0)
01733       .addReg(ARM::CPSR)
01734       .addImm(0)
01735       // Predicate.
01736       .addImm(ARMCC::AL)
01737       .addReg(0));
01738 
01739     const MCExpr *SymbolExpr = MCSymbolRefExpr::create(Label, OutContext);
01740     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tB)
01741       .addExpr(SymbolExpr)
01742       .addImm(ARMCC::AL)
01743       .addReg(0));
01744 
01745     OutStreamer->AddComment("eh_setjmp end");
01746     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVi8)
01747       .addReg(ARM::R0)
01748       .addReg(ARM::CPSR)
01749       .addImm(1)
01750       // Predicate.
01751       .addImm(ARMCC::AL)
01752       .addReg(0));
01753 
01754     OutStreamer->EmitLabel(Label);
01755     return;
01756   }
01757 
01758   case ARM::Int_eh_sjlj_setjmp_nofp:
01759   case ARM::Int_eh_sjlj_setjmp: {
01760     // Two incoming args: GPR:$src, GPR:$val
01761     // add $val, pc, #8
01762     // str $val, [$src, #+4]
01763     // mov r0, #0
01764     // add pc, pc, #0
01765     // mov r0, #1
01766     unsigned SrcReg = MI->getOperand(0).getReg();
01767     unsigned ValReg = MI->getOperand(1).getReg();
01768 
01769     OutStreamer->AddComment("eh_setjmp begin");
01770     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDri)
01771       .addReg(ValReg)
01772       .addReg(ARM::PC)
01773       .addImm(8)
01774       // Predicate.
01775       .addImm(ARMCC::AL)
01776       .addReg(0)
01777       // 's' bit operand (always reg0 for this).
01778       .addReg(0));
01779 
01780     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::STRi12)
01781       .addReg(ValReg)
01782       .addReg(SrcReg)
01783       .addImm(4)
01784       // Predicate.
01785       .addImm(ARMCC::AL)
01786       .addReg(0));
01787 
01788     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVi)
01789       .addReg(ARM::R0)
01790       .addImm(0)
01791       // Predicate.
01792       .addImm(ARMCC::AL)
01793       .addReg(0)
01794       // 's' bit operand (always reg0 for this).
01795       .addReg(0));
01796 
01797     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDri)
01798       .addReg(ARM::PC)
01799       .addReg(ARM::PC)
01800       .addImm(0)
01801       // Predicate.
01802       .addImm(ARMCC::AL)
01803       .addReg(0)
01804       // 's' bit operand (always reg0 for this).
01805       .addReg(0));
01806 
01807     OutStreamer->AddComment("eh_setjmp end");
01808     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVi)
01809       .addReg(ARM::R0)
01810       .addImm(1)
01811       // Predicate.
01812       .addImm(ARMCC::AL)
01813       .addReg(0)
01814       // 's' bit operand (always reg0 for this).
01815       .addReg(0));
01816     return;
01817   }
01818   case ARM::Int_eh_sjlj_longjmp: {
01819     // ldr sp, [$src, #8]
01820     // ldr $scratch, [$src, #4]
01821     // ldr r7, [$src]
01822     // bx $scratch
01823     unsigned SrcReg = MI->getOperand(0).getReg();
01824     unsigned ScratchReg = MI->getOperand(1).getReg();
01825     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12)
01826       .addReg(ARM::SP)
01827       .addReg(SrcReg)
01828       .addImm(8)
01829       // Predicate.
01830       .addImm(ARMCC::AL)
01831       .addReg(0));
01832 
01833     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12)
01834       .addReg(ScratchReg)
01835       .addReg(SrcReg)
01836       .addImm(4)
01837       // Predicate.
01838       .addImm(ARMCC::AL)
01839       .addReg(0));
01840 
01841     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12)
01842       .addReg(ARM::R7)
01843       .addReg(SrcReg)
01844       .addImm(0)
01845       // Predicate.
01846       .addImm(ARMCC::AL)
01847       .addReg(0));
01848 
01849     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::BX)
01850       .addReg(ScratchReg)
01851       // Predicate.
01852       .addImm(ARMCC::AL)
01853       .addReg(0));
01854     return;
01855   }
01856   case ARM::tInt_eh_sjlj_longjmp: {
01857     // ldr $scratch, [$src, #8]
01858     // mov sp, $scratch
01859     // ldr $scratch, [$src, #4]
01860     // ldr r7, [$src]
01861     // bx $scratch
01862     unsigned SrcReg = MI->getOperand(0).getReg();
01863     unsigned ScratchReg = MI->getOperand(1).getReg();
01864     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi)
01865       .addReg(ScratchReg)
01866       .addReg(SrcReg)
01867       // The offset immediate is #8. The operand value is scaled by 4 for the
01868       // tLDR instruction.
01869       .addImm(2)
01870       // Predicate.
01871       .addImm(ARMCC::AL)
01872       .addReg(0));
01873 
01874     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVr)
01875       .addReg(ARM::SP)
01876       .addReg(ScratchReg)
01877       // Predicate.
01878       .addImm(ARMCC::AL)
01879       .addReg(0));
01880 
01881     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi)
01882       .addReg(ScratchReg)
01883       .addReg(SrcReg)
01884       .addImm(1)
01885       // Predicate.
01886       .addImm(ARMCC::AL)
01887       .addReg(0));
01888 
01889     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi)
01890       .addReg(ARM::R7)
01891       .addReg(SrcReg)
01892       .addImm(0)
01893       // Predicate.
01894       .addImm(ARMCC::AL)
01895       .addReg(0));
01896 
01897     EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tBX)
01898       .addReg(ScratchReg)
01899       // Predicate.
01900       .addImm(ARMCC::AL)
01901       .addReg(0));
01902     return;
01903   }
01904   }
01905 
01906   MCInst TmpInst;
01907   LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
01908 
01909   EmitToStreamer(*OutStreamer, TmpInst);
01910 }
01911 
01912 //===----------------------------------------------------------------------===//
01913 // Target Registry Stuff
01914 //===----------------------------------------------------------------------===//
01915 
01916 // Force static initialization.
01917 extern "C" void LLVMInitializeARMAsmPrinter() {
01918   RegisterAsmPrinter<ARMAsmPrinter> X(TheARMLETarget);
01919   RegisterAsmPrinter<ARMAsmPrinter> Y(TheARMBETarget);
01920   RegisterAsmPrinter<ARMAsmPrinter> A(TheThumbLETarget);
01921   RegisterAsmPrinter<ARMAsmPrinter> B(TheThumbBETarget);
01922 }