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ARMAsmPrinter.cpp
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00001 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file contains a printer that converts from our internal representation
00011 // of machine-dependent LLVM code to GAS-format ARM assembly language.
00012 //
00013 //===----------------------------------------------------------------------===//
00014 
00015 #include "ARMAsmPrinter.h"
00016 #include "ARM.h"
00017 #include "ARMConstantPoolValue.h"
00018 #include "ARMFPUName.h"
00019 #include "ARMArchExtName.h"
00020 #include "ARMMachineFunctionInfo.h"
00021 #include "ARMTargetMachine.h"
00022 #include "ARMTargetObjectFile.h"
00023 #include "InstPrinter/ARMInstPrinter.h"
00024 #include "MCTargetDesc/ARMAddressingModes.h"
00025 #include "MCTargetDesc/ARMMCExpr.h"
00026 #include "llvm/ADT/SetVector.h"
00027 #include "llvm/ADT/SmallString.h"
00028 #include "llvm/CodeGen/MachineFunctionPass.h"
00029 #include "llvm/CodeGen/MachineJumpTableInfo.h"
00030 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
00031 #include "llvm/IR/Constants.h"
00032 #include "llvm/IR/DataLayout.h"
00033 #include "llvm/IR/DebugInfo.h"
00034 #include "llvm/IR/Mangler.h"
00035 #include "llvm/IR/Module.h"
00036 #include "llvm/IR/Type.h"
00037 #include "llvm/MC/MCAsmInfo.h"
00038 #include "llvm/MC/MCAssembler.h"
00039 #include "llvm/MC/MCContext.h"
00040 #include "llvm/MC/MCELFStreamer.h"
00041 #include "llvm/MC/MCInst.h"
00042 #include "llvm/MC/MCInstBuilder.h"
00043 #include "llvm/MC/MCObjectStreamer.h"
00044 #include "llvm/MC/MCSectionMachO.h"
00045 #include "llvm/MC/MCStreamer.h"
00046 #include "llvm/MC/MCSymbol.h"
00047 #include "llvm/Support/ARMBuildAttributes.h"
00048 #include "llvm/Support/COFF.h"
00049 #include "llvm/Support/CommandLine.h"
00050 #include "llvm/Support/Debug.h"
00051 #include "llvm/Support/ELF.h"
00052 #include "llvm/Support/ErrorHandling.h"
00053 #include "llvm/Support/TargetRegistry.h"
00054 #include "llvm/Support/raw_ostream.h"
00055 #include "llvm/Target/TargetMachine.h"
00056 #include <cctype>
00057 using namespace llvm;
00058 
00059 #define DEBUG_TYPE "asm-printer"
00060 
00061 ARMAsmPrinter::ARMAsmPrinter(TargetMachine &TM,
00062                              std::unique_ptr<MCStreamer> Streamer)
00063     : AsmPrinter(TM, std::move(Streamer)), AFI(nullptr), MCP(nullptr),
00064       InConstantPool(false) {}
00065 
00066 void ARMAsmPrinter::EmitFunctionBodyEnd() {
00067   // Make sure to terminate any constant pools that were at the end
00068   // of the function.
00069   if (!InConstantPool)
00070     return;
00071   InConstantPool = false;
00072   OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
00073 }
00074 
00075 void ARMAsmPrinter::EmitFunctionEntryLabel() {
00076   if (AFI->isThumbFunction()) {
00077     OutStreamer.EmitAssemblerFlag(MCAF_Code16);
00078     OutStreamer.EmitThumbFunc(CurrentFnSym);
00079   }
00080 
00081   OutStreamer.EmitLabel(CurrentFnSym);
00082 }
00083 
00084 void ARMAsmPrinter::EmitXXStructor(const Constant *CV) {
00085   uint64_t Size = TM.getDataLayout()->getTypeAllocSize(CV->getType());
00086   assert(Size && "C++ constructor pointer had zero size!");
00087 
00088   const GlobalValue *GV = dyn_cast<GlobalValue>(CV->stripPointerCasts());
00089   assert(GV && "C++ constructor pointer was not a GlobalValue!");
00090 
00091   const MCExpr *E = MCSymbolRefExpr::Create(GetARMGVSymbol(GV,
00092                                                            ARMII::MO_NO_FLAG),
00093                                             (Subtarget->isTargetELF()
00094                                              ? MCSymbolRefExpr::VK_ARM_TARGET1
00095                                              : MCSymbolRefExpr::VK_None),
00096                                             OutContext);
00097 
00098   OutStreamer.EmitValue(E, Size);
00099 }
00100 
00101 /// runOnMachineFunction - This uses the EmitInstruction()
00102 /// method to print assembly for each instruction.
00103 ///
00104 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
00105   AFI = MF.getInfo<ARMFunctionInfo>();
00106   MCP = MF.getConstantPool();
00107   Subtarget = &MF.getSubtarget<ARMSubtarget>();
00108 
00109   SetupMachineFunction(MF);
00110 
00111   if (Subtarget->isTargetCOFF()) {
00112     bool Internal = MF.getFunction()->hasInternalLinkage();
00113     COFF::SymbolStorageClass Scl = Internal ? COFF::IMAGE_SYM_CLASS_STATIC
00114                                             : COFF::IMAGE_SYM_CLASS_EXTERNAL;
00115     int Type = COFF::IMAGE_SYM_DTYPE_FUNCTION << COFF::SCT_COMPLEX_TYPE_SHIFT;
00116 
00117     OutStreamer.BeginCOFFSymbolDef(CurrentFnSym);
00118     OutStreamer.EmitCOFFSymbolStorageClass(Scl);
00119     OutStreamer.EmitCOFFSymbolType(Type);
00120     OutStreamer.EndCOFFSymbolDef();
00121   }
00122 
00123   // Emit the rest of the function body.
00124   EmitFunctionBody();
00125 
00126   // If we need V4T thumb mode Register Indirect Jump pads, emit them.
00127   // These are created per function, rather than per TU, since it's
00128   // relatively easy to exceed the thumb branch range within a TU.
00129   if (! ThumbIndirectPads.empty()) {
00130     OutStreamer.EmitAssemblerFlag(MCAF_Code16);
00131     EmitAlignment(1);
00132     for (unsigned i = 0, e = ThumbIndirectPads.size(); i < e; i++) {
00133       OutStreamer.EmitLabel(ThumbIndirectPads[i].second);
00134       EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tBX)
00135         .addReg(ThumbIndirectPads[i].first)
00136         // Add predicate operands.
00137         .addImm(ARMCC::AL)
00138         .addReg(0));
00139     }
00140     ThumbIndirectPads.clear();
00141   }
00142 
00143   // We didn't modify anything.
00144   return false;
00145 }
00146 
00147 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
00148                                  raw_ostream &O, const char *Modifier) {
00149   const MachineOperand &MO = MI->getOperand(OpNum);
00150   unsigned TF = MO.getTargetFlags();
00151 
00152   switch (MO.getType()) {
00153   default: llvm_unreachable("<unknown operand type>");
00154   case MachineOperand::MO_Register: {
00155     unsigned Reg = MO.getReg();
00156     assert(TargetRegisterInfo::isPhysicalRegister(Reg));
00157     assert(!MO.getSubReg() && "Subregs should be eliminated!");
00158     if(ARM::GPRPairRegClass.contains(Reg)) {
00159       const MachineFunction &MF = *MI->getParent()->getParent();
00160       const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
00161       Reg = TRI->getSubReg(Reg, ARM::gsub_0);
00162     }
00163     O << ARMInstPrinter::getRegisterName(Reg);
00164     break;
00165   }
00166   case MachineOperand::MO_Immediate: {
00167     int64_t Imm = MO.getImm();
00168     O << '#';
00169     if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
00170         (TF == ARMII::MO_LO16))
00171       O << ":lower16:";
00172     else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
00173              (TF == ARMII::MO_HI16))
00174       O << ":upper16:";
00175     O << Imm;
00176     break;
00177   }
00178   case MachineOperand::MO_MachineBasicBlock:
00179     O << *MO.getMBB()->getSymbol();
00180     return;
00181   case MachineOperand::MO_GlobalAddress: {
00182     const GlobalValue *GV = MO.getGlobal();
00183     if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
00184         (TF & ARMII::MO_LO16))
00185       O << ":lower16:";
00186     else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
00187              (TF & ARMII::MO_HI16))
00188       O << ":upper16:";
00189     O << *GetARMGVSymbol(GV, TF);
00190 
00191     printOffset(MO.getOffset(), O);
00192     if (TF == ARMII::MO_PLT)
00193       O << "(PLT)";
00194     break;
00195   }
00196   case MachineOperand::MO_ConstantPoolIndex:
00197     O << *GetCPISymbol(MO.getIndex());
00198     break;
00199   }
00200 }
00201 
00202 //===--------------------------------------------------------------------===//
00203 
00204 MCSymbol *ARMAsmPrinter::
00205 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
00206   const DataLayout *DL = TM.getDataLayout();
00207   SmallString<60> Name;
00208   raw_svector_ostream(Name) << DL->getPrivateGlobalPrefix() << "JTI"
00209     << getFunctionNumber() << '_' << uid << '_' << uid2;
00210   return OutContext.GetOrCreateSymbol(Name.str());
00211 }
00212 
00213 
00214 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel() const {
00215   const DataLayout *DL = TM.getDataLayout();
00216   SmallString<60> Name;
00217   raw_svector_ostream(Name) << DL->getPrivateGlobalPrefix() << "SJLJEH"
00218     << getFunctionNumber();
00219   return OutContext.GetOrCreateSymbol(Name.str());
00220 }
00221 
00222 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
00223                                     unsigned AsmVariant, const char *ExtraCode,
00224                                     raw_ostream &O) {
00225   // Does this asm operand have a single letter operand modifier?
00226   if (ExtraCode && ExtraCode[0]) {
00227     if (ExtraCode[1] != 0) return true; // Unknown modifier.
00228 
00229     switch (ExtraCode[0]) {
00230     default:
00231       // See if this is a generic print operand
00232       return AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O);
00233     case 'a': // Print as a memory address.
00234       if (MI->getOperand(OpNum).isReg()) {
00235         O << "["
00236           << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
00237           << "]";
00238         return false;
00239       }
00240       // Fallthrough
00241     case 'c': // Don't print "#" before an immediate operand.
00242       if (!MI->getOperand(OpNum).isImm())
00243         return true;
00244       O << MI->getOperand(OpNum).getImm();
00245       return false;
00246     case 'P': // Print a VFP double precision register.
00247     case 'q': // Print a NEON quad precision register.
00248       printOperand(MI, OpNum, O);
00249       return false;
00250     case 'y': // Print a VFP single precision register as indexed double.
00251       if (MI->getOperand(OpNum).isReg()) {
00252         unsigned Reg = MI->getOperand(OpNum).getReg();
00253         const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
00254         // Find the 'd' register that has this 's' register as a sub-register,
00255         // and determine the lane number.
00256         for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
00257           if (!ARM::DPRRegClass.contains(*SR))
00258             continue;
00259           bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
00260           O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");
00261           return false;
00262         }
00263       }
00264       return true;
00265     case 'B': // Bitwise inverse of integer or symbol without a preceding #.
00266       if (!MI->getOperand(OpNum).isImm())
00267         return true;
00268       O << ~(MI->getOperand(OpNum).getImm());
00269       return false;
00270     case 'L': // The low 16 bits of an immediate constant.
00271       if (!MI->getOperand(OpNum).isImm())
00272         return true;
00273       O << (MI->getOperand(OpNum).getImm() & 0xffff);
00274       return false;
00275     case 'M': { // A register range suitable for LDM/STM.
00276       if (!MI->getOperand(OpNum).isReg())
00277         return true;
00278       const MachineOperand &MO = MI->getOperand(OpNum);
00279       unsigned RegBegin = MO.getReg();
00280       // This takes advantage of the 2 operand-ness of ldm/stm and that we've
00281       // already got the operands in registers that are operands to the
00282       // inline asm statement.
00283       O << "{";
00284       if (ARM::GPRPairRegClass.contains(RegBegin)) {
00285         const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
00286         unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
00287         O << ARMInstPrinter::getRegisterName(Reg0) << ", ";
00288         RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1);
00289       }
00290       O << ARMInstPrinter::getRegisterName(RegBegin);
00291 
00292       // FIXME: The register allocator not only may not have given us the
00293       // registers in sequence, but may not be in ascending registers. This
00294       // will require changes in the register allocator that'll need to be
00295       // propagated down here if the operands change.
00296       unsigned RegOps = OpNum + 1;
00297       while (MI->getOperand(RegOps).isReg()) {
00298         O << ", "
00299           << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
00300         RegOps++;
00301       }
00302 
00303       O << "}";
00304 
00305       return false;
00306     }
00307     case 'R': // The most significant register of a pair.
00308     case 'Q': { // The least significant register of a pair.
00309       if (OpNum == 0)
00310         return true;
00311       const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
00312       if (!FlagsOP.isImm())
00313         return true;
00314       unsigned Flags = FlagsOP.getImm();
00315 
00316       // This operand may not be the one that actually provides the register. If
00317       // it's tied to a previous one then we should refer instead to that one
00318       // for registers and their classes.
00319       unsigned TiedIdx;
00320       if (InlineAsm::isUseOperandTiedToDef(Flags, TiedIdx)) {
00321         for (OpNum = InlineAsm::MIOp_FirstOperand; TiedIdx; --TiedIdx) {
00322           unsigned OpFlags = MI->getOperand(OpNum).getImm();
00323           OpNum += InlineAsm::getNumOperandRegisters(OpFlags) + 1;
00324         }
00325         Flags = MI->getOperand(OpNum).getImm();
00326 
00327         // Later code expects OpNum to be pointing at the register rather than
00328         // the flags.
00329         OpNum += 1;
00330       }
00331 
00332       unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
00333       unsigned RC;
00334       InlineAsm::hasRegClassConstraint(Flags, RC);
00335       if (RC == ARM::GPRPairRegClassID) {
00336         if (NumVals != 1)
00337           return true;
00338         const MachineOperand &MO = MI->getOperand(OpNum);
00339         if (!MO.isReg())
00340           return true;
00341         const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
00342         unsigned Reg = TRI->getSubReg(MO.getReg(), ExtraCode[0] == 'Q' ?
00343             ARM::gsub_0 : ARM::gsub_1);
00344         O << ARMInstPrinter::getRegisterName(Reg);
00345         return false;
00346       }
00347       if (NumVals != 2)
00348         return true;
00349       unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
00350       if (RegOp >= MI->getNumOperands())
00351         return true;
00352       const MachineOperand &MO = MI->getOperand(RegOp);
00353       if (!MO.isReg())
00354         return true;
00355       unsigned Reg = MO.getReg();
00356       O << ARMInstPrinter::getRegisterName(Reg);
00357       return false;
00358     }
00359 
00360     case 'e': // The low doubleword register of a NEON quad register.
00361     case 'f': { // The high doubleword register of a NEON quad register.
00362       if (!MI->getOperand(OpNum).isReg())
00363         return true;
00364       unsigned Reg = MI->getOperand(OpNum).getReg();
00365       if (!ARM::QPRRegClass.contains(Reg))
00366         return true;
00367       const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
00368       unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
00369                                        ARM::dsub_0 : ARM::dsub_1);
00370       O << ARMInstPrinter::getRegisterName(SubReg);
00371       return false;
00372     }
00373 
00374     // This modifier is not yet supported.
00375     case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
00376       return true;
00377     case 'H': { // The highest-numbered register of a pair.
00378       const MachineOperand &MO = MI->getOperand(OpNum);
00379       if (!MO.isReg())
00380         return true;
00381       const MachineFunction &MF = *MI->getParent()->getParent();
00382       const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
00383       unsigned Reg = MO.getReg();
00384       if(!ARM::GPRPairRegClass.contains(Reg))
00385         return false;
00386       Reg = TRI->getSubReg(Reg, ARM::gsub_1);
00387       O << ARMInstPrinter::getRegisterName(Reg);
00388       return false;
00389     }
00390     }
00391   }
00392 
00393   printOperand(MI, OpNum, O);
00394   return false;
00395 }
00396 
00397 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
00398                                           unsigned OpNum, unsigned AsmVariant,
00399                                           const char *ExtraCode,
00400                                           raw_ostream &O) {
00401   // Does this asm operand have a single letter operand modifier?
00402   if (ExtraCode && ExtraCode[0]) {
00403     if (ExtraCode[1] != 0) return true; // Unknown modifier.
00404 
00405     switch (ExtraCode[0]) {
00406       case 'A': // A memory operand for a VLD1/VST1 instruction.
00407       default: return true;  // Unknown modifier.
00408       case 'm': // The base register of a memory operand.
00409         if (!MI->getOperand(OpNum).isReg())
00410           return true;
00411         O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
00412         return false;
00413     }
00414   }
00415 
00416   const MachineOperand &MO = MI->getOperand(OpNum);
00417   assert(MO.isReg() && "unexpected inline asm memory operand");
00418   O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
00419   return false;
00420 }
00421 
00422 static bool isThumb(const MCSubtargetInfo& STI) {
00423   return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
00424 }
00425 
00426 void ARMAsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo &StartInfo,
00427                                      const MCSubtargetInfo *EndInfo) const {
00428   // If either end mode is unknown (EndInfo == NULL) or different than
00429   // the start mode, then restore the start mode.
00430   const bool WasThumb = isThumb(StartInfo);
00431   if (!EndInfo || WasThumb != isThumb(*EndInfo)) {
00432     OutStreamer.EmitAssemblerFlag(WasThumb ? MCAF_Code16 : MCAF_Code32);
00433   }
00434 }
00435 
00436 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
00437   Triple TT(TM.getTargetTriple());
00438   // Use unified assembler syntax.
00439   OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
00440 
00441   // Emit ARM Build Attributes
00442   if (TT.isOSBinFormatELF())
00443     emitAttributes();
00444 
00445   // Use the triple's architecture and subarchitecture to determine
00446   // if we're thumb for the purposes of the top level code16 assembler
00447   // flag.
00448   bool isThumb = TT.getArch() == Triple::thumb ||
00449                  TT.getArch() == Triple::thumbeb ||
00450                  TT.getSubArch() == Triple::ARMSubArch_v7m ||
00451                  TT.getSubArch() == Triple::ARMSubArch_v6m;
00452   if (!M.getModuleInlineAsm().empty() && isThumb)
00453     OutStreamer.EmitAssemblerFlag(MCAF_Code16);
00454 }
00455 
00456 static void
00457 emitNonLazySymbolPointer(MCStreamer &OutStreamer, MCSymbol *StubLabel,
00458                          MachineModuleInfoImpl::StubValueTy &MCSym) {
00459   // L_foo$stub:
00460   OutStreamer.EmitLabel(StubLabel);
00461   //   .indirect_symbol _foo
00462   OutStreamer.EmitSymbolAttribute(MCSym.getPointer(), MCSA_IndirectSymbol);
00463 
00464   if (MCSym.getInt())
00465     // External to current translation unit.
00466     OutStreamer.EmitIntValue(0, 4/*size*/);
00467   else
00468     // Internal to current translation unit.
00469     //
00470     // When we place the LSDA into the TEXT section, the type info
00471     // pointers need to be indirect and pc-rel. We accomplish this by
00472     // using NLPs; however, sometimes the types are local to the file.
00473     // We need to fill in the value for the NLP in those cases.
00474     OutStreamer.EmitValue(
00475         MCSymbolRefExpr::Create(MCSym.getPointer(), OutStreamer.getContext()),
00476         4 /*size*/);
00477 }
00478 
00479 
00480 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
00481   Triple TT(TM.getTargetTriple());
00482   if (TT.isOSBinFormatMachO()) {
00483     // All darwin targets use mach-o.
00484     const TargetLoweringObjectFileMachO &TLOFMacho =
00485       static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
00486     MachineModuleInfoMachO &MMIMacho =
00487       MMI->getObjFileInfo<MachineModuleInfoMachO>();
00488 
00489     // Output non-lazy-pointers for external and common global variables.
00490     MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
00491 
00492     if (!Stubs.empty()) {
00493       // Switch with ".non_lazy_symbol_pointer" directive.
00494       OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
00495       EmitAlignment(2);
00496 
00497       for (auto &Stub : Stubs)
00498         emitNonLazySymbolPointer(OutStreamer, Stub.first, Stub.second);
00499 
00500       Stubs.clear();
00501       OutStreamer.AddBlankLine();
00502     }
00503 
00504     Stubs = MMIMacho.GetHiddenGVStubList();
00505     if (!Stubs.empty()) {
00506       OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
00507       EmitAlignment(2);
00508 
00509       for (auto &Stub : Stubs)
00510         emitNonLazySymbolPointer(OutStreamer, Stub.first, Stub.second);
00511 
00512       Stubs.clear();
00513       OutStreamer.AddBlankLine();
00514     }
00515 
00516     // Funny Darwin hack: This flag tells the linker that no global symbols
00517     // contain code that falls through to other global symbols (e.g. the obvious
00518     // implementation of multiple entry points).  If this doesn't occur, the
00519     // linker can safely perform dead code stripping.  Since LLVM never
00520     // generates code that does this, it is always safe to set.
00521     OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
00522   }
00523 
00524   // Emit a .data.rel section containing any stubs that were created.
00525   if (TT.isOSBinFormatELF()) {
00526     const TargetLoweringObjectFileELF &TLOFELF =
00527       static_cast<const TargetLoweringObjectFileELF &>(getObjFileLowering());
00528 
00529     MachineModuleInfoELF &MMIELF = MMI->getObjFileInfo<MachineModuleInfoELF>();
00530 
00531     // Output stubs for external and common global variables.
00532     MachineModuleInfoELF::SymbolListTy Stubs = MMIELF.GetGVStubList();
00533     if (!Stubs.empty()) {
00534       OutStreamer.SwitchSection(TLOFELF.getDataRelSection());
00535       const DataLayout *TD = TM.getDataLayout();
00536 
00537       for (auto &stub: Stubs) {
00538         OutStreamer.EmitLabel(stub.first);
00539         OutStreamer.EmitSymbolValue(stub.second.getPointer(),
00540                                     TD->getPointerSize(0));
00541       }
00542       Stubs.clear();
00543     }
00544   }
00545 }
00546 
00547 //===----------------------------------------------------------------------===//
00548 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
00549 // FIXME:
00550 // The following seem like one-off assembler flags, but they actually need
00551 // to appear in the .ARM.attributes section in ELF.
00552 // Instead of subclassing the MCELFStreamer, we do the work here.
00553 
00554 static ARMBuildAttrs::CPUArch getArchForCPU(StringRef CPU,
00555                                             const ARMSubtarget *Subtarget) {
00556   if (CPU == "xscale")
00557     return ARMBuildAttrs::v5TEJ;
00558 
00559   if (Subtarget->hasV8Ops())
00560     return ARMBuildAttrs::v8;
00561   else if (Subtarget->hasV7Ops()) {
00562     if (Subtarget->isMClass() && Subtarget->hasThumb2DSP())
00563       return ARMBuildAttrs::v7E_M;
00564     return ARMBuildAttrs::v7;
00565   } else if (Subtarget->hasV6T2Ops())
00566     return ARMBuildAttrs::v6T2;
00567   else if (Subtarget->hasV6MOps())
00568     return ARMBuildAttrs::v6S_M;
00569   else if (Subtarget->hasV6Ops())
00570     return ARMBuildAttrs::v6;
00571   else if (Subtarget->hasV5TEOps())
00572     return ARMBuildAttrs::v5TE;
00573   else if (Subtarget->hasV5TOps())
00574     return ARMBuildAttrs::v5T;
00575   else if (Subtarget->hasV4TOps())
00576     return ARMBuildAttrs::v4T;
00577   else
00578     return ARMBuildAttrs::v4;
00579 }
00580 
00581 void ARMAsmPrinter::emitAttributes() {
00582   MCTargetStreamer &TS = *OutStreamer.getTargetStreamer();
00583   ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
00584 
00585   ATS.emitTextAttribute(ARMBuildAttrs::conformance, "2.09");
00586 
00587   ATS.switchVendor("aeabi");
00588 
00589   // Compute ARM ELF Attributes based on the default subtarget that
00590   // we'd have constructed. The existing ARM behavior isn't LTO clean
00591   // anyhow.
00592   // FIXME: For ifunc related functions we could iterate over and look
00593   // for a feature string that doesn't match the default one.
00594   StringRef TT = TM.getTargetTriple();
00595   StringRef CPU = TM.getTargetCPU();
00596   StringRef FS = TM.getTargetFeatureString();
00597   std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
00598   if (!FS.empty()) {
00599     if (!ArchFS.empty())
00600       ArchFS = ArchFS + "," + FS.str();
00601     else
00602       ArchFS = FS;
00603   }
00604   const ARMBaseTargetMachine &ATM =
00605       static_cast<const ARMBaseTargetMachine &>(TM);
00606   const ARMSubtarget STI(TT, CPU, ArchFS, ATM, ATM.isLittleEndian());
00607 
00608   std::string CPUString = STI.getCPUString();
00609 
00610   if (CPUString.find("generic") != 0) { //CPUString doesn't start with "generic"
00611     // FIXME: remove krait check when GNU tools support krait cpu
00612     if (STI.isKrait()) {
00613       ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a9");
00614       // We consider krait as a "cortex-a9" + hwdiv CPU
00615       // Enable hwdiv through ".arch_extension idiv"
00616       if (STI.hasDivide() || STI.hasDivideInARMMode())
00617         ATS.emitArchExtension(ARM::HWDIV);
00618     } else
00619       ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, CPUString);
00620   }
00621 
00622   ATS.emitAttribute(ARMBuildAttrs::CPU_arch, getArchForCPU(CPUString, &STI));
00623 
00624   // Tag_CPU_arch_profile must have the default value of 0 when "Architecture
00625   // profile is not applicable (e.g. pre v7, or cross-profile code)".
00626   if (STI.hasV7Ops()) {
00627     if (STI.isAClass()) {
00628       ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
00629                         ARMBuildAttrs::ApplicationProfile);
00630     } else if (STI.isRClass()) {
00631       ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
00632                         ARMBuildAttrs::RealTimeProfile);
00633     } else if (STI.isMClass()) {
00634       ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
00635                         ARMBuildAttrs::MicroControllerProfile);
00636     }
00637   }
00638 
00639   ATS.emitAttribute(ARMBuildAttrs::ARM_ISA_use,
00640                     STI.hasARMOps() ? ARMBuildAttrs::Allowed
00641                                     : ARMBuildAttrs::Not_Allowed);
00642   if (STI.isThumb1Only()) {
00643     ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use, ARMBuildAttrs::Allowed);
00644   } else if (STI.hasThumb2()) {
00645     ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
00646                       ARMBuildAttrs::AllowThumb32);
00647   }
00648 
00649   if (STI.hasNEON()) {
00650     /* NEON is not exactly a VFP architecture, but GAS emit one of
00651      * neon/neon-fp-armv8/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
00652     if (STI.hasFPARMv8()) {
00653       if (STI.hasCrypto())
00654         ATS.emitFPU(ARM::CRYPTO_NEON_FP_ARMV8);
00655       else
00656         ATS.emitFPU(ARM::NEON_FP_ARMV8);
00657     } else if (STI.hasVFP4())
00658       ATS.emitFPU(ARM::NEON_VFPV4);
00659     else
00660       ATS.emitFPU(ARM::NEON);
00661     // Emit Tag_Advanced_SIMD_arch for ARMv8 architecture
00662     if (STI.hasV8Ops())
00663       ATS.emitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
00664                         STI.hasV8_1a() ? ARMBuildAttrs::AllowNeonARMv8_1a:
00665                                          ARMBuildAttrs::AllowNeonARMv8);
00666   } else {
00667     if (STI.hasFPARMv8())
00668       // FPv5 and FP-ARMv8 have the same instructions, so are modeled as one
00669       // FPU, but there are two different names for it depending on the CPU.
00670       ATS.emitFPU(STI.hasD16() ? ARM::FPV5_D16 : ARM::FP_ARMV8);
00671     else if (STI.hasVFP4())
00672       ATS.emitFPU(STI.hasD16() ? ARM::VFPV4_D16 : ARM::VFPV4);
00673     else if (STI.hasVFP3())
00674       ATS.emitFPU(STI.hasD16() ? ARM::VFPV3_D16 : ARM::VFPV3);
00675     else if (STI.hasVFP2())
00676       ATS.emitFPU(ARM::VFPV2);
00677   }
00678 
00679   if (TM.getRelocationModel() == Reloc::PIC_) {
00680     // PIC specific attributes.
00681     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RW_data,
00682                       ARMBuildAttrs::AddressRWPCRel);
00683     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RO_data,
00684                       ARMBuildAttrs::AddressROPCRel);
00685     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_GOT_use,
00686                       ARMBuildAttrs::AddressGOT);
00687   } else {
00688     // Allow direct addressing of imported data for all other relocation models.
00689     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_GOT_use,
00690                       ARMBuildAttrs::AddressDirect);
00691   }
00692 
00693   // Signal various FP modes.
00694   if (!TM.Options.UnsafeFPMath) {
00695     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
00696                       ARMBuildAttrs::IEEEDenormals);
00697     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_exceptions, ARMBuildAttrs::Allowed);
00698 
00699     // If the user has permitted this code to choose the IEEE 754
00700     // rounding at run-time, emit the rounding attribute.
00701     if (TM.Options.HonorSignDependentRoundingFPMathOption)
00702       ATS.emitAttribute(ARMBuildAttrs::ABI_FP_rounding, ARMBuildAttrs::Allowed);
00703   } else {
00704     if (!STI.hasVFP2()) {
00705       // When the target doesn't have an FPU (by design or
00706       // intention), the assumptions made on the software support
00707       // mirror that of the equivalent hardware support *if it
00708       // existed*. For v7 and better we indicate that denormals are
00709       // flushed preserving sign, and for V6 we indicate that
00710       // denormals are flushed to positive zero.
00711       if (STI.hasV7Ops())
00712         ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
00713                           ARMBuildAttrs::PreserveFPSign);
00714     } else if (STI.hasVFP3()) {
00715       // In VFPv4, VFPv4U, VFPv3, or VFPv3U, it is preserved. That is,
00716       // the sign bit of the zero matches the sign bit of the input or
00717       // result that is being flushed to zero.
00718       ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
00719                         ARMBuildAttrs::PreserveFPSign);
00720     }
00721     // For VFPv2 implementations it is implementation defined as
00722     // to whether denormals are flushed to positive zero or to
00723     // whatever the sign of zero is (ARM v7AR ARM 2.7.5). Historically
00724     // LLVM has chosen to flush this to positive zero (most likely for
00725     // GCC compatibility), so that's the chosen value here (the
00726     // absence of its emission implies zero).
00727   }
00728 
00729   // TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath is the
00730   // equivalent of GCC's -ffinite-math-only flag.
00731   if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
00732     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
00733                       ARMBuildAttrs::Allowed);
00734   else
00735     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
00736                       ARMBuildAttrs::AllowIEE754);
00737 
00738   if (STI.allowsUnalignedMem())
00739     ATS.emitAttribute(ARMBuildAttrs::CPU_unaligned_access,
00740                       ARMBuildAttrs::Allowed);
00741   else
00742     ATS.emitAttribute(ARMBuildAttrs::CPU_unaligned_access,
00743                       ARMBuildAttrs::Not_Allowed);
00744 
00745   // FIXME: add more flags to ARMBuildAttributes.h
00746   // 8-bytes alignment stuff.
00747   ATS.emitAttribute(ARMBuildAttrs::ABI_align_needed, 1);
00748   ATS.emitAttribute(ARMBuildAttrs::ABI_align_preserved, 1);
00749 
00750   // ABI_HardFP_use attribute to indicate single precision FP.
00751   if (STI.isFPOnlySP())
00752     ATS.emitAttribute(ARMBuildAttrs::ABI_HardFP_use,
00753                       ARMBuildAttrs::HardFPSinglePrecision);
00754 
00755   // Hard float.  Use both S and D registers and conform to AAPCS-VFP.
00756   if (STI.isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard)
00757     ATS.emitAttribute(ARMBuildAttrs::ABI_VFP_args, ARMBuildAttrs::HardFPAAPCS);
00758 
00759   // FIXME: Should we signal R9 usage?
00760 
00761   if (STI.hasFP16())
00762     ATS.emitAttribute(ARMBuildAttrs::FP_HP_extension, ARMBuildAttrs::AllowHPFP);
00763 
00764   // FIXME: To support emitting this build attribute as GCC does, the
00765   // -mfp16-format option and associated plumbing must be
00766   // supported. For now the __fp16 type is exposed by default, so this
00767   // attribute should be emitted with value 1.
00768   ATS.emitAttribute(ARMBuildAttrs::ABI_FP_16bit_format,
00769                     ARMBuildAttrs::FP16FormatIEEE);
00770 
00771   if (STI.hasMPExtension())
00772     ATS.emitAttribute(ARMBuildAttrs::MPextension_use, ARMBuildAttrs::AllowMP);
00773 
00774   // Hardware divide in ARM mode is part of base arch, starting from ARMv8.
00775   // If only Thumb hwdiv is present, it must also be in base arch (ARMv7-R/M).
00776   // It is not possible to produce DisallowDIV: if hwdiv is present in the base
00777   // arch, supplying -hwdiv downgrades the effective arch, via ClearImpliedBits.
00778   // AllowDIVExt is only emitted if hwdiv isn't available in the base arch;
00779   // otherwise, the default value (AllowDIVIfExists) applies.
00780   if (STI.hasDivideInARMMode() && !STI.hasV8Ops())
00781     ATS.emitAttribute(ARMBuildAttrs::DIV_use, ARMBuildAttrs::AllowDIVExt);
00782 
00783   if (MMI) {
00784     if (const Module *SourceModule = MMI->getModule()) {
00785       // ABI_PCS_wchar_t to indicate wchar_t width
00786       // FIXME: There is no way to emit value 0 (wchar_t prohibited).
00787       if (auto WCharWidthValue = mdconst::extract_or_null<ConstantInt>(
00788               SourceModule->getModuleFlag("wchar_size"))) {
00789         int WCharWidth = WCharWidthValue->getZExtValue();
00790         assert((WCharWidth == 2 || WCharWidth == 4) &&
00791                "wchar_t width must be 2 or 4 bytes");
00792         ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_wchar_t, WCharWidth);
00793       }
00794 
00795       // ABI_enum_size to indicate enum width
00796       // FIXME: There is no way to emit value 0 (enums prohibited) or value 3
00797       //        (all enums contain a value needing 32 bits to encode).
00798       if (auto EnumWidthValue = mdconst::extract_or_null<ConstantInt>(
00799               SourceModule->getModuleFlag("min_enum_size"))) {
00800         int EnumWidth = EnumWidthValue->getZExtValue();
00801         assert((EnumWidth == 1 || EnumWidth == 4) &&
00802                "Minimum enum width must be 1 or 4 bytes");
00803         int EnumBuildAttr = EnumWidth == 1 ? 1 : 2;
00804         ATS.emitAttribute(ARMBuildAttrs::ABI_enum_size, EnumBuildAttr);
00805       }
00806     }
00807   }
00808 
00809   // TODO: We currently only support either reserving the register, or treating
00810   // it as another callee-saved register, but not as SB or a TLS pointer; It
00811   // would instead be nicer to push this from the frontend as metadata, as we do
00812   // for the wchar and enum size tags
00813   if (STI.isR9Reserved())
00814     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use, ARMBuildAttrs::R9Reserved);
00815   else
00816     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use, ARMBuildAttrs::R9IsGPR);
00817 
00818   if (STI.hasTrustZone() && STI.hasVirtualization())
00819     ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
00820                       ARMBuildAttrs::AllowTZVirtualization);
00821   else if (STI.hasTrustZone())
00822     ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
00823                       ARMBuildAttrs::AllowTZ);
00824   else if (STI.hasVirtualization())
00825     ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
00826                       ARMBuildAttrs::AllowVirtualization);
00827 
00828   ATS.finishAttributeSection();
00829 }
00830 
00831 //===----------------------------------------------------------------------===//
00832 
00833 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
00834                              unsigned LabelId, MCContext &Ctx) {
00835 
00836   MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
00837                        + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
00838   return Label;
00839 }
00840 
00841 static MCSymbolRefExpr::VariantKind
00842 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
00843   switch (Modifier) {
00844   case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
00845   case ARMCP::TLSGD:       return MCSymbolRefExpr::VK_TLSGD;
00846   case ARMCP::TPOFF:       return MCSymbolRefExpr::VK_TPOFF;
00847   case ARMCP::GOTTPOFF:    return MCSymbolRefExpr::VK_GOTTPOFF;
00848   case ARMCP::GOT:         return MCSymbolRefExpr::VK_GOT;
00849   case ARMCP::GOTOFF:      return MCSymbolRefExpr::VK_GOTOFF;
00850   }
00851   llvm_unreachable("Invalid ARMCPModifier!");
00852 }
00853 
00854 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV,
00855                                         unsigned char TargetFlags) {
00856   if (Subtarget->isTargetMachO()) {
00857     bool IsIndirect = (TargetFlags & ARMII::MO_NONLAZY) &&
00858       Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
00859 
00860     if (!IsIndirect)
00861       return getSymbol(GV);
00862 
00863     // FIXME: Remove this when Darwin transition to @GOT like syntax.
00864     MCSymbol *MCSym = getSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
00865     MachineModuleInfoMachO &MMIMachO =
00866       MMI->getObjFileInfo<MachineModuleInfoMachO>();
00867     MachineModuleInfoImpl::StubValueTy &StubSym =
00868       GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym)
00869                                 : MMIMachO.getGVStubEntry(MCSym);
00870     if (!StubSym.getPointer())
00871       StubSym = MachineModuleInfoImpl::StubValueTy(getSymbol(GV),
00872                                                    !GV->hasInternalLinkage());
00873     return MCSym;
00874   } else if (Subtarget->isTargetCOFF()) {
00875     assert(Subtarget->isTargetWindows() &&
00876            "Windows is the only supported COFF target");
00877 
00878     bool IsIndirect = (TargetFlags & ARMII::MO_DLLIMPORT);
00879     if (!IsIndirect)
00880       return getSymbol(GV);
00881 
00882     SmallString<128> Name;
00883     Name = "__imp_";
00884     getNameWithPrefix(Name, GV);
00885 
00886     return OutContext.GetOrCreateSymbol(Name);
00887   } else if (Subtarget->isTargetELF()) {
00888     return getSymbol(GV);
00889   }
00890   llvm_unreachable("unexpected target");
00891 }
00892 
00893 void ARMAsmPrinter::
00894 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
00895   const DataLayout *DL = TM.getDataLayout();
00896   int Size = TM.getDataLayout()->getTypeAllocSize(MCPV->getType());
00897 
00898   ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
00899 
00900   MCSymbol *MCSym;
00901   if (ACPV->isLSDA()) {
00902     MCSym = getCurExceptionSym();
00903   } else if (ACPV->isBlockAddress()) {
00904     const BlockAddress *BA =
00905       cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
00906     MCSym = GetBlockAddressSymbol(BA);
00907   } else if (ACPV->isGlobalValue()) {
00908     const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
00909 
00910     // On Darwin, const-pool entries may get the "FOO$non_lazy_ptr" mangling, so
00911     // flag the global as MO_NONLAZY.
00912     unsigned char TF = Subtarget->isTargetMachO() ? ARMII::MO_NONLAZY : 0;
00913     MCSym = GetARMGVSymbol(GV, TF);
00914   } else if (ACPV->isMachineBasicBlock()) {
00915     const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
00916     MCSym = MBB->getSymbol();
00917   } else {
00918     assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
00919     const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
00920     MCSym = GetExternalSymbolSymbol(Sym);
00921   }
00922 
00923   // Create an MCSymbol for the reference.
00924   const MCExpr *Expr =
00925     MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
00926                             OutContext);
00927 
00928   if (ACPV->getPCAdjustment()) {
00929     MCSymbol *PCLabel = getPICLabel(DL->getPrivateGlobalPrefix(),
00930                                     getFunctionNumber(),
00931                                     ACPV->getLabelId(),
00932                                     OutContext);
00933     const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
00934     PCRelExpr =
00935       MCBinaryExpr::CreateAdd(PCRelExpr,
00936                               MCConstantExpr::Create(ACPV->getPCAdjustment(),
00937                                                      OutContext),
00938                               OutContext);
00939     if (ACPV->mustAddCurrentAddress()) {
00940       // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
00941       // label, so just emit a local label end reference that instead.
00942       MCSymbol *DotSym = OutContext.CreateTempSymbol();
00943       OutStreamer.EmitLabel(DotSym);
00944       const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
00945       PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
00946     }
00947     Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
00948   }
00949   OutStreamer.EmitValue(Expr, Size);
00950 }
00951 
00952 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
00953   unsigned Opcode = MI->getOpcode();
00954   int OpNum = 1;
00955   if (Opcode == ARM::BR_JTadd)
00956     OpNum = 2;
00957   else if (Opcode == ARM::BR_JTm)
00958     OpNum = 3;
00959 
00960   const MachineOperand &MO1 = MI->getOperand(OpNum);
00961   const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
00962   unsigned JTI = MO1.getIndex();
00963 
00964   // Emit a label for the jump table.
00965   MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
00966   OutStreamer.EmitLabel(JTISymbol);
00967 
00968   // Mark the jump table as data-in-code.
00969   OutStreamer.EmitDataRegion(MCDR_DataRegionJT32);
00970 
00971   // Emit each entry of the table.
00972   const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
00973   const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
00974   const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
00975 
00976   for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
00977     MachineBasicBlock *MBB = JTBBs[i];
00978     // Construct an MCExpr for the entry. We want a value of the form:
00979     // (BasicBlockAddr - TableBeginAddr)
00980     //
00981     // For example, a table with entries jumping to basic blocks BB0 and BB1
00982     // would look like:
00983     // LJTI_0_0:
00984     //    .word (LBB0 - LJTI_0_0)
00985     //    .word (LBB1 - LJTI_0_0)
00986     const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
00987 
00988     if (TM.getRelocationModel() == Reloc::PIC_)
00989       Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
00990                                                                    OutContext),
00991                                      OutContext);
00992     // If we're generating a table of Thumb addresses in static relocation
00993     // model, we need to add one to keep interworking correctly.
00994     else if (AFI->isThumbFunction())
00995       Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(1,OutContext),
00996                                      OutContext);
00997     OutStreamer.EmitValue(Expr, 4);
00998   }
00999   // Mark the end of jump table data-in-code region.
01000   OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
01001 }
01002 
01003 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
01004   unsigned Opcode = MI->getOpcode();
01005   int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
01006   const MachineOperand &MO1 = MI->getOperand(OpNum);
01007   const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
01008   unsigned JTI = MO1.getIndex();
01009 
01010   MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
01011   OutStreamer.EmitLabel(JTISymbol);
01012 
01013   // Emit each entry of the table.
01014   const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
01015   const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
01016   const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
01017   unsigned OffsetWidth = 4;
01018   if (MI->getOpcode() == ARM::t2TBB_JT) {
01019     OffsetWidth = 1;
01020     // Mark the jump table as data-in-code.
01021     OutStreamer.EmitDataRegion(MCDR_DataRegionJT8);
01022   } else if (MI->getOpcode() == ARM::t2TBH_JT) {
01023     OffsetWidth = 2;
01024     // Mark the jump table as data-in-code.
01025     OutStreamer.EmitDataRegion(MCDR_DataRegionJT16);
01026   }
01027 
01028   for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
01029     MachineBasicBlock *MBB = JTBBs[i];
01030     const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
01031                                                           OutContext);
01032     // If this isn't a TBB or TBH, the entries are direct branch instructions.
01033     if (OffsetWidth == 4) {
01034       EmitToStreamer(OutStreamer, MCInstBuilder(ARM::t2B)
01035         .addExpr(MBBSymbolExpr)
01036         .addImm(ARMCC::AL)
01037         .addReg(0));
01038       continue;
01039     }
01040     // Otherwise it's an offset from the dispatch instruction. Construct an
01041     // MCExpr for the entry. We want a value of the form:
01042     // (BasicBlockAddr - TableBeginAddr) / 2
01043     //
01044     // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
01045     // would look like:
01046     // LJTI_0_0:
01047     //    .byte (LBB0 - LJTI_0_0) / 2
01048     //    .byte (LBB1 - LJTI_0_0) / 2
01049     const MCExpr *Expr =
01050       MCBinaryExpr::CreateSub(MBBSymbolExpr,
01051                               MCSymbolRefExpr::Create(JTISymbol, OutContext),
01052                               OutContext);
01053     Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
01054                                    OutContext);
01055     OutStreamer.EmitValue(Expr, OffsetWidth);
01056   }
01057   // Mark the end of jump table data-in-code region. 32-bit offsets use
01058   // actual branch instructions here, so we don't mark those as a data-region
01059   // at all.
01060   if (OffsetWidth != 4)
01061     OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
01062 }
01063 
01064 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
01065   assert(MI->getFlag(MachineInstr::FrameSetup) &&
01066       "Only instruction which are involved into frame setup code are allowed");
01067 
01068   MCTargetStreamer &TS = *OutStreamer.getTargetStreamer();
01069   ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
01070   const MachineFunction &MF = *MI->getParent()->getParent();
01071   const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
01072   const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
01073 
01074   unsigned FramePtr = RegInfo->getFrameRegister(MF);
01075   unsigned Opc = MI->getOpcode();
01076   unsigned SrcReg, DstReg;
01077 
01078   if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
01079     // Two special cases:
01080     // 1) tPUSH does not have src/dst regs.
01081     // 2) for Thumb1 code we sometimes materialize the constant via constpool
01082     // load. Yes, this is pretty fragile, but for now I don't see better
01083     // way... :(
01084     SrcReg = DstReg = ARM::SP;
01085   } else {
01086     SrcReg = MI->getOperand(1).getReg();
01087     DstReg = MI->getOperand(0).getReg();
01088   }
01089 
01090   // Try to figure out the unwinding opcode out of src / dst regs.
01091   if (MI->mayStore()) {
01092     // Register saves.
01093     assert(DstReg == ARM::SP &&
01094            "Only stack pointer as a destination reg is supported");
01095 
01096     SmallVector<unsigned, 4> RegList;
01097     // Skip src & dst reg, and pred ops.
01098     unsigned StartOp = 2 + 2;
01099     // Use all the operands.
01100     unsigned NumOffset = 0;
01101 
01102     switch (Opc) {
01103     default:
01104       MI->dump();
01105       llvm_unreachable("Unsupported opcode for unwinding information");
01106     case ARM::tPUSH:
01107       // Special case here: no src & dst reg, but two extra imp ops.
01108       StartOp = 2; NumOffset = 2;
01109     case ARM::STMDB_UPD:
01110     case ARM::t2STMDB_UPD:
01111     case ARM::VSTMDDB_UPD:
01112       assert(SrcReg == ARM::SP &&
01113              "Only stack pointer as a source reg is supported");
01114       for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
01115            i != NumOps; ++i) {
01116         const MachineOperand &MO = MI->getOperand(i);
01117         // Actually, there should never be any impdef stuff here. Skip it
01118         // temporary to workaround PR11902.
01119         if (MO.isImplicit())
01120           continue;
01121         RegList.push_back(MO.getReg());
01122       }
01123       break;
01124     case ARM::STR_PRE_IMM:
01125     case ARM::STR_PRE_REG:
01126     case ARM::t2STR_PRE:
01127       assert(MI->getOperand(2).getReg() == ARM::SP &&
01128              "Only stack pointer as a source reg is supported");
01129       RegList.push_back(SrcReg);
01130       break;
01131     }
01132     if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM)
01133       ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
01134   } else {
01135     // Changes of stack / frame pointer.
01136     if (SrcReg == ARM::SP) {
01137       int64_t Offset = 0;
01138       switch (Opc) {
01139       default:
01140         MI->dump();
01141         llvm_unreachable("Unsupported opcode for unwinding information");
01142       case ARM::MOVr:
01143       case ARM::tMOVr:
01144         Offset = 0;
01145         break;
01146       case ARM::ADDri:
01147         Offset = -MI->getOperand(2).getImm();
01148         break;
01149       case ARM::SUBri:
01150       case ARM::t2SUBri:
01151         Offset = MI->getOperand(2).getImm();
01152         break;
01153       case ARM::tSUBspi:
01154         Offset = MI->getOperand(2).getImm()*4;
01155         break;
01156       case ARM::tADDspi:
01157       case ARM::tADDrSPi:
01158         Offset = -MI->getOperand(2).getImm()*4;
01159         break;
01160       case ARM::tLDRpci: {
01161         // Grab the constpool index and check, whether it corresponds to
01162         // original or cloned constpool entry.
01163         unsigned CPI = MI->getOperand(1).getIndex();
01164         const MachineConstantPool *MCP = MF.getConstantPool();
01165         if (CPI >= MCP->getConstants().size())
01166           CPI = AFI.getOriginalCPIdx(CPI);
01167         assert(CPI != -1U && "Invalid constpool index");
01168 
01169         // Derive the actual offset.
01170         const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
01171         assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
01172         // FIXME: Check for user, it should be "add" instruction!
01173         Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
01174         break;
01175       }
01176       }
01177 
01178       if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM) {
01179         if (DstReg == FramePtr && FramePtr != ARM::SP)
01180           // Set-up of the frame pointer. Positive values correspond to "add"
01181           // instruction.
01182           ATS.emitSetFP(FramePtr, ARM::SP, -Offset);
01183         else if (DstReg == ARM::SP) {
01184           // Change of SP by an offset. Positive values correspond to "sub"
01185           // instruction.
01186           ATS.emitPad(Offset);
01187         } else {
01188           // Move of SP to a register.  Positive values correspond to an "add"
01189           // instruction.
01190           ATS.emitMovSP(DstReg, -Offset);
01191         }
01192       }
01193     } else if (DstReg == ARM::SP) {
01194       MI->dump();
01195       llvm_unreachable("Unsupported opcode for unwinding information");
01196     }
01197     else {
01198       MI->dump();
01199       llvm_unreachable("Unsupported opcode for unwinding information");
01200     }
01201   }
01202 }
01203 
01204 // Simple pseudo-instructions have their lowering (with expansion to real
01205 // instructions) auto-generated.
01206 #include "ARMGenMCPseudoLowering.inc"
01207 
01208 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
01209   const DataLayout *DL = TM.getDataLayout();
01210 
01211   // If we just ended a constant pool, mark it as such.
01212   if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
01213     OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
01214     InConstantPool = false;
01215   }
01216 
01217   // Emit unwinding stuff for frame-related instructions
01218   if (Subtarget->isTargetEHABICompatible() &&
01219        MI->getFlag(MachineInstr::FrameSetup))
01220     EmitUnwindingInstruction(MI);
01221 
01222   // Do any auto-generated pseudo lowerings.
01223   if (emitPseudoExpansionLowering(OutStreamer, MI))
01224     return;
01225 
01226   assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
01227          "Pseudo flag setting opcode should be expanded early");
01228 
01229   // Check for manual lowerings.
01230   unsigned Opc = MI->getOpcode();
01231   switch (Opc) {
01232   case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
01233   case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing");
01234   case ARM::LEApcrel:
01235   case ARM::tLEApcrel:
01236   case ARM::t2LEApcrel: {
01237     // FIXME: Need to also handle globals and externals
01238     MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex());
01239     EmitToStreamer(OutStreamer, MCInstBuilder(MI->getOpcode() ==
01240                                               ARM::t2LEApcrel ? ARM::t2ADR
01241                   : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
01242                      : ARM::ADR))
01243       .addReg(MI->getOperand(0).getReg())
01244       .addExpr(MCSymbolRefExpr::Create(CPISymbol, OutContext))
01245       // Add predicate operands.
01246       .addImm(MI->getOperand(2).getImm())
01247       .addReg(MI->getOperand(3).getReg()));
01248     return;
01249   }
01250   case ARM::LEApcrelJT:
01251   case ARM::tLEApcrelJT:
01252   case ARM::t2LEApcrelJT: {
01253     MCSymbol *JTIPICSymbol =
01254       GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
01255                                   MI->getOperand(2).getImm());
01256     EmitToStreamer(OutStreamer, MCInstBuilder(MI->getOpcode() ==
01257                                               ARM::t2LEApcrelJT ? ARM::t2ADR
01258                   : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
01259                      : ARM::ADR))
01260       .addReg(MI->getOperand(0).getReg())
01261       .addExpr(MCSymbolRefExpr::Create(JTIPICSymbol, OutContext))
01262       // Add predicate operands.
01263       .addImm(MI->getOperand(3).getImm())
01264       .addReg(MI->getOperand(4).getReg()));
01265     return;
01266   }
01267   // Darwin call instructions are just normal call instructions with different
01268   // clobber semantics (they clobber R9).
01269   case ARM::BX_CALL: {
01270     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
01271       .addReg(ARM::LR)
01272       .addReg(ARM::PC)
01273       // Add predicate operands.
01274       .addImm(ARMCC::AL)
01275       .addReg(0)
01276       // Add 's' bit operand (always reg0 for this)
01277       .addReg(0));
01278 
01279     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::BX)
01280       .addReg(MI->getOperand(0).getReg()));
01281     return;
01282   }
01283   case ARM::tBX_CALL: {
01284     if (Subtarget->hasV5TOps())
01285       llvm_unreachable("Expected BLX to be selected for v5t+");
01286 
01287     // On ARM v4t, when doing a call from thumb mode, we need to ensure
01288     // that the saved lr has its LSB set correctly (the arch doesn't
01289     // have blx).
01290     // So here we generate a bl to a small jump pad that does bx rN.
01291     // The jump pads are emitted after the function body.
01292 
01293     unsigned TReg = MI->getOperand(0).getReg();
01294     MCSymbol *TRegSym = nullptr;
01295     for (unsigned i = 0, e = ThumbIndirectPads.size(); i < e; i++) {
01296       if (ThumbIndirectPads[i].first == TReg) {
01297         TRegSym = ThumbIndirectPads[i].second;
01298         break;
01299       }
01300     }
01301 
01302     if (!TRegSym) {
01303       TRegSym = OutContext.CreateTempSymbol();
01304       ThumbIndirectPads.push_back(std::make_pair(TReg, TRegSym));
01305     }
01306 
01307     // Create a link-saving branch to the Reg Indirect Jump Pad.
01308     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tBL)
01309         // Predicate comes first here.
01310         .addImm(ARMCC::AL).addReg(0)
01311         .addExpr(MCSymbolRefExpr::Create(TRegSym, OutContext)));
01312     return;
01313   }
01314   case ARM::BMOVPCRX_CALL: {
01315     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
01316       .addReg(ARM::LR)
01317       .addReg(ARM::PC)
01318       // Add predicate operands.
01319       .addImm(ARMCC::AL)
01320       .addReg(0)
01321       // Add 's' bit operand (always reg0 for this)
01322       .addReg(0));
01323 
01324     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
01325       .addReg(ARM::PC)
01326       .addReg(MI->getOperand(0).getReg())
01327       // Add predicate operands.
01328       .addImm(ARMCC::AL)
01329       .addReg(0)
01330       // Add 's' bit operand (always reg0 for this)
01331       .addReg(0));
01332     return;
01333   }
01334   case ARM::BMOVPCB_CALL: {
01335     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
01336       .addReg(ARM::LR)
01337       .addReg(ARM::PC)
01338       // Add predicate operands.
01339       .addImm(ARMCC::AL)
01340       .addReg(0)
01341       // Add 's' bit operand (always reg0 for this)
01342       .addReg(0));
01343 
01344     const MachineOperand &Op = MI->getOperand(0);
01345     const GlobalValue *GV = Op.getGlobal();
01346     const unsigned TF = Op.getTargetFlags();
01347     MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
01348     const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
01349     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::Bcc)
01350       .addExpr(GVSymExpr)
01351       // Add predicate operands.
01352       .addImm(ARMCC::AL)
01353       .addReg(0));
01354     return;
01355   }
01356   case ARM::MOVi16_ga_pcrel:
01357   case ARM::t2MOVi16_ga_pcrel: {
01358     MCInst TmpInst;
01359     TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
01360     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
01361 
01362     unsigned TF = MI->getOperand(1).getTargetFlags();
01363     const GlobalValue *GV = MI->getOperand(1).getGlobal();
01364     MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
01365     const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
01366 
01367     MCSymbol *LabelSym = getPICLabel(DL->getPrivateGlobalPrefix(),
01368                                      getFunctionNumber(),
01369                                      MI->getOperand(2).getImm(), OutContext);
01370     const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
01371     unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
01372     const MCExpr *PCRelExpr =
01373       ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
01374                                       MCBinaryExpr::CreateAdd(LabelSymExpr,
01375                                       MCConstantExpr::Create(PCAdj, OutContext),
01376                                       OutContext), OutContext), OutContext);
01377       TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
01378 
01379     // Add predicate operands.
01380     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
01381     TmpInst.addOperand(MCOperand::CreateReg(0));
01382     // Add 's' bit operand (always reg0 for this)
01383     TmpInst.addOperand(MCOperand::CreateReg(0));
01384     EmitToStreamer(OutStreamer, TmpInst);
01385     return;
01386   }
01387   case ARM::MOVTi16_ga_pcrel:
01388   case ARM::t2MOVTi16_ga_pcrel: {
01389     MCInst TmpInst;
01390     TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
01391                       ? ARM::MOVTi16 : ARM::t2MOVTi16);
01392     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
01393     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
01394 
01395     unsigned TF = MI->getOperand(2).getTargetFlags();
01396     const GlobalValue *GV = MI->getOperand(2).getGlobal();
01397     MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
01398     const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
01399 
01400     MCSymbol *LabelSym = getPICLabel(DL->getPrivateGlobalPrefix(),
01401                                      getFunctionNumber(),
01402                                      MI->getOperand(3).getImm(), OutContext);
01403     const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
01404     unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
01405     const MCExpr *PCRelExpr =
01406         ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
01407                                    MCBinaryExpr::CreateAdd(LabelSymExpr,
01408                                       MCConstantExpr::Create(PCAdj, OutContext),
01409                                           OutContext), OutContext), OutContext);
01410       TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
01411     // Add predicate operands.
01412     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
01413     TmpInst.addOperand(MCOperand::CreateReg(0));
01414     // Add 's' bit operand (always reg0 for this)
01415     TmpInst.addOperand(MCOperand::CreateReg(0));
01416     EmitToStreamer(OutStreamer, TmpInst);
01417     return;
01418   }
01419   case ARM::tPICADD: {
01420     // This is a pseudo op for a label + instruction sequence, which looks like:
01421     // LPC0:
01422     //     add r0, pc
01423     // This adds the address of LPC0 to r0.
01424 
01425     // Emit the label.
01426     OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
01427                           getFunctionNumber(), MI->getOperand(2).getImm(),
01428                           OutContext));
01429 
01430     // Form and emit the add.
01431     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tADDhirr)
01432       .addReg(MI->getOperand(0).getReg())
01433       .addReg(MI->getOperand(0).getReg())
01434       .addReg(ARM::PC)
01435       // Add predicate operands.
01436       .addImm(ARMCC::AL)
01437       .addReg(0));
01438     return;
01439   }
01440   case ARM::PICADD: {
01441     // This is a pseudo op for a label + instruction sequence, which looks like:
01442     // LPC0:
01443     //     add r0, pc, r0
01444     // This adds the address of LPC0 to r0.
01445 
01446     // Emit the label.
01447     OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
01448                           getFunctionNumber(), MI->getOperand(2).getImm(),
01449                           OutContext));
01450 
01451     // Form and emit the add.
01452     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDrr)
01453       .addReg(MI->getOperand(0).getReg())
01454       .addReg(ARM::PC)
01455       .addReg(MI->getOperand(1).getReg())
01456       // Add predicate operands.
01457       .addImm(MI->getOperand(3).getImm())
01458       .addReg(MI->getOperand(4).getReg())
01459       // Add 's' bit operand (always reg0 for this)
01460       .addReg(0));
01461     return;
01462   }
01463   case ARM::PICSTR:
01464   case ARM::PICSTRB:
01465   case ARM::PICSTRH:
01466   case ARM::PICLDR:
01467   case ARM::PICLDRB:
01468   case ARM::PICLDRH:
01469   case ARM::PICLDRSB:
01470   case ARM::PICLDRSH: {
01471     // This is a pseudo op for a label + instruction sequence, which looks like:
01472     // LPC0:
01473     //     OP r0, [pc, r0]
01474     // The LCP0 label is referenced by a constant pool entry in order to get
01475     // a PC-relative address at the ldr instruction.
01476 
01477     // Emit the label.
01478     OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
01479                           getFunctionNumber(), MI->getOperand(2).getImm(),
01480                           OutContext));
01481 
01482     // Form and emit the load
01483     unsigned Opcode;
01484     switch (MI->getOpcode()) {
01485     default:
01486       llvm_unreachable("Unexpected opcode!");
01487     case ARM::PICSTR:   Opcode = ARM::STRrs; break;
01488     case ARM::PICSTRB:  Opcode = ARM::STRBrs; break;
01489     case ARM::PICSTRH:  Opcode = ARM::STRH; break;
01490     case ARM::PICLDR:   Opcode = ARM::LDRrs; break;
01491     case ARM::PICLDRB:  Opcode = ARM::LDRBrs; break;
01492     case ARM::PICLDRH:  Opcode = ARM::LDRH; break;
01493     case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
01494     case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
01495     }
01496     EmitToStreamer(OutStreamer, MCInstBuilder(Opcode)
01497       .addReg(MI->getOperand(0).getReg())
01498       .addReg(ARM::PC)
01499       .addReg(MI->getOperand(1).getReg())
01500       .addImm(0)
01501       // Add predicate operands.
01502       .addImm(MI->getOperand(3).getImm())
01503       .addReg(MI->getOperand(4).getReg()));
01504 
01505     return;
01506   }
01507   case ARM::CONSTPOOL_ENTRY: {
01508     /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
01509     /// in the function.  The first operand is the ID# for this instruction, the
01510     /// second is the index into the MachineConstantPool that this is, the third
01511     /// is the size in bytes of this constant pool entry.
01512     /// The required alignment is specified on the basic block holding this MI.
01513     unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
01514     unsigned CPIdx   = (unsigned)MI->getOperand(1).getIndex();
01515 
01516     // If this is the first entry of the pool, mark it.
01517     if (!InConstantPool) {
01518       OutStreamer.EmitDataRegion(MCDR_DataRegion);
01519       InConstantPool = true;
01520     }
01521 
01522     OutStreamer.EmitLabel(GetCPISymbol(LabelId));
01523 
01524     const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
01525     if (MCPE.isMachineConstantPoolEntry())
01526       EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
01527     else
01528       EmitGlobalConstant(MCPE.Val.ConstVal);
01529     return;
01530   }
01531   case ARM::t2BR_JT: {
01532     // Lower and emit the instruction itself, then the jump table following it.
01533     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
01534       .addReg(ARM::PC)
01535       .addReg(MI->getOperand(0).getReg())
01536       // Add predicate operands.
01537       .addImm(ARMCC::AL)
01538       .addReg(0));
01539 
01540     // Output the data for the jump table itself
01541     EmitJump2Table(MI);
01542     return;
01543   }
01544   case ARM::t2TBB_JT: {
01545     // Lower and emit the instruction itself, then the jump table following it.
01546     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::t2TBB)
01547       .addReg(ARM::PC)
01548       .addReg(MI->getOperand(0).getReg())
01549       // Add predicate operands.
01550       .addImm(ARMCC::AL)
01551       .addReg(0));
01552 
01553     // Output the data for the jump table itself
01554     EmitJump2Table(MI);
01555     // Make sure the next instruction is 2-byte aligned.
01556     EmitAlignment(1);
01557     return;
01558   }
01559   case ARM::t2TBH_JT: {
01560     // Lower and emit the instruction itself, then the jump table following it.
01561     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::t2TBH)
01562       .addReg(ARM::PC)
01563       .addReg(MI->getOperand(0).getReg())
01564       // Add predicate operands.
01565       .addImm(ARMCC::AL)
01566       .addReg(0));
01567 
01568     // Output the data for the jump table itself
01569     EmitJump2Table(MI);
01570     return;
01571   }
01572   case ARM::tBR_JTr:
01573   case ARM::BR_JTr: {
01574     // Lower and emit the instruction itself, then the jump table following it.
01575     // mov pc, target
01576     MCInst TmpInst;
01577     unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
01578       ARM::MOVr : ARM::tMOVr;
01579     TmpInst.setOpcode(Opc);
01580     TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
01581     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
01582     // Add predicate operands.
01583     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
01584     TmpInst.addOperand(MCOperand::CreateReg(0));
01585     // Add 's' bit operand (always reg0 for this)
01586     if (Opc == ARM::MOVr)
01587       TmpInst.addOperand(MCOperand::CreateReg(0));
01588     EmitToStreamer(OutStreamer, TmpInst);
01589 
01590     // Make sure the Thumb jump table is 4-byte aligned.
01591     if (Opc == ARM::tMOVr)
01592       EmitAlignment(2);
01593 
01594     // Output the data for the jump table itself
01595     EmitJumpTable(MI);
01596     return;
01597   }
01598   case ARM::BR_JTm: {
01599     // Lower and emit the instruction itself, then the jump table following it.
01600     // ldr pc, target
01601     MCInst TmpInst;
01602     if (MI->getOperand(1).getReg() == 0) {
01603       // literal offset
01604       TmpInst.setOpcode(ARM::LDRi12);
01605       TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
01606       TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
01607       TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
01608     } else {
01609       TmpInst.setOpcode(ARM::LDRrs);
01610       TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
01611       TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
01612       TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
01613       TmpInst.addOperand(MCOperand::CreateImm(0));
01614     }
01615     // Add predicate operands.
01616     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
01617     TmpInst.addOperand(MCOperand::CreateReg(0));
01618     EmitToStreamer(OutStreamer, TmpInst);
01619 
01620     // Output the data for the jump table itself
01621     EmitJumpTable(MI);
01622     return;
01623   }
01624   case ARM::BR_JTadd: {
01625     // Lower and emit the instruction itself, then the jump table following it.
01626     // add pc, target, idx
01627     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDrr)
01628       .addReg(ARM::PC)
01629       .addReg(MI->getOperand(0).getReg())
01630       .addReg(MI->getOperand(1).getReg())
01631       // Add predicate operands.
01632       .addImm(ARMCC::AL)
01633       .addReg(0)
01634       // Add 's' bit operand (always reg0 for this)
01635       .addReg(0));
01636 
01637     // Output the data for the jump table itself
01638     EmitJumpTable(MI);
01639     return;
01640   }
01641   case ARM::SPACE:
01642     OutStreamer.EmitZeros(MI->getOperand(1).getImm());
01643     return;
01644   case ARM::TRAP: {
01645     // Non-Darwin binutils don't yet support the "trap" mnemonic.
01646     // FIXME: Remove this special case when they do.
01647     if (!Subtarget->isTargetMachO()) {
01648       //.long 0xe7ffdefe @ trap
01649       uint32_t Val = 0xe7ffdefeUL;
01650       OutStreamer.AddComment("trap");
01651       OutStreamer.EmitIntValue(Val, 4);
01652       return;
01653     }
01654     break;
01655   }
01656   case ARM::TRAPNaCl: {
01657     //.long 0xe7fedef0 @ trap
01658     uint32_t Val = 0xe7fedef0UL;
01659     OutStreamer.AddComment("trap");
01660     OutStreamer.EmitIntValue(Val, 4);
01661     return;
01662   }
01663   case ARM::tTRAP: {
01664     // Non-Darwin binutils don't yet support the "trap" mnemonic.
01665     // FIXME: Remove this special case when they do.
01666     if (!Subtarget->isTargetMachO()) {
01667       //.short 57086 @ trap
01668       uint16_t Val = 0xdefe;
01669       OutStreamer.AddComment("trap");
01670       OutStreamer.EmitIntValue(Val, 2);
01671       return;
01672     }
01673     break;
01674   }
01675   case ARM::t2Int_eh_sjlj_setjmp:
01676   case ARM::t2Int_eh_sjlj_setjmp_nofp:
01677   case ARM::tInt_eh_sjlj_setjmp: {
01678     // Two incoming args: GPR:$src, GPR:$val
01679     // mov $val, pc
01680     // adds $val, #7
01681     // str $val, [$src, #4]
01682     // movs r0, #0
01683     // b 1f
01684     // movs r0, #1
01685     // 1:
01686     unsigned SrcReg = MI->getOperand(0).getReg();
01687     unsigned ValReg = MI->getOperand(1).getReg();
01688     MCSymbol *Label = GetARMSJLJEHLabel();
01689     OutStreamer.AddComment("eh_setjmp begin");
01690     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
01691       .addReg(ValReg)
01692       .addReg(ARM::PC)
01693       // Predicate.
01694       .addImm(ARMCC::AL)
01695       .addReg(0));
01696 
01697     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tADDi3)
01698       .addReg(ValReg)
01699       // 's' bit operand
01700       .addReg(ARM::CPSR)
01701       .addReg(ValReg)
01702       .addImm(7)
01703       // Predicate.
01704       .addImm(ARMCC::AL)
01705       .addReg(0));
01706 
01707     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tSTRi)
01708       .addReg(ValReg)
01709       .addReg(SrcReg)
01710       // The offset immediate is #4. The operand value is scaled by 4 for the
01711       // tSTR instruction.
01712       .addImm(1)
01713       // Predicate.
01714       .addImm(ARMCC::AL)
01715       .addReg(0));
01716 
01717     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVi8)
01718       .addReg(ARM::R0)
01719       .addReg(ARM::CPSR)
01720       .addImm(0)
01721       // Predicate.
01722       .addImm(ARMCC::AL)
01723       .addReg(0));
01724 
01725     const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
01726     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tB)
01727       .addExpr(SymbolExpr)
01728       .addImm(ARMCC::AL)
01729       .addReg(0));
01730 
01731     OutStreamer.AddComment("eh_setjmp end");
01732     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVi8)
01733       .addReg(ARM::R0)
01734       .addReg(ARM::CPSR)
01735       .addImm(1)
01736       // Predicate.
01737       .addImm(ARMCC::AL)
01738       .addReg(0));
01739 
01740     OutStreamer.EmitLabel(Label);
01741     return;
01742   }
01743 
01744   case ARM::Int_eh_sjlj_setjmp_nofp:
01745   case ARM::Int_eh_sjlj_setjmp: {
01746     // Two incoming args: GPR:$src, GPR:$val
01747     // add $val, pc, #8
01748     // str $val, [$src, #+4]
01749     // mov r0, #0
01750     // add pc, pc, #0
01751     // mov r0, #1
01752     unsigned SrcReg = MI->getOperand(0).getReg();
01753     unsigned ValReg = MI->getOperand(1).getReg();
01754 
01755     OutStreamer.AddComment("eh_setjmp begin");
01756     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDri)
01757       .addReg(ValReg)
01758       .addReg(ARM::PC)
01759       .addImm(8)
01760       // Predicate.
01761       .addImm(ARMCC::AL)
01762       .addReg(0)
01763       // 's' bit operand (always reg0 for this).
01764       .addReg(0));
01765 
01766     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::STRi12)
01767       .addReg(ValReg)
01768       .addReg(SrcReg)
01769       .addImm(4)
01770       // Predicate.
01771       .addImm(ARMCC::AL)
01772       .addReg(0));
01773 
01774     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVi)
01775       .addReg(ARM::R0)
01776       .addImm(0)
01777       // Predicate.
01778       .addImm(ARMCC::AL)
01779       .addReg(0)
01780       // 's' bit operand (always reg0 for this).
01781       .addReg(0));
01782 
01783     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDri)
01784       .addReg(ARM::PC)
01785       .addReg(ARM::PC)
01786       .addImm(0)
01787       // Predicate.
01788       .addImm(ARMCC::AL)
01789       .addReg(0)
01790       // 's' bit operand (always reg0 for this).
01791       .addReg(0));
01792 
01793     OutStreamer.AddComment("eh_setjmp end");
01794     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVi)
01795       .addReg(ARM::R0)
01796       .addImm(1)
01797       // Predicate.
01798       .addImm(ARMCC::AL)
01799       .addReg(0)
01800       // 's' bit operand (always reg0 for this).
01801       .addReg(0));
01802     return;
01803   }
01804   case ARM::Int_eh_sjlj_longjmp: {
01805     // ldr sp, [$src, #8]
01806     // ldr $scratch, [$src, #4]
01807     // ldr r7, [$src]
01808     // bx $scratch
01809     unsigned SrcReg = MI->getOperand(0).getReg();
01810     unsigned ScratchReg = MI->getOperand(1).getReg();
01811     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::LDRi12)
01812       .addReg(ARM::SP)
01813       .addReg(SrcReg)
01814       .addImm(8)
01815       // Predicate.
01816       .addImm(ARMCC::AL)
01817       .addReg(0));
01818 
01819     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::LDRi12)
01820       .addReg(ScratchReg)
01821       .addReg(SrcReg)
01822       .addImm(4)
01823       // Predicate.
01824       .addImm(ARMCC::AL)
01825       .addReg(0));
01826 
01827     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::LDRi12)
01828       .addReg(ARM::R7)
01829       .addReg(SrcReg)
01830       .addImm(0)
01831       // Predicate.
01832       .addImm(ARMCC::AL)
01833       .addReg(0));
01834 
01835     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::BX)
01836       .addReg(ScratchReg)
01837       // Predicate.
01838       .addImm(ARMCC::AL)
01839       .addReg(0));
01840     return;
01841   }
01842   case ARM::tInt_eh_sjlj_longjmp: {
01843     // ldr $scratch, [$src, #8]
01844     // mov sp, $scratch
01845     // ldr $scratch, [$src, #4]
01846     // ldr r7, [$src]
01847     // bx $scratch
01848     unsigned SrcReg = MI->getOperand(0).getReg();
01849     unsigned ScratchReg = MI->getOperand(1).getReg();
01850     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tLDRi)
01851       .addReg(ScratchReg)
01852       .addReg(SrcReg)
01853       // The offset immediate is #8. The operand value is scaled by 4 for the
01854       // tLDR instruction.
01855       .addImm(2)
01856       // Predicate.
01857       .addImm(ARMCC::AL)
01858       .addReg(0));
01859 
01860     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
01861       .addReg(ARM::SP)
01862       .addReg(ScratchReg)
01863       // Predicate.
01864       .addImm(ARMCC::AL)
01865       .addReg(0));
01866 
01867     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tLDRi)
01868       .addReg(ScratchReg)
01869       .addReg(SrcReg)
01870       .addImm(1)
01871       // Predicate.
01872       .addImm(ARMCC::AL)
01873       .addReg(0));
01874 
01875     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tLDRi)
01876       .addReg(ARM::R7)
01877       .addReg(SrcReg)
01878       .addImm(0)
01879       // Predicate.
01880       .addImm(ARMCC::AL)
01881       .addReg(0));
01882 
01883     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tBX)
01884       .addReg(ScratchReg)
01885       // Predicate.
01886       .addImm(ARMCC::AL)
01887       .addReg(0));
01888     return;
01889   }
01890   }
01891 
01892   MCInst TmpInst;
01893   LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
01894 
01895   EmitToStreamer(OutStreamer, TmpInst);
01896 }
01897 
01898 //===----------------------------------------------------------------------===//
01899 // Target Registry Stuff
01900 //===----------------------------------------------------------------------===//
01901 
01902 // Force static initialization.
01903 extern "C" void LLVMInitializeARMAsmPrinter() {
01904   RegisterAsmPrinter<ARMAsmPrinter> X(TheARMLETarget);
01905   RegisterAsmPrinter<ARMAsmPrinter> Y(TheARMBETarget);
01906   RegisterAsmPrinter<ARMAsmPrinter> A(TheThumbLETarget);
01907   RegisterAsmPrinter<ARMAsmPrinter> B(TheThumbBETarget);
01908 }