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ARMAsmPrinter.cpp
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00001 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file contains a printer that converts from our internal representation
00011 // of machine-dependent LLVM code to GAS-format ARM assembly language.
00012 //
00013 //===----------------------------------------------------------------------===//
00014 
00015 #define DEBUG_TYPE "asm-printer"
00016 #include "ARMAsmPrinter.h"
00017 #include "ARM.h"
00018 #include "ARMConstantPoolValue.h"
00019 #include "ARMFPUName.h"
00020 #include "ARMMachineFunctionInfo.h"
00021 #include "ARMTargetMachine.h"
00022 #include "ARMTargetObjectFile.h"
00023 #include "InstPrinter/ARMInstPrinter.h"
00024 #include "MCTargetDesc/ARMAddressingModes.h"
00025 #include "MCTargetDesc/ARMMCExpr.h"
00026 #include "llvm/ADT/SetVector.h"
00027 #include "llvm/ADT/SmallString.h"
00028 #include "llvm/CodeGen/MachineFunctionPass.h"
00029 #include "llvm/CodeGen/MachineJumpTableInfo.h"
00030 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
00031 #include "llvm/IR/Constants.h"
00032 #include "llvm/IR/DataLayout.h"
00033 #include "llvm/IR/DebugInfo.h"
00034 #include "llvm/IR/Mangler.h"
00035 #include "llvm/IR/Module.h"
00036 #include "llvm/IR/Type.h"
00037 #include "llvm/MC/MCAsmInfo.h"
00038 #include "llvm/MC/MCAssembler.h"
00039 #include "llvm/MC/MCContext.h"
00040 #include "llvm/MC/MCELFStreamer.h"
00041 #include "llvm/MC/MCInst.h"
00042 #include "llvm/MC/MCInstBuilder.h"
00043 #include "llvm/MC/MCObjectStreamer.h"
00044 #include "llvm/MC/MCSectionMachO.h"
00045 #include "llvm/MC/MCStreamer.h"
00046 #include "llvm/MC/MCSymbol.h"
00047 #include "llvm/Support/ARMBuildAttributes.h"
00048 #include "llvm/Support/CommandLine.h"
00049 #include "llvm/Support/Debug.h"
00050 #include "llvm/Support/ELF.h"
00051 #include "llvm/Support/ErrorHandling.h"
00052 #include "llvm/Support/TargetRegistry.h"
00053 #include "llvm/Support/raw_ostream.h"
00054 #include "llvm/Target/TargetMachine.h"
00055 #include <cctype>
00056 using namespace llvm;
00057 
00058 void ARMAsmPrinter::EmitFunctionBodyEnd() {
00059   // Make sure to terminate any constant pools that were at the end
00060   // of the function.
00061   if (!InConstantPool)
00062     return;
00063   InConstantPool = false;
00064   OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
00065 }
00066 
00067 void ARMAsmPrinter::EmitFunctionEntryLabel() {
00068   if (AFI->isThumbFunction()) {
00069     OutStreamer.EmitAssemblerFlag(MCAF_Code16);
00070     OutStreamer.EmitThumbFunc(CurrentFnSym);
00071   }
00072 
00073   OutStreamer.EmitLabel(CurrentFnSym);
00074 }
00075 
00076 void ARMAsmPrinter::EmitXXStructor(const Constant *CV) {
00077   uint64_t Size = TM.getDataLayout()->getTypeAllocSize(CV->getType());
00078   assert(Size && "C++ constructor pointer had zero size!");
00079 
00080   const GlobalValue *GV = dyn_cast<GlobalValue>(CV->stripPointerCasts());
00081   assert(GV && "C++ constructor pointer was not a GlobalValue!");
00082 
00083   const MCExpr *E = MCSymbolRefExpr::Create(getSymbol(GV),
00084                                             (Subtarget->isTargetELF()
00085                                              ? MCSymbolRefExpr::VK_ARM_TARGET1
00086                                              : MCSymbolRefExpr::VK_None),
00087                                             OutContext);
00088 
00089   OutStreamer.EmitValue(E, Size);
00090 }
00091 
00092 /// runOnMachineFunction - This uses the EmitInstruction()
00093 /// method to print assembly for each instruction.
00094 ///
00095 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
00096   AFI = MF.getInfo<ARMFunctionInfo>();
00097   MCP = MF.getConstantPool();
00098 
00099   return AsmPrinter::runOnMachineFunction(MF);
00100 }
00101 
00102 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
00103                                  raw_ostream &O, const char *Modifier) {
00104   const MachineOperand &MO = MI->getOperand(OpNum);
00105   unsigned TF = MO.getTargetFlags();
00106 
00107   switch (MO.getType()) {
00108   default: llvm_unreachable("<unknown operand type>");
00109   case MachineOperand::MO_Register: {
00110     unsigned Reg = MO.getReg();
00111     assert(TargetRegisterInfo::isPhysicalRegister(Reg));
00112     assert(!MO.getSubReg() && "Subregs should be eliminated!");
00113     if(ARM::GPRPairRegClass.contains(Reg)) {
00114       const MachineFunction &MF = *MI->getParent()->getParent();
00115       const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
00116       Reg = TRI->getSubReg(Reg, ARM::gsub_0);
00117     }
00118     O << ARMInstPrinter::getRegisterName(Reg);
00119     break;
00120   }
00121   case MachineOperand::MO_Immediate: {
00122     int64_t Imm = MO.getImm();
00123     O << '#';
00124     if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
00125         (TF == ARMII::MO_LO16))
00126       O << ":lower16:";
00127     else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
00128              (TF == ARMII::MO_HI16))
00129       O << ":upper16:";
00130     O << Imm;
00131     break;
00132   }
00133   case MachineOperand::MO_MachineBasicBlock:
00134     O << *MO.getMBB()->getSymbol();
00135     return;
00136   case MachineOperand::MO_GlobalAddress: {
00137     const GlobalValue *GV = MO.getGlobal();
00138     if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
00139         (TF & ARMII::MO_LO16))
00140       O << ":lower16:";
00141     else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
00142              (TF & ARMII::MO_HI16))
00143       O << ":upper16:";
00144     O << *getSymbol(GV);
00145 
00146     printOffset(MO.getOffset(), O);
00147     if (TF == ARMII::MO_PLT)
00148       O << "(PLT)";
00149     break;
00150   }
00151   case MachineOperand::MO_ConstantPoolIndex:
00152     O << *GetCPISymbol(MO.getIndex());
00153     break;
00154   }
00155 }
00156 
00157 //===--------------------------------------------------------------------===//
00158 
00159 MCSymbol *ARMAsmPrinter::
00160 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
00161   const DataLayout *DL = TM.getDataLayout();
00162   SmallString<60> Name;
00163   raw_svector_ostream(Name) << DL->getPrivateGlobalPrefix() << "JTI"
00164     << getFunctionNumber() << '_' << uid << '_' << uid2;
00165   return OutContext.GetOrCreateSymbol(Name.str());
00166 }
00167 
00168 
00169 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel() const {
00170   const DataLayout *DL = TM.getDataLayout();
00171   SmallString<60> Name;
00172   raw_svector_ostream(Name) << DL->getPrivateGlobalPrefix() << "SJLJEH"
00173     << getFunctionNumber();
00174   return OutContext.GetOrCreateSymbol(Name.str());
00175 }
00176 
00177 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
00178                                     unsigned AsmVariant, const char *ExtraCode,
00179                                     raw_ostream &O) {
00180   // Does this asm operand have a single letter operand modifier?
00181   if (ExtraCode && ExtraCode[0]) {
00182     if (ExtraCode[1] != 0) return true; // Unknown modifier.
00183 
00184     switch (ExtraCode[0]) {
00185     default:
00186       // See if this is a generic print operand
00187       return AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O);
00188     case 'a': // Print as a memory address.
00189       if (MI->getOperand(OpNum).isReg()) {
00190         O << "["
00191           << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
00192           << "]";
00193         return false;
00194       }
00195       // Fallthrough
00196     case 'c': // Don't print "#" before an immediate operand.
00197       if (!MI->getOperand(OpNum).isImm())
00198         return true;
00199       O << MI->getOperand(OpNum).getImm();
00200       return false;
00201     case 'P': // Print a VFP double precision register.
00202     case 'q': // Print a NEON quad precision register.
00203       printOperand(MI, OpNum, O);
00204       return false;
00205     case 'y': // Print a VFP single precision register as indexed double.
00206       if (MI->getOperand(OpNum).isReg()) {
00207         unsigned Reg = MI->getOperand(OpNum).getReg();
00208         const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
00209         // Find the 'd' register that has this 's' register as a sub-register,
00210         // and determine the lane number.
00211         for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
00212           if (!ARM::DPRRegClass.contains(*SR))
00213             continue;
00214           bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
00215           O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");
00216           return false;
00217         }
00218       }
00219       return true;
00220     case 'B': // Bitwise inverse of integer or symbol without a preceding #.
00221       if (!MI->getOperand(OpNum).isImm())
00222         return true;
00223       O << ~(MI->getOperand(OpNum).getImm());
00224       return false;
00225     case 'L': // The low 16 bits of an immediate constant.
00226       if (!MI->getOperand(OpNum).isImm())
00227         return true;
00228       O << (MI->getOperand(OpNum).getImm() & 0xffff);
00229       return false;
00230     case 'M': { // A register range suitable for LDM/STM.
00231       if (!MI->getOperand(OpNum).isReg())
00232         return true;
00233       const MachineOperand &MO = MI->getOperand(OpNum);
00234       unsigned RegBegin = MO.getReg();
00235       // This takes advantage of the 2 operand-ness of ldm/stm and that we've
00236       // already got the operands in registers that are operands to the
00237       // inline asm statement.
00238       O << "{";
00239       if (ARM::GPRPairRegClass.contains(RegBegin)) {
00240         const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
00241         unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
00242         O << ARMInstPrinter::getRegisterName(Reg0) << ", ";;
00243         RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1);
00244       }
00245       O << ARMInstPrinter::getRegisterName(RegBegin);
00246 
00247       // FIXME: The register allocator not only may not have given us the
00248       // registers in sequence, but may not be in ascending registers. This
00249       // will require changes in the register allocator that'll need to be
00250       // propagated down here if the operands change.
00251       unsigned RegOps = OpNum + 1;
00252       while (MI->getOperand(RegOps).isReg()) {
00253         O << ", "
00254           << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
00255         RegOps++;
00256       }
00257 
00258       O << "}";
00259 
00260       return false;
00261     }
00262     case 'R': // The most significant register of a pair.
00263     case 'Q': { // The least significant register of a pair.
00264       if (OpNum == 0)
00265         return true;
00266       const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
00267       if (!FlagsOP.isImm())
00268         return true;
00269       unsigned Flags = FlagsOP.getImm();
00270 
00271       // This operand may not be the one that actually provides the register. If
00272       // it's tied to a previous one then we should refer instead to that one
00273       // for registers and their classes.
00274       unsigned TiedIdx;
00275       if (InlineAsm::isUseOperandTiedToDef(Flags, TiedIdx)) {
00276         for (OpNum = InlineAsm::MIOp_FirstOperand; TiedIdx; --TiedIdx) {
00277           unsigned OpFlags = MI->getOperand(OpNum).getImm();
00278           OpNum += InlineAsm::getNumOperandRegisters(OpFlags) + 1;
00279         }
00280         Flags = MI->getOperand(OpNum).getImm();
00281 
00282         // Later code expects OpNum to be pointing at the register rather than
00283         // the flags.
00284         OpNum += 1;
00285       }
00286 
00287       unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
00288       unsigned RC;
00289       InlineAsm::hasRegClassConstraint(Flags, RC);
00290       if (RC == ARM::GPRPairRegClassID) {
00291         if (NumVals != 1)
00292           return true;
00293         const MachineOperand &MO = MI->getOperand(OpNum);
00294         if (!MO.isReg())
00295           return true;
00296         const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
00297         unsigned Reg = TRI->getSubReg(MO.getReg(), ExtraCode[0] == 'Q' ?
00298             ARM::gsub_0 : ARM::gsub_1);
00299         O << ARMInstPrinter::getRegisterName(Reg);
00300         return false;
00301       }
00302       if (NumVals != 2)
00303         return true;
00304       unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
00305       if (RegOp >= MI->getNumOperands())
00306         return true;
00307       const MachineOperand &MO = MI->getOperand(RegOp);
00308       if (!MO.isReg())
00309         return true;
00310       unsigned Reg = MO.getReg();
00311       O << ARMInstPrinter::getRegisterName(Reg);
00312       return false;
00313     }
00314 
00315     case 'e': // The low doubleword register of a NEON quad register.
00316     case 'f': { // The high doubleword register of a NEON quad register.
00317       if (!MI->getOperand(OpNum).isReg())
00318         return true;
00319       unsigned Reg = MI->getOperand(OpNum).getReg();
00320       if (!ARM::QPRRegClass.contains(Reg))
00321         return true;
00322       const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
00323       unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
00324                                        ARM::dsub_0 : ARM::dsub_1);
00325       O << ARMInstPrinter::getRegisterName(SubReg);
00326       return false;
00327     }
00328 
00329     // This modifier is not yet supported.
00330     case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
00331       return true;
00332     case 'H': { // The highest-numbered register of a pair.
00333       const MachineOperand &MO = MI->getOperand(OpNum);
00334       if (!MO.isReg())
00335         return true;
00336       const MachineFunction &MF = *MI->getParent()->getParent();
00337       const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
00338       unsigned Reg = MO.getReg();
00339       if(!ARM::GPRPairRegClass.contains(Reg))
00340         return false;
00341       Reg = TRI->getSubReg(Reg, ARM::gsub_1);
00342       O << ARMInstPrinter::getRegisterName(Reg);
00343       return false;
00344     }
00345     }
00346   }
00347 
00348   printOperand(MI, OpNum, O);
00349   return false;
00350 }
00351 
00352 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
00353                                           unsigned OpNum, unsigned AsmVariant,
00354                                           const char *ExtraCode,
00355                                           raw_ostream &O) {
00356   // Does this asm operand have a single letter operand modifier?
00357   if (ExtraCode && ExtraCode[0]) {
00358     if (ExtraCode[1] != 0) return true; // Unknown modifier.
00359 
00360     switch (ExtraCode[0]) {
00361       case 'A': // A memory operand for a VLD1/VST1 instruction.
00362       default: return true;  // Unknown modifier.
00363       case 'm': // The base register of a memory operand.
00364         if (!MI->getOperand(OpNum).isReg())
00365           return true;
00366         O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
00367         return false;
00368     }
00369   }
00370 
00371   const MachineOperand &MO = MI->getOperand(OpNum);
00372   assert(MO.isReg() && "unexpected inline asm memory operand");
00373   O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
00374   return false;
00375 }
00376 
00377 static bool isThumb(const MCSubtargetInfo& STI) {
00378   return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
00379 }
00380 
00381 void ARMAsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo &StartInfo,
00382                                      const MCSubtargetInfo *EndInfo) const {
00383   // If either end mode is unknown (EndInfo == NULL) or different than
00384   // the start mode, then restore the start mode.
00385   const bool WasThumb = isThumb(StartInfo);
00386   if (EndInfo == NULL || WasThumb != isThumb(*EndInfo)) {
00387     OutStreamer.EmitAssemblerFlag(WasThumb ? MCAF_Code16 : MCAF_Code32);
00388   }
00389 }
00390 
00391 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
00392   if (Subtarget->isTargetMachO()) {
00393     Reloc::Model RelocM = TM.getRelocationModel();
00394     if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
00395       // Declare all the text sections up front (before the DWARF sections
00396       // emitted by AsmPrinter::doInitialization) so the assembler will keep
00397       // them together at the beginning of the object file.  This helps
00398       // avoid out-of-range branches that are due a fundamental limitation of
00399       // the way symbol offsets are encoded with the current Darwin ARM
00400       // relocations.
00401       const TargetLoweringObjectFileMachO &TLOFMacho =
00402         static_cast<const TargetLoweringObjectFileMachO &>(
00403           getObjFileLowering());
00404 
00405       // Collect the set of sections our functions will go into.
00406       SetVector<const MCSection *, SmallVector<const MCSection *, 8>,
00407         SmallPtrSet<const MCSection *, 8> > TextSections;
00408       // Default text section comes first.
00409       TextSections.insert(TLOFMacho.getTextSection());
00410       // Now any user defined text sections from function attributes.
00411       for (Module::iterator F = M.begin(), e = M.end(); F != e; ++F)
00412         if (!F->isDeclaration() && !F->hasAvailableExternallyLinkage())
00413           TextSections.insert(TLOFMacho.SectionForGlobal(F, *Mang, TM));
00414       // Now the coalescable sections.
00415       TextSections.insert(TLOFMacho.getTextCoalSection());
00416       TextSections.insert(TLOFMacho.getConstTextCoalSection());
00417 
00418       // Emit the sections in the .s file header to fix the order.
00419       for (unsigned i = 0, e = TextSections.size(); i != e; ++i)
00420         OutStreamer.SwitchSection(TextSections[i]);
00421 
00422       if (RelocM == Reloc::DynamicNoPIC) {
00423         const MCSection *sect =
00424           OutContext.getMachOSection("__TEXT", "__symbol_stub4",
00425                                      MachO::S_SYMBOL_STUBS,
00426                                      12, SectionKind::getText());
00427         OutStreamer.SwitchSection(sect);
00428       } else {
00429         const MCSection *sect =
00430           OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
00431                                      MachO::S_SYMBOL_STUBS,
00432                                      16, SectionKind::getText());
00433         OutStreamer.SwitchSection(sect);
00434       }
00435       const MCSection *StaticInitSect =
00436         OutContext.getMachOSection("__TEXT", "__StaticInit",
00437                                    MachO::S_REGULAR |
00438                                    MachO::S_ATTR_PURE_INSTRUCTIONS,
00439                                    SectionKind::getText());
00440       OutStreamer.SwitchSection(StaticInitSect);
00441     }
00442 
00443     // Compiling with debug info should not affect the code
00444     // generation.  Ensure the cstring section comes before the
00445     // optional __DWARF secion. Otherwise, PC-relative loads would
00446     // have to use different instruction sequences at "-g" in order to
00447     // reach global data in the same object file.
00448     OutStreamer.SwitchSection(getObjFileLowering().getCStringSection());
00449   }
00450 
00451   // Use unified assembler syntax.
00452   OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
00453 
00454   // Emit ARM Build Attributes
00455   if (Subtarget->isTargetELF())
00456     emitAttributes();
00457 }
00458 
00459 
00460 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
00461   if (Subtarget->isTargetMachO()) {
00462     // All darwin targets use mach-o.
00463     const TargetLoweringObjectFileMachO &TLOFMacho =
00464       static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
00465     MachineModuleInfoMachO &MMIMacho =
00466       MMI->getObjFileInfo<MachineModuleInfoMachO>();
00467 
00468     // Output non-lazy-pointers for external and common global variables.
00469     MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
00470 
00471     if (!Stubs.empty()) {
00472       // Switch with ".non_lazy_symbol_pointer" directive.
00473       OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
00474       EmitAlignment(2);
00475       for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
00476         // L_foo$stub:
00477         OutStreamer.EmitLabel(Stubs[i].first);
00478         //   .indirect_symbol _foo
00479         MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
00480         OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
00481 
00482         if (MCSym.getInt())
00483           // External to current translation unit.
00484           OutStreamer.EmitIntValue(0, 4/*size*/);
00485         else
00486           // Internal to current translation unit.
00487           //
00488           // When we place the LSDA into the TEXT section, the type info
00489           // pointers need to be indirect and pc-rel. We accomplish this by
00490           // using NLPs; however, sometimes the types are local to the file.
00491           // We need to fill in the value for the NLP in those cases.
00492           OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
00493                                                         OutContext),
00494                                 4/*size*/);
00495       }
00496 
00497       Stubs.clear();
00498       OutStreamer.AddBlankLine();
00499     }
00500 
00501     Stubs = MMIMacho.GetHiddenGVStubList();
00502     if (!Stubs.empty()) {
00503       OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
00504       EmitAlignment(2);
00505       for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
00506         // L_foo$stub:
00507         OutStreamer.EmitLabel(Stubs[i].first);
00508         //   .long _foo
00509         OutStreamer.EmitValue(MCSymbolRefExpr::
00510                               Create(Stubs[i].second.getPointer(),
00511                                      OutContext),
00512                               4/*size*/);
00513       }
00514 
00515       Stubs.clear();
00516       OutStreamer.AddBlankLine();
00517     }
00518 
00519     // Funny Darwin hack: This flag tells the linker that no global symbols
00520     // contain code that falls through to other global symbols (e.g. the obvious
00521     // implementation of multiple entry points).  If this doesn't occur, the
00522     // linker can safely perform dead code stripping.  Since LLVM never
00523     // generates code that does this, it is always safe to set.
00524     OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
00525   }
00526 }
00527 
00528 //===----------------------------------------------------------------------===//
00529 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
00530 // FIXME:
00531 // The following seem like one-off assembler flags, but they actually need
00532 // to appear in the .ARM.attributes section in ELF.
00533 // Instead of subclassing the MCELFStreamer, we do the work here.
00534 
00535 static ARMBuildAttrs::CPUArch getArchForCPU(StringRef CPU,
00536                                             const ARMSubtarget *Subtarget) {
00537   if (CPU == "xscale")
00538     return ARMBuildAttrs::v5TEJ;
00539 
00540   if (Subtarget->hasV8Ops())
00541     return ARMBuildAttrs::v8;
00542   else if (Subtarget->hasV7Ops()) {
00543     if (Subtarget->isMClass() && Subtarget->hasThumb2DSP())
00544       return ARMBuildAttrs::v7E_M;
00545     return ARMBuildAttrs::v7;
00546   } else if (Subtarget->hasV6T2Ops())
00547     return ARMBuildAttrs::v6T2;
00548   else if (Subtarget->hasV6MOps())
00549     return ARMBuildAttrs::v6S_M;
00550   else if (Subtarget->hasV6Ops())
00551     return ARMBuildAttrs::v6;
00552   else if (Subtarget->hasV5TEOps())
00553     return ARMBuildAttrs::v5TE;
00554   else if (Subtarget->hasV5TOps())
00555     return ARMBuildAttrs::v5T;
00556   else if (Subtarget->hasV4TOps())
00557     return ARMBuildAttrs::v4T;
00558   else
00559     return ARMBuildAttrs::v4;
00560 }
00561 
00562 void ARMAsmPrinter::emitAttributes() {
00563   MCTargetStreamer &TS = *OutStreamer.getTargetStreamer();
00564   ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
00565 
00566   ATS.switchVendor("aeabi");
00567 
00568   std::string CPUString = Subtarget->getCPUString();
00569 
00570   // FIXME: remove krait check when GNU tools support krait cpu
00571   if (CPUString != "generic" && CPUString != "krait")
00572     ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, CPUString);
00573 
00574   ATS.emitAttribute(ARMBuildAttrs::CPU_arch,
00575                     getArchForCPU(CPUString, Subtarget));
00576 
00577   // Tag_CPU_arch_profile must have the default value of 0 when "Architecture
00578   // profile is not applicable (e.g. pre v7, or cross-profile code)".
00579   if (Subtarget->hasV7Ops()) {
00580     if (Subtarget->isAClass()) {
00581       ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
00582                         ARMBuildAttrs::ApplicationProfile);
00583     } else if (Subtarget->isRClass()) {
00584       ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
00585                         ARMBuildAttrs::RealTimeProfile);
00586     } else if (Subtarget->isMClass()) {
00587       ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
00588                         ARMBuildAttrs::MicroControllerProfile);
00589     }
00590   }
00591 
00592   ATS.emitAttribute(ARMBuildAttrs::ARM_ISA_use, Subtarget->hasARMOps() ?
00593                       ARMBuildAttrs::Allowed : ARMBuildAttrs::Not_Allowed);
00594   if (Subtarget->isThumb1Only()) {
00595     ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
00596                       ARMBuildAttrs::Allowed);
00597   } else if (Subtarget->hasThumb2()) {
00598     ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
00599                       ARMBuildAttrs::AllowThumb32);
00600   }
00601 
00602   if (Subtarget->hasNEON()) {
00603     /* NEON is not exactly a VFP architecture, but GAS emit one of
00604      * neon/neon-fp-armv8/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
00605     if (Subtarget->hasFPARMv8()) {
00606       if (Subtarget->hasCrypto())
00607         ATS.emitFPU(ARM::CRYPTO_NEON_FP_ARMV8);
00608       else
00609         ATS.emitFPU(ARM::NEON_FP_ARMV8);
00610     }
00611     else if (Subtarget->hasVFP4())
00612       ATS.emitFPU(ARM::NEON_VFPV4);
00613     else
00614       ATS.emitFPU(ARM::NEON);
00615     // Emit Tag_Advanced_SIMD_arch for ARMv8 architecture
00616     if (Subtarget->hasV8Ops())
00617       ATS.emitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
00618                         ARMBuildAttrs::AllowNeonARMv8);
00619   } else {
00620     if (Subtarget->hasFPARMv8())
00621       ATS.emitFPU(ARM::FP_ARMV8);
00622     else if (Subtarget->hasVFP4())
00623       ATS.emitFPU(Subtarget->hasD16() ? ARM::VFPV4_D16 : ARM::VFPV4);
00624     else if (Subtarget->hasVFP3())
00625       ATS.emitFPU(Subtarget->hasD16() ? ARM::VFPV3_D16 : ARM::VFPV3);
00626     else if (Subtarget->hasVFP2())
00627       ATS.emitFPU(ARM::VFPV2);
00628   }
00629 
00630   // Signal various FP modes.
00631   if (!TM.Options.UnsafeFPMath) {
00632     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal, ARMBuildAttrs::Allowed);
00633     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
00634                       ARMBuildAttrs::Allowed);
00635   }
00636 
00637   if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
00638     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
00639                       ARMBuildAttrs::Allowed);
00640   else
00641     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
00642                       ARMBuildAttrs::AllowIEE754);
00643 
00644   // FIXME: add more flags to ARMBuildAttributes.h
00645   // 8-bytes alignment stuff.
00646   ATS.emitAttribute(ARMBuildAttrs::ABI_align_needed, 1);
00647   ATS.emitAttribute(ARMBuildAttrs::ABI_align_preserved, 1);
00648 
00649   // ABI_HardFP_use attribute to indicate single precision FP.
00650   if (Subtarget->isFPOnlySP())
00651     ATS.emitAttribute(ARMBuildAttrs::ABI_HardFP_use,
00652                       ARMBuildAttrs::HardFPSinglePrecision);
00653 
00654   // Hard float.  Use both S and D registers and conform to AAPCS-VFP.
00655   if (Subtarget->isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard)
00656     ATS.emitAttribute(ARMBuildAttrs::ABI_VFP_args, ARMBuildAttrs::HardFPAAPCS);
00657 
00658   // FIXME: Should we signal R9 usage?
00659 
00660   if (Subtarget->hasFP16())
00661       ATS.emitAttribute(ARMBuildAttrs::FP_HP_extension, ARMBuildAttrs::AllowHPFP);
00662 
00663   if (Subtarget->hasMPExtension())
00664       ATS.emitAttribute(ARMBuildAttrs::MPextension_use, ARMBuildAttrs::AllowMP);
00665 
00666   // Hardware divide in ARM mode is part of base arch, starting from ARMv8.
00667   // If only Thumb hwdiv is present, it must also be in base arch (ARMv7-R/M).
00668   // It is not possible to produce DisallowDIV: if hwdiv is present in the base
00669   // arch, supplying -hwdiv downgrades the effective arch, via ClearImpliedBits.
00670   // AllowDIVExt is only emitted if hwdiv isn't available in the base arch;
00671   // otherwise, the default value (AllowDIVIfExists) applies.
00672   if (Subtarget->hasDivideInARMMode() && !Subtarget->hasV8Ops())
00673       ATS.emitAttribute(ARMBuildAttrs::DIV_use, ARMBuildAttrs::AllowDIVExt);
00674 
00675   if (Subtarget->hasTrustZone() && Subtarget->hasVirtualization())
00676       ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
00677                         ARMBuildAttrs::AllowTZVirtualization);
00678   else if (Subtarget->hasTrustZone())
00679       ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
00680                         ARMBuildAttrs::AllowTZ);
00681   else if (Subtarget->hasVirtualization())
00682       ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
00683                         ARMBuildAttrs::AllowVirtualization);
00684 
00685   ATS.finishAttributeSection();
00686 }
00687 
00688 //===----------------------------------------------------------------------===//
00689 
00690 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
00691                              unsigned LabelId, MCContext &Ctx) {
00692 
00693   MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
00694                        + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
00695   return Label;
00696 }
00697 
00698 static MCSymbolRefExpr::VariantKind
00699 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
00700   switch (Modifier) {
00701   case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
00702   case ARMCP::TLSGD:       return MCSymbolRefExpr::VK_TLSGD;
00703   case ARMCP::TPOFF:       return MCSymbolRefExpr::VK_TPOFF;
00704   case ARMCP::GOTTPOFF:    return MCSymbolRefExpr::VK_GOTTPOFF;
00705   case ARMCP::GOT:         return MCSymbolRefExpr::VK_GOT;
00706   case ARMCP::GOTOFF:      return MCSymbolRefExpr::VK_GOTOFF;
00707   }
00708   llvm_unreachable("Invalid ARMCPModifier!");
00709 }
00710 
00711 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV,
00712                                         unsigned char TargetFlags) {
00713   bool isIndirect = Subtarget->isTargetMachO() &&
00714     (TargetFlags & ARMII::MO_NONLAZY) &&
00715     Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
00716   if (!isIndirect)
00717     return getSymbol(GV);
00718 
00719   // FIXME: Remove this when Darwin transition to @GOT like syntax.
00720   MCSymbol *MCSym = getSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
00721   MachineModuleInfoMachO &MMIMachO =
00722     MMI->getObjFileInfo<MachineModuleInfoMachO>();
00723   MachineModuleInfoImpl::StubValueTy &StubSym =
00724     GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym) :
00725     MMIMachO.getGVStubEntry(MCSym);
00726   if (StubSym.getPointer() == 0)
00727     StubSym = MachineModuleInfoImpl::
00728       StubValueTy(getSymbol(GV), !GV->hasInternalLinkage());
00729   return MCSym;
00730 }
00731 
00732 void ARMAsmPrinter::
00733 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
00734   const DataLayout *DL = TM.getDataLayout();
00735   int Size = TM.getDataLayout()->getTypeAllocSize(MCPV->getType());
00736 
00737   ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
00738 
00739   MCSymbol *MCSym;
00740   if (ACPV->isLSDA()) {
00741     SmallString<128> Str;
00742     raw_svector_ostream OS(Str);
00743     OS << DL->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
00744     MCSym = OutContext.GetOrCreateSymbol(OS.str());
00745   } else if (ACPV->isBlockAddress()) {
00746     const BlockAddress *BA =
00747       cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
00748     MCSym = GetBlockAddressSymbol(BA);
00749   } else if (ACPV->isGlobalValue()) {
00750     const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
00751 
00752     // On Darwin, const-pool entries may get the "FOO$non_lazy_ptr" mangling, so
00753     // flag the global as MO_NONLAZY.
00754     unsigned char TF = Subtarget->isTargetMachO() ? ARMII::MO_NONLAZY : 0;
00755     MCSym = GetARMGVSymbol(GV, TF);
00756   } else if (ACPV->isMachineBasicBlock()) {
00757     const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
00758     MCSym = MBB->getSymbol();
00759   } else {
00760     assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
00761     const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
00762     MCSym = GetExternalSymbolSymbol(Sym);
00763   }
00764 
00765   // Create an MCSymbol for the reference.
00766   const MCExpr *Expr =
00767     MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
00768                             OutContext);
00769 
00770   if (ACPV->getPCAdjustment()) {
00771     MCSymbol *PCLabel = getPICLabel(DL->getPrivateGlobalPrefix(),
00772                                     getFunctionNumber(),
00773                                     ACPV->getLabelId(),
00774                                     OutContext);
00775     const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
00776     PCRelExpr =
00777       MCBinaryExpr::CreateAdd(PCRelExpr,
00778                               MCConstantExpr::Create(ACPV->getPCAdjustment(),
00779                                                      OutContext),
00780                               OutContext);
00781     if (ACPV->mustAddCurrentAddress()) {
00782       // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
00783       // label, so just emit a local label end reference that instead.
00784       MCSymbol *DotSym = OutContext.CreateTempSymbol();
00785       OutStreamer.EmitLabel(DotSym);
00786       const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
00787       PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
00788     }
00789     Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
00790   }
00791   OutStreamer.EmitValue(Expr, Size);
00792 }
00793 
00794 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
00795   unsigned Opcode = MI->getOpcode();
00796   int OpNum = 1;
00797   if (Opcode == ARM::BR_JTadd)
00798     OpNum = 2;
00799   else if (Opcode == ARM::BR_JTm)
00800     OpNum = 3;
00801 
00802   const MachineOperand &MO1 = MI->getOperand(OpNum);
00803   const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
00804   unsigned JTI = MO1.getIndex();
00805 
00806   // Emit a label for the jump table.
00807   MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
00808   OutStreamer.EmitLabel(JTISymbol);
00809 
00810   // Mark the jump table as data-in-code.
00811   OutStreamer.EmitDataRegion(MCDR_DataRegionJT32);
00812 
00813   // Emit each entry of the table.
00814   const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
00815   const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
00816   const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
00817 
00818   for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
00819     MachineBasicBlock *MBB = JTBBs[i];
00820     // Construct an MCExpr for the entry. We want a value of the form:
00821     // (BasicBlockAddr - TableBeginAddr)
00822     //
00823     // For example, a table with entries jumping to basic blocks BB0 and BB1
00824     // would look like:
00825     // LJTI_0_0:
00826     //    .word (LBB0 - LJTI_0_0)
00827     //    .word (LBB1 - LJTI_0_0)
00828     const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
00829 
00830     if (TM.getRelocationModel() == Reloc::PIC_)
00831       Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
00832                                                                    OutContext),
00833                                      OutContext);
00834     // If we're generating a table of Thumb addresses in static relocation
00835     // model, we need to add one to keep interworking correctly.
00836     else if (AFI->isThumbFunction())
00837       Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(1,OutContext),
00838                                      OutContext);
00839     OutStreamer.EmitValue(Expr, 4);
00840   }
00841   // Mark the end of jump table data-in-code region.
00842   OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
00843 }
00844 
00845 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
00846   unsigned Opcode = MI->getOpcode();
00847   int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
00848   const MachineOperand &MO1 = MI->getOperand(OpNum);
00849   const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
00850   unsigned JTI = MO1.getIndex();
00851 
00852   MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
00853   OutStreamer.EmitLabel(JTISymbol);
00854 
00855   // Emit each entry of the table.
00856   const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
00857   const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
00858   const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
00859   unsigned OffsetWidth = 4;
00860   if (MI->getOpcode() == ARM::t2TBB_JT) {
00861     OffsetWidth = 1;
00862     // Mark the jump table as data-in-code.
00863     OutStreamer.EmitDataRegion(MCDR_DataRegionJT8);
00864   } else if (MI->getOpcode() == ARM::t2TBH_JT) {
00865     OffsetWidth = 2;
00866     // Mark the jump table as data-in-code.
00867     OutStreamer.EmitDataRegion(MCDR_DataRegionJT16);
00868   }
00869 
00870   for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
00871     MachineBasicBlock *MBB = JTBBs[i];
00872     const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
00873                                                       OutContext);
00874     // If this isn't a TBB or TBH, the entries are direct branch instructions.
00875     if (OffsetWidth == 4) {
00876       EmitToStreamer(OutStreamer, MCInstBuilder(ARM::t2B)
00877         .addExpr(MBBSymbolExpr)
00878         .addImm(ARMCC::AL)
00879         .addReg(0));
00880       continue;
00881     }
00882     // Otherwise it's an offset from the dispatch instruction. Construct an
00883     // MCExpr for the entry. We want a value of the form:
00884     // (BasicBlockAddr - TableBeginAddr) / 2
00885     //
00886     // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
00887     // would look like:
00888     // LJTI_0_0:
00889     //    .byte (LBB0 - LJTI_0_0) / 2
00890     //    .byte (LBB1 - LJTI_0_0) / 2
00891     const MCExpr *Expr =
00892       MCBinaryExpr::CreateSub(MBBSymbolExpr,
00893                               MCSymbolRefExpr::Create(JTISymbol, OutContext),
00894                               OutContext);
00895     Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
00896                                    OutContext);
00897     OutStreamer.EmitValue(Expr, OffsetWidth);
00898   }
00899   // Mark the end of jump table data-in-code region. 32-bit offsets use
00900   // actual branch instructions here, so we don't mark those as a data-region
00901   // at all.
00902   if (OffsetWidth != 4)
00903     OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
00904 }
00905 
00906 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
00907   assert(MI->getFlag(MachineInstr::FrameSetup) &&
00908       "Only instruction which are involved into frame setup code are allowed");
00909 
00910   MCTargetStreamer &TS = *OutStreamer.getTargetStreamer();
00911   ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
00912   const MachineFunction &MF = *MI->getParent()->getParent();
00913   const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
00914   const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
00915 
00916   unsigned FramePtr = RegInfo->getFrameRegister(MF);
00917   unsigned Opc = MI->getOpcode();
00918   unsigned SrcReg, DstReg;
00919 
00920   if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
00921     // Two special cases:
00922     // 1) tPUSH does not have src/dst regs.
00923     // 2) for Thumb1 code we sometimes materialize the constant via constpool
00924     // load. Yes, this is pretty fragile, but for now I don't see better
00925     // way... :(
00926     SrcReg = DstReg = ARM::SP;
00927   } else {
00928     SrcReg = MI->getOperand(1).getReg();
00929     DstReg = MI->getOperand(0).getReg();
00930   }
00931 
00932   // Try to figure out the unwinding opcode out of src / dst regs.
00933   if (MI->mayStore()) {
00934     // Register saves.
00935     assert(DstReg == ARM::SP &&
00936            "Only stack pointer as a destination reg is supported");
00937 
00938     SmallVector<unsigned, 4> RegList;
00939     // Skip src & dst reg, and pred ops.
00940     unsigned StartOp = 2 + 2;
00941     // Use all the operands.
00942     unsigned NumOffset = 0;
00943 
00944     switch (Opc) {
00945     default:
00946       MI->dump();
00947       llvm_unreachable("Unsupported opcode for unwinding information");
00948     case ARM::tPUSH:
00949       // Special case here: no src & dst reg, but two extra imp ops.
00950       StartOp = 2; NumOffset = 2;
00951     case ARM::STMDB_UPD:
00952     case ARM::t2STMDB_UPD:
00953     case ARM::VSTMDDB_UPD:
00954       assert(SrcReg == ARM::SP &&
00955              "Only stack pointer as a source reg is supported");
00956       for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
00957            i != NumOps; ++i) {
00958         const MachineOperand &MO = MI->getOperand(i);
00959         // Actually, there should never be any impdef stuff here. Skip it
00960         // temporary to workaround PR11902.
00961         if (MO.isImplicit())
00962           continue;
00963         RegList.push_back(MO.getReg());
00964       }
00965       break;
00966     case ARM::STR_PRE_IMM:
00967     case ARM::STR_PRE_REG:
00968     case ARM::t2STR_PRE:
00969       assert(MI->getOperand(2).getReg() == ARM::SP &&
00970              "Only stack pointer as a source reg is supported");
00971       RegList.push_back(SrcReg);
00972       break;
00973     }
00974     ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
00975   } else {
00976     // Changes of stack / frame pointer.
00977     if (SrcReg == ARM::SP) {
00978       int64_t Offset = 0;
00979       switch (Opc) {
00980       default:
00981         MI->dump();
00982         llvm_unreachable("Unsupported opcode for unwinding information");
00983       case ARM::MOVr:
00984       case ARM::tMOVr:
00985         Offset = 0;
00986         break;
00987       case ARM::ADDri:
00988         Offset = -MI->getOperand(2).getImm();
00989         break;
00990       case ARM::SUBri:
00991       case ARM::t2SUBri:
00992         Offset = MI->getOperand(2).getImm();
00993         break;
00994       case ARM::tSUBspi:
00995         Offset = MI->getOperand(2).getImm()*4;
00996         break;
00997       case ARM::tADDspi:
00998       case ARM::tADDrSPi:
00999         Offset = -MI->getOperand(2).getImm()*4;
01000         break;
01001       case ARM::tLDRpci: {
01002         // Grab the constpool index and check, whether it corresponds to
01003         // original or cloned constpool entry.
01004         unsigned CPI = MI->getOperand(1).getIndex();
01005         const MachineConstantPool *MCP = MF.getConstantPool();
01006         if (CPI >= MCP->getConstants().size())
01007           CPI = AFI.getOriginalCPIdx(CPI);
01008         assert(CPI != -1U && "Invalid constpool index");
01009 
01010         // Derive the actual offset.
01011         const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
01012         assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
01013         // FIXME: Check for user, it should be "add" instruction!
01014         Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
01015         break;
01016       }
01017       }
01018 
01019       if (DstReg == FramePtr && FramePtr != ARM::SP)
01020         // Set-up of the frame pointer. Positive values correspond to "add"
01021         // instruction.
01022         ATS.emitSetFP(FramePtr, ARM::SP, -Offset);
01023       else if (DstReg == ARM::SP) {
01024         // Change of SP by an offset. Positive values correspond to "sub"
01025         // instruction.
01026         ATS.emitPad(Offset);
01027       } else {
01028         // Move of SP to a register.  Positive values correspond to an "add"
01029         // instruction.
01030         ATS.emitMovSP(DstReg, -Offset);
01031       }
01032     } else if (DstReg == ARM::SP) {
01033       MI->dump();
01034       llvm_unreachable("Unsupported opcode for unwinding information");
01035     }
01036     else {
01037       MI->dump();
01038       llvm_unreachable("Unsupported opcode for unwinding information");
01039     }
01040   }
01041 }
01042 
01043 // Simple pseudo-instructions have their lowering (with expansion to real
01044 // instructions) auto-generated.
01045 #include "ARMGenMCPseudoLowering.inc"
01046 
01047 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
01048   const DataLayout *DL = TM.getDataLayout();
01049 
01050   // If we just ended a constant pool, mark it as such.
01051   if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
01052     OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
01053     InConstantPool = false;
01054   }
01055 
01056   // Emit unwinding stuff for frame-related instructions
01057   if (Subtarget->isTargetEHABICompatible() &&
01058        MI->getFlag(MachineInstr::FrameSetup))
01059     EmitUnwindingInstruction(MI);
01060 
01061   // Do any auto-generated pseudo lowerings.
01062   if (emitPseudoExpansionLowering(OutStreamer, MI))
01063     return;
01064 
01065   assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
01066          "Pseudo flag setting opcode should be expanded early");
01067 
01068   // Check for manual lowerings.
01069   unsigned Opc = MI->getOpcode();
01070   switch (Opc) {
01071   case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
01072   case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing");
01073   case ARM::LEApcrel:
01074   case ARM::tLEApcrel:
01075   case ARM::t2LEApcrel: {
01076     // FIXME: Need to also handle globals and externals
01077     MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex());
01078     EmitToStreamer(OutStreamer, MCInstBuilder(MI->getOpcode() ==
01079                                               ARM::t2LEApcrel ? ARM::t2ADR
01080                   : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
01081                      : ARM::ADR))
01082       .addReg(MI->getOperand(0).getReg())
01083       .addExpr(MCSymbolRefExpr::Create(CPISymbol, OutContext))
01084       // Add predicate operands.
01085       .addImm(MI->getOperand(2).getImm())
01086       .addReg(MI->getOperand(3).getReg()));
01087     return;
01088   }
01089   case ARM::LEApcrelJT:
01090   case ARM::tLEApcrelJT:
01091   case ARM::t2LEApcrelJT: {
01092     MCSymbol *JTIPICSymbol =
01093       GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
01094                                   MI->getOperand(2).getImm());
01095     EmitToStreamer(OutStreamer, MCInstBuilder(MI->getOpcode() ==
01096                                               ARM::t2LEApcrelJT ? ARM::t2ADR
01097                   : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
01098                      : ARM::ADR))
01099       .addReg(MI->getOperand(0).getReg())
01100       .addExpr(MCSymbolRefExpr::Create(JTIPICSymbol, OutContext))
01101       // Add predicate operands.
01102       .addImm(MI->getOperand(3).getImm())
01103       .addReg(MI->getOperand(4).getReg()));
01104     return;
01105   }
01106   // Darwin call instructions are just normal call instructions with different
01107   // clobber semantics (they clobber R9).
01108   case ARM::BX_CALL: {
01109     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
01110       .addReg(ARM::LR)
01111       .addReg(ARM::PC)
01112       // Add predicate operands.
01113       .addImm(ARMCC::AL)
01114       .addReg(0)
01115       // Add 's' bit operand (always reg0 for this)
01116       .addReg(0));
01117 
01118     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::BX)
01119       .addReg(MI->getOperand(0).getReg()));
01120     return;
01121   }
01122   case ARM::tBX_CALL: {
01123     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
01124       .addReg(ARM::LR)
01125       .addReg(ARM::PC)
01126       // Add predicate operands.
01127       .addImm(ARMCC::AL)
01128       .addReg(0));
01129 
01130     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tBX)
01131       .addReg(MI->getOperand(0).getReg())
01132       // Add predicate operands.
01133       .addImm(ARMCC::AL)
01134       .addReg(0));
01135     return;
01136   }
01137   case ARM::BMOVPCRX_CALL: {
01138     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
01139       .addReg(ARM::LR)
01140       .addReg(ARM::PC)
01141       // Add predicate operands.
01142       .addImm(ARMCC::AL)
01143       .addReg(0)
01144       // Add 's' bit operand (always reg0 for this)
01145       .addReg(0));
01146 
01147     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
01148       .addReg(ARM::PC)
01149       .addReg(MI->getOperand(0).getReg())
01150       // Add predicate operands.
01151       .addImm(ARMCC::AL)
01152       .addReg(0)
01153       // Add 's' bit operand (always reg0 for this)
01154       .addReg(0));
01155     return;
01156   }
01157   case ARM::BMOVPCB_CALL: {
01158     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
01159       .addReg(ARM::LR)
01160       .addReg(ARM::PC)
01161       // Add predicate operands.
01162       .addImm(ARMCC::AL)
01163       .addReg(0)
01164       // Add 's' bit operand (always reg0 for this)
01165       .addReg(0));
01166 
01167     const GlobalValue *GV = MI->getOperand(0).getGlobal();
01168     MCSymbol *GVSym = getSymbol(GV);
01169     const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
01170     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::Bcc)
01171       .addExpr(GVSymExpr)
01172       // Add predicate operands.
01173       .addImm(ARMCC::AL)
01174       .addReg(0));
01175     return;
01176   }
01177   case ARM::MOVi16_ga_pcrel:
01178   case ARM::t2MOVi16_ga_pcrel: {
01179     MCInst TmpInst;
01180     TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
01181     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
01182 
01183     unsigned TF = MI->getOperand(1).getTargetFlags();
01184     const GlobalValue *GV = MI->getOperand(1).getGlobal();
01185     MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
01186     const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
01187 
01188     MCSymbol *LabelSym = getPICLabel(DL->getPrivateGlobalPrefix(),
01189                                      getFunctionNumber(),
01190                                      MI->getOperand(2).getImm(), OutContext);
01191     const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
01192     unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
01193     const MCExpr *PCRelExpr =
01194       ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
01195                                       MCBinaryExpr::CreateAdd(LabelSymExpr,
01196                                       MCConstantExpr::Create(PCAdj, OutContext),
01197                                       OutContext), OutContext), OutContext);
01198       TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
01199 
01200     // Add predicate operands.
01201     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
01202     TmpInst.addOperand(MCOperand::CreateReg(0));
01203     // Add 's' bit operand (always reg0 for this)
01204     TmpInst.addOperand(MCOperand::CreateReg(0));
01205     EmitToStreamer(OutStreamer, TmpInst);
01206     return;
01207   }
01208   case ARM::MOVTi16_ga_pcrel:
01209   case ARM::t2MOVTi16_ga_pcrel: {
01210     MCInst TmpInst;
01211     TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
01212                       ? ARM::MOVTi16 : ARM::t2MOVTi16);
01213     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
01214     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
01215 
01216     unsigned TF = MI->getOperand(2).getTargetFlags();
01217     const GlobalValue *GV = MI->getOperand(2).getGlobal();
01218     MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
01219     const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
01220 
01221     MCSymbol *LabelSym = getPICLabel(DL->getPrivateGlobalPrefix(),
01222                                      getFunctionNumber(),
01223                                      MI->getOperand(3).getImm(), OutContext);
01224     const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
01225     unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
01226     const MCExpr *PCRelExpr =
01227         ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
01228                                    MCBinaryExpr::CreateAdd(LabelSymExpr,
01229                                       MCConstantExpr::Create(PCAdj, OutContext),
01230                                           OutContext), OutContext), OutContext);
01231       TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
01232     // Add predicate operands.
01233     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
01234     TmpInst.addOperand(MCOperand::CreateReg(0));
01235     // Add 's' bit operand (always reg0 for this)
01236     TmpInst.addOperand(MCOperand::CreateReg(0));
01237     EmitToStreamer(OutStreamer, TmpInst);
01238     return;
01239   }
01240   case ARM::tPICADD: {
01241     // This is a pseudo op for a label + instruction sequence, which looks like:
01242     // LPC0:
01243     //     add r0, pc
01244     // This adds the address of LPC0 to r0.
01245 
01246     // Emit the label.
01247     OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
01248                           getFunctionNumber(), MI->getOperand(2).getImm(),
01249                           OutContext));
01250 
01251     // Form and emit the add.
01252     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tADDhirr)
01253       .addReg(MI->getOperand(0).getReg())
01254       .addReg(MI->getOperand(0).getReg())
01255       .addReg(ARM::PC)
01256       // Add predicate operands.
01257       .addImm(ARMCC::AL)
01258       .addReg(0));
01259     return;
01260   }
01261   case ARM::PICADD: {
01262     // This is a pseudo op for a label + instruction sequence, which looks like:
01263     // LPC0:
01264     //     add r0, pc, r0
01265     // This adds the address of LPC0 to r0.
01266 
01267     // Emit the label.
01268     OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
01269                           getFunctionNumber(), MI->getOperand(2).getImm(),
01270                           OutContext));
01271 
01272     // Form and emit the add.
01273     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDrr)
01274       .addReg(MI->getOperand(0).getReg())
01275       .addReg(ARM::PC)
01276       .addReg(MI->getOperand(1).getReg())
01277       // Add predicate operands.
01278       .addImm(MI->getOperand(3).getImm())
01279       .addReg(MI->getOperand(4).getReg())
01280       // Add 's' bit operand (always reg0 for this)
01281       .addReg(0));
01282     return;
01283   }
01284   case ARM::PICSTR:
01285   case ARM::PICSTRB:
01286   case ARM::PICSTRH:
01287   case ARM::PICLDR:
01288   case ARM::PICLDRB:
01289   case ARM::PICLDRH:
01290   case ARM::PICLDRSB:
01291   case ARM::PICLDRSH: {
01292     // This is a pseudo op for a label + instruction sequence, which looks like:
01293     // LPC0:
01294     //     OP r0, [pc, r0]
01295     // The LCP0 label is referenced by a constant pool entry in order to get
01296     // a PC-relative address at the ldr instruction.
01297 
01298     // Emit the label.
01299     OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
01300                           getFunctionNumber(), MI->getOperand(2).getImm(),
01301                           OutContext));
01302 
01303     // Form and emit the load
01304     unsigned Opcode;
01305     switch (MI->getOpcode()) {
01306     default:
01307       llvm_unreachable("Unexpected opcode!");
01308     case ARM::PICSTR:   Opcode = ARM::STRrs; break;
01309     case ARM::PICSTRB:  Opcode = ARM::STRBrs; break;
01310     case ARM::PICSTRH:  Opcode = ARM::STRH; break;
01311     case ARM::PICLDR:   Opcode = ARM::LDRrs; break;
01312     case ARM::PICLDRB:  Opcode = ARM::LDRBrs; break;
01313     case ARM::PICLDRH:  Opcode = ARM::LDRH; break;
01314     case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
01315     case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
01316     }
01317     EmitToStreamer(OutStreamer, MCInstBuilder(Opcode)
01318       .addReg(MI->getOperand(0).getReg())
01319       .addReg(ARM::PC)
01320       .addReg(MI->getOperand(1).getReg())
01321       .addImm(0)
01322       // Add predicate operands.
01323       .addImm(MI->getOperand(3).getImm())
01324       .addReg(MI->getOperand(4).getReg()));
01325 
01326     return;
01327   }
01328   case ARM::CONSTPOOL_ENTRY: {
01329     /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
01330     /// in the function.  The first operand is the ID# for this instruction, the
01331     /// second is the index into the MachineConstantPool that this is, the third
01332     /// is the size in bytes of this constant pool entry.
01333     /// The required alignment is specified on the basic block holding this MI.
01334     unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
01335     unsigned CPIdx   = (unsigned)MI->getOperand(1).getIndex();
01336 
01337     // If this is the first entry of the pool, mark it.
01338     if (!InConstantPool) {
01339       OutStreamer.EmitDataRegion(MCDR_DataRegion);
01340       InConstantPool = true;
01341     }
01342 
01343     OutStreamer.EmitLabel(GetCPISymbol(LabelId));
01344 
01345     const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
01346     if (MCPE.isMachineConstantPoolEntry())
01347       EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
01348     else
01349       EmitGlobalConstant(MCPE.Val.ConstVal);
01350     return;
01351   }
01352   case ARM::t2BR_JT: {
01353     // Lower and emit the instruction itself, then the jump table following it.
01354     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
01355       .addReg(ARM::PC)
01356       .addReg(MI->getOperand(0).getReg())
01357       // Add predicate operands.
01358       .addImm(ARMCC::AL)
01359       .addReg(0));
01360 
01361     // Output the data for the jump table itself
01362     EmitJump2Table(MI);
01363     return;
01364   }
01365   case ARM::t2TBB_JT: {
01366     // Lower and emit the instruction itself, then the jump table following it.
01367     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::t2TBB)
01368       .addReg(ARM::PC)
01369       .addReg(MI->getOperand(0).getReg())
01370       // Add predicate operands.
01371       .addImm(ARMCC::AL)
01372       .addReg(0));
01373 
01374     // Output the data for the jump table itself
01375     EmitJump2Table(MI);
01376     // Make sure the next instruction is 2-byte aligned.
01377     EmitAlignment(1);
01378     return;
01379   }
01380   case ARM::t2TBH_JT: {
01381     // Lower and emit the instruction itself, then the jump table following it.
01382     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::t2TBH)
01383       .addReg(ARM::PC)
01384       .addReg(MI->getOperand(0).getReg())
01385       // Add predicate operands.
01386       .addImm(ARMCC::AL)
01387       .addReg(0));
01388 
01389     // Output the data for the jump table itself
01390     EmitJump2Table(MI);
01391     return;
01392   }
01393   case ARM::tBR_JTr:
01394   case ARM::BR_JTr: {
01395     // Lower and emit the instruction itself, then the jump table following it.
01396     // mov pc, target
01397     MCInst TmpInst;
01398     unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
01399       ARM::MOVr : ARM::tMOVr;
01400     TmpInst.setOpcode(Opc);
01401     TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
01402     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
01403     // Add predicate operands.
01404     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
01405     TmpInst.addOperand(MCOperand::CreateReg(0));
01406     // Add 's' bit operand (always reg0 for this)
01407     if (Opc == ARM::MOVr)
01408       TmpInst.addOperand(MCOperand::CreateReg(0));
01409     EmitToStreamer(OutStreamer, TmpInst);
01410 
01411     // Make sure the Thumb jump table is 4-byte aligned.
01412     if (Opc == ARM::tMOVr)
01413       EmitAlignment(2);
01414 
01415     // Output the data for the jump table itself
01416     EmitJumpTable(MI);
01417     return;
01418   }
01419   case ARM::BR_JTm: {
01420     // Lower and emit the instruction itself, then the jump table following it.
01421     // ldr pc, target
01422     MCInst TmpInst;
01423     if (MI->getOperand(1).getReg() == 0) {
01424       // literal offset
01425       TmpInst.setOpcode(ARM::LDRi12);
01426       TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
01427       TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
01428       TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
01429     } else {
01430       TmpInst.setOpcode(ARM::LDRrs);
01431       TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
01432       TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
01433       TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
01434       TmpInst.addOperand(MCOperand::CreateImm(0));
01435     }
01436     // Add predicate operands.
01437     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
01438     TmpInst.addOperand(MCOperand::CreateReg(0));
01439     EmitToStreamer(OutStreamer, TmpInst);
01440 
01441     // Output the data for the jump table itself
01442     EmitJumpTable(MI);
01443     return;
01444   }
01445   case ARM::BR_JTadd: {
01446     // Lower and emit the instruction itself, then the jump table following it.
01447     // add pc, target, idx
01448     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDrr)
01449       .addReg(ARM::PC)
01450       .addReg(MI->getOperand(0).getReg())
01451       .addReg(MI->getOperand(1).getReg())
01452       // Add predicate operands.
01453       .addImm(ARMCC::AL)
01454       .addReg(0)
01455       // Add 's' bit operand (always reg0 for this)
01456       .addReg(0));
01457 
01458     // Output the data for the jump table itself
01459     EmitJumpTable(MI);
01460     return;
01461   }
01462   case ARM::TRAP: {
01463     // Non-Darwin binutils don't yet support the "trap" mnemonic.
01464     // FIXME: Remove this special case when they do.
01465     if (!Subtarget->isTargetMachO()) {
01466       //.long 0xe7ffdefe @ trap
01467       uint32_t Val = 0xe7ffdefeUL;
01468       OutStreamer.AddComment("trap");
01469       OutStreamer.EmitIntValue(Val, 4);
01470       return;
01471     }
01472     break;
01473   }
01474   case ARM::TRAPNaCl: {
01475     //.long 0xe7fedef0 @ trap
01476     uint32_t Val = 0xe7fedef0UL;
01477     OutStreamer.AddComment("trap");
01478     OutStreamer.EmitIntValue(Val, 4);
01479     return;
01480   }
01481   case ARM::tTRAP: {
01482     // Non-Darwin binutils don't yet support the "trap" mnemonic.
01483     // FIXME: Remove this special case when they do.
01484     if (!Subtarget->isTargetMachO()) {
01485       //.short 57086 @ trap
01486       uint16_t Val = 0xdefe;
01487       OutStreamer.AddComment("trap");
01488       OutStreamer.EmitIntValue(Val, 2);
01489       return;
01490     }
01491     break;
01492   }
01493   case ARM::t2Int_eh_sjlj_setjmp:
01494   case ARM::t2Int_eh_sjlj_setjmp_nofp:
01495   case ARM::tInt_eh_sjlj_setjmp: {
01496     // Two incoming args: GPR:$src, GPR:$val
01497     // mov $val, pc
01498     // adds $val, #7
01499     // str $val, [$src, #4]
01500     // movs r0, #0
01501     // b 1f
01502     // movs r0, #1
01503     // 1:
01504     unsigned SrcReg = MI->getOperand(0).getReg();
01505     unsigned ValReg = MI->getOperand(1).getReg();
01506     MCSymbol *Label = GetARMSJLJEHLabel();
01507     OutStreamer.AddComment("eh_setjmp begin");
01508     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
01509       .addReg(ValReg)
01510       .addReg(ARM::PC)
01511       // Predicate.
01512       .addImm(ARMCC::AL)
01513       .addReg(0));
01514 
01515     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tADDi3)
01516       .addReg(ValReg)
01517       // 's' bit operand
01518       .addReg(ARM::CPSR)
01519       .addReg(ValReg)
01520       .addImm(7)
01521       // Predicate.
01522       .addImm(ARMCC::AL)
01523       .addReg(0));
01524 
01525     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tSTRi)
01526       .addReg(ValReg)
01527       .addReg(SrcReg)
01528       // The offset immediate is #4. The operand value is scaled by 4 for the
01529       // tSTR instruction.
01530       .addImm(1)
01531       // Predicate.
01532       .addImm(ARMCC::AL)
01533       .addReg(0));
01534 
01535     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVi8)
01536       .addReg(ARM::R0)
01537       .addReg(ARM::CPSR)
01538       .addImm(0)
01539       // Predicate.
01540       .addImm(ARMCC::AL)
01541       .addReg(0));
01542 
01543     const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
01544     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tB)
01545       .addExpr(SymbolExpr)
01546       .addImm(ARMCC::AL)
01547       .addReg(0));
01548 
01549     OutStreamer.AddComment("eh_setjmp end");
01550     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVi8)
01551       .addReg(ARM::R0)
01552       .addReg(ARM::CPSR)
01553       .addImm(1)
01554       // Predicate.
01555       .addImm(ARMCC::AL)
01556       .addReg(0));
01557 
01558     OutStreamer.EmitLabel(Label);
01559     return;
01560   }
01561 
01562   case ARM::Int_eh_sjlj_setjmp_nofp:
01563   case ARM::Int_eh_sjlj_setjmp: {
01564     // Two incoming args: GPR:$src, GPR:$val
01565     // add $val, pc, #8
01566     // str $val, [$src, #+4]
01567     // mov r0, #0
01568     // add pc, pc, #0
01569     // mov r0, #1
01570     unsigned SrcReg = MI->getOperand(0).getReg();
01571     unsigned ValReg = MI->getOperand(1).getReg();
01572 
01573     OutStreamer.AddComment("eh_setjmp begin");
01574     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDri)
01575       .addReg(ValReg)
01576       .addReg(ARM::PC)
01577       .addImm(8)
01578       // Predicate.
01579       .addImm(ARMCC::AL)
01580       .addReg(0)
01581       // 's' bit operand (always reg0 for this).
01582       .addReg(0));
01583 
01584     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::STRi12)
01585       .addReg(ValReg)
01586       .addReg(SrcReg)
01587       .addImm(4)
01588       // Predicate.
01589       .addImm(ARMCC::AL)
01590       .addReg(0));
01591 
01592     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVi)
01593       .addReg(ARM::R0)
01594       .addImm(0)
01595       // Predicate.
01596       .addImm(ARMCC::AL)
01597       .addReg(0)
01598       // 's' bit operand (always reg0 for this).
01599       .addReg(0));
01600 
01601     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDri)
01602       .addReg(ARM::PC)
01603       .addReg(ARM::PC)
01604       .addImm(0)
01605       // Predicate.
01606       .addImm(ARMCC::AL)
01607       .addReg(0)
01608       // 's' bit operand (always reg0 for this).
01609       .addReg(0));
01610 
01611     OutStreamer.AddComment("eh_setjmp end");
01612     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVi)
01613       .addReg(ARM::R0)
01614       .addImm(1)
01615       // Predicate.
01616       .addImm(ARMCC::AL)
01617       .addReg(0)
01618       // 's' bit operand (always reg0 for this).
01619       .addReg(0));
01620     return;
01621   }
01622   case ARM::Int_eh_sjlj_longjmp: {
01623     // ldr sp, [$src, #8]
01624     // ldr $scratch, [$src, #4]
01625     // ldr r7, [$src]
01626     // bx $scratch
01627     unsigned SrcReg = MI->getOperand(0).getReg();
01628     unsigned ScratchReg = MI->getOperand(1).getReg();
01629     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::LDRi12)
01630       .addReg(ARM::SP)
01631       .addReg(SrcReg)
01632       .addImm(8)
01633       // Predicate.
01634       .addImm(ARMCC::AL)
01635       .addReg(0));
01636 
01637     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::LDRi12)
01638       .addReg(ScratchReg)
01639       .addReg(SrcReg)
01640       .addImm(4)
01641       // Predicate.
01642       .addImm(ARMCC::AL)
01643       .addReg(0));
01644 
01645     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::LDRi12)
01646       .addReg(ARM::R7)
01647       .addReg(SrcReg)
01648       .addImm(0)
01649       // Predicate.
01650       .addImm(ARMCC::AL)
01651       .addReg(0));
01652 
01653     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::BX)
01654       .addReg(ScratchReg)
01655       // Predicate.
01656       .addImm(ARMCC::AL)
01657       .addReg(0));
01658     return;
01659   }
01660   case ARM::tInt_eh_sjlj_longjmp: {
01661     // ldr $scratch, [$src, #8]
01662     // mov sp, $scratch
01663     // ldr $scratch, [$src, #4]
01664     // ldr r7, [$src]
01665     // bx $scratch
01666     unsigned SrcReg = MI->getOperand(0).getReg();
01667     unsigned ScratchReg = MI->getOperand(1).getReg();
01668     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tLDRi)
01669       .addReg(ScratchReg)
01670       .addReg(SrcReg)
01671       // The offset immediate is #8. The operand value is scaled by 4 for the
01672       // tLDR instruction.
01673       .addImm(2)
01674       // Predicate.
01675       .addImm(ARMCC::AL)
01676       .addReg(0));
01677 
01678     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
01679       .addReg(ARM::SP)
01680       .addReg(ScratchReg)
01681       // Predicate.
01682       .addImm(ARMCC::AL)
01683       .addReg(0));
01684 
01685     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tLDRi)
01686       .addReg(ScratchReg)
01687       .addReg(SrcReg)
01688       .addImm(1)
01689       // Predicate.
01690       .addImm(ARMCC::AL)
01691       .addReg(0));
01692 
01693     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tLDRi)
01694       .addReg(ARM::R7)
01695       .addReg(SrcReg)
01696       .addImm(0)
01697       // Predicate.
01698       .addImm(ARMCC::AL)
01699       .addReg(0));
01700 
01701     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tBX)
01702       .addReg(ScratchReg)
01703       // Predicate.
01704       .addImm(ARMCC::AL)
01705       .addReg(0));
01706     return;
01707   }
01708   }
01709 
01710   MCInst TmpInst;
01711   LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
01712 
01713   EmitToStreamer(OutStreamer, TmpInst);
01714 }
01715 
01716 //===----------------------------------------------------------------------===//
01717 // Target Registry Stuff
01718 //===----------------------------------------------------------------------===//
01719 
01720 // Force static initialization.
01721 extern "C" void LLVMInitializeARMAsmPrinter() {
01722   RegisterAsmPrinter<ARMAsmPrinter> X(TheARMLETarget);
01723   RegisterAsmPrinter<ARMAsmPrinter> Y(TheARMBETarget);
01724   RegisterAsmPrinter<ARMAsmPrinter> A(TheThumbLETarget);
01725   RegisterAsmPrinter<ARMAsmPrinter> B(TheThumbBETarget);
01726 }