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ARMAsmPrinter.cpp
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00001 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file contains a printer that converts from our internal representation
00011 // of machine-dependent LLVM code to GAS-format ARM assembly language.
00012 //
00013 //===----------------------------------------------------------------------===//
00014 
00015 #include "ARMAsmPrinter.h"
00016 #include "ARM.h"
00017 #include "ARMConstantPoolValue.h"
00018 #include "ARMFPUName.h"
00019 #include "ARMMachineFunctionInfo.h"
00020 #include "ARMTargetMachine.h"
00021 #include "ARMTargetObjectFile.h"
00022 #include "InstPrinter/ARMInstPrinter.h"
00023 #include "MCTargetDesc/ARMAddressingModes.h"
00024 #include "MCTargetDesc/ARMMCExpr.h"
00025 #include "llvm/ADT/SetVector.h"
00026 #include "llvm/ADT/SmallString.h"
00027 #include "llvm/CodeGen/MachineFunctionPass.h"
00028 #include "llvm/CodeGen/MachineJumpTableInfo.h"
00029 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
00030 #include "llvm/IR/Constants.h"
00031 #include "llvm/IR/DataLayout.h"
00032 #include "llvm/IR/DebugInfo.h"
00033 #include "llvm/IR/Mangler.h"
00034 #include "llvm/IR/Module.h"
00035 #include "llvm/IR/Type.h"
00036 #include "llvm/MC/MCAsmInfo.h"
00037 #include "llvm/MC/MCAssembler.h"
00038 #include "llvm/MC/MCContext.h"
00039 #include "llvm/MC/MCELFStreamer.h"
00040 #include "llvm/MC/MCInst.h"
00041 #include "llvm/MC/MCInstBuilder.h"
00042 #include "llvm/MC/MCObjectStreamer.h"
00043 #include "llvm/MC/MCSectionMachO.h"
00044 #include "llvm/MC/MCStreamer.h"
00045 #include "llvm/MC/MCSymbol.h"
00046 #include "llvm/Support/ARMBuildAttributes.h"
00047 #include "llvm/Support/COFF.h"
00048 #include "llvm/Support/CommandLine.h"
00049 #include "llvm/Support/Debug.h"
00050 #include "llvm/Support/ELF.h"
00051 #include "llvm/Support/ErrorHandling.h"
00052 #include "llvm/Support/TargetRegistry.h"
00053 #include "llvm/Support/raw_ostream.h"
00054 #include "llvm/Target/TargetMachine.h"
00055 #include <cctype>
00056 using namespace llvm;
00057 
00058 #define DEBUG_TYPE "asm-printer"
00059 
00060 void ARMAsmPrinter::EmitFunctionBodyEnd() {
00061   // Make sure to terminate any constant pools that were at the end
00062   // of the function.
00063   if (!InConstantPool)
00064     return;
00065   InConstantPool = false;
00066   OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
00067 }
00068 
00069 void ARMAsmPrinter::EmitFunctionEntryLabel() {
00070   if (AFI->isThumbFunction()) {
00071     OutStreamer.EmitAssemblerFlag(MCAF_Code16);
00072     OutStreamer.EmitThumbFunc(CurrentFnSym);
00073   }
00074 
00075   OutStreamer.EmitLabel(CurrentFnSym);
00076 }
00077 
00078 void ARMAsmPrinter::EmitXXStructor(const Constant *CV) {
00079   uint64_t Size = TM.getDataLayout()->getTypeAllocSize(CV->getType());
00080   assert(Size && "C++ constructor pointer had zero size!");
00081 
00082   const GlobalValue *GV = dyn_cast<GlobalValue>(CV->stripPointerCasts());
00083   assert(GV && "C++ constructor pointer was not a GlobalValue!");
00084 
00085   const MCExpr *E = MCSymbolRefExpr::Create(GetARMGVSymbol(GV,
00086                                                            ARMII::MO_NO_FLAG),
00087                                             (Subtarget->isTargetELF()
00088                                              ? MCSymbolRefExpr::VK_ARM_TARGET1
00089                                              : MCSymbolRefExpr::VK_None),
00090                                             OutContext);
00091 
00092   OutStreamer.EmitValue(E, Size);
00093 }
00094 
00095 /// runOnMachineFunction - This uses the EmitInstruction()
00096 /// method to print assembly for each instruction.
00097 ///
00098 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
00099   AFI = MF.getInfo<ARMFunctionInfo>();
00100   MCP = MF.getConstantPool();
00101 
00102   SetupMachineFunction(MF);
00103 
00104   if (Subtarget->isTargetCOFF()) {
00105     bool Internal = MF.getFunction()->hasInternalLinkage();
00106     COFF::SymbolStorageClass Scl = Internal ? COFF::IMAGE_SYM_CLASS_STATIC
00107                                             : COFF::IMAGE_SYM_CLASS_EXTERNAL;
00108     int Type = COFF::IMAGE_SYM_DTYPE_FUNCTION << COFF::SCT_COMPLEX_TYPE_SHIFT;
00109 
00110     OutStreamer.BeginCOFFSymbolDef(CurrentFnSym);
00111     OutStreamer.EmitCOFFSymbolStorageClass(Scl);
00112     OutStreamer.EmitCOFFSymbolType(Type);
00113     OutStreamer.EndCOFFSymbolDef();
00114   }
00115 
00116   // Have common code print out the function header with linkage info etc.
00117   EmitFunctionHeader();
00118 
00119   // Emit the rest of the function body.
00120   EmitFunctionBody();
00121 
00122   // We didn't modify anything.
00123   return false;
00124 }
00125 
00126 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
00127                                  raw_ostream &O, const char *Modifier) {
00128   const MachineOperand &MO = MI->getOperand(OpNum);
00129   unsigned TF = MO.getTargetFlags();
00130 
00131   switch (MO.getType()) {
00132   default: llvm_unreachable("<unknown operand type>");
00133   case MachineOperand::MO_Register: {
00134     unsigned Reg = MO.getReg();
00135     assert(TargetRegisterInfo::isPhysicalRegister(Reg));
00136     assert(!MO.getSubReg() && "Subregs should be eliminated!");
00137     if(ARM::GPRPairRegClass.contains(Reg)) {
00138       const MachineFunction &MF = *MI->getParent()->getParent();
00139       const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
00140       Reg = TRI->getSubReg(Reg, ARM::gsub_0);
00141     }
00142     O << ARMInstPrinter::getRegisterName(Reg);
00143     break;
00144   }
00145   case MachineOperand::MO_Immediate: {
00146     int64_t Imm = MO.getImm();
00147     O << '#';
00148     if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
00149         (TF == ARMII::MO_LO16))
00150       O << ":lower16:";
00151     else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
00152              (TF == ARMII::MO_HI16))
00153       O << ":upper16:";
00154     O << Imm;
00155     break;
00156   }
00157   case MachineOperand::MO_MachineBasicBlock:
00158     O << *MO.getMBB()->getSymbol();
00159     return;
00160   case MachineOperand::MO_GlobalAddress: {
00161     const GlobalValue *GV = MO.getGlobal();
00162     if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
00163         (TF & ARMII::MO_LO16))
00164       O << ":lower16:";
00165     else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
00166              (TF & ARMII::MO_HI16))
00167       O << ":upper16:";
00168     O << *GetARMGVSymbol(GV, TF);
00169 
00170     printOffset(MO.getOffset(), O);
00171     if (TF == ARMII::MO_PLT)
00172       O << "(PLT)";
00173     break;
00174   }
00175   case MachineOperand::MO_ConstantPoolIndex:
00176     O << *GetCPISymbol(MO.getIndex());
00177     break;
00178   }
00179 }
00180 
00181 //===--------------------------------------------------------------------===//
00182 
00183 MCSymbol *ARMAsmPrinter::
00184 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
00185   const DataLayout *DL = TM.getDataLayout();
00186   SmallString<60> Name;
00187   raw_svector_ostream(Name) << DL->getPrivateGlobalPrefix() << "JTI"
00188     << getFunctionNumber() << '_' << uid << '_' << uid2;
00189   return OutContext.GetOrCreateSymbol(Name.str());
00190 }
00191 
00192 
00193 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel() const {
00194   const DataLayout *DL = TM.getDataLayout();
00195   SmallString<60> Name;
00196   raw_svector_ostream(Name) << DL->getPrivateGlobalPrefix() << "SJLJEH"
00197     << getFunctionNumber();
00198   return OutContext.GetOrCreateSymbol(Name.str());
00199 }
00200 
00201 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
00202                                     unsigned AsmVariant, const char *ExtraCode,
00203                                     raw_ostream &O) {
00204   // Does this asm operand have a single letter operand modifier?
00205   if (ExtraCode && ExtraCode[0]) {
00206     if (ExtraCode[1] != 0) return true; // Unknown modifier.
00207 
00208     switch (ExtraCode[0]) {
00209     default:
00210       // See if this is a generic print operand
00211       return AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O);
00212     case 'a': // Print as a memory address.
00213       if (MI->getOperand(OpNum).isReg()) {
00214         O << "["
00215           << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
00216           << "]";
00217         return false;
00218       }
00219       // Fallthrough
00220     case 'c': // Don't print "#" before an immediate operand.
00221       if (!MI->getOperand(OpNum).isImm())
00222         return true;
00223       O << MI->getOperand(OpNum).getImm();
00224       return false;
00225     case 'P': // Print a VFP double precision register.
00226     case 'q': // Print a NEON quad precision register.
00227       printOperand(MI, OpNum, O);
00228       return false;
00229     case 'y': // Print a VFP single precision register as indexed double.
00230       if (MI->getOperand(OpNum).isReg()) {
00231         unsigned Reg = MI->getOperand(OpNum).getReg();
00232         const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
00233         // Find the 'd' register that has this 's' register as a sub-register,
00234         // and determine the lane number.
00235         for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
00236           if (!ARM::DPRRegClass.contains(*SR))
00237             continue;
00238           bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
00239           O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");
00240           return false;
00241         }
00242       }
00243       return true;
00244     case 'B': // Bitwise inverse of integer or symbol without a preceding #.
00245       if (!MI->getOperand(OpNum).isImm())
00246         return true;
00247       O << ~(MI->getOperand(OpNum).getImm());
00248       return false;
00249     case 'L': // The low 16 bits of an immediate constant.
00250       if (!MI->getOperand(OpNum).isImm())
00251         return true;
00252       O << (MI->getOperand(OpNum).getImm() & 0xffff);
00253       return false;
00254     case 'M': { // A register range suitable for LDM/STM.
00255       if (!MI->getOperand(OpNum).isReg())
00256         return true;
00257       const MachineOperand &MO = MI->getOperand(OpNum);
00258       unsigned RegBegin = MO.getReg();
00259       // This takes advantage of the 2 operand-ness of ldm/stm and that we've
00260       // already got the operands in registers that are operands to the
00261       // inline asm statement.
00262       O << "{";
00263       if (ARM::GPRPairRegClass.contains(RegBegin)) {
00264         const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
00265         unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
00266         O << ARMInstPrinter::getRegisterName(Reg0) << ", ";
00267         RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1);
00268       }
00269       O << ARMInstPrinter::getRegisterName(RegBegin);
00270 
00271       // FIXME: The register allocator not only may not have given us the
00272       // registers in sequence, but may not be in ascending registers. This
00273       // will require changes in the register allocator that'll need to be
00274       // propagated down here if the operands change.
00275       unsigned RegOps = OpNum + 1;
00276       while (MI->getOperand(RegOps).isReg()) {
00277         O << ", "
00278           << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
00279         RegOps++;
00280       }
00281 
00282       O << "}";
00283 
00284       return false;
00285     }
00286     case 'R': // The most significant register of a pair.
00287     case 'Q': { // The least significant register of a pair.
00288       if (OpNum == 0)
00289         return true;
00290       const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
00291       if (!FlagsOP.isImm())
00292         return true;
00293       unsigned Flags = FlagsOP.getImm();
00294 
00295       // This operand may not be the one that actually provides the register. If
00296       // it's tied to a previous one then we should refer instead to that one
00297       // for registers and their classes.
00298       unsigned TiedIdx;
00299       if (InlineAsm::isUseOperandTiedToDef(Flags, TiedIdx)) {
00300         for (OpNum = InlineAsm::MIOp_FirstOperand; TiedIdx; --TiedIdx) {
00301           unsigned OpFlags = MI->getOperand(OpNum).getImm();
00302           OpNum += InlineAsm::getNumOperandRegisters(OpFlags) + 1;
00303         }
00304         Flags = MI->getOperand(OpNum).getImm();
00305 
00306         // Later code expects OpNum to be pointing at the register rather than
00307         // the flags.
00308         OpNum += 1;
00309       }
00310 
00311       unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
00312       unsigned RC;
00313       InlineAsm::hasRegClassConstraint(Flags, RC);
00314       if (RC == ARM::GPRPairRegClassID) {
00315         if (NumVals != 1)
00316           return true;
00317         const MachineOperand &MO = MI->getOperand(OpNum);
00318         if (!MO.isReg())
00319           return true;
00320         const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
00321         unsigned Reg = TRI->getSubReg(MO.getReg(), ExtraCode[0] == 'Q' ?
00322             ARM::gsub_0 : ARM::gsub_1);
00323         O << ARMInstPrinter::getRegisterName(Reg);
00324         return false;
00325       }
00326       if (NumVals != 2)
00327         return true;
00328       unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
00329       if (RegOp >= MI->getNumOperands())
00330         return true;
00331       const MachineOperand &MO = MI->getOperand(RegOp);
00332       if (!MO.isReg())
00333         return true;
00334       unsigned Reg = MO.getReg();
00335       O << ARMInstPrinter::getRegisterName(Reg);
00336       return false;
00337     }
00338 
00339     case 'e': // The low doubleword register of a NEON quad register.
00340     case 'f': { // The high doubleword register of a NEON quad register.
00341       if (!MI->getOperand(OpNum).isReg())
00342         return true;
00343       unsigned Reg = MI->getOperand(OpNum).getReg();
00344       if (!ARM::QPRRegClass.contains(Reg))
00345         return true;
00346       const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
00347       unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
00348                                        ARM::dsub_0 : ARM::dsub_1);
00349       O << ARMInstPrinter::getRegisterName(SubReg);
00350       return false;
00351     }
00352 
00353     // This modifier is not yet supported.
00354     case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
00355       return true;
00356     case 'H': { // The highest-numbered register of a pair.
00357       const MachineOperand &MO = MI->getOperand(OpNum);
00358       if (!MO.isReg())
00359         return true;
00360       const MachineFunction &MF = *MI->getParent()->getParent();
00361       const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
00362       unsigned Reg = MO.getReg();
00363       if(!ARM::GPRPairRegClass.contains(Reg))
00364         return false;
00365       Reg = TRI->getSubReg(Reg, ARM::gsub_1);
00366       O << ARMInstPrinter::getRegisterName(Reg);
00367       return false;
00368     }
00369     }
00370   }
00371 
00372   printOperand(MI, OpNum, O);
00373   return false;
00374 }
00375 
00376 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
00377                                           unsigned OpNum, unsigned AsmVariant,
00378                                           const char *ExtraCode,
00379                                           raw_ostream &O) {
00380   // Does this asm operand have a single letter operand modifier?
00381   if (ExtraCode && ExtraCode[0]) {
00382     if (ExtraCode[1] != 0) return true; // Unknown modifier.
00383 
00384     switch (ExtraCode[0]) {
00385       case 'A': // A memory operand for a VLD1/VST1 instruction.
00386       default: return true;  // Unknown modifier.
00387       case 'm': // The base register of a memory operand.
00388         if (!MI->getOperand(OpNum).isReg())
00389           return true;
00390         O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
00391         return false;
00392     }
00393   }
00394 
00395   const MachineOperand &MO = MI->getOperand(OpNum);
00396   assert(MO.isReg() && "unexpected inline asm memory operand");
00397   O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
00398   return false;
00399 }
00400 
00401 static bool isThumb(const MCSubtargetInfo& STI) {
00402   return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
00403 }
00404 
00405 void ARMAsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo &StartInfo,
00406                                      const MCSubtargetInfo *EndInfo) const {
00407   // If either end mode is unknown (EndInfo == NULL) or different than
00408   // the start mode, then restore the start mode.
00409   const bool WasThumb = isThumb(StartInfo);
00410   if (!EndInfo || WasThumb != isThumb(*EndInfo)) {
00411     OutStreamer.EmitAssemblerFlag(WasThumb ? MCAF_Code16 : MCAF_Code32);
00412   }
00413 }
00414 
00415 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
00416   if (Subtarget->isTargetMachO()) {
00417     Reloc::Model RelocM = TM.getRelocationModel();
00418     if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
00419       // Declare all the text sections up front (before the DWARF sections
00420       // emitted by AsmPrinter::doInitialization) so the assembler will keep
00421       // them together at the beginning of the object file.  This helps
00422       // avoid out-of-range branches that are due a fundamental limitation of
00423       // the way symbol offsets are encoded with the current Darwin ARM
00424       // relocations.
00425       const TargetLoweringObjectFileMachO &TLOFMacho =
00426         static_cast<const TargetLoweringObjectFileMachO &>(
00427           getObjFileLowering());
00428 
00429       // Collect the set of sections our functions will go into.
00430       SetVector<const MCSection *, SmallVector<const MCSection *, 8>,
00431         SmallPtrSet<const MCSection *, 8> > TextSections;
00432       // Default text section comes first.
00433       TextSections.insert(TLOFMacho.getTextSection());
00434       // Now any user defined text sections from function attributes.
00435       for (Module::iterator F = M.begin(), e = M.end(); F != e; ++F)
00436         if (!F->isDeclaration() && !F->hasAvailableExternallyLinkage())
00437           TextSections.insert(TLOFMacho.SectionForGlobal(F, *Mang, TM));
00438       // Now the coalescable sections.
00439       TextSections.insert(TLOFMacho.getTextCoalSection());
00440       TextSections.insert(TLOFMacho.getConstTextCoalSection());
00441 
00442       // Emit the sections in the .s file header to fix the order.
00443       for (unsigned i = 0, e = TextSections.size(); i != e; ++i)
00444         OutStreamer.SwitchSection(TextSections[i]);
00445 
00446       if (RelocM == Reloc::DynamicNoPIC) {
00447         const MCSection *sect =
00448           OutContext.getMachOSection("__TEXT", "__symbol_stub4",
00449                                      MachO::S_SYMBOL_STUBS,
00450                                      12, SectionKind::getText());
00451         OutStreamer.SwitchSection(sect);
00452       } else {
00453         const MCSection *sect =
00454           OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
00455                                      MachO::S_SYMBOL_STUBS,
00456                                      16, SectionKind::getText());
00457         OutStreamer.SwitchSection(sect);
00458       }
00459       const MCSection *StaticInitSect =
00460         OutContext.getMachOSection("__TEXT", "__StaticInit",
00461                                    MachO::S_REGULAR |
00462                                    MachO::S_ATTR_PURE_INSTRUCTIONS,
00463                                    SectionKind::getText());
00464       OutStreamer.SwitchSection(StaticInitSect);
00465     }
00466 
00467     // Compiling with debug info should not affect the code
00468     // generation.  Ensure the cstring section comes before the
00469     // optional __DWARF secion. Otherwise, PC-relative loads would
00470     // have to use different instruction sequences at "-g" in order to
00471     // reach global data in the same object file.
00472     OutStreamer.SwitchSection(getObjFileLowering().getCStringSection());
00473   }
00474 
00475   // Use unified assembler syntax.
00476   OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
00477 
00478   // Emit ARM Build Attributes
00479   if (Subtarget->isTargetELF())
00480     emitAttributes();
00481 
00482   if (!M.getModuleInlineAsm().empty() && Subtarget->isThumb())
00483     OutStreamer.EmitAssemblerFlag(MCAF_Code16);
00484 }
00485 
00486 static void
00487 emitNonLazySymbolPointer(MCStreamer &OutStreamer, MCSymbol *StubLabel,
00488                          MachineModuleInfoImpl::StubValueTy &MCSym) {
00489   // L_foo$stub:
00490   OutStreamer.EmitLabel(StubLabel);
00491   //   .indirect_symbol _foo
00492   OutStreamer.EmitSymbolAttribute(MCSym.getPointer(), MCSA_IndirectSymbol);
00493 
00494   if (MCSym.getInt())
00495     // External to current translation unit.
00496     OutStreamer.EmitIntValue(0, 4/*size*/);
00497   else
00498     // Internal to current translation unit.
00499     //
00500     // When we place the LSDA into the TEXT section, the type info
00501     // pointers need to be indirect and pc-rel. We accomplish this by
00502     // using NLPs; however, sometimes the types are local to the file.
00503     // We need to fill in the value for the NLP in those cases.
00504     OutStreamer.EmitValue(
00505         MCSymbolRefExpr::Create(MCSym.getPointer(), OutStreamer.getContext()),
00506         4 /*size*/);
00507 }
00508 
00509 
00510 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
00511   if (Subtarget->isTargetMachO()) {
00512     // All darwin targets use mach-o.
00513     const TargetLoweringObjectFileMachO &TLOFMacho =
00514       static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
00515     MachineModuleInfoMachO &MMIMacho =
00516       MMI->getObjFileInfo<MachineModuleInfoMachO>();
00517 
00518     // Output non-lazy-pointers for external and common global variables.
00519     MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
00520 
00521     if (!Stubs.empty()) {
00522       // Switch with ".non_lazy_symbol_pointer" directive.
00523       OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
00524       EmitAlignment(2);
00525 
00526       for (auto &Stub : Stubs)
00527         emitNonLazySymbolPointer(OutStreamer, Stub.first, Stub.second);
00528 
00529       Stubs.clear();
00530       OutStreamer.AddBlankLine();
00531     }
00532 
00533     Stubs = MMIMacho.GetHiddenGVStubList();
00534     if (!Stubs.empty()) {
00535       OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
00536       EmitAlignment(2);
00537 
00538       for (auto &Stub : Stubs)
00539         emitNonLazySymbolPointer(OutStreamer, Stub.first, Stub.second);
00540 
00541       Stubs.clear();
00542       OutStreamer.AddBlankLine();
00543     }
00544 
00545     // Funny Darwin hack: This flag tells the linker that no global symbols
00546     // contain code that falls through to other global symbols (e.g. the obvious
00547     // implementation of multiple entry points).  If this doesn't occur, the
00548     // linker can safely perform dead code stripping.  Since LLVM never
00549     // generates code that does this, it is always safe to set.
00550     OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
00551   }
00552 
00553   // Emit a .data.rel section containing any stubs that were created.
00554   if (Subtarget->isTargetELF()) {
00555     const TargetLoweringObjectFileELF &TLOFELF =
00556       static_cast<const TargetLoweringObjectFileELF &>(getObjFileLowering());
00557 
00558     MachineModuleInfoELF &MMIELF = MMI->getObjFileInfo<MachineModuleInfoELF>();
00559 
00560     // Output stubs for external and common global variables.
00561     MachineModuleInfoELF::SymbolListTy Stubs = MMIELF.GetGVStubList();
00562     if (!Stubs.empty()) {
00563       OutStreamer.SwitchSection(TLOFELF.getDataRelSection());
00564       const DataLayout *TD = TM.getDataLayout();
00565 
00566       for (auto &stub: Stubs) {
00567         OutStreamer.EmitLabel(stub.first);
00568         OutStreamer.EmitSymbolValue(stub.second.getPointer(),
00569                                     TD->getPointerSize(0));
00570       }
00571       Stubs.clear();
00572     }
00573   }
00574 }
00575 
00576 //===----------------------------------------------------------------------===//
00577 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
00578 // FIXME:
00579 // The following seem like one-off assembler flags, but they actually need
00580 // to appear in the .ARM.attributes section in ELF.
00581 // Instead of subclassing the MCELFStreamer, we do the work here.
00582 
00583 static ARMBuildAttrs::CPUArch getArchForCPU(StringRef CPU,
00584                                             const ARMSubtarget *Subtarget) {
00585   if (CPU == "xscale")
00586     return ARMBuildAttrs::v5TEJ;
00587 
00588   if (Subtarget->hasV8Ops())
00589     return ARMBuildAttrs::v8;
00590   else if (Subtarget->hasV7Ops()) {
00591     if (Subtarget->isMClass() && Subtarget->hasThumb2DSP())
00592       return ARMBuildAttrs::v7E_M;
00593     return ARMBuildAttrs::v7;
00594   } else if (Subtarget->hasV6T2Ops())
00595     return ARMBuildAttrs::v6T2;
00596   else if (Subtarget->hasV6MOps())
00597     return ARMBuildAttrs::v6S_M;
00598   else if (Subtarget->hasV6Ops())
00599     return ARMBuildAttrs::v6;
00600   else if (Subtarget->hasV5TEOps())
00601     return ARMBuildAttrs::v5TE;
00602   else if (Subtarget->hasV5TOps())
00603     return ARMBuildAttrs::v5T;
00604   else if (Subtarget->hasV4TOps())
00605     return ARMBuildAttrs::v4T;
00606   else
00607     return ARMBuildAttrs::v4;
00608 }
00609 
00610 void ARMAsmPrinter::emitAttributes() {
00611   MCTargetStreamer &TS = *OutStreamer.getTargetStreamer();
00612   ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
00613 
00614   ATS.switchVendor("aeabi");
00615 
00616   std::string CPUString = Subtarget->getCPUString();
00617 
00618   // FIXME: remove krait check when GNU tools support krait cpu
00619   if (CPUString != "generic" && CPUString != "krait")
00620     ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, CPUString);
00621 
00622   ATS.emitAttribute(ARMBuildAttrs::CPU_arch,
00623                     getArchForCPU(CPUString, Subtarget));
00624 
00625   // Tag_CPU_arch_profile must have the default value of 0 when "Architecture
00626   // profile is not applicable (e.g. pre v7, or cross-profile code)".
00627   if (Subtarget->hasV7Ops()) {
00628     if (Subtarget->isAClass()) {
00629       ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
00630                         ARMBuildAttrs::ApplicationProfile);
00631     } else if (Subtarget->isRClass()) {
00632       ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
00633                         ARMBuildAttrs::RealTimeProfile);
00634     } else if (Subtarget->isMClass()) {
00635       ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
00636                         ARMBuildAttrs::MicroControllerProfile);
00637     }
00638   }
00639 
00640   ATS.emitAttribute(ARMBuildAttrs::ARM_ISA_use, Subtarget->hasARMOps() ?
00641                       ARMBuildAttrs::Allowed : ARMBuildAttrs::Not_Allowed);
00642   if (Subtarget->isThumb1Only()) {
00643     ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
00644                       ARMBuildAttrs::Allowed);
00645   } else if (Subtarget->hasThumb2()) {
00646     ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
00647                       ARMBuildAttrs::AllowThumb32);
00648   }
00649 
00650   if (Subtarget->hasNEON()) {
00651     /* NEON is not exactly a VFP architecture, but GAS emit one of
00652      * neon/neon-fp-armv8/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
00653     if (Subtarget->hasFPARMv8()) {
00654       if (Subtarget->hasCrypto())
00655         ATS.emitFPU(ARM::CRYPTO_NEON_FP_ARMV8);
00656       else
00657         ATS.emitFPU(ARM::NEON_FP_ARMV8);
00658     }
00659     else if (Subtarget->hasVFP4())
00660       ATS.emitFPU(ARM::NEON_VFPV4);
00661     else
00662       ATS.emitFPU(ARM::NEON);
00663     // Emit Tag_Advanced_SIMD_arch for ARMv8 architecture
00664     if (Subtarget->hasV8Ops())
00665       ATS.emitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
00666                         ARMBuildAttrs::AllowNeonARMv8);
00667   } else {
00668     if (Subtarget->hasFPARMv8())
00669       ATS.emitFPU(ARM::FP_ARMV8);
00670     else if (Subtarget->hasVFP4())
00671       ATS.emitFPU(Subtarget->hasD16() ? ARM::VFPV4_D16 : ARM::VFPV4);
00672     else if (Subtarget->hasVFP3())
00673       ATS.emitFPU(Subtarget->hasD16() ? ARM::VFPV3_D16 : ARM::VFPV3);
00674     else if (Subtarget->hasVFP2())
00675       ATS.emitFPU(ARM::VFPV2);
00676   }
00677 
00678   if (TM.getRelocationModel() == Reloc::PIC_) {
00679     // PIC specific attributes.
00680     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RW_data,
00681                       ARMBuildAttrs::AddressRWPCRel);
00682     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RO_data,
00683                       ARMBuildAttrs::AddressROPCRel);
00684     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_GOT_use,
00685                       ARMBuildAttrs::AddressGOT);
00686   } else {
00687     // Allow direct addressing of imported data for all other relocation models.
00688     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_GOT_use,
00689                       ARMBuildAttrs::AddressDirect);
00690   }
00691 
00692   // Signal various FP modes.
00693   if (!TM.Options.UnsafeFPMath) {
00694     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal, ARMBuildAttrs::Allowed);
00695     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
00696                       ARMBuildAttrs::Allowed);
00697   }
00698 
00699   if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
00700     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
00701                       ARMBuildAttrs::Allowed);
00702   else
00703     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
00704                       ARMBuildAttrs::AllowIEE754);
00705 
00706   // FIXME: add more flags to ARMBuildAttributes.h
00707   // 8-bytes alignment stuff.
00708   ATS.emitAttribute(ARMBuildAttrs::ABI_align_needed, 1);
00709   ATS.emitAttribute(ARMBuildAttrs::ABI_align_preserved, 1);
00710 
00711   // ABI_HardFP_use attribute to indicate single precision FP.
00712   if (Subtarget->isFPOnlySP())
00713     ATS.emitAttribute(ARMBuildAttrs::ABI_HardFP_use,
00714                       ARMBuildAttrs::HardFPSinglePrecision);
00715 
00716   // Hard float.  Use both S and D registers and conform to AAPCS-VFP.
00717   if (Subtarget->isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard)
00718     ATS.emitAttribute(ARMBuildAttrs::ABI_VFP_args, ARMBuildAttrs::HardFPAAPCS);
00719 
00720   // FIXME: Should we signal R9 usage?
00721 
00722   if (Subtarget->hasFP16())
00723       ATS.emitAttribute(ARMBuildAttrs::FP_HP_extension, ARMBuildAttrs::AllowHPFP);
00724 
00725   if (Subtarget->hasMPExtension())
00726       ATS.emitAttribute(ARMBuildAttrs::MPextension_use, ARMBuildAttrs::AllowMP);
00727 
00728   // Hardware divide in ARM mode is part of base arch, starting from ARMv8.
00729   // If only Thumb hwdiv is present, it must also be in base arch (ARMv7-R/M).
00730   // It is not possible to produce DisallowDIV: if hwdiv is present in the base
00731   // arch, supplying -hwdiv downgrades the effective arch, via ClearImpliedBits.
00732   // AllowDIVExt is only emitted if hwdiv isn't available in the base arch;
00733   // otherwise, the default value (AllowDIVIfExists) applies.
00734   if (Subtarget->hasDivideInARMMode() && !Subtarget->hasV8Ops())
00735       ATS.emitAttribute(ARMBuildAttrs::DIV_use, ARMBuildAttrs::AllowDIVExt);
00736 
00737   if (MMI) {
00738     if (const Module *SourceModule = MMI->getModule()) {
00739       // ABI_PCS_wchar_t to indicate wchar_t width
00740       // FIXME: There is no way to emit value 0 (wchar_t prohibited).
00741       if (auto WCharWidthValue = cast_or_null<ConstantInt>(
00742               SourceModule->getModuleFlag("wchar_size"))) {
00743         int WCharWidth = WCharWidthValue->getZExtValue();
00744         assert((WCharWidth == 2 || WCharWidth == 4) &&
00745                "wchar_t width must be 2 or 4 bytes");
00746         ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_wchar_t, WCharWidth);
00747       }
00748 
00749       // ABI_enum_size to indicate enum width
00750       // FIXME: There is no way to emit value 0 (enums prohibited) or value 3
00751       //        (all enums contain a value needing 32 bits to encode).
00752       if (auto EnumWidthValue = cast_or_null<ConstantInt>(
00753               SourceModule->getModuleFlag("min_enum_size"))) {
00754         int EnumWidth = EnumWidthValue->getZExtValue();
00755         assert((EnumWidth == 1 || EnumWidth == 4) &&
00756                "Minimum enum width must be 1 or 4 bytes");
00757         int EnumBuildAttr = EnumWidth == 1 ? 1 : 2;
00758         ATS.emitAttribute(ARMBuildAttrs::ABI_enum_size, EnumBuildAttr);
00759       }
00760     }
00761   }
00762 
00763   // TODO: We currently only support either reserving the register, or treating
00764   // it as another callee-saved register, but not as SB or a TLS pointer; It
00765   // would instead be nicer to push this from the frontend as metadata, as we do
00766   // for the wchar and enum size tags
00767   if (Subtarget->isR9Reserved())
00768       ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use,
00769                         ARMBuildAttrs::R9Reserved);
00770   else
00771       ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use,
00772                         ARMBuildAttrs::R9IsGPR);
00773 
00774   if (Subtarget->hasTrustZone() && Subtarget->hasVirtualization())
00775       ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
00776                         ARMBuildAttrs::AllowTZVirtualization);
00777   else if (Subtarget->hasTrustZone())
00778       ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
00779                         ARMBuildAttrs::AllowTZ);
00780   else if (Subtarget->hasVirtualization())
00781       ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
00782                         ARMBuildAttrs::AllowVirtualization);
00783 
00784   ATS.finishAttributeSection();
00785 }
00786 
00787 //===----------------------------------------------------------------------===//
00788 
00789 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
00790                              unsigned LabelId, MCContext &Ctx) {
00791 
00792   MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
00793                        + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
00794   return Label;
00795 }
00796 
00797 static MCSymbolRefExpr::VariantKind
00798 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
00799   switch (Modifier) {
00800   case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
00801   case ARMCP::TLSGD:       return MCSymbolRefExpr::VK_TLSGD;
00802   case ARMCP::TPOFF:       return MCSymbolRefExpr::VK_TPOFF;
00803   case ARMCP::GOTTPOFF:    return MCSymbolRefExpr::VK_GOTTPOFF;
00804   case ARMCP::GOT:         return MCSymbolRefExpr::VK_GOT;
00805   case ARMCP::GOTOFF:      return MCSymbolRefExpr::VK_GOTOFF;
00806   }
00807   llvm_unreachable("Invalid ARMCPModifier!");
00808 }
00809 
00810 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV,
00811                                         unsigned char TargetFlags) {
00812   if (Subtarget->isTargetMachO()) {
00813     bool IsIndirect = (TargetFlags & ARMII::MO_NONLAZY) &&
00814       Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
00815 
00816     if (!IsIndirect)
00817       return getSymbol(GV);
00818 
00819     // FIXME: Remove this when Darwin transition to @GOT like syntax.
00820     MCSymbol *MCSym = getSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
00821     MachineModuleInfoMachO &MMIMachO =
00822       MMI->getObjFileInfo<MachineModuleInfoMachO>();
00823     MachineModuleInfoImpl::StubValueTy &StubSym =
00824       GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym)
00825                                 : MMIMachO.getGVStubEntry(MCSym);
00826     if (!StubSym.getPointer())
00827       StubSym = MachineModuleInfoImpl::StubValueTy(getSymbol(GV),
00828                                                    !GV->hasInternalLinkage());
00829     return MCSym;
00830   } else if (Subtarget->isTargetCOFF()) {
00831     assert(Subtarget->isTargetWindows() &&
00832            "Windows is the only supported COFF target");
00833 
00834     bool IsIndirect = (TargetFlags & ARMII::MO_DLLIMPORT);
00835     if (!IsIndirect)
00836       return getSymbol(GV);
00837 
00838     SmallString<128> Name;
00839     Name = "__imp_";
00840     getNameWithPrefix(Name, GV);
00841 
00842     return OutContext.GetOrCreateSymbol(Name);
00843   } else if (Subtarget->isTargetELF()) {
00844     return getSymbol(GV);
00845   }
00846   llvm_unreachable("unexpected target");
00847 }
00848 
00849 void ARMAsmPrinter::
00850 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
00851   const DataLayout *DL = TM.getDataLayout();
00852   int Size = TM.getDataLayout()->getTypeAllocSize(MCPV->getType());
00853 
00854   ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
00855 
00856   MCSymbol *MCSym;
00857   if (ACPV->isLSDA()) {
00858     SmallString<128> Str;
00859     raw_svector_ostream OS(Str);
00860     OS << DL->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
00861     MCSym = OutContext.GetOrCreateSymbol(OS.str());
00862   } else if (ACPV->isBlockAddress()) {
00863     const BlockAddress *BA =
00864       cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
00865     MCSym = GetBlockAddressSymbol(BA);
00866   } else if (ACPV->isGlobalValue()) {
00867     const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
00868 
00869     // On Darwin, const-pool entries may get the "FOO$non_lazy_ptr" mangling, so
00870     // flag the global as MO_NONLAZY.
00871     unsigned char TF = Subtarget->isTargetMachO() ? ARMII::MO_NONLAZY : 0;
00872     MCSym = GetARMGVSymbol(GV, TF);
00873   } else if (ACPV->isMachineBasicBlock()) {
00874     const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
00875     MCSym = MBB->getSymbol();
00876   } else {
00877     assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
00878     const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
00879     MCSym = GetExternalSymbolSymbol(Sym);
00880   }
00881 
00882   // Create an MCSymbol for the reference.
00883   const MCExpr *Expr =
00884     MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
00885                             OutContext);
00886 
00887   if (ACPV->getPCAdjustment()) {
00888     MCSymbol *PCLabel = getPICLabel(DL->getPrivateGlobalPrefix(),
00889                                     getFunctionNumber(),
00890                                     ACPV->getLabelId(),
00891                                     OutContext);
00892     const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
00893     PCRelExpr =
00894       MCBinaryExpr::CreateAdd(PCRelExpr,
00895                               MCConstantExpr::Create(ACPV->getPCAdjustment(),
00896                                                      OutContext),
00897                               OutContext);
00898     if (ACPV->mustAddCurrentAddress()) {
00899       // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
00900       // label, so just emit a local label end reference that instead.
00901       MCSymbol *DotSym = OutContext.CreateTempSymbol();
00902       OutStreamer.EmitLabel(DotSym);
00903       const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
00904       PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
00905     }
00906     Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
00907   }
00908   OutStreamer.EmitValue(Expr, Size);
00909 }
00910 
00911 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
00912   unsigned Opcode = MI->getOpcode();
00913   int OpNum = 1;
00914   if (Opcode == ARM::BR_JTadd)
00915     OpNum = 2;
00916   else if (Opcode == ARM::BR_JTm)
00917     OpNum = 3;
00918 
00919   const MachineOperand &MO1 = MI->getOperand(OpNum);
00920   const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
00921   unsigned JTI = MO1.getIndex();
00922 
00923   // Emit a label for the jump table.
00924   MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
00925   OutStreamer.EmitLabel(JTISymbol);
00926 
00927   // Mark the jump table as data-in-code.
00928   OutStreamer.EmitDataRegion(MCDR_DataRegionJT32);
00929 
00930   // Emit each entry of the table.
00931   const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
00932   const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
00933   const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
00934 
00935   for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
00936     MachineBasicBlock *MBB = JTBBs[i];
00937     // Construct an MCExpr for the entry. We want a value of the form:
00938     // (BasicBlockAddr - TableBeginAddr)
00939     //
00940     // For example, a table with entries jumping to basic blocks BB0 and BB1
00941     // would look like:
00942     // LJTI_0_0:
00943     //    .word (LBB0 - LJTI_0_0)
00944     //    .word (LBB1 - LJTI_0_0)
00945     const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
00946 
00947     if (TM.getRelocationModel() == Reloc::PIC_)
00948       Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
00949                                                                    OutContext),
00950                                      OutContext);
00951     // If we're generating a table of Thumb addresses in static relocation
00952     // model, we need to add one to keep interworking correctly.
00953     else if (AFI->isThumbFunction())
00954       Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(1,OutContext),
00955                                      OutContext);
00956     OutStreamer.EmitValue(Expr, 4);
00957   }
00958   // Mark the end of jump table data-in-code region.
00959   OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
00960 }
00961 
00962 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
00963   unsigned Opcode = MI->getOpcode();
00964   int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
00965   const MachineOperand &MO1 = MI->getOperand(OpNum);
00966   const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
00967   unsigned JTI = MO1.getIndex();
00968 
00969   MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
00970   OutStreamer.EmitLabel(JTISymbol);
00971 
00972   // Emit each entry of the table.
00973   const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
00974   const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
00975   const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
00976   unsigned OffsetWidth = 4;
00977   if (MI->getOpcode() == ARM::t2TBB_JT) {
00978     OffsetWidth = 1;
00979     // Mark the jump table as data-in-code.
00980     OutStreamer.EmitDataRegion(MCDR_DataRegionJT8);
00981   } else if (MI->getOpcode() == ARM::t2TBH_JT) {
00982     OffsetWidth = 2;
00983     // Mark the jump table as data-in-code.
00984     OutStreamer.EmitDataRegion(MCDR_DataRegionJT16);
00985   }
00986 
00987   for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
00988     MachineBasicBlock *MBB = JTBBs[i];
00989     const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
00990                                                           OutContext);
00991     // If this isn't a TBB or TBH, the entries are direct branch instructions.
00992     if (OffsetWidth == 4) {
00993       EmitToStreamer(OutStreamer, MCInstBuilder(ARM::t2B)
00994         .addExpr(MBBSymbolExpr)
00995         .addImm(ARMCC::AL)
00996         .addReg(0));
00997       continue;
00998     }
00999     // Otherwise it's an offset from the dispatch instruction. Construct an
01000     // MCExpr for the entry. We want a value of the form:
01001     // (BasicBlockAddr - TableBeginAddr) / 2
01002     //
01003     // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
01004     // would look like:
01005     // LJTI_0_0:
01006     //    .byte (LBB0 - LJTI_0_0) / 2
01007     //    .byte (LBB1 - LJTI_0_0) / 2
01008     const MCExpr *Expr =
01009       MCBinaryExpr::CreateSub(MBBSymbolExpr,
01010                               MCSymbolRefExpr::Create(JTISymbol, OutContext),
01011                               OutContext);
01012     Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
01013                                    OutContext);
01014     OutStreamer.EmitValue(Expr, OffsetWidth);
01015   }
01016   // Mark the end of jump table data-in-code region. 32-bit offsets use
01017   // actual branch instructions here, so we don't mark those as a data-region
01018   // at all.
01019   if (OffsetWidth != 4)
01020     OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
01021 }
01022 
01023 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
01024   assert(MI->getFlag(MachineInstr::FrameSetup) &&
01025       "Only instruction which are involved into frame setup code are allowed");
01026 
01027   MCTargetStreamer &TS = *OutStreamer.getTargetStreamer();
01028   ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
01029   const MachineFunction &MF = *MI->getParent()->getParent();
01030   const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
01031   const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
01032 
01033   unsigned FramePtr = RegInfo->getFrameRegister(MF);
01034   unsigned Opc = MI->getOpcode();
01035   unsigned SrcReg, DstReg;
01036 
01037   if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
01038     // Two special cases:
01039     // 1) tPUSH does not have src/dst regs.
01040     // 2) for Thumb1 code we sometimes materialize the constant via constpool
01041     // load. Yes, this is pretty fragile, but for now I don't see better
01042     // way... :(
01043     SrcReg = DstReg = ARM::SP;
01044   } else {
01045     SrcReg = MI->getOperand(1).getReg();
01046     DstReg = MI->getOperand(0).getReg();
01047   }
01048 
01049   // Try to figure out the unwinding opcode out of src / dst regs.
01050   if (MI->mayStore()) {
01051     // Register saves.
01052     assert(DstReg == ARM::SP &&
01053            "Only stack pointer as a destination reg is supported");
01054 
01055     SmallVector<unsigned, 4> RegList;
01056     // Skip src & dst reg, and pred ops.
01057     unsigned StartOp = 2 + 2;
01058     // Use all the operands.
01059     unsigned NumOffset = 0;
01060 
01061     switch (Opc) {
01062     default:
01063       MI->dump();
01064       llvm_unreachable("Unsupported opcode for unwinding information");
01065     case ARM::tPUSH:
01066       // Special case here: no src & dst reg, but two extra imp ops.
01067       StartOp = 2; NumOffset = 2;
01068     case ARM::STMDB_UPD:
01069     case ARM::t2STMDB_UPD:
01070     case ARM::VSTMDDB_UPD:
01071       assert(SrcReg == ARM::SP &&
01072              "Only stack pointer as a source reg is supported");
01073       for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
01074            i != NumOps; ++i) {
01075         const MachineOperand &MO = MI->getOperand(i);
01076         // Actually, there should never be any impdef stuff here. Skip it
01077         // temporary to workaround PR11902.
01078         if (MO.isImplicit())
01079           continue;
01080         RegList.push_back(MO.getReg());
01081       }
01082       break;
01083     case ARM::STR_PRE_IMM:
01084     case ARM::STR_PRE_REG:
01085     case ARM::t2STR_PRE:
01086       assert(MI->getOperand(2).getReg() == ARM::SP &&
01087              "Only stack pointer as a source reg is supported");
01088       RegList.push_back(SrcReg);
01089       break;
01090     }
01091     if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM)
01092       ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
01093   } else {
01094     // Changes of stack / frame pointer.
01095     if (SrcReg == ARM::SP) {
01096       int64_t Offset = 0;
01097       switch (Opc) {
01098       default:
01099         MI->dump();
01100         llvm_unreachable("Unsupported opcode for unwinding information");
01101       case ARM::MOVr:
01102       case ARM::tMOVr:
01103         Offset = 0;
01104         break;
01105       case ARM::ADDri:
01106         Offset = -MI->getOperand(2).getImm();
01107         break;
01108       case ARM::SUBri:
01109       case ARM::t2SUBri:
01110         Offset = MI->getOperand(2).getImm();
01111         break;
01112       case ARM::tSUBspi:
01113         Offset = MI->getOperand(2).getImm()*4;
01114         break;
01115       case ARM::tADDspi:
01116       case ARM::tADDrSPi:
01117         Offset = -MI->getOperand(2).getImm()*4;
01118         break;
01119       case ARM::tLDRpci: {
01120         // Grab the constpool index and check, whether it corresponds to
01121         // original or cloned constpool entry.
01122         unsigned CPI = MI->getOperand(1).getIndex();
01123         const MachineConstantPool *MCP = MF.getConstantPool();
01124         if (CPI >= MCP->getConstants().size())
01125           CPI = AFI.getOriginalCPIdx(CPI);
01126         assert(CPI != -1U && "Invalid constpool index");
01127 
01128         // Derive the actual offset.
01129         const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
01130         assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
01131         // FIXME: Check for user, it should be "add" instruction!
01132         Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
01133         break;
01134       }
01135       }
01136 
01137       if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM) {
01138         if (DstReg == FramePtr && FramePtr != ARM::SP)
01139           // Set-up of the frame pointer. Positive values correspond to "add"
01140           // instruction.
01141           ATS.emitSetFP(FramePtr, ARM::SP, -Offset);
01142         else if (DstReg == ARM::SP) {
01143           // Change of SP by an offset. Positive values correspond to "sub"
01144           // instruction.
01145           ATS.emitPad(Offset);
01146         } else {
01147           // Move of SP to a register.  Positive values correspond to an "add"
01148           // instruction.
01149           ATS.emitMovSP(DstReg, -Offset);
01150         }
01151       }
01152     } else if (DstReg == ARM::SP) {
01153       MI->dump();
01154       llvm_unreachable("Unsupported opcode for unwinding information");
01155     }
01156     else {
01157       MI->dump();
01158       llvm_unreachable("Unsupported opcode for unwinding information");
01159     }
01160   }
01161 }
01162 
01163 // Simple pseudo-instructions have their lowering (with expansion to real
01164 // instructions) auto-generated.
01165 #include "ARMGenMCPseudoLowering.inc"
01166 
01167 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
01168   const DataLayout *DL = TM.getDataLayout();
01169 
01170   // If we just ended a constant pool, mark it as such.
01171   if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
01172     OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
01173     InConstantPool = false;
01174   }
01175 
01176   // Emit unwinding stuff for frame-related instructions
01177   if (Subtarget->isTargetEHABICompatible() &&
01178        MI->getFlag(MachineInstr::FrameSetup))
01179     EmitUnwindingInstruction(MI);
01180 
01181   // Do any auto-generated pseudo lowerings.
01182   if (emitPseudoExpansionLowering(OutStreamer, MI))
01183     return;
01184 
01185   assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
01186          "Pseudo flag setting opcode should be expanded early");
01187 
01188   // Check for manual lowerings.
01189   unsigned Opc = MI->getOpcode();
01190   switch (Opc) {
01191   case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
01192   case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing");
01193   case ARM::LEApcrel:
01194   case ARM::tLEApcrel:
01195   case ARM::t2LEApcrel: {
01196     // FIXME: Need to also handle globals and externals
01197     MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex());
01198     EmitToStreamer(OutStreamer, MCInstBuilder(MI->getOpcode() ==
01199                                               ARM::t2LEApcrel ? ARM::t2ADR
01200                   : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
01201                      : ARM::ADR))
01202       .addReg(MI->getOperand(0).getReg())
01203       .addExpr(MCSymbolRefExpr::Create(CPISymbol, OutContext))
01204       // Add predicate operands.
01205       .addImm(MI->getOperand(2).getImm())
01206       .addReg(MI->getOperand(3).getReg()));
01207     return;
01208   }
01209   case ARM::LEApcrelJT:
01210   case ARM::tLEApcrelJT:
01211   case ARM::t2LEApcrelJT: {
01212     MCSymbol *JTIPICSymbol =
01213       GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
01214                                   MI->getOperand(2).getImm());
01215     EmitToStreamer(OutStreamer, MCInstBuilder(MI->getOpcode() ==
01216                                               ARM::t2LEApcrelJT ? ARM::t2ADR
01217                   : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
01218                      : ARM::ADR))
01219       .addReg(MI->getOperand(0).getReg())
01220       .addExpr(MCSymbolRefExpr::Create(JTIPICSymbol, OutContext))
01221       // Add predicate operands.
01222       .addImm(MI->getOperand(3).getImm())
01223       .addReg(MI->getOperand(4).getReg()));
01224     return;
01225   }
01226   // Darwin call instructions are just normal call instructions with different
01227   // clobber semantics (they clobber R9).
01228   case ARM::BX_CALL: {
01229     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
01230       .addReg(ARM::LR)
01231       .addReg(ARM::PC)
01232       // Add predicate operands.
01233       .addImm(ARMCC::AL)
01234       .addReg(0)
01235       // Add 's' bit operand (always reg0 for this)
01236       .addReg(0));
01237 
01238     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::BX)
01239       .addReg(MI->getOperand(0).getReg()));
01240     return;
01241   }
01242   case ARM::tBX_CALL: {
01243     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
01244       .addReg(ARM::LR)
01245       .addReg(ARM::PC)
01246       // Add predicate operands.
01247       .addImm(ARMCC::AL)
01248       .addReg(0));
01249 
01250     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tBX)
01251       .addReg(MI->getOperand(0).getReg())
01252       // Add predicate operands.
01253       .addImm(ARMCC::AL)
01254       .addReg(0));
01255     return;
01256   }
01257   case ARM::BMOVPCRX_CALL: {
01258     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
01259       .addReg(ARM::LR)
01260       .addReg(ARM::PC)
01261       // Add predicate operands.
01262       .addImm(ARMCC::AL)
01263       .addReg(0)
01264       // Add 's' bit operand (always reg0 for this)
01265       .addReg(0));
01266 
01267     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
01268       .addReg(ARM::PC)
01269       .addReg(MI->getOperand(0).getReg())
01270       // Add predicate operands.
01271       .addImm(ARMCC::AL)
01272       .addReg(0)
01273       // Add 's' bit operand (always reg0 for this)
01274       .addReg(0));
01275     return;
01276   }
01277   case ARM::BMOVPCB_CALL: {
01278     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
01279       .addReg(ARM::LR)
01280       .addReg(ARM::PC)
01281       // Add predicate operands.
01282       .addImm(ARMCC::AL)
01283       .addReg(0)
01284       // Add 's' bit operand (always reg0 for this)
01285       .addReg(0));
01286 
01287     const MachineOperand &Op = MI->getOperand(0);
01288     const GlobalValue *GV = Op.getGlobal();
01289     const unsigned TF = Op.getTargetFlags();
01290     MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
01291     const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
01292     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::Bcc)
01293       .addExpr(GVSymExpr)
01294       // Add predicate operands.
01295       .addImm(ARMCC::AL)
01296       .addReg(0));
01297     return;
01298   }
01299   case ARM::MOVi16_ga_pcrel:
01300   case ARM::t2MOVi16_ga_pcrel: {
01301     MCInst TmpInst;
01302     TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
01303     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
01304 
01305     unsigned TF = MI->getOperand(1).getTargetFlags();
01306     const GlobalValue *GV = MI->getOperand(1).getGlobal();
01307     MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
01308     const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
01309 
01310     MCSymbol *LabelSym = getPICLabel(DL->getPrivateGlobalPrefix(),
01311                                      getFunctionNumber(),
01312                                      MI->getOperand(2).getImm(), OutContext);
01313     const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
01314     unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
01315     const MCExpr *PCRelExpr =
01316       ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
01317                                       MCBinaryExpr::CreateAdd(LabelSymExpr,
01318                                       MCConstantExpr::Create(PCAdj, OutContext),
01319                                       OutContext), OutContext), OutContext);
01320       TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
01321 
01322     // Add predicate operands.
01323     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
01324     TmpInst.addOperand(MCOperand::CreateReg(0));
01325     // Add 's' bit operand (always reg0 for this)
01326     TmpInst.addOperand(MCOperand::CreateReg(0));
01327     EmitToStreamer(OutStreamer, TmpInst);
01328     return;
01329   }
01330   case ARM::MOVTi16_ga_pcrel:
01331   case ARM::t2MOVTi16_ga_pcrel: {
01332     MCInst TmpInst;
01333     TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
01334                       ? ARM::MOVTi16 : ARM::t2MOVTi16);
01335     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
01336     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
01337 
01338     unsigned TF = MI->getOperand(2).getTargetFlags();
01339     const GlobalValue *GV = MI->getOperand(2).getGlobal();
01340     MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
01341     const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
01342 
01343     MCSymbol *LabelSym = getPICLabel(DL->getPrivateGlobalPrefix(),
01344                                      getFunctionNumber(),
01345                                      MI->getOperand(3).getImm(), OutContext);
01346     const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
01347     unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
01348     const MCExpr *PCRelExpr =
01349         ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
01350                                    MCBinaryExpr::CreateAdd(LabelSymExpr,
01351                                       MCConstantExpr::Create(PCAdj, OutContext),
01352                                           OutContext), OutContext), OutContext);
01353       TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
01354     // Add predicate operands.
01355     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
01356     TmpInst.addOperand(MCOperand::CreateReg(0));
01357     // Add 's' bit operand (always reg0 for this)
01358     TmpInst.addOperand(MCOperand::CreateReg(0));
01359     EmitToStreamer(OutStreamer, TmpInst);
01360     return;
01361   }
01362   case ARM::tPICADD: {
01363     // This is a pseudo op for a label + instruction sequence, which looks like:
01364     // LPC0:
01365     //     add r0, pc
01366     // This adds the address of LPC0 to r0.
01367 
01368     // Emit the label.
01369     OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
01370                           getFunctionNumber(), MI->getOperand(2).getImm(),
01371                           OutContext));
01372 
01373     // Form and emit the add.
01374     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tADDhirr)
01375       .addReg(MI->getOperand(0).getReg())
01376       .addReg(MI->getOperand(0).getReg())
01377       .addReg(ARM::PC)
01378       // Add predicate operands.
01379       .addImm(ARMCC::AL)
01380       .addReg(0));
01381     return;
01382   }
01383   case ARM::PICADD: {
01384     // This is a pseudo op for a label + instruction sequence, which looks like:
01385     // LPC0:
01386     //     add r0, pc, r0
01387     // This adds the address of LPC0 to r0.
01388 
01389     // Emit the label.
01390     OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
01391                           getFunctionNumber(), MI->getOperand(2).getImm(),
01392                           OutContext));
01393 
01394     // Form and emit the add.
01395     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDrr)
01396       .addReg(MI->getOperand(0).getReg())
01397       .addReg(ARM::PC)
01398       .addReg(MI->getOperand(1).getReg())
01399       // Add predicate operands.
01400       .addImm(MI->getOperand(3).getImm())
01401       .addReg(MI->getOperand(4).getReg())
01402       // Add 's' bit operand (always reg0 for this)
01403       .addReg(0));
01404     return;
01405   }
01406   case ARM::PICSTR:
01407   case ARM::PICSTRB:
01408   case ARM::PICSTRH:
01409   case ARM::PICLDR:
01410   case ARM::PICLDRB:
01411   case ARM::PICLDRH:
01412   case ARM::PICLDRSB:
01413   case ARM::PICLDRSH: {
01414     // This is a pseudo op for a label + instruction sequence, which looks like:
01415     // LPC0:
01416     //     OP r0, [pc, r0]
01417     // The LCP0 label is referenced by a constant pool entry in order to get
01418     // a PC-relative address at the ldr instruction.
01419 
01420     // Emit the label.
01421     OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
01422                           getFunctionNumber(), MI->getOperand(2).getImm(),
01423                           OutContext));
01424 
01425     // Form and emit the load
01426     unsigned Opcode;
01427     switch (MI->getOpcode()) {
01428     default:
01429       llvm_unreachable("Unexpected opcode!");
01430     case ARM::PICSTR:   Opcode = ARM::STRrs; break;
01431     case ARM::PICSTRB:  Opcode = ARM::STRBrs; break;
01432     case ARM::PICSTRH:  Opcode = ARM::STRH; break;
01433     case ARM::PICLDR:   Opcode = ARM::LDRrs; break;
01434     case ARM::PICLDRB:  Opcode = ARM::LDRBrs; break;
01435     case ARM::PICLDRH:  Opcode = ARM::LDRH; break;
01436     case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
01437     case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
01438     }
01439     EmitToStreamer(OutStreamer, MCInstBuilder(Opcode)
01440       .addReg(MI->getOperand(0).getReg())
01441       .addReg(ARM::PC)
01442       .addReg(MI->getOperand(1).getReg())
01443       .addImm(0)
01444       // Add predicate operands.
01445       .addImm(MI->getOperand(3).getImm())
01446       .addReg(MI->getOperand(4).getReg()));
01447 
01448     return;
01449   }
01450   case ARM::CONSTPOOL_ENTRY: {
01451     /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
01452     /// in the function.  The first operand is the ID# for this instruction, the
01453     /// second is the index into the MachineConstantPool that this is, the third
01454     /// is the size in bytes of this constant pool entry.
01455     /// The required alignment is specified on the basic block holding this MI.
01456     unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
01457     unsigned CPIdx   = (unsigned)MI->getOperand(1).getIndex();
01458 
01459     // If this is the first entry of the pool, mark it.
01460     if (!InConstantPool) {
01461       OutStreamer.EmitDataRegion(MCDR_DataRegion);
01462       InConstantPool = true;
01463     }
01464 
01465     OutStreamer.EmitLabel(GetCPISymbol(LabelId));
01466 
01467     const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
01468     if (MCPE.isMachineConstantPoolEntry())
01469       EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
01470     else
01471       EmitGlobalConstant(MCPE.Val.ConstVal);
01472     return;
01473   }
01474   case ARM::t2BR_JT: {
01475     // Lower and emit the instruction itself, then the jump table following it.
01476     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
01477       .addReg(ARM::PC)
01478       .addReg(MI->getOperand(0).getReg())
01479       // Add predicate operands.
01480       .addImm(ARMCC::AL)
01481       .addReg(0));
01482 
01483     // Output the data for the jump table itself
01484     EmitJump2Table(MI);
01485     return;
01486   }
01487   case ARM::t2TBB_JT: {
01488     // Lower and emit the instruction itself, then the jump table following it.
01489     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::t2TBB)
01490       .addReg(ARM::PC)
01491       .addReg(MI->getOperand(0).getReg())
01492       // Add predicate operands.
01493       .addImm(ARMCC::AL)
01494       .addReg(0));
01495 
01496     // Output the data for the jump table itself
01497     EmitJump2Table(MI);
01498     // Make sure the next instruction is 2-byte aligned.
01499     EmitAlignment(1);
01500     return;
01501   }
01502   case ARM::t2TBH_JT: {
01503     // Lower and emit the instruction itself, then the jump table following it.
01504     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::t2TBH)
01505       .addReg(ARM::PC)
01506       .addReg(MI->getOperand(0).getReg())
01507       // Add predicate operands.
01508       .addImm(ARMCC::AL)
01509       .addReg(0));
01510 
01511     // Output the data for the jump table itself
01512     EmitJump2Table(MI);
01513     return;
01514   }
01515   case ARM::tBR_JTr:
01516   case ARM::BR_JTr: {
01517     // Lower and emit the instruction itself, then the jump table following it.
01518     // mov pc, target
01519     MCInst TmpInst;
01520     unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
01521       ARM::MOVr : ARM::tMOVr;
01522     TmpInst.setOpcode(Opc);
01523     TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
01524     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
01525     // Add predicate operands.
01526     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
01527     TmpInst.addOperand(MCOperand::CreateReg(0));
01528     // Add 's' bit operand (always reg0 for this)
01529     if (Opc == ARM::MOVr)
01530       TmpInst.addOperand(MCOperand::CreateReg(0));
01531     EmitToStreamer(OutStreamer, TmpInst);
01532 
01533     // Make sure the Thumb jump table is 4-byte aligned.
01534     if (Opc == ARM::tMOVr)
01535       EmitAlignment(2);
01536 
01537     // Output the data for the jump table itself
01538     EmitJumpTable(MI);
01539     return;
01540   }
01541   case ARM::BR_JTm: {
01542     // Lower and emit the instruction itself, then the jump table following it.
01543     // ldr pc, target
01544     MCInst TmpInst;
01545     if (MI->getOperand(1).getReg() == 0) {
01546       // literal offset
01547       TmpInst.setOpcode(ARM::LDRi12);
01548       TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
01549       TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
01550       TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
01551     } else {
01552       TmpInst.setOpcode(ARM::LDRrs);
01553       TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
01554       TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
01555       TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
01556       TmpInst.addOperand(MCOperand::CreateImm(0));
01557     }
01558     // Add predicate operands.
01559     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
01560     TmpInst.addOperand(MCOperand::CreateReg(0));
01561     EmitToStreamer(OutStreamer, TmpInst);
01562 
01563     // Output the data for the jump table itself
01564     EmitJumpTable(MI);
01565     return;
01566   }
01567   case ARM::BR_JTadd: {
01568     // Lower and emit the instruction itself, then the jump table following it.
01569     // add pc, target, idx
01570     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDrr)
01571       .addReg(ARM::PC)
01572       .addReg(MI->getOperand(0).getReg())
01573       .addReg(MI->getOperand(1).getReg())
01574       // Add predicate operands.
01575       .addImm(ARMCC::AL)
01576       .addReg(0)
01577       // Add 's' bit operand (always reg0 for this)
01578       .addReg(0));
01579 
01580     // Output the data for the jump table itself
01581     EmitJumpTable(MI);
01582     return;
01583   }
01584   case ARM::TRAP: {
01585     // Non-Darwin binutils don't yet support the "trap" mnemonic.
01586     // FIXME: Remove this special case when they do.
01587     if (!Subtarget->isTargetMachO()) {
01588       //.long 0xe7ffdefe @ trap
01589       uint32_t Val = 0xe7ffdefeUL;
01590       OutStreamer.AddComment("trap");
01591       OutStreamer.EmitIntValue(Val, 4);
01592       return;
01593     }
01594     break;
01595   }
01596   case ARM::TRAPNaCl: {
01597     //.long 0xe7fedef0 @ trap
01598     uint32_t Val = 0xe7fedef0UL;
01599     OutStreamer.AddComment("trap");
01600     OutStreamer.EmitIntValue(Val, 4);
01601     return;
01602   }
01603   case ARM::tTRAP: {
01604     // Non-Darwin binutils don't yet support the "trap" mnemonic.
01605     // FIXME: Remove this special case when they do.
01606     if (!Subtarget->isTargetMachO()) {
01607       //.short 57086 @ trap
01608       uint16_t Val = 0xdefe;
01609       OutStreamer.AddComment("trap");
01610       OutStreamer.EmitIntValue(Val, 2);
01611       return;
01612     }
01613     break;
01614   }
01615   case ARM::t2Int_eh_sjlj_setjmp:
01616   case ARM::t2Int_eh_sjlj_setjmp_nofp:
01617   case ARM::tInt_eh_sjlj_setjmp: {
01618     // Two incoming args: GPR:$src, GPR:$val
01619     // mov $val, pc
01620     // adds $val, #7
01621     // str $val, [$src, #4]
01622     // movs r0, #0
01623     // b 1f
01624     // movs r0, #1
01625     // 1:
01626     unsigned SrcReg = MI->getOperand(0).getReg();
01627     unsigned ValReg = MI->getOperand(1).getReg();
01628     MCSymbol *Label = GetARMSJLJEHLabel();
01629     OutStreamer.AddComment("eh_setjmp begin");
01630     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
01631       .addReg(ValReg)
01632       .addReg(ARM::PC)
01633       // Predicate.
01634       .addImm(ARMCC::AL)
01635       .addReg(0));
01636 
01637     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tADDi3)
01638       .addReg(ValReg)
01639       // 's' bit operand
01640       .addReg(ARM::CPSR)
01641       .addReg(ValReg)
01642       .addImm(7)
01643       // Predicate.
01644       .addImm(ARMCC::AL)
01645       .addReg(0));
01646 
01647     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tSTRi)
01648       .addReg(ValReg)
01649       .addReg(SrcReg)
01650       // The offset immediate is #4. The operand value is scaled by 4 for the
01651       // tSTR instruction.
01652       .addImm(1)
01653       // Predicate.
01654       .addImm(ARMCC::AL)
01655       .addReg(0));
01656 
01657     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVi8)
01658       .addReg(ARM::R0)
01659       .addReg(ARM::CPSR)
01660       .addImm(0)
01661       // Predicate.
01662       .addImm(ARMCC::AL)
01663       .addReg(0));
01664 
01665     const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
01666     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tB)
01667       .addExpr(SymbolExpr)
01668       .addImm(ARMCC::AL)
01669       .addReg(0));
01670 
01671     OutStreamer.AddComment("eh_setjmp end");
01672     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVi8)
01673       .addReg(ARM::R0)
01674       .addReg(ARM::CPSR)
01675       .addImm(1)
01676       // Predicate.
01677       .addImm(ARMCC::AL)
01678       .addReg(0));
01679 
01680     OutStreamer.EmitLabel(Label);
01681     return;
01682   }
01683 
01684   case ARM::Int_eh_sjlj_setjmp_nofp:
01685   case ARM::Int_eh_sjlj_setjmp: {
01686     // Two incoming args: GPR:$src, GPR:$val
01687     // add $val, pc, #8
01688     // str $val, [$src, #+4]
01689     // mov r0, #0
01690     // add pc, pc, #0
01691     // mov r0, #1
01692     unsigned SrcReg = MI->getOperand(0).getReg();
01693     unsigned ValReg = MI->getOperand(1).getReg();
01694 
01695     OutStreamer.AddComment("eh_setjmp begin");
01696     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDri)
01697       .addReg(ValReg)
01698       .addReg(ARM::PC)
01699       .addImm(8)
01700       // Predicate.
01701       .addImm(ARMCC::AL)
01702       .addReg(0)
01703       // 's' bit operand (always reg0 for this).
01704       .addReg(0));
01705 
01706     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::STRi12)
01707       .addReg(ValReg)
01708       .addReg(SrcReg)
01709       .addImm(4)
01710       // Predicate.
01711       .addImm(ARMCC::AL)
01712       .addReg(0));
01713 
01714     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVi)
01715       .addReg(ARM::R0)
01716       .addImm(0)
01717       // Predicate.
01718       .addImm(ARMCC::AL)
01719       .addReg(0)
01720       // 's' bit operand (always reg0 for this).
01721       .addReg(0));
01722 
01723     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDri)
01724       .addReg(ARM::PC)
01725       .addReg(ARM::PC)
01726       .addImm(0)
01727       // Predicate.
01728       .addImm(ARMCC::AL)
01729       .addReg(0)
01730       // 's' bit operand (always reg0 for this).
01731       .addReg(0));
01732 
01733     OutStreamer.AddComment("eh_setjmp end");
01734     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVi)
01735       .addReg(ARM::R0)
01736       .addImm(1)
01737       // Predicate.
01738       .addImm(ARMCC::AL)
01739       .addReg(0)
01740       // 's' bit operand (always reg0 for this).
01741       .addReg(0));
01742     return;
01743   }
01744   case ARM::Int_eh_sjlj_longjmp: {
01745     // ldr sp, [$src, #8]
01746     // ldr $scratch, [$src, #4]
01747     // ldr r7, [$src]
01748     // bx $scratch
01749     unsigned SrcReg = MI->getOperand(0).getReg();
01750     unsigned ScratchReg = MI->getOperand(1).getReg();
01751     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::LDRi12)
01752       .addReg(ARM::SP)
01753       .addReg(SrcReg)
01754       .addImm(8)
01755       // Predicate.
01756       .addImm(ARMCC::AL)
01757       .addReg(0));
01758 
01759     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::LDRi12)
01760       .addReg(ScratchReg)
01761       .addReg(SrcReg)
01762       .addImm(4)
01763       // Predicate.
01764       .addImm(ARMCC::AL)
01765       .addReg(0));
01766 
01767     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::LDRi12)
01768       .addReg(ARM::R7)
01769       .addReg(SrcReg)
01770       .addImm(0)
01771       // Predicate.
01772       .addImm(ARMCC::AL)
01773       .addReg(0));
01774 
01775     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::BX)
01776       .addReg(ScratchReg)
01777       // Predicate.
01778       .addImm(ARMCC::AL)
01779       .addReg(0));
01780     return;
01781   }
01782   case ARM::tInt_eh_sjlj_longjmp: {
01783     // ldr $scratch, [$src, #8]
01784     // mov sp, $scratch
01785     // ldr $scratch, [$src, #4]
01786     // ldr r7, [$src]
01787     // bx $scratch
01788     unsigned SrcReg = MI->getOperand(0).getReg();
01789     unsigned ScratchReg = MI->getOperand(1).getReg();
01790     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tLDRi)
01791       .addReg(ScratchReg)
01792       .addReg(SrcReg)
01793       // The offset immediate is #8. The operand value is scaled by 4 for the
01794       // tLDR instruction.
01795       .addImm(2)
01796       // Predicate.
01797       .addImm(ARMCC::AL)
01798       .addReg(0));
01799 
01800     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
01801       .addReg(ARM::SP)
01802       .addReg(ScratchReg)
01803       // Predicate.
01804       .addImm(ARMCC::AL)
01805       .addReg(0));
01806 
01807     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tLDRi)
01808       .addReg(ScratchReg)
01809       .addReg(SrcReg)
01810       .addImm(1)
01811       // Predicate.
01812       .addImm(ARMCC::AL)
01813       .addReg(0));
01814 
01815     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tLDRi)
01816       .addReg(ARM::R7)
01817       .addReg(SrcReg)
01818       .addImm(0)
01819       // Predicate.
01820       .addImm(ARMCC::AL)
01821       .addReg(0));
01822 
01823     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tBX)
01824       .addReg(ScratchReg)
01825       // Predicate.
01826       .addImm(ARMCC::AL)
01827       .addReg(0));
01828     return;
01829   }
01830   }
01831 
01832   MCInst TmpInst;
01833   LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
01834 
01835   EmitToStreamer(OutStreamer, TmpInst);
01836 }
01837 
01838 //===----------------------------------------------------------------------===//
01839 // Target Registry Stuff
01840 //===----------------------------------------------------------------------===//
01841 
01842 // Force static initialization.
01843 extern "C" void LLVMInitializeARMAsmPrinter() {
01844   RegisterAsmPrinter<ARMAsmPrinter> X(TheARMLETarget);
01845   RegisterAsmPrinter<ARMAsmPrinter> Y(TheARMBETarget);
01846   RegisterAsmPrinter<ARMAsmPrinter> A(TheThumbLETarget);
01847   RegisterAsmPrinter<ARMAsmPrinter> B(TheThumbBETarget);
01848 }