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ARMAsmPrinter.cpp
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00001 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file contains a printer that converts from our internal representation
00011 // of machine-dependent LLVM code to GAS-format ARM assembly language.
00012 //
00013 //===----------------------------------------------------------------------===//
00014 
00015 #include "ARMAsmPrinter.h"
00016 #include "ARM.h"
00017 #include "ARMConstantPoolValue.h"
00018 #include "ARMFPUName.h"
00019 #include "ARMMachineFunctionInfo.h"
00020 #include "ARMTargetMachine.h"
00021 #include "ARMTargetObjectFile.h"
00022 #include "InstPrinter/ARMInstPrinter.h"
00023 #include "MCTargetDesc/ARMAddressingModes.h"
00024 #include "MCTargetDesc/ARMMCExpr.h"
00025 #include "llvm/ADT/SetVector.h"
00026 #include "llvm/ADT/SmallString.h"
00027 #include "llvm/CodeGen/MachineFunctionPass.h"
00028 #include "llvm/CodeGen/MachineJumpTableInfo.h"
00029 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
00030 #include "llvm/IR/Constants.h"
00031 #include "llvm/IR/DataLayout.h"
00032 #include "llvm/IR/DebugInfo.h"
00033 #include "llvm/IR/Mangler.h"
00034 #include "llvm/IR/Module.h"
00035 #include "llvm/IR/Type.h"
00036 #include "llvm/MC/MCAsmInfo.h"
00037 #include "llvm/MC/MCAssembler.h"
00038 #include "llvm/MC/MCContext.h"
00039 #include "llvm/MC/MCELFStreamer.h"
00040 #include "llvm/MC/MCInst.h"
00041 #include "llvm/MC/MCInstBuilder.h"
00042 #include "llvm/MC/MCObjectStreamer.h"
00043 #include "llvm/MC/MCSectionMachO.h"
00044 #include "llvm/MC/MCStreamer.h"
00045 #include "llvm/MC/MCSymbol.h"
00046 #include "llvm/Support/ARMBuildAttributes.h"
00047 #include "llvm/Support/COFF.h"
00048 #include "llvm/Support/CommandLine.h"
00049 #include "llvm/Support/Debug.h"
00050 #include "llvm/Support/ELF.h"
00051 #include "llvm/Support/ErrorHandling.h"
00052 #include "llvm/Support/TargetRegistry.h"
00053 #include "llvm/Support/raw_ostream.h"
00054 #include "llvm/Target/TargetMachine.h"
00055 #include <cctype>
00056 using namespace llvm;
00057 
00058 #define DEBUG_TYPE "asm-printer"
00059 
00060 void ARMAsmPrinter::EmitFunctionBodyEnd() {
00061   // Make sure to terminate any constant pools that were at the end
00062   // of the function.
00063   if (!InConstantPool)
00064     return;
00065   InConstantPool = false;
00066   OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
00067 }
00068 
00069 void ARMAsmPrinter::EmitFunctionEntryLabel() {
00070   if (AFI->isThumbFunction()) {
00071     OutStreamer.EmitAssemblerFlag(MCAF_Code16);
00072     OutStreamer.EmitThumbFunc(CurrentFnSym);
00073   }
00074 
00075   OutStreamer.EmitLabel(CurrentFnSym);
00076 }
00077 
00078 void ARMAsmPrinter::EmitXXStructor(const Constant *CV) {
00079   uint64_t Size =
00080       TM.getSubtargetImpl()->getDataLayout()->getTypeAllocSize(CV->getType());
00081   assert(Size && "C++ constructor pointer had zero size!");
00082 
00083   const GlobalValue *GV = dyn_cast<GlobalValue>(CV->stripPointerCasts());
00084   assert(GV && "C++ constructor pointer was not a GlobalValue!");
00085 
00086   const MCExpr *E = MCSymbolRefExpr::Create(GetARMGVSymbol(GV,
00087                                                            ARMII::MO_NO_FLAG),
00088                                             (Subtarget->isTargetELF()
00089                                              ? MCSymbolRefExpr::VK_ARM_TARGET1
00090                                              : MCSymbolRefExpr::VK_None),
00091                                             OutContext);
00092 
00093   OutStreamer.EmitValue(E, Size);
00094 }
00095 
00096 /// runOnMachineFunction - This uses the EmitInstruction()
00097 /// method to print assembly for each instruction.
00098 ///
00099 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
00100   AFI = MF.getInfo<ARMFunctionInfo>();
00101   MCP = MF.getConstantPool();
00102 
00103   SetupMachineFunction(MF);
00104 
00105   if (Subtarget->isTargetCOFF()) {
00106     bool Internal = MF.getFunction()->hasInternalLinkage();
00107     COFF::SymbolStorageClass Scl = Internal ? COFF::IMAGE_SYM_CLASS_STATIC
00108                                             : COFF::IMAGE_SYM_CLASS_EXTERNAL;
00109     int Type = COFF::IMAGE_SYM_DTYPE_FUNCTION << COFF::SCT_COMPLEX_TYPE_SHIFT;
00110 
00111     OutStreamer.BeginCOFFSymbolDef(CurrentFnSym);
00112     OutStreamer.EmitCOFFSymbolStorageClass(Scl);
00113     OutStreamer.EmitCOFFSymbolType(Type);
00114     OutStreamer.EndCOFFSymbolDef();
00115   }
00116 
00117   // Have common code print out the function header with linkage info etc.
00118   EmitFunctionHeader();
00119 
00120   // Emit the rest of the function body.
00121   EmitFunctionBody();
00122 
00123   // If we need V4T thumb mode Register Indirect Jump pads, emit them.
00124   // These are created per function, rather than per TU, since it's
00125   // relatively easy to exceed the thumb branch range within a TU.
00126   if (! ThumbIndirectPads.empty()) {
00127     OutStreamer.EmitAssemblerFlag(MCAF_Code16);
00128     EmitAlignment(1);
00129     for (unsigned i = 0, e = ThumbIndirectPads.size(); i < e; i++) {
00130       OutStreamer.EmitLabel(ThumbIndirectPads[i].second);
00131       EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tBX)
00132         .addReg(ThumbIndirectPads[i].first)
00133         // Add predicate operands.
00134         .addImm(ARMCC::AL)
00135         .addReg(0));
00136     }
00137     ThumbIndirectPads.clear();
00138   }
00139 
00140   // We didn't modify anything.
00141   return false;
00142 }
00143 
00144 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
00145                                  raw_ostream &O, const char *Modifier) {
00146   const MachineOperand &MO = MI->getOperand(OpNum);
00147   unsigned TF = MO.getTargetFlags();
00148 
00149   switch (MO.getType()) {
00150   default: llvm_unreachable("<unknown operand type>");
00151   case MachineOperand::MO_Register: {
00152     unsigned Reg = MO.getReg();
00153     assert(TargetRegisterInfo::isPhysicalRegister(Reg));
00154     assert(!MO.getSubReg() && "Subregs should be eliminated!");
00155     if(ARM::GPRPairRegClass.contains(Reg)) {
00156       const MachineFunction &MF = *MI->getParent()->getParent();
00157       const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
00158       Reg = TRI->getSubReg(Reg, ARM::gsub_0);
00159     }
00160     O << ARMInstPrinter::getRegisterName(Reg);
00161     break;
00162   }
00163   case MachineOperand::MO_Immediate: {
00164     int64_t Imm = MO.getImm();
00165     O << '#';
00166     if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
00167         (TF == ARMII::MO_LO16))
00168       O << ":lower16:";
00169     else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
00170              (TF == ARMII::MO_HI16))
00171       O << ":upper16:";
00172     O << Imm;
00173     break;
00174   }
00175   case MachineOperand::MO_MachineBasicBlock:
00176     O << *MO.getMBB()->getSymbol();
00177     return;
00178   case MachineOperand::MO_GlobalAddress: {
00179     const GlobalValue *GV = MO.getGlobal();
00180     if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
00181         (TF & ARMII::MO_LO16))
00182       O << ":lower16:";
00183     else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
00184              (TF & ARMII::MO_HI16))
00185       O << ":upper16:";
00186     O << *GetARMGVSymbol(GV, TF);
00187 
00188     printOffset(MO.getOffset(), O);
00189     if (TF == ARMII::MO_PLT)
00190       O << "(PLT)";
00191     break;
00192   }
00193   case MachineOperand::MO_ConstantPoolIndex:
00194     O << *GetCPISymbol(MO.getIndex());
00195     break;
00196   }
00197 }
00198 
00199 //===--------------------------------------------------------------------===//
00200 
00201 MCSymbol *ARMAsmPrinter::
00202 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
00203   const DataLayout *DL = TM.getSubtargetImpl()->getDataLayout();
00204   SmallString<60> Name;
00205   raw_svector_ostream(Name) << DL->getPrivateGlobalPrefix() << "JTI"
00206     << getFunctionNumber() << '_' << uid << '_' << uid2;
00207   return OutContext.GetOrCreateSymbol(Name.str());
00208 }
00209 
00210 
00211 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel() const {
00212   const DataLayout *DL = TM.getSubtargetImpl()->getDataLayout();
00213   SmallString<60> Name;
00214   raw_svector_ostream(Name) << DL->getPrivateGlobalPrefix() << "SJLJEH"
00215     << getFunctionNumber();
00216   return OutContext.GetOrCreateSymbol(Name.str());
00217 }
00218 
00219 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
00220                                     unsigned AsmVariant, const char *ExtraCode,
00221                                     raw_ostream &O) {
00222   // Does this asm operand have a single letter operand modifier?
00223   if (ExtraCode && ExtraCode[0]) {
00224     if (ExtraCode[1] != 0) return true; // Unknown modifier.
00225 
00226     switch (ExtraCode[0]) {
00227     default:
00228       // See if this is a generic print operand
00229       return AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O);
00230     case 'a': // Print as a memory address.
00231       if (MI->getOperand(OpNum).isReg()) {
00232         O << "["
00233           << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
00234           << "]";
00235         return false;
00236       }
00237       // Fallthrough
00238     case 'c': // Don't print "#" before an immediate operand.
00239       if (!MI->getOperand(OpNum).isImm())
00240         return true;
00241       O << MI->getOperand(OpNum).getImm();
00242       return false;
00243     case 'P': // Print a VFP double precision register.
00244     case 'q': // Print a NEON quad precision register.
00245       printOperand(MI, OpNum, O);
00246       return false;
00247     case 'y': // Print a VFP single precision register as indexed double.
00248       if (MI->getOperand(OpNum).isReg()) {
00249         unsigned Reg = MI->getOperand(OpNum).getReg();
00250         const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
00251         // Find the 'd' register that has this 's' register as a sub-register,
00252         // and determine the lane number.
00253         for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
00254           if (!ARM::DPRRegClass.contains(*SR))
00255             continue;
00256           bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
00257           O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");
00258           return false;
00259         }
00260       }
00261       return true;
00262     case 'B': // Bitwise inverse of integer or symbol without a preceding #.
00263       if (!MI->getOperand(OpNum).isImm())
00264         return true;
00265       O << ~(MI->getOperand(OpNum).getImm());
00266       return false;
00267     case 'L': // The low 16 bits of an immediate constant.
00268       if (!MI->getOperand(OpNum).isImm())
00269         return true;
00270       O << (MI->getOperand(OpNum).getImm() & 0xffff);
00271       return false;
00272     case 'M': { // A register range suitable for LDM/STM.
00273       if (!MI->getOperand(OpNum).isReg())
00274         return true;
00275       const MachineOperand &MO = MI->getOperand(OpNum);
00276       unsigned RegBegin = MO.getReg();
00277       // This takes advantage of the 2 operand-ness of ldm/stm and that we've
00278       // already got the operands in registers that are operands to the
00279       // inline asm statement.
00280       O << "{";
00281       if (ARM::GPRPairRegClass.contains(RegBegin)) {
00282         const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
00283         unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
00284         O << ARMInstPrinter::getRegisterName(Reg0) << ", ";
00285         RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1);
00286       }
00287       O << ARMInstPrinter::getRegisterName(RegBegin);
00288 
00289       // FIXME: The register allocator not only may not have given us the
00290       // registers in sequence, but may not be in ascending registers. This
00291       // will require changes in the register allocator that'll need to be
00292       // propagated down here if the operands change.
00293       unsigned RegOps = OpNum + 1;
00294       while (MI->getOperand(RegOps).isReg()) {
00295         O << ", "
00296           << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
00297         RegOps++;
00298       }
00299 
00300       O << "}";
00301 
00302       return false;
00303     }
00304     case 'R': // The most significant register of a pair.
00305     case 'Q': { // The least significant register of a pair.
00306       if (OpNum == 0)
00307         return true;
00308       const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
00309       if (!FlagsOP.isImm())
00310         return true;
00311       unsigned Flags = FlagsOP.getImm();
00312 
00313       // This operand may not be the one that actually provides the register. If
00314       // it's tied to a previous one then we should refer instead to that one
00315       // for registers and their classes.
00316       unsigned TiedIdx;
00317       if (InlineAsm::isUseOperandTiedToDef(Flags, TiedIdx)) {
00318         for (OpNum = InlineAsm::MIOp_FirstOperand; TiedIdx; --TiedIdx) {
00319           unsigned OpFlags = MI->getOperand(OpNum).getImm();
00320           OpNum += InlineAsm::getNumOperandRegisters(OpFlags) + 1;
00321         }
00322         Flags = MI->getOperand(OpNum).getImm();
00323 
00324         // Later code expects OpNum to be pointing at the register rather than
00325         // the flags.
00326         OpNum += 1;
00327       }
00328 
00329       unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
00330       unsigned RC;
00331       InlineAsm::hasRegClassConstraint(Flags, RC);
00332       if (RC == ARM::GPRPairRegClassID) {
00333         if (NumVals != 1)
00334           return true;
00335         const MachineOperand &MO = MI->getOperand(OpNum);
00336         if (!MO.isReg())
00337           return true;
00338         const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
00339         unsigned Reg = TRI->getSubReg(MO.getReg(), ExtraCode[0] == 'Q' ?
00340             ARM::gsub_0 : ARM::gsub_1);
00341         O << ARMInstPrinter::getRegisterName(Reg);
00342         return false;
00343       }
00344       if (NumVals != 2)
00345         return true;
00346       unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
00347       if (RegOp >= MI->getNumOperands())
00348         return true;
00349       const MachineOperand &MO = MI->getOperand(RegOp);
00350       if (!MO.isReg())
00351         return true;
00352       unsigned Reg = MO.getReg();
00353       O << ARMInstPrinter::getRegisterName(Reg);
00354       return false;
00355     }
00356 
00357     case 'e': // The low doubleword register of a NEON quad register.
00358     case 'f': { // The high doubleword register of a NEON quad register.
00359       if (!MI->getOperand(OpNum).isReg())
00360         return true;
00361       unsigned Reg = MI->getOperand(OpNum).getReg();
00362       if (!ARM::QPRRegClass.contains(Reg))
00363         return true;
00364       const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
00365       unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
00366                                        ARM::dsub_0 : ARM::dsub_1);
00367       O << ARMInstPrinter::getRegisterName(SubReg);
00368       return false;
00369     }
00370 
00371     // This modifier is not yet supported.
00372     case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
00373       return true;
00374     case 'H': { // The highest-numbered register of a pair.
00375       const MachineOperand &MO = MI->getOperand(OpNum);
00376       if (!MO.isReg())
00377         return true;
00378       const MachineFunction &MF = *MI->getParent()->getParent();
00379       const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
00380       unsigned Reg = MO.getReg();
00381       if(!ARM::GPRPairRegClass.contains(Reg))
00382         return false;
00383       Reg = TRI->getSubReg(Reg, ARM::gsub_1);
00384       O << ARMInstPrinter::getRegisterName(Reg);
00385       return false;
00386     }
00387     }
00388   }
00389 
00390   printOperand(MI, OpNum, O);
00391   return false;
00392 }
00393 
00394 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
00395                                           unsigned OpNum, unsigned AsmVariant,
00396                                           const char *ExtraCode,
00397                                           raw_ostream &O) {
00398   // Does this asm operand have a single letter operand modifier?
00399   if (ExtraCode && ExtraCode[0]) {
00400     if (ExtraCode[1] != 0) return true; // Unknown modifier.
00401 
00402     switch (ExtraCode[0]) {
00403       case 'A': // A memory operand for a VLD1/VST1 instruction.
00404       default: return true;  // Unknown modifier.
00405       case 'm': // The base register of a memory operand.
00406         if (!MI->getOperand(OpNum).isReg())
00407           return true;
00408         O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
00409         return false;
00410     }
00411   }
00412 
00413   const MachineOperand &MO = MI->getOperand(OpNum);
00414   assert(MO.isReg() && "unexpected inline asm memory operand");
00415   O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
00416   return false;
00417 }
00418 
00419 static bool isThumb(const MCSubtargetInfo& STI) {
00420   return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
00421 }
00422 
00423 void ARMAsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo &StartInfo,
00424                                      const MCSubtargetInfo *EndInfo) const {
00425   // If either end mode is unknown (EndInfo == NULL) or different than
00426   // the start mode, then restore the start mode.
00427   const bool WasThumb = isThumb(StartInfo);
00428   if (!EndInfo || WasThumb != isThumb(*EndInfo)) {
00429     OutStreamer.EmitAssemblerFlag(WasThumb ? MCAF_Code16 : MCAF_Code32);
00430   }
00431 }
00432 
00433 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
00434   if (Subtarget->isTargetMachO()) {
00435     Reloc::Model RelocM = TM.getRelocationModel();
00436     if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
00437       // Declare all the text sections up front (before the DWARF sections
00438       // emitted by AsmPrinter::doInitialization) so the assembler will keep
00439       // them together at the beginning of the object file.  This helps
00440       // avoid out-of-range branches that are due a fundamental limitation of
00441       // the way symbol offsets are encoded with the current Darwin ARM
00442       // relocations.
00443       const TargetLoweringObjectFileMachO &TLOFMacho =
00444         static_cast<const TargetLoweringObjectFileMachO &>(
00445           getObjFileLowering());
00446 
00447       // Collect the set of sections our functions will go into.
00448       SetVector<const MCSection *, SmallVector<const MCSection *, 8>,
00449         SmallPtrSet<const MCSection *, 8> > TextSections;
00450       // Default text section comes first.
00451       TextSections.insert(TLOFMacho.getTextSection());
00452       // Now any user defined text sections from function attributes.
00453       for (Module::iterator F = M.begin(), e = M.end(); F != e; ++F)
00454         if (!F->isDeclaration() && !F->hasAvailableExternallyLinkage())
00455           TextSections.insert(TLOFMacho.SectionForGlobal(F, *Mang, TM));
00456       // Now the coalescable sections.
00457       TextSections.insert(TLOFMacho.getTextCoalSection());
00458       TextSections.insert(TLOFMacho.getConstTextCoalSection());
00459 
00460       // Emit the sections in the .s file header to fix the order.
00461       for (unsigned i = 0, e = TextSections.size(); i != e; ++i)
00462         OutStreamer.SwitchSection(TextSections[i]);
00463 
00464       if (RelocM == Reloc::DynamicNoPIC) {
00465         const MCSection *sect =
00466           OutContext.getMachOSection("__TEXT", "__symbol_stub4",
00467                                      MachO::S_SYMBOL_STUBS,
00468                                      12, SectionKind::getText());
00469         OutStreamer.SwitchSection(sect);
00470       } else {
00471         const MCSection *sect =
00472           OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
00473                                      MachO::S_SYMBOL_STUBS,
00474                                      16, SectionKind::getText());
00475         OutStreamer.SwitchSection(sect);
00476       }
00477       const MCSection *StaticInitSect =
00478         OutContext.getMachOSection("__TEXT", "__StaticInit",
00479                                    MachO::S_REGULAR |
00480                                    MachO::S_ATTR_PURE_INSTRUCTIONS,
00481                                    SectionKind::getText());
00482       OutStreamer.SwitchSection(StaticInitSect);
00483     }
00484 
00485     // Compiling with debug info should not affect the code
00486     // generation.  Ensure the cstring section comes before the
00487     // optional __DWARF secion. Otherwise, PC-relative loads would
00488     // have to use different instruction sequences at "-g" in order to
00489     // reach global data in the same object file.
00490     OutStreamer.SwitchSection(getObjFileLowering().getCStringSection());
00491   }
00492 
00493   // Use unified assembler syntax.
00494   OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
00495 
00496   // Emit ARM Build Attributes
00497   if (Subtarget->isTargetELF())
00498     emitAttributes();
00499 
00500   if (!M.getModuleInlineAsm().empty() && Subtarget->isThumb())
00501     OutStreamer.EmitAssemblerFlag(MCAF_Code16);
00502 }
00503 
00504 static void
00505 emitNonLazySymbolPointer(MCStreamer &OutStreamer, MCSymbol *StubLabel,
00506                          MachineModuleInfoImpl::StubValueTy &MCSym) {
00507   // L_foo$stub:
00508   OutStreamer.EmitLabel(StubLabel);
00509   //   .indirect_symbol _foo
00510   OutStreamer.EmitSymbolAttribute(MCSym.getPointer(), MCSA_IndirectSymbol);
00511 
00512   if (MCSym.getInt())
00513     // External to current translation unit.
00514     OutStreamer.EmitIntValue(0, 4/*size*/);
00515   else
00516     // Internal to current translation unit.
00517     //
00518     // When we place the LSDA into the TEXT section, the type info
00519     // pointers need to be indirect and pc-rel. We accomplish this by
00520     // using NLPs; however, sometimes the types are local to the file.
00521     // We need to fill in the value for the NLP in those cases.
00522     OutStreamer.EmitValue(
00523         MCSymbolRefExpr::Create(MCSym.getPointer(), OutStreamer.getContext()),
00524         4 /*size*/);
00525 }
00526 
00527 
00528 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
00529   if (Subtarget->isTargetMachO()) {
00530     // All darwin targets use mach-o.
00531     const TargetLoweringObjectFileMachO &TLOFMacho =
00532       static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
00533     MachineModuleInfoMachO &MMIMacho =
00534       MMI->getObjFileInfo<MachineModuleInfoMachO>();
00535 
00536     // Output non-lazy-pointers for external and common global variables.
00537     MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
00538 
00539     if (!Stubs.empty()) {
00540       // Switch with ".non_lazy_symbol_pointer" directive.
00541       OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
00542       EmitAlignment(2);
00543 
00544       for (auto &Stub : Stubs)
00545         emitNonLazySymbolPointer(OutStreamer, Stub.first, Stub.second);
00546 
00547       Stubs.clear();
00548       OutStreamer.AddBlankLine();
00549     }
00550 
00551     Stubs = MMIMacho.GetHiddenGVStubList();
00552     if (!Stubs.empty()) {
00553       OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
00554       EmitAlignment(2);
00555 
00556       for (auto &Stub : Stubs)
00557         emitNonLazySymbolPointer(OutStreamer, Stub.first, Stub.second);
00558 
00559       Stubs.clear();
00560       OutStreamer.AddBlankLine();
00561     }
00562 
00563     // Funny Darwin hack: This flag tells the linker that no global symbols
00564     // contain code that falls through to other global symbols (e.g. the obvious
00565     // implementation of multiple entry points).  If this doesn't occur, the
00566     // linker can safely perform dead code stripping.  Since LLVM never
00567     // generates code that does this, it is always safe to set.
00568     OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
00569   }
00570 
00571   // Emit a .data.rel section containing any stubs that were created.
00572   if (Subtarget->isTargetELF()) {
00573     const TargetLoweringObjectFileELF &TLOFELF =
00574       static_cast<const TargetLoweringObjectFileELF &>(getObjFileLowering());
00575 
00576     MachineModuleInfoELF &MMIELF = MMI->getObjFileInfo<MachineModuleInfoELF>();
00577 
00578     // Output stubs for external and common global variables.
00579     MachineModuleInfoELF::SymbolListTy Stubs = MMIELF.GetGVStubList();
00580     if (!Stubs.empty()) {
00581       OutStreamer.SwitchSection(TLOFELF.getDataRelSection());
00582       const DataLayout *TD = TM.getSubtargetImpl()->getDataLayout();
00583 
00584       for (auto &stub: Stubs) {
00585         OutStreamer.EmitLabel(stub.first);
00586         OutStreamer.EmitSymbolValue(stub.second.getPointer(),
00587                                     TD->getPointerSize(0));
00588       }
00589       Stubs.clear();
00590     }
00591   }
00592 }
00593 
00594 //===----------------------------------------------------------------------===//
00595 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
00596 // FIXME:
00597 // The following seem like one-off assembler flags, but they actually need
00598 // to appear in the .ARM.attributes section in ELF.
00599 // Instead of subclassing the MCELFStreamer, we do the work here.
00600 
00601 static ARMBuildAttrs::CPUArch getArchForCPU(StringRef CPU,
00602                                             const ARMSubtarget *Subtarget) {
00603   if (CPU == "xscale")
00604     return ARMBuildAttrs::v5TEJ;
00605 
00606   if (Subtarget->hasV8Ops())
00607     return ARMBuildAttrs::v8;
00608   else if (Subtarget->hasV7Ops()) {
00609     if (Subtarget->isMClass() && Subtarget->hasThumb2DSP())
00610       return ARMBuildAttrs::v7E_M;
00611     return ARMBuildAttrs::v7;
00612   } else if (Subtarget->hasV6T2Ops())
00613     return ARMBuildAttrs::v6T2;
00614   else if (Subtarget->hasV6MOps())
00615     return ARMBuildAttrs::v6S_M;
00616   else if (Subtarget->hasV6Ops())
00617     return ARMBuildAttrs::v6;
00618   else if (Subtarget->hasV5TEOps())
00619     return ARMBuildAttrs::v5TE;
00620   else if (Subtarget->hasV5TOps())
00621     return ARMBuildAttrs::v5T;
00622   else if (Subtarget->hasV4TOps())
00623     return ARMBuildAttrs::v4T;
00624   else
00625     return ARMBuildAttrs::v4;
00626 }
00627 
00628 void ARMAsmPrinter::emitAttributes() {
00629   MCTargetStreamer &TS = *OutStreamer.getTargetStreamer();
00630   ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
00631 
00632   ATS.switchVendor("aeabi");
00633 
00634   std::string CPUString = Subtarget->getCPUString();
00635 
00636   // FIXME: remove krait check when GNU tools support krait cpu
00637   if (CPUString != "generic" && CPUString != "krait")
00638     ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, CPUString);
00639 
00640   ATS.emitAttribute(ARMBuildAttrs::CPU_arch,
00641                     getArchForCPU(CPUString, Subtarget));
00642 
00643   // Tag_CPU_arch_profile must have the default value of 0 when "Architecture
00644   // profile is not applicable (e.g. pre v7, or cross-profile code)".
00645   if (Subtarget->hasV7Ops()) {
00646     if (Subtarget->isAClass()) {
00647       ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
00648                         ARMBuildAttrs::ApplicationProfile);
00649     } else if (Subtarget->isRClass()) {
00650       ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
00651                         ARMBuildAttrs::RealTimeProfile);
00652     } else if (Subtarget->isMClass()) {
00653       ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
00654                         ARMBuildAttrs::MicroControllerProfile);
00655     }
00656   }
00657 
00658   ATS.emitAttribute(ARMBuildAttrs::ARM_ISA_use, Subtarget->hasARMOps() ?
00659                       ARMBuildAttrs::Allowed : ARMBuildAttrs::Not_Allowed);
00660   if (Subtarget->isThumb1Only()) {
00661     ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
00662                       ARMBuildAttrs::Allowed);
00663   } else if (Subtarget->hasThumb2()) {
00664     ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
00665                       ARMBuildAttrs::AllowThumb32);
00666   }
00667 
00668   if (Subtarget->hasNEON()) {
00669     /* NEON is not exactly a VFP architecture, but GAS emit one of
00670      * neon/neon-fp-armv8/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
00671     if (Subtarget->hasFPARMv8()) {
00672       if (Subtarget->hasCrypto())
00673         ATS.emitFPU(ARM::CRYPTO_NEON_FP_ARMV8);
00674       else
00675         ATS.emitFPU(ARM::NEON_FP_ARMV8);
00676     }
00677     else if (Subtarget->hasVFP4())
00678       ATS.emitFPU(ARM::NEON_VFPV4);
00679     else
00680       ATS.emitFPU(ARM::NEON);
00681     // Emit Tag_Advanced_SIMD_arch for ARMv8 architecture
00682     if (Subtarget->hasV8Ops())
00683       ATS.emitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
00684                         ARMBuildAttrs::AllowNeonARMv8);
00685   } else {
00686     if (Subtarget->hasFPARMv8())
00687       // FPv5 and FP-ARMv8 have the same instructions, so are modeled as one
00688       // FPU, but there are two different names for it depending on the CPU.
00689       ATS.emitFPU(Subtarget->hasD16() ? ARM::FPV5_D16 : ARM::FP_ARMV8);
00690     else if (Subtarget->hasVFP4())
00691       ATS.emitFPU(Subtarget->hasD16() ? ARM::VFPV4_D16 : ARM::VFPV4);
00692     else if (Subtarget->hasVFP3())
00693       ATS.emitFPU(Subtarget->hasD16() ? ARM::VFPV3_D16 : ARM::VFPV3);
00694     else if (Subtarget->hasVFP2())
00695       ATS.emitFPU(ARM::VFPV2);
00696   }
00697 
00698   if (TM.getRelocationModel() == Reloc::PIC_) {
00699     // PIC specific attributes.
00700     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RW_data,
00701                       ARMBuildAttrs::AddressRWPCRel);
00702     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RO_data,
00703                       ARMBuildAttrs::AddressROPCRel);
00704     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_GOT_use,
00705                       ARMBuildAttrs::AddressGOT);
00706   } else {
00707     // Allow direct addressing of imported data for all other relocation models.
00708     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_GOT_use,
00709                       ARMBuildAttrs::AddressDirect);
00710   }
00711 
00712   // Signal various FP modes.
00713   if (!TM.Options.UnsafeFPMath) {
00714     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
00715                       ARMBuildAttrs::IEEEDenormals);
00716     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
00717                       ARMBuildAttrs::Allowed);
00718 
00719     // If the user has permitted this code to choose the IEEE 754
00720     // rounding at run-time, emit the rounding attribute.
00721     if (TM.Options.HonorSignDependentRoundingFPMathOption)
00722       ATS.emitAttribute(ARMBuildAttrs::ABI_FP_rounding,
00723                         ARMBuildAttrs::Allowed);
00724   } else {
00725     if (!Subtarget->hasVFP2()) {
00726       // When the target doesn't have an FPU (by design or
00727       // intention), the assumptions made on the software support
00728       // mirror that of the equivalent hardware support *if it
00729       // existed*. For v7 and better we indicate that denormals are
00730       // flushed preserving sign, and for V6 we indicate that
00731       // denormals are flushed to positive zero.
00732       if (Subtarget->hasV7Ops())
00733         ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
00734                           ARMBuildAttrs::PreserveFPSign);
00735     } else if (Subtarget->hasVFP3()) {
00736       // In VFPv4, VFPv4U, VFPv3, or VFPv3U, it is preserved. That is,
00737       // the sign bit of the zero matches the sign bit of the input or
00738       // result that is being flushed to zero.
00739       ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
00740                         ARMBuildAttrs::PreserveFPSign);
00741     }
00742     // For VFPv2 implementations it is implementation defined as
00743     // to whether denormals are flushed to positive zero or to
00744     // whatever the sign of zero is (ARM v7AR ARM 2.7.5). Historically
00745     // LLVM has chosen to flush this to positive zero (most likely for
00746     // GCC compatibility), so that's the chosen value here (the
00747     // absence of its emission implies zero).
00748   }
00749 
00750   // TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath is the
00751   // equivalent of GCC's -ffinite-math-only flag.
00752   if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
00753     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
00754                       ARMBuildAttrs::Allowed);
00755   else
00756     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
00757                       ARMBuildAttrs::AllowIEE754);
00758 
00759   if (Subtarget->allowsUnalignedMem())
00760     ATS.emitAttribute(ARMBuildAttrs::CPU_unaligned_access,
00761                       ARMBuildAttrs::Allowed);
00762   else
00763     ATS.emitAttribute(ARMBuildAttrs::CPU_unaligned_access,
00764                       ARMBuildAttrs::Not_Allowed);
00765 
00766   // FIXME: add more flags to ARMBuildAttributes.h
00767   // 8-bytes alignment stuff.
00768   ATS.emitAttribute(ARMBuildAttrs::ABI_align_needed, 1);
00769   ATS.emitAttribute(ARMBuildAttrs::ABI_align_preserved, 1);
00770 
00771   // ABI_HardFP_use attribute to indicate single precision FP.
00772   if (Subtarget->isFPOnlySP())
00773     ATS.emitAttribute(ARMBuildAttrs::ABI_HardFP_use,
00774                       ARMBuildAttrs::HardFPSinglePrecision);
00775 
00776   // Hard float.  Use both S and D registers and conform to AAPCS-VFP.
00777   if (Subtarget->isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard)
00778     ATS.emitAttribute(ARMBuildAttrs::ABI_VFP_args, ARMBuildAttrs::HardFPAAPCS);
00779 
00780   // FIXME: Should we signal R9 usage?
00781 
00782   if (Subtarget->hasFP16())
00783       ATS.emitAttribute(ARMBuildAttrs::FP_HP_extension, ARMBuildAttrs::AllowHPFP);
00784 
00785   // FIXME: To support emitting this build attribute as GCC does, the
00786   // -mfp16-format option and associated plumbing must be
00787   // supported. For now the __fp16 type is exposed by default, so this
00788   // attribute should be emitted with value 1.
00789   ATS.emitAttribute(ARMBuildAttrs::ABI_FP_16bit_format,
00790                     ARMBuildAttrs::FP16FormatIEEE);
00791 
00792   if (Subtarget->hasMPExtension())
00793       ATS.emitAttribute(ARMBuildAttrs::MPextension_use, ARMBuildAttrs::AllowMP);
00794 
00795   // Hardware divide in ARM mode is part of base arch, starting from ARMv8.
00796   // If only Thumb hwdiv is present, it must also be in base arch (ARMv7-R/M).
00797   // It is not possible to produce DisallowDIV: if hwdiv is present in the base
00798   // arch, supplying -hwdiv downgrades the effective arch, via ClearImpliedBits.
00799   // AllowDIVExt is only emitted if hwdiv isn't available in the base arch;
00800   // otherwise, the default value (AllowDIVIfExists) applies.
00801   if (Subtarget->hasDivideInARMMode() && !Subtarget->hasV8Ops())
00802       ATS.emitAttribute(ARMBuildAttrs::DIV_use, ARMBuildAttrs::AllowDIVExt);
00803 
00804   if (MMI) {
00805     if (const Module *SourceModule = MMI->getModule()) {
00806       // ABI_PCS_wchar_t to indicate wchar_t width
00807       // FIXME: There is no way to emit value 0 (wchar_t prohibited).
00808       if (auto WCharWidthValue = mdconst::extract_or_null<ConstantInt>(
00809               SourceModule->getModuleFlag("wchar_size"))) {
00810         int WCharWidth = WCharWidthValue->getZExtValue();
00811         assert((WCharWidth == 2 || WCharWidth == 4) &&
00812                "wchar_t width must be 2 or 4 bytes");
00813         ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_wchar_t, WCharWidth);
00814       }
00815 
00816       // ABI_enum_size to indicate enum width
00817       // FIXME: There is no way to emit value 0 (enums prohibited) or value 3
00818       //        (all enums contain a value needing 32 bits to encode).
00819       if (auto EnumWidthValue = mdconst::extract_or_null<ConstantInt>(
00820               SourceModule->getModuleFlag("min_enum_size"))) {
00821         int EnumWidth = EnumWidthValue->getZExtValue();
00822         assert((EnumWidth == 1 || EnumWidth == 4) &&
00823                "Minimum enum width must be 1 or 4 bytes");
00824         int EnumBuildAttr = EnumWidth == 1 ? 1 : 2;
00825         ATS.emitAttribute(ARMBuildAttrs::ABI_enum_size, EnumBuildAttr);
00826       }
00827     }
00828   }
00829 
00830   // TODO: We currently only support either reserving the register, or treating
00831   // it as another callee-saved register, but not as SB or a TLS pointer; It
00832   // would instead be nicer to push this from the frontend as metadata, as we do
00833   // for the wchar and enum size tags
00834   if (Subtarget->isR9Reserved())
00835       ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use,
00836                         ARMBuildAttrs::R9Reserved);
00837   else
00838       ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use,
00839                         ARMBuildAttrs::R9IsGPR);
00840 
00841   if (Subtarget->hasTrustZone() && Subtarget->hasVirtualization())
00842       ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
00843                         ARMBuildAttrs::AllowTZVirtualization);
00844   else if (Subtarget->hasTrustZone())
00845       ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
00846                         ARMBuildAttrs::AllowTZ);
00847   else if (Subtarget->hasVirtualization())
00848       ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
00849                         ARMBuildAttrs::AllowVirtualization);
00850 
00851   ATS.finishAttributeSection();
00852 }
00853 
00854 //===----------------------------------------------------------------------===//
00855 
00856 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
00857                              unsigned LabelId, MCContext &Ctx) {
00858 
00859   MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
00860                        + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
00861   return Label;
00862 }
00863 
00864 static MCSymbolRefExpr::VariantKind
00865 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
00866   switch (Modifier) {
00867   case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
00868   case ARMCP::TLSGD:       return MCSymbolRefExpr::VK_TLSGD;
00869   case ARMCP::TPOFF:       return MCSymbolRefExpr::VK_TPOFF;
00870   case ARMCP::GOTTPOFF:    return MCSymbolRefExpr::VK_GOTTPOFF;
00871   case ARMCP::GOT:         return MCSymbolRefExpr::VK_GOT;
00872   case ARMCP::GOTOFF:      return MCSymbolRefExpr::VK_GOTOFF;
00873   }
00874   llvm_unreachable("Invalid ARMCPModifier!");
00875 }
00876 
00877 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV,
00878                                         unsigned char TargetFlags) {
00879   if (Subtarget->isTargetMachO()) {
00880     bool IsIndirect = (TargetFlags & ARMII::MO_NONLAZY) &&
00881       Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
00882 
00883     if (!IsIndirect)
00884       return getSymbol(GV);
00885 
00886     // FIXME: Remove this when Darwin transition to @GOT like syntax.
00887     MCSymbol *MCSym = getSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
00888     MachineModuleInfoMachO &MMIMachO =
00889       MMI->getObjFileInfo<MachineModuleInfoMachO>();
00890     MachineModuleInfoImpl::StubValueTy &StubSym =
00891       GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym)
00892                                 : MMIMachO.getGVStubEntry(MCSym);
00893     if (!StubSym.getPointer())
00894       StubSym = MachineModuleInfoImpl::StubValueTy(getSymbol(GV),
00895                                                    !GV->hasInternalLinkage());
00896     return MCSym;
00897   } else if (Subtarget->isTargetCOFF()) {
00898     assert(Subtarget->isTargetWindows() &&
00899            "Windows is the only supported COFF target");
00900 
00901     bool IsIndirect = (TargetFlags & ARMII::MO_DLLIMPORT);
00902     if (!IsIndirect)
00903       return getSymbol(GV);
00904 
00905     SmallString<128> Name;
00906     Name = "__imp_";
00907     getNameWithPrefix(Name, GV);
00908 
00909     return OutContext.GetOrCreateSymbol(Name);
00910   } else if (Subtarget->isTargetELF()) {
00911     return getSymbol(GV);
00912   }
00913   llvm_unreachable("unexpected target");
00914 }
00915 
00916 void ARMAsmPrinter::
00917 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
00918   const DataLayout *DL = TM.getSubtargetImpl()->getDataLayout();
00919   int Size =
00920       TM.getSubtargetImpl()->getDataLayout()->getTypeAllocSize(MCPV->getType());
00921 
00922   ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
00923 
00924   MCSymbol *MCSym;
00925   if (ACPV->isLSDA()) {
00926     SmallString<128> Str;
00927     raw_svector_ostream OS(Str);
00928     OS << DL->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
00929     MCSym = OutContext.GetOrCreateSymbol(OS.str());
00930   } else if (ACPV->isBlockAddress()) {
00931     const BlockAddress *BA =
00932       cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
00933     MCSym = GetBlockAddressSymbol(BA);
00934   } else if (ACPV->isGlobalValue()) {
00935     const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
00936 
00937     // On Darwin, const-pool entries may get the "FOO$non_lazy_ptr" mangling, so
00938     // flag the global as MO_NONLAZY.
00939     unsigned char TF = Subtarget->isTargetMachO() ? ARMII::MO_NONLAZY : 0;
00940     MCSym = GetARMGVSymbol(GV, TF);
00941   } else if (ACPV->isMachineBasicBlock()) {
00942     const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
00943     MCSym = MBB->getSymbol();
00944   } else {
00945     assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
00946     const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
00947     MCSym = GetExternalSymbolSymbol(Sym);
00948   }
00949 
00950   // Create an MCSymbol for the reference.
00951   const MCExpr *Expr =
00952     MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
00953                             OutContext);
00954 
00955   if (ACPV->getPCAdjustment()) {
00956     MCSymbol *PCLabel = getPICLabel(DL->getPrivateGlobalPrefix(),
00957                                     getFunctionNumber(),
00958                                     ACPV->getLabelId(),
00959                                     OutContext);
00960     const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
00961     PCRelExpr =
00962       MCBinaryExpr::CreateAdd(PCRelExpr,
00963                               MCConstantExpr::Create(ACPV->getPCAdjustment(),
00964                                                      OutContext),
00965                               OutContext);
00966     if (ACPV->mustAddCurrentAddress()) {
00967       // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
00968       // label, so just emit a local label end reference that instead.
00969       MCSymbol *DotSym = OutContext.CreateTempSymbol();
00970       OutStreamer.EmitLabel(DotSym);
00971       const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
00972       PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
00973     }
00974     Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
00975   }
00976   OutStreamer.EmitValue(Expr, Size);
00977 }
00978 
00979 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
00980   unsigned Opcode = MI->getOpcode();
00981   int OpNum = 1;
00982   if (Opcode == ARM::BR_JTadd)
00983     OpNum = 2;
00984   else if (Opcode == ARM::BR_JTm)
00985     OpNum = 3;
00986 
00987   const MachineOperand &MO1 = MI->getOperand(OpNum);
00988   const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
00989   unsigned JTI = MO1.getIndex();
00990 
00991   // Emit a label for the jump table.
00992   MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
00993   OutStreamer.EmitLabel(JTISymbol);
00994 
00995   // Mark the jump table as data-in-code.
00996   OutStreamer.EmitDataRegion(MCDR_DataRegionJT32);
00997 
00998   // Emit each entry of the table.
00999   const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
01000   const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
01001   const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
01002 
01003   for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
01004     MachineBasicBlock *MBB = JTBBs[i];
01005     // Construct an MCExpr for the entry. We want a value of the form:
01006     // (BasicBlockAddr - TableBeginAddr)
01007     //
01008     // For example, a table with entries jumping to basic blocks BB0 and BB1
01009     // would look like:
01010     // LJTI_0_0:
01011     //    .word (LBB0 - LJTI_0_0)
01012     //    .word (LBB1 - LJTI_0_0)
01013     const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
01014 
01015     if (TM.getRelocationModel() == Reloc::PIC_)
01016       Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
01017                                                                    OutContext),
01018                                      OutContext);
01019     // If we're generating a table of Thumb addresses in static relocation
01020     // model, we need to add one to keep interworking correctly.
01021     else if (AFI->isThumbFunction())
01022       Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(1,OutContext),
01023                                      OutContext);
01024     OutStreamer.EmitValue(Expr, 4);
01025   }
01026   // Mark the end of jump table data-in-code region.
01027   OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
01028 }
01029 
01030 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
01031   unsigned Opcode = MI->getOpcode();
01032   int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
01033   const MachineOperand &MO1 = MI->getOperand(OpNum);
01034   const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
01035   unsigned JTI = MO1.getIndex();
01036 
01037   MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
01038   OutStreamer.EmitLabel(JTISymbol);
01039 
01040   // Emit each entry of the table.
01041   const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
01042   const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
01043   const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
01044   unsigned OffsetWidth = 4;
01045   if (MI->getOpcode() == ARM::t2TBB_JT) {
01046     OffsetWidth = 1;
01047     // Mark the jump table as data-in-code.
01048     OutStreamer.EmitDataRegion(MCDR_DataRegionJT8);
01049   } else if (MI->getOpcode() == ARM::t2TBH_JT) {
01050     OffsetWidth = 2;
01051     // Mark the jump table as data-in-code.
01052     OutStreamer.EmitDataRegion(MCDR_DataRegionJT16);
01053   }
01054 
01055   for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
01056     MachineBasicBlock *MBB = JTBBs[i];
01057     const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
01058                                                           OutContext);
01059     // If this isn't a TBB or TBH, the entries are direct branch instructions.
01060     if (OffsetWidth == 4) {
01061       EmitToStreamer(OutStreamer, MCInstBuilder(ARM::t2B)
01062         .addExpr(MBBSymbolExpr)
01063         .addImm(ARMCC::AL)
01064         .addReg(0));
01065       continue;
01066     }
01067     // Otherwise it's an offset from the dispatch instruction. Construct an
01068     // MCExpr for the entry. We want a value of the form:
01069     // (BasicBlockAddr - TableBeginAddr) / 2
01070     //
01071     // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
01072     // would look like:
01073     // LJTI_0_0:
01074     //    .byte (LBB0 - LJTI_0_0) / 2
01075     //    .byte (LBB1 - LJTI_0_0) / 2
01076     const MCExpr *Expr =
01077       MCBinaryExpr::CreateSub(MBBSymbolExpr,
01078                               MCSymbolRefExpr::Create(JTISymbol, OutContext),
01079                               OutContext);
01080     Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
01081                                    OutContext);
01082     OutStreamer.EmitValue(Expr, OffsetWidth);
01083   }
01084   // Mark the end of jump table data-in-code region. 32-bit offsets use
01085   // actual branch instructions here, so we don't mark those as a data-region
01086   // at all.
01087   if (OffsetWidth != 4)
01088     OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
01089 }
01090 
01091 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
01092   assert(MI->getFlag(MachineInstr::FrameSetup) &&
01093       "Only instruction which are involved into frame setup code are allowed");
01094 
01095   MCTargetStreamer &TS = *OutStreamer.getTargetStreamer();
01096   ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
01097   const MachineFunction &MF = *MI->getParent()->getParent();
01098   const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
01099   const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
01100 
01101   unsigned FramePtr = RegInfo->getFrameRegister(MF);
01102   unsigned Opc = MI->getOpcode();
01103   unsigned SrcReg, DstReg;
01104 
01105   if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
01106     // Two special cases:
01107     // 1) tPUSH does not have src/dst regs.
01108     // 2) for Thumb1 code we sometimes materialize the constant via constpool
01109     // load. Yes, this is pretty fragile, but for now I don't see better
01110     // way... :(
01111     SrcReg = DstReg = ARM::SP;
01112   } else {
01113     SrcReg = MI->getOperand(1).getReg();
01114     DstReg = MI->getOperand(0).getReg();
01115   }
01116 
01117   // Try to figure out the unwinding opcode out of src / dst regs.
01118   if (MI->mayStore()) {
01119     // Register saves.
01120     assert(DstReg == ARM::SP &&
01121            "Only stack pointer as a destination reg is supported");
01122 
01123     SmallVector<unsigned, 4> RegList;
01124     // Skip src & dst reg, and pred ops.
01125     unsigned StartOp = 2 + 2;
01126     // Use all the operands.
01127     unsigned NumOffset = 0;
01128 
01129     switch (Opc) {
01130     default:
01131       MI->dump();
01132       llvm_unreachable("Unsupported opcode for unwinding information");
01133     case ARM::tPUSH:
01134       // Special case here: no src & dst reg, but two extra imp ops.
01135       StartOp = 2; NumOffset = 2;
01136     case ARM::STMDB_UPD:
01137     case ARM::t2STMDB_UPD:
01138     case ARM::VSTMDDB_UPD:
01139       assert(SrcReg == ARM::SP &&
01140              "Only stack pointer as a source reg is supported");
01141       for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
01142            i != NumOps; ++i) {
01143         const MachineOperand &MO = MI->getOperand(i);
01144         // Actually, there should never be any impdef stuff here. Skip it
01145         // temporary to workaround PR11902.
01146         if (MO.isImplicit())
01147           continue;
01148         RegList.push_back(MO.getReg());
01149       }
01150       break;
01151     case ARM::STR_PRE_IMM:
01152     case ARM::STR_PRE_REG:
01153     case ARM::t2STR_PRE:
01154       assert(MI->getOperand(2).getReg() == ARM::SP &&
01155              "Only stack pointer as a source reg is supported");
01156       RegList.push_back(SrcReg);
01157       break;
01158     }
01159     if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM)
01160       ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
01161   } else {
01162     // Changes of stack / frame pointer.
01163     if (SrcReg == ARM::SP) {
01164       int64_t Offset = 0;
01165       switch (Opc) {
01166       default:
01167         MI->dump();
01168         llvm_unreachable("Unsupported opcode for unwinding information");
01169       case ARM::MOVr:
01170       case ARM::tMOVr:
01171         Offset = 0;
01172         break;
01173       case ARM::ADDri:
01174         Offset = -MI->getOperand(2).getImm();
01175         break;
01176       case ARM::SUBri:
01177       case ARM::t2SUBri:
01178         Offset = MI->getOperand(2).getImm();
01179         break;
01180       case ARM::tSUBspi:
01181         Offset = MI->getOperand(2).getImm()*4;
01182         break;
01183       case ARM::tADDspi:
01184       case ARM::tADDrSPi:
01185         Offset = -MI->getOperand(2).getImm()*4;
01186         break;
01187       case ARM::tLDRpci: {
01188         // Grab the constpool index and check, whether it corresponds to
01189         // original or cloned constpool entry.
01190         unsigned CPI = MI->getOperand(1).getIndex();
01191         const MachineConstantPool *MCP = MF.getConstantPool();
01192         if (CPI >= MCP->getConstants().size())
01193           CPI = AFI.getOriginalCPIdx(CPI);
01194         assert(CPI != -1U && "Invalid constpool index");
01195 
01196         // Derive the actual offset.
01197         const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
01198         assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
01199         // FIXME: Check for user, it should be "add" instruction!
01200         Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
01201         break;
01202       }
01203       }
01204 
01205       if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM) {
01206         if (DstReg == FramePtr && FramePtr != ARM::SP)
01207           // Set-up of the frame pointer. Positive values correspond to "add"
01208           // instruction.
01209           ATS.emitSetFP(FramePtr, ARM::SP, -Offset);
01210         else if (DstReg == ARM::SP) {
01211           // Change of SP by an offset. Positive values correspond to "sub"
01212           // instruction.
01213           ATS.emitPad(Offset);
01214         } else {
01215           // Move of SP to a register.  Positive values correspond to an "add"
01216           // instruction.
01217           ATS.emitMovSP(DstReg, -Offset);
01218         }
01219       }
01220     } else if (DstReg == ARM::SP) {
01221       MI->dump();
01222       llvm_unreachable("Unsupported opcode for unwinding information");
01223     }
01224     else {
01225       MI->dump();
01226       llvm_unreachable("Unsupported opcode for unwinding information");
01227     }
01228   }
01229 }
01230 
01231 // Simple pseudo-instructions have their lowering (with expansion to real
01232 // instructions) auto-generated.
01233 #include "ARMGenMCPseudoLowering.inc"
01234 
01235 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
01236   const DataLayout *DL = TM.getSubtargetImpl()->getDataLayout();
01237 
01238   // If we just ended a constant pool, mark it as such.
01239   if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
01240     OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
01241     InConstantPool = false;
01242   }
01243 
01244   // Emit unwinding stuff for frame-related instructions
01245   if (Subtarget->isTargetEHABICompatible() &&
01246        MI->getFlag(MachineInstr::FrameSetup))
01247     EmitUnwindingInstruction(MI);
01248 
01249   // Do any auto-generated pseudo lowerings.
01250   if (emitPseudoExpansionLowering(OutStreamer, MI))
01251     return;
01252 
01253   assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
01254          "Pseudo flag setting opcode should be expanded early");
01255 
01256   // Check for manual lowerings.
01257   unsigned Opc = MI->getOpcode();
01258   switch (Opc) {
01259   case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
01260   case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing");
01261   case ARM::LEApcrel:
01262   case ARM::tLEApcrel:
01263   case ARM::t2LEApcrel: {
01264     // FIXME: Need to also handle globals and externals
01265     MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex());
01266     EmitToStreamer(OutStreamer, MCInstBuilder(MI->getOpcode() ==
01267                                               ARM::t2LEApcrel ? ARM::t2ADR
01268                   : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
01269                      : ARM::ADR))
01270       .addReg(MI->getOperand(0).getReg())
01271       .addExpr(MCSymbolRefExpr::Create(CPISymbol, OutContext))
01272       // Add predicate operands.
01273       .addImm(MI->getOperand(2).getImm())
01274       .addReg(MI->getOperand(3).getReg()));
01275     return;
01276   }
01277   case ARM::LEApcrelJT:
01278   case ARM::tLEApcrelJT:
01279   case ARM::t2LEApcrelJT: {
01280     MCSymbol *JTIPICSymbol =
01281       GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
01282                                   MI->getOperand(2).getImm());
01283     EmitToStreamer(OutStreamer, MCInstBuilder(MI->getOpcode() ==
01284                                               ARM::t2LEApcrelJT ? ARM::t2ADR
01285                   : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
01286                      : ARM::ADR))
01287       .addReg(MI->getOperand(0).getReg())
01288       .addExpr(MCSymbolRefExpr::Create(JTIPICSymbol, OutContext))
01289       // Add predicate operands.
01290       .addImm(MI->getOperand(3).getImm())
01291       .addReg(MI->getOperand(4).getReg()));
01292     return;
01293   }
01294   // Darwin call instructions are just normal call instructions with different
01295   // clobber semantics (they clobber R9).
01296   case ARM::BX_CALL: {
01297     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
01298       .addReg(ARM::LR)
01299       .addReg(ARM::PC)
01300       // Add predicate operands.
01301       .addImm(ARMCC::AL)
01302       .addReg(0)
01303       // Add 's' bit operand (always reg0 for this)
01304       .addReg(0));
01305 
01306     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::BX)
01307       .addReg(MI->getOperand(0).getReg()));
01308     return;
01309   }
01310   case ARM::tBX_CALL: {
01311     if (Subtarget->hasV5TOps())
01312       llvm_unreachable("Expected BLX to be selected for v5t+");
01313 
01314     // On ARM v4t, when doing a call from thumb mode, we need to ensure
01315     // that the saved lr has its LSB set correctly (the arch doesn't
01316     // have blx).
01317     // So here we generate a bl to a small jump pad that does bx rN.
01318     // The jump pads are emitted after the function body.
01319 
01320     unsigned TReg = MI->getOperand(0).getReg();
01321     MCSymbol *TRegSym = nullptr;
01322     for (unsigned i = 0, e = ThumbIndirectPads.size(); i < e; i++) {
01323       if (ThumbIndirectPads[i].first == TReg) {
01324         TRegSym = ThumbIndirectPads[i].second;
01325         break;
01326       }
01327     }
01328 
01329     if (!TRegSym) {
01330       TRegSym = OutContext.CreateTempSymbol();
01331       ThumbIndirectPads.push_back(std::make_pair(TReg, TRegSym));
01332     }
01333 
01334     // Create a link-saving branch to the Reg Indirect Jump Pad.
01335     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tBL)
01336         // Predicate comes first here.
01337         .addImm(ARMCC::AL).addReg(0)
01338         .addExpr(MCSymbolRefExpr::Create(TRegSym, OutContext)));
01339     return;
01340   }
01341   case ARM::BMOVPCRX_CALL: {
01342     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
01343       .addReg(ARM::LR)
01344       .addReg(ARM::PC)
01345       // Add predicate operands.
01346       .addImm(ARMCC::AL)
01347       .addReg(0)
01348       // Add 's' bit operand (always reg0 for this)
01349       .addReg(0));
01350 
01351     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
01352       .addReg(ARM::PC)
01353       .addReg(MI->getOperand(0).getReg())
01354       // Add predicate operands.
01355       .addImm(ARMCC::AL)
01356       .addReg(0)
01357       // Add 's' bit operand (always reg0 for this)
01358       .addReg(0));
01359     return;
01360   }
01361   case ARM::BMOVPCB_CALL: {
01362     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
01363       .addReg(ARM::LR)
01364       .addReg(ARM::PC)
01365       // Add predicate operands.
01366       .addImm(ARMCC::AL)
01367       .addReg(0)
01368       // Add 's' bit operand (always reg0 for this)
01369       .addReg(0));
01370 
01371     const MachineOperand &Op = MI->getOperand(0);
01372     const GlobalValue *GV = Op.getGlobal();
01373     const unsigned TF = Op.getTargetFlags();
01374     MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
01375     const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
01376     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::Bcc)
01377       .addExpr(GVSymExpr)
01378       // Add predicate operands.
01379       .addImm(ARMCC::AL)
01380       .addReg(0));
01381     return;
01382   }
01383   case ARM::MOVi16_ga_pcrel:
01384   case ARM::t2MOVi16_ga_pcrel: {
01385     MCInst TmpInst;
01386     TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
01387     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
01388 
01389     unsigned TF = MI->getOperand(1).getTargetFlags();
01390     const GlobalValue *GV = MI->getOperand(1).getGlobal();
01391     MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
01392     const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
01393 
01394     MCSymbol *LabelSym = getPICLabel(DL->getPrivateGlobalPrefix(),
01395                                      getFunctionNumber(),
01396                                      MI->getOperand(2).getImm(), OutContext);
01397     const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
01398     unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
01399     const MCExpr *PCRelExpr =
01400       ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
01401                                       MCBinaryExpr::CreateAdd(LabelSymExpr,
01402                                       MCConstantExpr::Create(PCAdj, OutContext),
01403                                       OutContext), OutContext), OutContext);
01404       TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
01405 
01406     // Add predicate operands.
01407     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
01408     TmpInst.addOperand(MCOperand::CreateReg(0));
01409     // Add 's' bit operand (always reg0 for this)
01410     TmpInst.addOperand(MCOperand::CreateReg(0));
01411     EmitToStreamer(OutStreamer, TmpInst);
01412     return;
01413   }
01414   case ARM::MOVTi16_ga_pcrel:
01415   case ARM::t2MOVTi16_ga_pcrel: {
01416     MCInst TmpInst;
01417     TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
01418                       ? ARM::MOVTi16 : ARM::t2MOVTi16);
01419     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
01420     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
01421 
01422     unsigned TF = MI->getOperand(2).getTargetFlags();
01423     const GlobalValue *GV = MI->getOperand(2).getGlobal();
01424     MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
01425     const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
01426 
01427     MCSymbol *LabelSym = getPICLabel(DL->getPrivateGlobalPrefix(),
01428                                      getFunctionNumber(),
01429                                      MI->getOperand(3).getImm(), OutContext);
01430     const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
01431     unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
01432     const MCExpr *PCRelExpr =
01433         ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
01434                                    MCBinaryExpr::CreateAdd(LabelSymExpr,
01435                                       MCConstantExpr::Create(PCAdj, OutContext),
01436                                           OutContext), OutContext), OutContext);
01437       TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
01438     // Add predicate operands.
01439     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
01440     TmpInst.addOperand(MCOperand::CreateReg(0));
01441     // Add 's' bit operand (always reg0 for this)
01442     TmpInst.addOperand(MCOperand::CreateReg(0));
01443     EmitToStreamer(OutStreamer, TmpInst);
01444     return;
01445   }
01446   case ARM::tPICADD: {
01447     // This is a pseudo op for a label + instruction sequence, which looks like:
01448     // LPC0:
01449     //     add r0, pc
01450     // This adds the address of LPC0 to r0.
01451 
01452     // Emit the label.
01453     OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
01454                           getFunctionNumber(), MI->getOperand(2).getImm(),
01455                           OutContext));
01456 
01457     // Form and emit the add.
01458     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tADDhirr)
01459       .addReg(MI->getOperand(0).getReg())
01460       .addReg(MI->getOperand(0).getReg())
01461       .addReg(ARM::PC)
01462       // Add predicate operands.
01463       .addImm(ARMCC::AL)
01464       .addReg(0));
01465     return;
01466   }
01467   case ARM::PICADD: {
01468     // This is a pseudo op for a label + instruction sequence, which looks like:
01469     // LPC0:
01470     //     add r0, pc, r0
01471     // This adds the address of LPC0 to r0.
01472 
01473     // Emit the label.
01474     OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
01475                           getFunctionNumber(), MI->getOperand(2).getImm(),
01476                           OutContext));
01477 
01478     // Form and emit the add.
01479     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDrr)
01480       .addReg(MI->getOperand(0).getReg())
01481       .addReg(ARM::PC)
01482       .addReg(MI->getOperand(1).getReg())
01483       // Add predicate operands.
01484       .addImm(MI->getOperand(3).getImm())
01485       .addReg(MI->getOperand(4).getReg())
01486       // Add 's' bit operand (always reg0 for this)
01487       .addReg(0));
01488     return;
01489   }
01490   case ARM::PICSTR:
01491   case ARM::PICSTRB:
01492   case ARM::PICSTRH:
01493   case ARM::PICLDR:
01494   case ARM::PICLDRB:
01495   case ARM::PICLDRH:
01496   case ARM::PICLDRSB:
01497   case ARM::PICLDRSH: {
01498     // This is a pseudo op for a label + instruction sequence, which looks like:
01499     // LPC0:
01500     //     OP r0, [pc, r0]
01501     // The LCP0 label is referenced by a constant pool entry in order to get
01502     // a PC-relative address at the ldr instruction.
01503 
01504     // Emit the label.
01505     OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
01506                           getFunctionNumber(), MI->getOperand(2).getImm(),
01507                           OutContext));
01508 
01509     // Form and emit the load
01510     unsigned Opcode;
01511     switch (MI->getOpcode()) {
01512     default:
01513       llvm_unreachable("Unexpected opcode!");
01514     case ARM::PICSTR:   Opcode = ARM::STRrs; break;
01515     case ARM::PICSTRB:  Opcode = ARM::STRBrs; break;
01516     case ARM::PICSTRH:  Opcode = ARM::STRH; break;
01517     case ARM::PICLDR:   Opcode = ARM::LDRrs; break;
01518     case ARM::PICLDRB:  Opcode = ARM::LDRBrs; break;
01519     case ARM::PICLDRH:  Opcode = ARM::LDRH; break;
01520     case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
01521     case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
01522     }
01523     EmitToStreamer(OutStreamer, MCInstBuilder(Opcode)
01524       .addReg(MI->getOperand(0).getReg())
01525       .addReg(ARM::PC)
01526       .addReg(MI->getOperand(1).getReg())
01527       .addImm(0)
01528       // Add predicate operands.
01529       .addImm(MI->getOperand(3).getImm())
01530       .addReg(MI->getOperand(4).getReg()));
01531 
01532     return;
01533   }
01534   case ARM::CONSTPOOL_ENTRY: {
01535     /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
01536     /// in the function.  The first operand is the ID# for this instruction, the
01537     /// second is the index into the MachineConstantPool that this is, the third
01538     /// is the size in bytes of this constant pool entry.
01539     /// The required alignment is specified on the basic block holding this MI.
01540     unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
01541     unsigned CPIdx   = (unsigned)MI->getOperand(1).getIndex();
01542 
01543     // If this is the first entry of the pool, mark it.
01544     if (!InConstantPool) {
01545       OutStreamer.EmitDataRegion(MCDR_DataRegion);
01546       InConstantPool = true;
01547     }
01548 
01549     OutStreamer.EmitLabel(GetCPISymbol(LabelId));
01550 
01551     const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
01552     if (MCPE.isMachineConstantPoolEntry())
01553       EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
01554     else
01555       EmitGlobalConstant(MCPE.Val.ConstVal);
01556     return;
01557   }
01558   case ARM::t2BR_JT: {
01559     // Lower and emit the instruction itself, then the jump table following it.
01560     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
01561       .addReg(ARM::PC)
01562       .addReg(MI->getOperand(0).getReg())
01563       // Add predicate operands.
01564       .addImm(ARMCC::AL)
01565       .addReg(0));
01566 
01567     // Output the data for the jump table itself
01568     EmitJump2Table(MI);
01569     return;
01570   }
01571   case ARM::t2TBB_JT: {
01572     // Lower and emit the instruction itself, then the jump table following it.
01573     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::t2TBB)
01574       .addReg(ARM::PC)
01575       .addReg(MI->getOperand(0).getReg())
01576       // Add predicate operands.
01577       .addImm(ARMCC::AL)
01578       .addReg(0));
01579 
01580     // Output the data for the jump table itself
01581     EmitJump2Table(MI);
01582     // Make sure the next instruction is 2-byte aligned.
01583     EmitAlignment(1);
01584     return;
01585   }
01586   case ARM::t2TBH_JT: {
01587     // Lower and emit the instruction itself, then the jump table following it.
01588     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::t2TBH)
01589       .addReg(ARM::PC)
01590       .addReg(MI->getOperand(0).getReg())
01591       // Add predicate operands.
01592       .addImm(ARMCC::AL)
01593       .addReg(0));
01594 
01595     // Output the data for the jump table itself
01596     EmitJump2Table(MI);
01597     return;
01598   }
01599   case ARM::tBR_JTr:
01600   case ARM::BR_JTr: {
01601     // Lower and emit the instruction itself, then the jump table following it.
01602     // mov pc, target
01603     MCInst TmpInst;
01604     unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
01605       ARM::MOVr : ARM::tMOVr;
01606     TmpInst.setOpcode(Opc);
01607     TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
01608     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
01609     // Add predicate operands.
01610     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
01611     TmpInst.addOperand(MCOperand::CreateReg(0));
01612     // Add 's' bit operand (always reg0 for this)
01613     if (Opc == ARM::MOVr)
01614       TmpInst.addOperand(MCOperand::CreateReg(0));
01615     EmitToStreamer(OutStreamer, TmpInst);
01616 
01617     // Make sure the Thumb jump table is 4-byte aligned.
01618     if (Opc == ARM::tMOVr)
01619       EmitAlignment(2);
01620 
01621     // Output the data for the jump table itself
01622     EmitJumpTable(MI);
01623     return;
01624   }
01625   case ARM::BR_JTm: {
01626     // Lower and emit the instruction itself, then the jump table following it.
01627     // ldr pc, target
01628     MCInst TmpInst;
01629     if (MI->getOperand(1).getReg() == 0) {
01630       // literal offset
01631       TmpInst.setOpcode(ARM::LDRi12);
01632       TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
01633       TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
01634       TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
01635     } else {
01636       TmpInst.setOpcode(ARM::LDRrs);
01637       TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
01638       TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
01639       TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
01640       TmpInst.addOperand(MCOperand::CreateImm(0));
01641     }
01642     // Add predicate operands.
01643     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
01644     TmpInst.addOperand(MCOperand::CreateReg(0));
01645     EmitToStreamer(OutStreamer, TmpInst);
01646 
01647     // Output the data for the jump table itself
01648     EmitJumpTable(MI);
01649     return;
01650   }
01651   case ARM::BR_JTadd: {
01652     // Lower and emit the instruction itself, then the jump table following it.
01653     // add pc, target, idx
01654     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDrr)
01655       .addReg(ARM::PC)
01656       .addReg(MI->getOperand(0).getReg())
01657       .addReg(MI->getOperand(1).getReg())
01658       // Add predicate operands.
01659       .addImm(ARMCC::AL)
01660       .addReg(0)
01661       // Add 's' bit operand (always reg0 for this)
01662       .addReg(0));
01663 
01664     // Output the data for the jump table itself
01665     EmitJumpTable(MI);
01666     return;
01667   }
01668   case ARM::SPACE:
01669     OutStreamer.EmitZeros(MI->getOperand(1).getImm());
01670     return;
01671   case ARM::TRAP: {
01672     // Non-Darwin binutils don't yet support the "trap" mnemonic.
01673     // FIXME: Remove this special case when they do.
01674     if (!Subtarget->isTargetMachO()) {
01675       //.long 0xe7ffdefe @ trap
01676       uint32_t Val = 0xe7ffdefeUL;
01677       OutStreamer.AddComment("trap");
01678       OutStreamer.EmitIntValue(Val, 4);
01679       return;
01680     }
01681     break;
01682   }
01683   case ARM::TRAPNaCl: {
01684     //.long 0xe7fedef0 @ trap
01685     uint32_t Val = 0xe7fedef0UL;
01686     OutStreamer.AddComment("trap");
01687     OutStreamer.EmitIntValue(Val, 4);
01688     return;
01689   }
01690   case ARM::tTRAP: {
01691     // Non-Darwin binutils don't yet support the "trap" mnemonic.
01692     // FIXME: Remove this special case when they do.
01693     if (!Subtarget->isTargetMachO()) {
01694       //.short 57086 @ trap
01695       uint16_t Val = 0xdefe;
01696       OutStreamer.AddComment("trap");
01697       OutStreamer.EmitIntValue(Val, 2);
01698       return;
01699     }
01700     break;
01701   }
01702   case ARM::t2Int_eh_sjlj_setjmp:
01703   case ARM::t2Int_eh_sjlj_setjmp_nofp:
01704   case ARM::tInt_eh_sjlj_setjmp: {
01705     // Two incoming args: GPR:$src, GPR:$val
01706     // mov $val, pc
01707     // adds $val, #7
01708     // str $val, [$src, #4]
01709     // movs r0, #0
01710     // b 1f
01711     // movs r0, #1
01712     // 1:
01713     unsigned SrcReg = MI->getOperand(0).getReg();
01714     unsigned ValReg = MI->getOperand(1).getReg();
01715     MCSymbol *Label = GetARMSJLJEHLabel();
01716     OutStreamer.AddComment("eh_setjmp begin");
01717     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
01718       .addReg(ValReg)
01719       .addReg(ARM::PC)
01720       // Predicate.
01721       .addImm(ARMCC::AL)
01722       .addReg(0));
01723 
01724     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tADDi3)
01725       .addReg(ValReg)
01726       // 's' bit operand
01727       .addReg(ARM::CPSR)
01728       .addReg(ValReg)
01729       .addImm(7)
01730       // Predicate.
01731       .addImm(ARMCC::AL)
01732       .addReg(0));
01733 
01734     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tSTRi)
01735       .addReg(ValReg)
01736       .addReg(SrcReg)
01737       // The offset immediate is #4. The operand value is scaled by 4 for the
01738       // tSTR instruction.
01739       .addImm(1)
01740       // Predicate.
01741       .addImm(ARMCC::AL)
01742       .addReg(0));
01743 
01744     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVi8)
01745       .addReg(ARM::R0)
01746       .addReg(ARM::CPSR)
01747       .addImm(0)
01748       // Predicate.
01749       .addImm(ARMCC::AL)
01750       .addReg(0));
01751 
01752     const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
01753     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tB)
01754       .addExpr(SymbolExpr)
01755       .addImm(ARMCC::AL)
01756       .addReg(0));
01757 
01758     OutStreamer.AddComment("eh_setjmp end");
01759     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVi8)
01760       .addReg(ARM::R0)
01761       .addReg(ARM::CPSR)
01762       .addImm(1)
01763       // Predicate.
01764       .addImm(ARMCC::AL)
01765       .addReg(0));
01766 
01767     OutStreamer.EmitLabel(Label);
01768     return;
01769   }
01770 
01771   case ARM::Int_eh_sjlj_setjmp_nofp:
01772   case ARM::Int_eh_sjlj_setjmp: {
01773     // Two incoming args: GPR:$src, GPR:$val
01774     // add $val, pc, #8
01775     // str $val, [$src, #+4]
01776     // mov r0, #0
01777     // add pc, pc, #0
01778     // mov r0, #1
01779     unsigned SrcReg = MI->getOperand(0).getReg();
01780     unsigned ValReg = MI->getOperand(1).getReg();
01781 
01782     OutStreamer.AddComment("eh_setjmp begin");
01783     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDri)
01784       .addReg(ValReg)
01785       .addReg(ARM::PC)
01786       .addImm(8)
01787       // Predicate.
01788       .addImm(ARMCC::AL)
01789       .addReg(0)
01790       // 's' bit operand (always reg0 for this).
01791       .addReg(0));
01792 
01793     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::STRi12)
01794       .addReg(ValReg)
01795       .addReg(SrcReg)
01796       .addImm(4)
01797       // Predicate.
01798       .addImm(ARMCC::AL)
01799       .addReg(0));
01800 
01801     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVi)
01802       .addReg(ARM::R0)
01803       .addImm(0)
01804       // Predicate.
01805       .addImm(ARMCC::AL)
01806       .addReg(0)
01807       // 's' bit operand (always reg0 for this).
01808       .addReg(0));
01809 
01810     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDri)
01811       .addReg(ARM::PC)
01812       .addReg(ARM::PC)
01813       .addImm(0)
01814       // Predicate.
01815       .addImm(ARMCC::AL)
01816       .addReg(0)
01817       // 's' bit operand (always reg0 for this).
01818       .addReg(0));
01819 
01820     OutStreamer.AddComment("eh_setjmp end");
01821     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVi)
01822       .addReg(ARM::R0)
01823       .addImm(1)
01824       // Predicate.
01825       .addImm(ARMCC::AL)
01826       .addReg(0)
01827       // 's' bit operand (always reg0 for this).
01828       .addReg(0));
01829     return;
01830   }
01831   case ARM::Int_eh_sjlj_longjmp: {
01832     // ldr sp, [$src, #8]
01833     // ldr $scratch, [$src, #4]
01834     // ldr r7, [$src]
01835     // bx $scratch
01836     unsigned SrcReg = MI->getOperand(0).getReg();
01837     unsigned ScratchReg = MI->getOperand(1).getReg();
01838     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::LDRi12)
01839       .addReg(ARM::SP)
01840       .addReg(SrcReg)
01841       .addImm(8)
01842       // Predicate.
01843       .addImm(ARMCC::AL)
01844       .addReg(0));
01845 
01846     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::LDRi12)
01847       .addReg(ScratchReg)
01848       .addReg(SrcReg)
01849       .addImm(4)
01850       // Predicate.
01851       .addImm(ARMCC::AL)
01852       .addReg(0));
01853 
01854     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::LDRi12)
01855       .addReg(ARM::R7)
01856       .addReg(SrcReg)
01857       .addImm(0)
01858       // Predicate.
01859       .addImm(ARMCC::AL)
01860       .addReg(0));
01861 
01862     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::BX)
01863       .addReg(ScratchReg)
01864       // Predicate.
01865       .addImm(ARMCC::AL)
01866       .addReg(0));
01867     return;
01868   }
01869   case ARM::tInt_eh_sjlj_longjmp: {
01870     // ldr $scratch, [$src, #8]
01871     // mov sp, $scratch
01872     // ldr $scratch, [$src, #4]
01873     // ldr r7, [$src]
01874     // bx $scratch
01875     unsigned SrcReg = MI->getOperand(0).getReg();
01876     unsigned ScratchReg = MI->getOperand(1).getReg();
01877     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tLDRi)
01878       .addReg(ScratchReg)
01879       .addReg(SrcReg)
01880       // The offset immediate is #8. The operand value is scaled by 4 for the
01881       // tLDR instruction.
01882       .addImm(2)
01883       // Predicate.
01884       .addImm(ARMCC::AL)
01885       .addReg(0));
01886 
01887     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
01888       .addReg(ARM::SP)
01889       .addReg(ScratchReg)
01890       // Predicate.
01891       .addImm(ARMCC::AL)
01892       .addReg(0));
01893 
01894     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tLDRi)
01895       .addReg(ScratchReg)
01896       .addReg(SrcReg)
01897       .addImm(1)
01898       // Predicate.
01899       .addImm(ARMCC::AL)
01900       .addReg(0));
01901 
01902     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tLDRi)
01903       .addReg(ARM::R7)
01904       .addReg(SrcReg)
01905       .addImm(0)
01906       // Predicate.
01907       .addImm(ARMCC::AL)
01908       .addReg(0));
01909 
01910     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tBX)
01911       .addReg(ScratchReg)
01912       // Predicate.
01913       .addImm(ARMCC::AL)
01914       .addReg(0));
01915     return;
01916   }
01917   }
01918 
01919   MCInst TmpInst;
01920   LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
01921 
01922   EmitToStreamer(OutStreamer, TmpInst);
01923 }
01924 
01925 //===----------------------------------------------------------------------===//
01926 // Target Registry Stuff
01927 //===----------------------------------------------------------------------===//
01928 
01929 // Force static initialization.
01930 extern "C" void LLVMInitializeARMAsmPrinter() {
01931   RegisterAsmPrinter<ARMAsmPrinter> X(TheARMLETarget);
01932   RegisterAsmPrinter<ARMAsmPrinter> Y(TheARMBETarget);
01933   RegisterAsmPrinter<ARMAsmPrinter> A(TheThumbLETarget);
01934   RegisterAsmPrinter<ARMAsmPrinter> B(TheThumbBETarget);
01935 }