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ARMAsmPrinter.cpp
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00001 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file contains a printer that converts from our internal representation
00011 // of machine-dependent LLVM code to GAS-format ARM assembly language.
00012 //
00013 //===----------------------------------------------------------------------===//
00014 
00015 #include "ARMAsmPrinter.h"
00016 #include "ARM.h"
00017 #include "ARMConstantPoolValue.h"
00018 #include "ARMFPUName.h"
00019 #include "ARMMachineFunctionInfo.h"
00020 #include "ARMTargetMachine.h"
00021 #include "ARMTargetObjectFile.h"
00022 #include "InstPrinter/ARMInstPrinter.h"
00023 #include "MCTargetDesc/ARMAddressingModes.h"
00024 #include "MCTargetDesc/ARMMCExpr.h"
00025 #include "llvm/ADT/SetVector.h"
00026 #include "llvm/ADT/SmallString.h"
00027 #include "llvm/CodeGen/MachineFunctionPass.h"
00028 #include "llvm/CodeGen/MachineJumpTableInfo.h"
00029 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
00030 #include "llvm/IR/Constants.h"
00031 #include "llvm/IR/DataLayout.h"
00032 #include "llvm/IR/DebugInfo.h"
00033 #include "llvm/IR/Mangler.h"
00034 #include "llvm/IR/Module.h"
00035 #include "llvm/IR/Type.h"
00036 #include "llvm/MC/MCAsmInfo.h"
00037 #include "llvm/MC/MCAssembler.h"
00038 #include "llvm/MC/MCContext.h"
00039 #include "llvm/MC/MCELFStreamer.h"
00040 #include "llvm/MC/MCInst.h"
00041 #include "llvm/MC/MCInstBuilder.h"
00042 #include "llvm/MC/MCObjectStreamer.h"
00043 #include "llvm/MC/MCSectionMachO.h"
00044 #include "llvm/MC/MCStreamer.h"
00045 #include "llvm/MC/MCSymbol.h"
00046 #include "llvm/Support/ARMBuildAttributes.h"
00047 #include "llvm/Support/COFF.h"
00048 #include "llvm/Support/CommandLine.h"
00049 #include "llvm/Support/Debug.h"
00050 #include "llvm/Support/ELF.h"
00051 #include "llvm/Support/ErrorHandling.h"
00052 #include "llvm/Support/TargetRegistry.h"
00053 #include "llvm/Support/raw_ostream.h"
00054 #include "llvm/Target/TargetMachine.h"
00055 #include <cctype>
00056 using namespace llvm;
00057 
00058 #define DEBUG_TYPE "asm-printer"
00059 
00060 void ARMAsmPrinter::EmitFunctionBodyEnd() {
00061   // Make sure to terminate any constant pools that were at the end
00062   // of the function.
00063   if (!InConstantPool)
00064     return;
00065   InConstantPool = false;
00066   OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
00067 }
00068 
00069 void ARMAsmPrinter::EmitFunctionEntryLabel() {
00070   if (AFI->isThumbFunction()) {
00071     OutStreamer.EmitAssemblerFlag(MCAF_Code16);
00072     OutStreamer.EmitThumbFunc(CurrentFnSym);
00073   }
00074 
00075   OutStreamer.EmitLabel(CurrentFnSym);
00076 }
00077 
00078 void ARMAsmPrinter::EmitXXStructor(const Constant *CV) {
00079   uint64_t Size = TM.getDataLayout()->getTypeAllocSize(CV->getType());
00080   assert(Size && "C++ constructor pointer had zero size!");
00081 
00082   const GlobalValue *GV = dyn_cast<GlobalValue>(CV->stripPointerCasts());
00083   assert(GV && "C++ constructor pointer was not a GlobalValue!");
00084 
00085   const MCExpr *E = MCSymbolRefExpr::Create(GetARMGVSymbol(GV,
00086                                                            ARMII::MO_NO_FLAG),
00087                                             (Subtarget->isTargetELF()
00088                                              ? MCSymbolRefExpr::VK_ARM_TARGET1
00089                                              : MCSymbolRefExpr::VK_None),
00090                                             OutContext);
00091 
00092   OutStreamer.EmitValue(E, Size);
00093 }
00094 
00095 /// runOnMachineFunction - This uses the EmitInstruction()
00096 /// method to print assembly for each instruction.
00097 ///
00098 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
00099   AFI = MF.getInfo<ARMFunctionInfo>();
00100   MCP = MF.getConstantPool();
00101 
00102   SetupMachineFunction(MF);
00103 
00104   if (Subtarget->isTargetCOFF()) {
00105     bool Internal = MF.getFunction()->hasInternalLinkage();
00106     COFF::SymbolStorageClass Scl = Internal ? COFF::IMAGE_SYM_CLASS_STATIC
00107                                             : COFF::IMAGE_SYM_CLASS_EXTERNAL;
00108     int Type = COFF::IMAGE_SYM_DTYPE_FUNCTION << COFF::SCT_COMPLEX_TYPE_SHIFT;
00109 
00110     OutStreamer.BeginCOFFSymbolDef(CurrentFnSym);
00111     OutStreamer.EmitCOFFSymbolStorageClass(Scl);
00112     OutStreamer.EmitCOFFSymbolType(Type);
00113     OutStreamer.EndCOFFSymbolDef();
00114   }
00115 
00116   // Have common code print out the function header with linkage info etc.
00117   EmitFunctionHeader();
00118 
00119   // Emit the rest of the function body.
00120   EmitFunctionBody();
00121 
00122   // We didn't modify anything.
00123   return false;
00124 }
00125 
00126 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
00127                                  raw_ostream &O, const char *Modifier) {
00128   const MachineOperand &MO = MI->getOperand(OpNum);
00129   unsigned TF = MO.getTargetFlags();
00130 
00131   switch (MO.getType()) {
00132   default: llvm_unreachable("<unknown operand type>");
00133   case MachineOperand::MO_Register: {
00134     unsigned Reg = MO.getReg();
00135     assert(TargetRegisterInfo::isPhysicalRegister(Reg));
00136     assert(!MO.getSubReg() && "Subregs should be eliminated!");
00137     if(ARM::GPRPairRegClass.contains(Reg)) {
00138       const MachineFunction &MF = *MI->getParent()->getParent();
00139       const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
00140       Reg = TRI->getSubReg(Reg, ARM::gsub_0);
00141     }
00142     O << ARMInstPrinter::getRegisterName(Reg);
00143     break;
00144   }
00145   case MachineOperand::MO_Immediate: {
00146     int64_t Imm = MO.getImm();
00147     O << '#';
00148     if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
00149         (TF == ARMII::MO_LO16))
00150       O << ":lower16:";
00151     else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
00152              (TF == ARMII::MO_HI16))
00153       O << ":upper16:";
00154     O << Imm;
00155     break;
00156   }
00157   case MachineOperand::MO_MachineBasicBlock:
00158     O << *MO.getMBB()->getSymbol();
00159     return;
00160   case MachineOperand::MO_GlobalAddress: {
00161     const GlobalValue *GV = MO.getGlobal();
00162     if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
00163         (TF & ARMII::MO_LO16))
00164       O << ":lower16:";
00165     else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
00166              (TF & ARMII::MO_HI16))
00167       O << ":upper16:";
00168     O << *GetARMGVSymbol(GV, TF);
00169 
00170     printOffset(MO.getOffset(), O);
00171     if (TF == ARMII::MO_PLT)
00172       O << "(PLT)";
00173     break;
00174   }
00175   case MachineOperand::MO_ConstantPoolIndex:
00176     O << *GetCPISymbol(MO.getIndex());
00177     break;
00178   }
00179 }
00180 
00181 //===--------------------------------------------------------------------===//
00182 
00183 MCSymbol *ARMAsmPrinter::
00184 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
00185   const DataLayout *DL = TM.getDataLayout();
00186   SmallString<60> Name;
00187   raw_svector_ostream(Name) << DL->getPrivateGlobalPrefix() << "JTI"
00188     << getFunctionNumber() << '_' << uid << '_' << uid2;
00189   return OutContext.GetOrCreateSymbol(Name.str());
00190 }
00191 
00192 
00193 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel() const {
00194   const DataLayout *DL = TM.getDataLayout();
00195   SmallString<60> Name;
00196   raw_svector_ostream(Name) << DL->getPrivateGlobalPrefix() << "SJLJEH"
00197     << getFunctionNumber();
00198   return OutContext.GetOrCreateSymbol(Name.str());
00199 }
00200 
00201 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
00202                                     unsigned AsmVariant, const char *ExtraCode,
00203                                     raw_ostream &O) {
00204   // Does this asm operand have a single letter operand modifier?
00205   if (ExtraCode && ExtraCode[0]) {
00206     if (ExtraCode[1] != 0) return true; // Unknown modifier.
00207 
00208     switch (ExtraCode[0]) {
00209     default:
00210       // See if this is a generic print operand
00211       return AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O);
00212     case 'a': // Print as a memory address.
00213       if (MI->getOperand(OpNum).isReg()) {
00214         O << "["
00215           << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
00216           << "]";
00217         return false;
00218       }
00219       // Fallthrough
00220     case 'c': // Don't print "#" before an immediate operand.
00221       if (!MI->getOperand(OpNum).isImm())
00222         return true;
00223       O << MI->getOperand(OpNum).getImm();
00224       return false;
00225     case 'P': // Print a VFP double precision register.
00226     case 'q': // Print a NEON quad precision register.
00227       printOperand(MI, OpNum, O);
00228       return false;
00229     case 'y': // Print a VFP single precision register as indexed double.
00230       if (MI->getOperand(OpNum).isReg()) {
00231         unsigned Reg = MI->getOperand(OpNum).getReg();
00232         const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
00233         // Find the 'd' register that has this 's' register as a sub-register,
00234         // and determine the lane number.
00235         for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
00236           if (!ARM::DPRRegClass.contains(*SR))
00237             continue;
00238           bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
00239           O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");
00240           return false;
00241         }
00242       }
00243       return true;
00244     case 'B': // Bitwise inverse of integer or symbol without a preceding #.
00245       if (!MI->getOperand(OpNum).isImm())
00246         return true;
00247       O << ~(MI->getOperand(OpNum).getImm());
00248       return false;
00249     case 'L': // The low 16 bits of an immediate constant.
00250       if (!MI->getOperand(OpNum).isImm())
00251         return true;
00252       O << (MI->getOperand(OpNum).getImm() & 0xffff);
00253       return false;
00254     case 'M': { // A register range suitable for LDM/STM.
00255       if (!MI->getOperand(OpNum).isReg())
00256         return true;
00257       const MachineOperand &MO = MI->getOperand(OpNum);
00258       unsigned RegBegin = MO.getReg();
00259       // This takes advantage of the 2 operand-ness of ldm/stm and that we've
00260       // already got the operands in registers that are operands to the
00261       // inline asm statement.
00262       O << "{";
00263       if (ARM::GPRPairRegClass.contains(RegBegin)) {
00264         const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
00265         unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
00266         O << ARMInstPrinter::getRegisterName(Reg0) << ", ";
00267         RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1);
00268       }
00269       O << ARMInstPrinter::getRegisterName(RegBegin);
00270 
00271       // FIXME: The register allocator not only may not have given us the
00272       // registers in sequence, but may not be in ascending registers. This
00273       // will require changes in the register allocator that'll need to be
00274       // propagated down here if the operands change.
00275       unsigned RegOps = OpNum + 1;
00276       while (MI->getOperand(RegOps).isReg()) {
00277         O << ", "
00278           << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
00279         RegOps++;
00280       }
00281 
00282       O << "}";
00283 
00284       return false;
00285     }
00286     case 'R': // The most significant register of a pair.
00287     case 'Q': { // The least significant register of a pair.
00288       if (OpNum == 0)
00289         return true;
00290       const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
00291       if (!FlagsOP.isImm())
00292         return true;
00293       unsigned Flags = FlagsOP.getImm();
00294 
00295       // This operand may not be the one that actually provides the register. If
00296       // it's tied to a previous one then we should refer instead to that one
00297       // for registers and their classes.
00298       unsigned TiedIdx;
00299       if (InlineAsm::isUseOperandTiedToDef(Flags, TiedIdx)) {
00300         for (OpNum = InlineAsm::MIOp_FirstOperand; TiedIdx; --TiedIdx) {
00301           unsigned OpFlags = MI->getOperand(OpNum).getImm();
00302           OpNum += InlineAsm::getNumOperandRegisters(OpFlags) + 1;
00303         }
00304         Flags = MI->getOperand(OpNum).getImm();
00305 
00306         // Later code expects OpNum to be pointing at the register rather than
00307         // the flags.
00308         OpNum += 1;
00309       }
00310 
00311       unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
00312       unsigned RC;
00313       InlineAsm::hasRegClassConstraint(Flags, RC);
00314       if (RC == ARM::GPRPairRegClassID) {
00315         if (NumVals != 1)
00316           return true;
00317         const MachineOperand &MO = MI->getOperand(OpNum);
00318         if (!MO.isReg())
00319           return true;
00320         const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
00321         unsigned Reg = TRI->getSubReg(MO.getReg(), ExtraCode[0] == 'Q' ?
00322             ARM::gsub_0 : ARM::gsub_1);
00323         O << ARMInstPrinter::getRegisterName(Reg);
00324         return false;
00325       }
00326       if (NumVals != 2)
00327         return true;
00328       unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
00329       if (RegOp >= MI->getNumOperands())
00330         return true;
00331       const MachineOperand &MO = MI->getOperand(RegOp);
00332       if (!MO.isReg())
00333         return true;
00334       unsigned Reg = MO.getReg();
00335       O << ARMInstPrinter::getRegisterName(Reg);
00336       return false;
00337     }
00338 
00339     case 'e': // The low doubleword register of a NEON quad register.
00340     case 'f': { // The high doubleword register of a NEON quad register.
00341       if (!MI->getOperand(OpNum).isReg())
00342         return true;
00343       unsigned Reg = MI->getOperand(OpNum).getReg();
00344       if (!ARM::QPRRegClass.contains(Reg))
00345         return true;
00346       const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
00347       unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
00348                                        ARM::dsub_0 : ARM::dsub_1);
00349       O << ARMInstPrinter::getRegisterName(SubReg);
00350       return false;
00351     }
00352 
00353     // This modifier is not yet supported.
00354     case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
00355       return true;
00356     case 'H': { // The highest-numbered register of a pair.
00357       const MachineOperand &MO = MI->getOperand(OpNum);
00358       if (!MO.isReg())
00359         return true;
00360       const MachineFunction &MF = *MI->getParent()->getParent();
00361       const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
00362       unsigned Reg = MO.getReg();
00363       if(!ARM::GPRPairRegClass.contains(Reg))
00364         return false;
00365       Reg = TRI->getSubReg(Reg, ARM::gsub_1);
00366       O << ARMInstPrinter::getRegisterName(Reg);
00367       return false;
00368     }
00369     }
00370   }
00371 
00372   printOperand(MI, OpNum, O);
00373   return false;
00374 }
00375 
00376 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
00377                                           unsigned OpNum, unsigned AsmVariant,
00378                                           const char *ExtraCode,
00379                                           raw_ostream &O) {
00380   // Does this asm operand have a single letter operand modifier?
00381   if (ExtraCode && ExtraCode[0]) {
00382     if (ExtraCode[1] != 0) return true; // Unknown modifier.
00383 
00384     switch (ExtraCode[0]) {
00385       case 'A': // A memory operand for a VLD1/VST1 instruction.
00386       default: return true;  // Unknown modifier.
00387       case 'm': // The base register of a memory operand.
00388         if (!MI->getOperand(OpNum).isReg())
00389           return true;
00390         O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
00391         return false;
00392     }
00393   }
00394 
00395   const MachineOperand &MO = MI->getOperand(OpNum);
00396   assert(MO.isReg() && "unexpected inline asm memory operand");
00397   O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
00398   return false;
00399 }
00400 
00401 static bool isThumb(const MCSubtargetInfo& STI) {
00402   return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
00403 }
00404 
00405 void ARMAsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo &StartInfo,
00406                                      const MCSubtargetInfo *EndInfo) const {
00407   // If either end mode is unknown (EndInfo == NULL) or different than
00408   // the start mode, then restore the start mode.
00409   const bool WasThumb = isThumb(StartInfo);
00410   if (!EndInfo || WasThumb != isThumb(*EndInfo)) {
00411     OutStreamer.EmitAssemblerFlag(WasThumb ? MCAF_Code16 : MCAF_Code32);
00412   }
00413 }
00414 
00415 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
00416   if (Subtarget->isTargetMachO()) {
00417     Reloc::Model RelocM = TM.getRelocationModel();
00418     if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
00419       // Declare all the text sections up front (before the DWARF sections
00420       // emitted by AsmPrinter::doInitialization) so the assembler will keep
00421       // them together at the beginning of the object file.  This helps
00422       // avoid out-of-range branches that are due a fundamental limitation of
00423       // the way symbol offsets are encoded with the current Darwin ARM
00424       // relocations.
00425       const TargetLoweringObjectFileMachO &TLOFMacho =
00426         static_cast<const TargetLoweringObjectFileMachO &>(
00427           getObjFileLowering());
00428 
00429       // Collect the set of sections our functions will go into.
00430       SetVector<const MCSection *, SmallVector<const MCSection *, 8>,
00431         SmallPtrSet<const MCSection *, 8> > TextSections;
00432       // Default text section comes first.
00433       TextSections.insert(TLOFMacho.getTextSection());
00434       // Now any user defined text sections from function attributes.
00435       for (Module::iterator F = M.begin(), e = M.end(); F != e; ++F)
00436         if (!F->isDeclaration() && !F->hasAvailableExternallyLinkage())
00437           TextSections.insert(TLOFMacho.SectionForGlobal(F, *Mang, TM));
00438       // Now the coalescable sections.
00439       TextSections.insert(TLOFMacho.getTextCoalSection());
00440       TextSections.insert(TLOFMacho.getConstTextCoalSection());
00441 
00442       // Emit the sections in the .s file header to fix the order.
00443       for (unsigned i = 0, e = TextSections.size(); i != e; ++i)
00444         OutStreamer.SwitchSection(TextSections[i]);
00445 
00446       if (RelocM == Reloc::DynamicNoPIC) {
00447         const MCSection *sect =
00448           OutContext.getMachOSection("__TEXT", "__symbol_stub4",
00449                                      MachO::S_SYMBOL_STUBS,
00450                                      12, SectionKind::getText());
00451         OutStreamer.SwitchSection(sect);
00452       } else {
00453         const MCSection *sect =
00454           OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
00455                                      MachO::S_SYMBOL_STUBS,
00456                                      16, SectionKind::getText());
00457         OutStreamer.SwitchSection(sect);
00458       }
00459       const MCSection *StaticInitSect =
00460         OutContext.getMachOSection("__TEXT", "__StaticInit",
00461                                    MachO::S_REGULAR |
00462                                    MachO::S_ATTR_PURE_INSTRUCTIONS,
00463                                    SectionKind::getText());
00464       OutStreamer.SwitchSection(StaticInitSect);
00465     }
00466 
00467     // Compiling with debug info should not affect the code
00468     // generation.  Ensure the cstring section comes before the
00469     // optional __DWARF secion. Otherwise, PC-relative loads would
00470     // have to use different instruction sequences at "-g" in order to
00471     // reach global data in the same object file.
00472     OutStreamer.SwitchSection(getObjFileLowering().getCStringSection());
00473   }
00474 
00475   // Use unified assembler syntax.
00476   OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
00477 
00478   // Emit ARM Build Attributes
00479   if (Subtarget->isTargetELF())
00480     emitAttributes();
00481 }
00482 
00483 static void
00484 emitNonLazySymbolPointer(MCStreamer &OutStreamer, MCSymbol *StubLabel,
00485                          MachineModuleInfoImpl::StubValueTy &MCSym) {
00486   // L_foo$stub:
00487   OutStreamer.EmitLabel(StubLabel);
00488   //   .indirect_symbol _foo
00489   OutStreamer.EmitSymbolAttribute(MCSym.getPointer(), MCSA_IndirectSymbol);
00490 
00491   if (MCSym.getInt())
00492     // External to current translation unit.
00493     OutStreamer.EmitIntValue(0, 4/*size*/);
00494   else
00495     // Internal to current translation unit.
00496     //
00497     // When we place the LSDA into the TEXT section, the type info
00498     // pointers need to be indirect and pc-rel. We accomplish this by
00499     // using NLPs; however, sometimes the types are local to the file.
00500     // We need to fill in the value for the NLP in those cases.
00501     OutStreamer.EmitValue(
00502         MCSymbolRefExpr::Create(MCSym.getPointer(), OutStreamer.getContext()),
00503         4 /*size*/);
00504 }
00505 
00506 
00507 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
00508   if (Subtarget->isTargetMachO()) {
00509     // All darwin targets use mach-o.
00510     const TargetLoweringObjectFileMachO &TLOFMacho =
00511       static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
00512     MachineModuleInfoMachO &MMIMacho =
00513       MMI->getObjFileInfo<MachineModuleInfoMachO>();
00514 
00515     // Output non-lazy-pointers for external and common global variables.
00516     MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
00517 
00518     if (!Stubs.empty()) {
00519       // Switch with ".non_lazy_symbol_pointer" directive.
00520       OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
00521       EmitAlignment(2);
00522 
00523       for (auto &Stub : Stubs)
00524         emitNonLazySymbolPointer(OutStreamer, Stub.first, Stub.second);
00525 
00526       Stubs.clear();
00527       OutStreamer.AddBlankLine();
00528     }
00529 
00530     Stubs = MMIMacho.GetHiddenGVStubList();
00531     if (!Stubs.empty()) {
00532       OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
00533       EmitAlignment(2);
00534 
00535       for (auto &Stub : Stubs)
00536         emitNonLazySymbolPointer(OutStreamer, Stub.first, Stub.second);
00537 
00538       Stubs.clear();
00539       OutStreamer.AddBlankLine();
00540     }
00541 
00542     // Funny Darwin hack: This flag tells the linker that no global symbols
00543     // contain code that falls through to other global symbols (e.g. the obvious
00544     // implementation of multiple entry points).  If this doesn't occur, the
00545     // linker can safely perform dead code stripping.  Since LLVM never
00546     // generates code that does this, it is always safe to set.
00547     OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
00548   }
00549 
00550   // Emit a .data.rel section containing any stubs that were created.
00551   if (Subtarget->isTargetELF()) {
00552     const TargetLoweringObjectFileELF &TLOFELF =
00553       static_cast<const TargetLoweringObjectFileELF &>(getObjFileLowering());
00554 
00555     MachineModuleInfoELF &MMIELF = MMI->getObjFileInfo<MachineModuleInfoELF>();
00556 
00557     // Output stubs for external and common global variables.
00558     MachineModuleInfoELF::SymbolListTy Stubs = MMIELF.GetGVStubList();
00559     if (!Stubs.empty()) {
00560       OutStreamer.SwitchSection(TLOFELF.getDataRelSection());
00561       const DataLayout *TD = TM.getDataLayout();
00562 
00563       for (auto &stub: Stubs) {
00564         OutStreamer.EmitLabel(stub.first);
00565         OutStreamer.EmitSymbolValue(stub.second.getPointer(),
00566                                     TD->getPointerSize(0));
00567       }
00568       Stubs.clear();
00569     }
00570   }
00571 }
00572 
00573 //===----------------------------------------------------------------------===//
00574 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
00575 // FIXME:
00576 // The following seem like one-off assembler flags, but they actually need
00577 // to appear in the .ARM.attributes section in ELF.
00578 // Instead of subclassing the MCELFStreamer, we do the work here.
00579 
00580 static ARMBuildAttrs::CPUArch getArchForCPU(StringRef CPU,
00581                                             const ARMSubtarget *Subtarget) {
00582   if (CPU == "xscale")
00583     return ARMBuildAttrs::v5TEJ;
00584 
00585   if (Subtarget->hasV8Ops())
00586     return ARMBuildAttrs::v8;
00587   else if (Subtarget->hasV7Ops()) {
00588     if (Subtarget->isMClass() && Subtarget->hasThumb2DSP())
00589       return ARMBuildAttrs::v7E_M;
00590     return ARMBuildAttrs::v7;
00591   } else if (Subtarget->hasV6T2Ops())
00592     return ARMBuildAttrs::v6T2;
00593   else if (Subtarget->hasV6MOps())
00594     return ARMBuildAttrs::v6S_M;
00595   else if (Subtarget->hasV6Ops())
00596     return ARMBuildAttrs::v6;
00597   else if (Subtarget->hasV5TEOps())
00598     return ARMBuildAttrs::v5TE;
00599   else if (Subtarget->hasV5TOps())
00600     return ARMBuildAttrs::v5T;
00601   else if (Subtarget->hasV4TOps())
00602     return ARMBuildAttrs::v4T;
00603   else
00604     return ARMBuildAttrs::v4;
00605 }
00606 
00607 void ARMAsmPrinter::emitAttributes() {
00608   MCTargetStreamer &TS = *OutStreamer.getTargetStreamer();
00609   ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
00610 
00611   ATS.switchVendor("aeabi");
00612 
00613   std::string CPUString = Subtarget->getCPUString();
00614 
00615   // FIXME: remove krait check when GNU tools support krait cpu
00616   if (CPUString != "generic" && CPUString != "krait")
00617     ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, CPUString);
00618 
00619   ATS.emitAttribute(ARMBuildAttrs::CPU_arch,
00620                     getArchForCPU(CPUString, Subtarget));
00621 
00622   // Tag_CPU_arch_profile must have the default value of 0 when "Architecture
00623   // profile is not applicable (e.g. pre v7, or cross-profile code)".
00624   if (Subtarget->hasV7Ops()) {
00625     if (Subtarget->isAClass()) {
00626       ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
00627                         ARMBuildAttrs::ApplicationProfile);
00628     } else if (Subtarget->isRClass()) {
00629       ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
00630                         ARMBuildAttrs::RealTimeProfile);
00631     } else if (Subtarget->isMClass()) {
00632       ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
00633                         ARMBuildAttrs::MicroControllerProfile);
00634     }
00635   }
00636 
00637   ATS.emitAttribute(ARMBuildAttrs::ARM_ISA_use, Subtarget->hasARMOps() ?
00638                       ARMBuildAttrs::Allowed : ARMBuildAttrs::Not_Allowed);
00639   if (Subtarget->isThumb1Only()) {
00640     ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
00641                       ARMBuildAttrs::Allowed);
00642   } else if (Subtarget->hasThumb2()) {
00643     ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
00644                       ARMBuildAttrs::AllowThumb32);
00645   }
00646 
00647   if (Subtarget->hasNEON()) {
00648     /* NEON is not exactly a VFP architecture, but GAS emit one of
00649      * neon/neon-fp-armv8/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
00650     if (Subtarget->hasFPARMv8()) {
00651       if (Subtarget->hasCrypto())
00652         ATS.emitFPU(ARM::CRYPTO_NEON_FP_ARMV8);
00653       else
00654         ATS.emitFPU(ARM::NEON_FP_ARMV8);
00655     }
00656     else if (Subtarget->hasVFP4())
00657       ATS.emitFPU(ARM::NEON_VFPV4);
00658     else
00659       ATS.emitFPU(ARM::NEON);
00660     // Emit Tag_Advanced_SIMD_arch for ARMv8 architecture
00661     if (Subtarget->hasV8Ops())
00662       ATS.emitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
00663                         ARMBuildAttrs::AllowNeonARMv8);
00664   } else {
00665     if (Subtarget->hasFPARMv8())
00666       ATS.emitFPU(ARM::FP_ARMV8);
00667     else if (Subtarget->hasVFP4())
00668       ATS.emitFPU(Subtarget->hasD16() ? ARM::VFPV4_D16 : ARM::VFPV4);
00669     else if (Subtarget->hasVFP3())
00670       ATS.emitFPU(Subtarget->hasD16() ? ARM::VFPV3_D16 : ARM::VFPV3);
00671     else if (Subtarget->hasVFP2())
00672       ATS.emitFPU(ARM::VFPV2);
00673   }
00674 
00675   if (TM.getRelocationModel() == Reloc::PIC_) {
00676     // PIC specific attributes.
00677     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RW_data,
00678                       ARMBuildAttrs::AddressRWPCRel);
00679     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RO_data,
00680                       ARMBuildAttrs::AddressROPCRel);
00681     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_GOT_use,
00682                       ARMBuildAttrs::AddressGOT);
00683   } else {
00684     // Allow direct addressing of imported data for all other relocation models.
00685     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_GOT_use,
00686                       ARMBuildAttrs::AddressDirect);
00687   }
00688 
00689   // Signal various FP modes.
00690   if (!TM.Options.UnsafeFPMath) {
00691     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal, ARMBuildAttrs::Allowed);
00692     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
00693                       ARMBuildAttrs::Allowed);
00694   }
00695 
00696   if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
00697     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
00698                       ARMBuildAttrs::Allowed);
00699   else
00700     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
00701                       ARMBuildAttrs::AllowIEE754);
00702 
00703   // FIXME: add more flags to ARMBuildAttributes.h
00704   // 8-bytes alignment stuff.
00705   ATS.emitAttribute(ARMBuildAttrs::ABI_align_needed, 1);
00706   ATS.emitAttribute(ARMBuildAttrs::ABI_align_preserved, 1);
00707 
00708   // ABI_HardFP_use attribute to indicate single precision FP.
00709   if (Subtarget->isFPOnlySP())
00710     ATS.emitAttribute(ARMBuildAttrs::ABI_HardFP_use,
00711                       ARMBuildAttrs::HardFPSinglePrecision);
00712 
00713   // Hard float.  Use both S and D registers and conform to AAPCS-VFP.
00714   if (Subtarget->isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard)
00715     ATS.emitAttribute(ARMBuildAttrs::ABI_VFP_args, ARMBuildAttrs::HardFPAAPCS);
00716 
00717   // FIXME: Should we signal R9 usage?
00718 
00719   if (Subtarget->hasFP16())
00720       ATS.emitAttribute(ARMBuildAttrs::FP_HP_extension, ARMBuildAttrs::AllowHPFP);
00721 
00722   if (Subtarget->hasMPExtension())
00723       ATS.emitAttribute(ARMBuildAttrs::MPextension_use, ARMBuildAttrs::AllowMP);
00724 
00725   // Hardware divide in ARM mode is part of base arch, starting from ARMv8.
00726   // If only Thumb hwdiv is present, it must also be in base arch (ARMv7-R/M).
00727   // It is not possible to produce DisallowDIV: if hwdiv is present in the base
00728   // arch, supplying -hwdiv downgrades the effective arch, via ClearImpliedBits.
00729   // AllowDIVExt is only emitted if hwdiv isn't available in the base arch;
00730   // otherwise, the default value (AllowDIVIfExists) applies.
00731   if (Subtarget->hasDivideInARMMode() && !Subtarget->hasV8Ops())
00732       ATS.emitAttribute(ARMBuildAttrs::DIV_use, ARMBuildAttrs::AllowDIVExt);
00733 
00734   if (MMI) {
00735     if (const Module *SourceModule = MMI->getModule()) {
00736       // ABI_PCS_wchar_t to indicate wchar_t width
00737       // FIXME: There is no way to emit value 0 (wchar_t prohibited).
00738       if (auto WCharWidthValue = cast_or_null<ConstantInt>(
00739               SourceModule->getModuleFlag("wchar_size"))) {
00740         int WCharWidth = WCharWidthValue->getZExtValue();
00741         assert((WCharWidth == 2 || WCharWidth == 4) &&
00742                "wchar_t width must be 2 or 4 bytes");
00743         ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_wchar_t, WCharWidth);
00744       }
00745 
00746       // ABI_enum_size to indicate enum width
00747       // FIXME: There is no way to emit value 0 (enums prohibited) or value 3
00748       //        (all enums contain a value needing 32 bits to encode).
00749       if (auto EnumWidthValue = cast_or_null<ConstantInt>(
00750               SourceModule->getModuleFlag("min_enum_size"))) {
00751         int EnumWidth = EnumWidthValue->getZExtValue();
00752         assert((EnumWidth == 1 || EnumWidth == 4) &&
00753                "Minimum enum width must be 1 or 4 bytes");
00754         int EnumBuildAttr = EnumWidth == 1 ? 1 : 2;
00755         ATS.emitAttribute(ARMBuildAttrs::ABI_enum_size, EnumBuildAttr);
00756       }
00757     }
00758   }
00759 
00760   if (Subtarget->hasTrustZone() && Subtarget->hasVirtualization())
00761       ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
00762                         ARMBuildAttrs::AllowTZVirtualization);
00763   else if (Subtarget->hasTrustZone())
00764       ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
00765                         ARMBuildAttrs::AllowTZ);
00766   else if (Subtarget->hasVirtualization())
00767       ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
00768                         ARMBuildAttrs::AllowVirtualization);
00769 
00770   ATS.finishAttributeSection();
00771 }
00772 
00773 //===----------------------------------------------------------------------===//
00774 
00775 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
00776                              unsigned LabelId, MCContext &Ctx) {
00777 
00778   MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
00779                        + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
00780   return Label;
00781 }
00782 
00783 static MCSymbolRefExpr::VariantKind
00784 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
00785   switch (Modifier) {
00786   case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
00787   case ARMCP::TLSGD:       return MCSymbolRefExpr::VK_TLSGD;
00788   case ARMCP::TPOFF:       return MCSymbolRefExpr::VK_TPOFF;
00789   case ARMCP::GOTTPOFF:    return MCSymbolRefExpr::VK_GOTTPOFF;
00790   case ARMCP::GOT:         return MCSymbolRefExpr::VK_GOT;
00791   case ARMCP::GOTOFF:      return MCSymbolRefExpr::VK_GOTOFF;
00792   }
00793   llvm_unreachable("Invalid ARMCPModifier!");
00794 }
00795 
00796 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV,
00797                                         unsigned char TargetFlags) {
00798   if (Subtarget->isTargetMachO()) {
00799     bool IsIndirect = (TargetFlags & ARMII::MO_NONLAZY) &&
00800       Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
00801 
00802     if (!IsIndirect)
00803       return getSymbol(GV);
00804 
00805     // FIXME: Remove this when Darwin transition to @GOT like syntax.
00806     MCSymbol *MCSym = getSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
00807     MachineModuleInfoMachO &MMIMachO =
00808       MMI->getObjFileInfo<MachineModuleInfoMachO>();
00809     MachineModuleInfoImpl::StubValueTy &StubSym =
00810       GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym)
00811                                 : MMIMachO.getGVStubEntry(MCSym);
00812     if (!StubSym.getPointer())
00813       StubSym = MachineModuleInfoImpl::StubValueTy(getSymbol(GV),
00814                                                    !GV->hasInternalLinkage());
00815     return MCSym;
00816   } else if (Subtarget->isTargetCOFF()) {
00817     assert(Subtarget->isTargetWindows() &&
00818            "Windows is the only supported COFF target");
00819 
00820     bool IsIndirect = (TargetFlags & ARMII::MO_DLLIMPORT);
00821     if (!IsIndirect)
00822       return getSymbol(GV);
00823 
00824     SmallString<128> Name;
00825     Name = "__imp_";
00826     getNameWithPrefix(Name, GV);
00827 
00828     return OutContext.GetOrCreateSymbol(Name);
00829   } else if (Subtarget->isTargetELF()) {
00830     return getSymbol(GV);
00831   }
00832   llvm_unreachable("unexpected target");
00833 }
00834 
00835 void ARMAsmPrinter::
00836 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
00837   const DataLayout *DL = TM.getDataLayout();
00838   int Size = TM.getDataLayout()->getTypeAllocSize(MCPV->getType());
00839 
00840   ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
00841 
00842   MCSymbol *MCSym;
00843   if (ACPV->isLSDA()) {
00844     SmallString<128> Str;
00845     raw_svector_ostream OS(Str);
00846     OS << DL->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
00847     MCSym = OutContext.GetOrCreateSymbol(OS.str());
00848   } else if (ACPV->isBlockAddress()) {
00849     const BlockAddress *BA =
00850       cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
00851     MCSym = GetBlockAddressSymbol(BA);
00852   } else if (ACPV->isGlobalValue()) {
00853     const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
00854 
00855     // On Darwin, const-pool entries may get the "FOO$non_lazy_ptr" mangling, so
00856     // flag the global as MO_NONLAZY.
00857     unsigned char TF = Subtarget->isTargetMachO() ? ARMII::MO_NONLAZY : 0;
00858     MCSym = GetARMGVSymbol(GV, TF);
00859   } else if (ACPV->isMachineBasicBlock()) {
00860     const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
00861     MCSym = MBB->getSymbol();
00862   } else {
00863     assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
00864     const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
00865     MCSym = GetExternalSymbolSymbol(Sym);
00866   }
00867 
00868   // Create an MCSymbol for the reference.
00869   const MCExpr *Expr =
00870     MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
00871                             OutContext);
00872 
00873   if (ACPV->getPCAdjustment()) {
00874     MCSymbol *PCLabel = getPICLabel(DL->getPrivateGlobalPrefix(),
00875                                     getFunctionNumber(),
00876                                     ACPV->getLabelId(),
00877                                     OutContext);
00878     const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
00879     PCRelExpr =
00880       MCBinaryExpr::CreateAdd(PCRelExpr,
00881                               MCConstantExpr::Create(ACPV->getPCAdjustment(),
00882                                                      OutContext),
00883                               OutContext);
00884     if (ACPV->mustAddCurrentAddress()) {
00885       // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
00886       // label, so just emit a local label end reference that instead.
00887       MCSymbol *DotSym = OutContext.CreateTempSymbol();
00888       OutStreamer.EmitLabel(DotSym);
00889       const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
00890       PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
00891     }
00892     Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
00893   }
00894   OutStreamer.EmitValue(Expr, Size);
00895 }
00896 
00897 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
00898   unsigned Opcode = MI->getOpcode();
00899   int OpNum = 1;
00900   if (Opcode == ARM::BR_JTadd)
00901     OpNum = 2;
00902   else if (Opcode == ARM::BR_JTm)
00903     OpNum = 3;
00904 
00905   const MachineOperand &MO1 = MI->getOperand(OpNum);
00906   const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
00907   unsigned JTI = MO1.getIndex();
00908 
00909   // Emit a label for the jump table.
00910   MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
00911   OutStreamer.EmitLabel(JTISymbol);
00912 
00913   // Mark the jump table as data-in-code.
00914   OutStreamer.EmitDataRegion(MCDR_DataRegionJT32);
00915 
00916   // Emit each entry of the table.
00917   const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
00918   const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
00919   const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
00920 
00921   for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
00922     MachineBasicBlock *MBB = JTBBs[i];
00923     // Construct an MCExpr for the entry. We want a value of the form:
00924     // (BasicBlockAddr - TableBeginAddr)
00925     //
00926     // For example, a table with entries jumping to basic blocks BB0 and BB1
00927     // would look like:
00928     // LJTI_0_0:
00929     //    .word (LBB0 - LJTI_0_0)
00930     //    .word (LBB1 - LJTI_0_0)
00931     const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
00932 
00933     if (TM.getRelocationModel() == Reloc::PIC_)
00934       Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
00935                                                                    OutContext),
00936                                      OutContext);
00937     // If we're generating a table of Thumb addresses in static relocation
00938     // model, we need to add one to keep interworking correctly.
00939     else if (AFI->isThumbFunction())
00940       Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(1,OutContext),
00941                                      OutContext);
00942     OutStreamer.EmitValue(Expr, 4);
00943   }
00944   // Mark the end of jump table data-in-code region.
00945   OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
00946 }
00947 
00948 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
00949   unsigned Opcode = MI->getOpcode();
00950   int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
00951   const MachineOperand &MO1 = MI->getOperand(OpNum);
00952   const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
00953   unsigned JTI = MO1.getIndex();
00954 
00955   MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
00956   OutStreamer.EmitLabel(JTISymbol);
00957 
00958   // Emit each entry of the table.
00959   const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
00960   const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
00961   const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
00962   unsigned OffsetWidth = 4;
00963   if (MI->getOpcode() == ARM::t2TBB_JT) {
00964     OffsetWidth = 1;
00965     // Mark the jump table as data-in-code.
00966     OutStreamer.EmitDataRegion(MCDR_DataRegionJT8);
00967   } else if (MI->getOpcode() == ARM::t2TBH_JT) {
00968     OffsetWidth = 2;
00969     // Mark the jump table as data-in-code.
00970     OutStreamer.EmitDataRegion(MCDR_DataRegionJT16);
00971   }
00972 
00973   for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
00974     MachineBasicBlock *MBB = JTBBs[i];
00975     const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
00976                                                           OutContext);
00977     // If this isn't a TBB or TBH, the entries are direct branch instructions.
00978     if (OffsetWidth == 4) {
00979       EmitToStreamer(OutStreamer, MCInstBuilder(ARM::t2B)
00980         .addExpr(MBBSymbolExpr)
00981         .addImm(ARMCC::AL)
00982         .addReg(0));
00983       continue;
00984     }
00985     // Otherwise it's an offset from the dispatch instruction. Construct an
00986     // MCExpr for the entry. We want a value of the form:
00987     // (BasicBlockAddr - TableBeginAddr) / 2
00988     //
00989     // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
00990     // would look like:
00991     // LJTI_0_0:
00992     //    .byte (LBB0 - LJTI_0_0) / 2
00993     //    .byte (LBB1 - LJTI_0_0) / 2
00994     const MCExpr *Expr =
00995       MCBinaryExpr::CreateSub(MBBSymbolExpr,
00996                               MCSymbolRefExpr::Create(JTISymbol, OutContext),
00997                               OutContext);
00998     Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
00999                                    OutContext);
01000     OutStreamer.EmitValue(Expr, OffsetWidth);
01001   }
01002   // Mark the end of jump table data-in-code region. 32-bit offsets use
01003   // actual branch instructions here, so we don't mark those as a data-region
01004   // at all.
01005   if (OffsetWidth != 4)
01006     OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
01007 }
01008 
01009 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
01010   assert(MI->getFlag(MachineInstr::FrameSetup) &&
01011       "Only instruction which are involved into frame setup code are allowed");
01012 
01013   MCTargetStreamer &TS = *OutStreamer.getTargetStreamer();
01014   ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
01015   const MachineFunction &MF = *MI->getParent()->getParent();
01016   const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
01017   const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
01018 
01019   unsigned FramePtr = RegInfo->getFrameRegister(MF);
01020   unsigned Opc = MI->getOpcode();
01021   unsigned SrcReg, DstReg;
01022 
01023   if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
01024     // Two special cases:
01025     // 1) tPUSH does not have src/dst regs.
01026     // 2) for Thumb1 code we sometimes materialize the constant via constpool
01027     // load. Yes, this is pretty fragile, but for now I don't see better
01028     // way... :(
01029     SrcReg = DstReg = ARM::SP;
01030   } else {
01031     SrcReg = MI->getOperand(1).getReg();
01032     DstReg = MI->getOperand(0).getReg();
01033   }
01034 
01035   // Try to figure out the unwinding opcode out of src / dst regs.
01036   if (MI->mayStore()) {
01037     // Register saves.
01038     assert(DstReg == ARM::SP &&
01039            "Only stack pointer as a destination reg is supported");
01040 
01041     SmallVector<unsigned, 4> RegList;
01042     // Skip src & dst reg, and pred ops.
01043     unsigned StartOp = 2 + 2;
01044     // Use all the operands.
01045     unsigned NumOffset = 0;
01046 
01047     switch (Opc) {
01048     default:
01049       MI->dump();
01050       llvm_unreachable("Unsupported opcode for unwinding information");
01051     case ARM::tPUSH:
01052       // Special case here: no src & dst reg, but two extra imp ops.
01053       StartOp = 2; NumOffset = 2;
01054     case ARM::STMDB_UPD:
01055     case ARM::t2STMDB_UPD:
01056     case ARM::VSTMDDB_UPD:
01057       assert(SrcReg == ARM::SP &&
01058              "Only stack pointer as a source reg is supported");
01059       for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
01060            i != NumOps; ++i) {
01061         const MachineOperand &MO = MI->getOperand(i);
01062         // Actually, there should never be any impdef stuff here. Skip it
01063         // temporary to workaround PR11902.
01064         if (MO.isImplicit())
01065           continue;
01066         RegList.push_back(MO.getReg());
01067       }
01068       break;
01069     case ARM::STR_PRE_IMM:
01070     case ARM::STR_PRE_REG:
01071     case ARM::t2STR_PRE:
01072       assert(MI->getOperand(2).getReg() == ARM::SP &&
01073              "Only stack pointer as a source reg is supported");
01074       RegList.push_back(SrcReg);
01075       break;
01076     }
01077     if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM)
01078       ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
01079   } else {
01080     // Changes of stack / frame pointer.
01081     if (SrcReg == ARM::SP) {
01082       int64_t Offset = 0;
01083       switch (Opc) {
01084       default:
01085         MI->dump();
01086         llvm_unreachable("Unsupported opcode for unwinding information");
01087       case ARM::MOVr:
01088       case ARM::tMOVr:
01089         Offset = 0;
01090         break;
01091       case ARM::ADDri:
01092         Offset = -MI->getOperand(2).getImm();
01093         break;
01094       case ARM::SUBri:
01095       case ARM::t2SUBri:
01096         Offset = MI->getOperand(2).getImm();
01097         break;
01098       case ARM::tSUBspi:
01099         Offset = MI->getOperand(2).getImm()*4;
01100         break;
01101       case ARM::tADDspi:
01102       case ARM::tADDrSPi:
01103         Offset = -MI->getOperand(2).getImm()*4;
01104         break;
01105       case ARM::tLDRpci: {
01106         // Grab the constpool index and check, whether it corresponds to
01107         // original or cloned constpool entry.
01108         unsigned CPI = MI->getOperand(1).getIndex();
01109         const MachineConstantPool *MCP = MF.getConstantPool();
01110         if (CPI >= MCP->getConstants().size())
01111           CPI = AFI.getOriginalCPIdx(CPI);
01112         assert(CPI != -1U && "Invalid constpool index");
01113 
01114         // Derive the actual offset.
01115         const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
01116         assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
01117         // FIXME: Check for user, it should be "add" instruction!
01118         Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
01119         break;
01120       }
01121       }
01122 
01123       if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM) {
01124         if (DstReg == FramePtr && FramePtr != ARM::SP)
01125           // Set-up of the frame pointer. Positive values correspond to "add"
01126           // instruction.
01127           ATS.emitSetFP(FramePtr, ARM::SP, -Offset);
01128         else if (DstReg == ARM::SP) {
01129           // Change of SP by an offset. Positive values correspond to "sub"
01130           // instruction.
01131           ATS.emitPad(Offset);
01132         } else {
01133           // Move of SP to a register.  Positive values correspond to an "add"
01134           // instruction.
01135           ATS.emitMovSP(DstReg, -Offset);
01136         }
01137       }
01138     } else if (DstReg == ARM::SP) {
01139       MI->dump();
01140       llvm_unreachable("Unsupported opcode for unwinding information");
01141     }
01142     else {
01143       MI->dump();
01144       llvm_unreachable("Unsupported opcode for unwinding information");
01145     }
01146   }
01147 }
01148 
01149 // Simple pseudo-instructions have their lowering (with expansion to real
01150 // instructions) auto-generated.
01151 #include "ARMGenMCPseudoLowering.inc"
01152 
01153 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
01154   const DataLayout *DL = TM.getDataLayout();
01155 
01156   // If we just ended a constant pool, mark it as such.
01157   if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
01158     OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
01159     InConstantPool = false;
01160   }
01161 
01162   // Emit unwinding stuff for frame-related instructions
01163   if (Subtarget->isTargetEHABICompatible() &&
01164        MI->getFlag(MachineInstr::FrameSetup))
01165     EmitUnwindingInstruction(MI);
01166 
01167   // Do any auto-generated pseudo lowerings.
01168   if (emitPseudoExpansionLowering(OutStreamer, MI))
01169     return;
01170 
01171   assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
01172          "Pseudo flag setting opcode should be expanded early");
01173 
01174   // Check for manual lowerings.
01175   unsigned Opc = MI->getOpcode();
01176   switch (Opc) {
01177   case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
01178   case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing");
01179   case ARM::LEApcrel:
01180   case ARM::tLEApcrel:
01181   case ARM::t2LEApcrel: {
01182     // FIXME: Need to also handle globals and externals
01183     MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex());
01184     EmitToStreamer(OutStreamer, MCInstBuilder(MI->getOpcode() ==
01185                                               ARM::t2LEApcrel ? ARM::t2ADR
01186                   : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
01187                      : ARM::ADR))
01188       .addReg(MI->getOperand(0).getReg())
01189       .addExpr(MCSymbolRefExpr::Create(CPISymbol, OutContext))
01190       // Add predicate operands.
01191       .addImm(MI->getOperand(2).getImm())
01192       .addReg(MI->getOperand(3).getReg()));
01193     return;
01194   }
01195   case ARM::LEApcrelJT:
01196   case ARM::tLEApcrelJT:
01197   case ARM::t2LEApcrelJT: {
01198     MCSymbol *JTIPICSymbol =
01199       GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
01200                                   MI->getOperand(2).getImm());
01201     EmitToStreamer(OutStreamer, MCInstBuilder(MI->getOpcode() ==
01202                                               ARM::t2LEApcrelJT ? ARM::t2ADR
01203                   : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
01204                      : ARM::ADR))
01205       .addReg(MI->getOperand(0).getReg())
01206       .addExpr(MCSymbolRefExpr::Create(JTIPICSymbol, OutContext))
01207       // Add predicate operands.
01208       .addImm(MI->getOperand(3).getImm())
01209       .addReg(MI->getOperand(4).getReg()));
01210     return;
01211   }
01212   // Darwin call instructions are just normal call instructions with different
01213   // clobber semantics (they clobber R9).
01214   case ARM::BX_CALL: {
01215     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
01216       .addReg(ARM::LR)
01217       .addReg(ARM::PC)
01218       // Add predicate operands.
01219       .addImm(ARMCC::AL)
01220       .addReg(0)
01221       // Add 's' bit operand (always reg0 for this)
01222       .addReg(0));
01223 
01224     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::BX)
01225       .addReg(MI->getOperand(0).getReg()));
01226     return;
01227   }
01228   case ARM::tBX_CALL: {
01229     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
01230       .addReg(ARM::LR)
01231       .addReg(ARM::PC)
01232       // Add predicate operands.
01233       .addImm(ARMCC::AL)
01234       .addReg(0));
01235 
01236     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tBX)
01237       .addReg(MI->getOperand(0).getReg())
01238       // Add predicate operands.
01239       .addImm(ARMCC::AL)
01240       .addReg(0));
01241     return;
01242   }
01243   case ARM::BMOVPCRX_CALL: {
01244     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
01245       .addReg(ARM::LR)
01246       .addReg(ARM::PC)
01247       // Add predicate operands.
01248       .addImm(ARMCC::AL)
01249       .addReg(0)
01250       // Add 's' bit operand (always reg0 for this)
01251       .addReg(0));
01252 
01253     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
01254       .addReg(ARM::PC)
01255       .addReg(MI->getOperand(0).getReg())
01256       // Add predicate operands.
01257       .addImm(ARMCC::AL)
01258       .addReg(0)
01259       // Add 's' bit operand (always reg0 for this)
01260       .addReg(0));
01261     return;
01262   }
01263   case ARM::BMOVPCB_CALL: {
01264     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
01265       .addReg(ARM::LR)
01266       .addReg(ARM::PC)
01267       // Add predicate operands.
01268       .addImm(ARMCC::AL)
01269       .addReg(0)
01270       // Add 's' bit operand (always reg0 for this)
01271       .addReg(0));
01272 
01273     const MachineOperand &Op = MI->getOperand(0);
01274     const GlobalValue *GV = Op.getGlobal();
01275     const unsigned TF = Op.getTargetFlags();
01276     MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
01277     const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
01278     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::Bcc)
01279       .addExpr(GVSymExpr)
01280       // Add predicate operands.
01281       .addImm(ARMCC::AL)
01282       .addReg(0));
01283     return;
01284   }
01285   case ARM::MOVi16_ga_pcrel:
01286   case ARM::t2MOVi16_ga_pcrel: {
01287     MCInst TmpInst;
01288     TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
01289     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
01290 
01291     unsigned TF = MI->getOperand(1).getTargetFlags();
01292     const GlobalValue *GV = MI->getOperand(1).getGlobal();
01293     MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
01294     const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
01295 
01296     MCSymbol *LabelSym = getPICLabel(DL->getPrivateGlobalPrefix(),
01297                                      getFunctionNumber(),
01298                                      MI->getOperand(2).getImm(), OutContext);
01299     const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
01300     unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
01301     const MCExpr *PCRelExpr =
01302       ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
01303                                       MCBinaryExpr::CreateAdd(LabelSymExpr,
01304                                       MCConstantExpr::Create(PCAdj, OutContext),
01305                                       OutContext), OutContext), OutContext);
01306       TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
01307 
01308     // Add predicate operands.
01309     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
01310     TmpInst.addOperand(MCOperand::CreateReg(0));
01311     // Add 's' bit operand (always reg0 for this)
01312     TmpInst.addOperand(MCOperand::CreateReg(0));
01313     EmitToStreamer(OutStreamer, TmpInst);
01314     return;
01315   }
01316   case ARM::MOVTi16_ga_pcrel:
01317   case ARM::t2MOVTi16_ga_pcrel: {
01318     MCInst TmpInst;
01319     TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
01320                       ? ARM::MOVTi16 : ARM::t2MOVTi16);
01321     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
01322     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
01323 
01324     unsigned TF = MI->getOperand(2).getTargetFlags();
01325     const GlobalValue *GV = MI->getOperand(2).getGlobal();
01326     MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
01327     const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
01328 
01329     MCSymbol *LabelSym = getPICLabel(DL->getPrivateGlobalPrefix(),
01330                                      getFunctionNumber(),
01331                                      MI->getOperand(3).getImm(), OutContext);
01332     const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
01333     unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
01334     const MCExpr *PCRelExpr =
01335         ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
01336                                    MCBinaryExpr::CreateAdd(LabelSymExpr,
01337                                       MCConstantExpr::Create(PCAdj, OutContext),
01338                                           OutContext), OutContext), OutContext);
01339       TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
01340     // Add predicate operands.
01341     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
01342     TmpInst.addOperand(MCOperand::CreateReg(0));
01343     // Add 's' bit operand (always reg0 for this)
01344     TmpInst.addOperand(MCOperand::CreateReg(0));
01345     EmitToStreamer(OutStreamer, TmpInst);
01346     return;
01347   }
01348   case ARM::tPICADD: {
01349     // This is a pseudo op for a label + instruction sequence, which looks like:
01350     // LPC0:
01351     //     add r0, pc
01352     // This adds the address of LPC0 to r0.
01353 
01354     // Emit the label.
01355     OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
01356                           getFunctionNumber(), MI->getOperand(2).getImm(),
01357                           OutContext));
01358 
01359     // Form and emit the add.
01360     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tADDhirr)
01361       .addReg(MI->getOperand(0).getReg())
01362       .addReg(MI->getOperand(0).getReg())
01363       .addReg(ARM::PC)
01364       // Add predicate operands.
01365       .addImm(ARMCC::AL)
01366       .addReg(0));
01367     return;
01368   }
01369   case ARM::PICADD: {
01370     // This is a pseudo op for a label + instruction sequence, which looks like:
01371     // LPC0:
01372     //     add r0, pc, r0
01373     // This adds the address of LPC0 to r0.
01374 
01375     // Emit the label.
01376     OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
01377                           getFunctionNumber(), MI->getOperand(2).getImm(),
01378                           OutContext));
01379 
01380     // Form and emit the add.
01381     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDrr)
01382       .addReg(MI->getOperand(0).getReg())
01383       .addReg(ARM::PC)
01384       .addReg(MI->getOperand(1).getReg())
01385       // Add predicate operands.
01386       .addImm(MI->getOperand(3).getImm())
01387       .addReg(MI->getOperand(4).getReg())
01388       // Add 's' bit operand (always reg0 for this)
01389       .addReg(0));
01390     return;
01391   }
01392   case ARM::PICSTR:
01393   case ARM::PICSTRB:
01394   case ARM::PICSTRH:
01395   case ARM::PICLDR:
01396   case ARM::PICLDRB:
01397   case ARM::PICLDRH:
01398   case ARM::PICLDRSB:
01399   case ARM::PICLDRSH: {
01400     // This is a pseudo op for a label + instruction sequence, which looks like:
01401     // LPC0:
01402     //     OP r0, [pc, r0]
01403     // The LCP0 label is referenced by a constant pool entry in order to get
01404     // a PC-relative address at the ldr instruction.
01405 
01406     // Emit the label.
01407     OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
01408                           getFunctionNumber(), MI->getOperand(2).getImm(),
01409                           OutContext));
01410 
01411     // Form and emit the load
01412     unsigned Opcode;
01413     switch (MI->getOpcode()) {
01414     default:
01415       llvm_unreachable("Unexpected opcode!");
01416     case ARM::PICSTR:   Opcode = ARM::STRrs; break;
01417     case ARM::PICSTRB:  Opcode = ARM::STRBrs; break;
01418     case ARM::PICSTRH:  Opcode = ARM::STRH; break;
01419     case ARM::PICLDR:   Opcode = ARM::LDRrs; break;
01420     case ARM::PICLDRB:  Opcode = ARM::LDRBrs; break;
01421     case ARM::PICLDRH:  Opcode = ARM::LDRH; break;
01422     case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
01423     case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
01424     }
01425     EmitToStreamer(OutStreamer, MCInstBuilder(Opcode)
01426       .addReg(MI->getOperand(0).getReg())
01427       .addReg(ARM::PC)
01428       .addReg(MI->getOperand(1).getReg())
01429       .addImm(0)
01430       // Add predicate operands.
01431       .addImm(MI->getOperand(3).getImm())
01432       .addReg(MI->getOperand(4).getReg()));
01433 
01434     return;
01435   }
01436   case ARM::CONSTPOOL_ENTRY: {
01437     /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
01438     /// in the function.  The first operand is the ID# for this instruction, the
01439     /// second is the index into the MachineConstantPool that this is, the third
01440     /// is the size in bytes of this constant pool entry.
01441     /// The required alignment is specified on the basic block holding this MI.
01442     unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
01443     unsigned CPIdx   = (unsigned)MI->getOperand(1).getIndex();
01444 
01445     // If this is the first entry of the pool, mark it.
01446     if (!InConstantPool) {
01447       OutStreamer.EmitDataRegion(MCDR_DataRegion);
01448       InConstantPool = true;
01449     }
01450 
01451     OutStreamer.EmitLabel(GetCPISymbol(LabelId));
01452 
01453     const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
01454     if (MCPE.isMachineConstantPoolEntry())
01455       EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
01456     else
01457       EmitGlobalConstant(MCPE.Val.ConstVal);
01458     return;
01459   }
01460   case ARM::t2BR_JT: {
01461     // Lower and emit the instruction itself, then the jump table following it.
01462     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
01463       .addReg(ARM::PC)
01464       .addReg(MI->getOperand(0).getReg())
01465       // Add predicate operands.
01466       .addImm(ARMCC::AL)
01467       .addReg(0));
01468 
01469     // Output the data for the jump table itself
01470     EmitJump2Table(MI);
01471     return;
01472   }
01473   case ARM::t2TBB_JT: {
01474     // Lower and emit the instruction itself, then the jump table following it.
01475     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::t2TBB)
01476       .addReg(ARM::PC)
01477       .addReg(MI->getOperand(0).getReg())
01478       // Add predicate operands.
01479       .addImm(ARMCC::AL)
01480       .addReg(0));
01481 
01482     // Output the data for the jump table itself
01483     EmitJump2Table(MI);
01484     // Make sure the next instruction is 2-byte aligned.
01485     EmitAlignment(1);
01486     return;
01487   }
01488   case ARM::t2TBH_JT: {
01489     // Lower and emit the instruction itself, then the jump table following it.
01490     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::t2TBH)
01491       .addReg(ARM::PC)
01492       .addReg(MI->getOperand(0).getReg())
01493       // Add predicate operands.
01494       .addImm(ARMCC::AL)
01495       .addReg(0));
01496 
01497     // Output the data for the jump table itself
01498     EmitJump2Table(MI);
01499     return;
01500   }
01501   case ARM::tBR_JTr:
01502   case ARM::BR_JTr: {
01503     // Lower and emit the instruction itself, then the jump table following it.
01504     // mov pc, target
01505     MCInst TmpInst;
01506     unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
01507       ARM::MOVr : ARM::tMOVr;
01508     TmpInst.setOpcode(Opc);
01509     TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
01510     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
01511     // Add predicate operands.
01512     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
01513     TmpInst.addOperand(MCOperand::CreateReg(0));
01514     // Add 's' bit operand (always reg0 for this)
01515     if (Opc == ARM::MOVr)
01516       TmpInst.addOperand(MCOperand::CreateReg(0));
01517     EmitToStreamer(OutStreamer, TmpInst);
01518 
01519     // Make sure the Thumb jump table is 4-byte aligned.
01520     if (Opc == ARM::tMOVr)
01521       EmitAlignment(2);
01522 
01523     // Output the data for the jump table itself
01524     EmitJumpTable(MI);
01525     return;
01526   }
01527   case ARM::BR_JTm: {
01528     // Lower and emit the instruction itself, then the jump table following it.
01529     // ldr pc, target
01530     MCInst TmpInst;
01531     if (MI->getOperand(1).getReg() == 0) {
01532       // literal offset
01533       TmpInst.setOpcode(ARM::LDRi12);
01534       TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
01535       TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
01536       TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
01537     } else {
01538       TmpInst.setOpcode(ARM::LDRrs);
01539       TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
01540       TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
01541       TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
01542       TmpInst.addOperand(MCOperand::CreateImm(0));
01543     }
01544     // Add predicate operands.
01545     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
01546     TmpInst.addOperand(MCOperand::CreateReg(0));
01547     EmitToStreamer(OutStreamer, TmpInst);
01548 
01549     // Output the data for the jump table itself
01550     EmitJumpTable(MI);
01551     return;
01552   }
01553   case ARM::BR_JTadd: {
01554     // Lower and emit the instruction itself, then the jump table following it.
01555     // add pc, target, idx
01556     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDrr)
01557       .addReg(ARM::PC)
01558       .addReg(MI->getOperand(0).getReg())
01559       .addReg(MI->getOperand(1).getReg())
01560       // Add predicate operands.
01561       .addImm(ARMCC::AL)
01562       .addReg(0)
01563       // Add 's' bit operand (always reg0 for this)
01564       .addReg(0));
01565 
01566     // Output the data for the jump table itself
01567     EmitJumpTable(MI);
01568     return;
01569   }
01570   case ARM::TRAP: {
01571     // Non-Darwin binutils don't yet support the "trap" mnemonic.
01572     // FIXME: Remove this special case when they do.
01573     if (!Subtarget->isTargetMachO()) {
01574       //.long 0xe7ffdefe @ trap
01575       uint32_t Val = 0xe7ffdefeUL;
01576       OutStreamer.AddComment("trap");
01577       OutStreamer.EmitIntValue(Val, 4);
01578       return;
01579     }
01580     break;
01581   }
01582   case ARM::TRAPNaCl: {
01583     //.long 0xe7fedef0 @ trap
01584     uint32_t Val = 0xe7fedef0UL;
01585     OutStreamer.AddComment("trap");
01586     OutStreamer.EmitIntValue(Val, 4);
01587     return;
01588   }
01589   case ARM::tTRAP: {
01590     // Non-Darwin binutils don't yet support the "trap" mnemonic.
01591     // FIXME: Remove this special case when they do.
01592     if (!Subtarget->isTargetMachO()) {
01593       //.short 57086 @ trap
01594       uint16_t Val = 0xdefe;
01595       OutStreamer.AddComment("trap");
01596       OutStreamer.EmitIntValue(Val, 2);
01597       return;
01598     }
01599     break;
01600   }
01601   case ARM::t2Int_eh_sjlj_setjmp:
01602   case ARM::t2Int_eh_sjlj_setjmp_nofp:
01603   case ARM::tInt_eh_sjlj_setjmp: {
01604     // Two incoming args: GPR:$src, GPR:$val
01605     // mov $val, pc
01606     // adds $val, #7
01607     // str $val, [$src, #4]
01608     // movs r0, #0
01609     // b 1f
01610     // movs r0, #1
01611     // 1:
01612     unsigned SrcReg = MI->getOperand(0).getReg();
01613     unsigned ValReg = MI->getOperand(1).getReg();
01614     MCSymbol *Label = GetARMSJLJEHLabel();
01615     OutStreamer.AddComment("eh_setjmp begin");
01616     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
01617       .addReg(ValReg)
01618       .addReg(ARM::PC)
01619       // Predicate.
01620       .addImm(ARMCC::AL)
01621       .addReg(0));
01622 
01623     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tADDi3)
01624       .addReg(ValReg)
01625       // 's' bit operand
01626       .addReg(ARM::CPSR)
01627       .addReg(ValReg)
01628       .addImm(7)
01629       // Predicate.
01630       .addImm(ARMCC::AL)
01631       .addReg(0));
01632 
01633     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tSTRi)
01634       .addReg(ValReg)
01635       .addReg(SrcReg)
01636       // The offset immediate is #4. The operand value is scaled by 4 for the
01637       // tSTR instruction.
01638       .addImm(1)
01639       // Predicate.
01640       .addImm(ARMCC::AL)
01641       .addReg(0));
01642 
01643     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVi8)
01644       .addReg(ARM::R0)
01645       .addReg(ARM::CPSR)
01646       .addImm(0)
01647       // Predicate.
01648       .addImm(ARMCC::AL)
01649       .addReg(0));
01650 
01651     const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
01652     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tB)
01653       .addExpr(SymbolExpr)
01654       .addImm(ARMCC::AL)
01655       .addReg(0));
01656 
01657     OutStreamer.AddComment("eh_setjmp end");
01658     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVi8)
01659       .addReg(ARM::R0)
01660       .addReg(ARM::CPSR)
01661       .addImm(1)
01662       // Predicate.
01663       .addImm(ARMCC::AL)
01664       .addReg(0));
01665 
01666     OutStreamer.EmitLabel(Label);
01667     return;
01668   }
01669 
01670   case ARM::Int_eh_sjlj_setjmp_nofp:
01671   case ARM::Int_eh_sjlj_setjmp: {
01672     // Two incoming args: GPR:$src, GPR:$val
01673     // add $val, pc, #8
01674     // str $val, [$src, #+4]
01675     // mov r0, #0
01676     // add pc, pc, #0
01677     // mov r0, #1
01678     unsigned SrcReg = MI->getOperand(0).getReg();
01679     unsigned ValReg = MI->getOperand(1).getReg();
01680 
01681     OutStreamer.AddComment("eh_setjmp begin");
01682     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDri)
01683       .addReg(ValReg)
01684       .addReg(ARM::PC)
01685       .addImm(8)
01686       // Predicate.
01687       .addImm(ARMCC::AL)
01688       .addReg(0)
01689       // 's' bit operand (always reg0 for this).
01690       .addReg(0));
01691 
01692     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::STRi12)
01693       .addReg(ValReg)
01694       .addReg(SrcReg)
01695       .addImm(4)
01696       // Predicate.
01697       .addImm(ARMCC::AL)
01698       .addReg(0));
01699 
01700     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVi)
01701       .addReg(ARM::R0)
01702       .addImm(0)
01703       // Predicate.
01704       .addImm(ARMCC::AL)
01705       .addReg(0)
01706       // 's' bit operand (always reg0 for this).
01707       .addReg(0));
01708 
01709     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDri)
01710       .addReg(ARM::PC)
01711       .addReg(ARM::PC)
01712       .addImm(0)
01713       // Predicate.
01714       .addImm(ARMCC::AL)
01715       .addReg(0)
01716       // 's' bit operand (always reg0 for this).
01717       .addReg(0));
01718 
01719     OutStreamer.AddComment("eh_setjmp end");
01720     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVi)
01721       .addReg(ARM::R0)
01722       .addImm(1)
01723       // Predicate.
01724       .addImm(ARMCC::AL)
01725       .addReg(0)
01726       // 's' bit operand (always reg0 for this).
01727       .addReg(0));
01728     return;
01729   }
01730   case ARM::Int_eh_sjlj_longjmp: {
01731     // ldr sp, [$src, #8]
01732     // ldr $scratch, [$src, #4]
01733     // ldr r7, [$src]
01734     // bx $scratch
01735     unsigned SrcReg = MI->getOperand(0).getReg();
01736     unsigned ScratchReg = MI->getOperand(1).getReg();
01737     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::LDRi12)
01738       .addReg(ARM::SP)
01739       .addReg(SrcReg)
01740       .addImm(8)
01741       // Predicate.
01742       .addImm(ARMCC::AL)
01743       .addReg(0));
01744 
01745     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::LDRi12)
01746       .addReg(ScratchReg)
01747       .addReg(SrcReg)
01748       .addImm(4)
01749       // Predicate.
01750       .addImm(ARMCC::AL)
01751       .addReg(0));
01752 
01753     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::LDRi12)
01754       .addReg(ARM::R7)
01755       .addReg(SrcReg)
01756       .addImm(0)
01757       // Predicate.
01758       .addImm(ARMCC::AL)
01759       .addReg(0));
01760 
01761     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::BX)
01762       .addReg(ScratchReg)
01763       // Predicate.
01764       .addImm(ARMCC::AL)
01765       .addReg(0));
01766     return;
01767   }
01768   case ARM::tInt_eh_sjlj_longjmp: {
01769     // ldr $scratch, [$src, #8]
01770     // mov sp, $scratch
01771     // ldr $scratch, [$src, #4]
01772     // ldr r7, [$src]
01773     // bx $scratch
01774     unsigned SrcReg = MI->getOperand(0).getReg();
01775     unsigned ScratchReg = MI->getOperand(1).getReg();
01776     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tLDRi)
01777       .addReg(ScratchReg)
01778       .addReg(SrcReg)
01779       // The offset immediate is #8. The operand value is scaled by 4 for the
01780       // tLDR instruction.
01781       .addImm(2)
01782       // Predicate.
01783       .addImm(ARMCC::AL)
01784       .addReg(0));
01785 
01786     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
01787       .addReg(ARM::SP)
01788       .addReg(ScratchReg)
01789       // Predicate.
01790       .addImm(ARMCC::AL)
01791       .addReg(0));
01792 
01793     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tLDRi)
01794       .addReg(ScratchReg)
01795       .addReg(SrcReg)
01796       .addImm(1)
01797       // Predicate.
01798       .addImm(ARMCC::AL)
01799       .addReg(0));
01800 
01801     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tLDRi)
01802       .addReg(ARM::R7)
01803       .addReg(SrcReg)
01804       .addImm(0)
01805       // Predicate.
01806       .addImm(ARMCC::AL)
01807       .addReg(0));
01808 
01809     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tBX)
01810       .addReg(ScratchReg)
01811       // Predicate.
01812       .addImm(ARMCC::AL)
01813       .addReg(0));
01814     return;
01815   }
01816   }
01817 
01818   MCInst TmpInst;
01819   LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
01820 
01821   EmitToStreamer(OutStreamer, TmpInst);
01822 }
01823 
01824 //===----------------------------------------------------------------------===//
01825 // Target Registry Stuff
01826 //===----------------------------------------------------------------------===//
01827 
01828 // Force static initialization.
01829 extern "C" void LLVMInitializeARMAsmPrinter() {
01830   RegisterAsmPrinter<ARMAsmPrinter> X(TheARMLETarget);
01831   RegisterAsmPrinter<ARMAsmPrinter> Y(TheARMBETarget);
01832   RegisterAsmPrinter<ARMAsmPrinter> A(TheThumbLETarget);
01833   RegisterAsmPrinter<ARMAsmPrinter> B(TheThumbBETarget);
01834 }