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ARMAsmPrinter.cpp
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00001 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file contains a printer that converts from our internal representation
00011 // of machine-dependent LLVM code to GAS-format ARM assembly language.
00012 //
00013 //===----------------------------------------------------------------------===//
00014 
00015 #include "ARMAsmPrinter.h"
00016 #include "ARM.h"
00017 #include "ARMConstantPoolValue.h"
00018 #include "ARMFPUName.h"
00019 #include "ARMArchExtName.h"
00020 #include "ARMMachineFunctionInfo.h"
00021 #include "ARMTargetMachine.h"
00022 #include "ARMTargetObjectFile.h"
00023 #include "InstPrinter/ARMInstPrinter.h"
00024 #include "MCTargetDesc/ARMAddressingModes.h"
00025 #include "MCTargetDesc/ARMMCExpr.h"
00026 #include "llvm/ADT/SetVector.h"
00027 #include "llvm/ADT/SmallString.h"
00028 #include "llvm/CodeGen/MachineFunctionPass.h"
00029 #include "llvm/CodeGen/MachineJumpTableInfo.h"
00030 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
00031 #include "llvm/IR/Constants.h"
00032 #include "llvm/IR/DataLayout.h"
00033 #include "llvm/IR/DebugInfo.h"
00034 #include "llvm/IR/Mangler.h"
00035 #include "llvm/IR/Module.h"
00036 #include "llvm/IR/Type.h"
00037 #include "llvm/MC/MCAsmInfo.h"
00038 #include "llvm/MC/MCAssembler.h"
00039 #include "llvm/MC/MCContext.h"
00040 #include "llvm/MC/MCELFStreamer.h"
00041 #include "llvm/MC/MCInst.h"
00042 #include "llvm/MC/MCInstBuilder.h"
00043 #include "llvm/MC/MCObjectStreamer.h"
00044 #include "llvm/MC/MCSectionMachO.h"
00045 #include "llvm/MC/MCStreamer.h"
00046 #include "llvm/MC/MCSymbol.h"
00047 #include "llvm/Support/ARMBuildAttributes.h"
00048 #include "llvm/Support/COFF.h"
00049 #include "llvm/Support/CommandLine.h"
00050 #include "llvm/Support/Debug.h"
00051 #include "llvm/Support/ELF.h"
00052 #include "llvm/Support/ErrorHandling.h"
00053 #include "llvm/Support/TargetRegistry.h"
00054 #include "llvm/Support/raw_ostream.h"
00055 #include "llvm/Target/TargetMachine.h"
00056 #include <cctype>
00057 using namespace llvm;
00058 
00059 #define DEBUG_TYPE "asm-printer"
00060 
00061 ARMAsmPrinter::ARMAsmPrinter(TargetMachine &TM,
00062                              std::unique_ptr<MCStreamer> Streamer)
00063     : AsmPrinter(TM, std::move(Streamer)), AFI(nullptr), MCP(nullptr),
00064       InConstantPool(false) {}
00065 
00066 void ARMAsmPrinter::EmitFunctionBodyEnd() {
00067   // Make sure to terminate any constant pools that were at the end
00068   // of the function.
00069   if (!InConstantPool)
00070     return;
00071   InConstantPool = false;
00072   OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
00073 }
00074 
00075 void ARMAsmPrinter::EmitFunctionEntryLabel() {
00076   if (AFI->isThumbFunction()) {
00077     OutStreamer.EmitAssemblerFlag(MCAF_Code16);
00078     OutStreamer.EmitThumbFunc(CurrentFnSym);
00079   }
00080 
00081   OutStreamer.EmitLabel(CurrentFnSym);
00082 }
00083 
00084 void ARMAsmPrinter::EmitXXStructor(const Constant *CV) {
00085   uint64_t Size = TM.getDataLayout()->getTypeAllocSize(CV->getType());
00086   assert(Size && "C++ constructor pointer had zero size!");
00087 
00088   const GlobalValue *GV = dyn_cast<GlobalValue>(CV->stripPointerCasts());
00089   assert(GV && "C++ constructor pointer was not a GlobalValue!");
00090 
00091   const MCExpr *E = MCSymbolRefExpr::Create(GetARMGVSymbol(GV,
00092                                                            ARMII::MO_NO_FLAG),
00093                                             (Subtarget->isTargetELF()
00094                                              ? MCSymbolRefExpr::VK_ARM_TARGET1
00095                                              : MCSymbolRefExpr::VK_None),
00096                                             OutContext);
00097 
00098   OutStreamer.EmitValue(E, Size);
00099 }
00100 
00101 /// runOnMachineFunction - This uses the EmitInstruction()
00102 /// method to print assembly for each instruction.
00103 ///
00104 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
00105   AFI = MF.getInfo<ARMFunctionInfo>();
00106   MCP = MF.getConstantPool();
00107   Subtarget = &MF.getSubtarget<ARMSubtarget>();
00108 
00109   SetupMachineFunction(MF);
00110 
00111   if (Subtarget->isTargetCOFF()) {
00112     bool Internal = MF.getFunction()->hasInternalLinkage();
00113     COFF::SymbolStorageClass Scl = Internal ? COFF::IMAGE_SYM_CLASS_STATIC
00114                                             : COFF::IMAGE_SYM_CLASS_EXTERNAL;
00115     int Type = COFF::IMAGE_SYM_DTYPE_FUNCTION << COFF::SCT_COMPLEX_TYPE_SHIFT;
00116 
00117     OutStreamer.BeginCOFFSymbolDef(CurrentFnSym);
00118     OutStreamer.EmitCOFFSymbolStorageClass(Scl);
00119     OutStreamer.EmitCOFFSymbolType(Type);
00120     OutStreamer.EndCOFFSymbolDef();
00121   }
00122 
00123   // Emit the rest of the function body.
00124   EmitFunctionBody();
00125 
00126   // If we need V4T thumb mode Register Indirect Jump pads, emit them.
00127   // These are created per function, rather than per TU, since it's
00128   // relatively easy to exceed the thumb branch range within a TU.
00129   if (! ThumbIndirectPads.empty()) {
00130     OutStreamer.EmitAssemblerFlag(MCAF_Code16);
00131     EmitAlignment(1);
00132     for (unsigned i = 0, e = ThumbIndirectPads.size(); i < e; i++) {
00133       OutStreamer.EmitLabel(ThumbIndirectPads[i].second);
00134       EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tBX)
00135         .addReg(ThumbIndirectPads[i].first)
00136         // Add predicate operands.
00137         .addImm(ARMCC::AL)
00138         .addReg(0));
00139     }
00140     ThumbIndirectPads.clear();
00141   }
00142 
00143   // We didn't modify anything.
00144   return false;
00145 }
00146 
00147 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
00148                                  raw_ostream &O, const char *Modifier) {
00149   const MachineOperand &MO = MI->getOperand(OpNum);
00150   unsigned TF = MO.getTargetFlags();
00151 
00152   switch (MO.getType()) {
00153   default: llvm_unreachable("<unknown operand type>");
00154   case MachineOperand::MO_Register: {
00155     unsigned Reg = MO.getReg();
00156     assert(TargetRegisterInfo::isPhysicalRegister(Reg));
00157     assert(!MO.getSubReg() && "Subregs should be eliminated!");
00158     if(ARM::GPRPairRegClass.contains(Reg)) {
00159       const MachineFunction &MF = *MI->getParent()->getParent();
00160       const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
00161       Reg = TRI->getSubReg(Reg, ARM::gsub_0);
00162     }
00163     O << ARMInstPrinter::getRegisterName(Reg);
00164     break;
00165   }
00166   case MachineOperand::MO_Immediate: {
00167     int64_t Imm = MO.getImm();
00168     O << '#';
00169     if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
00170         (TF == ARMII::MO_LO16))
00171       O << ":lower16:";
00172     else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
00173              (TF == ARMII::MO_HI16))
00174       O << ":upper16:";
00175     O << Imm;
00176     break;
00177   }
00178   case MachineOperand::MO_MachineBasicBlock:
00179     O << *MO.getMBB()->getSymbol();
00180     return;
00181   case MachineOperand::MO_GlobalAddress: {
00182     const GlobalValue *GV = MO.getGlobal();
00183     if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
00184         (TF & ARMII::MO_LO16))
00185       O << ":lower16:";
00186     else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
00187              (TF & ARMII::MO_HI16))
00188       O << ":upper16:";
00189     O << *GetARMGVSymbol(GV, TF);
00190 
00191     printOffset(MO.getOffset(), O);
00192     if (TF == ARMII::MO_PLT)
00193       O << "(PLT)";
00194     break;
00195   }
00196   case MachineOperand::MO_ConstantPoolIndex:
00197     O << *GetCPISymbol(MO.getIndex());
00198     break;
00199   }
00200 }
00201 
00202 //===--------------------------------------------------------------------===//
00203 
00204 MCSymbol *ARMAsmPrinter::
00205 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
00206   const DataLayout *DL = TM.getDataLayout();
00207   SmallString<60> Name;
00208   raw_svector_ostream(Name) << DL->getPrivateGlobalPrefix() << "JTI"
00209     << getFunctionNumber() << '_' << uid << '_' << uid2;
00210   return OutContext.GetOrCreateSymbol(Name);
00211 }
00212 
00213 
00214 MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel() const {
00215   const DataLayout *DL = TM.getDataLayout();
00216   SmallString<60> Name;
00217   raw_svector_ostream(Name) << DL->getPrivateGlobalPrefix() << "SJLJEH"
00218     << getFunctionNumber();
00219   return OutContext.GetOrCreateSymbol(Name);
00220 }
00221 
00222 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
00223                                     unsigned AsmVariant, const char *ExtraCode,
00224                                     raw_ostream &O) {
00225   // Does this asm operand have a single letter operand modifier?
00226   if (ExtraCode && ExtraCode[0]) {
00227     if (ExtraCode[1] != 0) return true; // Unknown modifier.
00228 
00229     switch (ExtraCode[0]) {
00230     default:
00231       // See if this is a generic print operand
00232       return AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O);
00233     case 'a': // Print as a memory address.
00234       if (MI->getOperand(OpNum).isReg()) {
00235         O << "["
00236           << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
00237           << "]";
00238         return false;
00239       }
00240       // Fallthrough
00241     case 'c': // Don't print "#" before an immediate operand.
00242       if (!MI->getOperand(OpNum).isImm())
00243         return true;
00244       O << MI->getOperand(OpNum).getImm();
00245       return false;
00246     case 'P': // Print a VFP double precision register.
00247     case 'q': // Print a NEON quad precision register.
00248       printOperand(MI, OpNum, O);
00249       return false;
00250     case 'y': // Print a VFP single precision register as indexed double.
00251       if (MI->getOperand(OpNum).isReg()) {
00252         unsigned Reg = MI->getOperand(OpNum).getReg();
00253         const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
00254         // Find the 'd' register that has this 's' register as a sub-register,
00255         // and determine the lane number.
00256         for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
00257           if (!ARM::DPRRegClass.contains(*SR))
00258             continue;
00259           bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
00260           O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");
00261           return false;
00262         }
00263       }
00264       return true;
00265     case 'B': // Bitwise inverse of integer or symbol without a preceding #.
00266       if (!MI->getOperand(OpNum).isImm())
00267         return true;
00268       O << ~(MI->getOperand(OpNum).getImm());
00269       return false;
00270     case 'L': // The low 16 bits of an immediate constant.
00271       if (!MI->getOperand(OpNum).isImm())
00272         return true;
00273       O << (MI->getOperand(OpNum).getImm() & 0xffff);
00274       return false;
00275     case 'M': { // A register range suitable for LDM/STM.
00276       if (!MI->getOperand(OpNum).isReg())
00277         return true;
00278       const MachineOperand &MO = MI->getOperand(OpNum);
00279       unsigned RegBegin = MO.getReg();
00280       // This takes advantage of the 2 operand-ness of ldm/stm and that we've
00281       // already got the operands in registers that are operands to the
00282       // inline asm statement.
00283       O << "{";
00284       if (ARM::GPRPairRegClass.contains(RegBegin)) {
00285         const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
00286         unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
00287         O << ARMInstPrinter::getRegisterName(Reg0) << ", ";
00288         RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1);
00289       }
00290       O << ARMInstPrinter::getRegisterName(RegBegin);
00291 
00292       // FIXME: The register allocator not only may not have given us the
00293       // registers in sequence, but may not be in ascending registers. This
00294       // will require changes in the register allocator that'll need to be
00295       // propagated down here if the operands change.
00296       unsigned RegOps = OpNum + 1;
00297       while (MI->getOperand(RegOps).isReg()) {
00298         O << ", "
00299           << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
00300         RegOps++;
00301       }
00302 
00303       O << "}";
00304 
00305       return false;
00306     }
00307     case 'R': // The most significant register of a pair.
00308     case 'Q': { // The least significant register of a pair.
00309       if (OpNum == 0)
00310         return true;
00311       const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
00312       if (!FlagsOP.isImm())
00313         return true;
00314       unsigned Flags = FlagsOP.getImm();
00315 
00316       // This operand may not be the one that actually provides the register. If
00317       // it's tied to a previous one then we should refer instead to that one
00318       // for registers and their classes.
00319       unsigned TiedIdx;
00320       if (InlineAsm::isUseOperandTiedToDef(Flags, TiedIdx)) {
00321         for (OpNum = InlineAsm::MIOp_FirstOperand; TiedIdx; --TiedIdx) {
00322           unsigned OpFlags = MI->getOperand(OpNum).getImm();
00323           OpNum += InlineAsm::getNumOperandRegisters(OpFlags) + 1;
00324         }
00325         Flags = MI->getOperand(OpNum).getImm();
00326 
00327         // Later code expects OpNum to be pointing at the register rather than
00328         // the flags.
00329         OpNum += 1;
00330       }
00331 
00332       unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
00333       unsigned RC;
00334       InlineAsm::hasRegClassConstraint(Flags, RC);
00335       if (RC == ARM::GPRPairRegClassID) {
00336         if (NumVals != 1)
00337           return true;
00338         const MachineOperand &MO = MI->getOperand(OpNum);
00339         if (!MO.isReg())
00340           return true;
00341         const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
00342         unsigned Reg = TRI->getSubReg(MO.getReg(), ExtraCode[0] == 'Q' ?
00343             ARM::gsub_0 : ARM::gsub_1);
00344         O << ARMInstPrinter::getRegisterName(Reg);
00345         return false;
00346       }
00347       if (NumVals != 2)
00348         return true;
00349       unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
00350       if (RegOp >= MI->getNumOperands())
00351         return true;
00352       const MachineOperand &MO = MI->getOperand(RegOp);
00353       if (!MO.isReg())
00354         return true;
00355       unsigned Reg = MO.getReg();
00356       O << ARMInstPrinter::getRegisterName(Reg);
00357       return false;
00358     }
00359 
00360     case 'e': // The low doubleword register of a NEON quad register.
00361     case 'f': { // The high doubleword register of a NEON quad register.
00362       if (!MI->getOperand(OpNum).isReg())
00363         return true;
00364       unsigned Reg = MI->getOperand(OpNum).getReg();
00365       if (!ARM::QPRRegClass.contains(Reg))
00366         return true;
00367       const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
00368       unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
00369                                        ARM::dsub_0 : ARM::dsub_1);
00370       O << ARMInstPrinter::getRegisterName(SubReg);
00371       return false;
00372     }
00373 
00374     // This modifier is not yet supported.
00375     case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
00376       return true;
00377     case 'H': { // The highest-numbered register of a pair.
00378       const MachineOperand &MO = MI->getOperand(OpNum);
00379       if (!MO.isReg())
00380         return true;
00381       const MachineFunction &MF = *MI->getParent()->getParent();
00382       const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
00383       unsigned Reg = MO.getReg();
00384       if(!ARM::GPRPairRegClass.contains(Reg))
00385         return false;
00386       Reg = TRI->getSubReg(Reg, ARM::gsub_1);
00387       O << ARMInstPrinter::getRegisterName(Reg);
00388       return false;
00389     }
00390     }
00391   }
00392 
00393   printOperand(MI, OpNum, O);
00394   return false;
00395 }
00396 
00397 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
00398                                           unsigned OpNum, unsigned AsmVariant,
00399                                           const char *ExtraCode,
00400                                           raw_ostream &O) {
00401   // Does this asm operand have a single letter operand modifier?
00402   if (ExtraCode && ExtraCode[0]) {
00403     if (ExtraCode[1] != 0) return true; // Unknown modifier.
00404 
00405     switch (ExtraCode[0]) {
00406       case 'A': // A memory operand for a VLD1/VST1 instruction.
00407       default: return true;  // Unknown modifier.
00408       case 'm': // The base register of a memory operand.
00409         if (!MI->getOperand(OpNum).isReg())
00410           return true;
00411         O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
00412         return false;
00413     }
00414   }
00415 
00416   const MachineOperand &MO = MI->getOperand(OpNum);
00417   assert(MO.isReg() && "unexpected inline asm memory operand");
00418   O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
00419   return false;
00420 }
00421 
00422 static bool isThumb(const MCSubtargetInfo& STI) {
00423   return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
00424 }
00425 
00426 void ARMAsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo &StartInfo,
00427                                      const MCSubtargetInfo *EndInfo) const {
00428   // If either end mode is unknown (EndInfo == NULL) or different than
00429   // the start mode, then restore the start mode.
00430   const bool WasThumb = isThumb(StartInfo);
00431   if (!EndInfo || WasThumb != isThumb(*EndInfo)) {
00432     OutStreamer.EmitAssemblerFlag(WasThumb ? MCAF_Code16 : MCAF_Code32);
00433   }
00434 }
00435 
00436 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
00437   Triple TT(TM.getTargetTriple());
00438   // Use unified assembler syntax.
00439   OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
00440 
00441   // Emit ARM Build Attributes
00442   if (TT.isOSBinFormatELF())
00443     emitAttributes();
00444 
00445   // Use the triple's architecture and subarchitecture to determine
00446   // if we're thumb for the purposes of the top level code16 assembler
00447   // flag.
00448   bool isThumb = TT.getArch() == Triple::thumb ||
00449                  TT.getArch() == Triple::thumbeb ||
00450                  TT.getSubArch() == Triple::ARMSubArch_v7m ||
00451                  TT.getSubArch() == Triple::ARMSubArch_v6m;
00452   if (!M.getModuleInlineAsm().empty() && isThumb)
00453     OutStreamer.EmitAssemblerFlag(MCAF_Code16);
00454 }
00455 
00456 static void
00457 emitNonLazySymbolPointer(MCStreamer &OutStreamer, MCSymbol *StubLabel,
00458                          MachineModuleInfoImpl::StubValueTy &MCSym) {
00459   // L_foo$stub:
00460   OutStreamer.EmitLabel(StubLabel);
00461   //   .indirect_symbol _foo
00462   OutStreamer.EmitSymbolAttribute(MCSym.getPointer(), MCSA_IndirectSymbol);
00463 
00464   if (MCSym.getInt())
00465     // External to current translation unit.
00466     OutStreamer.EmitIntValue(0, 4/*size*/);
00467   else
00468     // Internal to current translation unit.
00469     //
00470     // When we place the LSDA into the TEXT section, the type info
00471     // pointers need to be indirect and pc-rel. We accomplish this by
00472     // using NLPs; however, sometimes the types are local to the file.
00473     // We need to fill in the value for the NLP in those cases.
00474     OutStreamer.EmitValue(
00475         MCSymbolRefExpr::Create(MCSym.getPointer(), OutStreamer.getContext()),
00476         4 /*size*/);
00477 }
00478 
00479 
00480 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
00481   Triple TT(TM.getTargetTriple());
00482   if (TT.isOSBinFormatMachO()) {
00483     // All darwin targets use mach-o.
00484     const TargetLoweringObjectFileMachO &TLOFMacho =
00485       static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
00486     MachineModuleInfoMachO &MMIMacho =
00487       MMI->getObjFileInfo<MachineModuleInfoMachO>();
00488 
00489     // Output non-lazy-pointers for external and common global variables.
00490     MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
00491 
00492     if (!Stubs.empty()) {
00493       // Switch with ".non_lazy_symbol_pointer" directive.
00494       OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
00495       EmitAlignment(2);
00496 
00497       for (auto &Stub : Stubs)
00498         emitNonLazySymbolPointer(OutStreamer, Stub.first, Stub.second);
00499 
00500       Stubs.clear();
00501       OutStreamer.AddBlankLine();
00502     }
00503 
00504     Stubs = MMIMacho.GetHiddenGVStubList();
00505     if (!Stubs.empty()) {
00506       OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
00507       EmitAlignment(2);
00508 
00509       for (auto &Stub : Stubs)
00510         emitNonLazySymbolPointer(OutStreamer, Stub.first, Stub.second);
00511 
00512       Stubs.clear();
00513       OutStreamer.AddBlankLine();
00514     }
00515 
00516     // Funny Darwin hack: This flag tells the linker that no global symbols
00517     // contain code that falls through to other global symbols (e.g. the obvious
00518     // implementation of multiple entry points).  If this doesn't occur, the
00519     // linker can safely perform dead code stripping.  Since LLVM never
00520     // generates code that does this, it is always safe to set.
00521     OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
00522   }
00523 }
00524 
00525 //===----------------------------------------------------------------------===//
00526 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
00527 // FIXME:
00528 // The following seem like one-off assembler flags, but they actually need
00529 // to appear in the .ARM.attributes section in ELF.
00530 // Instead of subclassing the MCELFStreamer, we do the work here.
00531 
00532 static ARMBuildAttrs::CPUArch getArchForCPU(StringRef CPU,
00533                                             const ARMSubtarget *Subtarget) {
00534   if (CPU == "xscale")
00535     return ARMBuildAttrs::v5TEJ;
00536 
00537   if (Subtarget->hasV8Ops())
00538     return ARMBuildAttrs::v8;
00539   else if (Subtarget->hasV7Ops()) {
00540     if (Subtarget->isMClass() && Subtarget->hasThumb2DSP())
00541       return ARMBuildAttrs::v7E_M;
00542     return ARMBuildAttrs::v7;
00543   } else if (Subtarget->hasV6T2Ops())
00544     return ARMBuildAttrs::v6T2;
00545   else if (Subtarget->hasV6MOps())
00546     return ARMBuildAttrs::v6S_M;
00547   else if (Subtarget->hasV6Ops())
00548     return ARMBuildAttrs::v6;
00549   else if (Subtarget->hasV5TEOps())
00550     return ARMBuildAttrs::v5TE;
00551   else if (Subtarget->hasV5TOps())
00552     return ARMBuildAttrs::v5T;
00553   else if (Subtarget->hasV4TOps())
00554     return ARMBuildAttrs::v4T;
00555   else
00556     return ARMBuildAttrs::v4;
00557 }
00558 
00559 void ARMAsmPrinter::emitAttributes() {
00560   MCTargetStreamer &TS = *OutStreamer.getTargetStreamer();
00561   ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
00562 
00563   ATS.emitTextAttribute(ARMBuildAttrs::conformance, "2.09");
00564 
00565   ATS.switchVendor("aeabi");
00566 
00567   // Compute ARM ELF Attributes based on the default subtarget that
00568   // we'd have constructed. The existing ARM behavior isn't LTO clean
00569   // anyhow.
00570   // FIXME: For ifunc related functions we could iterate over and look
00571   // for a feature string that doesn't match the default one.
00572   StringRef TT = TM.getTargetTriple();
00573   StringRef CPU = TM.getTargetCPU();
00574   StringRef FS = TM.getTargetFeatureString();
00575   std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
00576   if (!FS.empty()) {
00577     if (!ArchFS.empty())
00578       ArchFS = (Twine(ArchFS) + "," + FS).str();
00579     else
00580       ArchFS = FS;
00581   }
00582   const ARMBaseTargetMachine &ATM =
00583       static_cast<const ARMBaseTargetMachine &>(TM);
00584   const ARMSubtarget STI(TT, CPU, ArchFS, ATM, ATM.isLittleEndian());
00585 
00586   std::string CPUString = STI.getCPUString();
00587 
00588   if (CPUString.find("generic") != 0) { //CPUString doesn't start with "generic"
00589     // FIXME: remove krait check when GNU tools support krait cpu
00590     if (STI.isKrait()) {
00591       ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a9");
00592       // We consider krait as a "cortex-a9" + hwdiv CPU
00593       // Enable hwdiv through ".arch_extension idiv"
00594       if (STI.hasDivide() || STI.hasDivideInARMMode())
00595         ATS.emitArchExtension(ARM::HWDIV);
00596     } else
00597       ATS.emitTextAttribute(ARMBuildAttrs::CPU_name, CPUString);
00598   }
00599 
00600   ATS.emitAttribute(ARMBuildAttrs::CPU_arch, getArchForCPU(CPUString, &STI));
00601 
00602   // Tag_CPU_arch_profile must have the default value of 0 when "Architecture
00603   // profile is not applicable (e.g. pre v7, or cross-profile code)".
00604   if (STI.hasV7Ops()) {
00605     if (STI.isAClass()) {
00606       ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
00607                         ARMBuildAttrs::ApplicationProfile);
00608     } else if (STI.isRClass()) {
00609       ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
00610                         ARMBuildAttrs::RealTimeProfile);
00611     } else if (STI.isMClass()) {
00612       ATS.emitAttribute(ARMBuildAttrs::CPU_arch_profile,
00613                         ARMBuildAttrs::MicroControllerProfile);
00614     }
00615   }
00616 
00617   ATS.emitAttribute(ARMBuildAttrs::ARM_ISA_use,
00618                     STI.hasARMOps() ? ARMBuildAttrs::Allowed
00619                                     : ARMBuildAttrs::Not_Allowed);
00620   if (STI.isThumb1Only()) {
00621     ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use, ARMBuildAttrs::Allowed);
00622   } else if (STI.hasThumb2()) {
00623     ATS.emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
00624                       ARMBuildAttrs::AllowThumb32);
00625   }
00626 
00627   if (STI.hasNEON()) {
00628     /* NEON is not exactly a VFP architecture, but GAS emit one of
00629      * neon/neon-fp-armv8/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
00630     if (STI.hasFPARMv8()) {
00631       if (STI.hasCrypto())
00632         ATS.emitFPU(ARM::CRYPTO_NEON_FP_ARMV8);
00633       else
00634         ATS.emitFPU(ARM::NEON_FP_ARMV8);
00635     } else if (STI.hasVFP4())
00636       ATS.emitFPU(ARM::NEON_VFPV4);
00637     else
00638       ATS.emitFPU(ARM::NEON);
00639     // Emit Tag_Advanced_SIMD_arch for ARMv8 architecture
00640     if (STI.hasV8Ops())
00641       ATS.emitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
00642                         STI.hasV8_1aOps() ? ARMBuildAttrs::AllowNeonARMv8_1a:
00643                                             ARMBuildAttrs::AllowNeonARMv8);
00644   } else {
00645     if (STI.hasFPARMv8())
00646       // FPv5 and FP-ARMv8 have the same instructions, so are modeled as one
00647       // FPU, but there are two different names for it depending on the CPU.
00648       ATS.emitFPU(STI.hasD16() ? ARM::FPV5_D16 : ARM::FP_ARMV8);
00649     else if (STI.hasVFP4())
00650       ATS.emitFPU(STI.hasD16() ? ARM::VFPV4_D16 : ARM::VFPV4);
00651     else if (STI.hasVFP3())
00652       ATS.emitFPU(STI.hasD16() ? ARM::VFPV3_D16 : ARM::VFPV3);
00653     else if (STI.hasVFP2())
00654       ATS.emitFPU(ARM::VFPV2);
00655   }
00656 
00657   if (TM.getRelocationModel() == Reloc::PIC_) {
00658     // PIC specific attributes.
00659     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RW_data,
00660                       ARMBuildAttrs::AddressRWPCRel);
00661     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RO_data,
00662                       ARMBuildAttrs::AddressROPCRel);
00663     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_GOT_use,
00664                       ARMBuildAttrs::AddressGOT);
00665   } else {
00666     // Allow direct addressing of imported data for all other relocation models.
00667     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_GOT_use,
00668                       ARMBuildAttrs::AddressDirect);
00669   }
00670 
00671   // Signal various FP modes.
00672   if (!TM.Options.UnsafeFPMath) {
00673     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
00674                       ARMBuildAttrs::IEEEDenormals);
00675     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_exceptions, ARMBuildAttrs::Allowed);
00676 
00677     // If the user has permitted this code to choose the IEEE 754
00678     // rounding at run-time, emit the rounding attribute.
00679     if (TM.Options.HonorSignDependentRoundingFPMathOption)
00680       ATS.emitAttribute(ARMBuildAttrs::ABI_FP_rounding, ARMBuildAttrs::Allowed);
00681   } else {
00682     if (!STI.hasVFP2()) {
00683       // When the target doesn't have an FPU (by design or
00684       // intention), the assumptions made on the software support
00685       // mirror that of the equivalent hardware support *if it
00686       // existed*. For v7 and better we indicate that denormals are
00687       // flushed preserving sign, and for V6 we indicate that
00688       // denormals are flushed to positive zero.
00689       if (STI.hasV7Ops())
00690         ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
00691                           ARMBuildAttrs::PreserveFPSign);
00692     } else if (STI.hasVFP3()) {
00693       // In VFPv4, VFPv4U, VFPv3, or VFPv3U, it is preserved. That is,
00694       // the sign bit of the zero matches the sign bit of the input or
00695       // result that is being flushed to zero.
00696       ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
00697                         ARMBuildAttrs::PreserveFPSign);
00698     }
00699     // For VFPv2 implementations it is implementation defined as
00700     // to whether denormals are flushed to positive zero or to
00701     // whatever the sign of zero is (ARM v7AR ARM 2.7.5). Historically
00702     // LLVM has chosen to flush this to positive zero (most likely for
00703     // GCC compatibility), so that's the chosen value here (the
00704     // absence of its emission implies zero).
00705   }
00706 
00707   // TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath is the
00708   // equivalent of GCC's -ffinite-math-only flag.
00709   if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
00710     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
00711                       ARMBuildAttrs::Allowed);
00712   else
00713     ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
00714                       ARMBuildAttrs::AllowIEE754);
00715 
00716   if (STI.allowsUnalignedMem())
00717     ATS.emitAttribute(ARMBuildAttrs::CPU_unaligned_access,
00718                       ARMBuildAttrs::Allowed);
00719   else
00720     ATS.emitAttribute(ARMBuildAttrs::CPU_unaligned_access,
00721                       ARMBuildAttrs::Not_Allowed);
00722 
00723   // FIXME: add more flags to ARMBuildAttributes.h
00724   // 8-bytes alignment stuff.
00725   ATS.emitAttribute(ARMBuildAttrs::ABI_align_needed, 1);
00726   ATS.emitAttribute(ARMBuildAttrs::ABI_align_preserved, 1);
00727 
00728   // ABI_HardFP_use attribute to indicate single precision FP.
00729   if (STI.isFPOnlySP())
00730     ATS.emitAttribute(ARMBuildAttrs::ABI_HardFP_use,
00731                       ARMBuildAttrs::HardFPSinglePrecision);
00732 
00733   // Hard float.  Use both S and D registers and conform to AAPCS-VFP.
00734   if (STI.isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard)
00735     ATS.emitAttribute(ARMBuildAttrs::ABI_VFP_args, ARMBuildAttrs::HardFPAAPCS);
00736 
00737   // FIXME: Should we signal R9 usage?
00738 
00739   if (STI.hasFP16())
00740     ATS.emitAttribute(ARMBuildAttrs::FP_HP_extension, ARMBuildAttrs::AllowHPFP);
00741 
00742   // FIXME: To support emitting this build attribute as GCC does, the
00743   // -mfp16-format option and associated plumbing must be
00744   // supported. For now the __fp16 type is exposed by default, so this
00745   // attribute should be emitted with value 1.
00746   ATS.emitAttribute(ARMBuildAttrs::ABI_FP_16bit_format,
00747                     ARMBuildAttrs::FP16FormatIEEE);
00748 
00749   if (STI.hasMPExtension())
00750     ATS.emitAttribute(ARMBuildAttrs::MPextension_use, ARMBuildAttrs::AllowMP);
00751 
00752   // Hardware divide in ARM mode is part of base arch, starting from ARMv8.
00753   // If only Thumb hwdiv is present, it must also be in base arch (ARMv7-R/M).
00754   // It is not possible to produce DisallowDIV: if hwdiv is present in the base
00755   // arch, supplying -hwdiv downgrades the effective arch, via ClearImpliedBits.
00756   // AllowDIVExt is only emitted if hwdiv isn't available in the base arch;
00757   // otherwise, the default value (AllowDIVIfExists) applies.
00758   if (STI.hasDivideInARMMode() && !STI.hasV8Ops())
00759     ATS.emitAttribute(ARMBuildAttrs::DIV_use, ARMBuildAttrs::AllowDIVExt);
00760 
00761   if (MMI) {
00762     if (const Module *SourceModule = MMI->getModule()) {
00763       // ABI_PCS_wchar_t to indicate wchar_t width
00764       // FIXME: There is no way to emit value 0 (wchar_t prohibited).
00765       if (auto WCharWidthValue = mdconst::extract_or_null<ConstantInt>(
00766               SourceModule->getModuleFlag("wchar_size"))) {
00767         int WCharWidth = WCharWidthValue->getZExtValue();
00768         assert((WCharWidth == 2 || WCharWidth == 4) &&
00769                "wchar_t width must be 2 or 4 bytes");
00770         ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_wchar_t, WCharWidth);
00771       }
00772 
00773       // ABI_enum_size to indicate enum width
00774       // FIXME: There is no way to emit value 0 (enums prohibited) or value 3
00775       //        (all enums contain a value needing 32 bits to encode).
00776       if (auto EnumWidthValue = mdconst::extract_or_null<ConstantInt>(
00777               SourceModule->getModuleFlag("min_enum_size"))) {
00778         int EnumWidth = EnumWidthValue->getZExtValue();
00779         assert((EnumWidth == 1 || EnumWidth == 4) &&
00780                "Minimum enum width must be 1 or 4 bytes");
00781         int EnumBuildAttr = EnumWidth == 1 ? 1 : 2;
00782         ATS.emitAttribute(ARMBuildAttrs::ABI_enum_size, EnumBuildAttr);
00783       }
00784     }
00785   }
00786 
00787   // TODO: We currently only support either reserving the register, or treating
00788   // it as another callee-saved register, but not as SB or a TLS pointer; It
00789   // would instead be nicer to push this from the frontend as metadata, as we do
00790   // for the wchar and enum size tags
00791   if (STI.isR9Reserved())
00792     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use, ARMBuildAttrs::R9Reserved);
00793   else
00794     ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use, ARMBuildAttrs::R9IsGPR);
00795 
00796   if (STI.hasTrustZone() && STI.hasVirtualization())
00797     ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
00798                       ARMBuildAttrs::AllowTZVirtualization);
00799   else if (STI.hasTrustZone())
00800     ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
00801                       ARMBuildAttrs::AllowTZ);
00802   else if (STI.hasVirtualization())
00803     ATS.emitAttribute(ARMBuildAttrs::Virtualization_use,
00804                       ARMBuildAttrs::AllowVirtualization);
00805 
00806   ATS.finishAttributeSection();
00807 }
00808 
00809 //===----------------------------------------------------------------------===//
00810 
00811 static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
00812                              unsigned LabelId, MCContext &Ctx) {
00813 
00814   MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
00815                        + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
00816   return Label;
00817 }
00818 
00819 static MCSymbolRefExpr::VariantKind
00820 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
00821   switch (Modifier) {
00822   case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
00823   case ARMCP::TLSGD:       return MCSymbolRefExpr::VK_TLSGD;
00824   case ARMCP::TPOFF:       return MCSymbolRefExpr::VK_TPOFF;
00825   case ARMCP::GOTTPOFF:    return MCSymbolRefExpr::VK_GOTTPOFF;
00826   case ARMCP::GOT:         return MCSymbolRefExpr::VK_GOT;
00827   case ARMCP::GOTOFF:      return MCSymbolRefExpr::VK_GOTOFF;
00828   }
00829   llvm_unreachable("Invalid ARMCPModifier!");
00830 }
00831 
00832 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV,
00833                                         unsigned char TargetFlags) {
00834   if (Subtarget->isTargetMachO()) {
00835     bool IsIndirect = (TargetFlags & ARMII::MO_NONLAZY) &&
00836       Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
00837 
00838     if (!IsIndirect)
00839       return getSymbol(GV);
00840 
00841     // FIXME: Remove this when Darwin transition to @GOT like syntax.
00842     MCSymbol *MCSym = getSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
00843     MachineModuleInfoMachO &MMIMachO =
00844       MMI->getObjFileInfo<MachineModuleInfoMachO>();
00845     MachineModuleInfoImpl::StubValueTy &StubSym =
00846       GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym)
00847                                 : MMIMachO.getGVStubEntry(MCSym);
00848     if (!StubSym.getPointer())
00849       StubSym = MachineModuleInfoImpl::StubValueTy(getSymbol(GV),
00850                                                    !GV->hasInternalLinkage());
00851     return MCSym;
00852   } else if (Subtarget->isTargetCOFF()) {
00853     assert(Subtarget->isTargetWindows() &&
00854            "Windows is the only supported COFF target");
00855 
00856     bool IsIndirect = (TargetFlags & ARMII::MO_DLLIMPORT);
00857     if (!IsIndirect)
00858       return getSymbol(GV);
00859 
00860     SmallString<128> Name;
00861     Name = "__imp_";
00862     getNameWithPrefix(Name, GV);
00863 
00864     return OutContext.GetOrCreateSymbol(Name);
00865   } else if (Subtarget->isTargetELF()) {
00866     return getSymbol(GV);
00867   }
00868   llvm_unreachable("unexpected target");
00869 }
00870 
00871 void ARMAsmPrinter::
00872 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
00873   const DataLayout *DL = TM.getDataLayout();
00874   int Size = TM.getDataLayout()->getTypeAllocSize(MCPV->getType());
00875 
00876   ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
00877 
00878   MCSymbol *MCSym;
00879   if (ACPV->isLSDA()) {
00880     MCSym = getCurExceptionSym();
00881   } else if (ACPV->isBlockAddress()) {
00882     const BlockAddress *BA =
00883       cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
00884     MCSym = GetBlockAddressSymbol(BA);
00885   } else if (ACPV->isGlobalValue()) {
00886     const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
00887 
00888     // On Darwin, const-pool entries may get the "FOO$non_lazy_ptr" mangling, so
00889     // flag the global as MO_NONLAZY.
00890     unsigned char TF = Subtarget->isTargetMachO() ? ARMII::MO_NONLAZY : 0;
00891     MCSym = GetARMGVSymbol(GV, TF);
00892   } else if (ACPV->isMachineBasicBlock()) {
00893     const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
00894     MCSym = MBB->getSymbol();
00895   } else {
00896     assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
00897     const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
00898     MCSym = GetExternalSymbolSymbol(Sym);
00899   }
00900 
00901   // Create an MCSymbol for the reference.
00902   const MCExpr *Expr =
00903     MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
00904                             OutContext);
00905 
00906   if (ACPV->getPCAdjustment()) {
00907     MCSymbol *PCLabel = getPICLabel(DL->getPrivateGlobalPrefix(),
00908                                     getFunctionNumber(),
00909                                     ACPV->getLabelId(),
00910                                     OutContext);
00911     const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
00912     PCRelExpr =
00913       MCBinaryExpr::CreateAdd(PCRelExpr,
00914                               MCConstantExpr::Create(ACPV->getPCAdjustment(),
00915                                                      OutContext),
00916                               OutContext);
00917     if (ACPV->mustAddCurrentAddress()) {
00918       // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
00919       // label, so just emit a local label end reference that instead.
00920       MCSymbol *DotSym = OutContext.CreateTempSymbol();
00921       OutStreamer.EmitLabel(DotSym);
00922       const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
00923       PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
00924     }
00925     Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
00926   }
00927   OutStreamer.EmitValue(Expr, Size);
00928 }
00929 
00930 void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
00931   unsigned Opcode = MI->getOpcode();
00932   int OpNum = 1;
00933   if (Opcode == ARM::BR_JTadd)
00934     OpNum = 2;
00935   else if (Opcode == ARM::BR_JTm)
00936     OpNum = 3;
00937 
00938   const MachineOperand &MO1 = MI->getOperand(OpNum);
00939   const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
00940   unsigned JTI = MO1.getIndex();
00941 
00942   // Emit a label for the jump table.
00943   MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
00944   OutStreamer.EmitLabel(JTISymbol);
00945 
00946   // Mark the jump table as data-in-code.
00947   OutStreamer.EmitDataRegion(MCDR_DataRegionJT32);
00948 
00949   // Emit each entry of the table.
00950   const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
00951   const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
00952   const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
00953 
00954   for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
00955     MachineBasicBlock *MBB = JTBBs[i];
00956     // Construct an MCExpr for the entry. We want a value of the form:
00957     // (BasicBlockAddr - TableBeginAddr)
00958     //
00959     // For example, a table with entries jumping to basic blocks BB0 and BB1
00960     // would look like:
00961     // LJTI_0_0:
00962     //    .word (LBB0 - LJTI_0_0)
00963     //    .word (LBB1 - LJTI_0_0)
00964     const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
00965 
00966     if (TM.getRelocationModel() == Reloc::PIC_)
00967       Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
00968                                                                    OutContext),
00969                                      OutContext);
00970     // If we're generating a table of Thumb addresses in static relocation
00971     // model, we need to add one to keep interworking correctly.
00972     else if (AFI->isThumbFunction())
00973       Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(1,OutContext),
00974                                      OutContext);
00975     OutStreamer.EmitValue(Expr, 4);
00976   }
00977   // Mark the end of jump table data-in-code region.
00978   OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
00979 }
00980 
00981 void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
00982   unsigned Opcode = MI->getOpcode();
00983   int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
00984   const MachineOperand &MO1 = MI->getOperand(OpNum);
00985   const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
00986   unsigned JTI = MO1.getIndex();
00987 
00988   MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
00989   OutStreamer.EmitLabel(JTISymbol);
00990 
00991   // Emit each entry of the table.
00992   const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
00993   const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
00994   const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
00995   unsigned OffsetWidth = 4;
00996   if (MI->getOpcode() == ARM::t2TBB_JT) {
00997     OffsetWidth = 1;
00998     // Mark the jump table as data-in-code.
00999     OutStreamer.EmitDataRegion(MCDR_DataRegionJT8);
01000   } else if (MI->getOpcode() == ARM::t2TBH_JT) {
01001     OffsetWidth = 2;
01002     // Mark the jump table as data-in-code.
01003     OutStreamer.EmitDataRegion(MCDR_DataRegionJT16);
01004   }
01005 
01006   for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
01007     MachineBasicBlock *MBB = JTBBs[i];
01008     const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
01009                                                           OutContext);
01010     // If this isn't a TBB or TBH, the entries are direct branch instructions.
01011     if (OffsetWidth == 4) {
01012       EmitToStreamer(OutStreamer, MCInstBuilder(ARM::t2B)
01013         .addExpr(MBBSymbolExpr)
01014         .addImm(ARMCC::AL)
01015         .addReg(0));
01016       continue;
01017     }
01018     // Otherwise it's an offset from the dispatch instruction. Construct an
01019     // MCExpr for the entry. We want a value of the form:
01020     // (BasicBlockAddr - TableBeginAddr) / 2
01021     //
01022     // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
01023     // would look like:
01024     // LJTI_0_0:
01025     //    .byte (LBB0 - LJTI_0_0) / 2
01026     //    .byte (LBB1 - LJTI_0_0) / 2
01027     const MCExpr *Expr =
01028       MCBinaryExpr::CreateSub(MBBSymbolExpr,
01029                               MCSymbolRefExpr::Create(JTISymbol, OutContext),
01030                               OutContext);
01031     Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
01032                                    OutContext);
01033     OutStreamer.EmitValue(Expr, OffsetWidth);
01034   }
01035   // Mark the end of jump table data-in-code region. 32-bit offsets use
01036   // actual branch instructions here, so we don't mark those as a data-region
01037   // at all.
01038   if (OffsetWidth != 4)
01039     OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
01040 }
01041 
01042 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
01043   assert(MI->getFlag(MachineInstr::FrameSetup) &&
01044       "Only instruction which are involved into frame setup code are allowed");
01045 
01046   MCTargetStreamer &TS = *OutStreamer.getTargetStreamer();
01047   ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
01048   const MachineFunction &MF = *MI->getParent()->getParent();
01049   const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
01050   const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
01051 
01052   unsigned FramePtr = RegInfo->getFrameRegister(MF);
01053   unsigned Opc = MI->getOpcode();
01054   unsigned SrcReg, DstReg;
01055 
01056   if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
01057     // Two special cases:
01058     // 1) tPUSH does not have src/dst regs.
01059     // 2) for Thumb1 code we sometimes materialize the constant via constpool
01060     // load. Yes, this is pretty fragile, but for now I don't see better
01061     // way... :(
01062     SrcReg = DstReg = ARM::SP;
01063   } else {
01064     SrcReg = MI->getOperand(1).getReg();
01065     DstReg = MI->getOperand(0).getReg();
01066   }
01067 
01068   // Try to figure out the unwinding opcode out of src / dst regs.
01069   if (MI->mayStore()) {
01070     // Register saves.
01071     assert(DstReg == ARM::SP &&
01072            "Only stack pointer as a destination reg is supported");
01073 
01074     SmallVector<unsigned, 4> RegList;
01075     // Skip src & dst reg, and pred ops.
01076     unsigned StartOp = 2 + 2;
01077     // Use all the operands.
01078     unsigned NumOffset = 0;
01079 
01080     switch (Opc) {
01081     default:
01082       MI->dump();
01083       llvm_unreachable("Unsupported opcode for unwinding information");
01084     case ARM::tPUSH:
01085       // Special case here: no src & dst reg, but two extra imp ops.
01086       StartOp = 2; NumOffset = 2;
01087     case ARM::STMDB_UPD:
01088     case ARM::t2STMDB_UPD:
01089     case ARM::VSTMDDB_UPD:
01090       assert(SrcReg == ARM::SP &&
01091              "Only stack pointer as a source reg is supported");
01092       for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
01093            i != NumOps; ++i) {
01094         const MachineOperand &MO = MI->getOperand(i);
01095         // Actually, there should never be any impdef stuff here. Skip it
01096         // temporary to workaround PR11902.
01097         if (MO.isImplicit())
01098           continue;
01099         RegList.push_back(MO.getReg());
01100       }
01101       break;
01102     case ARM::STR_PRE_IMM:
01103     case ARM::STR_PRE_REG:
01104     case ARM::t2STR_PRE:
01105       assert(MI->getOperand(2).getReg() == ARM::SP &&
01106              "Only stack pointer as a source reg is supported");
01107       RegList.push_back(SrcReg);
01108       break;
01109     }
01110     if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM)
01111       ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
01112   } else {
01113     // Changes of stack / frame pointer.
01114     if (SrcReg == ARM::SP) {
01115       int64_t Offset = 0;
01116       switch (Opc) {
01117       default:
01118         MI->dump();
01119         llvm_unreachable("Unsupported opcode for unwinding information");
01120       case ARM::MOVr:
01121       case ARM::tMOVr:
01122         Offset = 0;
01123         break;
01124       case ARM::ADDri:
01125         Offset = -MI->getOperand(2).getImm();
01126         break;
01127       case ARM::SUBri:
01128       case ARM::t2SUBri:
01129         Offset = MI->getOperand(2).getImm();
01130         break;
01131       case ARM::tSUBspi:
01132         Offset = MI->getOperand(2).getImm()*4;
01133         break;
01134       case ARM::tADDspi:
01135       case ARM::tADDrSPi:
01136         Offset = -MI->getOperand(2).getImm()*4;
01137         break;
01138       case ARM::tLDRpci: {
01139         // Grab the constpool index and check, whether it corresponds to
01140         // original or cloned constpool entry.
01141         unsigned CPI = MI->getOperand(1).getIndex();
01142         const MachineConstantPool *MCP = MF.getConstantPool();
01143         if (CPI >= MCP->getConstants().size())
01144           CPI = AFI.getOriginalCPIdx(CPI);
01145         assert(CPI != -1U && "Invalid constpool index");
01146 
01147         // Derive the actual offset.
01148         const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
01149         assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
01150         // FIXME: Check for user, it should be "add" instruction!
01151         Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
01152         break;
01153       }
01154       }
01155 
01156       if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM) {
01157         if (DstReg == FramePtr && FramePtr != ARM::SP)
01158           // Set-up of the frame pointer. Positive values correspond to "add"
01159           // instruction.
01160           ATS.emitSetFP(FramePtr, ARM::SP, -Offset);
01161         else if (DstReg == ARM::SP) {
01162           // Change of SP by an offset. Positive values correspond to "sub"
01163           // instruction.
01164           ATS.emitPad(Offset);
01165         } else {
01166           // Move of SP to a register.  Positive values correspond to an "add"
01167           // instruction.
01168           ATS.emitMovSP(DstReg, -Offset);
01169         }
01170       }
01171     } else if (DstReg == ARM::SP) {
01172       MI->dump();
01173       llvm_unreachable("Unsupported opcode for unwinding information");
01174     }
01175     else {
01176       MI->dump();
01177       llvm_unreachable("Unsupported opcode for unwinding information");
01178     }
01179   }
01180 }
01181 
01182 // Simple pseudo-instructions have their lowering (with expansion to real
01183 // instructions) auto-generated.
01184 #include "ARMGenMCPseudoLowering.inc"
01185 
01186 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
01187   const DataLayout *DL = TM.getDataLayout();
01188 
01189   // If we just ended a constant pool, mark it as such.
01190   if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
01191     OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
01192     InConstantPool = false;
01193   }
01194 
01195   // Emit unwinding stuff for frame-related instructions
01196   if (Subtarget->isTargetEHABICompatible() &&
01197        MI->getFlag(MachineInstr::FrameSetup))
01198     EmitUnwindingInstruction(MI);
01199 
01200   // Do any auto-generated pseudo lowerings.
01201   if (emitPseudoExpansionLowering(OutStreamer, MI))
01202     return;
01203 
01204   assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
01205          "Pseudo flag setting opcode should be expanded early");
01206 
01207   // Check for manual lowerings.
01208   unsigned Opc = MI->getOpcode();
01209   switch (Opc) {
01210   case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
01211   case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing");
01212   case ARM::LEApcrel:
01213   case ARM::tLEApcrel:
01214   case ARM::t2LEApcrel: {
01215     // FIXME: Need to also handle globals and externals
01216     MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex());
01217     EmitToStreamer(OutStreamer, MCInstBuilder(MI->getOpcode() ==
01218                                               ARM::t2LEApcrel ? ARM::t2ADR
01219                   : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
01220                      : ARM::ADR))
01221       .addReg(MI->getOperand(0).getReg())
01222       .addExpr(MCSymbolRefExpr::Create(CPISymbol, OutContext))
01223       // Add predicate operands.
01224       .addImm(MI->getOperand(2).getImm())
01225       .addReg(MI->getOperand(3).getReg()));
01226     return;
01227   }
01228   case ARM::LEApcrelJT:
01229   case ARM::tLEApcrelJT:
01230   case ARM::t2LEApcrelJT: {
01231     MCSymbol *JTIPICSymbol =
01232       GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
01233                                   MI->getOperand(2).getImm());
01234     EmitToStreamer(OutStreamer, MCInstBuilder(MI->getOpcode() ==
01235                                               ARM::t2LEApcrelJT ? ARM::t2ADR
01236                   : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
01237                      : ARM::ADR))
01238       .addReg(MI->getOperand(0).getReg())
01239       .addExpr(MCSymbolRefExpr::Create(JTIPICSymbol, OutContext))
01240       // Add predicate operands.
01241       .addImm(MI->getOperand(3).getImm())
01242       .addReg(MI->getOperand(4).getReg()));
01243     return;
01244   }
01245   // Darwin call instructions are just normal call instructions with different
01246   // clobber semantics (they clobber R9).
01247   case ARM::BX_CALL: {
01248     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
01249       .addReg(ARM::LR)
01250       .addReg(ARM::PC)
01251       // Add predicate operands.
01252       .addImm(ARMCC::AL)
01253       .addReg(0)
01254       // Add 's' bit operand (always reg0 for this)
01255       .addReg(0));
01256 
01257     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::BX)
01258       .addReg(MI->getOperand(0).getReg()));
01259     return;
01260   }
01261   case ARM::tBX_CALL: {
01262     if (Subtarget->hasV5TOps())
01263       llvm_unreachable("Expected BLX to be selected for v5t+");
01264 
01265     // On ARM v4t, when doing a call from thumb mode, we need to ensure
01266     // that the saved lr has its LSB set correctly (the arch doesn't
01267     // have blx).
01268     // So here we generate a bl to a small jump pad that does bx rN.
01269     // The jump pads are emitted after the function body.
01270 
01271     unsigned TReg = MI->getOperand(0).getReg();
01272     MCSymbol *TRegSym = nullptr;
01273     for (unsigned i = 0, e = ThumbIndirectPads.size(); i < e; i++) {
01274       if (ThumbIndirectPads[i].first == TReg) {
01275         TRegSym = ThumbIndirectPads[i].second;
01276         break;
01277       }
01278     }
01279 
01280     if (!TRegSym) {
01281       TRegSym = OutContext.CreateTempSymbol();
01282       ThumbIndirectPads.push_back(std::make_pair(TReg, TRegSym));
01283     }
01284 
01285     // Create a link-saving branch to the Reg Indirect Jump Pad.
01286     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tBL)
01287         // Predicate comes first here.
01288         .addImm(ARMCC::AL).addReg(0)
01289         .addExpr(MCSymbolRefExpr::Create(TRegSym, OutContext)));
01290     return;
01291   }
01292   case ARM::BMOVPCRX_CALL: {
01293     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
01294       .addReg(ARM::LR)
01295       .addReg(ARM::PC)
01296       // Add predicate operands.
01297       .addImm(ARMCC::AL)
01298       .addReg(0)
01299       // Add 's' bit operand (always reg0 for this)
01300       .addReg(0));
01301 
01302     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
01303       .addReg(ARM::PC)
01304       .addReg(MI->getOperand(0).getReg())
01305       // Add predicate operands.
01306       .addImm(ARMCC::AL)
01307       .addReg(0)
01308       // Add 's' bit operand (always reg0 for this)
01309       .addReg(0));
01310     return;
01311   }
01312   case ARM::BMOVPCB_CALL: {
01313     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVr)
01314       .addReg(ARM::LR)
01315       .addReg(ARM::PC)
01316       // Add predicate operands.
01317       .addImm(ARMCC::AL)
01318       .addReg(0)
01319       // Add 's' bit operand (always reg0 for this)
01320       .addReg(0));
01321 
01322     const MachineOperand &Op = MI->getOperand(0);
01323     const GlobalValue *GV = Op.getGlobal();
01324     const unsigned TF = Op.getTargetFlags();
01325     MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
01326     const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
01327     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::Bcc)
01328       .addExpr(GVSymExpr)
01329       // Add predicate operands.
01330       .addImm(ARMCC::AL)
01331       .addReg(0));
01332     return;
01333   }
01334   case ARM::MOVi16_ga_pcrel:
01335   case ARM::t2MOVi16_ga_pcrel: {
01336     MCInst TmpInst;
01337     TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
01338     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
01339 
01340     unsigned TF = MI->getOperand(1).getTargetFlags();
01341     const GlobalValue *GV = MI->getOperand(1).getGlobal();
01342     MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
01343     const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
01344 
01345     MCSymbol *LabelSym = getPICLabel(DL->getPrivateGlobalPrefix(),
01346                                      getFunctionNumber(),
01347                                      MI->getOperand(2).getImm(), OutContext);
01348     const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
01349     unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
01350     const MCExpr *PCRelExpr =
01351       ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
01352                                       MCBinaryExpr::CreateAdd(LabelSymExpr,
01353                                       MCConstantExpr::Create(PCAdj, OutContext),
01354                                       OutContext), OutContext), OutContext);
01355       TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
01356 
01357     // Add predicate operands.
01358     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
01359     TmpInst.addOperand(MCOperand::CreateReg(0));
01360     // Add 's' bit operand (always reg0 for this)
01361     TmpInst.addOperand(MCOperand::CreateReg(0));
01362     EmitToStreamer(OutStreamer, TmpInst);
01363     return;
01364   }
01365   case ARM::MOVTi16_ga_pcrel:
01366   case ARM::t2MOVTi16_ga_pcrel: {
01367     MCInst TmpInst;
01368     TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
01369                       ? ARM::MOVTi16 : ARM::t2MOVTi16);
01370     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
01371     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
01372 
01373     unsigned TF = MI->getOperand(2).getTargetFlags();
01374     const GlobalValue *GV = MI->getOperand(2).getGlobal();
01375     MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
01376     const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
01377 
01378     MCSymbol *LabelSym = getPICLabel(DL->getPrivateGlobalPrefix(),
01379                                      getFunctionNumber(),
01380                                      MI->getOperand(3).getImm(), OutContext);
01381     const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
01382     unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
01383     const MCExpr *PCRelExpr =
01384         ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
01385                                    MCBinaryExpr::CreateAdd(LabelSymExpr,
01386                                       MCConstantExpr::Create(PCAdj, OutContext),
01387                                           OutContext), OutContext), OutContext);
01388       TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
01389     // Add predicate operands.
01390     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
01391     TmpInst.addOperand(MCOperand::CreateReg(0));
01392     // Add 's' bit operand (always reg0 for this)
01393     TmpInst.addOperand(MCOperand::CreateReg(0));
01394     EmitToStreamer(OutStreamer, TmpInst);
01395     return;
01396   }
01397   case ARM::tPICADD: {
01398     // This is a pseudo op for a label + instruction sequence, which looks like:
01399     // LPC0:
01400     //     add r0, pc
01401     // This adds the address of LPC0 to r0.
01402 
01403     // Emit the label.
01404     OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
01405                           getFunctionNumber(), MI->getOperand(2).getImm(),
01406                           OutContext));
01407 
01408     // Form and emit the add.
01409     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tADDhirr)
01410       .addReg(MI->getOperand(0).getReg())
01411       .addReg(MI->getOperand(0).getReg())
01412       .addReg(ARM::PC)
01413       // Add predicate operands.
01414       .addImm(ARMCC::AL)
01415       .addReg(0));
01416     return;
01417   }
01418   case ARM::PICADD: {
01419     // This is a pseudo op for a label + instruction sequence, which looks like:
01420     // LPC0:
01421     //     add r0, pc, r0
01422     // This adds the address of LPC0 to r0.
01423 
01424     // Emit the label.
01425     OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
01426                           getFunctionNumber(), MI->getOperand(2).getImm(),
01427                           OutContext));
01428 
01429     // Form and emit the add.
01430     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDrr)
01431       .addReg(MI->getOperand(0).getReg())
01432       .addReg(ARM::PC)
01433       .addReg(MI->getOperand(1).getReg())
01434       // Add predicate operands.
01435       .addImm(MI->getOperand(3).getImm())
01436       .addReg(MI->getOperand(4).getReg())
01437       // Add 's' bit operand (always reg0 for this)
01438       .addReg(0));
01439     return;
01440   }
01441   case ARM::PICSTR:
01442   case ARM::PICSTRB:
01443   case ARM::PICSTRH:
01444   case ARM::PICLDR:
01445   case ARM::PICLDRB:
01446   case ARM::PICLDRH:
01447   case ARM::PICLDRSB:
01448   case ARM::PICLDRSH: {
01449     // This is a pseudo op for a label + instruction sequence, which looks like:
01450     // LPC0:
01451     //     OP r0, [pc, r0]
01452     // The LCP0 label is referenced by a constant pool entry in order to get
01453     // a PC-relative address at the ldr instruction.
01454 
01455     // Emit the label.
01456     OutStreamer.EmitLabel(getPICLabel(DL->getPrivateGlobalPrefix(),
01457                           getFunctionNumber(), MI->getOperand(2).getImm(),
01458                           OutContext));
01459 
01460     // Form and emit the load
01461     unsigned Opcode;
01462     switch (MI->getOpcode()) {
01463     default:
01464       llvm_unreachable("Unexpected opcode!");
01465     case ARM::PICSTR:   Opcode = ARM::STRrs; break;
01466     case ARM::PICSTRB:  Opcode = ARM::STRBrs; break;
01467     case ARM::PICSTRH:  Opcode = ARM::STRH; break;
01468     case ARM::PICLDR:   Opcode = ARM::LDRrs; break;
01469     case ARM::PICLDRB:  Opcode = ARM::LDRBrs; break;
01470     case ARM::PICLDRH:  Opcode = ARM::LDRH; break;
01471     case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
01472     case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
01473     }
01474     EmitToStreamer(OutStreamer, MCInstBuilder(Opcode)
01475       .addReg(MI->getOperand(0).getReg())
01476       .addReg(ARM::PC)
01477       .addReg(MI->getOperand(1).getReg())
01478       .addImm(0)
01479       // Add predicate operands.
01480       .addImm(MI->getOperand(3).getImm())
01481       .addReg(MI->getOperand(4).getReg()));
01482 
01483     return;
01484   }
01485   case ARM::CONSTPOOL_ENTRY: {
01486     /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
01487     /// in the function.  The first operand is the ID# for this instruction, the
01488     /// second is the index into the MachineConstantPool that this is, the third
01489     /// is the size in bytes of this constant pool entry.
01490     /// The required alignment is specified on the basic block holding this MI.
01491     unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
01492     unsigned CPIdx   = (unsigned)MI->getOperand(1).getIndex();
01493 
01494     // If this is the first entry of the pool, mark it.
01495     if (!InConstantPool) {
01496       OutStreamer.EmitDataRegion(MCDR_DataRegion);
01497       InConstantPool = true;
01498     }
01499 
01500     OutStreamer.EmitLabel(GetCPISymbol(LabelId));
01501 
01502     const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
01503     if (MCPE.isMachineConstantPoolEntry())
01504       EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
01505     else
01506       EmitGlobalConstant(MCPE.Val.ConstVal);
01507     return;
01508   }
01509   case ARM::t2BR_JT: {
01510     // Lower and emit the instruction itself, then the jump table following it.
01511     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
01512       .addReg(ARM::PC)
01513       .addReg(MI->getOperand(0).getReg())
01514       // Add predicate operands.
01515       .addImm(ARMCC::AL)
01516       .addReg(0));
01517 
01518     // Output the data for the jump table itself
01519     EmitJump2Table(MI);
01520     return;
01521   }
01522   case ARM::t2TBB_JT: {
01523     // Lower and emit the instruction itself, then the jump table following it.
01524     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::t2TBB)
01525       .addReg(ARM::PC)
01526       .addReg(MI->getOperand(0).getReg())
01527       // Add predicate operands.
01528       .addImm(ARMCC::AL)
01529       .addReg(0));
01530 
01531     // Output the data for the jump table itself
01532     EmitJump2Table(MI);
01533     // Make sure the next instruction is 2-byte aligned.
01534     EmitAlignment(1);
01535     return;
01536   }
01537   case ARM::t2TBH_JT: {
01538     // Lower and emit the instruction itself, then the jump table following it.
01539     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::t2TBH)
01540       .addReg(ARM::PC)
01541       .addReg(MI->getOperand(0).getReg())
01542       // Add predicate operands.
01543       .addImm(ARMCC::AL)
01544       .addReg(0));
01545 
01546     // Output the data for the jump table itself
01547     EmitJump2Table(MI);
01548     return;
01549   }
01550   case ARM::tBR_JTr:
01551   case ARM::BR_JTr: {
01552     // Lower and emit the instruction itself, then the jump table following it.
01553     // mov pc, target
01554     MCInst TmpInst;
01555     unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
01556       ARM::MOVr : ARM::tMOVr;
01557     TmpInst.setOpcode(Opc);
01558     TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
01559     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
01560     // Add predicate operands.
01561     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
01562     TmpInst.addOperand(MCOperand::CreateReg(0));
01563     // Add 's' bit operand (always reg0 for this)
01564     if (Opc == ARM::MOVr)
01565       TmpInst.addOperand(MCOperand::CreateReg(0));
01566     EmitToStreamer(OutStreamer, TmpInst);
01567 
01568     // Make sure the Thumb jump table is 4-byte aligned.
01569     if (Opc == ARM::tMOVr)
01570       EmitAlignment(2);
01571 
01572     // Output the data for the jump table itself
01573     EmitJumpTable(MI);
01574     return;
01575   }
01576   case ARM::BR_JTm: {
01577     // Lower and emit the instruction itself, then the jump table following it.
01578     // ldr pc, target
01579     MCInst TmpInst;
01580     if (MI->getOperand(1).getReg() == 0) {
01581       // literal offset
01582       TmpInst.setOpcode(ARM::LDRi12);
01583       TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
01584       TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
01585       TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
01586     } else {
01587       TmpInst.setOpcode(ARM::LDRrs);
01588       TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
01589       TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
01590       TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
01591       TmpInst.addOperand(MCOperand::CreateImm(0));
01592     }
01593     // Add predicate operands.
01594     TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
01595     TmpInst.addOperand(MCOperand::CreateReg(0));
01596     EmitToStreamer(OutStreamer, TmpInst);
01597 
01598     // Output the data for the jump table itself
01599     EmitJumpTable(MI);
01600     return;
01601   }
01602   case ARM::BR_JTadd: {
01603     // Lower and emit the instruction itself, then the jump table following it.
01604     // add pc, target, idx
01605     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDrr)
01606       .addReg(ARM::PC)
01607       .addReg(MI->getOperand(0).getReg())
01608       .addReg(MI->getOperand(1).getReg())
01609       // Add predicate operands.
01610       .addImm(ARMCC::AL)
01611       .addReg(0)
01612       // Add 's' bit operand (always reg0 for this)
01613       .addReg(0));
01614 
01615     // Output the data for the jump table itself
01616     EmitJumpTable(MI);
01617     return;
01618   }
01619   case ARM::SPACE:
01620     OutStreamer.EmitZeros(MI->getOperand(1).getImm());
01621     return;
01622   case ARM::TRAP: {
01623     // Non-Darwin binutils don't yet support the "trap" mnemonic.
01624     // FIXME: Remove this special case when they do.
01625     if (!Subtarget->isTargetMachO()) {
01626       //.long 0xe7ffdefe @ trap
01627       uint32_t Val = 0xe7ffdefeUL;
01628       OutStreamer.AddComment("trap");
01629       OutStreamer.EmitIntValue(Val, 4);
01630       return;
01631     }
01632     break;
01633   }
01634   case ARM::TRAPNaCl: {
01635     //.long 0xe7fedef0 @ trap
01636     uint32_t Val = 0xe7fedef0UL;
01637     OutStreamer.AddComment("trap");
01638     OutStreamer.EmitIntValue(Val, 4);
01639     return;
01640   }
01641   case ARM::tTRAP: {
01642     // Non-Darwin binutils don't yet support the "trap" mnemonic.
01643     // FIXME: Remove this special case when they do.
01644     if (!Subtarget->isTargetMachO()) {
01645       //.short 57086 @ trap
01646       uint16_t Val = 0xdefe;
01647       OutStreamer.AddComment("trap");
01648       OutStreamer.EmitIntValue(Val, 2);
01649       return;
01650     }
01651     break;
01652   }
01653   case ARM::t2Int_eh_sjlj_setjmp:
01654   case ARM::t2Int_eh_sjlj_setjmp_nofp:
01655   case ARM::tInt_eh_sjlj_setjmp: {
01656     // Two incoming args: GPR:$src, GPR:$val
01657     // mov $val, pc
01658     // adds $val, #7
01659     // str $val, [$src, #4]
01660     // movs r0, #0
01661     // b 1f
01662     // movs r0, #1
01663     // 1:
01664     unsigned SrcReg = MI->getOperand(0).getReg();
01665     unsigned ValReg = MI->getOperand(1).getReg();
01666     MCSymbol *Label = GetARMSJLJEHLabel();
01667     OutStreamer.AddComment("eh_setjmp begin");
01668     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
01669       .addReg(ValReg)
01670       .addReg(ARM::PC)
01671       // Predicate.
01672       .addImm(ARMCC::AL)
01673       .addReg(0));
01674 
01675     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tADDi3)
01676       .addReg(ValReg)
01677       // 's' bit operand
01678       .addReg(ARM::CPSR)
01679       .addReg(ValReg)
01680       .addImm(7)
01681       // Predicate.
01682       .addImm(ARMCC::AL)
01683       .addReg(0));
01684 
01685     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tSTRi)
01686       .addReg(ValReg)
01687       .addReg(SrcReg)
01688       // The offset immediate is #4. The operand value is scaled by 4 for the
01689       // tSTR instruction.
01690       .addImm(1)
01691       // Predicate.
01692       .addImm(ARMCC::AL)
01693       .addReg(0));
01694 
01695     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVi8)
01696       .addReg(ARM::R0)
01697       .addReg(ARM::CPSR)
01698       .addImm(0)
01699       // Predicate.
01700       .addImm(ARMCC::AL)
01701       .addReg(0));
01702 
01703     const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
01704     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tB)
01705       .addExpr(SymbolExpr)
01706       .addImm(ARMCC::AL)
01707       .addReg(0));
01708 
01709     OutStreamer.AddComment("eh_setjmp end");
01710     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVi8)
01711       .addReg(ARM::R0)
01712       .addReg(ARM::CPSR)
01713       .addImm(1)
01714       // Predicate.
01715       .addImm(ARMCC::AL)
01716       .addReg(0));
01717 
01718     OutStreamer.EmitLabel(Label);
01719     return;
01720   }
01721 
01722   case ARM::Int_eh_sjlj_setjmp_nofp:
01723   case ARM::Int_eh_sjlj_setjmp: {
01724     // Two incoming args: GPR:$src, GPR:$val
01725     // add $val, pc, #8
01726     // str $val, [$src, #+4]
01727     // mov r0, #0
01728     // add pc, pc, #0
01729     // mov r0, #1
01730     unsigned SrcReg = MI->getOperand(0).getReg();
01731     unsigned ValReg = MI->getOperand(1).getReg();
01732 
01733     OutStreamer.AddComment("eh_setjmp begin");
01734     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDri)
01735       .addReg(ValReg)
01736       .addReg(ARM::PC)
01737       .addImm(8)
01738       // Predicate.
01739       .addImm(ARMCC::AL)
01740       .addReg(0)
01741       // 's' bit operand (always reg0 for this).
01742       .addReg(0));
01743 
01744     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::STRi12)
01745       .addReg(ValReg)
01746       .addReg(SrcReg)
01747       .addImm(4)
01748       // Predicate.
01749       .addImm(ARMCC::AL)
01750       .addReg(0));
01751 
01752     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVi)
01753       .addReg(ARM::R0)
01754       .addImm(0)
01755       // Predicate.
01756       .addImm(ARMCC::AL)
01757       .addReg(0)
01758       // 's' bit operand (always reg0 for this).
01759       .addReg(0));
01760 
01761     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::ADDri)
01762       .addReg(ARM::PC)
01763       .addReg(ARM::PC)
01764       .addImm(0)
01765       // Predicate.
01766       .addImm(ARMCC::AL)
01767       .addReg(0)
01768       // 's' bit operand (always reg0 for this).
01769       .addReg(0));
01770 
01771     OutStreamer.AddComment("eh_setjmp end");
01772     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::MOVi)
01773       .addReg(ARM::R0)
01774       .addImm(1)
01775       // Predicate.
01776       .addImm(ARMCC::AL)
01777       .addReg(0)
01778       // 's' bit operand (always reg0 for this).
01779       .addReg(0));
01780     return;
01781   }
01782   case ARM::Int_eh_sjlj_longjmp: {
01783     // ldr sp, [$src, #8]
01784     // ldr $scratch, [$src, #4]
01785     // ldr r7, [$src]
01786     // bx $scratch
01787     unsigned SrcReg = MI->getOperand(0).getReg();
01788     unsigned ScratchReg = MI->getOperand(1).getReg();
01789     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::LDRi12)
01790       .addReg(ARM::SP)
01791       .addReg(SrcReg)
01792       .addImm(8)
01793       // Predicate.
01794       .addImm(ARMCC::AL)
01795       .addReg(0));
01796 
01797     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::LDRi12)
01798       .addReg(ScratchReg)
01799       .addReg(SrcReg)
01800       .addImm(4)
01801       // Predicate.
01802       .addImm(ARMCC::AL)
01803       .addReg(0));
01804 
01805     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::LDRi12)
01806       .addReg(ARM::R7)
01807       .addReg(SrcReg)
01808       .addImm(0)
01809       // Predicate.
01810       .addImm(ARMCC::AL)
01811       .addReg(0));
01812 
01813     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::BX)
01814       .addReg(ScratchReg)
01815       // Predicate.
01816       .addImm(ARMCC::AL)
01817       .addReg(0));
01818     return;
01819   }
01820   case ARM::tInt_eh_sjlj_longjmp: {
01821     // ldr $scratch, [$src, #8]
01822     // mov sp, $scratch
01823     // ldr $scratch, [$src, #4]
01824     // ldr r7, [$src]
01825     // bx $scratch
01826     unsigned SrcReg = MI->getOperand(0).getReg();
01827     unsigned ScratchReg = MI->getOperand(1).getReg();
01828     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tLDRi)
01829       .addReg(ScratchReg)
01830       .addReg(SrcReg)
01831       // The offset immediate is #8. The operand value is scaled by 4 for the
01832       // tLDR instruction.
01833       .addImm(2)
01834       // Predicate.
01835       .addImm(ARMCC::AL)
01836       .addReg(0));
01837 
01838     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tMOVr)
01839       .addReg(ARM::SP)
01840       .addReg(ScratchReg)
01841       // Predicate.
01842       .addImm(ARMCC::AL)
01843       .addReg(0));
01844 
01845     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tLDRi)
01846       .addReg(ScratchReg)
01847       .addReg(SrcReg)
01848       .addImm(1)
01849       // Predicate.
01850       .addImm(ARMCC::AL)
01851       .addReg(0));
01852 
01853     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tLDRi)
01854       .addReg(ARM::R7)
01855       .addReg(SrcReg)
01856       .addImm(0)
01857       // Predicate.
01858       .addImm(ARMCC::AL)
01859       .addReg(0));
01860 
01861     EmitToStreamer(OutStreamer, MCInstBuilder(ARM::tBX)
01862       .addReg(ScratchReg)
01863       // Predicate.
01864       .addImm(ARMCC::AL)
01865       .addReg(0));
01866     return;
01867   }
01868   }
01869 
01870   MCInst TmpInst;
01871   LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
01872 
01873   EmitToStreamer(OutStreamer, TmpInst);
01874 }
01875 
01876 //===----------------------------------------------------------------------===//
01877 // Target Registry Stuff
01878 //===----------------------------------------------------------------------===//
01879 
01880 // Force static initialization.
01881 extern "C" void LLVMInitializeARMAsmPrinter() {
01882   RegisterAsmPrinter<ARMAsmPrinter> X(TheARMLETarget);
01883   RegisterAsmPrinter<ARMAsmPrinter> Y(TheARMBETarget);
01884   RegisterAsmPrinter<ARMAsmPrinter> A(TheThumbLETarget);
01885   RegisterAsmPrinter<ARMAsmPrinter> B(TheThumbBETarget);
01886 }