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ARMBaseInfo.h
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00001 //===-- ARMBaseInfo.h - Top level definitions for ARM -------- --*- C++ -*-===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file contains small standalone helper functions and enum definitions for
00011 // the ARM target useful for the compiler back-end and the MC libraries.
00012 // As such, it deliberately does not include references to LLVM core
00013 // code gen types, passes, etc..
00014 //
00015 //===----------------------------------------------------------------------===//
00016 
00017 #ifndef ARMBASEINFO_H
00018 #define ARMBASEINFO_H
00019 
00020 #include "ARMMCTargetDesc.h"
00021 #include "llvm/Support/ErrorHandling.h"
00022 
00023 namespace llvm {
00024 
00025 // Enums corresponding to ARM condition codes
00026 namespace ARMCC {
00027   // The CondCodes constants map directly to the 4-bit encoding of the
00028   // condition field for predicated instructions.
00029   enum CondCodes { // Meaning (integer)          Meaning (floating-point)
00030     EQ,            // Equal                      Equal
00031     NE,            // Not equal                  Not equal, or unordered
00032     HS,            // Carry set                  >, ==, or unordered
00033     LO,            // Carry clear                Less than
00034     MI,            // Minus, negative            Less than
00035     PL,            // Plus, positive or zero     >, ==, or unordered
00036     VS,            // Overflow                   Unordered
00037     VC,            // No overflow                Not unordered
00038     HI,            // Unsigned higher            Greater than, or unordered
00039     LS,            // Unsigned lower or same     Less than or equal
00040     GE,            // Greater than or equal      Greater than or equal
00041     LT,            // Less than                  Less than, or unordered
00042     GT,            // Greater than               Greater than
00043     LE,            // Less than or equal         <, ==, or unordered
00044     AL             // Always (unconditional)     Always (unconditional)
00045   };
00046 
00047   inline static CondCodes getOppositeCondition(CondCodes CC) {
00048     switch (CC) {
00049     default: llvm_unreachable("Unknown condition code");
00050     case EQ: return NE;
00051     case NE: return EQ;
00052     case HS: return LO;
00053     case LO: return HS;
00054     case MI: return PL;
00055     case PL: return MI;
00056     case VS: return VC;
00057     case VC: return VS;
00058     case HI: return LS;
00059     case LS: return HI;
00060     case GE: return LT;
00061     case LT: return GE;
00062     case GT: return LE;
00063     case LE: return GT;
00064     }
00065   }
00066 } // namespace ARMCC
00067 
00068 inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) {
00069   switch (CC) {
00070   case ARMCC::EQ:  return "eq";
00071   case ARMCC::NE:  return "ne";
00072   case ARMCC::HS:  return "hs";
00073   case ARMCC::LO:  return "lo";
00074   case ARMCC::MI:  return "mi";
00075   case ARMCC::PL:  return "pl";
00076   case ARMCC::VS:  return "vs";
00077   case ARMCC::VC:  return "vc";
00078   case ARMCC::HI:  return "hi";
00079   case ARMCC::LS:  return "ls";
00080   case ARMCC::GE:  return "ge";
00081   case ARMCC::LT:  return "lt";
00082   case ARMCC::GT:  return "gt";
00083   case ARMCC::LE:  return "le";
00084   case ARMCC::AL:  return "al";
00085   }
00086   llvm_unreachable("Unknown condition code");
00087 }
00088 
00089 namespace ARM_PROC {
00090   enum IMod {
00091     IE = 2,
00092     ID = 3
00093   };
00094 
00095   enum IFlags {
00096     F = 1,
00097     I = 2,
00098     A = 4
00099   };
00100 
00101   inline static const char *IFlagsToString(unsigned val) {
00102     switch (val) {
00103     default: llvm_unreachable("Unknown iflags operand");
00104     case F: return "f";
00105     case I: return "i";
00106     case A: return "a";
00107     }
00108   }
00109 
00110   inline static const char *IModToString(unsigned val) {
00111     switch (val) {
00112     default: llvm_unreachable("Unknown imod operand");
00113     case IE: return "ie";
00114     case ID: return "id";
00115     }
00116   }
00117 }
00118 
00119 namespace ARM_MB {
00120   // The Memory Barrier Option constants map directly to the 4-bit encoding of
00121   // the option field for memory barrier operations.
00122   enum MemBOpt {
00123     RESERVED_0 = 0,
00124     OSHLD = 1,
00125     OSHST = 2,
00126     OSH   = 3,
00127     RESERVED_4 = 4,
00128     NSHLD = 5,
00129     NSHST = 6,
00130     NSH   = 7,
00131     RESERVED_8 = 8,
00132     ISHLD = 9,
00133     ISHST = 10,
00134     ISH   = 11,
00135     RESERVED_12 = 12,
00136     LD = 13,
00137     ST    = 14,
00138     SY    = 15
00139   };
00140 
00141   inline static const char *MemBOptToString(unsigned val, bool HasV8) {
00142     switch (val) {
00143     default: llvm_unreachable("Unknown memory operation");
00144     case SY:    return "sy";
00145     case ST:    return "st";
00146     case LD: return HasV8 ? "ld" : "#0xd";
00147     case RESERVED_12: return "#0xc";
00148     case ISH:   return "ish";
00149     case ISHST: return "ishst";
00150     case ISHLD: return HasV8 ?  "ishld" : "#0x9";
00151     case RESERVED_8: return "#0x8";
00152     case NSH:   return "nsh";
00153     case NSHST: return "nshst";
00154     case NSHLD: return HasV8 ? "nshld" : "#0x5";
00155     case RESERVED_4: return "#0x4";
00156     case OSH:   return "osh";
00157     case OSHST: return "oshst";
00158     case OSHLD: return HasV8 ? "oshld" : "#0x1";
00159     case RESERVED_0: return "#0x0";
00160     }
00161   }
00162 } // namespace ARM_MB
00163 
00164 namespace ARM_ISB {
00165   enum InstSyncBOpt {
00166     RESERVED_0 = 0,
00167     RESERVED_1 = 1,
00168     RESERVED_2 = 2,
00169     RESERVED_3 = 3,
00170     RESERVED_4 = 4,
00171     RESERVED_5 = 5,
00172     RESERVED_6 = 6,
00173     RESERVED_7 = 7,
00174     RESERVED_8 = 8,
00175     RESERVED_9 = 9,
00176     RESERVED_10 = 10,
00177     RESERVED_11 = 11,
00178     RESERVED_12 = 12,
00179     RESERVED_13 = 13,
00180     RESERVED_14 = 14,
00181     SY = 15
00182   };
00183 
00184   inline static const char *InstSyncBOptToString(unsigned val) {
00185     switch (val) {
00186     default:
00187       llvm_unreachable("Unknown memory operation");
00188       case RESERVED_0:  return "#0x0";
00189       case RESERVED_1:  return "#0x1";
00190       case RESERVED_2:  return "#0x2";
00191       case RESERVED_3:  return "#0x3";
00192       case RESERVED_4:  return "#0x4";
00193       case RESERVED_5:  return "#0x5";
00194       case RESERVED_6:  return "#0x6";
00195       case RESERVED_7:  return "#0x7";
00196       case RESERVED_8:  return "#0x8";
00197       case RESERVED_9:  return "#0x9";
00198       case RESERVED_10: return "#0xa";
00199       case RESERVED_11: return "#0xb";
00200       case RESERVED_12: return "#0xc";
00201       case RESERVED_13: return "#0xd";
00202       case RESERVED_14: return "#0xe";
00203       case SY:          return "sy";
00204     }
00205   }
00206 } // namespace ARM_ISB
00207 
00208 /// isARMLowRegister - Returns true if the register is a low register (r0-r7).
00209 ///
00210 static inline bool isARMLowRegister(unsigned Reg) {
00211   using namespace ARM;
00212   switch (Reg) {
00213   case R0:  case R1:  case R2:  case R3:
00214   case R4:  case R5:  case R6:  case R7:
00215     return true;
00216   default:
00217     return false;
00218   }
00219 }
00220 
00221 /// ARMII - This namespace holds all of the target specific flags that
00222 /// instruction info tracks.
00223 ///
00224 namespace ARMII {
00225 
00226   /// ARM Index Modes
00227   enum IndexMode {
00228     IndexModeNone  = 0,
00229     IndexModePre   = 1,
00230     IndexModePost  = 2,
00231     IndexModeUpd   = 3
00232   };
00233 
00234   /// ARM Addressing Modes
00235   enum AddrMode {
00236     AddrModeNone    = 0,
00237     AddrMode1       = 1,
00238     AddrMode2       = 2,
00239     AddrMode3       = 3,
00240     AddrMode4       = 4,
00241     AddrMode5       = 5,
00242     AddrMode6       = 6,
00243     AddrModeT1_1    = 7,
00244     AddrModeT1_2    = 8,
00245     AddrModeT1_4    = 9,
00246     AddrModeT1_s    = 10, // i8 * 4 for pc and sp relative data
00247     AddrModeT2_i12  = 11,
00248     AddrModeT2_i8   = 12,
00249     AddrModeT2_so   = 13,
00250     AddrModeT2_pc   = 14, // +/- i12 for pc relative data
00251     AddrModeT2_i8s4 = 15, // i8 * 4
00252     AddrMode_i12    = 16
00253   };
00254 
00255   inline static const char *AddrModeToString(AddrMode addrmode) {
00256     switch (addrmode) {
00257     case AddrModeNone:    return "AddrModeNone";
00258     case AddrMode1:       return "AddrMode1";
00259     case AddrMode2:       return "AddrMode2";
00260     case AddrMode3:       return "AddrMode3";
00261     case AddrMode4:       return "AddrMode4";
00262     case AddrMode5:       return "AddrMode5";
00263     case AddrMode6:       return "AddrMode6";
00264     case AddrModeT1_1:    return "AddrModeT1_1";
00265     case AddrModeT1_2:    return "AddrModeT1_2";
00266     case AddrModeT1_4:    return "AddrModeT1_4";
00267     case AddrModeT1_s:    return "AddrModeT1_s";
00268     case AddrModeT2_i12:  return "AddrModeT2_i12";
00269     case AddrModeT2_i8:   return "AddrModeT2_i8";
00270     case AddrModeT2_so:   return "AddrModeT2_so";
00271     case AddrModeT2_pc:   return "AddrModeT2_pc";
00272     case AddrModeT2_i8s4: return "AddrModeT2_i8s4";
00273     case AddrMode_i12:    return "AddrMode_i12";
00274     }
00275   }
00276 
00277   /// Target Operand Flag enum.
00278   enum TOF {
00279     //===------------------------------------------------------------------===//
00280     // ARM Specific MachineOperand flags.
00281 
00282     MO_NO_FLAG = 0,
00283 
00284     /// MO_LO16 - On a symbol operand, this represents a relocation containing
00285     /// lower 16 bit of the address. Used only via movw instruction.
00286     MO_LO16 = 0x1,
00287 
00288     /// MO_HI16 - On a symbol operand, this represents a relocation containing
00289     /// higher 16 bit of the address. Used only via movt instruction.
00290     MO_HI16 = 0x2,
00291 
00292     /// MO_PLT - On a symbol operand, this represents an ELF PLT reference on a
00293     /// call operand.
00294     MO_PLT = 0x3,
00295 
00296     /// MO_OPTION_MASK - Most flags are mutually exclusive; this mask selects
00297     /// just that part of the flag set.
00298     MO_OPTION_MASK = 0x7f,
00299 
00300     /// MO_NONLAZY - This is an independent flag, on a symbol operand "FOO" it
00301     /// represents a symbol which, if indirect, will get special Darwin mangling
00302     /// as a non-lazy-ptr indirect symbol (i.e. "L_FOO$non_lazy_ptr"). Can be
00303     /// combined with MO_LO16, MO_HI16 or MO_NO_FLAG (in a constant-pool, for
00304     /// example).
00305     MO_NONLAZY = 0x80,
00306 
00307     // It's undefined behaviour if an enum overflows the range between its
00308     // smallest and largest values, but since these are |ed together, it can
00309     // happen. Put a sentinel in (values of this enum are stored as "unsigned
00310     // char").
00311     MO_UNUSED_MAXIMUM = 0xff
00312   };
00313 
00314   enum {
00315     //===------------------------------------------------------------------===//
00316     // Instruction Flags.
00317 
00318     //===------------------------------------------------------------------===//
00319     // This four-bit field describes the addressing mode used.
00320     AddrModeMask  = 0x1f, // The AddrMode enums are declared in ARMBaseInfo.h
00321 
00322     // IndexMode - Unindex, pre-indexed, or post-indexed are valid for load
00323     // and store ops only.  Generic "updating" flag is used for ld/st multiple.
00324     // The index mode enums are declared in ARMBaseInfo.h
00325     IndexModeShift = 5,
00326     IndexModeMask  = 3 << IndexModeShift,
00327 
00328     //===------------------------------------------------------------------===//
00329     // Instruction encoding formats.
00330     //
00331     FormShift     = 7,
00332     FormMask      = 0x3f << FormShift,
00333 
00334     // Pseudo instructions
00335     Pseudo        = 0  << FormShift,
00336 
00337     // Multiply instructions
00338     MulFrm        = 1  << FormShift,
00339 
00340     // Branch instructions
00341     BrFrm         = 2  << FormShift,
00342     BrMiscFrm     = 3  << FormShift,
00343 
00344     // Data Processing instructions
00345     DPFrm         = 4  << FormShift,
00346     DPSoRegFrm    = 5  << FormShift,
00347 
00348     // Load and Store
00349     LdFrm         = 6  << FormShift,
00350     StFrm         = 7  << FormShift,
00351     LdMiscFrm     = 8  << FormShift,
00352     StMiscFrm     = 9  << FormShift,
00353     LdStMulFrm    = 10 << FormShift,
00354 
00355     LdStExFrm     = 11 << FormShift,
00356 
00357     // Miscellaneous arithmetic instructions
00358     ArithMiscFrm  = 12 << FormShift,
00359     SatFrm        = 13 << FormShift,
00360 
00361     // Extend instructions
00362     ExtFrm        = 14 << FormShift,
00363 
00364     // VFP formats
00365     VFPUnaryFrm   = 15 << FormShift,
00366     VFPBinaryFrm  = 16 << FormShift,
00367     VFPConv1Frm   = 17 << FormShift,
00368     VFPConv2Frm   = 18 << FormShift,
00369     VFPConv3Frm   = 19 << FormShift,
00370     VFPConv4Frm   = 20 << FormShift,
00371     VFPConv5Frm   = 21 << FormShift,
00372     VFPLdStFrm    = 22 << FormShift,
00373     VFPLdStMulFrm = 23 << FormShift,
00374     VFPMiscFrm    = 24 << FormShift,
00375 
00376     // Thumb format
00377     ThumbFrm      = 25 << FormShift,
00378 
00379     // Miscelleaneous format
00380     MiscFrm       = 26 << FormShift,
00381 
00382     // NEON formats
00383     NGetLnFrm     = 27 << FormShift,
00384     NSetLnFrm     = 28 << FormShift,
00385     NDupFrm       = 29 << FormShift,
00386     NLdStFrm      = 30 << FormShift,
00387     N1RegModImmFrm= 31 << FormShift,
00388     N2RegFrm      = 32 << FormShift,
00389     NVCVTFrm      = 33 << FormShift,
00390     NVDupLnFrm    = 34 << FormShift,
00391     N2RegVShLFrm  = 35 << FormShift,
00392     N2RegVShRFrm  = 36 << FormShift,
00393     N3RegFrm      = 37 << FormShift,
00394     N3RegVShFrm   = 38 << FormShift,
00395     NVExtFrm      = 39 << FormShift,
00396     NVMulSLFrm    = 40 << FormShift,
00397     NVTBLFrm      = 41 << FormShift,
00398 
00399     //===------------------------------------------------------------------===//
00400     // Misc flags.
00401 
00402     // UnaryDP - Indicates this is a unary data processing instruction, i.e.
00403     // it doesn't have a Rn operand.
00404     UnaryDP       = 1 << 13,
00405 
00406     // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
00407     // a 16-bit Thumb instruction if certain conditions are met.
00408     Xform16Bit    = 1 << 14,
00409 
00410     // ThumbArithFlagSetting - The instruction is a 16-bit flag setting Thumb
00411     // instruction. Used by the parser to determine whether to require the 'S'
00412     // suffix on the mnemonic (when not in an IT block) or preclude it (when
00413     // in an IT block).
00414     ThumbArithFlagSetting = 1 << 18,
00415 
00416     //===------------------------------------------------------------------===//
00417     // Code domain.
00418     DomainShift   = 15,
00419     DomainMask    = 7 << DomainShift,
00420     DomainGeneral = 0 << DomainShift,
00421     DomainVFP     = 1 << DomainShift,
00422     DomainNEON    = 2 << DomainShift,
00423     DomainNEONA8  = 4 << DomainShift,
00424 
00425     //===------------------------------------------------------------------===//
00426     // Field shifts - such shifts are used to set field while generating
00427     // machine instructions.
00428     //
00429     // FIXME: This list will need adjusting/fixing as the MC code emitter
00430     // takes shape and the ARMCodeEmitter.cpp bits go away.
00431     ShiftTypeShift = 4,
00432 
00433     M_BitShift     = 5,
00434     ShiftImmShift  = 5,
00435     ShiftShift     = 7,
00436     N_BitShift     = 7,
00437     ImmHiShift     = 8,
00438     SoRotImmShift  = 8,
00439     RegRsShift     = 8,
00440     ExtRotImmShift = 10,
00441     RegRdLoShift   = 12,
00442     RegRdShift     = 12,
00443     RegRdHiShift   = 16,
00444     RegRnShift     = 16,
00445     S_BitShift     = 20,
00446     W_BitShift     = 21,
00447     AM3_I_BitShift = 22,
00448     D_BitShift     = 22,
00449     U_BitShift     = 23,
00450     P_BitShift     = 24,
00451     I_BitShift     = 25,
00452     CondShift      = 28
00453   };
00454 
00455 } // end namespace ARMII
00456 
00457 } // end namespace llvm;
00458 
00459 #endif