LLVM 19.0.0git
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#include "ARMISelLowering.h"
#include "ARMBaseInstrInfo.h"
#include "ARMBaseRegisterInfo.h"
#include "ARMCallingConv.h"
#include "ARMConstantPoolValue.h"
#include "ARMMachineFunctionInfo.h"
#include "ARMPerfectShuffle.h"
#include "ARMRegisterInfo.h"
#include "ARMSelectionDAGInfo.h"
#include "ARMSubtarget.h"
#include "ARMTargetTransformInfo.h"
#include "MCTargetDesc/ARMAddressingModes.h"
#include "MCTargetDesc/ARMBaseInfo.h"
#include "Utils/ARMBaseInfo.h"
#include "llvm/ADT/APFloat.h"
#include "llvm/ADT/APInt.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/StringSwitch.h"
#include "llvm/ADT/Twine.h"
#include "llvm/Analysis/VectorUtils.h"
#include "llvm/CodeGen/CallingConvLower.h"
#include "llvm/CodeGen/ComplexDeinterleavingPass.h"
#include "llvm/CodeGen/ISDOpcodes.h"
#include "llvm/CodeGen/IntrinsicLowering.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineJumpTableInfo.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RuntimeLibcalls.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGAddressAnalysis.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/CodeGen/TargetOpcodes.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/CodeGenTypes/MachineValueType.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/IR/Constant.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/GlobalAlias.h"
#include "llvm/IR/GlobalValue.h"
#include "llvm/IR/GlobalVariable.h"
#include "llvm/IR/IRBuilder.h"
#include "llvm/IR/InlineAsm.h"
#include "llvm/IR/Instruction.h"
#include "llvm/IR/Instructions.h"
#include "llvm/IR/IntrinsicInst.h"
#include "llvm/IR/Intrinsics.h"
#include "llvm/IR/IntrinsicsARM.h"
#include "llvm/IR/Module.h"
#include "llvm/IR/PatternMatch.h"
#include "llvm/IR/Type.h"
#include "llvm/IR/User.h"
#include "llvm/IR/Value.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCInstrItineraries.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSchedule.h"
#include "llvm/Support/AtomicOrdering.h"
#include "llvm/Support/BranchProbability.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/KnownBits.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/TargetParser/Triple.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
#include <cstdlib>
#include <iterator>
#include <limits>
#include <optional>
#include <tuple>
#include <utility>
#include <vector>
Go to the source code of this file.
Classes | |
struct | BaseUpdateTarget |
Load/store instruction that can be merged with a base address update. More... | |
struct | BaseUpdateUser |
Macros | |
#define | DEBUG_TYPE "arm-isel" |
#define | MAKE_CASE(V) |
Typedefs | |
using | RCPair = std::pair< unsigned, const TargetRegisterClass * > |
Enumerations | |
enum | ShuffleOpCodes { OP_COPY = 0 , OP_VREV , OP_VDUP0 , OP_VDUP1 , OP_VDUP2 , OP_VDUP3 , OP_VEXT1 , OP_VEXT2 , OP_VEXT3 , OP_VUZPL , OP_VUZPR , OP_VZIPL , OP_VZIPR , OP_VTRNL , OP_VTRNR } |
enum | HABaseType { HA_UNKNOWN = 0 , HA_FLOAT , HA_DOUBLE , HA_VECT64 , HA_VECT128 } |
Variables | |
static cl::opt< bool > | ARMInterworking ("arm-interworking", cl::Hidden, cl::desc("Enable / disable ARM interworking (for debugging only)"), cl::init(true)) |
static cl::opt< bool > | EnableConstpoolPromotion ("arm-promote-constant", cl::Hidden, cl::desc("Enable / disable promotion of unnamed_addr constants into " "constant pools"), cl::init(false)) |
static cl::opt< unsigned > | ConstpoolPromotionMaxSize ("arm-promote-constant-max-size", cl::Hidden, cl::desc("Maximum size of constant to promote into a constant pool"), cl::init(64)) |
static cl::opt< unsigned > | ConstpoolPromotionMaxTotal ("arm-promote-constant-max-total", cl::Hidden, cl::desc("Maximum size of ALL constants to promote into a constant pool"), cl::init(128)) |
cl::opt< unsigned > | MVEMaxSupportedInterleaveFactor ("mve-max-interleave-factor", cl::Hidden, cl::desc("Maximum interleave factor for MVE VLDn to generate."), cl::init(2)) |
static const MCPhysReg | GPRArgRegs [] |
#define DEBUG_TYPE "arm-isel" |
Definition at line 122 of file ARMISelLowering.cpp.
#define MAKE_CASE | ( | V | ) |
using RCPair = std::pair<unsigned, const TargetRegisterClass *> |
Definition at line 20407 of file ARMISelLowering.cpp.
enum HABaseType |
Enumerator | |
---|---|
HA_UNKNOWN | |
HA_FLOAT | |
HA_DOUBLE | |
HA_VECT64 | |
HA_VECT128 |
Definition at line 21929 of file ARMISelLowering.cpp.
enum ShuffleOpCodes |
Enumerator | |
---|---|
OP_COPY | |
OP_VREV | |
OP_VDUP0 | |
OP_VDUP1 | |
OP_VDUP2 | |
OP_VDUP3 | |
OP_VEXT1 | |
OP_VEXT2 | |
OP_VEXT3 | |
OP_VUZPL | |
OP_VUZPR | |
OP_VZIPL | |
OP_VZIPR | |
OP_VTRNL | |
OP_VTRNR |
Definition at line 8364 of file ARMISelLowering.cpp.
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Definition at line 12700 of file ARMISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, llvm::EVT::bitsGT(), llvm::ISD::BUILD_VECTOR, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getDataLayout(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::TargetLoweringBase::getPointerTy(), llvm::EVT::getSimpleVT(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::ConstantSDNode::getZExtValue(), llvm::ISD::INTRINSIC_WO_CHAIN, llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::EVT::isInteger(), llvm_unreachable, N, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::MVT::SimpleTy, and llvm::ISD::TRUNCATE.
Referenced by PerformADDCombineWithOperands().
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Definition at line 12881 of file ARMISelLowering.cpp.
References llvm::ARMISD::ADDC, AddCombineTo64BitSMLAL16(), llvm::ARMISD::ADDE, assert(), llvm::ISD::Constant, llvm::TargetLowering::DAGCombinerInfo::DAG, findMUL_LOHI(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getNumOperands(), llvm::SDNode::getNumValues(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVTList(), llvm::ConstantSDNode::getZExtValue(), llvm::SDNode::hasAnyUseOfValue(), llvm::SDNode::isPredecessorOf(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ARMISD::SMLAL, llvm::ARMISD::SMMLAR, llvm::ARMISD::SMMLSR, llvm::ISD::SMUL_LOHI, llvm::ARMISD::SUBC, llvm::ARMISD::SUBE, llvm::ARMISD::UMLAL, llvm::ISD::UMUL_LOHI, and llvm::ARMSubtarget::useMulOps().
Referenced by AddCombineTo64bitUMAAL(), and PerformAddeSubeCombine().
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Definition at line 12804 of file ARMISelLowering.cpp.
References llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getVTList(), llvm::ARMSubtarget::hasBaseDSP(), llvm::Hi, isS16(), isSRA16(), llvm::Lo, llvm::Mul, llvm::ISD::MUL, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ARMISD::SMLALBB, llvm::ARMISD::SMLALBT, llvm::ARMISD::SMLALTB, llvm::ARMISD::SMLALTT, and llvm::ISD::SRA.
Referenced by AddCombineTo64bitMLAL().
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Definition at line 13047 of file ARMISelLowering.cpp.
References llvm::ARMISD::ADDC, AddCombineTo64bitMLAL(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getVTList(), llvm::isNullConstant(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ARMISD::UMAAL, and llvm::ARMISD::UMLAL.
Referenced by PerformADDECombine().
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Definition at line 12619 of file ARMISelLowering.cpp.
References llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getDataLayout(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::TargetLoweringBase::getPointerTy(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::ISD::INTRINSIC_WO_CHAIN, IsVUZPShuffleNode(), N, and llvm::SmallVectorTemplateBase< T, bool >::push_back().
Referenced by PerformADDCombineWithOperands().
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Definition at line 12647 of file ARMISelLowering.cpp.
References Concat, llvm::ISD::CONCAT_VECTORS, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::TargetLoweringBase::getPointerTy(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::ISD::INTRINSIC_WO_CHAIN, llvm::EVT::is128BitVector(), llvm::EVT::is64BitVector(), IsVUZPShuffleNode(), N, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::ISD::SIGN_EXTEND, and llvm::ISD::ZERO_EXTEND.
Referenced by PerformADDCombineWithOperands().
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AddRequiredExtensionForVMULL - Add a sign/zero extension to extend the total value size to 64 bits.
We need a 64-bit D register as an operand to VMULL. We insert the required extension here to get the vector to fill a D register.
Definition at line 9485 of file ARMISelLowering.cpp.
References assert(), getExtensionTo64Bits(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::EVT::is128BitVector(), and N.
Referenced by SkipExtensionForVMULL().
Return true if all users of V are within function F, looking through ConstantExprs.
Definition at line 3783 of file ARMISelLowering.cpp.
References llvm::append_range(), llvm::SmallVectorBase< Size_T >::empty(), F, I, and llvm::SmallVectorImpl< T >::pop_back_val().
Referenced by promoteToConstantPool().
Check if Ext1 and Ext2 are extends of the same type, doubling the bitwidth of the vector elements.
Definition at line 19240 of file ARMISelLowering.cpp.
References llvm::PatternMatch::m_Value(), llvm::PatternMatch::m_ZExtOrSExt(), and llvm::PatternMatch::match().
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Attaches vregs to MEMCPY that it will use as scratch registers when it is expanded into LDM/STM.
This is done as a post-isel lowering instead of as a custom inserter because we need the use list from the SDNode.
Definition at line 12351 of file ARMISelLowering.cpp.
References llvm::MachineInstrBuilder::addReg(), llvm::RegState::Dead, llvm::RegState::Define, DL, llvm::MachineFunction::getRegInfo(), I, llvm::ARMSubtarget::isThumb1Only(), MI, and MRI.
Referenced by llvm::ARMTargetLowering::AdjustInstrPostInstrSelection().
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Definition at line 5594 of file ARMISelLowering.cpp.
References llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getLoad(), isFloatingPointZero(), and llvm_unreachable.
Definition at line 14854 of file ARMISelLowering.cpp.
Referenced by FindBFIToCombineWith().
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canChangeToInt - Given the fp compare operand, return true if it is suitable to morph to an integer compare sequence.
Definition at line 5573 of file ARMISelLowering.cpp.
References isFloatingPointZero(), llvm::ISD::isNormalLoad(), and N.
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Definition at line 2340 of file ARMISelLowering.cpp.
References CC, llvm::CallingConv::Fast, llvm::CallingConv::SwiftTail, and llvm::CallingConv::Tail.
Definition at line 14655 of file ARMISelLowering.cpp.
References CC, llvm::ARMCC::getOppositeCondition(), getVCMPCondCode(), isValidMVECond(), and N.
Referenced by PerformORCombine_i1(), and PerformXORCombine().
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Definition at line 11792 of file ARMISelLowering.cpp.
References llvm::MachineInstr::definesRegister(), llvm::MachineBasicBlock::end(), llvm::MachineInstr::readsRegister(), llvm::MachineBasicBlock::successors(), and TRI.
Referenced by llvm::ARMTargetLowering::EmitInstrWithCustomInserter().
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Definition at line 5179 of file ARMISelLowering.cpp.
References CC, llvm::ARMCC::EQ, llvm::ARMCC::GE, llvm::ARMCC::GT, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETO, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SETUNE, and llvm::ARMCC::VS.
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Definition at line 14289 of file ARMISelLowering.cpp.
References llvm::countl_zero(), llvm::countr_zero(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::ConstantSDNode::getZExtValue(), llvm::SDNode::hasOneUse(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::TargetLowering::DAGCombinerInfo::isCalledByLegalizer(), llvm::isMask_32(), llvm::isShiftedMask_32(), N, llvm::ISD::SHL, and llvm::ISD::SRL.
Referenced by PerformANDCombine().
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CombineBaseUpdate - Target-specific DAG combine function for VLDDUP, NEON load/store intrinsics, and generic vector load/stores, to merge base address updates.
For generic load/stores, the memory type is assumed to be a vector. The caller is assumed to have checked legality.
Definition at line 16137 of file ARMISelLowering.cpp.
References llvm::ISD::ADD, Addr, llvm::sampleprof::Base, llvm::SmallVectorTemplateCommon< T, typename >::begin(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SmallVectorTemplateCommon< T, typename >::end(), findPointerConstIncrement(), llvm::SelectionDAG::getConstant(), llvm::User::getNumOperands(), llvm::User::getOperand(), getPointerConstIncrement(), I, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, isStore(), isValidBaseUpdate(), LHS, N, llvm::Offset, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SmallVectorImpl< T >::resize(), RHS, llvm::SmallVectorBase< Size_T >::size(), llvm::ISD::STORE, std::swap(), and TryCombineBaseUpdate().
Referenced by PerformLOADCombine(), PerformSTORECombine(), and PerformVLDCombine().
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Definition at line 12568 of file ARMISelLowering.cpp.
References llvm::AllOnes, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), isConditionalZeroOrAllOnes(), N, llvm::ISD::SELECT, and std::swap().
Referenced by combineSelectAndUseCommutative(), PerformADDCombineWithOperands(), performSUBCombine(), and PerformSUBCombine().
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Definition at line 12594 of file ARMISelLowering.cpp.
References llvm::AllOnes, combineSelectAndUse(), llvm::SDValue::getNode(), llvm::SDNode::hasOneUse(), and N.
Referenced by performADDCombine(), PerformANDCombine(), performANDCombine(), llvm::LanaiTargetLowering::PerformDAGCombine(), PerformORCombine(), performORCombine(), performXORCombine(), and PerformXORCombine().
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CombineVLDDUP - For a VDUPLANE node N, check if its source operand is a vldN-lane (N > 1) intrinsic, and if all the other uses of that intrinsic are also VDUPLANEs.
If so, combine them to a vldN-dup operation and return true.
Definition at line 16358 of file ARMISelLowering.cpp.
References llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SDNode::getConstantOperandVal(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::SDValue::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getResNo(), llvm::SelectionDAG::getVTList(), llvm::ISD::INTRINSIC_W_CHAIN, llvm::EVT::is64BitVector(), N, llvm::SDNode::use_begin(), llvm::SDNode::use_end(), llvm::ARMISD::VDUPLANE, llvm::ARMISD::VLD2DUP, llvm::ARMISD::VLD3DUP, and llvm::ARMISD::VLD4DUP.
Referenced by PerformVDUPLANECombine().
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BC
is a bitcast that is about to be turned into a VMOVDRR.
When DstVT
, the destination type of BC
, is on the vector register bank and the source of bitcast, Op
, operates on the same bank, it might be possible to combine them, such that everything stays on the vector register bank. return
The node that would replace BT
, if the combine is possible.
Definition at line 6178 of file ARMISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::APInt::getBitWidth(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::EVT::getScalarType(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::APInt::getZExtValue(), and llvm::EVT::isVector().
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Definition at line 4995 of file ARMISelLowering.cpp.
References DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVTList(), and llvm::ARMISD::SUBC.
Referenced by LowerSETCCCARRY(), and LowerUADDSUBO_CARRY().
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Definition at line 5008 of file ARMISelLowering.cpp.
References llvm::ARMISD::ADDE, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), and llvm::SelectionDAG::getVTList().
Referenced by LowerUADDSUBO_CARRY().
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Definition at line 10447 of file ARMISelLowering.cpp.
References llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getTargetConstant(), llvm::DataLayout::isBigEndian(), isBigEndian(), llvm::SelectionDAG::SplitScalar(), and std::swap().
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Emit a post-increment load operation with given size.
The instructions will be added to BB at Pos.
Definition at line 11355 of file ARMISelLowering.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::ARMCC::AL, assert(), llvm::BuildMI(), llvm::Data, llvm::RegState::Define, getLdOpcode(), llvm::predOps(), llvm::t1CondCodeOp(), and TII.
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Emit a post-increment store operation with given size.
The instructions will be added to BB at Pos.
Definition at line 11396 of file ARMISelLowering.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::ARMCC::AL, assert(), llvm::BuildMI(), llvm::Data, getStOpcode(), llvm::predOps(), llvm::t1CondCodeOp(), and TII.
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Definition at line 6680 of file ARMISelLowering.cpp.
References llvm::ARMISD::ASRL, assert(), llvm::ISD::BUILD_PAIR, llvm::ConstantSDNode::getAPIntValue(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::SDNode::getValueType(), llvm::SelectionDAG::getVTList(), llvm::SelectionDAG::getZExtOrTrunc(), llvm::Hi, llvm::isOneConstant(), llvm::Lo, llvm::ARMISD::LSLL, llvm::ARMISD::LSRL, N, llvm::ARMISD::RRX, llvm::ISD::SHL, llvm::SelectionDAG::SplitScalar(), llvm::ISD::SRA, llvm::ARMISD::SRA_GLUE, llvm::ISD::SRL, llvm::ARMISD::SRL_GLUE, llvm::ISD::SUB, and llvm::APInt::uge().
Referenced by llvm::ARMTargetLowering::ReplaceNodeResults().
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Definition at line 5606 of file ARMISelLowering.cpp.
References llvm::ISD::ADD, llvm::commonAlignment(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getNode(), isFloatingPointZero(), llvm_unreachable, and Ptr.
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Definition at line 6153 of file ARMISelLowering.cpp.
References assert(), llvm::ISD::BUILD_PAIR, DL, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getVTList(), N, llvm::ISD::READ_REGISTER, and Results.
Referenced by llvm::ARMTargetLowering::ReplaceNodeResults().
Definition at line 14860 of file ARMISelLowering.cpp.
References llvm::ARMISD::BFI, BitsProperlyConcatenate(), From, N, and ParseBFI().
Referenced by PerformBFICombine().
Definition at line 12797 of file ARMISelLowering.cpp.
References llvm::ISD::SMUL_LOHI, and llvm::ISD::UMUL_LOHI.
Referenced by AddCombineTo64bitMLAL().
Definition at line 16093 of file ARMISelLowering.cpp.
References llvm::ISD::ADD, N, llvm::ISD::OR, Ptr, and llvm::ARMISD::VLD1_UPD.
Referenced by CombineBaseUpdate().
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FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
Definition at line 2049 of file ARMISelLowering.cpp.
References llvm::ARMCC::AL, CC, llvm::ARMCC::EQ, llvm::ARMCC::GE, llvm::ARMCC::GT, llvm::ARMCC::HI, llvm::ARMCC::LE, llvm_unreachable, llvm::ARMCC::LS, llvm::ARMCC::LT, llvm::ARMCC::MI, llvm::ARMCC::NE, llvm::ARMCC::PL, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETO, llvm::ISD::SETOEQ, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETONE, llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SETUNE, llvm::ISD::SETUO, llvm::ARMCC::VC, and llvm::ARMCC::VS.
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GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit the specified operations to build the shuffle.
Definition at line 8455 of file ARMISelLowering.cpp.
References assert(), GeneratePerfectShuffle(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVTList(), LHS, llvm_unreachable, OP_COPY, OP_VDUP0, OP_VDUP1, OP_VDUP2, OP_VDUP3, OP_VEXT1, OP_VEXT2, OP_VEXT3, OP_VREV, OP_VTRNL, OP_VTRNR, OP_VUZPL, OP_VUZPR, OP_VZIPL, OP_VZIPR, PerfectShuffleTable, RHS, llvm::ARMISD::VDUPLANE, llvm::ARMISD::VEXT, llvm::ARMISD::VREV16, llvm::ARMISD::VREV32, llvm::ARMISD::VREV64, llvm::ARMISD::VTRN, llvm::ARMISD::VUZP, and llvm::ARMISD::VZIP.
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Adds logic in loop entry MBB to calculate loop iteration count and adds t2WhileLoopSetup and t2WhileLoopStart to generate WLS loop.
Definition at line 11821 of file ARMISelLowering.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineInstrBuilder::addUse(), llvm::ARMCC::AL, llvm::BuildMI(), llvm::RegState::Kill, MRI, llvm::predOps(), and TII.
Referenced by llvm::ARMTargetLowering::EmitInstrWithCustomInserter().
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Adds logic in the loopBody MBB to generate MVE_VCTP, t2DoLoopDec and t2DoLoopEnd.
These are used by later passes to generate tail predicated loops.
Definition at line 11859 of file ARMISelLowering.cpp.
References llvm::MachineInstrBuilder::add(), llvm::MachineInstrBuilder::addDef(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), llvm::MachineInstrBuilder::addUse(), llvm::ARMCC::AL, llvm::BuildMI(), MRI, llvm::ARMVCC::None, llvm::predOps(), llvm::ARMVCC::Then, and TII.
Referenced by llvm::ARMTargetLowering::EmitInstrWithCustomInserter().
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Definition at line 19759 of file ARMISelLowering.cpp.
References llvm::ISD::ADD, assert(), llvm::sampleprof::Base, llvm::SelectionDAG::getConstant(), llvm::ARM_AM::getShiftOpcForNode(), llvm::ARM_AM::no_shift, llvm::Offset, Ptr, RHS, and llvm::ISD::SUB.
Referenced by llvm::ARMTargetLowering::getPostIndexedAddressParts(), and llvm::ARMTargetLowering::getPreIndexedAddressParts().
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Definition at line 20669 of file ARMISelLowering.cpp.
References assert(), Context, llvm::EVT::getTypeForEVT(), isSigned(), llvm::ARMSubtarget::isTargetWindows(), N, llvm::ISD::SDIVREM, llvm::ISD::SREM, std::swap(), llvm::ISD::UDIVREM, and llvm::ISD::UREM.
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Definition at line 20651 of file ARMISelLowering.cpp.
References assert(), isSigned(), llvm_unreachable, N, llvm::ISD::SDIVREM, llvm::ISD::SREM, llvm::ISD::UDIVREM, and llvm::ISD::UREM.
Definition at line 9465 of file ARMISelLowering.cpp.
References assert(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::EVT::isSimple(), llvm_unreachable, and llvm::MVT::SimpleTy.
Return the load opcode for a given load size.
If load size >= 8, neon opcode will be returned.
Definition at line 11317 of file ARMISelLowering.cpp.
Referenced by emitPostLd().
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Definition at line 19843 of file ARMISelLowering.cpp.
References llvm::ISD::ADD, assert(), llvm::sampleprof::Base, llvm::SelectionDAG::getConstant(), llvm::Offset, Ptr, RHS, and llvm::ISD::SUB.
Referenced by llvm::ARMTargetLowering::getPostIndexedAddressParts(), and llvm::ARMTargetLowering::getPreIndexedAddressParts().
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Definition at line 16071 of file ARMISelLowering.cpp.
References llvm::ISD::ADD, llvm::SDValue::getNode(), llvm::ConstantSDNode::getZExtValue(), llvm::SelectionDAG::haveNoCommonBitsSet(), llvm::ISD::OR, Ptr, and llvm::ARMISD::VLD1_UPD.
Referenced by CombineBaseUpdate().
Return the store opcode for a given store size.
If store size >= 8, neon opcode will be returned.
Definition at line 11336 of file ARMISelLowering.cpp.
Referenced by emitPostSt().
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Definition at line 19818 of file ARMISelLowering.cpp.
References llvm::ISD::ADD, assert(), llvm::sampleprof::Base, llvm::SelectionDAG::getConstant(), llvm::Offset, Ptr, RHS, and llvm::ISD::SUB.
Referenced by llvm::ARMTargetLowering::getPostIndexedAddressParts(), and llvm::ARMTargetLowering::getPreIndexedAddressParts().
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Definition at line 14646 of file ARMISelLowering.cpp.
References llvm_unreachable, N, llvm::ARMISD::VCMP, and llvm::ARMISD::VCMPZ.
Referenced by CanInvertMVEVCMP(), and PerformXORCombine().
Definition at line 8551 of file ARMISelLowering.cpp.
References llvm::EVT::getSimpleVT(), llvm_unreachable, and llvm::MVT::SimpleTy.
Referenced by LowerCONCAT_VECTORS_i1(), LowerEXTRACT_SUBVECTOR(), LowerEXTRACT_VECTOR_ELT_i1(), LowerINSERT_VECTOR_ELT_i1(), and PromoteMVEPredVector().
Getvshiftimm - Check if this is a valid build_vector for the immediate operand of a vector shift operation, where all the elements of the build_vector must have the same constant integer value.
Definition at line 6587 of file ARMISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::APInt::getSExtValue(), and llvm::BuildVectorSDNode::isConstantSplat().
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getZeroVector - Returns a vector of specified type with all zero elements.
Zero vectors are used to represent vector negation and in those cases will be implemented with the NEON VNEG instruction. However, VNEG does not support i64 elements, so sometimes the zero vectors will need to be explicitly constructed. Regardless, use a canonical VMOV to create the zero vector.
Definition at line 6287 of file ARMISelLowering.cpp.
References assert(), llvm::ISD::BITCAST, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::EVT::is128BitVector(), llvm::EVT::isVector(), and llvm::ARMISD::VMOVIMM.
Referenced by canonicalizeShuffleMaskWithHorizOp(), combineAdd(), combineArithReduction(), combineConcatVectorOps(), combineEXTRACT_SUBVECTOR(), combineINSERT_SUBVECTOR(), combineTargetShuffle(), combineX86ShuffleChain(), combineX86ShufflesConstants(), combineX86ShufflesRecursively(), createVariablePermute(), getAVX2GatherNode(), getGatherNode(), getNullFPConstForNullVal(), getScalarMaskingNode(), getShuffleVectorZeroOrUndef(), getVectorMaskingNode(), LowerAVXCONCAT_VECTORS(), LowerBuildVectorAsInsert(), LowerBuildVectorv16i8(), LowerBuildVectorv4x32(), LowerCTTZ(), LowerMGATHER(), LowerMLOAD(), LowerSCALAR_TO_VECTOR(), LowerShift(), lowerShuffleAsBlend(), lowerShuffleAsSpecificZeroOrAnyExtend(), lowerShuffleAsVALIGN(), lowerShuffleToEXPAND(), lowerShuffleWithSHUFPD(), lowerV16I8Shuffle(), lowerV2X128Shuffle(), lowerV4X128Shuffle(), lowerV8I16Shuffle(), lowerVECTOR_SHUFFLE(), matchBinaryPermuteShuffle(), matchShuffleWithUNPCK(), llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(), llvm::X86TargetLowering::SimplifyMultipleUseDemandedBitsForTargetNode(), and widenSubVector().
hasNormalLoadOperand - Check if any of the operands of a BUILD_VECTOR node are normal, non-volatile loads.
If so, it is profitable to bitcast an i64 vector to have f64 elements, since the value can then be loaded directly into a VFP register.
Definition at line 15239 of file ARMISelLowering.cpp.
References llvm::ISD::isNormalLoad(), and N.
Referenced by PerformBUILD_VECTORCombine().
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IntCCToARMCC - Convert a DAG integer condition code to an ARM CC.
Definition at line 2032 of file ARMISelLowering.cpp.
References CC, llvm::ARMCC::EQ, llvm::ARMCC::GE, llvm::ARMCC::GT, llvm::ARMCC::HI, llvm::ARMCC::HS, llvm::ARMCC::LE, llvm_unreachable, llvm::ARMCC::LO, llvm::ARMCC::LS, llvm::ARMCC::LT, llvm::ARMCC::NE, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, and llvm::ISD::SETULT.
Referenced by LowerSETCCCARRY().
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Definition at line 9581 of file ARMISelLowering.cpp.
References llvm::ISD::ADD, llvm::SDNode::hasOneUse(), isSignExtended(), N, and llvm::ISD::SUB.
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Definition at line 9592 of file ARMISelLowering.cpp.
References llvm::ISD::ADD, llvm::SDNode::hasOneUse(), isZeroExtended(), N, and llvm::ISD::SUB.
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Definition at line 14966 of file ARMISelLowering.cpp.
References llvm::ISD::AND, CC, llvm::ARMISD::CMOV, llvm::ARMISD::CMPZ, llvm::ARMISD::CSINC, llvm::SDValue::getConstantOperandVal(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::ARMCC::getOppositeCondition(), llvm::SDNode::hasOneUse(), llvm::isNullConstant(), and llvm::isOneConstant().
Referenced by llvm::ARMTargetLowering::PerformCMOVCombine(), PerformCMPZCombine(), and PerformCSETCombine().
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Definition at line 12495 of file ARMISelLowering.cpp.
References llvm::AllOnes, CC, llvm::SelectionDAG::getAllOnesConstant(), llvm::SelectionDAG::getConstant(), isZeroOrAllOnes(), N, llvm::ISD::SELECT, llvm::ISD::SETCC, llvm::ISD::SIGN_EXTEND, and llvm::ISD::ZERO_EXTEND.
Referenced by combineSelectAndUse().
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isExtendedBUILD_VECTOR - Check if N is a constant BUILD_VECTOR where each element has been zero/sign-extended, depending on the isSigned parameter, from an integer type half its size.
Definition at line 9393 of file ARMISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, llvm::CallingConv::C, llvm::SelectionDAG::getDataLayout(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::ConstantSDNode::getSExtValue(), llvm::SDNode::getValueType(), llvm::DataLayout::isBigEndian(), llvm::isIntN(), isSigned(), llvm::isUIntN(), llvm::ConstantSDNode::isZero(), and N.
isFloatingPointZero - Return true if this is +0.0.
Definition at line 4699 of file ARMISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::ISD::isEXTLoad(), llvm::ISD::isNON_EXTLoad(), llvm::isNullConstant(), llvm::ARMISD::VMOVIMM, and llvm::ARMISD::Wrapper.
Referenced by bitcastf32Toi32(), canChangeToInt(), and expandf64Toi32().
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Definition at line 5255 of file ARMISelLowering.cpp.
References CC, llvm::ISD::SETGE, and llvm::ISD::SETGT.
Referenced by isLowerSaturate(), and LowerSaturatingConditional().
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Definition at line 21937 of file ARMISelLowering.cpp.
References llvm::sampleprof::Base, HA_DOUBLE, HA_FLOAT, HA_UNKNOWN, HA_VECT128, HA_VECT64, llvm::Type::isDoubleTy(), llvm::Type::isFloatTy(), and isHomogeneousAggregate().
Referenced by llvm::ARMTargetLowering::functionArgumentNeedsConsecutiveRegisters(), and isHomogeneousAggregate().
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isLegalAddressImmediate - Return true if the integer value can be used as the offset of the target addressing mode for load / store of the given type.
Definition at line 19552 of file ARMISelLowering.cpp.
References llvm::EVT::getSimpleVT(), llvm::ARMSubtarget::hasVFP2Base(), isLegalT1AddressImmediate(), isLegalT2AddressImmediate(), llvm::EVT::isSimple(), llvm::ARMSubtarget::isThumb1Only(), llvm::ARMSubtarget::isThumb2(), and llvm::MVT::SimpleTy.
Referenced by llvm::ARMTargetLowering::isLegalAddressingMode().
Definition at line 8382 of file ARMISelLowering.cpp.
References OP_COPY, OP_VDUP0, OP_VDUP1, OP_VDUP2, OP_VDUP3, and OP_VREV.
Referenced by llvm::ARMTargetLowering::isShuffleMaskLegal(), and LowerVECTOR_SHUFFLE().
Definition at line 19472 of file ARMISelLowering.cpp.
References llvm::EVT::getSimpleVT(), and llvm::MVT::SimpleTy.
Referenced by isLegalAddressImmediate().
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Definition at line 19498 of file ARMISelLowering.cpp.
References llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::MVT::getVectorElementType(), llvm::ARMSubtarget::hasVFP2Base(), llvm::EVT::isFloatingPoint(), llvm::EVT::isInteger(), llvm::EVT::isVector(), and llvm::MVT::SimpleTy.
Referenced by isLegalAddressImmediate().
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Definition at line 5269 of file ARMISelLowering.cpp.
References CC, isGTorGE(), isLTorLE(), LHS, and RHS.
Referenced by isLowerSaturatingConditional().
Definition at line 5361 of file ARMISelLowering.cpp.
References CC, isLowerSaturate(), LHS, and RHS.
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Definition at line 5259 of file ARMISelLowering.cpp.
References CC, llvm::ISD::SETLE, and llvm::ISD::SETLT.
Referenced by isLowerSaturate(), and LowerSaturatingConditional().
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Check if ShuffleMask
is a NEON two-result shuffle (VZIP, VUZP, VTRN), and return the corresponding ARMISD opcode if it is, or 0 if it isn't.
Definition at line 7533 of file ARMISelLowering.cpp.
References isVTRN_v_undef_Mask(), isVTRNMask(), isVUZP_v_undef_Mask(), isVUZPMask(), isVZIP_v_undef_Mask(), isVZIPMask(), llvm::ARMISD::VTRN, llvm::ARMISD::VUZP, and llvm::ARMISD::VZIP.
Referenced by llvm::ARMTargetLowering::isShuffleMaskLegal(), and LowerVECTOR_SHUFFLE().
Definition at line 18053 of file ARMISelLowering.cpp.
References llvm::CallingConv::C, and llvm::APInt::isPowerOf2().
Referenced by llvm::ARMTargetLowering::PerformCMOVCombine(), and llvm::ARMTargetLowering::PerformCMOVToBFICombine().
Definition at line 7853 of file ARMISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::ISD::MUL, N, llvm::ISD::SADDSAT, llvm::ISD::SSUBSAT, llvm::ISD::SUB, llvm::ISD::UADDSAT, and llvm::ISD::USUBSAT.
Definition at line 7556 of file ARMISelLowering.cpp.
References llvm::EVT::getVectorNumElements().
Referenced by llvm::ShuffleVectorInst::isReverse(), llvm::ShuffleVectorInst::isReverseMask(), llvm::ARMTargetLowering::isShuffleMaskLegal(), LowerVECTOR_SHUFFLE(), and LowerVECTOR_SHUFFLE_i1().
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Definition at line 2025 of file ARMISelLowering.cpp.
References llvm::SelectionDAG::ComputeNumSignBits(), isSHL16(), and isSRA16().
Referenced by AddCombineTo64BitSMLAL16(), and PerformORCombineToSMULWBT().
Definition at line 2013 of file ARMISelLowering.cpp.
References llvm::ISD::SHL.
Referenced by isS16(), and PerformORCombineToSMULWBT().
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isSignExtended - Check if a node is a vector value that is sign-extended or a constant BUILD_VECTOR with sign-extended elements.
Definition at line 9446 of file ARMISelLowering.cpp.
References isExtendedBUILD_VECTOR(), llvm::ISD::isSEXTLoad(), N, and llvm::ISD::SIGN_EXTEND.
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Definition at line 7739 of file ARMISelLowering.cpp.
References llvm::SelectionDAG::getConstant(), llvm::ARM_AM::getSOImmVal(), and N.
Definition at line 7234 of file ARMISelLowering.cpp.
References llvm::EVT::getVectorNumElements().
Referenced by LowerVECTOR_SHUFFLE().
Definition at line 2005 of file ARMISelLowering.cpp.
References llvm::ISD::SRA.
Referenced by AddCombineTo64BitSMLAL16(), isS16(), and PerformORCombineToSMULWBT().
Definition at line 1997 of file ARMISelLowering.cpp.
References llvm::ISD::SRL.
Referenced by PerformORCombineToSMULWBT().
Definition at line 7570 of file ARMISelLowering.cpp.
References llvm::EVT::getVectorNumElements(), and llvm::Upper.
Referenced by llvm::ARMTargetLowering::isShuffleMaskLegal(), and LowerVECTOR_SHUFFLE().
Definition at line 16117 of file ARMISelLowering.cpp.
References llvm::SDNode::hasPredecessorHelper(), N, and llvm::SmallVectorTemplateBase< T, bool >::push_back().
Referenced by CombineBaseUpdate().
Definition at line 14629 of file ARMISelLowering.cpp.
References CC, llvm::ARMCC::EQ, llvm::ARMCC::GE, llvm::ARMCC::GT, llvm::ARMCC::HI, llvm::ARMCC::HS, llvm::ARMCC::LE, llvm::ARMCC::LT, and llvm::ARMCC::NE.
Referenced by CanInvertMVEVCMP(), and PerformVCMPCombine().
Definition at line 7262 of file ARMISelLowering.cpp.
References llvm::EVT::getVectorNumElements().
Referenced by llvm::ARMTargetLowering::isShuffleMaskLegal(), and LowerVECTOR_SHUFFLE().
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isVMOVModifiedImm - Check if the specified splat value corresponds to a valid vector constant for a NEON or MVE instruction with a "modified immediate" operand (e.g., VMOV).
If so, return the encoded value.
Definition at line 6970 of file ARMISelLowering.cpp.
References assert(), llvm::ARM_AM::createVMOVModImm(), llvm::SelectionDAG::getDataLayout(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getTargetConstant(), llvm::EVT::is128BitVector(), llvm::DataLayout::isBigEndian(), llvm_unreachable, llvm::MVEVMVNModImm, llvm::OtherModImm, and llvm::VMOVModImm.
Referenced by PerformANDCombine(), and PerformORCombine().
Definition at line 7592 of file ARMISelLowering.cpp.
References llvm::EVT::getVectorNumElements(), N, and llvm::Offset.
Referenced by llvm::ARMTargetLowering::isShuffleMaskLegal(), and LowerVECTOR_SHUFFLE().
Definition at line 7616 of file ARMISelLowering.cpp.
References llvm::EVT::getVectorNumElements().
Referenced by llvm::ARMTargetLowering::PerformMVETruncCombine(), and PerformShuffleVMOVNCombine().
isVShiftLImm - Check if this is a valid build_vector for the immediate operand of a vector shift left operation.
That value must be in the range: 0 <= Value < ElementBits for a left shift; or 0 <= Value <= ElementBits for a long left shift.
Definition at line 6608 of file ARMISelLowering.cpp.
References assert(), llvm::EVT::getScalarSizeInBits(), getVShiftImm(), and llvm::EVT::isVector().
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isVShiftRImm - Check if this is a valid build_vector for the immediate operand of a vector shift right operation.
For a shift opcode, the value is positive, but for an intrinsic the value count must be negative. The absolute value must be in the range: 1 <= |Value| <= ElementBits for a right shift; or 1 <= |Value| <= ElementBits/2 for a narrow right shift.
Definition at line 6622 of file ARMISelLowering.cpp.
References assert(), llvm::EVT::getScalarSizeInBits(), getVShiftImm(), and llvm::EVT::isVector().
Definition at line 7298 of file ARMISelLowering.cpp.
Referenced by llvm::ARMTargetLowering::isShuffleMaskLegal().
isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
Definition at line 7365 of file ARMISelLowering.cpp.
References llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorNumElements(), and SelectPairHalf().
Referenced by isNEONTwoResultShuffleMask().
Definition at line 7333 of file ARMISelLowering.cpp.
References llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorNumElements(), and SelectPairHalf().
Referenced by isNEONTwoResultShuffleMask().
isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
Definition at line 7427 of file ARMISelLowering.cpp.
References llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorNumElements(), Idx, llvm::EVT::is64BitVector(), and SelectPairHalf().
Referenced by isNEONTwoResultShuffleMask().
Definition at line 7397 of file ARMISelLowering.cpp.
References llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorNumElements(), llvm::EVT::is64BitVector(), and SelectPairHalf().
Referenced by isNEONTwoResultShuffleMask().
Definition at line 12607 of file ARMISelLowering.cpp.
References N, llvm::ARMISD::VTRN, and llvm::ARMISD::VUZP.
Referenced by AddCombineToVPADD(), and AddCombineVUZPToVPADDL().
isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
Definition at line 7501 of file ARMISelLowering.cpp.
References llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorNumElements(), Idx, llvm::EVT::is64BitVector(), and SelectPairHalf().
Referenced by isNEONTwoResultShuffleMask().
Definition at line 7468 of file ARMISelLowering.cpp.
References llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorNumElements(), Idx, llvm::EVT::is64BitVector(), and SelectPairHalf().
Referenced by isNEONTwoResultShuffleMask().
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isZeroExtended - Check if a node is a vector value that is zero-extended (or any-extended) or a constant BUILD_VECTOR with zero-extended elements.
Definition at line 9456 of file ARMISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, isExtendedBUILD_VECTOR(), llvm::ISD::isZEXTLoad(), N, and llvm::ISD::ZERO_EXTEND.
Definition at line 12479 of file ARMISelLowering.cpp.
References llvm::AllOnes, llvm::isAllOnesConstant(), llvm::isNullConstant(), and N.
Referenced by combineSelectAndUse(), and isConditionalZeroOrAllOnes().
Definition at line 10234 of file ARMISelLowering.cpp.
References llvm::ISD::isBuildVectorAllZeros(), llvm::isNullConstant(), N, and llvm::ARMISD::VMOVIMM.
Referenced by findZeroVectorIdx(), LowerMLOAD(), PerformSUBCombine(), and PerformVCMPCombine().
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Definition at line 5056 of file ARMISelLowering.cpp.
References llvm::Add, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSExtOrTrunc(), llvm::EVT::getSimpleVT(), llvm::EVT::isSimple(), llvm::ARMSubtarget::isThumb1Only(), llvm::ARMISD::QADD16b, llvm::ARMISD::QADD8b, llvm::ARMISD::QSUB16b, llvm::ARMISD::QSUB8b, llvm::ISD::SADDSAT, llvm::MVT::SimpleTy, llvm::ISD::SSUBSAT, llvm::ISD::TRUNCATE, llvm::ISD::UADDSAT, llvm::ARMISD::UQADD16b, llvm::ARMISD::UQADD8b, llvm::ARMISD::UQSUB16b, llvm::ARMISD::UQSUB8b, and llvm::ISD::USUBSAT.
Referenced by llvm::ARMTargetLowering::LowerOperation(), and llvm::ARMTargetLowering::ReplaceNodeResults().
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Definition at line 4240 of file ARMISelLowering.cpp.
References assert(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::ISD::INTRINSIC_VOID, llvm::ARM_MB::ISH, llvm::ARM_MB::ISHST, llvm::ARMSubtarget::isMClass(), llvm::ARMISD::MEMBARRIER_MCR, llvm::Release, llvm::SyncScope::SingleThread, and llvm::ARM_MB::SY.
Referenced by llvm::ARMTargetLowering::LowerOperation(), llvm::RISCVTargetLowering::LowerOperation(), and llvm::X86TargetLowering::LowerOperation().
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Definition at line 10414 of file ARMISelLowering.cpp.
References llvm::isStrongerThanMonotonic().
Referenced by llvm::ARMTargetLowering::LowerOperation().
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Definition at line 7756 of file ARMISelLowering.cpp.
References llvm::all_of(), assert(), llvm::sampleprof::Base, llvm::drop_begin(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getValueType(), llvm::EVT::getVectorNumElements(), llvm::ISD::INSERT_VECTOR_ELT, llvm::ARMISD::PREDICATE_CAST, and llvm::ISD::SIGN_EXTEND_INREG.
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Definition at line 7818 of file ARMISelLowering.cpp.
References llvm::ISD::ADD, DL, llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVTList(), I, N, and llvm::ARMISD::VIDUP.
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Definition at line 7697 of file ARMISelLowering.cpp.
References assert(), llvm::ISD::BUILD_VECTOR, Check, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FP_EXTEND, llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), Idx, llvm::Offset, and llvm::ARMISD::VCVTL.
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Definition at line 7644 of file ARMISelLowering.cpp.
References assert(), llvm::ISD::BUILD_VECTOR, Check, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FP_ROUND, llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), Idx, and llvm::ARMISD::VCVTN.
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Definition at line 9202 of file ARMISelLowering.cpp.
References assert(), llvm::ISD::BITCAST, llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm::DWARFExpression::Operation::getNumOperands(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getUNDEF(), llvm::ISD::INSERT_VECTOR_ELT, llvm::SDValue::isUndef(), and LowerCONCAT_VECTORS_i1().
Referenced by llvm::ARMTargetLowering::LowerOperation(), llvm::X86TargetLowering::LowerOperation(), LowerSDIV(), and LowerUDIV().
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Definition at line 9120 of file ARMISelLowering.cpp.
References assert(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::EVT::getDoubleNumVectorElementsVT(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm::DWARFExpression::Operation::getNumOperands(), llvm::EVT::getScalarType(), llvm::EVT::getSimpleVT(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), getVectorTyFromPredicateVector(), llvm::MVT::getVectorVT(), I, llvm::ISD::INSERT_VECTOR_ELT, llvm::isPowerOf2_32(), llvm::ARMISD::MVETRUNC, llvm::ARMCC::NE, PromoteMVEPredVector(), llvm::SmallVectorImpl< T >::resize(), llvm::SmallVectorBase< Size_T >::size(), llvm::ISD::UNDEF, llvm::ARMISD::VCMPZ, and llvm::ARMISD::VECTOR_REG_CAST.
Referenced by LowerCONCAT_VECTORS().
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Definition at line 6551 of file ARMISelLowering.cpp.
References assert(), llvm::ISD::CTPOP, DL, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getDataLayout(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::TargetLoweringBase::getPointerTy(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::MVT::getVectorVT(), llvm::ISD::INTRINSIC_WO_CHAIN, llvm::EVT::is64BitVector(), N, and llvm::SmallVectorTemplateBase< T, bool >::push_back().
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Definition at line 6495 of file ARMISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::AND, llvm::ISD::BITREVERSE, llvm::ISD::CTLZ, llvm::ISD::CTPOP, llvm::ISD::CTTZ_ZERO_UNDEF, llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetConstant(), llvm::EVT::getVectorElementType(), getZeroVector(), llvm::EVT::isVector(), N, llvm::ISD::SUB, llvm::ARMISD::VMOVIMM, and X.
Referenced by llvm::ARMTargetLowering::LowerOperation(), and llvm::X86TargetLowering::LowerOperation().
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Definition at line 9227 of file ARMISelLowering.cpp.
References assert(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getScalarType(), llvm::EVT::getSimpleVT(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), getVectorTyFromPredicateVector(), llvm::MVT::getVectorVT(), llvm::ISD::INSERT_VECTOR_ELT, llvm::ARMCC::NE, llvm::ARMISD::PREDICATE_CAST, PromoteMVEPredVector(), llvm::ISD::UNDEF, and llvm::ARMISD::VCMPZ.
Referenced by llvm::ARMTargetLowering::LowerOperation(), and llvm::X86TargetLowering::LowerOperation().
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Definition at line 9099 of file ARMISelLowering.cpp.
References llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getScalarValueSizeInBits(), llvm::SDValue::getValueType(), LowerEXTRACT_VECTOR_ELT_i1(), and llvm::ARMISD::VGETLANEu.
Referenced by llvm::ARMTargetLowering::LowerOperation().
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Definition at line 9081 of file ARMISelLowering.cpp.
References assert(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), getVectorTyFromPredicateVector(), llvm::ARMISD::PREDICATE_CAST, and llvm::ISD::SRL.
Referenced by LowerEXTRACT_VECTOR_ELT().
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Definition at line 5913 of file ARMISelLowering.cpp.
References DL, llvm::ISD::FP_TO_SINT_SAT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getScalarType(), llvm::SelectionDAG::getValueType(), llvm::ISD::SMAX, llvm::ISD::SMIN, and llvm::ISD::UMIN.
Referenced by llvm::ARMTargetLowering::LowerOperation(), and llvm::ARMTargetLowering::ReplaceNodeResults().
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Definition at line 9018 of file ARMISelLowering.cpp.
References assert(), llvm::ARMISD::BFI, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getValueType(), getVectorTyFromPredicateVector(), llvm::ARMISD::PREDICATE_CAST, and llvm::ISD::SIGN_EXTEND_INREG.
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Definition at line 3141 of file ARMISelLowering.cpp.
References llvm::SmallVectorTemplateCommon< T, typename >::begin(), DL, F, llvm::SelectionDAG::getConstant(), llvm::MachineFunction::getFunction(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::SmallVectorImpl< T >::insert(), llvm::ARMISD::INTRET_GLUE, and llvm::report_fatal_error().
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Definition at line 10240 of file ARMISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::SelectionDAG::getMaskedLoad(), llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::getValue(), llvm::SDValue::isUndef(), isZeroVector(), N, llvm::ARMISD::VECTOR_REG_CAST, llvm::ARMISD::VMOVIMM, and llvm::ISD::VSELECT.
Referenced by llvm::ARMTargetLowering::LowerOperation(), and llvm::X86TargetLowering::LowerOperation().
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Definition at line 9603 of file ARMISelLowering.cpp.
References assert(), llvm::ISD::BITCAST, DL, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getValueType(), llvm::EVT::is128BitVector(), llvm::EVT::is64BitVector(), isAddSubSExt(), isAddSubZExt(), llvm::EVT::isInteger(), isSignExtended(), isZeroExtended(), SkipExtensionForVMULL(), std::swap(), llvm::ARMISD::VMULLs, and llvm::ARMISD::VMULLu.
Referenced by llvm::ARMTargetLowering::LowerOperation(), and llvm::X86TargetLowering::LowerOperation().
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Definition at line 10105 of file ARMISelLowering.cpp.
References assert(), llvm::ISD::BITREVERSE, llvm::ISD::EXTLOAD, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getExtLoad(), llvm::EVT::getIntegerVT(), llvm::SelectionDAG::getMergeValues(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::DataLayout::isBigEndian(), llvm::ISD::NON_EXTLOAD, llvm::ARMISD::PREDICATE_CAST, and llvm::ISD::SRL.
Referenced by llvm::ARMTargetLowering::LowerOperation().
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Definition at line 10163 of file ARMISelLowering.cpp.
References assert(), llvm::ISD::BITREVERSE, llvm::ISD::BUILD_VECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::EVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTruncStore(), llvm::SelectionDAG::getUNDEF(), llvm::EVT::getVectorNumElements(), I, llvm::DataLayout::isBigEndian(), llvm::ARMISD::PREDICATE_CAST, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and llvm::ISD::SRL.
Referenced by LowerSTORE().
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Definition at line 4276 of file ARMISelLowering.cpp.
References llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::ARMSubtarget::isThumb1Only(), llvm::ARMSubtarget::isThumb2(), and llvm::ARMISD::PRELOAD.
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Definition at line 8532 of file ARMISelLowering.cpp.
References assert(), DL, llvm::SelectionDAG::getNode(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), and llvm::ARMISD::VREV64.
Referenced by LowerVECTOR_SHUFFLE().
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Definition at line 5295 of file ARMISelLowering.cpp.
References llvm::countr_one(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), isGTorGE(), isLTorLE(), llvm::isPowerOf2_64(), llvm::ISD::SELECT_CC, llvm::ARMISD::SSAT, and llvm::ARMISD::USAT.
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Definition at line 9748 of file ARMISelLowering.cpp.
References assert(), llvm::ISD::CONCAT_VECTORS, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), LowerCONCAT_VECTORS(), LowerSDIV_v4i16(), LowerSDIV_v4i8(), llvm::ISD::SIGN_EXTEND, and llvm::ISD::TRUNCATE.
Referenced by llvm::ARMTargetLowering::LowerOperation().
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Definition at line 9709 of file ARMISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::BITCAST, llvm::ISD::FMUL, llvm::ISD::FP_TO_SINT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::ISD::INTRINSIC_WO_CHAIN, llvm::ISD::SIGN_EXTEND, llvm::ISD::SINT_TO_FP, and llvm::ISD::TRUNCATE.
Referenced by LowerSDIV(), and LowerUDIV().
Definition at line 9678 of file ARMISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::BITCAST, llvm::ISD::FMUL, llvm::ISD::FP_TO_SINT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::ISD::INTRINSIC_WO_CHAIN, llvm::ISD::SIGN_EXTEND, llvm::ISD::SINT_TO_FP, llvm::ISD::TRUNCATE, X, and Y.
Referenced by LowerSDIV().
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Definition at line 6937 of file ARMISelLowering.cpp.
References assert(), llvm::ARMISD::CMOV, Cond, ConvertBooleanCarryToCarryFlag(), DL, llvm::get(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getCopyToReg(), llvm::SelectionDAG::getEntryNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getRegister(), llvm::SDValue::getValue(), llvm::SelectionDAG::getVTList(), IntCCToARMCC(), LHS, RHS, llvm::ISD::SUB, and llvm::ARMISD::SUBE.
Referenced by llvm::ARMTargetLowering::LowerOperation().
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Definition at line 6637 of file ARMISelLowering.cpp.
References assert(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), getZeroVector(), llvm::EVT::isVector(), isVShiftLImm(), isVShiftRImm(), N, llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ISD::SUB, llvm::ARMISD::VSHLIMM, llvm::ARMISD::VSHLs, llvm::ARMISD::VSHLu, llvm::ARMISD::VSHRsIMM, and llvm::ARMISD::VSHRuIMM.
Referenced by lowerBuildVectorToBitOp(), llvm::ARMTargetLowering::LowerOperation(), and llvm::X86TargetLowering::LowerOperation().
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Definition at line 10201 of file ARMISelLowering.cpp.
References assert(), llvm::ISD::EXTRACT_ELEMENT, llvm::SelectionDAG::getDataLayout(), llvm::ARMSubtarget::getDualLoadStoreAlignment(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getVTList(), llvm::Hi, llvm::DataLayout::isLittleEndian(), llvm::ARMSubtarget::isThumb1Only(), llvm::Lo, LowerPredicateStore(), N, and llvm::ARMISD::STRD.
Referenced by llvm::ARMTargetLowering::LowerOperation(), and llvm::SparcTargetLowering::LowerOperation().
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Definition at line 9297 of file ARMISelLowering.cpp.
References DL, llvm::SelectionDAG::getNode(), llvm::EVT::getScalarType(), llvm::Hi, llvm::Lo, LowerTruncatei1(), llvm::ARMISD::MVETRUNC, N, and llvm::SelectionDAG::SplitVectorOperand().
Referenced by llvm::ARMTargetLowering::LowerOperation(), and llvm::ARMTargetLowering::ReplaceNodeResults().
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Definition at line 9281 of file ARMISelLowering.cpp.
References llvm::And, llvm::ISD::AND, assert(), DL, llvm::SelectionDAG::getCondCode(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), N, llvm::ISD::SETCC, and llvm::ISD::SETNE.
Referenced by LowerTruncate().
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Definition at line 9861 of file ARMISelLowering.cpp.
References llvm::ARMISD::ADDE, ConvertBooleanCarryToCarryFlag(), ConvertCarryFlagToBooleanCarry(), DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getVTList(), llvm::ISD::MERGE_VALUES, N, llvm::ISD::SUB, llvm::ARMISD::SUBE, and llvm::ISD::UADDO_CARRY.
Referenced by llvm::ARMTargetLowering::LowerOperation().
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Definition at line 9784 of file ARMISelLowering.cpp.
References llvm::ISD::ADD, assert(), llvm::ISD::BITCAST, llvm::ISD::CONCAT_VECTORS, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::FMUL, llvm::ISD::FP_TO_SINT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getNode(), llvm::ISD::INTRINSIC_WO_CHAIN, LowerCONCAT_VECTORS(), LowerSDIV_v4i16(), llvm::ISD::SINT_TO_FP, llvm::ISD::TRUNCATE, and llvm::ISD::ZERO_EXTEND.
Referenced by llvm::ARMTargetLowering::LowerOperation().
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Definition at line 4303 of file ARMISelLowering.cpp.
References llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getInfo(), llvm::SelectionDAG::getMachineFunction(), llvm::TargetLoweringBase::getPointerTy(), llvm::SelectionDAG::getStore(), llvm::SelectionDAG::getTargetLoweringInfo(), and llvm::ARMFunctionInfo::getVarArgsFrameIndex().
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Definition at line 10267 of file ARMISelLowering.cpp.
References llvm::ISD::AND, llvm::ISD::ANY_EXTEND, assert(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FADD, llvm::ISD::FMAXNUM, llvm::ISD::FMINNUM, llvm::ISD::FMUL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm_unreachable, llvm::ISD::MUL, llvm::ISD::OR, llvm::ISD::VECREDUCE_AND, llvm::ISD::VECREDUCE_FADD, llvm::ISD::VECREDUCE_FMAX, llvm::ISD::VECREDUCE_FMIN, llvm::ISD::VECREDUCE_FMUL, llvm::ISD::VECREDUCE_MUL, llvm::ISD::VECREDUCE_OR, llvm::ISD::VECREDUCE_XOR, llvm::ARMISD::VREV16, llvm::ARMISD::VREV32, and llvm::ISD::XOR.
Referenced by llvm::ARMTargetLowering::LowerOperation(), and LowerVecReduceF().
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Definition at line 10333 of file ARMISelLowering.cpp.
References LowerVecReduce().
Referenced by llvm::ARMTargetLowering::LowerOperation().
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Definition at line 10340 of file ARMISelLowering.cpp.
References assert(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::Hi, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::EVT::is128BitVector(), llvm_unreachable, llvm::Lo, llvm::ISD::SIGN_EXTEND, llvm::SelectionDAG::SplitVector(), llvm::ISD::VECREDUCE_SMAX, llvm::ISD::VECREDUCE_SMIN, llvm::ISD::VECREDUCE_UMAX, llvm::ISD::VECREDUCE_UMIN, and llvm::ISD::ZERO_EXTEND.
Referenced by llvm::ARMTargetLowering::LowerOperation().
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Definition at line 8790 of file ARMISelLowering.cpp.
References llvm::all_of(), assert(), llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, llvm::ARMISD::BUILD_VECTOR, llvm::ISD::CONCAT_VECTORS, llvm::ISD::EXTRACT_VECTOR_ELT, GeneratePerfectShuffle(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::EVT::getFloatingPointVT(), llvm::MVT::getIntegerVT(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::ShuffleVectorSDNode::getSplatIndex(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::MVT::getVectorVT(), llvm::SelectionDAG::getVTList(), llvm::Hi, isLegalMVEShuffleOp(), isNEONTwoResultShuffleMask(), isReverseMask(), isSingletonVEXTMask(), llvm::ShuffleVectorSDNode::isSplat(), isTruncMask(), llvm::SDValue::isUndef(), isVEXTMask(), isVMOVNMask(), llvm::isVREVMask(), llvm::Lo, LowerReverse_VECTOR_SHUFFLE(), LowerVECTOR_SHUFFLE_i1(), LowerVECTOR_SHUFFLEUsingMovs(), LowerVECTOR_SHUFFLEUsingOneOff(), LowerVECTOR_SHUFFLEv8i8(), llvm::ARMISD::MVETRUNC, PerfectShuffleTable, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::ISD::SCALAR_TO_VECTOR, llvm::ArrayRef< T >::size(), llvm::ISD::SRL, std::swap(), llvm::ARMISD::VDUP, llvm::ARMISD::VDUPLANE, llvm::ARMISD::VECTOR_REG_CAST, llvm::ARMISD::VEXT, llvm::ARMISD::VMOVN, llvm::ARMISD::VREV16, llvm::ARMISD::VREV32, and llvm::ARMISD::VREV64.
Referenced by llvm::ARMTargetLowering::LowerOperation().
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Definition at line 8601 of file ARMISelLowering.cpp.
References assert(), llvm::ISD::BITREVERSE, llvm::cast(), llvm::SelectionDAG::getConstant(), llvm::ShuffleVectorSDNode::getMask(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVectorShuffle(), isReverseMask(), llvm::ARMCC::NE, llvm::ARMISD::PREDICATE_CAST, PromoteMVEPredVector(), llvm::ISD::SRL, llvm::ARMISD::VCMPZ, and llvm::ARMISD::VECTOR_REG_CAST.
Referenced by LowerVECTOR_SHUFFLE().
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Definition at line 8653 of file ARMISelLowering.cpp.
References assert(), llvm::ARMISD::BUILD_VECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getBitcast(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::Length, and llvm::SmallVectorTemplateBase< T, bool >::push_back().
Referenced by LowerVECTOR_SHUFFLE().
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Definition at line 8739 of file ARMISelLowering.cpp.
References llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getNode(), llvm::EVT::getScalarType(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::EVT::getVectorNumElements(), and llvm::ISD::INSERT_VECTOR_ELT.
Referenced by LowerVECTOR_SHUFFLE().
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Definition at line 8512 of file ARMISelLowering.cpp.
References DL, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), I, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::ARMISD::VTBL1, and llvm::ARMISD::VTBL2.
Referenced by LowerVECTOR_SHUFFLE().
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Definition at line 9357 of file ARMISelLowering.cpp.
References llvm::ISD::CONCAT_VECTORS, DL, llvm::SelectionDAG::getContext(), llvm::EVT::getHalfNumVectorElementsVT(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarType(), llvm::SelectionDAG::getVTList(), llvm::ARMISD::MVESEXT, llvm::ARMISD::MVEZEXT, N, and llvm::ISD::SIGN_EXTEND.
Referenced by llvm::ARMTargetLowering::LowerOperation(), and llvm::ARMTargetLowering::ReplaceNodeResults().
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Definition at line 5844 of file ARMISelLowering.cpp.
References llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSubtarget(), llvm_unreachable, llvm::ISD::TRUNCATE, and llvm::SelectionDAG::UnrollVectorOp().
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Definition at line 5950 of file ARMISelLowering.cpp.
References assert(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getSubtarget(), llvm::EVT::getVectorElementType(), llvm_unreachable, llvm::ISD::SIGN_EXTEND, llvm::ISD::SINT_TO_FP, llvm::ISD::UINT_TO_FP, llvm::SelectionDAG::UnrollVectorOp(), and llvm::ISD::ZERO_EXTEND.
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Definition at line 6757 of file ARMISelLowering.cpp.
References llvm::ARMCC::AL, llvm::ISD::AND, assert(), llvm::ISD::BITCAST, CC, llvm::EVT::changeVectorElementTypeToInteger(), llvm::ARMCC::EQ, llvm::ARMCC::GE, llvm::SelectionDAG::getCondCode(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNOT(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getSExtOrTrunc(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::ARMCC::GT, llvm::ARMCC::HI, llvm::ARMCC::HS, llvm::ISD::isBuildVectorAllZeros(), llvm::EVT::isFloatingPoint(), llvm::ARMCC::LE, llvm_unreachable, llvm::ARMCC::LT, llvm::ARMCC::NE, llvm::ISD::OR, llvm::ISD::SETCC, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETO, llvm::ISD::SETOEQ, llvm::ISD::SETOGE, llvm::ISD::SETOGT, llvm::ISD::SETOLE, llvm::ISD::SETOLT, llvm::ISD::SETONE, llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, llvm::ISD::SETUNE, llvm::ISD::SETUO, std::swap(), llvm::ARMISD::VCMP, llvm::ARMISD::VCMPZ, llvm::ARMISD::VREV64, and llvm::ARMISD::VTST.
Referenced by combineSetCC(), and llvm::ARMTargetLowering::LowerOperation().
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Definition at line 3435 of file ARMISelLowering.cpp.
References assert(), DL, llvm::SelectionDAG::getNode(), llvm::SDValue::getValueType(), llvm::Hi, llvm::Lo, llvm::SelectionDAG::SplitScalar(), and llvm::ISD::WRITE_REGISTER.
Referenced by llvm::ARMTargetLowering::LowerOperation().
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MatchingStackOffset - Return true if the given stack call argument is already available in the same position (relatively) of the caller's incoming argument stack.
Definition at line 2950 of file ARMISelLowering.cpp.
References assert(), llvm::ISD::CopyFromReg, llvm::FrameIndexSDNode::getIndex(), llvm::MachineFrameInfo::getObjectOffset(), llvm::MachineFrameInfo::getObjectSize(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueSizeInBits(), llvm::MachineFrameInfo::isFixedObjectIndex(), llvm::HexagonInstrInfo::isLoadFromStackSlot(), llvm::Register::isVirtual(), MRI, llvm::Offset, Ptr, and TII.
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Definition at line 11308 of file ARMISelLowering.cpp.
References llvm_unreachable, MBB, and llvm::MachineBasicBlock::successors().
Referenced by llvm::ARMTargetLowering::EmitInstrWithCustomInserter().
Definition at line 14831 of file ARMISelLowering.cpp.
References assert(), llvm::ARMISD::BFI, From, llvm::APInt::getBitWidth(), llvm::APInt::getLimitedValue(), llvm::APInt::getLowBitsSet(), N, llvm::APInt::popcount(), and llvm::ISD::SRL.
Referenced by FindBFIToCombineWith(), and PerformBFICombine().
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Definition at line 13502 of file ARMISelLowering.cpp.
References llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::TargetLowering::expandABS(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::TargetLoweringBase::isOperationLegal(), and N.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
Definition at line 14011 of file ARMISelLowering.cpp.
References llvm::TargetLowering::DAGCombinerInfo::DAG, N, PerformADDCombineWithOperands(), PerformADDVecReduce(), and PerformSHLSimplify().
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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PerformADDCombineWithOperands - Try DAG combinations for an ADD with operands N0 and N1.
This is a helper for PerformADDCombine that is called with the default operands, and if that fails, with commuted operands.
Definition at line 13534 of file ARMISelLowering.cpp.
References AddCombineBUILD_VECTORToVPADDL(), AddCombineToVPADD(), AddCombineVUZPToVPADDL(), combineSelectAndUse(), llvm::SDValue::getNode(), llvm::SDNode::hasOneUse(), and N.
Referenced by PerformADDCombine().
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Definition at line 13124 of file ARMISelLowering.cpp.
References llvm::ARMISD::ADDC, llvm::ARMISD::ADDE, llvm::CallingConv::C, llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::isNullConstant(), llvm::isOneConstant(), llvm::ARMSubtarget::isThumb1Only(), LHS, N, RHS, and llvm::ARMISD::SUBC.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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PerformADDECombine - Target-specific dag combine transform from ARMISD::ADDC, ARMISD::ADDE, and ISD::MUL_LOHI to MLAL or ARMISD::ADDC, ARMISD::ADDE and ARMISD::UMLAL to ARMISD::UMAAL.
Definition at line 13517 of file ARMISelLowering.cpp.
References AddCombineTo64bitUMAAL(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::ARMSubtarget::isThumb1Only(), N, and PerformAddeSubeCombine().
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 13157 of file ARMISelLowering.cpp.
References AddCombineTo64bitMLAL(), llvm::ARMISD::ADDE, llvm::CallingConv::C, llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::ARMSubtarget::isThumb1Only(), N, RHS, llvm::ISD::SMUL_LOHI, and llvm::ARMISD::SUBE.
Referenced by PerformADDECombine(), and llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 13700 of file ARMISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::BUILD_PAIR, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNumOperands(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getResNo(), llvm::SelectionDAG::getVTList(), I, N, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SelectionDAG::SplitScalar(), TryDistrubutionADDVecReduce(), llvm::ARMISD::VADDLVAps, llvm::ARMISD::VADDLVApu, llvm::ARMISD::VADDLVAs, llvm::ARMISD::VADDLVAu, llvm::ARMISD::VADDLVps, llvm::ARMISD::VADDLVpu, llvm::ARMISD::VADDLVs, llvm::ARMISD::VADDLVu, llvm::ARMISD::VMLALVAps, llvm::ARMISD::VMLALVApu, llvm::ARMISD::VMLALVAs, llvm::ARMISD::VMLALVAu, llvm::ARMISD::VMLALVps, llvm::ARMISD::VMLALVpu, llvm::ARMISD::VMLALVs, and llvm::ARMISD::VMLALVu.
Referenced by PerformADDCombine().
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Definition at line 14393 of file ARMISelLowering.cpp.
References llvm::ISD::BITCAST, CombineANDShift(), combineSelectAndUseCommutative(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::APInt::getZExtValue(), llvm::BuildVectorSDNode::isConstantSplat(), llvm::ARMSubtarget::isThumb1Only(), llvm::TargetLoweringBase::isTypeLegal(), isVMOVModifiedImm(), N, llvm::OtherModImm, PerformSHLSimplify(), and llvm::ARMISD::VBICIMM.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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Target-specific dag combine xforms for ARMISD::BUILD_VECTOR.
Definition at line 15284 of file ARMISelLowering.cpp.
References llvm::TargetLowering::DAGCombinerInfo::AddToWorklist(), assert(), llvm::ISD::BITCAST, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), Idx, llvm::ISD::INSERT_VECTOR_ELT, llvm::TargetLoweringBase::isTypeLegal(), llvm::SDValue::isUndef(), and N.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 14891 of file ARMISelLowering.cpp.
References llvm::ISD::AND, assert(), llvm::ARMISD::BFI, llvm::APInt::countl_zero(), llvm::APInt::countr_zero(), llvm::countr_zero(), FindBFIToCombineWith(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::ConstantSDNode::getZExtValue(), llvm::SDValue::hasOneUse(), N, ParseBFI(), and llvm::ISD::SRL.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 18542 of file ARMISelLowering.cpp.
References llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::DataLayout::isBigEndian(), N, PerformExtractEltToVMOVRRD(), llvm::ARMISD::VDUP, llvm::ARMISD::VECTOR_REG_CAST, llvm::ARMISD::VMOVFPIMM, llvm::ARMISD::VMOVIMM, and llvm::ARMISD::VMVNIMM.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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PerformBUILD_VECTORCombine - Target-specific dag combine xforms for ISD::BUILD_VECTOR.
Definition at line 15251 of file ARMISelLowering.cpp.
References llvm::TargetLowering::DAGCombinerInfo::AddToWorklist(), llvm::ISD::BITCAST, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getNode(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), hasNormalLoadOperand(), N, PerformVMOVDRRCombine(), and llvm::SmallVectorTemplateBase< T, bool >::push_back().
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 14999 of file ARMISelLowering.cpp.
References llvm::CallingConv::C, Cond, llvm::ARMCC::EQ, IsCMPZCSINC(), and N.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 15012 of file ARMISelLowering.cpp.
References llvm::CallingConv::C, Cond, llvm::ARMCC::EQ, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::ARMCC::getOppositeCondition(), IsCMPZCSINC(), N, and llvm::ARMCC::NE.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND, ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
Definition at line 17852 of file ARMISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::TargetLoweringBase::isTypeLegal(), llvm_unreachable, N, PerformSplittingToWideningLoad(), llvm::ISD::SIGN_EXTEND, llvm::ARMISD::VGETLANEs, llvm::ARMISD::VGETLANEu, and llvm::ISD::ZERO_EXTEND.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 15555 of file ARMISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, llvm::ARMISD::BUILD_VECTOR, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), Idx, llvm::ARMISD::MVETRUNC, N, llvm::Offset, PerformExtractEltToVMOVRRD(), llvm::ARMISD::VDUP, llvm::ARMISD::VMOVDRR, llvm::ARMISD::VMOVhr, llvm::ARMISD::VMOVrh, and X.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 15494 of file ARMISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::find_if(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDValue::getResNo(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::TargetLowering::DAGCombinerInfo::isAfterLegalizeDAG(), llvm::TargetLoweringBase::isTypeLegal(), N, llvm::ISD::SINT_TO_FP, llvm::ISD::UINT_TO_FP, llvm::SDNode::use_begin(), llvm::SDNode::use_size(), llvm::SDNode::uses(), llvm::ARMISD::VECTOR_REG_CAST, and llvm::ARMISD::VMOVRRD.
Referenced by PerformBITCASTCombine(), and PerformExtractEltCombine().
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Definition at line 16753 of file ARMISelLowering.cpp.
References llvm::CallingConv::C, DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::MemSDNode::getAAInfo(), llvm::StoreSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getContext(), llvm::MachineMemOperand::getFlags(), llvm::EVT::getIntegerVT(), llvm::MemSDNode::getMemOperand(), llvm::SelectionDAG::getNodeIfExists(), llvm::SDNode::getOpcode(), llvm::MemSDNode::getOriginalAlign(), llvm::MemSDNode::getPointerInfo(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTruncStore(), llvm::StoreSDNode::getValue(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVTList(), llvm::MemSDNode::isSimple(), llvm::StoreSDNode::isTruncatingStore(), llvm::LSBaseSDNode::isUnindexed(), and llvm::ARMISD::VGETLANEu.
Referenced by PerformSTORECombine().
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Definition at line 17000 of file ARMISelLowering.cpp.
References N, PerformFADDVCMLACombine(), and PerformFAddVSelectCombine().
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 16969 of file ARMISelLowering.cpp.
References A, B, DL, llvm::ISD::FADD, llvm::SelectionDAG::getNode(), llvm::ISD::INTRINSIC_WO_CHAIN, LHS, N, RHS, and llvm::SDNode::setFlags().
Referenced by PerformFADDCombine().
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Definition at line 16926 of file ARMISelLowering.cpp.
References llvm::ISD::BITCAST, DL, llvm::FAdd, llvm::ISD::FADD, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNodeFlags::hasNoSignedZeros(), N, std::swap(), llvm::ARMISD::VMOVIMM, and llvm::ISD::VSELECT.
Referenced by PerformFADDCombine().
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Definition at line 17895 of file ARMISelLowering.cpp.
References N, and PerformSplittingToWideningLoad().
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 18193 of file ARMISelLowering.cpp.
References assert(), llvm::ISD::BR, llvm::ISD::BR_CC, llvm::ISD::BRCOND, CC, Cond, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::ISD::getSetCCInverse(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getVTList(), Int, llvm::ARMISD::LE, llvm::ARMISD::LOOP_DEC, N, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::SelectionDAG::ReplaceAllUsesWith(), SearchLoopIntrinsic(), llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULT, Size, llvm::ISD::TokenFactor, llvm::ARMISD::WLS, and llvm::ARMISD::WLSSETUP.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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PerformInsertEltCombine - Target-specific dag combine xforms for ISD::INSERT_VECTOR_ELT.
Definition at line 15465 of file ARMISelLowering.cpp.
References llvm::TargetLowering::DAGCombinerInfo::AddToWorklist(), llvm::ISD::BITCAST, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getContext(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::ISD::INSERT_VECTOR_ELT, llvm::ISD::isNormalLoad(), and N.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 15631 of file ARMISelLowering.cpp.
References llvm::ISD::CONCAT_VECTORS, llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::SelectionDAG::getNode(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::EVT::getVectorNumElements(), llvm::Hi, llvm::EVT::isFixedLengthVector(), llvm::TargetLoweringBase::isTypeLegal(), llvm::SDValue::isUndef(), llvm::Lo, and N.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 16517 of file ARMISelLowering.cpp.
References CombineBaseUpdate(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getTargetLoweringInfo(), llvm::ISD::isNormalLoad(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), and N.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 17438 of file ARMISelLowering.cpp.
References llvm::CallingConv::C, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getMergeValues(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::ARMISD::LSLL, llvm::ARMISD::LSRL, Merge, N, and llvm::SelectionDAG::ReplaceAllUsesWith().
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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PerformMinMaxCombine - Target-specific DAG combining for creating truncating saturates.
Definition at line 17947 of file ARMISelLowering.cpp.
References llvm::ISD::AND, DL, llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getUNDEF(), llvm::SelectionDAG::getValueType(), llvm::ISD::isConstantSplatVector(), N, PerformMinMaxToSatCombine(), PerformVQDMULHCombine(), llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SMAX, llvm::ISD::SMIN, std::swap(), llvm::ISD::UMIN, llvm::ARMISD::VECTOR_REG_CAST, llvm::ARMISD::VQMOVNs, and llvm::ARMISD::VQMOVNu.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 17906 of file ARMISelLowering.cpp.
References llvm::APInt::countr_one(), DL, llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandAPInt(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::ARMSubtarget::isThumb2(), llvm::ISD::SMAX, llvm::ISD::SMIN, llvm::ARMISD::SSAT, std::swap(), and llvm::ARMISD::USAT.
Referenced by PerformMinMaxCombine().
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Definition at line 14203 of file ARMISelLowering.cpp.
References llvm::ISD::ADD, llvm::CallingConv::C, llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::EVT::is128BitVector(), llvm::EVT::is64BitVector(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::TargetLowering::DAGCombinerInfo::isCalledByLegalizer(), llvm::ARMSubtarget::isThumb1Only(), llvm::Log2_32(), N, PerformMVEVMULLCombine(), PerformVMULCombine(), llvm::ISD::SHL, and llvm::ISD::SUB.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 16234 of file ARMISelLowering.cpp.
References llvm::ISD::ADD, Addr, llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getMemIntrinsicNode(), llvm::MemSDNode::getMemOperand(), llvm::SDValue::getNode(), llvm::User::getOperand(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getVTList(), llvm::ConstantSDNode::getZExtValue(), llvm::SDNode::hasPredecessorHelper(), llvm::SmallPtrSetImpl< PtrType >::insert(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::TargetLowering::DAGCombinerInfo::isCalledByLegalizer(), llvm_unreachable, N, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::ARMISD::VLD2_UPD, llvm::ARMISD::VLD4_UPD, llvm::ARMISD::VST2_UPD, and llvm::ARMISD::VST4_UPD.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 14138 of file ARMISelLowering.cpp.
References llvm::And, llvm::ISD::AND, llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::isAllOnesConstant(), llvm::ARMSubtarget::isLittle(), llvm::isNullConstant(), N, llvm::ISD::SIGN_EXTEND_INREG, llvm::ARMISD::VECTOR_REG_CAST, llvm::ARMISD::VMULLs, and llvm::ARMISD::VMULLu.
Referenced by PerformMULCombine().
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PerformORCombine - Target-specific dag combine xforms for ISD::OR.
Definition at line 14686 of file ARMISelLowering.cpp.
References llvm::ISD::AND, llvm::ISD::BITCAST, combineSelectAndUseCommutative(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::APInt::getBitWidth(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::APInt::getZExtValue(), llvm::SDValue::hasOneUse(), llvm::EVT::is128BitVector(), llvm::BuildVectorSDNode::isConstantSplat(), llvm::ARMSubtarget::isThumb1Only(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), isVMOVModifiedImm(), N, llvm::OtherModImm, PerformORCombine_i1(), PerformORCombineToBFI(), PerformORCombineToSMULWBT(), PerformSHLSimplify(), llvm::ARMISD::VBSP, and llvm::ARMISD::VORRIMM.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 14660 of file ARMISelLowering.cpp.
References llvm::And, llvm::ISD::AND, CanInvertMVEVCMP(), DL, llvm::SelectionDAG::getLogicalNOT(), llvm::SelectionDAG::getNode(), N, llvm::ARMISD::VCMP, and llvm::ARMISD::VCMPZ.
Referenced by PerformORCombine().
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Definition at line 14503 of file ARMISelLowering.cpp.
References llvm::ISD::AND, llvm::ARMISD::BFI, llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::countr_zero(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::ConstantSDNode::getAPIntValue(), llvm::SDNode::getAsZExtVal(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::ConstantSDNode::getZExtValue(), llvm::ARM::isBitFieldInvertedMask(), llvm::ARMSubtarget::isThumb1Only(), llvm::SelectionDAG::MaskedValueIsZero(), N, llvm::ISD::SHL, and llvm::ISD::SRL.
Referenced by PerformORCombine().
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Definition at line 14443 of file ARMISelLowering.cpp.
References llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), isS16(), isSHL16(), isSRA16(), isSRL16(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ISD::SHL, llvm::ISD::SMUL_LOHI, llvm::ARMISD::SMULWB, llvm::ARMISD::SMULWT, and llvm::ISD::SRL.
Referenced by PerformORCombine().
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Definition at line 15375 of file ARMISelLowering.cpp.
References llvm::CallingConv::C, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getConstant(), llvm::APInt::getLowBitsSet(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::isBitwiseNot(), N, llvm::ARMISD::PREDICATE_CAST, llvm::TargetLowering::SimplifyDemandedBits(), X, and llvm::ISD::XOR.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 17328 of file ARMISelLowering.cpp.
References llvm::SelectionDAG::getNode(), llvm::APInt::isAllOnes(), N, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and llvm::APInt::setBit().
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 13185 of file ARMISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, CC, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), LHS, N, Reduction, RHS, llvm::ISD::SELECT, llvm::ISD::SELECT_CC, llvm::ISD::SETCC, llvm::ISD::SETGT, llvm::ISD::SETLT, llvm::ISD::SETUGT, llvm::ISD::SETULT, std::swap(), llvm::ISD::TRUNCATE, llvm::ISD::VECREDUCE_SMAX, llvm::ISD::VECREDUCE_SMIN, llvm::ISD::VECREDUCE_UMAX, llvm::ISD::VECREDUCE_UMIN, llvm::ARMISD::VMAXVs, llvm::ARMISD::VMAXVu, llvm::ARMISD::VMINVs, and llvm::ARMISD::VMINVu.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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PerformShiftCombine - Checks for immediate versions of vector shifts and lowers them.
As with the vector shift intrinsics, this is done during DAG combining instead of DAG legalizing because the build_vectors for 64-bit vector element shift counts are generally not legal, and it is hard to see their values after they get legalized to loads from a constant pool.
Definition at line 17694 of file ARMISelLowering.cpp.
References llvm::ISD::AND, llvm::countl_zero(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::ConstantSDNode::getZExtValue(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::TargetLowering::DAGCombinerInfo::isCalledByLegalizer(), llvm::isMask_32(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), isVShiftLImm(), isVShiftRImm(), llvm_unreachable, N, llvm::ISD::SHL, llvm::ISD::SRA, llvm::ISD::SRL, llvm::ARMISD::VSHLIMM, llvm::ARMISD::VSHRsIMM, and llvm::ARMISD::VSHRuIMM.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 13903 of file ARMISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::AND, llvm::ARMISD::CMP, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::dbgs(), llvm::SDValue::dump(), llvm::dump(), llvm::APInt::getBitWidth(), llvm::SelectionDAG::getConstant(), llvm::APInt::getHighBitsSet(), llvm::SelectionDAG::getNode(), llvm::APInt::getZExtValue(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), LLVM_DEBUG, llvm::APInt::lshrInPlace(), N, llvm::ISD::OR, llvm::ISD::SETCC, llvm::ISD::SHL, llvm::ISD::SUB, llvm::APInt::uge(), X, and llvm::ISD::XOR.
Referenced by PerformADDCombine(), PerformANDCombine(), PerformORCombine(), and PerformXORCombine().
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Definition at line 15672 of file ARMISelLowering.cpp.
References DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getValueType(), isVMOVNTruncMask(), llvm::ARMISD::MVETRUNC, N, llvm::ARMISD::VECTOR_REG_CAST, and llvm::ARMISD::VMOVN.
Referenced by PerformVECTOR_SHUFFLECombine().
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Definition at line 15616 of file ARMISelLowering.cpp.
References llvm::SelectionDAG::getNode(), N, llvm::ARMISD::VGETLANEs, and llvm::ARMISD::VGETLANEu.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 18682 of file ARMISelLowering.cpp.
References assert(), llvm::CallingConv::C, DL, llvm::ISD::EXTLOAD, llvm::SelectionDAG::getContext(), llvm::TypeSize::getFixed(), llvm::EVT::getIntegerVT(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMergeValues(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getObjectPtrOffset(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getUNDEF(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::SDValue::hasOneUse(), llvm::EVT::isVector(), llvm::ARMISD::MVESEXT, N, llvm::ISD::NON_EXTLOAD, llvm::Offset, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ISD::SEXTLOAD, llvm::ISD::TokenFactor, llvm::ISD::UNINDEXED, and llvm::ISD::ZEXTLOAD.
Referenced by llvm::ARMTargetLowering::PerformMVEExtCombine().
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Definition at line 16711 of file ARMISelLowering.cpp.
References llvm::CallingConv::C, DL, llvm::MemSDNode::getAAInfo(), llvm::StoreSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getContext(), llvm::TypeSize::getFixed(), llvm::MachineMemOperand::getFlags(), llvm::MemSDNode::getMemOperand(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNumOperands(), llvm::SelectionDAG::getObjectPtrOffset(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::MemSDNode::getOriginalAlign(), llvm::MemSDNode::getPointerInfo(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getTruncStore(), llvm::StoreSDNode::getValue(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::MachinePointerInfo::getWithOffset(), llvm::MemSDNode::isSimple(), llvm::StoreSDNode::isTruncatingStore(), llvm::LSBaseSDNode::isUnindexed(), llvm::ARMISD::MVETRUNC, llvm::SmallVectorTemplateBase< T, bool >::push_back(), and llvm::ISD::TokenFactor.
Referenced by PerformSTORECombine().
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Definition at line 16618 of file ARMISelLowering.cpp.
References assert(), llvm::CallingConv::C, DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::FP_ROUND, llvm::MemSDNode::getAAInfo(), llvm::StoreSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::TypeSize::getFixed(), llvm::MachineMemOperand::getFlags(), llvm::EVT::getIntegerVT(), llvm::ShuffleVectorSDNode::getMask(), llvm::MemSDNode::getMemOperand(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getObjectPtrOffset(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::MemSDNode::getOriginalAlign(), llvm::MemSDNode::getPointerInfo(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getTruncStore(), llvm::SelectionDAG::getUNDEF(), llvm::StoreSDNode::getValue(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::MachinePointerInfo::getWithOffset(), I, llvm::MemSDNode::isSimple(), llvm::StoreSDNode::isTruncatingStore(), llvm::SDValue::isUndef(), llvm::LSBaseSDNode::isUnindexed(), llvm::EVT::isVector(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::ISD::TokenFactor, llvm::ARMISD::VCVTN, and llvm::ARMISD::VECTOR_REG_CAST.
Referenced by PerformSTORECombine().
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Definition at line 17771 of file ARMISelLowering.cpp.
References assert(), llvm::CallingConv::C, llvm::ISD::CONCAT_VECTORS, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::TypeSize::getFixed(), llvm::EVT::getIntegerVT(), llvm::SelectionDAG::getLoad(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getObjectPtrOffset(), llvm::SDValue::getOpcode(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getUNDEF(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::SDValue::hasOneUse(), llvm::isPowerOf2_32(), llvm::EVT::isVector(), llvm::ISD::LOAD, N, llvm::ISD::NON_EXTLOAD, llvm::Offset, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ISD::SEXTLOAD, llvm::ISD::SIGN_EXTEND, llvm::SmallVectorBase< Size_T >::size(), llvm::ISD::TokenFactor, llvm::ISD::UNINDEXED, llvm::ARMISD::VCVTL, llvm::ARMISD::VECTOR_REG_CAST, and llvm::ISD::ZEXTLOAD.
Referenced by PerformExtendCombine(), and PerformFPExtendCombine().
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PerformSTORECombine - Target-specific dag combine xforms for ISD::STORE.
Definition at line 16787 of file ARMISelLowering.cpp.
References llvm::ISD::ADD, llvm::TargetLowering::DAGCombinerInfo::AddToWorklist(), llvm::ISD::BITCAST, CombineBaseUpdate(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::MemSDNode::getAAInfo(), llvm::MemSDNode::getAlign(), llvm::StoreSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::MachineMemOperand::getFlags(), llvm::MemSDNode::getMemOperand(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::MemSDNode::getOriginalAlign(), llvm::MemSDNode::getPointerInfo(), llvm::SelectionDAG::getStore(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::StoreSDNode::getValue(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::MachinePointerInfo::getWithOffset(), llvm::SDNode::hasOneUse(), llvm::DataLayout::isBigEndian(), isBigEndian(), llvm::ISD::isNormalStore(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), llvm::MemSDNode::isVolatile(), N, PerformExtractFpToIntStores(), PerformSplittingMVETruncToNarrowingStores(), PerformSplittingToNarrowingStores(), PerformTruncatingStoreCombine(), and llvm::ARMISD::VMOVDRR.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
Definition at line 14054 of file ARMISelLowering.cpp.
References llvm::ISD::BITCAST, combineSelectAndUse(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getConstant(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDNode::hasOneUse(), isZeroVector(), N, PerformSubCSINCCombine(), llvm::ISD::SUB, llvm::ARMISD::VDUP, and llvm::ARMISD::VMOVIMM.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine(), and llvm::LanaiTargetLowering::PerformDAGCombine().
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Definition at line 14034 of file ARMISelLowering.cpp.
References llvm::ARMISD::CSINC, llvm::ARMISD::CSINV, llvm::SelectionDAG::getNode(), llvm::isNullConstant(), N, llvm::ISD::SUB, and X.
Referenced by PerformSUBCombine().
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Definition at line 16533 of file ARMISelLowering.cpp.
References llvm::ISD::ADD, assert(), llvm::ISD::BITCAST, DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::MemSDNode::getAlign(), llvm::StoreSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::MachineMemOperand::getFlags(), llvm::SelectionDAG::getIntPtrConstant(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::SelectionDAG::getNode(), llvm::MemSDNode::getPointerInfo(), llvm::TargetLoweringBase::getPointerTy(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getScalarType(), llvm::EVT::getSizeInBits(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getStore(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getUNDEF(), llvm::StoreSDNode::getValue(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::EVT::getVectorVT(), I, llvm::MVT::integer_valuetypes(), llvm::DataLayout::isBigEndian(), llvm::isPowerOf2_32(), llvm::StoreSDNode::isTruncatingStore(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), and llvm::ISD::TokenFactor.
Referenced by PerformSTORECombine().
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Definition at line 13102 of file ARMISelLowering.cpp.
References llvm::ARMISD::ADDC, llvm::ARMISD::ADDE, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getVTList(), llvm::isNullConstant(), N, and llvm::ARMISD::UMAAL.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 15433 of file ARMISelLowering.cpp.
References Cond, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), getSwappedCondition(), llvm::EVT::isFloatingPoint(), isValidMVECond(), isZeroVector(), N, llvm::ARMISD::VCMP, llvm::ARMISD::VCMPZ, and llvm::ARMISD::VDUP.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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PerformVCVTCombine - VCVT (floating-point to fixed-point, Advanced SIMD) can replace combinations of VMUL and VCVT (floating-point to integer) when the VMUL has a constant operand that is a power of 2.
Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>): vmul.f32 d16, d17, d16 vcvt.s32.f32 d16, d16 becomes: vcvt.s32.f32 d16, d16, #3
Definition at line 16878 of file ARMISelLowering.cpp.
References llvm::CallingConv::C, llvm::ISD::FMUL, llvm::ISD::FP_TO_SINT, llvm::SelectionDAG::getConstant(), llvm::BuildVectorSDNode::getConstantFPSplatPow2ToLog2Int(), llvm::SelectionDAG::getNode(), llvm::MVT::getSizeInBits(), llvm::ISD::INTRINSIC_WO_CHAIN, isSigned(), N, and llvm::ISD::TRUNCATE.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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PerformVDIVCombine - VCVT (fixed-point to floating-point, Advanced SIMD) can replace combinations of VCVT (integer to floating-point) and VDIV when the VDIV has a constant operand that is a power of 2.
Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>): vcvt.f32.s32 d16, d16 vdiv.f32 d16, d17, d16 becomes: vcvt.f32.s32 d16, d16, #3
Definition at line 17018 of file ARMISelLowering.cpp.
References llvm::CallingConv::C, llvm::SelectionDAG::getConstant(), llvm::BuildVectorSDNode::getConstantFPSplatPow2ToLog2Int(), llvm::SelectionDAG::getNode(), llvm::MVT::getSizeInBits(), llvm::ISD::INTRINSIC_WO_CHAIN, isSigned(), N, llvm::ISD::SIGN_EXTEND, llvm::ISD::SINT_TO_FP, llvm::ISD::UINT_TO_FP, and llvm::ISD::ZERO_EXTEND.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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PerformVDUPCombine - Target-specific dag combine xforms for ARMISD::VDUP.
Definition at line 16479 of file ARMISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getValue(), llvm::SelectionDAG::getVTList(), N, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ARMISD::VDUP, llvm::ARMISD::VLD1DUP, and llvm::ARMISD::VMOVrh.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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PerformVDUPLANECombine - Target-specific dag combine xforms for ARMISD::VDUPLANE.
Definition at line 16436 of file ARMISelLowering.cpp.
References llvm::ISD::BITCAST, CombineVLDDUP(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::ARM_AM::decodeVMOVModImm(), llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::EVT::getVectorElementType(), llvm::TargetLoweringBase::isTypeLegal(), N, llvm::ARMISD::VDUP, llvm::ARMISD::VMOVIMM, and llvm::ARMISD::VMVNIMM.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 17068 of file ARMISelLowering.cpp.
References A, llvm::ISD::ADD, llvm::any_of(), assert(), B, llvm::EVT::bitsLE(), llvm::ISD::BUILD_PAIR, llvm::EVT::changeVectorElementType(), llvm::MVT::getIntegerVT(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorMinNumElements(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorNumElements(), llvm::SelectionDAG::getVTList(), llvm::EVT::is128BitVector(), llvm::ISD::isBuildVectorAllZeros(), llvm::Mul, llvm::ISD::MUL, llvm::ARMISD::MVESEXT, llvm::ARMISD::MVEZEXT, N, RetTy, llvm::ISD::SIGN_EXTEND, llvm::ISD::TRUNCATE, llvm::ARMISD::VADDLVps, llvm::ARMISD::VADDLVpu, llvm::ARMISD::VADDLVs, llvm::ARMISD::VADDLVu, llvm::ARMISD::VADDVps, llvm::ARMISD::VADDVpu, llvm::ARMISD::VADDVs, llvm::ARMISD::VADDVu, llvm::ISD::VECREDUCE_ADD, llvm::ARMISD::VMLALVAs, llvm::ARMISD::VMLALVAu, llvm::ARMISD::VMLALVps, llvm::ARMISD::VMLALVpu, llvm::ARMISD::VMLALVs, llvm::ARMISD::VMLALVu, llvm::ARMISD::VMLAVps, llvm::ARMISD::VMLAVpu, llvm::ARMISD::VMLAVs, llvm::ARMISD::VMLAVu, llvm::ISD::VSELECT, and llvm::ISD::ZERO_EXTEND.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 15408 of file ARMISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getUNDEF(), N, and llvm::ARMISD::VECTOR_REG_CAST.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for ISD::VECTOR_SHUFFLE.
Definition at line 15697 of file ARMISelLowering.cpp.
References llvm::ISD::CONCAT_VECTORS, llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVectorShuffle(), llvm::TargetLoweringBase::isTypeLegal(), llvm::SDValue::isUndef(), N, PerformShuffleVMOVNCombine(), and llvm::SmallVectorTemplateBase< T, bool >::push_back().
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 16226 of file ARMISelLowering.cpp.
References CombineBaseUpdate(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::TargetLowering::DAGCombinerInfo::isCalledByLegalizer(), and N.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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PerformVMOVDRRCombine - Target-specific dag combine xforms for ARMISD::VMOVDRR.
This is also used for BUILD_VECTORs with 2 operands.
Definition at line 15126 of file ARMISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDValue::getResNo(), N, and llvm::ARMISD::VMOVRRD.
Referenced by PerformBUILD_VECTORCombine(), and llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 15142 of file ARMISelLowering.cpp.
References llvm::ISD::BITCAST, llvm::ISD::CopyFromReg, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getLoad(), llvm::APInt::getLowBitsSet(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDValue::getValue(), llvm::SelectionDAG::getVTList(), N, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::TargetLowering::SimplifyDemandedBits(), and llvm::ARMISD::VMOVrh.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 17361 of file ARMISelLowering.cpp.
References llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SDNode::getConstantOperandVal(), llvm::APInt::getHighBitsSet(), llvm::APInt::getLowBitsSet(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::APInt::getSplat(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDNode::isUndef(), N, llvm::TargetLowering::SimplifyDemandedVectorElts(), llvm::ARMISD::VQMOVNs, and llvm::ARMISD::VQMOVNu.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 15204 of file ARMISelLowering.cpp.
References llvm::CallingConv::C, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::LoadSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getExtLoad(), llvm::MemSDNode::getMemOperand(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SDValue::getValue(), llvm::SDValue::hasOneUse(), llvm::ISD::isNormalLoad(), N, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ARMISD::VGETLANEu, and llvm::ISD::ZEXTLOAD.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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PerformVMOVRRDCombine - Target-specific dag combine xforms for ARMISD::VMOVRRD.
Definition at line 15034 of file ARMISelLowering.cpp.
References llvm::ISD::ADD, llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::commonAlignment(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::ISD::FrameIndex, llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getLoad(), llvm::SelectionDAG::getMergeValues(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::SDNode::hasOneUse(), llvm::ISD::INSERT_VECTOR_ELT, llvm::DataLayout::isBigEndian(), llvm::ARMSubtarget::isLittle(), llvm::ISD::isNormalLoad(), N, llvm::Offset, llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), std::swap(), llvm::ARMISD::VECTOR_REG_CAST, and llvm::ARMISD::VMOVDRR.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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PerformVMULCombine Distribute (A + B) * C to (A * C) + (B * C) to take advantage of the special multiplier accumulator forwarding.
vmul d3, d0, d2 vmla d3, d1, d2 is faster than vadd d3, d0, d1 vmul d3, d3, d2
Definition at line 14107 of file ARMISelLowering.cpp.
References llvm::ISD::ADD, llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::ISD::FADD, llvm::ISD::FSUB, llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::ISD::MUL, N, llvm::ISD::SUB, and std::swap().
Referenced by PerformMULCombine().
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Definition at line 13296 of file ARMISelLowering.cpp.
References llvm::ISD::ANY_EXTEND, assert(), llvm::ISD::CONCAT_VECTORS, DL, llvm::ISD::EXTRACT_SUBVECTOR, llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::MVT::getScalarSizeInBits(), llvm::EVT::getScalarType(), llvm::ConstantSDNode::getSExtValue(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVectorIdxConstant(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorVT(), I, llvm::isConstOrConstSplat(), llvm::EVT::isPow2VectorType(), llvm::EVT::isVector(), llvm::Mul, llvm::ISD::MUL, N, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::ISD::SETCC, llvm::ISD::SETLT, llvm::ISD::SIGN_EXTEND, llvm::ISD::SMIN, llvm::ISD::SRA, llvm::ISD::TRUNCATE, llvm::ARMISD::VECTOR_REG_CAST, llvm::ARMISD::VQDMULH, and llvm::ISD::VSELECT.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine(), PerformMinMaxCombine(), and PerformVSELECTCombine().
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Definition at line 17417 of file ARMISelLowering.cpp.
References llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getVectorShuffle(), llvm::Value::hasOneUse(), LHS, N, and RHS.
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Definition at line 17401 of file ARMISelLowering.cpp.
References llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::APInt::getHighBitsSet(), llvm::APInt::getLowBitsSet(), llvm::APInt::getSplat(), llvm::SelectionDAG::getTargetLoweringInfo(), N, and llvm::TargetLowering::SimplifyDemandedVectorElts().
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 13404 of file ARMISelLowering.cpp.
References Cond, llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::SelectionDAG::getNode(), llvm::isConstOrConstSplat(), LHS, N, PerformVQDMULHCombine(), RHS, llvm::ISD::VSELECT, and llvm::ISD::XOR.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 13444 of file ARMISelLowering.cpp.
References llvm::ISD::BUILD_VECTOR, CC, llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SelectionDAG::getSplatValue(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getZExtOrTrunc(), I, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::TargetLoweringBase::isTypeLegal(), llvm::SDValue::isUndef(), N, llvm::ISD::SETUGE, llvm::ISD::SETULT, and std::swap().
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 14786 of file ARMISelLowering.cpp.
References CanInvertMVEVCMP(), CC, combineSelectAndUseCommutative(), llvm::TargetLowering::DAGCombinerInfo::DAG, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::ARMCC::getOppositeCondition(), llvm::ARMSubtarget::getTargetLowering(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::SDNode::getValueType(), getVCMPCondCode(), llvm::TargetLowering::isConstTrueVal(), llvm::ARMSubtarget::isThumb1Only(), llvm::TargetLoweringBase::isTypeLegal(), N, PerformSHLSimplify(), llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::ARMISD::VCMP, and llvm::ARMISD::VCMPZ.
Referenced by llvm::ARMTargetLowering::PerformDAGCombine().
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Definition at line 8566 of file ARMISelLowering.cpp.
References llvm::AllOnes, llvm::ISD::BITCAST, llvm::ARM_AM::createVMOVModImm(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), getVectorTyFromPredicateVector(), llvm::ARMISD::PREDICATE_CAST, llvm::ARMISD::VMOVIMM, and llvm::ISD::VSELECT.
Referenced by LowerCONCAT_VECTORS_i1(), LowerEXTRACT_SUBVECTOR(), and LowerVECTOR_SHUFFLE_i1().
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Definition at line 3799 of file ARMISelLowering.cpp.
References allUsersAreInFunction(), llvm::StringRef::bytes_begin(), llvm::StringRef::bytes_end(), ConstpoolPromotionMaxSize, ConstpoolPromotionMaxTotal, llvm::ARMConstantPoolConstant::Create(), EnableConstpoolPromotion, llvm::TargetOptions::EnableFastISel, F, llvm::ConstantDataArray::get(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::MachineFunction::getFunction(), llvm::ARMFunctionInfo::getGlobalsPromotedToConstantPool(), llvm::MachineFunction::getInfo(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getNode(), llvm::DataLayout::getPreferredAlign(), llvm::ARMFunctionInfo::getPromotedConstpoolIncrease(), llvm::ARMTargetLowering::getSubtarget(), llvm::MachineFunction::getTarget(), llvm::SelectionDAG::getTargetConstantPool(), llvm::DataLayout::getTypeAllocSize(), llvm::TargetLowering::isPositionIndependent(), llvm::ARMSubtarget::isROPI(), llvm::ARMFunctionInfo::markGlobalAsPromotedToConstantPool(), llvm::TargetMachine::Options, llvm::ARMFunctionInfo::setPromotedConstpoolIncrease(), llvm::StringRef::size(), Size, and llvm::ARMISD::Wrapper.
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Definition at line 10462 of file ARMISelLowering.cpp.
References assert(), llvm::ISD::BUILD_PAIR, createGPRPairNode(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetExtractSubreg(), llvm::SelectionDAG::getVTList(), llvm::Hi, llvm::DataLayout::isBigEndian(), isBigEndian(), llvm::Lo, N, Results, and llvm::SelectionDAG::setNodeMemRefs().
Referenced by llvm::ARMTargetLowering::ReplaceNodeResults().
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Definition at line 10673 of file ARMISelLowering.cpp.
References llvm::ISD::BUILD_PAIR, llvm::SelectionDAG::getNode(), llvm::SDValue::getValue(), llvm::SelectionDAG::getVTList(), llvm::Hi, llvm::Lo, N, Results, llvm::ARMISD::SMLALD, llvm::ARMISD::SMLALDX, llvm::ARMISD::SMLSLD, llvm::ARMISD::SMLSLDX, and llvm::SelectionDAG::SplitScalar().
Referenced by llvm::ARMTargetLowering::ReplaceNodeResults().
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Definition at line 10424 of file ARMISelLowering.cpp.
References llvm::ISD::BUILD_PAIR, DL, llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::getValue(), llvm::SelectionDAG::getVTList(), llvm::ISD::INTRINSIC_W_CHAIN, N, and Results.
Referenced by llvm::ARMTargetLowering::ReplaceNodeResults().
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Definition at line 18156 of file ARMISelLowering.cpp.
References CC, llvm::ISD::INTRINSIC_W_CHAIN, N, SearchLoopIntrinsic(), llvm::ISD::SETCC, and llvm::ISD::XOR.
Referenced by PerformHWLoopCombine(), and SearchLoopIntrinsic().
Definition at line 7305 of file ARMISelLowering.cpp.
Referenced by isVTRN_v_undef_Mask(), isVTRNMask(), isVUZP_v_undef_Mask(), isVUZPMask(), isVZIP_v_undef_Mask(), and isVZIPMask().
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SkipExtensionForVMULL - For a node that is a SIGN_EXTEND, ZERO_EXTEND, ANY_EXTEND, extending load, or BUILD_VECTOR with extended elements, return the unextended value.
The unextended vector should be 64 bits so that it can be used as an operand to a VMULL instruction. If the original vector size before extension is less than 64 bits we add a an extension to resize the vector to 64 bits.
Definition at line 9531 of file ARMISelLowering.cpp.
References AddRequiredExtensionForVMULL(), llvm::ISD::ANY_EXTEND, assert(), llvm::ISD::BITCAST, llvm::ISD::BUILD_VECTOR, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getDataLayout(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getScalarSizeInBits(), llvm::SDValue::getValue(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::DataLayout::isBigEndian(), llvm::ISD::isSEXTLoad(), llvm::ISD::isZEXTLoad(), N, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ISD::SIGN_EXTEND, SkipLoadExtensionForVMULL(), llvm::ISD::ZERO_EXTEND, and llvm::APInt::zextOrTrunc().
Referenced by LowerMUL().
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SkipLoadExtensionForVMULL - return a load of the original vector size that does not do any sign/zero extension.
If the original vector is less than 64 bits, an appropriate extension will be added after the load to reach a total size of 64 bits. We have to add the extension separately because ARM does not have a sign/zero extending load for vectors.
Definition at line 9507 of file ARMISelLowering.cpp.
References getExtensionTo64Bits(), llvm::SelectionDAG::getExtLoad(), and llvm::SelectionDAG::getLoad().
Referenced by SkipExtensionForVMULL().
STATISTIC | ( | NumConstpoolPromoted | , |
"Number of constants with their storage promoted into constant pools" | |||
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STATISTIC | ( | NumMovwMovt | , |
"Number of GAs materialized with movw + movt" | |||
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STATISTIC | ( | NumTailCalls | , |
"Number of tail calls" | |||
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Definition at line 15768 of file ARMISelLowering.cpp.
References assert(), llvm::ISD::BITCAST, llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::MemSDNode::getAlign(), llvm::SelectionDAG::getConstant(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::MemSDNode::getMemOperand(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::EVT::getScalarSizeInBits(), llvm::EVT::getSizeInBits(), llvm::MVT::getSizeInBits(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::MVT::getVectorVT(), llvm::SelectionDAG::getVTList(), llvm_unreachable, llvm::ISD::LOAD, N, llvm::SmallVectorTemplateBase< T, bool >::push_back(), llvm::SmallVectorBase< Size_T >::size(), llvm::ISD::STORE, llvm::Align::value(), llvm::ARMISD::VLD1_UPD, llvm::ARMISD::VLD1DUP, llvm::ARMISD::VLD1DUP_UPD, llvm::ARMISD::VLD1x2_UPD, llvm::ARMISD::VLD1x3_UPD, llvm::ARMISD::VLD1x4_UPD, llvm::ARMISD::VLD2_UPD, llvm::ARMISD::VLD2DUP, llvm::ARMISD::VLD2DUP_UPD, llvm::ARMISD::VLD2LN_UPD, llvm::ARMISD::VLD3_UPD, llvm::ARMISD::VLD3DUP, llvm::ARMISD::VLD3DUP_UPD, llvm::ARMISD::VLD3LN_UPD, llvm::ARMISD::VLD4_UPD, llvm::ARMISD::VLD4DUP, llvm::ARMISD::VLD4DUP_UPD, llvm::ARMISD::VLD4LN_UPD, llvm::ARMISD::VST1_UPD, llvm::ARMISD::VST1x2_UPD, llvm::ARMISD::VST1x3_UPD, llvm::ARMISD::VST1x4_UPD, llvm::ARMISD::VST2_UPD, llvm::ARMISD::VST2LN_UPD, llvm::ARMISD::VST3_UPD, llvm::ARMISD::VST3LN_UPD, llvm::ARMISD::VST4_UPD, and llvm::ARMISD::VST4LN_UPD.
Referenced by CombineBaseUpdate().
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Definition at line 13555 of file ARMISelLowering.cpp.
References llvm::ISD::ADD, llvm::MemSDNode::getChain(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::hasOneUse(), llvm::LSBaseSDNode::isIndexed(), llvm::MemSDNode::isSimple(), llvm::BaseIndexOffset::match(), llvm::ISD::MUL, N, llvm::ARMISD::VADDVs, llvm::ARMISD::VADDVu, llvm::ISD::VECREDUCE_ADD, llvm::ARMISD::VMLAVs, llvm::ARMISD::VMLAVu, and X.
Referenced by PerformADDVecReduce().
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Definition at line 10072 of file ARMISelLowering.cpp.
References DL, llvm::SelectionDAG::getNode(), llvm::Hi, llvm::Lo, N, llvm::ISD::OR, llvm::SelectionDAG::SplitScalar(), and llvm::ARMISD::WIN__DBZCHK.
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Referenced by promoteToConstantPool().
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Referenced by promoteToConstantPool().
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Referenced by promoteToConstantPool().
Definition at line 155 of file ARMISelLowering.cpp.
cl::opt< unsigned > MVEMaxSupportedInterleaveFactor("mve-max-interleave-factor", cl::Hidden, cl::desc("Maximum interleave factor for MVE VLDn to generate."), cl::init(2)) | ( | "mve-max-interleave-factor" | , |
cl::Hidden | , | ||
cl::desc("Maximum interleave factor for MVE VLDn to generate.") | , | ||
cl::init(2) | |||
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Referenced by canTailPredicateLoop(), and llvm::ARMTargetLowering::getMaxSupportedInterleaveFactor().