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ARMJITInfo.cpp
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00001 //===-- ARMJITInfo.cpp - Implement the JIT interfaces for the ARM target --===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file implements the JIT interfaces for the ARM target.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #include "ARMJITInfo.h"
00015 #include "ARMConstantPoolValue.h"
00016 #include "ARMRelocations.h"
00017 #include "MCTargetDesc/ARMBaseInfo.h"
00018 #include "llvm/CodeGen/JITCodeEmitter.h"
00019 #include "llvm/IR/Function.h"
00020 #include "llvm/Support/Debug.h"
00021 #include "llvm/Support/ErrorHandling.h"
00022 #include "llvm/Support/Memory.h"
00023 #include "llvm/Support/raw_ostream.h"
00024 #include <cstdlib>
00025 using namespace llvm;
00026 
00027 #define DEBUG_TYPE "jit"
00028 
00029 void ARMJITInfo::replaceMachineCodeForFunction(void *Old, void *New) {
00030   report_fatal_error("ARMJITInfo::replaceMachineCodeForFunction");
00031 }
00032 
00033 /// JITCompilerFunction - This contains the address of the JIT function used to
00034 /// compile a function lazily.
00035 static TargetJITInfo::JITCompilerFn JITCompilerFunction;
00036 
00037 // Get the ASMPREFIX for the current host.  This is often '_'.
00038 #ifndef __USER_LABEL_PREFIX__
00039 #define __USER_LABEL_PREFIX__
00040 #endif
00041 #define GETASMPREFIX2(X) #X
00042 #define GETASMPREFIX(X) GETASMPREFIX2(X)
00043 #define ASMPREFIX GETASMPREFIX(__USER_LABEL_PREFIX__)
00044 
00045 // CompilationCallback stub - We can't use a C function with inline assembly in
00046 // it, because the prolog/epilog inserted by GCC won't work for us. (We need
00047 // to preserve more context and manipulate the stack directly).  Instead,
00048 // write our own wrapper, which does things our way, so we have complete
00049 // control over register saving and restoring.
00050 extern "C" {
00051 #if defined(__arm__)
00052   void ARMCompilationCallback();
00053   asm(
00054     ".text\n"
00055     ".align 2\n"
00056     ".globl " ASMPREFIX "ARMCompilationCallback\n"
00057     ASMPREFIX "ARMCompilationCallback:\n"
00058     // Save caller saved registers since they may contain stuff
00059     // for the real target function right now. We have to act as if this
00060     // whole compilation callback doesn't exist as far as the caller is
00061     // concerned, so we can't just preserve the callee saved regs.
00062     "stmdb sp!, {r0, r1, r2, r3, lr}\n"
00063 #if (defined(__VFP_FP__) && !defined(__SOFTFP__))
00064     "vstmdb sp!, {d0, d1, d2, d3, d4, d5, d6, d7}\n"
00065 #endif
00066     // The LR contains the address of the stub function on entry.
00067     // pass it as the argument to the C part of the callback
00068     "mov  r0, lr\n"
00069     "sub  sp, sp, #4\n"
00070     // Call the C portion of the callback
00071     "bl   " ASMPREFIX "ARMCompilationCallbackC\n"
00072     "add  sp, sp, #4\n"
00073     // Restoring the LR to the return address of the function that invoked
00074     // the stub and de-allocating the stack space for it requires us to
00075     // swap the two saved LR values on the stack, as they're backwards
00076     // for what we need since the pop instruction has a pre-determined
00077     // order for the registers.
00078     //      +--------+
00079     //   0  | LR     | Original return address
00080     //      +--------+
00081     //   1  | LR     | Stub address (start of stub)
00082     // 2-5  | R3..R0 | Saved registers (we need to preserve all regs)
00083     // 6-20 | D0..D7 | Saved VFP registers
00084     //      +--------+
00085     //
00086 #if (defined(__VFP_FP__) && !defined(__SOFTFP__))
00087     // Restore VFP caller-saved registers.
00088     "vldmia sp!, {d0, d1, d2, d3, d4, d5, d6, d7}\n"
00089 #endif
00090     //
00091     //      We need to exchange the values in slots 0 and 1 so we can
00092     //      return to the address in slot 1 with the address in slot 0
00093     //      restored to the LR.
00094     "ldr  r0, [sp,#20]\n"
00095     "ldr  r1, [sp,#16]\n"
00096     "str  r1, [sp,#20]\n"
00097     "str  r0, [sp,#16]\n"
00098     // Return to the (newly modified) stub to invoke the real function.
00099     // The above twiddling of the saved return addresses allows us to
00100     // deallocate everything, including the LR the stub saved, with two
00101     // updating load instructions.
00102     "ldmia  sp!, {r0, r1, r2, r3, lr}\n"
00103     "ldr    pc, [sp], #4\n"
00104       );
00105 #else  // Not an ARM host
00106   void ARMCompilationCallback() {
00107     llvm_unreachable("Cannot call ARMCompilationCallback() on a non-ARM arch!");
00108   }
00109 #endif
00110 }
00111 
00112 /// ARMCompilationCallbackC - This is the target-specific function invoked
00113 /// by the function stub when we did not know the real target of a call.
00114 /// This function must locate the start of the stub or call site and pass
00115 /// it into the JIT compiler function.
00116 extern "C" void ARMCompilationCallbackC(intptr_t StubAddr) {
00117   // Get the address of the compiled code for this function.
00118   intptr_t NewVal = (intptr_t)JITCompilerFunction((void*)StubAddr);
00119 
00120   // Rewrite the call target... so that we don't end up here every time we
00121   // execute the call. We're replacing the first two instructions of the
00122   // stub with:
00123   //   ldr pc, [pc,#-4]
00124   //   <addr>
00125   if (!sys::Memory::setRangeWritable((void*)StubAddr, 8)) {
00126     llvm_unreachable("ERROR: Unable to mark stub writable");
00127   }
00128   *(intptr_t *)StubAddr = 0xe51ff004;  // ldr pc, [pc, #-4]
00129   *(intptr_t *)(StubAddr+4) = NewVal;
00130   if (!sys::Memory::setRangeExecutable((void*)StubAddr, 8)) {
00131     llvm_unreachable("ERROR: Unable to mark stub executable");
00132   }
00133 }
00134 
00135 TargetJITInfo::LazyResolverFn
00136 ARMJITInfo::getLazyResolverFunction(JITCompilerFn F) {
00137   JITCompilerFunction = F;
00138   return ARMCompilationCallback;
00139 }
00140 
00141 void *ARMJITInfo::emitGlobalValueIndirectSym(const GlobalValue *GV, void *Ptr,
00142                                              JITCodeEmitter &JCE) {
00143   uint8_t Buffer[4];
00144   uint8_t *Cur = Buffer;
00145   MachineCodeEmitter::emitWordLEInto(Cur, (intptr_t)Ptr);
00146   void *PtrAddr = JCE.allocIndirectGV(
00147       GV, Buffer, sizeof(Buffer), /*Alignment=*/4);
00148   addIndirectSymAddr(Ptr, (intptr_t)PtrAddr);
00149   return PtrAddr;
00150 }
00151 
00152 TargetJITInfo::StubLayout ARMJITInfo::getStubLayout() {
00153   // The stub contains up to 3 4-byte instructions, aligned at 4 bytes, and a
00154   // 4-byte address.  See emitFunctionStub for details.
00155   StubLayout Result = {16, 4};
00156   return Result;
00157 }
00158 
00159 void *ARMJITInfo::emitFunctionStub(const Function* F, void *Fn,
00160                                    JITCodeEmitter &JCE) {
00161   void *Addr;
00162   // If this is just a call to an external function, emit a branch instead of a
00163   // call.  The code is the same except for one bit of the last instruction.
00164   if (Fn != (void*)(intptr_t)ARMCompilationCallback) {
00165     // Branch to the corresponding function addr.
00166     if (IsPIC) {
00167       // The stub is 16-byte size and 4-aligned.
00168       intptr_t LazyPtr = getIndirectSymAddr(Fn);
00169       if (!LazyPtr) {
00170         // In PIC mode, the function stub is loading a lazy-ptr.
00171         LazyPtr= (intptr_t)emitGlobalValueIndirectSym((const GlobalValue*)F, Fn, JCE);
00172         DEBUG(if (F)
00173                 errs() << "JIT: Indirect symbol emitted at [" << LazyPtr
00174                        << "] for GV '" << F->getName() << "'\n";
00175               else
00176                 errs() << "JIT: Stub emitted at [" << LazyPtr
00177                        << "] for external function at '" << Fn << "'\n");
00178       }
00179       JCE.emitAlignment(4);
00180       Addr = (void*)JCE.getCurrentPCValue();
00181       if (!sys::Memory::setRangeWritable(Addr, 16)) {
00182         llvm_unreachable("ERROR: Unable to mark stub writable");
00183       }
00184       JCE.emitWordLE(0xe59fc004);            // ldr ip, [pc, #+4]
00185       JCE.emitWordLE(0xe08fc00c);            // L_func$scv: add ip, pc, ip
00186       JCE.emitWordLE(0xe59cf000);            // ldr pc, [ip]
00187       JCE.emitWordLE(LazyPtr - (intptr_t(Addr)+4+8));  // func - (L_func$scv+8)
00188       sys::Memory::InvalidateInstructionCache(Addr, 16);
00189       if (!sys::Memory::setRangeExecutable(Addr, 16)) {
00190         llvm_unreachable("ERROR: Unable to mark stub executable");
00191       }
00192     } else {
00193       // The stub is 8-byte size and 4-aligned.
00194       JCE.emitAlignment(4);
00195       Addr = (void*)JCE.getCurrentPCValue();
00196       if (!sys::Memory::setRangeWritable(Addr, 8)) {
00197         llvm_unreachable("ERROR: Unable to mark stub writable");
00198       }
00199       JCE.emitWordLE(0xe51ff004);    // ldr pc, [pc, #-4]
00200       JCE.emitWordLE((intptr_t)Fn);  // addr of function
00201       sys::Memory::InvalidateInstructionCache(Addr, 8);
00202       if (!sys::Memory::setRangeExecutable(Addr, 8)) {
00203         llvm_unreachable("ERROR: Unable to mark stub executable");
00204       }
00205     }
00206   } else {
00207     // The compilation callback will overwrite the first two words of this
00208     // stub with indirect branch instructions targeting the compiled code.
00209     // This stub sets the return address to restart the stub, so that
00210     // the new branch will be invoked when we come back.
00211     //
00212     // Branch and link to the compilation callback.
00213     // The stub is 16-byte size and 4-byte aligned.
00214     JCE.emitAlignment(4);
00215     Addr = (void*)JCE.getCurrentPCValue();
00216     if (!sys::Memory::setRangeWritable(Addr, 16)) {
00217       llvm_unreachable("ERROR: Unable to mark stub writable");
00218     }
00219     // Save LR so the callback can determine which stub called it.
00220     // The compilation callback is responsible for popping this prior
00221     // to returning.
00222     JCE.emitWordLE(0xe92d4000); // push {lr}
00223     // Set the return address to go back to the start of this stub.
00224     JCE.emitWordLE(0xe24fe00c); // sub lr, pc, #12
00225     // Invoke the compilation callback.
00226     JCE.emitWordLE(0xe51ff004); // ldr pc, [pc, #-4]
00227     // The address of the compilation callback.
00228     JCE.emitWordLE((intptr_t)ARMCompilationCallback);
00229     sys::Memory::InvalidateInstructionCache(Addr, 16);
00230     if (!sys::Memory::setRangeExecutable(Addr, 16)) {
00231       llvm_unreachable("ERROR: Unable to mark stub executable");
00232     }
00233   }
00234 
00235   return Addr;
00236 }
00237 
00238 intptr_t ARMJITInfo::resolveRelocDestAddr(MachineRelocation *MR) const {
00239   ARM::RelocationType RT = (ARM::RelocationType)MR->getRelocationType();
00240   switch (RT) {
00241   default:
00242     return (intptr_t)(MR->getResultPointer());
00243   case ARM::reloc_arm_pic_jt:
00244     // Destination address - jump table base.
00245     return (intptr_t)(MR->getResultPointer()) - MR->getConstantVal();
00246   case ARM::reloc_arm_jt_base:
00247     // Jump table base address.
00248     return getJumpTableBaseAddr(MR->getJumpTableIndex());
00249   case ARM::reloc_arm_cp_entry:
00250   case ARM::reloc_arm_vfp_cp_entry:
00251     // Constant pool entry address.
00252     return getConstantPoolEntryAddr(MR->getConstantPoolIndex());
00253   case ARM::reloc_arm_machine_cp_entry: {
00254     ARMConstantPoolValue *ACPV = (ARMConstantPoolValue*)MR->getConstantVal();
00255     assert((!ACPV->hasModifier() && !ACPV->mustAddCurrentAddress()) &&
00256            "Can't handle this machine constant pool entry yet!");
00257     intptr_t Addr = (intptr_t)(MR->getResultPointer());
00258     Addr -= getPCLabelAddr(ACPV->getLabelId()) + ACPV->getPCAdjustment();
00259     return Addr;
00260   }
00261   }
00262 }
00263 
00264 /// relocate - Before the JIT can run a block of code that has been emitted,
00265 /// it must rewrite the code to contain the actual addresses of any
00266 /// referenced global symbols.
00267 void ARMJITInfo::relocate(void *Function, MachineRelocation *MR,
00268                           unsigned NumRelocs, unsigned char* GOTBase) {
00269   for (unsigned i = 0; i != NumRelocs; ++i, ++MR) {
00270     void *RelocPos = (char*)Function + MR->getMachineCodeOffset();
00271     intptr_t ResultPtr = resolveRelocDestAddr(MR);
00272     switch ((ARM::RelocationType)MR->getRelocationType()) {
00273     case ARM::reloc_arm_cp_entry:
00274     case ARM::reloc_arm_vfp_cp_entry:
00275     case ARM::reloc_arm_relative: {
00276       // It is necessary to calculate the correct PC relative value. We
00277       // subtract the base addr from the target addr to form a byte offset.
00278       ResultPtr = ResultPtr - (intptr_t)RelocPos - 8;
00279       // If the result is positive, set bit U(23) to 1.
00280       if (ResultPtr >= 0)
00281         *((intptr_t*)RelocPos) |= 1 << ARMII::U_BitShift;
00282       else {
00283         // Otherwise, obtain the absolute value and set bit U(23) to 0.
00284         *((intptr_t*)RelocPos) &= ~(1 << ARMII::U_BitShift);
00285         ResultPtr = - ResultPtr;
00286       }
00287       // Set the immed value calculated.
00288       // VFP immediate offset is multiplied by 4.
00289       if (MR->getRelocationType() == ARM::reloc_arm_vfp_cp_entry)
00290         ResultPtr = ResultPtr >> 2;
00291       *((intptr_t*)RelocPos) |= ResultPtr;
00292       // Set register Rn to PC (which is register 15 on all architectures).
00293       // FIXME: This avoids the need for register info in the JIT class.
00294       *((intptr_t*)RelocPos) |= 15 << ARMII::RegRnShift;
00295       break;
00296     }
00297     case ARM::reloc_arm_pic_jt:
00298     case ARM::reloc_arm_machine_cp_entry:
00299     case ARM::reloc_arm_absolute: {
00300       // These addresses have already been resolved.
00301       *((intptr_t*)RelocPos) |= (intptr_t)ResultPtr;
00302       break;
00303     }
00304     case ARM::reloc_arm_branch: {
00305       // It is necessary to calculate the correct value of signed_immed_24
00306       // field. We subtract the base addr from the target addr to form a
00307       // byte offset, which must be inside the range -33554432 and +33554428.
00308       // Then, we set the signed_immed_24 field of the instruction to bits
00309       // [25:2] of the byte offset. More details ARM-ARM p. A4-11.
00310       ResultPtr = ResultPtr - (intptr_t)RelocPos - 8;
00311       ResultPtr = (ResultPtr & 0x03FFFFFC) >> 2;
00312       assert(ResultPtr >= -33554432 && ResultPtr <= 33554428);
00313       *((intptr_t*)RelocPos) |= ResultPtr;
00314       break;
00315     }
00316     case ARM::reloc_arm_jt_base: {
00317       // JT base - (instruction addr + 8)
00318       ResultPtr = ResultPtr - (intptr_t)RelocPos - 8;
00319       *((intptr_t*)RelocPos) |= ResultPtr;
00320       break;
00321     }
00322     case ARM::reloc_arm_movw: {
00323       ResultPtr = ResultPtr & 0xFFFF;
00324       *((intptr_t*)RelocPos) |= ResultPtr & 0xFFF;
00325       *((intptr_t*)RelocPos) |= ((ResultPtr >> 12) & 0xF) << 16;
00326       break;
00327     }
00328     case ARM::reloc_arm_movt: {
00329       ResultPtr = (ResultPtr >> 16) & 0xFFFF;
00330       *((intptr_t*)RelocPos) |= ResultPtr & 0xFFF;
00331       *((intptr_t*)RelocPos) |= ((ResultPtr >> 12) & 0xF) << 16;
00332       break;
00333     }
00334     }
00335   }
00336 }