LLVM API Documentation

FunctionLoweringInfo.h
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00001 //===-- FunctionLoweringInfo.h - Lower functions from LLVM IR to CodeGen --===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This implements routines for translating functions from LLVM IR into
00011 // Machine IR.
00012 //
00013 //===----------------------------------------------------------------------===//
00014 
00015 #ifndef LLVM_CODEGEN_FUNCTIONLOWERINGINFO_H
00016 #define LLVM_CODEGEN_FUNCTIONLOWERINGINFO_H
00017 
00018 #include "llvm/ADT/APInt.h"
00019 #include "llvm/ADT/DenseMap.h"
00020 #include "llvm/ADT/IndexedMap.h"
00021 #include "llvm/ADT/SmallPtrSet.h"
00022 #include "llvm/ADT/SmallVector.h"
00023 #include "llvm/CodeGen/MachineBasicBlock.h"
00024 #include "llvm/CodeGen/ISDOpcodes.h"
00025 #include "llvm/IR/InlineAsm.h"
00026 #include "llvm/IR/Instructions.h"
00027 #include "llvm/Target/TargetRegisterInfo.h"
00028 #include <vector>
00029 
00030 namespace llvm {
00031 
00032 class AllocaInst;
00033 class BasicBlock;
00034 class BranchProbabilityInfo;
00035 class CallInst;
00036 class Function;
00037 class GlobalVariable;
00038 class Instruction;
00039 class MachineInstr;
00040 class MachineBasicBlock;
00041 class MachineFunction;
00042 class MachineModuleInfo;
00043 class MachineRegisterInfo;
00044 class SelectionDAG;
00045 class MVT;
00046 class TargetLowering;
00047 class Value;
00048 
00049 //===--------------------------------------------------------------------===//
00050 /// FunctionLoweringInfo - This contains information that is global to a
00051 /// function that is used when lowering a region of the function.
00052 ///
00053 class FunctionLoweringInfo {
00054 public:
00055   const Function *Fn;
00056   MachineFunction *MF;
00057   const TargetLowering *TLI;
00058   MachineRegisterInfo *RegInfo;
00059   BranchProbabilityInfo *BPI;
00060   /// CanLowerReturn - true iff the function's return value can be lowered to
00061   /// registers.
00062   bool CanLowerReturn;
00063 
00064   /// DemoteRegister - if CanLowerReturn is false, DemoteRegister is a vreg
00065   /// allocated to hold a pointer to the hidden sret parameter.
00066   unsigned DemoteRegister;
00067 
00068   /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
00069   DenseMap<const BasicBlock*, MachineBasicBlock *> MBBMap;
00070 
00071   /// ValueMap - Since we emit code for the function a basic block at a time,
00072   /// we must remember which virtual registers hold the values for
00073   /// cross-basic-block values.
00074   DenseMap<const Value*, unsigned> ValueMap;
00075 
00076   /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
00077   /// the entry block.  This allows the allocas to be efficiently referenced
00078   /// anywhere in the function.
00079   DenseMap<const AllocaInst*, int> StaticAllocaMap;
00080 
00081   /// ByValArgFrameIndexMap - Keep track of frame indices for byval arguments.
00082   DenseMap<const Argument*, int> ByValArgFrameIndexMap;
00083 
00084   /// ArgDbgValues - A list of DBG_VALUE instructions created during isel for
00085   /// function arguments that are inserted after scheduling is completed.
00086   SmallVector<MachineInstr*, 8> ArgDbgValues;
00087 
00088   /// RegFixups - Registers which need to be replaced after isel is done.
00089   DenseMap<unsigned, unsigned> RegFixups;
00090 
00091   /// MBB - The current block.
00092   MachineBasicBlock *MBB;
00093 
00094   /// MBB - The current insert position inside the current block.
00095   MachineBasicBlock::iterator InsertPt;
00096 
00097 #ifndef NDEBUG
00098   SmallPtrSet<const Instruction *, 8> CatchInfoLost;
00099   SmallPtrSet<const Instruction *, 8> CatchInfoFound;
00100 #endif
00101 
00102   struct LiveOutInfo {
00103     unsigned NumSignBits : 31;
00104     bool IsValid : 1;
00105     APInt KnownOne, KnownZero;
00106     LiveOutInfo() : NumSignBits(0), IsValid(true), KnownOne(1, 0),
00107                     KnownZero(1, 0) {}
00108   };
00109 
00110   /// Record the preferred extend type (ISD::SIGN_EXTEND or ISD::ZERO_EXTEND)
00111   /// for a value.
00112   DenseMap<const Value *, ISD::NodeType> PreferredExtendType;
00113 
00114   /// VisitedBBs - The set of basic blocks visited thus far by instruction
00115   /// selection.
00116   SmallPtrSet<const BasicBlock*, 4> VisitedBBs;
00117 
00118   /// PHINodesToUpdate - A list of phi instructions whose operand list will
00119   /// be updated after processing the current basic block.
00120   /// TODO: This isn't per-function state, it's per-basic-block state. But
00121   /// there's no other convenient place for it to live right now.
00122   std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
00123   unsigned OrigNumPHINodesToUpdate;
00124 
00125   /// If the current MBB is a landing pad, the exception pointer and exception
00126   /// selector registers are copied into these virtual registers by
00127   /// SelectionDAGISel::PrepareEHLandingPad().
00128   unsigned ExceptionPointerVirtReg, ExceptionSelectorVirtReg;
00129 
00130   /// set - Initialize this FunctionLoweringInfo with the given Function
00131   /// and its associated MachineFunction.
00132   ///
00133   void set(const Function &Fn, MachineFunction &MF, SelectionDAG *DAG);
00134 
00135   /// clear - Clear out all the function-specific state. This returns this
00136   /// FunctionLoweringInfo to an empty state, ready to be used for a
00137   /// different function.
00138   void clear();
00139 
00140   /// isExportedInst - Return true if the specified value is an instruction
00141   /// exported from its block.
00142   bool isExportedInst(const Value *V) {
00143     return ValueMap.count(V);
00144   }
00145 
00146   unsigned CreateReg(MVT VT);
00147   
00148   unsigned CreateRegs(Type *Ty);
00149   
00150   unsigned InitializeRegForValue(const Value *V) {
00151     unsigned &R = ValueMap[V];
00152     assert(R == 0 && "Already initialized this value register!");
00153     return R = CreateRegs(V->getType());
00154   }
00155 
00156   /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
00157   /// register is a PHI destination and the PHI's LiveOutInfo is not valid.
00158   const LiveOutInfo *GetLiveOutRegInfo(unsigned Reg) {
00159     if (!LiveOutRegInfo.inBounds(Reg))
00160       return nullptr;
00161 
00162     const LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
00163     if (!LOI->IsValid)
00164       return nullptr;
00165 
00166     return LOI;
00167   }
00168 
00169   /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
00170   /// register is a PHI destination and the PHI's LiveOutInfo is not valid. If
00171   /// the register's LiveOutInfo is for a smaller bit width, it is extended to
00172   /// the larger bit width by zero extension. The bit width must be no smaller
00173   /// than the LiveOutInfo's existing bit width.
00174   const LiveOutInfo *GetLiveOutRegInfo(unsigned Reg, unsigned BitWidth);
00175 
00176   /// AddLiveOutRegInfo - Adds LiveOutInfo for a register.
00177   void AddLiveOutRegInfo(unsigned Reg, unsigned NumSignBits,
00178                          const APInt &KnownZero, const APInt &KnownOne) {
00179     // Only install this information if it tells us something.
00180     if (NumSignBits == 1 && KnownZero == 0 && KnownOne == 0)
00181       return;
00182 
00183     LiveOutRegInfo.grow(Reg);
00184     LiveOutInfo &LOI = LiveOutRegInfo[Reg];
00185     LOI.NumSignBits = NumSignBits;
00186     LOI.KnownOne = KnownOne;
00187     LOI.KnownZero = KnownZero;
00188   }
00189 
00190   /// ComputePHILiveOutRegInfo - Compute LiveOutInfo for a PHI's destination
00191   /// register based on the LiveOutInfo of its operands.
00192   void ComputePHILiveOutRegInfo(const PHINode*);
00193 
00194   /// InvalidatePHILiveOutRegInfo - Invalidates a PHI's LiveOutInfo, to be
00195   /// called when a block is visited before all of its predecessors.
00196   void InvalidatePHILiveOutRegInfo(const PHINode *PN) {
00197     // PHIs with no uses have no ValueMap entry.
00198     DenseMap<const Value*, unsigned>::const_iterator It = ValueMap.find(PN);
00199     if (It == ValueMap.end())
00200       return;
00201 
00202     unsigned Reg = It->second;
00203     LiveOutRegInfo.grow(Reg);
00204     LiveOutRegInfo[Reg].IsValid = false;
00205   }
00206 
00207   /// setArgumentFrameIndex - Record frame index for the byval
00208   /// argument.
00209   void setArgumentFrameIndex(const Argument *A, int FI);
00210 
00211   /// getArgumentFrameIndex - Get frame index for the byval argument.
00212   int getArgumentFrameIndex(const Argument *A);
00213 
00214 private:
00215   /// LiveOutRegInfo - Information about live out vregs.
00216   IndexedMap<LiveOutInfo, VirtReg2IndexFunctor> LiveOutRegInfo;
00217 };
00218 
00219 /// ComputeUsesVAFloatArgument - Determine if any floating-point values are
00220 /// being passed to this variadic function, and set the MachineModuleInfo's
00221 /// usesVAFloatArgument flag if so. This flag is used to emit an undefined
00222 /// reference to _fltused on Windows, which will link in MSVCRT's
00223 /// floating-point support.
00224 void ComputeUsesVAFloatArgument(const CallInst &I, MachineModuleInfo *MMI);
00225 
00226 /// AddCatchInfo - Extract the personality and type infos from an eh.selector
00227 /// call, and add them to the specified machine basic block.
00228 void AddCatchInfo(const CallInst &I,
00229                   MachineModuleInfo *MMI, MachineBasicBlock *MBB);
00230 
00231 /// AddLandingPadInfo - Extract the exception handling information from the
00232 /// landingpad instruction and add them to the specified machine module info.
00233 void AddLandingPadInfo(const LandingPadInst &I, MachineModuleInfo &MMI,
00234                        MachineBasicBlock *MBB);
00235 
00236 } // end namespace llvm
00237 
00238 #endif