LLVM 19.0.0git
HexagonAsmBackend.cpp
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1//===-- HexagonAsmBackend.cpp - Hexagon Assembler Backend -----------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "HexagonFixupKinds.h"
17#include "llvm/MC/MCAsmLayout.h"
18#include "llvm/MC/MCAssembler.h"
19#include "llvm/MC/MCContext.h"
22#include "llvm/MC/MCInstrInfo.h"
26#include "llvm/Support/Debug.h"
28
29#include <sstream>
30
31using namespace llvm;
32using namespace Hexagon;
33
34#define DEBUG_TYPE "hexagon-asm-backend"
35
37 ("mno-fixup", cl::desc("Disable fixing up resolved relocations for Hexagon"));
38
39namespace {
40
41class HexagonAsmBackend : public MCAsmBackend {
42 uint8_t OSABI;
43 StringRef CPU;
44 mutable uint64_t relaxedCnt;
45 std::unique_ptr <MCInstrInfo> MCII;
46 std::unique_ptr <MCInst *> RelaxTarget;
47 MCInst * Extender;
48 unsigned MaxPacketSize;
49
50 void ReplaceInstruction(MCCodeEmitter &E, MCRelaxableFragment &RF,
51 MCInst &HMB) const {
54 E.encodeInstruction(HMB, Code, Fixups, *RF.getSubtargetInfo());
55
56 // Update the fragment.
57 RF.setInst(HMB);
58 RF.getContents() = Code;
59 RF.getFixups() = Fixups;
60 }
61
62public:
63 HexagonAsmBackend(const Target &T, const Triple &TT, uint8_t OSABI,
64 StringRef CPU)
65 : MCAsmBackend(llvm::endianness::little), OSABI(OSABI), CPU(CPU),
66 relaxedCnt(0), MCII(T.createMCInstrInfo()), RelaxTarget(new MCInst *),
67 Extender(nullptr), MaxPacketSize(HexagonMCInstrInfo::packetSize(CPU)) {}
68
69 std::unique_ptr<MCObjectTargetWriter>
70 createObjectTargetWriter() const override {
71 return createHexagonELFObjectWriter(OSABI, CPU);
72 }
73
74 void setExtender(MCContext &Context) const {
75 if (Extender == nullptr)
76 const_cast<HexagonAsmBackend *>(this)->Extender = Context.createMCInst();
77 }
78
79 MCInst *takeExtender() const {
80 assert(Extender != nullptr);
81 MCInst * Result = Extender;
82 const_cast<HexagonAsmBackend *>(this)->Extender = nullptr;
83 return Result;
84 }
85
86 unsigned getNumFixupKinds() const override {
88 }
89
90 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
91 const static MCFixupKindInfo Infos[Hexagon::NumTargetFixupKinds] = {
92 // This table *must* be in same the order of fixup_* kinds in
93 // HexagonFixupKinds.h.
94 //
95 // namei offset bits flags
96 { "fixup_Hexagon_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
97 { "fixup_Hexagon_B15_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
98 { "fixup_Hexagon_B7_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
99 { "fixup_Hexagon_LO16", 0, 32, 0 },
100 { "fixup_Hexagon_HI16", 0, 32, 0 },
101 { "fixup_Hexagon_32", 0, 32, 0 },
102 { "fixup_Hexagon_16", 0, 32, 0 },
103 { "fixup_Hexagon_8", 0, 32, 0 },
104 { "fixup_Hexagon_GPREL16_0", 0, 32, 0 },
105 { "fixup_Hexagon_GPREL16_1", 0, 32, 0 },
106 { "fixup_Hexagon_GPREL16_2", 0, 32, 0 },
107 { "fixup_Hexagon_GPREL16_3", 0, 32, 0 },
108 { "fixup_Hexagon_HL16", 0, 32, 0 },
109 { "fixup_Hexagon_B13_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
110 { "fixup_Hexagon_B9_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
111 { "fixup_Hexagon_B32_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
112 { "fixup_Hexagon_32_6_X", 0, 32, 0 },
113 { "fixup_Hexagon_B22_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
114 { "fixup_Hexagon_B15_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
115 { "fixup_Hexagon_B13_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
116 { "fixup_Hexagon_B9_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
117 { "fixup_Hexagon_B7_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
118 { "fixup_Hexagon_16_X", 0, 32, 0 },
119 { "fixup_Hexagon_12_X", 0, 32, 0 },
120 { "fixup_Hexagon_11_X", 0, 32, 0 },
121 { "fixup_Hexagon_10_X", 0, 32, 0 },
122 { "fixup_Hexagon_9_X", 0, 32, 0 },
123 { "fixup_Hexagon_8_X", 0, 32, 0 },
124 { "fixup_Hexagon_7_X", 0, 32, 0 },
125 { "fixup_Hexagon_6_X", 0, 32, 0 },
126 { "fixup_Hexagon_32_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
127 { "fixup_Hexagon_COPY", 0, 32, 0 },
128 { "fixup_Hexagon_GLOB_DAT", 0, 32, 0 },
129 { "fixup_Hexagon_JMP_SLOT", 0, 32, 0 },
130 { "fixup_Hexagon_RELATIVE", 0, 32, 0 },
131 { "fixup_Hexagon_PLT_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
132 { "fixup_Hexagon_GOTREL_LO16", 0, 32, 0 },
133 { "fixup_Hexagon_GOTREL_HI16", 0, 32, 0 },
134 { "fixup_Hexagon_GOTREL_32", 0, 32, 0 },
135 { "fixup_Hexagon_GOT_LO16", 0, 32, 0 },
136 { "fixup_Hexagon_GOT_HI16", 0, 32, 0 },
137 { "fixup_Hexagon_GOT_32", 0, 32, 0 },
138 { "fixup_Hexagon_GOT_16", 0, 32, 0 },
139 { "fixup_Hexagon_DTPMOD_32", 0, 32, 0 },
140 { "fixup_Hexagon_DTPREL_LO16", 0, 32, 0 },
141 { "fixup_Hexagon_DTPREL_HI16", 0, 32, 0 },
142 { "fixup_Hexagon_DTPREL_32", 0, 32, 0 },
143 { "fixup_Hexagon_DTPREL_16", 0, 32, 0 },
144 { "fixup_Hexagon_GD_PLT_B22_PCREL",0, 32, MCFixupKindInfo::FKF_IsPCRel },
145 { "fixup_Hexagon_LD_PLT_B22_PCREL",0, 32, MCFixupKindInfo::FKF_IsPCRel },
146 { "fixup_Hexagon_GD_GOT_LO16", 0, 32, 0 },
147 { "fixup_Hexagon_GD_GOT_HI16", 0, 32, 0 },
148 { "fixup_Hexagon_GD_GOT_32", 0, 32, 0 },
149 { "fixup_Hexagon_GD_GOT_16", 0, 32, 0 },
150 { "fixup_Hexagon_LD_GOT_LO16", 0, 32, 0 },
151 { "fixup_Hexagon_LD_GOT_HI16", 0, 32, 0 },
152 { "fixup_Hexagon_LD_GOT_32", 0, 32, 0 },
153 { "fixup_Hexagon_LD_GOT_16", 0, 32, 0 },
154 { "fixup_Hexagon_IE_LO16", 0, 32, 0 },
155 { "fixup_Hexagon_IE_HI16", 0, 32, 0 },
156 { "fixup_Hexagon_IE_32", 0, 32, 0 },
157 { "fixup_Hexagon_IE_16", 0, 32, 0 },
158 { "fixup_Hexagon_IE_GOT_LO16", 0, 32, 0 },
159 { "fixup_Hexagon_IE_GOT_HI16", 0, 32, 0 },
160 { "fixup_Hexagon_IE_GOT_32", 0, 32, 0 },
161 { "fixup_Hexagon_IE_GOT_16", 0, 32, 0 },
162 { "fixup_Hexagon_TPREL_LO16", 0, 32, 0 },
163 { "fixup_Hexagon_TPREL_HI16", 0, 32, 0 },
164 { "fixup_Hexagon_TPREL_32", 0, 32, 0 },
165 { "fixup_Hexagon_TPREL_16", 0, 32, 0 },
166 { "fixup_Hexagon_6_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
167 { "fixup_Hexagon_GOTREL_32_6_X", 0, 32, 0 },
168 { "fixup_Hexagon_GOTREL_16_X", 0, 32, 0 },
169 { "fixup_Hexagon_GOTREL_11_X", 0, 32, 0 },
170 { "fixup_Hexagon_GOT_32_6_X", 0, 32, 0 },
171 { "fixup_Hexagon_GOT_16_X", 0, 32, 0 },
172 { "fixup_Hexagon_GOT_11_X", 0, 32, 0 },
173 { "fixup_Hexagon_DTPREL_32_6_X", 0, 32, 0 },
174 { "fixup_Hexagon_DTPREL_16_X", 0, 32, 0 },
175 { "fixup_Hexagon_DTPREL_11_X", 0, 32, 0 },
176 { "fixup_Hexagon_GD_GOT_32_6_X", 0, 32, 0 },
177 { "fixup_Hexagon_GD_GOT_16_X", 0, 32, 0 },
178 { "fixup_Hexagon_GD_GOT_11_X", 0, 32, 0 },
179 { "fixup_Hexagon_LD_GOT_32_6_X", 0, 32, 0 },
180 { "fixup_Hexagon_LD_GOT_16_X", 0, 32, 0 },
181 { "fixup_Hexagon_LD_GOT_11_X", 0, 32, 0 },
182 { "fixup_Hexagon_IE_32_6_X", 0, 32, 0 },
183 { "fixup_Hexagon_IE_16_X", 0, 32, 0 },
184 { "fixup_Hexagon_IE_GOT_32_6_X", 0, 32, 0 },
185 { "fixup_Hexagon_IE_GOT_16_X", 0, 32, 0 },
186 { "fixup_Hexagon_IE_GOT_11_X", 0, 32, 0 },
187 { "fixup_Hexagon_TPREL_32_6_X", 0, 32, 0 },
188 { "fixup_Hexagon_TPREL_16_X", 0, 32, 0 },
189 { "fixup_Hexagon_TPREL_11_X", 0, 32, 0 },
190 { "fixup_Hexagon_GD_PLT_B22_PCREL_X",0, 32, MCFixupKindInfo::FKF_IsPCRel },
191 { "fixup_Hexagon_GD_PLT_B32_PCREL_X",0, 32, MCFixupKindInfo::FKF_IsPCRel },
192 { "fixup_Hexagon_LD_PLT_B22_PCREL_X",0, 32, MCFixupKindInfo::FKF_IsPCRel },
193 { "fixup_Hexagon_LD_PLT_B32_PCREL_X",0, 32, MCFixupKindInfo::FKF_IsPCRel }
194 };
195
196 if (Kind < FirstTargetFixupKind)
198
199 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
200 "Invalid kind!");
201 return Infos[Kind - FirstTargetFixupKind];
202 }
203
204 bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
205 const MCValue &Target,
206 const MCSubtargetInfo *STI) override {
207 switch(Fixup.getTargetKind()) {
208 default:
209 llvm_unreachable("Unknown Fixup Kind!");
210
213 case fixup_Hexagon_16:
214 case fixup_Hexagon_8:
299 // These relocations should always have a relocation recorded
300 return true;
301
303 //IsResolved = false;
304 break;
305
316 if (DisableFixup)
317 return true;
318 break;
319
320 case FK_Data_1:
321 case FK_Data_2:
322 case FK_Data_4:
323 case FK_PCRel_4:
324 case fixup_Hexagon_32:
325 // Leave these relocations alone as they are used for EH.
326 return false;
327 }
328 return false;
329 }
330
331 /// getFixupKindNumBytes - The number of bytes the fixup may change.
332 static unsigned getFixupKindNumBytes(unsigned Kind) {
333 switch (Kind) {
334 default:
335 return 0;
336
337 case FK_Data_1:
338 return 1;
339 case FK_Data_2:
340 return 2;
341 case FK_Data_4: // this later gets mapped to R_HEX_32
342 case FK_PCRel_4: // this later gets mapped to R_HEX_32_PCREL
343 case fixup_Hexagon_32:
357 return 4;
358 }
359 }
360
361 // Make up for left shift when encoding the operand.
363 switch((unsigned)Kind) {
364 default:
365 break;
366
372 Value >>= 2;
373 break;
374
380 Value &= 0x3f;
381 break;
382
386 Value >>= 6;
387 break;
388 }
389 return (Value);
390 }
391
392 void HandleFixupError(const int bits, const int align_bits,
393 const int64_t FixupValue, const char *fixupStr) const {
394 // Error: value 1124 out of range: -1024-1023 when resolving
395 // symbol in file xprtsock.S
396 const APInt IntMin = APInt::getSignedMinValue(bits+align_bits);
397 const APInt IntMax = APInt::getSignedMaxValue(bits+align_bits);
398 std::stringstream errStr;
399 errStr << "\nError: value " <<
400 FixupValue <<
401 " out of range: " <<
402 IntMin.getSExtValue() <<
403 "-" <<
404 IntMax.getSExtValue() <<
405 " when resolving " <<
406 fixupStr <<
407 " fixup\n";
408 llvm_unreachable(errStr.str().c_str());
409 }
410
411 /// ApplyFixup - Apply the \arg Value for given \arg Fixup into the provided
412 /// data fragment, at the offset specified by the fixup and following the
413 /// fixup kind as appropriate.
414 void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
416 uint64_t FixupValue, bool IsResolved,
417 const MCSubtargetInfo *STI) const override {
418
419 // When FixupValue is 0 the relocation is external and there
420 // is nothing for us to do.
421 if (!FixupValue) return;
422
423 MCFixupKind Kind = Fixup.getKind();
425 uint32_t InstMask;
426 uint32_t Reloc;
427
428 // LLVM gives us an encoded value, we have to convert it back
429 // to a real offset before we can use it.
430 uint32_t Offset = Fixup.getOffset();
431 unsigned NumBytes = getFixupKindNumBytes(Kind);
432 assert(Offset + NumBytes <= Data.size() && "Invalid fixup offset!");
433 char *InstAddr = Data.data() + Offset;
434
435 Value = adjustFixupValue(Kind, FixupValue);
436 if(!Value)
437 return;
438 int sValue = (int)Value;
439
440 switch((unsigned)Kind) {
441 default:
442 return;
443
445 if (!(isIntN(7, sValue)))
446 HandleFixupError(7, 2, (int64_t)FixupValue, "B7_PCREL");
447 [[fallthrough]];
449 InstMask = 0x00001f18; // Word32_B7
450 Reloc = (((Value >> 2) & 0x1f) << 8) | // Value 6-2 = Target 12-8
451 ((Value & 0x3) << 3); // Value 1-0 = Target 4-3
452 break;
453
455 if (!(isIntN(9, sValue)))
456 HandleFixupError(9, 2, (int64_t)FixupValue, "B9_PCREL");
457 [[fallthrough]];
459 InstMask = 0x003000fe; // Word32_B9
460 Reloc = (((Value >> 7) & 0x3) << 20) | // Value 8-7 = Target 21-20
461 ((Value & 0x7f) << 1); // Value 6-0 = Target 7-1
462 break;
463
464 // Since the existing branches that use this relocation cannot be
465 // extended, they should only be fixed up if the target is within range.
467 if (!(isIntN(13, sValue)))
468 HandleFixupError(13, 2, (int64_t)FixupValue, "B13_PCREL");
469 [[fallthrough]];
471 InstMask = 0x00202ffe; // Word32_B13
472 Reloc = (((Value >> 12) & 0x1) << 21) | // Value 12 = Target 21
473 (((Value >> 11) & 0x1) << 13) | // Value 11 = Target 13
474 ((Value & 0x7ff) << 1); // Value 10-0 = Target 11-1
475 break;
476
478 if (!(isIntN(15, sValue)))
479 HandleFixupError(15, 2, (int64_t)FixupValue, "B15_PCREL");
480 [[fallthrough]];
482 InstMask = 0x00df20fe; // Word32_B15
483 Reloc = (((Value >> 13) & 0x3) << 22) | // Value 14-13 = Target 23-22
484 (((Value >> 8) & 0x1f) << 16) | // Value 12-8 = Target 20-16
485 (((Value >> 7) & 0x1) << 13) | // Value 7 = Target 13
486 ((Value & 0x7f) << 1); // Value 6-0 = Target 7-1
487 break;
488
490 if (!(isIntN(22, sValue)))
491 HandleFixupError(22, 2, (int64_t)FixupValue, "B22_PCREL");
492 [[fallthrough]];
494 InstMask = 0x01ff3ffe; // Word32_B22
495 Reloc = (((Value >> 13) & 0x1ff) << 16) | // Value 21-13 = Target 24-16
496 ((Value & 0x1fff) << 1); // Value 12-0 = Target 13-1
497 break;
498
500 InstMask = 0x0fff3fff; // Word32_X26
501 Reloc = (((Value >> 14) & 0xfff) << 16) | // Value 25-14 = Target 27-16
502 (Value & 0x3fff); // Value 13-0 = Target 13-0
503 break;
504
505 case FK_Data_1:
506 case FK_Data_2:
507 case FK_Data_4:
508 case fixup_Hexagon_32:
509 InstMask = 0xffffffff; // Word32
510 Reloc = Value;
511 break;
512 }
513
514 LLVM_DEBUG(dbgs() << "Name=" << getFixupKindInfo(Kind).Name << "("
515 << (unsigned)Kind << ")\n");
517 uint32_t OldData = 0; for (unsigned i = 0; i < NumBytes; i++) OldData |=
518 (InstAddr[i] << (i * 8)) & (0xff << (i * 8));
519 dbgs() << "\tBValue=0x"; dbgs().write_hex(Value) << ": AValue=0x";
520 dbgs().write_hex(FixupValue)
521 << ": Offset=" << Offset << ": Size=" << Data.size() << ": OInst=0x";
522 dbgs().write_hex(OldData) << ": Reloc=0x"; dbgs().write_hex(Reloc););
523
524 // For each byte of the fragment that the fixup touches, mask in the
525 // bits from the fixup value. The Value has been "split up" into the
526 // appropriate bitfields above.
527 for (unsigned i = 0; i < NumBytes; i++){
528 InstAddr[i] &= uint8_t(~InstMask >> (i * 8)) & 0xff; // Clear reloc bits
529 InstAddr[i] |= uint8_t(Reloc >> (i * 8)) & 0xff; // Apply new reloc
530 }
531
532 LLVM_DEBUG(uint32_t NewData = 0;
533 for (unsigned i = 0; i < NumBytes; i++) NewData |=
534 (InstAddr[i] << (i * 8)) & (0xff << (i * 8));
535 dbgs() << ": NInst=0x"; dbgs().write_hex(NewData) << "\n";);
536 }
537
538 bool isInstRelaxable(MCInst const &HMI) const {
539 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(*MCII, HMI);
540 bool Relaxable = false;
541 // Branches and loop-setup insns are handled as necessary by relaxation.
544 MCID.isBranch()) ||
546 MCID.isBranch()) ||
548 HMI.getOpcode() != Hexagon::C4_addipc))
549 if (HexagonMCInstrInfo::isExtendable(*MCII, HMI)) {
550 Relaxable = true;
551 MCOperand const &Operand =
554 Relaxable = false;
555 }
556
557 return Relaxable;
558 }
559
560 /// MayNeedRelaxation - Check whether the given instruction may need
561 /// relaxation.
562 ///
563 /// \param Inst - The instruction to test.
564 bool mayNeedRelaxation(MCInst const &Inst,
565 const MCSubtargetInfo &STI) const override {
566 return true;
567 }
568
569 /// fixupNeedsRelaxation - Target specific predicate for whether a given
570 /// fixup requires the associated instruction to be relaxed.
571 bool fixupNeedsRelaxationAdvanced(const MCFixup &Fixup, bool Resolved,
573 const MCRelaxableFragment *DF,
574 const MCAsmLayout &Layout,
575 const bool WasForced) const override {
576 MCInst const &MCB = DF->getInst();
578
579 *RelaxTarget = nullptr;
580 MCInst &MCI = const_cast<MCInst &>(HexagonMCInstrInfo::instruction(
581 MCB, Fixup.getOffset() / HEXAGON_INSTR_SIZE));
582 bool Relaxable = isInstRelaxable(MCI);
583 if (Relaxable == false)
584 return false;
585 // If we cannot resolve the fixup value, it requires relaxation.
586 if (!Resolved) {
587 switch (Fixup.getTargetKind()) {
589 // GetFixupCount assumes B22 won't relax
590 [[fallthrough]];
591 default:
592 return false;
593 break;
599 ++relaxedCnt;
600 *RelaxTarget = &MCI;
601 setExtender(Layout.getAssembler().getContext());
602 return true;
603 } else {
604 return false;
605 }
606 break;
607 }
608 }
609 }
610
611 MCFixupKind Kind = Fixup.getKind();
612 int64_t sValue = Value;
613 int64_t maxValue;
614
615 switch ((unsigned)Kind) {
617 maxValue = 1 << 8;
618 break;
620 maxValue = 1 << 10;
621 break;
623 maxValue = 1 << 16;
624 break;
626 maxValue = 1 << 23;
627 break;
628 default:
629 maxValue = INT64_MAX;
630 break;
631 }
632
633 bool isFarAway = -maxValue > sValue || sValue > maxValue - 1;
634
635 if (isFarAway) {
637 ++relaxedCnt;
638 *RelaxTarget = &MCI;
639 setExtender(Layout.getAssembler().getContext());
640 return true;
641 }
642 }
643
644 return false;
645 }
646
647 /// Simple predicate for targets where !Resolved implies requiring relaxation
649 const MCRelaxableFragment *DF,
650 const MCAsmLayout &Layout) const override {
651 llvm_unreachable("Handled by fixupNeedsRelaxationAdvanced");
652 }
653
654 void relaxInstruction(MCInst &Inst,
655 const MCSubtargetInfo &STI) const override {
657 "Hexagon relaxInstruction only works on bundles");
658
659 MCInst Res;
660 Res.setOpcode(Hexagon::BUNDLE);
662 // Copy the results into the bundle.
663 bool Update = false;
664 for (auto &I : HexagonMCInstrInfo::bundleInstructions(Inst)) {
665 MCInst &CrntHMI = const_cast<MCInst &>(*I.getInst());
666
667 // if immediate extender needed, add it in
668 if (*RelaxTarget == &CrntHMI) {
669 Update = true;
671 "No room to insert extender for relaxation");
672
673 MCInst *HMIx = takeExtender();
675 *MCII, CrntHMI,
678 *RelaxTarget = nullptr;
679 }
680 // now copy over the original instruction(the one we may have extended)
681 Res.addOperand(MCOperand::createInst(I.getInst()));
682 }
683
684 Inst = std::move(Res);
685 (void)Update;
686 assert(Update && "Didn't find relaxation target");
687 }
688
689 bool writeNopData(raw_ostream &OS, uint64_t Count,
690 const MCSubtargetInfo *STI) const override {
691 static const uint32_t Nopcode = 0x7f000000, // Hard-coded NOP.
692 ParseIn = 0x00004000, // In packet parse-bits.
693 ParseEnd = 0x0000c000; // End of packet parse-bits.
694
695 while (Count % HEXAGON_INSTR_SIZE) {
696 LLVM_DEBUG(dbgs() << "Alignment not a multiple of the instruction size:"
697 << Count % HEXAGON_INSTR_SIZE << "/"
698 << HEXAGON_INSTR_SIZE << "\n");
699 --Count;
700 OS << '\0';
701 }
702
703 while (Count) {
704 Count -= HEXAGON_INSTR_SIZE;
705 // Close the packet whenever a multiple of the maximum packet size remains
706 uint32_t ParseBits = (Count % (MaxPacketSize * HEXAGON_INSTR_SIZE)) ?
707 ParseIn : ParseEnd;
708 support::endian::write<uint32_t>(OS, Nopcode | ParseBits, Endian);
709 }
710 return true;
711 }
712
713 void finishLayout(MCAssembler const &Asm,
714 MCAsmLayout &Layout) const override {
715 for (auto *I : Layout.getSectionOrder()) {
716 auto &Fragments = I->getFragmentList();
717 for (auto &J : Fragments) {
718 switch (J.getKind()) {
719 default:
720 break;
722 auto Size = Asm.computeFragmentSize(Layout, J);
723 for (auto K = J.getIterator();
724 K != Fragments.begin() && Size >= HEXAGON_PACKET_SIZE;) {
725 --K;
726 switch (K->getKind()) {
727 default:
728 break;
730 // Don't pad before other alignments
731 Size = 0;
732 break;
733 }
735 MCContext &Context = Asm.getContext();
736 auto &RF = cast<MCRelaxableFragment>(*K);
737 auto &Inst = const_cast<MCInst &>(RF.getInst());
738 while (Size > 0 &&
739 HexagonMCInstrInfo::bundleSize(Inst) < MaxPacketSize) {
740 MCInst *Nop = Context.createMCInst();
741 Nop->setOpcode(Hexagon::A2_nop);
743 Size -= 4;
744 if (!HexagonMCChecker(
745 Context, *MCII, *RF.getSubtargetInfo(), Inst,
746 *Context.getRegisterInfo(), false)
747 .check()) {
748 Inst.erase(Inst.end() - 1);
749 Size = 0;
750 }
751 }
752 bool Error = HexagonMCShuffle(Context, true, *MCII,
753 *RF.getSubtargetInfo(), Inst);
754 //assert(!Error);
755 (void)Error;
756 ReplaceInstruction(Asm.getEmitter(), RF, Inst);
757 Layout.invalidateFragmentsFrom(&RF);
758 Size = 0; // Only look back one instruction
759 break;
760 }
761 }
762 }
763 }
764 }
765 }
766 }
767 }
768}; // class HexagonAsmBackend
769
770} // namespace
771
772// MCAsmBackend
774 const MCSubtargetInfo &STI,
775 MCRegisterInfo const & /*MRI*/,
776 const MCTargetOptions &Options) {
777 const Triple &TT = STI.getTargetTriple();
778 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
779
781 return new HexagonAsmBackend(T, TT, OSABI, CPUString);
782}
static unsigned getFixupKindNumBytes(unsigned Kind)
The number of bytes the fixup may change.
static uint64_t adjustFixupValue(const MCFixup &Fixup, const MCValue &Target, uint64_t Value, MCContext &Ctx, const Triple &TheTriple, bool IsResolved)
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
#define LLVM_DEBUG(X)
Definition: Debug.h:101
static RegisterPass< DebugifyFunctionPass > DF("debugify-function", "Attach debug info to a function")
std::string Name
uint64_t Size
static cl::opt< bool > DisableFixup("mno-fixup", cl::desc("Disable fixing up resolved relocations for Hexagon"))
Definition for classes that emit Hexagon machine code from MCInsts.
#define HEXAGON_INSTR_SIZE
#define HEXAGON_PACKET_SIZE
static LVOptions Options
Definition: LVOptions.cpp:25
#define I(x, y, z)
Definition: MD5.cpp:58
LLVMContext & Context
PowerPC TLS Dynamic Call Fixup
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
raw_pwrite_stream & OS
static MCInstrInfo * createMCInstrInfo()
Class for arbitrary precision integers.
Definition: APInt.h:76
static APInt getSignedMaxValue(unsigned numBits)
Gets maximum signed value of APInt for a specific bit width.
Definition: APInt.h:187
static APInt getSignedMinValue(unsigned numBits)
Gets minimum signed value of APInt for a specific bit width.
Definition: APInt.h:197
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1513
Lightweight error class with error context and mandatory checking.
Definition: Error.h:160
Check for a valid bundle.
bool check(bool FullCheck=true)
Generic interface to target specific assembler backends.
Definition: MCAsmBackend.h:43
virtual bool fixupNeedsRelaxationAdvanced(const MCFixup &Fixup, bool Resolved, uint64_t Value, const MCRelaxableFragment *DF, const MCAsmLayout &Layout, const bool WasForced) const
Target specific predicate for whether a given fixup requires the associated instruction to be relaxed...
virtual bool writeNopData(raw_ostream &OS, uint64_t Count, const MCSubtargetInfo *STI) const =0
Write an (optimal) nop sequence of Count bytes to the given output.
virtual void relaxInstruction(MCInst &Inst, const MCSubtargetInfo &STI) const
Relax the instruction in the given fragment to the next wider instruction.
Definition: MCAsmBackend.h:186
virtual bool mayNeedRelaxation(const MCInst &Inst, const MCSubtargetInfo &STI) const
Check whether the given instruction may need relaxation.
Definition: MCAsmBackend.h:163
virtual bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, const MCRelaxableFragment *DF, const MCAsmLayout &Layout) const =0
Simple predicate for targets where !Resolved implies requiring relaxation.
virtual void finishLayout(MCAssembler const &Asm, MCAsmLayout &Layout) const
Give backend an opportunity to finish layout after relaxation.
Definition: MCAsmBackend.h:228
virtual std::unique_ptr< MCObjectTargetWriter > createObjectTargetWriter() const =0
virtual bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, const MCSubtargetInfo *STI)
Hook to check if a relocation is needed for some target specific reason.
Definition: MCAsmBackend.h:102
virtual unsigned getNumFixupKinds() const =0
Get the number of target specific fixup kinds.
virtual const MCFixupKindInfo & getFixupKindInfo(MCFixupKind Kind) const
Get information on a fixup kind.
virtual void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, const MCValue &Target, MutableArrayRef< char > Data, uint64_t Value, bool IsResolved, const MCSubtargetInfo *STI) const =0
Apply the Value for given Fixup into the provided data fragment, at the offset specified by the fixup...
Encapsulates the layout of an assembly file at a particular point in time.
Definition: MCAsmLayout.h:28
void invalidateFragmentsFrom(MCFragment *F)
Invalidate the fragments starting with F because it has been resized.
Definition: MCFragment.cpp:70
llvm::SmallVectorImpl< MCSection * > & getSectionOrder()
Definition: MCAsmLayout.h:69
MCAssembler & getAssembler() const
Get the assembler object this is a layout for.
Definition: MCAsmLayout.h:50
MCContext & getContext() const
Definition: MCAssembler.h:326
MCCodeEmitter - Generic instruction encoding interface.
Definition: MCCodeEmitter.h:21
Context object for machine code objects.
Definition: MCContext.h:76
SmallVectorImpl< char > & getContents()
Definition: MCFragment.h:197
SmallVectorImpl< MCFixup > & getFixups()
Definition: MCFragment.h:223
const MCSubtargetInfo * getSubtargetInfo() const
Retrieve the MCSubTargetInfo in effect when the instruction was encoded.
Definition: MCFragment.h:173
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:71
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:184
void erase(iterator I)
Definition: MCInst.h:216
unsigned getOpcode() const
Definition: MCInst.h:198
void addOperand(const MCOperand Op)
Definition: MCInst.h:210
iterator end()
Definition: MCInst.h:221
void setOpcode(unsigned Op)
Definition: MCInst.h:197
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:206
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
bool isBranch() const
Returns true if this is a conditional, unconditional, or indirect branch.
Definition: MCInstrDesc.h:307
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:36
int64_t getImm() const
Definition: MCInst.h:80
static MCOperand createImm(int64_t Val)
Definition: MCInst.h:141
const MCExpr * getExpr() const
Definition: MCInst.h:114
static MCOperand createInst(const MCInst *Val)
Definition: MCInst.h:169
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
A relaxable fragment holds on to its MCInst, since it may need to be relaxed during the assembler lay...
Definition: MCFragment.h:274
const MCInst & getInst() const
Definition: MCFragment.h:287
void setInst(const MCInst &Value)
Definition: MCFragment.h:288
Generic base class for all target subtargets.
const Triple & getTargetTriple() const
StringRef getCPU() const
This represents an "assembler immediate".
Definition: MCValue.h:36
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Definition: ArrayRef.h:307
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
Definition: SmallString.h:26
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
LLVM Value Representation.
Definition: Value.h:74
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
raw_ostream & write_hex(unsigned long long N)
Output N in hexadecimal, without any prefix or padding.
#define INT64_MAX
Definition: DataTypes.h:71
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
size_t bundleSize(MCInst const &MCI)
unsigned short getExtendableOp(MCInstrInfo const &MCII, MCInst const &MCI)
bool mustNotExtend(MCExpr const &Expr)
MCInstrDesc const & getDesc(MCInstrInfo const &MCII, MCInst const &MCI)
iterator_range< Hexagon::PacketIterator > bundleInstructions(MCInstrInfo const &MCII, MCInst const &MCI)
bool isBundle(MCInst const &MCI)
bool isExtendable(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned getType(MCInstrInfo const &MCII, MCInst const &MCI)
Return the Hexagon ISA class for the insn.
MCInst const & instruction(MCInst const &MCB, size_t Index)
MCOperand const & getExtendableOperand(MCInstrInfo const &MCII, MCInst const &MCI)
unsigned packetSize(StringRef CPU)
MCInst deriveExtender(MCInstrInfo const &MCII, MCInst const &Inst, MCOperand const &MO)
StringRef selectHexagonCPU(StringRef CPU)
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:456
bool HexagonMCShuffle(MCContext &Context, bool ReportErrors, MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst &MCB)
std::unique_ptr< MCObjectTargetWriter > createHexagonELFObjectWriter(uint8_t OSABI, StringRef CPU)
MCAsmBackend * createHexagonAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:163
MCFixupKind
Extensible enumeration to represent the type of a fixup.
Definition: MCFixup.h:21
@ FirstTargetFixupKind
Definition: MCFixup.h:45
@ FK_PCRel_4
A four-byte pc relative fixup.
Definition: MCFixup.h:30
@ FK_Data_1
A one-byte fixup.
Definition: MCFixup.h:23
@ FK_Data_4
A four-byte fixup.
Definition: MCFixup.h:25
@ FK_Data_2
A two-byte fixup.
Definition: MCFixup.h:24
bool isIntN(unsigned N, int64_t x)
Checks if an signed integer fits into the given (dynamic) bit width.
Definition: MathExtras.h:233
endianness
Definition: bit.h:70
Target independent information on a fixup kind.
@ FKF_IsPCRel
Is this fixup kind PCrelative? This is used by the assembler backend to evaluate fixup values in a ta...