LLVM API Documentation
00001 //===-- HexagonISelLowering.cpp - Hexagon DAG Lowering Implementation -----===// 00002 // 00003 // The LLVM Compiler Infrastructure 00004 // 00005 // This file is distributed under the University of Illinois Open Source 00006 // License. See LICENSE.TXT for details. 00007 // 00008 //===----------------------------------------------------------------------===// 00009 // 00010 // This file implements the interfaces that Hexagon uses to lower LLVM code 00011 // into a selection DAG. 00012 // 00013 //===----------------------------------------------------------------------===// 00014 00015 #include "HexagonISelLowering.h" 00016 #include "HexagonMachineFunctionInfo.h" 00017 #include "HexagonSubtarget.h" 00018 #include "HexagonTargetMachine.h" 00019 #include "HexagonTargetObjectFile.h" 00020 #include "llvm/CodeGen/CallingConvLower.h" 00021 #include "llvm/CodeGen/MachineFrameInfo.h" 00022 #include "llvm/CodeGen/MachineFunction.h" 00023 #include "llvm/CodeGen/MachineInstrBuilder.h" 00024 #include "llvm/CodeGen/MachineJumpTableInfo.h" 00025 #include "llvm/CodeGen/MachineRegisterInfo.h" 00026 #include "llvm/CodeGen/SelectionDAGISel.h" 00027 #include "llvm/CodeGen/ValueTypes.h" 00028 #include "llvm/IR/CallingConv.h" 00029 #include "llvm/IR/DerivedTypes.h" 00030 #include "llvm/IR/Function.h" 00031 #include "llvm/IR/GlobalAlias.h" 00032 #include "llvm/IR/GlobalVariable.h" 00033 #include "llvm/IR/InlineAsm.h" 00034 #include "llvm/IR/Intrinsics.h" 00035 #include "llvm/Support/CommandLine.h" 00036 #include "llvm/Support/Debug.h" 00037 #include "llvm/Support/ErrorHandling.h" 00038 #include "llvm/Support/raw_ostream.h" 00039 00040 using namespace llvm; 00041 00042 const unsigned Hexagon_MAX_RET_SIZE = 64; 00043 00044 static cl::opt<bool> 00045 EmitJumpTables("hexagon-emit-jump-tables", cl::init(true), cl::Hidden, 00046 cl::desc("Control jump table emission on Hexagon target")); 00047 00048 int NumNamedVarArgParams = -1; 00049 00050 // Implement calling convention for Hexagon. 00051 static bool 00052 CC_Hexagon(unsigned ValNo, MVT ValVT, 00053 MVT LocVT, CCValAssign::LocInfo LocInfo, 00054 ISD::ArgFlagsTy ArgFlags, CCState &State); 00055 00056 static bool 00057 CC_Hexagon32(unsigned ValNo, MVT ValVT, 00058 MVT LocVT, CCValAssign::LocInfo LocInfo, 00059 ISD::ArgFlagsTy ArgFlags, CCState &State); 00060 00061 static bool 00062 CC_Hexagon64(unsigned ValNo, MVT ValVT, 00063 MVT LocVT, CCValAssign::LocInfo LocInfo, 00064 ISD::ArgFlagsTy ArgFlags, CCState &State); 00065 00066 static bool 00067 RetCC_Hexagon(unsigned ValNo, MVT ValVT, 00068 MVT LocVT, CCValAssign::LocInfo LocInfo, 00069 ISD::ArgFlagsTy ArgFlags, CCState &State); 00070 00071 static bool 00072 RetCC_Hexagon32(unsigned ValNo, MVT ValVT, 00073 MVT LocVT, CCValAssign::LocInfo LocInfo, 00074 ISD::ArgFlagsTy ArgFlags, CCState &State); 00075 00076 static bool 00077 RetCC_Hexagon64(unsigned ValNo, MVT ValVT, 00078 MVT LocVT, CCValAssign::LocInfo LocInfo, 00079 ISD::ArgFlagsTy ArgFlags, CCState &State); 00080 00081 static bool 00082 CC_Hexagon_VarArg (unsigned ValNo, MVT ValVT, 00083 MVT LocVT, CCValAssign::LocInfo LocInfo, 00084 ISD::ArgFlagsTy ArgFlags, CCState &State) { 00085 00086 // NumNamedVarArgParams can not be zero for a VarArg function. 00087 assert ( (NumNamedVarArgParams > 0) && 00088 "NumNamedVarArgParams is not bigger than zero."); 00089 00090 if ( (int)ValNo < NumNamedVarArgParams ) { 00091 // Deal with named arguments. 00092 return CC_Hexagon(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State); 00093 } 00094 00095 // Deal with un-named arguments. 00096 unsigned ofst; 00097 if (ArgFlags.isByVal()) { 00098 // If pass-by-value, the size allocated on stack is decided 00099 // by ArgFlags.getByValSize(), not by the size of LocVT. 00100 assert ((ArgFlags.getByValSize() > 8) && 00101 "ByValSize must be bigger than 8 bytes"); 00102 ofst = State.AllocateStack(ArgFlags.getByValSize(), 4); 00103 State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo)); 00104 return false; 00105 } 00106 if (LocVT == MVT::i1 || LocVT == MVT::i8 || LocVT == MVT::i16) { 00107 LocVT = MVT::i32; 00108 ValVT = MVT::i32; 00109 if (ArgFlags.isSExt()) 00110 LocInfo = CCValAssign::SExt; 00111 else if (ArgFlags.isZExt()) 00112 LocInfo = CCValAssign::ZExt; 00113 else 00114 LocInfo = CCValAssign::AExt; 00115 } 00116 if (LocVT == MVT::i32 || LocVT == MVT::f32) { 00117 ofst = State.AllocateStack(4, 4); 00118 State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo)); 00119 return false; 00120 } 00121 if (LocVT == MVT::i64 || LocVT == MVT::f64) { 00122 ofst = State.AllocateStack(8, 8); 00123 State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo)); 00124 return false; 00125 } 00126 llvm_unreachable(0); 00127 } 00128 00129 00130 static bool 00131 CC_Hexagon (unsigned ValNo, MVT ValVT, 00132 MVT LocVT, CCValAssign::LocInfo LocInfo, 00133 ISD::ArgFlagsTy ArgFlags, CCState &State) { 00134 00135 if (ArgFlags.isByVal()) { 00136 // Passed on stack. 00137 assert ((ArgFlags.getByValSize() > 8) && 00138 "ByValSize must be bigger than 8 bytes"); 00139 unsigned Offset = State.AllocateStack(ArgFlags.getByValSize(), 4); 00140 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 00141 return false; 00142 } 00143 00144 if (LocVT == MVT::i1 || LocVT == MVT::i8 || LocVT == MVT::i16) { 00145 LocVT = MVT::i32; 00146 ValVT = MVT::i32; 00147 if (ArgFlags.isSExt()) 00148 LocInfo = CCValAssign::SExt; 00149 else if (ArgFlags.isZExt()) 00150 LocInfo = CCValAssign::ZExt; 00151 else 00152 LocInfo = CCValAssign::AExt; 00153 } 00154 00155 if (LocVT == MVT::i32 || LocVT == MVT::f32) { 00156 if (!CC_Hexagon32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 00157 return false; 00158 } 00159 00160 if (LocVT == MVT::i64 || LocVT == MVT::f64) { 00161 if (!CC_Hexagon64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 00162 return false; 00163 } 00164 00165 return true; // CC didn't match. 00166 } 00167 00168 00169 static bool CC_Hexagon32(unsigned ValNo, MVT ValVT, 00170 MVT LocVT, CCValAssign::LocInfo LocInfo, 00171 ISD::ArgFlagsTy ArgFlags, CCState &State) { 00172 00173 static const uint16_t RegList[] = { 00174 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4, 00175 Hexagon::R5 00176 }; 00177 if (unsigned Reg = State.AllocateReg(RegList, 6)) { 00178 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 00179 return false; 00180 } 00181 00182 unsigned Offset = State.AllocateStack(4, 4); 00183 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 00184 return false; 00185 } 00186 00187 static bool CC_Hexagon64(unsigned ValNo, MVT ValVT, 00188 MVT LocVT, CCValAssign::LocInfo LocInfo, 00189 ISD::ArgFlagsTy ArgFlags, CCState &State) { 00190 00191 if (unsigned Reg = State.AllocateReg(Hexagon::D0)) { 00192 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 00193 return false; 00194 } 00195 00196 static const uint16_t RegList1[] = { 00197 Hexagon::D1, Hexagon::D2 00198 }; 00199 static const uint16_t RegList2[] = { 00200 Hexagon::R1, Hexagon::R3 00201 }; 00202 if (unsigned Reg = State.AllocateReg(RegList1, RegList2, 2)) { 00203 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 00204 return false; 00205 } 00206 00207 unsigned Offset = State.AllocateStack(8, 8, Hexagon::D2); 00208 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 00209 return false; 00210 } 00211 00212 static bool RetCC_Hexagon(unsigned ValNo, MVT ValVT, 00213 MVT LocVT, CCValAssign::LocInfo LocInfo, 00214 ISD::ArgFlagsTy ArgFlags, CCState &State) { 00215 00216 00217 if (LocVT == MVT::i1 || 00218 LocVT == MVT::i8 || 00219 LocVT == MVT::i16) { 00220 LocVT = MVT::i32; 00221 ValVT = MVT::i32; 00222 if (ArgFlags.isSExt()) 00223 LocInfo = CCValAssign::SExt; 00224 else if (ArgFlags.isZExt()) 00225 LocInfo = CCValAssign::ZExt; 00226 else 00227 LocInfo = CCValAssign::AExt; 00228 } 00229 00230 if (LocVT == MVT::i32 || LocVT == MVT::f32) { 00231 if (!RetCC_Hexagon32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 00232 return false; 00233 } 00234 00235 if (LocVT == MVT::i64 || LocVT == MVT::f64) { 00236 if (!RetCC_Hexagon64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) 00237 return false; 00238 } 00239 00240 return true; // CC didn't match. 00241 } 00242 00243 static bool RetCC_Hexagon32(unsigned ValNo, MVT ValVT, 00244 MVT LocVT, CCValAssign::LocInfo LocInfo, 00245 ISD::ArgFlagsTy ArgFlags, CCState &State) { 00246 00247 if (LocVT == MVT::i32 || LocVT == MVT::f32) { 00248 if (unsigned Reg = State.AllocateReg(Hexagon::R0)) { 00249 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 00250 return false; 00251 } 00252 } 00253 00254 unsigned Offset = State.AllocateStack(4, 4); 00255 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 00256 return false; 00257 } 00258 00259 static bool RetCC_Hexagon64(unsigned ValNo, MVT ValVT, 00260 MVT LocVT, CCValAssign::LocInfo LocInfo, 00261 ISD::ArgFlagsTy ArgFlags, CCState &State) { 00262 if (LocVT == MVT::i64 || LocVT == MVT::f64) { 00263 if (unsigned Reg = State.AllocateReg(Hexagon::D0)) { 00264 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 00265 return false; 00266 } 00267 } 00268 00269 unsigned Offset = State.AllocateStack(8, 8); 00270 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 00271 return false; 00272 } 00273 00274 SDValue 00275 HexagonTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) 00276 const { 00277 return SDValue(); 00278 } 00279 00280 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 00281 /// by "Src" to address "Dst" of size "Size". Alignment information is 00282 /// specified by the specific parameter attribute. The copy will be passed as 00283 /// a byval function parameter. Sometimes what we are copying is the end of a 00284 /// larger object, the part that does not fit in registers. 00285 static SDValue 00286 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 00287 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 00288 SDLoc dl) { 00289 00290 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 00291 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 00292 /*isVolatile=*/false, /*AlwaysInline=*/false, 00293 MachinePointerInfo(), MachinePointerInfo()); 00294 } 00295 00296 00297 // LowerReturn - Lower ISD::RET. If a struct is larger than 8 bytes and is 00298 // passed by value, the function prototype is modified to return void and 00299 // the value is stored in memory pointed by a pointer passed by caller. 00300 SDValue 00301 HexagonTargetLowering::LowerReturn(SDValue Chain, 00302 CallingConv::ID CallConv, bool isVarArg, 00303 const SmallVectorImpl<ISD::OutputArg> &Outs, 00304 const SmallVectorImpl<SDValue> &OutVals, 00305 SDLoc dl, SelectionDAG &DAG) const { 00306 00307 // CCValAssign - represent the assignment of the return value to locations. 00308 SmallVector<CCValAssign, 16> RVLocs; 00309 00310 // CCState - Info about the registers and stack slot. 00311 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 00312 getTargetMachine(), RVLocs, *DAG.getContext()); 00313 00314 // Analyze return values of ISD::RET 00315 CCInfo.AnalyzeReturn(Outs, RetCC_Hexagon); 00316 00317 SDValue Flag; 00318 SmallVector<SDValue, 4> RetOps(1, Chain); 00319 00320 // Copy the result values into the output registers. 00321 for (unsigned i = 0; i != RVLocs.size(); ++i) { 00322 CCValAssign &VA = RVLocs[i]; 00323 00324 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag); 00325 00326 // Guarantee that all emitted copies are stuck together with flags. 00327 Flag = Chain.getValue(1); 00328 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 00329 } 00330 00331 RetOps[0] = Chain; // Update chain. 00332 00333 // Add the flag if we have it. 00334 if (Flag.getNode()) 00335 RetOps.push_back(Flag); 00336 00337 return DAG.getNode(HexagonISD::RET_FLAG, dl, MVT::Other, 00338 &RetOps[0], RetOps.size()); 00339 } 00340 00341 00342 00343 00344 /// LowerCallResult - Lower the result values of an ISD::CALL into the 00345 /// appropriate copies out of appropriate physical registers. This assumes that 00346 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call 00347 /// being lowered. Returns a SDNode with the same number of values as the 00348 /// ISD::CALL. 00349 SDValue 00350 HexagonTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 00351 CallingConv::ID CallConv, bool isVarArg, 00352 const 00353 SmallVectorImpl<ISD::InputArg> &Ins, 00354 SDLoc dl, SelectionDAG &DAG, 00355 SmallVectorImpl<SDValue> &InVals, 00356 const SmallVectorImpl<SDValue> &OutVals, 00357 SDValue Callee) const { 00358 00359 // Assign locations to each value returned by this call. 00360 SmallVector<CCValAssign, 16> RVLocs; 00361 00362 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 00363 getTargetMachine(), RVLocs, *DAG.getContext()); 00364 00365 CCInfo.AnalyzeCallResult(Ins, RetCC_Hexagon); 00366 00367 // Copy all of the result registers out of their specified physreg. 00368 for (unsigned i = 0; i != RVLocs.size(); ++i) { 00369 Chain = DAG.getCopyFromReg(Chain, dl, 00370 RVLocs[i].getLocReg(), 00371 RVLocs[i].getValVT(), InFlag).getValue(1); 00372 InFlag = Chain.getValue(2); 00373 InVals.push_back(Chain.getValue(0)); 00374 } 00375 00376 return Chain; 00377 } 00378 00379 /// LowerCall - Functions arguments are copied from virtual regs to 00380 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 00381 SDValue 00382 HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 00383 SmallVectorImpl<SDValue> &InVals) const { 00384 SelectionDAG &DAG = CLI.DAG; 00385 SDLoc &dl = CLI.DL; 00386 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs; 00387 SmallVector<SDValue, 32> &OutVals = CLI.OutVals; 00388 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins; 00389 SDValue Chain = CLI.Chain; 00390 SDValue Callee = CLI.Callee; 00391 bool &isTailCall = CLI.IsTailCall; 00392 CallingConv::ID CallConv = CLI.CallConv; 00393 bool isVarArg = CLI.IsVarArg; 00394 00395 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet(); 00396 00397 // Analyze operands of the call, assigning locations to each operand. 00398 SmallVector<CCValAssign, 16> ArgLocs; 00399 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 00400 getTargetMachine(), ArgLocs, *DAG.getContext()); 00401 00402 // Check for varargs. 00403 NumNamedVarArgParams = -1; 00404 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Callee)) 00405 { 00406 const Function* CalleeFn = NULL; 00407 Callee = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, MVT::i32); 00408 if ((CalleeFn = dyn_cast<Function>(GA->getGlobal()))) 00409 { 00410 // If a function has zero args and is a vararg function, that's 00411 // disallowed so it must be an undeclared function. Do not assume 00412 // varargs if the callee is undefined. 00413 if (CalleeFn->isVarArg() && 00414 CalleeFn->getFunctionType()->getNumParams() != 0) { 00415 NumNamedVarArgParams = CalleeFn->getFunctionType()->getNumParams(); 00416 } 00417 } 00418 } 00419 00420 if (NumNamedVarArgParams > 0) 00421 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon_VarArg); 00422 else 00423 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon); 00424 00425 00426 if(isTailCall) { 00427 bool StructAttrFlag = 00428 DAG.getMachineFunction().getFunction()->hasStructRetAttr(); 00429 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, 00430 isVarArg, IsStructRet, 00431 StructAttrFlag, 00432 Outs, OutVals, Ins, DAG); 00433 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i){ 00434 CCValAssign &VA = ArgLocs[i]; 00435 if (VA.isMemLoc()) { 00436 isTailCall = false; 00437 break; 00438 } 00439 } 00440 if (isTailCall) { 00441 DEBUG(dbgs () << "Eligible for Tail Call\n"); 00442 } else { 00443 DEBUG(dbgs () << 00444 "Argument must be passed on stack. Not eligible for Tail Call\n"); 00445 } 00446 } 00447 // Get a count of how many bytes are to be pushed on the stack. 00448 unsigned NumBytes = CCInfo.getNextStackOffset(); 00449 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass; 00450 SmallVector<SDValue, 8> MemOpChains; 00451 00452 SDValue StackPtr = 00453 DAG.getCopyFromReg(Chain, dl, TM.getRegisterInfo()->getStackRegister(), 00454 getPointerTy()); 00455 00456 // Walk the register/memloc assignments, inserting copies/loads. 00457 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 00458 CCValAssign &VA = ArgLocs[i]; 00459 SDValue Arg = OutVals[i]; 00460 ISD::ArgFlagsTy Flags = Outs[i].Flags; 00461 00462 // Promote the value if needed. 00463 switch (VA.getLocInfo()) { 00464 default: 00465 // Loc info must be one of Full, SExt, ZExt, or AExt. 00466 llvm_unreachable("Unknown loc info!"); 00467 case CCValAssign::Full: 00468 break; 00469 case CCValAssign::SExt: 00470 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 00471 break; 00472 case CCValAssign::ZExt: 00473 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 00474 break; 00475 case CCValAssign::AExt: 00476 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 00477 break; 00478 } 00479 00480 if (VA.isMemLoc()) { 00481 unsigned LocMemOffset = VA.getLocMemOffset(); 00482 SDValue PtrOff = DAG.getConstant(LocMemOffset, StackPtr.getValueType()); 00483 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 00484 00485 if (Flags.isByVal()) { 00486 // The argument is a struct passed by value. According to LLVM, "Arg" 00487 // is is pointer. 00488 MemOpChains.push_back(CreateCopyOfByValArgument(Arg, PtrOff, Chain, 00489 Flags, DAG, dl)); 00490 } else { 00491 // The argument is not passed by value. "Arg" is a buildin type. It is 00492 // not a pointer. 00493 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 00494 MachinePointerInfo(),false, false, 00495 0)); 00496 } 00497 continue; 00498 } 00499 00500 // Arguments that can be passed on register must be kept at RegsToPass 00501 // vector. 00502 if (VA.isRegLoc()) { 00503 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 00504 } 00505 } 00506 00507 // Transform all store nodes into one single node because all store 00508 // nodes are independent of each other. 00509 if (!MemOpChains.empty()) { 00510 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOpChains[0], 00511 MemOpChains.size()); 00512 } 00513 00514 if (!isTailCall) 00515 Chain = DAG.getCALLSEQ_START(Chain, DAG.getConstant(NumBytes, 00516 getPointerTy(), true), 00517 dl); 00518 00519 // Build a sequence of copy-to-reg nodes chained together with token 00520 // chain and flag operands which copy the outgoing args into registers. 00521 // The InFlag in necessary since all emitted instructions must be 00522 // stuck together. 00523 SDValue InFlag; 00524 if (!isTailCall) { 00525 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 00526 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 00527 RegsToPass[i].second, InFlag); 00528 InFlag = Chain.getValue(1); 00529 } 00530 } 00531 00532 // For tail calls lower the arguments to the 'real' stack slot. 00533 if (isTailCall) { 00534 // Force all the incoming stack arguments to be loaded from the stack 00535 // before any new outgoing arguments are stored to the stack, because the 00536 // outgoing stack slots may alias the incoming argument stack slots, and 00537 // the alias isn't otherwise explicit. This is slightly more conservative 00538 // than necessary, because it means that each store effectively depends 00539 // on every argument instead of just those arguments it would clobber. 00540 // 00541 // Do not flag preceding copytoreg stuff together with the following stuff. 00542 InFlag = SDValue(); 00543 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 00544 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 00545 RegsToPass[i].second, InFlag); 00546 InFlag = Chain.getValue(1); 00547 } 00548 InFlag =SDValue(); 00549 } 00550 00551 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 00552 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 00553 // node so that legalize doesn't hack it. 00554 if (flag_aligned_memcpy) { 00555 const char *MemcpyName = 00556 "__hexagon_memcpy_likely_aligned_min32bytes_mult8bytes"; 00557 Callee = 00558 DAG.getTargetExternalSymbol(MemcpyName, getPointerTy()); 00559 flag_aligned_memcpy = false; 00560 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 00561 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy()); 00562 } else if (ExternalSymbolSDNode *S = 00563 dyn_cast<ExternalSymbolSDNode>(Callee)) { 00564 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy()); 00565 } 00566 00567 // Returns a chain & a flag for retval copy to use. 00568 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 00569 SmallVector<SDValue, 8> Ops; 00570 Ops.push_back(Chain); 00571 Ops.push_back(Callee); 00572 00573 // Add argument registers to the end of the list so that they are 00574 // known live into the call. 00575 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 00576 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 00577 RegsToPass[i].second.getValueType())); 00578 } 00579 00580 if (InFlag.getNode()) { 00581 Ops.push_back(InFlag); 00582 } 00583 00584 if (isTailCall) 00585 return DAG.getNode(HexagonISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size()); 00586 00587 Chain = DAG.getNode(HexagonISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); 00588 InFlag = Chain.getValue(1); 00589 00590 // Create the CALLSEQ_END node. 00591 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 00592 DAG.getIntPtrConstant(0, true), InFlag, dl); 00593 InFlag = Chain.getValue(1); 00594 00595 // Handle result values, copying them out of physregs into vregs that we 00596 // return. 00597 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG, 00598 InVals, OutVals, Callee); 00599 } 00600 00601 static bool getIndexedAddressParts(SDNode *Ptr, EVT VT, 00602 bool isSEXTLoad, SDValue &Base, 00603 SDValue &Offset, bool &isInc, 00604 SelectionDAG &DAG) { 00605 if (Ptr->getOpcode() != ISD::ADD) 00606 return false; 00607 00608 if (VT == MVT::i64 || VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) { 00609 isInc = (Ptr->getOpcode() == ISD::ADD); 00610 Base = Ptr->getOperand(0); 00611 Offset = Ptr->getOperand(1); 00612 // Ensure that Offset is a constant. 00613 return (isa<ConstantSDNode>(Offset)); 00614 } 00615 00616 return false; 00617 } 00618 00619 // TODO: Put this function along with the other isS* functions in 00620 // HexagonISelDAGToDAG.cpp into a common file. Or better still, use the 00621 // functions defined in HexagonOperands.td. 00622 static bool Is_PostInc_S4_Offset(SDNode * S, int ShiftAmount) { 00623 ConstantSDNode *N = cast<ConstantSDNode>(S); 00624 00625 // immS4 predicate - True if the immediate fits in a 4-bit sign extended. 00626 // field. 00627 int64_t v = (int64_t)N->getSExtValue(); 00628 int64_t m = 0; 00629 if (ShiftAmount > 0) { 00630 m = v % ShiftAmount; 00631 v = v >> ShiftAmount; 00632 } 00633 return (v <= 7) && (v >= -8) && (m == 0); 00634 } 00635 00636 /// getPostIndexedAddressParts - returns true by value, base pointer and 00637 /// offset pointer and addressing mode by reference if this node can be 00638 /// combined with a load / store to form a post-indexed load / store. 00639 bool HexagonTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op, 00640 SDValue &Base, 00641 SDValue &Offset, 00642 ISD::MemIndexedMode &AM, 00643 SelectionDAG &DAG) const 00644 { 00645 EVT VT; 00646 SDValue Ptr; 00647 bool isSEXTLoad = false; 00648 00649 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 00650 VT = LD->getMemoryVT(); 00651 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; 00652 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 00653 VT = ST->getMemoryVT(); 00654 if (ST->getValue().getValueType() == MVT::i64 && ST->isTruncatingStore()) { 00655 return false; 00656 } 00657 } else { 00658 return false; 00659 } 00660 00661 bool isInc = false; 00662 bool isLegal = getIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset, 00663 isInc, DAG); 00664 // ShiftAmount = number of left-shifted bits in the Hexagon instruction. 00665 int ShiftAmount = VT.getSizeInBits() / 16; 00666 if (isLegal && Is_PostInc_S4_Offset(Offset.getNode(), ShiftAmount)) { 00667 AM = isInc ? ISD::POST_INC : ISD::POST_DEC; 00668 return true; 00669 } 00670 00671 return false; 00672 } 00673 00674 SDValue HexagonTargetLowering::LowerINLINEASM(SDValue Op, 00675 SelectionDAG &DAG) const { 00676 SDNode *Node = Op.getNode(); 00677 MachineFunction &MF = DAG.getMachineFunction(); 00678 HexagonMachineFunctionInfo *FuncInfo = 00679 MF.getInfo<HexagonMachineFunctionInfo>(); 00680 switch (Node->getOpcode()) { 00681 case ISD::INLINEASM: { 00682 unsigned NumOps = Node->getNumOperands(); 00683 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue) 00684 --NumOps; // Ignore the flag operand. 00685 00686 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) { 00687 if (FuncInfo->hasClobberLR()) 00688 break; 00689 unsigned Flags = 00690 cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue(); 00691 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags); 00692 ++i; // Skip the ID value. 00693 00694 switch (InlineAsm::getKind(Flags)) { 00695 default: llvm_unreachable("Bad flags!"); 00696 case InlineAsm::Kind_RegDef: 00697 case InlineAsm::Kind_RegUse: 00698 case InlineAsm::Kind_Imm: 00699 case InlineAsm::Kind_Clobber: 00700 case InlineAsm::Kind_Mem: { 00701 for (; NumVals; --NumVals, ++i) {} 00702 break; 00703 } 00704 case InlineAsm::Kind_RegDefEarlyClobber: { 00705 for (; NumVals; --NumVals, ++i) { 00706 unsigned Reg = 00707 cast<RegisterSDNode>(Node->getOperand(i))->getReg(); 00708 00709 // Check it to be lr 00710 if (Reg == TM.getRegisterInfo()->getRARegister()) { 00711 FuncInfo->setHasClobberLR(true); 00712 break; 00713 } 00714 } 00715 break; 00716 } 00717 } 00718 } 00719 } 00720 } // Node->getOpcode 00721 return Op; 00722 } 00723 00724 00725 // 00726 // Taken from the XCore backend. 00727 // 00728 SDValue HexagonTargetLowering:: 00729 LowerBR_JT(SDValue Op, SelectionDAG &DAG) const 00730 { 00731 SDValue Chain = Op.getOperand(0); 00732 SDValue Table = Op.getOperand(1); 00733 SDValue Index = Op.getOperand(2); 00734 SDLoc dl(Op); 00735 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table); 00736 unsigned JTI = JT->getIndex(); 00737 MachineFunction &MF = DAG.getMachineFunction(); 00738 const MachineJumpTableInfo *MJTI = MF.getJumpTableInfo(); 00739 SDValue TargetJT = DAG.getTargetJumpTable(JT->getIndex(), MVT::i32); 00740 00741 // Mark all jump table targets as address taken. 00742 const std::vector<MachineJumpTableEntry> &JTE = MJTI->getJumpTables(); 00743 const std::vector<MachineBasicBlock*> &JTBBs = JTE[JTI].MBBs; 00744 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) { 00745 MachineBasicBlock *MBB = JTBBs[i]; 00746 MBB->setHasAddressTaken(); 00747 // This line is needed to set the hasAddressTaken flag on the BasicBlock 00748 // object. 00749 BlockAddress::get(const_cast<BasicBlock *>(MBB->getBasicBlock())); 00750 } 00751 00752 SDValue JumpTableBase = DAG.getNode(HexagonISD::WrapperJT, dl, 00753 getPointerTy(), TargetJT); 00754 SDValue ShiftIndex = DAG.getNode(ISD::SHL, dl, MVT::i32, Index, 00755 DAG.getConstant(2, MVT::i32)); 00756 SDValue JTAddress = DAG.getNode(ISD::ADD, dl, MVT::i32, JumpTableBase, 00757 ShiftIndex); 00758 SDValue LoadTarget = DAG.getLoad(MVT::i32, dl, Chain, JTAddress, 00759 MachinePointerInfo(), false, false, false, 00760 0); 00761 return DAG.getNode(HexagonISD::BR_JT, dl, MVT::Other, Chain, LoadTarget); 00762 } 00763 00764 00765 SDValue 00766 HexagonTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 00767 SelectionDAG &DAG) const { 00768 SDValue Chain = Op.getOperand(0); 00769 SDValue Size = Op.getOperand(1); 00770 SDLoc dl(Op); 00771 00772 unsigned SPReg = getStackPointerRegisterToSaveRestore(); 00773 00774 // Get a reference to the stack pointer. 00775 SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, SPReg, MVT::i32); 00776 00777 // Subtract the dynamic size from the actual stack size to 00778 // obtain the new stack size. 00779 SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i32, StackPointer, Size); 00780 00781 // 00782 // For Hexagon, the outgoing memory arguments area should be on top of the 00783 // alloca area on the stack i.e., the outgoing memory arguments should be 00784 // at a lower address than the alloca area. Move the alloca area down the 00785 // stack by adding back the space reserved for outgoing arguments to SP 00786 // here. 00787 // 00788 // We do not know what the size of the outgoing args is at this point. 00789 // So, we add a pseudo instruction ADJDYNALLOC that will adjust the 00790 // stack pointer. We patch this instruction with the correct, known 00791 // offset in emitPrologue(). 00792 // 00793 // Use a placeholder immediate (zero) for now. This will be patched up 00794 // by emitPrologue(). 00795 SDValue ArgAdjust = DAG.getNode(HexagonISD::ADJDYNALLOC, dl, 00796 MVT::i32, 00797 Sub, 00798 DAG.getConstant(0, MVT::i32)); 00799 00800 // The Sub result contains the new stack start address, so it 00801 // must be placed in the stack pointer register. 00802 SDValue CopyChain = DAG.getCopyToReg(Chain, dl, 00803 TM.getRegisterInfo()->getStackRegister(), 00804 Sub); 00805 00806 SDValue Ops[2] = { ArgAdjust, CopyChain }; 00807 return DAG.getMergeValues(Ops, 2, dl); 00808 } 00809 00810 SDValue 00811 HexagonTargetLowering::LowerFormalArguments(SDValue Chain, 00812 CallingConv::ID CallConv, 00813 bool isVarArg, 00814 const 00815 SmallVectorImpl<ISD::InputArg> &Ins, 00816 SDLoc dl, SelectionDAG &DAG, 00817 SmallVectorImpl<SDValue> &InVals) 00818 const { 00819 00820 MachineFunction &MF = DAG.getMachineFunction(); 00821 MachineFrameInfo *MFI = MF.getFrameInfo(); 00822 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 00823 HexagonMachineFunctionInfo *FuncInfo = 00824 MF.getInfo<HexagonMachineFunctionInfo>(); 00825 00826 00827 // Assign locations to all of the incoming arguments. 00828 SmallVector<CCValAssign, 16> ArgLocs; 00829 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 00830 getTargetMachine(), ArgLocs, *DAG.getContext()); 00831 00832 CCInfo.AnalyzeFormalArguments(Ins, CC_Hexagon); 00833 00834 // For LLVM, in the case when returning a struct by value (>8byte), 00835 // the first argument is a pointer that points to the location on caller's 00836 // stack where the return value will be stored. For Hexagon, the location on 00837 // caller's stack is passed only when the struct size is smaller than (and 00838 // equal to) 8 bytes. If not, no address will be passed into callee and 00839 // callee return the result direclty through R0/R1. 00840 00841 SmallVector<SDValue, 4> MemOps; 00842 00843 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 00844 CCValAssign &VA = ArgLocs[i]; 00845 ISD::ArgFlagsTy Flags = Ins[i].Flags; 00846 unsigned ObjSize; 00847 unsigned StackLocation; 00848 int FI; 00849 00850 if ( (VA.isRegLoc() && !Flags.isByVal()) 00851 || (VA.isRegLoc() && Flags.isByVal() && Flags.getByValSize() > 8)) { 00852 // Arguments passed in registers 00853 // 1. int, long long, ptr args that get allocated in register. 00854 // 2. Large struct that gets an register to put its address in. 00855 EVT RegVT = VA.getLocVT(); 00856 if (RegVT == MVT::i8 || RegVT == MVT::i16 || 00857 RegVT == MVT::i32 || RegVT == MVT::f32) { 00858 unsigned VReg = 00859 RegInfo.createVirtualRegister(&Hexagon::IntRegsRegClass); 00860 RegInfo.addLiveIn(VA.getLocReg(), VReg); 00861 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); 00862 } else if (RegVT == MVT::i64) { 00863 unsigned VReg = 00864 RegInfo.createVirtualRegister(&Hexagon::DoubleRegsRegClass); 00865 RegInfo.addLiveIn(VA.getLocReg(), VReg); 00866 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); 00867 } else { 00868 assert (0); 00869 } 00870 } else if (VA.isRegLoc() && Flags.isByVal() && Flags.getByValSize() <= 8) { 00871 assert (0 && "ByValSize must be bigger than 8 bytes"); 00872 } else { 00873 // Sanity check. 00874 assert(VA.isMemLoc()); 00875 00876 if (Flags.isByVal()) { 00877 // If it's a byval parameter, then we need to compute the 00878 // "real" size, not the size of the pointer. 00879 ObjSize = Flags.getByValSize(); 00880 } else { 00881 ObjSize = VA.getLocVT().getStoreSizeInBits() >> 3; 00882 } 00883 00884 StackLocation = HEXAGON_LRFP_SIZE + VA.getLocMemOffset(); 00885 // Create the frame index object for this incoming parameter... 00886 FI = MFI->CreateFixedObject(ObjSize, StackLocation, true); 00887 00888 // Create the SelectionDAG nodes cordl, responding to a load 00889 // from this parameter. 00890 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); 00891 00892 if (Flags.isByVal()) { 00893 // If it's a pass-by-value aggregate, then do not dereference the stack 00894 // location. Instead, we should generate a reference to the stack 00895 // location. 00896 InVals.push_back(FIN); 00897 } else { 00898 InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN, 00899 MachinePointerInfo(), false, false, 00900 false, 0)); 00901 } 00902 } 00903 } 00904 00905 if (!MemOps.empty()) 00906 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOps[0], 00907 MemOps.size()); 00908 00909 if (isVarArg) { 00910 // This will point to the next argument passed via stack. 00911 int FrameIndex = MFI->CreateFixedObject(Hexagon_PointerSize, 00912 HEXAGON_LRFP_SIZE + 00913 CCInfo.getNextStackOffset(), 00914 true); 00915 FuncInfo->setVarArgsFrameIndex(FrameIndex); 00916 } 00917 00918 return Chain; 00919 } 00920 00921 SDValue 00922 HexagonTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { 00923 // VASTART stores the address of the VarArgsFrameIndex slot into the 00924 // memory location argument. 00925 MachineFunction &MF = DAG.getMachineFunction(); 00926 HexagonMachineFunctionInfo *QFI = MF.getInfo<HexagonMachineFunctionInfo>(); 00927 SDValue Addr = DAG.getFrameIndex(QFI->getVarArgsFrameIndex(), MVT::i32); 00928 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 00929 return DAG.getStore(Op.getOperand(0), SDLoc(Op), Addr, 00930 Op.getOperand(1), MachinePointerInfo(SV), false, 00931 false, 0); 00932 } 00933 00934 SDValue 00935 HexagonTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { 00936 SDValue LHS = Op.getOperand(0); 00937 SDValue RHS = Op.getOperand(1); 00938 SDValue CC = Op.getOperand(4); 00939 SDValue TrueVal = Op.getOperand(2); 00940 SDValue FalseVal = Op.getOperand(3); 00941 SDLoc dl(Op); 00942 SDNode* OpNode = Op.getNode(); 00943 EVT SVT = OpNode->getValueType(0); 00944 00945 SDValue Cond = DAG.getNode(ISD::SETCC, dl, MVT::i1, LHS, RHS, CC); 00946 return DAG.getNode(ISD::SELECT, dl, SVT, Cond, TrueVal, FalseVal); 00947 } 00948 00949 SDValue 00950 HexagonTargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const { 00951 EVT ValTy = Op.getValueType(); 00952 SDLoc dl(Op); 00953 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 00954 SDValue Res; 00955 if (CP->isMachineConstantPoolEntry()) 00956 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), ValTy, 00957 CP->getAlignment()); 00958 else 00959 Res = DAG.getTargetConstantPool(CP->getConstVal(), ValTy, 00960 CP->getAlignment()); 00961 return DAG.getNode(HexagonISD::CONST32, dl, ValTy, Res); 00962 } 00963 00964 SDValue 00965 HexagonTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const { 00966 const TargetRegisterInfo *TRI = TM.getRegisterInfo(); 00967 MachineFunction &MF = DAG.getMachineFunction(); 00968 MachineFrameInfo *MFI = MF.getFrameInfo(); 00969 MFI->setReturnAddressIsTaken(true); 00970 00971 EVT VT = Op.getValueType(); 00972 SDLoc dl(Op); 00973 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 00974 if (Depth) { 00975 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 00976 SDValue Offset = DAG.getConstant(4, MVT::i32); 00977 return DAG.getLoad(VT, dl, DAG.getEntryNode(), 00978 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset), 00979 MachinePointerInfo(), false, false, false, 0); 00980 } 00981 00982 // Return LR, which contains the return address. Mark it an implicit live-in. 00983 unsigned Reg = MF.addLiveIn(TRI->getRARegister(), getRegClassFor(MVT::i32)); 00984 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT); 00985 } 00986 00987 SDValue 00988 HexagonTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 00989 const HexagonRegisterInfo *TRI = TM.getRegisterInfo(); 00990 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 00991 MFI->setFrameAddressIsTaken(true); 00992 00993 EVT VT = Op.getValueType(); 00994 SDLoc dl(Op); 00995 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 00996 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, 00997 TRI->getFrameRegister(), VT); 00998 while (Depth--) 00999 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, 01000 MachinePointerInfo(), 01001 false, false, false, 0); 01002 return FrameAddr; 01003 } 01004 01005 SDValue HexagonTargetLowering::LowerATOMIC_FENCE(SDValue Op, 01006 SelectionDAG& DAG) const { 01007 SDLoc dl(Op); 01008 return DAG.getNode(HexagonISD::BARRIER, dl, MVT::Other, Op.getOperand(0)); 01009 } 01010 01011 01012 SDValue HexagonTargetLowering::LowerGLOBALADDRESS(SDValue Op, 01013 SelectionDAG &DAG) const { 01014 SDValue Result; 01015 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 01016 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); 01017 SDLoc dl(Op); 01018 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset); 01019 01020 const HexagonTargetObjectFile &TLOF = 01021 static_cast<const HexagonTargetObjectFile &>(getObjFileLowering()); 01022 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) { 01023 return DAG.getNode(HexagonISD::CONST32_GP, dl, getPointerTy(), Result); 01024 } 01025 01026 return DAG.getNode(HexagonISD::CONST32, dl, getPointerTy(), Result); 01027 } 01028 01029 SDValue 01030 HexagonTargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const { 01031 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 01032 SDValue BA_SD = DAG.getTargetBlockAddress(BA, MVT::i32); 01033 SDLoc dl(Op); 01034 return DAG.getNode(HexagonISD::CONST32_GP, dl, getPointerTy(), BA_SD); 01035 } 01036 01037 //===----------------------------------------------------------------------===// 01038 // TargetLowering Implementation 01039 //===----------------------------------------------------------------------===// 01040 01041 HexagonTargetLowering::HexagonTargetLowering(HexagonTargetMachine 01042 &targetmachine) 01043 : TargetLowering(targetmachine, new HexagonTargetObjectFile()), 01044 TM(targetmachine) { 01045 01046 const HexagonRegisterInfo* QRI = TM.getRegisterInfo(); 01047 01048 // Set up the register classes. 01049 addRegisterClass(MVT::i32, &Hexagon::IntRegsRegClass); 01050 addRegisterClass(MVT::i64, &Hexagon::DoubleRegsRegClass); 01051 01052 if (QRI->Subtarget.hasV5TOps()) { 01053 addRegisterClass(MVT::f32, &Hexagon::IntRegsRegClass); 01054 addRegisterClass(MVT::f64, &Hexagon::DoubleRegsRegClass); 01055 } 01056 01057 addRegisterClass(MVT::i1, &Hexagon::PredRegsRegClass); 01058 01059 computeRegisterProperties(); 01060 01061 // Align loop entry 01062 setPrefLoopAlignment(4); 01063 01064 // Limits for inline expansion of memcpy/memmove 01065 MaxStoresPerMemcpy = 6; 01066 MaxStoresPerMemmove = 6; 01067 01068 // 01069 // Library calls for unsupported operations 01070 // 01071 01072 setLibcallName(RTLIB::SINTTOFP_I128_F64, "__hexagon_floattidf"); 01073 setLibcallName(RTLIB::SINTTOFP_I128_F32, "__hexagon_floattisf"); 01074 01075 setLibcallName(RTLIB::FPTOUINT_F32_I128, "__hexagon_fixunssfti"); 01076 setLibcallName(RTLIB::FPTOUINT_F64_I128, "__hexagon_fixunsdfti"); 01077 01078 setLibcallName(RTLIB::FPTOSINT_F32_I128, "__hexagon_fixsfti"); 01079 setLibcallName(RTLIB::FPTOSINT_F64_I128, "__hexagon_fixdfti"); 01080 01081 setLibcallName(RTLIB::SDIV_I32, "__hexagon_divsi3"); 01082 setOperationAction(ISD::SDIV, MVT::i32, Expand); 01083 setLibcallName(RTLIB::SREM_I32, "__hexagon_umodsi3"); 01084 setOperationAction(ISD::SREM, MVT::i32, Expand); 01085 01086 setLibcallName(RTLIB::SDIV_I64, "__hexagon_divdi3"); 01087 setOperationAction(ISD::SDIV, MVT::i64, Expand); 01088 setLibcallName(RTLIB::SREM_I64, "__hexagon_moddi3"); 01089 setOperationAction(ISD::SREM, MVT::i64, Expand); 01090 01091 setLibcallName(RTLIB::UDIV_I32, "__hexagon_udivsi3"); 01092 setOperationAction(ISD::UDIV, MVT::i32, Expand); 01093 01094 setLibcallName(RTLIB::UDIV_I64, "__hexagon_udivdi3"); 01095 setOperationAction(ISD::UDIV, MVT::i64, Expand); 01096 01097 setLibcallName(RTLIB::UREM_I32, "__hexagon_umodsi3"); 01098 setOperationAction(ISD::UREM, MVT::i32, Expand); 01099 01100 setLibcallName(RTLIB::UREM_I64, "__hexagon_umoddi3"); 01101 setOperationAction(ISD::UREM, MVT::i64, Expand); 01102 01103 setLibcallName(RTLIB::DIV_F32, "__hexagon_divsf3"); 01104 setOperationAction(ISD::FDIV, MVT::f32, Expand); 01105 01106 setLibcallName(RTLIB::DIV_F64, "__hexagon_divdf3"); 01107 setOperationAction(ISD::FDIV, MVT::f64, Expand); 01108 01109 setOperationAction(ISD::FSQRT, MVT::f32, Expand); 01110 setOperationAction(ISD::FSQRT, MVT::f64, Expand); 01111 setOperationAction(ISD::FSIN, MVT::f32, Expand); 01112 setOperationAction(ISD::FSIN, MVT::f64, Expand); 01113 01114 if (QRI->Subtarget.hasV5TOps()) { 01115 // Hexagon V5 Support. 01116 setOperationAction(ISD::FADD, MVT::f32, Legal); 01117 setOperationAction(ISD::FADD, MVT::f64, Legal); 01118 setOperationAction(ISD::FP_EXTEND, MVT::f32, Legal); 01119 setCondCodeAction(ISD::SETOEQ, MVT::f32, Legal); 01120 setCondCodeAction(ISD::SETOEQ, MVT::f64, Legal); 01121 setCondCodeAction(ISD::SETUEQ, MVT::f32, Legal); 01122 setCondCodeAction(ISD::SETUEQ, MVT::f64, Legal); 01123 01124 setCondCodeAction(ISD::SETOGE, MVT::f32, Legal); 01125 setCondCodeAction(ISD::SETOGE, MVT::f64, Legal); 01126 setCondCodeAction(ISD::SETUGE, MVT::f32, Legal); 01127 setCondCodeAction(ISD::SETUGE, MVT::f64, Legal); 01128 01129 setCondCodeAction(ISD::SETOGT, MVT::f32, Legal); 01130 setCondCodeAction(ISD::SETOGT, MVT::f64, Legal); 01131 setCondCodeAction(ISD::SETUGT, MVT::f32, Legal); 01132 setCondCodeAction(ISD::SETUGT, MVT::f64, Legal); 01133 01134 setCondCodeAction(ISD::SETOLE, MVT::f32, Legal); 01135 setCondCodeAction(ISD::SETOLE, MVT::f64, Legal); 01136 setCondCodeAction(ISD::SETOLT, MVT::f32, Legal); 01137 setCondCodeAction(ISD::SETOLT, MVT::f64, Legal); 01138 01139 setOperationAction(ISD::ConstantFP, MVT::f32, Legal); 01140 setOperationAction(ISD::ConstantFP, MVT::f64, Legal); 01141 01142 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Promote); 01143 setOperationAction(ISD::FP_TO_SINT, MVT::i1, Promote); 01144 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote); 01145 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote); 01146 01147 setOperationAction(ISD::FP_TO_UINT, MVT::i8, Promote); 01148 setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote); 01149 setOperationAction(ISD::UINT_TO_FP, MVT::i8, Promote); 01150 setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote); 01151 01152 setOperationAction(ISD::FP_TO_UINT, MVT::i16, Promote); 01153 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote); 01154 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Promote); 01155 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote); 01156 01157 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal); 01158 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal); 01159 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal); 01160 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal); 01161 01162 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal); 01163 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal); 01164 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal); 01165 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal); 01166 01167 setOperationAction(ISD::FABS, MVT::f32, Legal); 01168 setOperationAction(ISD::FABS, MVT::f64, Expand); 01169 01170 setOperationAction(ISD::FNEG, MVT::f32, Legal); 01171 setOperationAction(ISD::FNEG, MVT::f64, Expand); 01172 } else { 01173 01174 // Expand fp<->uint. 01175 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Expand); 01176 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 01177 01178 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); 01179 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 01180 01181 setLibcallName(RTLIB::SINTTOFP_I64_F32, "__hexagon_floatdisf"); 01182 setLibcallName(RTLIB::UINTTOFP_I64_F32, "__hexagon_floatundisf"); 01183 01184 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__hexagon_floatunsisf"); 01185 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__hexagon_floatsisf"); 01186 01187 setLibcallName(RTLIB::SINTTOFP_I64_F64, "__hexagon_floatdidf"); 01188 setLibcallName(RTLIB::UINTTOFP_I64_F64, "__hexagon_floatundidf"); 01189 01190 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__hexagon_floatunsidf"); 01191 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__hexagon_floatsidf"); 01192 01193 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__hexagon_fixunssfsi"); 01194 setLibcallName(RTLIB::FPTOUINT_F32_I64, "__hexagon_fixunssfdi"); 01195 01196 setLibcallName(RTLIB::FPTOSINT_F64_I64, "__hexagon_fixdfdi"); 01197 setLibcallName(RTLIB::FPTOSINT_F32_I64, "__hexagon_fixsfdi"); 01198 01199 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__hexagon_fixunsdfsi"); 01200 setLibcallName(RTLIB::FPTOUINT_F64_I64, "__hexagon_fixunsdfdi"); 01201 01202 setLibcallName(RTLIB::ADD_F64, "__hexagon_adddf3"); 01203 setOperationAction(ISD::FADD, MVT::f64, Expand); 01204 01205 setLibcallName(RTLIB::ADD_F32, "__hexagon_addsf3"); 01206 setOperationAction(ISD::FADD, MVT::f32, Expand); 01207 01208 setLibcallName(RTLIB::FPEXT_F32_F64, "__hexagon_extendsfdf2"); 01209 setOperationAction(ISD::FP_EXTEND, MVT::f32, Expand); 01210 01211 setLibcallName(RTLIB::OEQ_F32, "__hexagon_eqsf2"); 01212 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand); 01213 01214 setLibcallName(RTLIB::OEQ_F64, "__hexagon_eqdf2"); 01215 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand); 01216 01217 setLibcallName(RTLIB::OGE_F32, "__hexagon_gesf2"); 01218 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand); 01219 01220 setLibcallName(RTLIB::OGE_F64, "__hexagon_gedf2"); 01221 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand); 01222 01223 setLibcallName(RTLIB::OGT_F32, "__hexagon_gtsf2"); 01224 setCondCodeAction(ISD::SETOGT, MVT::f32, Expand); 01225 01226 setLibcallName(RTLIB::OGT_F64, "__hexagon_gtdf2"); 01227 setCondCodeAction(ISD::SETOGT, MVT::f64, Expand); 01228 01229 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__hexagon_fixdfsi"); 01230 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Expand); 01231 01232 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__hexagon_fixsfsi"); 01233 setOperationAction(ISD::FP_TO_SINT, MVT::f32, Expand); 01234 01235 setLibcallName(RTLIB::OLE_F64, "__hexagon_ledf2"); 01236 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand); 01237 01238 setLibcallName(RTLIB::OLE_F32, "__hexagon_lesf2"); 01239 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand); 01240 01241 setLibcallName(RTLIB::OLT_F64, "__hexagon_ltdf2"); 01242 setCondCodeAction(ISD::SETOLT, MVT::f64, Expand); 01243 01244 setLibcallName(RTLIB::OLT_F32, "__hexagon_ltsf2"); 01245 setCondCodeAction(ISD::SETOLT, MVT::f32, Expand); 01246 01247 setLibcallName(RTLIB::MUL_F64, "__hexagon_muldf3"); 01248 setOperationAction(ISD::FMUL, MVT::f64, Expand); 01249 01250 setLibcallName(RTLIB::MUL_F32, "__hexagon_mulsf3"); 01251 setOperationAction(ISD::MUL, MVT::f32, Expand); 01252 01253 setLibcallName(RTLIB::UNE_F64, "__hexagon_nedf2"); 01254 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand); 01255 01256 setLibcallName(RTLIB::UNE_F32, "__hexagon_nesf2"); 01257 01258 setLibcallName(RTLIB::SUB_F64, "__hexagon_subdf3"); 01259 setOperationAction(ISD::SUB, MVT::f64, Expand); 01260 01261 setLibcallName(RTLIB::SUB_F32, "__hexagon_subsf3"); 01262 setOperationAction(ISD::SUB, MVT::f32, Expand); 01263 01264 setLibcallName(RTLIB::FPROUND_F64_F32, "__hexagon_truncdfsf2"); 01265 setOperationAction(ISD::FP_ROUND, MVT::f64, Expand); 01266 01267 setLibcallName(RTLIB::UO_F64, "__hexagon_unorddf2"); 01268 setCondCodeAction(ISD::SETUO, MVT::f64, Expand); 01269 01270 setLibcallName(RTLIB::O_F64, "__hexagon_unorddf2"); 01271 setCondCodeAction(ISD::SETO, MVT::f64, Expand); 01272 01273 setLibcallName(RTLIB::O_F32, "__hexagon_unordsf2"); 01274 setCondCodeAction(ISD::SETO, MVT::f32, Expand); 01275 01276 setLibcallName(RTLIB::UO_F32, "__hexagon_unordsf2"); 01277 setCondCodeAction(ISD::SETUO, MVT::f32, Expand); 01278 01279 setOperationAction(ISD::FABS, MVT::f32, Expand); 01280 setOperationAction(ISD::FABS, MVT::f64, Expand); 01281 setOperationAction(ISD::FNEG, MVT::f32, Expand); 01282 setOperationAction(ISD::FNEG, MVT::f64, Expand); 01283 } 01284 01285 setLibcallName(RTLIB::SREM_I32, "__hexagon_modsi3"); 01286 setOperationAction(ISD::SREM, MVT::i32, Expand); 01287 01288 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal); 01289 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal); 01290 setIndexedLoadAction(ISD::POST_INC, MVT::i32, Legal); 01291 setIndexedLoadAction(ISD::POST_INC, MVT::i64, Legal); 01292 01293 setIndexedStoreAction(ISD::POST_INC, MVT::i8, Legal); 01294 setIndexedStoreAction(ISD::POST_INC, MVT::i16, Legal); 01295 setIndexedStoreAction(ISD::POST_INC, MVT::i32, Legal); 01296 setIndexedStoreAction(ISD::POST_INC, MVT::i64, Legal); 01297 01298 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); 01299 01300 // Turn FP extload into load/fextend. 01301 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 01302 // Hexagon has a i1 sign extending load. 01303 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Expand); 01304 // Turn FP truncstore into trunc + store. 01305 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 01306 01307 // Custom legalize GlobalAddress nodes into CONST32. 01308 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 01309 setOperationAction(ISD::GlobalAddress, MVT::i8, Custom); 01310 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 01311 // Truncate action? 01312 setOperationAction(ISD::TRUNCATE, MVT::i64, Expand); 01313 01314 // Hexagon doesn't have sext_inreg, replace them with shl/sra. 01315 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 01316 01317 // Hexagon has no REM or DIVREM operations. 01318 setOperationAction(ISD::UREM, MVT::i32, Expand); 01319 setOperationAction(ISD::SREM, MVT::i32, Expand); 01320 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 01321 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 01322 setOperationAction(ISD::SREM, MVT::i64, Expand); 01323 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); 01324 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); 01325 01326 setOperationAction(ISD::BSWAP, MVT::i64, Expand); 01327 01328 // Lower SELECT_CC to SETCC and SELECT. 01329 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 01330 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); 01331 01332 if (QRI->Subtarget.hasV5TOps()) { 01333 01334 // We need to make the operation type of SELECT node to be Custom, 01335 // such that we don't go into the infinite loop of 01336 // select -> setcc -> select_cc -> select loop. 01337 setOperationAction(ISD::SELECT, MVT::f32, Custom); 01338 setOperationAction(ISD::SELECT, MVT::f64, Custom); 01339 01340 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand); 01341 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); 01342 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); 01343 01344 } else { 01345 01346 // Hexagon has no select or setcc: expand to SELECT_CC. 01347 setOperationAction(ISD::SELECT, MVT::f32, Expand); 01348 setOperationAction(ISD::SELECT, MVT::f64, Expand); 01349 01350 // This is a workaround documented in DAGCombiner.cpp:2892 We don't 01351 // support SELECT_CC on every type. 01352 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); 01353 01354 } 01355 01356 if (EmitJumpTables) { 01357 setOperationAction(ISD::BR_JT, MVT::Other, Custom); 01358 } else { 01359 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 01360 } 01361 // Increase jump tables cutover to 5, was 4. 01362 setMinimumJumpTableEntries(5); 01363 01364 setOperationAction(ISD::BR_CC, MVT::f32, Expand); 01365 setOperationAction(ISD::BR_CC, MVT::f64, Expand); 01366 setOperationAction(ISD::BR_CC, MVT::i1, Expand); 01367 setOperationAction(ISD::BR_CC, MVT::i32, Expand); 01368 setOperationAction(ISD::BR_CC, MVT::i64, Expand); 01369 01370 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom); 01371 01372 setOperationAction(ISD::FSIN , MVT::f64, Expand); 01373 setOperationAction(ISD::FCOS , MVT::f64, Expand); 01374 setOperationAction(ISD::FREM , MVT::f64, Expand); 01375 setOperationAction(ISD::FSIN , MVT::f32, Expand); 01376 setOperationAction(ISD::FCOS , MVT::f32, Expand); 01377 setOperationAction(ISD::FREM , MVT::f32, Expand); 01378 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); 01379 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); 01380 01381 // In V4, we have double word add/sub with carry. The problem with 01382 // modelling this instruction is that it produces 2 results - Rdd and Px. 01383 // To model update of Px, we will have to use Defs[p0..p3] which will 01384 // cause any predicate live range to spill. So, we pretend we dont't 01385 // have these instructions. 01386 setOperationAction(ISD::ADDE, MVT::i8, Expand); 01387 setOperationAction(ISD::ADDE, MVT::i16, Expand); 01388 setOperationAction(ISD::ADDE, MVT::i32, Expand); 01389 setOperationAction(ISD::ADDE, MVT::i64, Expand); 01390 setOperationAction(ISD::SUBE, MVT::i8, Expand); 01391 setOperationAction(ISD::SUBE, MVT::i16, Expand); 01392 setOperationAction(ISD::SUBE, MVT::i32, Expand); 01393 setOperationAction(ISD::SUBE, MVT::i64, Expand); 01394 setOperationAction(ISD::ADDC, MVT::i8, Expand); 01395 setOperationAction(ISD::ADDC, MVT::i16, Expand); 01396 setOperationAction(ISD::ADDC, MVT::i32, Expand); 01397 setOperationAction(ISD::ADDC, MVT::i64, Expand); 01398 setOperationAction(ISD::SUBC, MVT::i8, Expand); 01399 setOperationAction(ISD::SUBC, MVT::i16, Expand); 01400 setOperationAction(ISD::SUBC, MVT::i32, Expand); 01401 setOperationAction(ISD::SUBC, MVT::i64, Expand); 01402 01403 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 01404 setOperationAction(ISD::CTPOP, MVT::i64, Expand); 01405 setOperationAction(ISD::CTTZ , MVT::i32, Expand); 01406 setOperationAction(ISD::CTTZ , MVT::i64, Expand); 01407 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand); 01408 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); 01409 setOperationAction(ISD::CTLZ , MVT::i32, Expand); 01410 setOperationAction(ISD::CTLZ , MVT::i64, Expand); 01411 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand); 01412 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand); 01413 setOperationAction(ISD::ROTL , MVT::i32, Expand); 01414 setOperationAction(ISD::ROTR , MVT::i32, Expand); 01415 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 01416 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 01417 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 01418 setOperationAction(ISD::FPOW , MVT::f64, Expand); 01419 setOperationAction(ISD::FPOW , MVT::f32, Expand); 01420 01421 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 01422 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 01423 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 01424 01425 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 01426 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 01427 01428 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); 01429 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); 01430 01431 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 01432 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 01433 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 01434 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 01435 01436 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom); 01437 01438 if (TM.getSubtargetImpl()->isSubtargetV2()) { 01439 setExceptionPointerRegister(Hexagon::R20); 01440 setExceptionSelectorRegister(Hexagon::R21); 01441 } else { 01442 setExceptionPointerRegister(Hexagon::R0); 01443 setExceptionSelectorRegister(Hexagon::R1); 01444 } 01445 01446 // VASTART needs to be custom lowered to use the VarArgsFrameIndex. 01447 setOperationAction(ISD::VASTART , MVT::Other, Custom); 01448 01449 // Use the default implementation. 01450 setOperationAction(ISD::VAARG , MVT::Other, Expand); 01451 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 01452 setOperationAction(ISD::VAEND , MVT::Other, Expand); 01453 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 01454 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand); 01455 01456 01457 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); 01458 setOperationAction(ISD::INLINEASM , MVT::Other, Custom); 01459 01460 setMinFunctionAlignment(2); 01461 01462 // Needed for DYNAMIC_STACKALLOC expansion. 01463 unsigned StackRegister = TM.getRegisterInfo()->getStackRegister(); 01464 setStackPointerRegisterToSaveRestore(StackRegister); 01465 setSchedulingPreference(Sched::VLIW); 01466 } 01467 01468 01469 const char* 01470 HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const { 01471 switch (Opcode) { 01472 default: return 0; 01473 case HexagonISD::CONST32: return "HexagonISD::CONST32"; 01474 case HexagonISD::CONST32_GP: return "HexagonISD::CONST32_GP"; 01475 case HexagonISD::CONST32_Int_Real: return "HexagonISD::CONST32_Int_Real"; 01476 case HexagonISD::ADJDYNALLOC: return "HexagonISD::ADJDYNALLOC"; 01477 case HexagonISD::CMPICC: return "HexagonISD::CMPICC"; 01478 case HexagonISD::CMPFCC: return "HexagonISD::CMPFCC"; 01479 case HexagonISD::BRICC: return "HexagonISD::BRICC"; 01480 case HexagonISD::BRFCC: return "HexagonISD::BRFCC"; 01481 case HexagonISD::SELECT_ICC: return "HexagonISD::SELECT_ICC"; 01482 case HexagonISD::SELECT_FCC: return "HexagonISD::SELECT_FCC"; 01483 case HexagonISD::Hi: return "HexagonISD::Hi"; 01484 case HexagonISD::Lo: return "HexagonISD::Lo"; 01485 case HexagonISD::FTOI: return "HexagonISD::FTOI"; 01486 case HexagonISD::ITOF: return "HexagonISD::ITOF"; 01487 case HexagonISD::CALL: return "HexagonISD::CALL"; 01488 case HexagonISD::RET_FLAG: return "HexagonISD::RET_FLAG"; 01489 case HexagonISD::BR_JT: return "HexagonISD::BR_JT"; 01490 case HexagonISD::TC_RETURN: return "HexagonISD::TC_RETURN"; 01491 case HexagonISD::EH_RETURN: return "HexagonISD::EH_RETURN"; 01492 } 01493 } 01494 01495 bool 01496 HexagonTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const { 01497 EVT MTy1 = EVT::getEVT(Ty1); 01498 EVT MTy2 = EVT::getEVT(Ty2); 01499 if (!MTy1.isSimple() || !MTy2.isSimple()) { 01500 return false; 01501 } 01502 return ((MTy1.getSimpleVT() == MVT::i64) && (MTy2.getSimpleVT() == MVT::i32)); 01503 } 01504 01505 bool HexagonTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { 01506 if (!VT1.isSimple() || !VT2.isSimple()) { 01507 return false; 01508 } 01509 return ((VT1.getSimpleVT() == MVT::i64) && (VT2.getSimpleVT() == MVT::i32)); 01510 } 01511 01512 SDValue 01513 HexagonTargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const { 01514 SDValue Chain = Op.getOperand(0); 01515 SDValue Offset = Op.getOperand(1); 01516 SDValue Handler = Op.getOperand(2); 01517 SDLoc dl(Op); 01518 01519 // Mark function as containing a call to EH_RETURN. 01520 HexagonMachineFunctionInfo *FuncInfo = 01521 DAG.getMachineFunction().getInfo<HexagonMachineFunctionInfo>(); 01522 FuncInfo->setHasEHReturn(); 01523 01524 unsigned OffsetReg = Hexagon::R28; 01525 01526 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), 01527 DAG.getRegister(Hexagon::R30, getPointerTy()), 01528 DAG.getIntPtrConstant(4)); 01529 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(), 01530 false, false, 0); 01531 Chain = DAG.getCopyToReg(Chain, dl, OffsetReg, Offset); 01532 01533 // Not needed we already use it as explict input to EH_RETURN. 01534 // MF.getRegInfo().addLiveOut(OffsetReg); 01535 01536 return DAG.getNode(HexagonISD::EH_RETURN, dl, MVT::Other, Chain); 01537 } 01538 01539 SDValue 01540 HexagonTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 01541 switch (Op.getOpcode()) { 01542 default: llvm_unreachable("Should not custom lower this!"); 01543 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 01544 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG); 01545 // Frame & Return address. Currently unimplemented. 01546 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 01547 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 01548 case ISD::GlobalTLSAddress: 01549 llvm_unreachable("TLS not implemented for Hexagon."); 01550 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG); 01551 case ISD::GlobalAddress: return LowerGLOBALADDRESS(Op, DAG); 01552 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 01553 case ISD::VASTART: return LowerVASTART(Op, DAG); 01554 case ISD::BR_JT: return LowerBR_JT(Op, DAG); 01555 01556 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 01557 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 01558 case ISD::SELECT: return Op; 01559 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 01560 case ISD::INLINEASM: return LowerINLINEASM(Op, DAG); 01561 01562 } 01563 } 01564 01565 01566 01567 //===----------------------------------------------------------------------===// 01568 // Hexagon Scheduler Hooks 01569 //===----------------------------------------------------------------------===// 01570 MachineBasicBlock * 01571 HexagonTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 01572 MachineBasicBlock *BB) 01573 const { 01574 switch (MI->getOpcode()) { 01575 case Hexagon::ADJDYNALLOC: { 01576 MachineFunction *MF = BB->getParent(); 01577 HexagonMachineFunctionInfo *FuncInfo = 01578 MF->getInfo<HexagonMachineFunctionInfo>(); 01579 FuncInfo->addAllocaAdjustInst(MI); 01580 return BB; 01581 } 01582 default: llvm_unreachable("Unexpected instr type to insert"); 01583 } // switch 01584 } 01585 01586 //===----------------------------------------------------------------------===// 01587 // Inline Assembly Support 01588 //===----------------------------------------------------------------------===// 01589 01590 std::pair<unsigned, const TargetRegisterClass*> 01591 HexagonTargetLowering::getRegForInlineAsmConstraint(const 01592 std::string &Constraint, 01593 EVT VT) const { 01594 if (Constraint.size() == 1) { 01595 switch (Constraint[0]) { 01596 case 'r': // R0-R31 01597 switch (VT.getSimpleVT().SimpleTy) { 01598 default: 01599 llvm_unreachable("getRegForInlineAsmConstraint Unhandled data type"); 01600 case MVT::i32: 01601 case MVT::i16: 01602 case MVT::i8: 01603 case MVT::f32: 01604 return std::make_pair(0U, &Hexagon::IntRegsRegClass); 01605 case MVT::i64: 01606 case MVT::f64: 01607 return std::make_pair(0U, &Hexagon::DoubleRegsRegClass); 01608 } 01609 default: 01610 llvm_unreachable("Unknown asm register class"); 01611 } 01612 } 01613 01614 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 01615 } 01616 01617 /// isFPImmLegal - Returns true if the target can instruction select the 01618 /// specified FP immediate natively. If false, the legalizer will 01619 /// materialize the FP immediate as a load from a constant pool. 01620 bool HexagonTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 01621 const HexagonRegisterInfo* QRI = TM.getRegisterInfo(); 01622 return QRI->Subtarget.hasV5TOps(); 01623 } 01624 01625 /// isLegalAddressingMode - Return true if the addressing mode represented by 01626 /// AM is legal for this target, for a load/store of the specified type. 01627 bool HexagonTargetLowering::isLegalAddressingMode(const AddrMode &AM, 01628 Type *Ty) const { 01629 // Allows a signed-extended 11-bit immediate field. 01630 if (AM.BaseOffs <= -(1LL << 13) || AM.BaseOffs >= (1LL << 13)-1) { 01631 return false; 01632 } 01633 01634 // No global is ever allowed as a base. 01635 if (AM.BaseGV) { 01636 return false; 01637 } 01638 01639 int Scale = AM.Scale; 01640 if (Scale < 0) Scale = -Scale; 01641 switch (Scale) { 01642 case 0: // No scale reg, "r+i", "r", or just "i". 01643 break; 01644 default: // No scaled addressing mode. 01645 return false; 01646 } 01647 return true; 01648 } 01649 01650 /// isLegalICmpImmediate - Return true if the specified immediate is legal 01651 /// icmp immediate, that is the target has icmp instructions which can compare 01652 /// a register against the immediate without having to materialize the 01653 /// immediate into a register. 01654 bool HexagonTargetLowering::isLegalICmpImmediate(int64_t Imm) const { 01655 return Imm >= -512 && Imm <= 511; 01656 } 01657 01658 /// IsEligibleForTailCallOptimization - Check whether the call is eligible 01659 /// for tail call optimization. Targets which want to do tail call 01660 /// optimization should implement this function. 01661 bool HexagonTargetLowering::IsEligibleForTailCallOptimization( 01662 SDValue Callee, 01663 CallingConv::ID CalleeCC, 01664 bool isVarArg, 01665 bool isCalleeStructRet, 01666 bool isCallerStructRet, 01667 const SmallVectorImpl<ISD::OutputArg> &Outs, 01668 const SmallVectorImpl<SDValue> &OutVals, 01669 const SmallVectorImpl<ISD::InputArg> &Ins, 01670 SelectionDAG& DAG) const { 01671 const Function *CallerF = DAG.getMachineFunction().getFunction(); 01672 CallingConv::ID CallerCC = CallerF->getCallingConv(); 01673 bool CCMatch = CallerCC == CalleeCC; 01674 01675 // *************************************************************************** 01676 // Look for obvious safe cases to perform tail call optimization that do not 01677 // require ABI changes. 01678 // *************************************************************************** 01679 01680 // If this is a tail call via a function pointer, then don't do it! 01681 if (!(dyn_cast<GlobalAddressSDNode>(Callee)) 01682 && !(dyn_cast<ExternalSymbolSDNode>(Callee))) { 01683 return false; 01684 } 01685 01686 // Do not optimize if the calling conventions do not match. 01687 if (!CCMatch) 01688 return false; 01689 01690 // Do not tail call optimize vararg calls. 01691 if (isVarArg) 01692 return false; 01693 01694 // Also avoid tail call optimization if either caller or callee uses struct 01695 // return semantics. 01696 if (isCalleeStructRet || isCallerStructRet) 01697 return false; 01698 01699 // In addition to the cases above, we also disable Tail Call Optimization if 01700 // the calling convention code that at least one outgoing argument needs to 01701 // go on the stack. We cannot check that here because at this point that 01702 // information is not available. 01703 return true; 01704 }