46#include "llvm/IR/IntrinsicsHexagon.h"
66#define DEBUG_TYPE "hexagon-lowering"
70 cl::desc(
"Control jump table emission on Hexagon target"));
74 cl::desc(
"Enable Hexagon SDNode scheduling"));
78 cl::desc(
"Set minimum jump tables"));
82 cl::desc(
"Convert constant loads to immediate values."));
86 cl::desc(
"Rewrite unaligned loads as a pair of aligned loads"));
91 cl::desc(
"Disable minimum alignment of 1 for "
92 "arguments passed by value on stack"));
100 Hexagon::R0, Hexagon::R1, Hexagon::R2,
101 Hexagon::R3, Hexagon::R4, Hexagon::R5
103 const unsigned NumArgRegs = std::size(ArgRegs);
104 unsigned RegNum = State.getFirstUnallocated(ArgRegs);
107 if (RegNum != NumArgRegs && RegNum % 2 == 1)
108 State.AllocateReg(ArgRegs[RegNum]);
116#include "HexagonGenCallingConv.inc"
120 unsigned &NumIntermediates,
MVT &RegisterVT)
const {
128 if (isBoolVector && !Subtarget.useHVXOps() && isPowerOf2 && NumElts >= 8) {
129 RegisterVT = MVT::v8i8;
130 IntermediateVT = MVT::v8i1;
131 NumIntermediates = NumElts / 8;
132 return NumIntermediates;
137 if (isBoolVector && Subtarget.useHVX64BOps() && isPowerOf2 && NumElts >= 64) {
138 RegisterVT = MVT::v64i8;
139 IntermediateVT = MVT::v64i1;
140 NumIntermediates = NumElts / 64;
141 return NumIntermediates;
146 if (isBoolVector && Subtarget.useHVX128BOps() && isPowerOf2 &&
148 RegisterVT = MVT::v128i8;
149 IntermediateVT = MVT::v128i1;
150 NumIntermediates = NumElts / 128;
151 return NumIntermediates;
155 Context, CC, VT, IntermediateVT, NumIntermediates, RegisterVT);
158std::pair<MVT, unsigned>
168 if (!Subtarget.useHVXOps() && NumElems >= 8)
169 return {MVT::v8i8, NumElems / 8};
171 if (Subtarget.useHVX64BOps() && NumElems >= 64)
172 return {MVT::v64i8, NumElems / 64};
174 if (Subtarget.useHVX128BOps() && NumElems >= 128)
175 return {MVT::v128i8, NumElems / 128};
185 auto [RegisterVT, NumRegisters] =
197 unsigned IntNo =
Op.getConstantOperandVal(0);
202 case Intrinsic::thread_pointer: {
204 return DAG.
getNode(HexagonISD::THREAD_POINTER, dl, PtrVT);
218 Align Alignment = Flags.getNonZeroByValAlign();
219 return DAG.
getMemcpy(Chain, dl, Dst, Src, SizeNode, Alignment, Alignment,
231 CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
234 return CCInfo.
CheckReturn(Outs, RetCC_Hexagon_HVX);
255 if (Subtarget.useHVXOps())
264 for (
unsigned i = 0; i != RVLocs.
size(); ++i) {
301 return DAG.
getNode(HexagonISD::RET_GLUE, dl, MVT::Other, RetOps);
313 .
Case(
"r0", Hexagon::R0)
314 .
Case(
"r1", Hexagon::R1)
315 .
Case(
"r2", Hexagon::R2)
316 .
Case(
"r3", Hexagon::R3)
317 .
Case(
"r4", Hexagon::R4)
318 .
Case(
"r5", Hexagon::R5)
319 .
Case(
"r6", Hexagon::R6)
320 .
Case(
"r7", Hexagon::R7)
321 .
Case(
"r8", Hexagon::R8)
322 .
Case(
"r9", Hexagon::R9)
323 .
Case(
"r10", Hexagon::R10)
324 .
Case(
"r11", Hexagon::R11)
325 .
Case(
"r12", Hexagon::R12)
326 .
Case(
"r13", Hexagon::R13)
327 .
Case(
"r14", Hexagon::R14)
328 .
Case(
"r15", Hexagon::R15)
329 .
Case(
"r16", Hexagon::R16)
330 .
Case(
"r17", Hexagon::R17)
331 .
Case(
"r18", Hexagon::R18)
332 .
Case(
"r19", Hexagon::R19)
333 .
Case(
"r20", Hexagon::R20)
334 .
Case(
"r21", Hexagon::R21)
335 .
Case(
"r22", Hexagon::R22)
336 .
Case(
"r23", Hexagon::R23)
337 .
Case(
"r24", Hexagon::R24)
338 .
Case(
"r25", Hexagon::R25)
339 .
Case(
"r26", Hexagon::R26)
340 .
Case(
"r27", Hexagon::R27)
341 .
Case(
"r28", Hexagon::R28)
342 .
Case(
"r29", Hexagon::R29)
343 .
Case(
"r30", Hexagon::R30)
344 .
Case(
"r31", Hexagon::R31)
345 .
Case(
"r1:0", Hexagon::D0)
346 .
Case(
"r3:2", Hexagon::D1)
347 .
Case(
"r5:4", Hexagon::D2)
348 .
Case(
"r7:6", Hexagon::D3)
349 .
Case(
"r9:8", Hexagon::D4)
350 .
Case(
"r11:10", Hexagon::D5)
351 .
Case(
"r13:12", Hexagon::D6)
352 .
Case(
"r15:14", Hexagon::D7)
353 .
Case(
"r17:16", Hexagon::D8)
354 .
Case(
"r19:18", Hexagon::D9)
355 .
Case(
"r21:20", Hexagon::D10)
356 .
Case(
"r23:22", Hexagon::D11)
357 .
Case(
"r25:24", Hexagon::D12)
358 .
Case(
"r27:26", Hexagon::D13)
359 .
Case(
"r29:28", Hexagon::D14)
360 .
Case(
"r31:30", Hexagon::D15)
361 .
Case(
"sp", Hexagon::R29)
362 .
Case(
"fp", Hexagon::R30)
363 .
Case(
"lr", Hexagon::R31)
364 .
Case(
"p0", Hexagon::P0)
365 .
Case(
"p1", Hexagon::P1)
366 .
Case(
"p2", Hexagon::P2)
367 .
Case(
"p3", Hexagon::P3)
368 .
Case(
"sa0", Hexagon::SA0)
369 .
Case(
"lc0", Hexagon::LC0)
370 .
Case(
"sa1", Hexagon::SA1)
371 .
Case(
"lc1", Hexagon::LC1)
372 .
Case(
"m0", Hexagon::M0)
373 .
Case(
"m1", Hexagon::M1)
374 .
Case(
"usr", Hexagon::USR)
375 .
Case(
"ugp", Hexagon::UGP)
376 .
Case(
"cs0", Hexagon::CS0)
377 .
Case(
"cs1", Hexagon::CS1)
398 if (Subtarget.useHVXOps())
404 for (
unsigned i = 0; i != RVLocs.
size(); ++i) {
406 if (RVLocs[i].getValVT() == MVT::i1) {
416 Register PredR = MRI.createVirtualRegister(&Hexagon::PredRegsRegClass);
428 RVLocs[i].getValVT(), Glue);
454 bool IsStructRet = Outs.
empty() ?
false : Outs[0].Flags.isSRet();
463 bool TreatAsVarArg = !Subtarget.isEnvironmentMusl() && IsVarArg;
469 if (Subtarget.useHVXOps())
479 IsVarArg, IsStructRet, StructAttrFlag, Outs,
488 :
"Argument must be passed on stack. "
489 "Not eligible for Tail Call\n"));
500 bool NeedsArgAlign =
false;
501 Align LargestAlignSeen;
503 for (
unsigned i = 0, e = ArgLocs.
size(); i != e; ++i) {
508 bool ArgAlign = Subtarget.isHVXVectorType(VA.
getValVT());
509 NeedsArgAlign |= ArgAlign;
535 StackPtr.getValueType());
538 LargestAlignSeen = std::max(
540 if (Flags.isByVal()) {
560 if (NeedsArgAlign && Subtarget.hasV60Ops()) {
561 LLVM_DEBUG(
dbgs() <<
"Function needs byte stack align due to call args\n");
562 Align VecAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
563 LargestAlignSeen = std::max(LargestAlignSeen, VecAlign);
568 if (!MemOpChains.
empty())
582 for (
const auto &R : RegsToPass) {
583 Chain = DAG.
getCopyToReg(Chain, dl, R.first, R.second, Glue);
598 for (
const auto &R : RegsToPass) {
599 Chain = DAG.
getCopyToReg(Chain, dl, R.first, R.second, Glue);
620 Ops.push_back(Chain);
621 Ops.push_back(Callee);
625 for (
const auto &R : RegsToPass)
629 assert(Mask &&
"Missing call preserved mask for calling convention");
637 return DAG.
getNode(HexagonISD::TC_RETURN, dl, MVT::Other,
Ops);
645 unsigned OpCode = DoesNotReturn ? HexagonISD::CALLnr : HexagonISD::CALL;
646 Chain = DAG.
getNode(OpCode, dl, {MVT::Other, MVT::Glue},
Ops);
656 InVals, OutVals, Callee);
671 bool IsLegalType = VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32 ||
672 VT == MVT::i64 || VT == MVT::f32 || VT == MVT::f64 ||
673 VT == MVT::v2i16 || VT == MVT::v2i32 || VT == MVT::v4i8 ||
674 VT == MVT::v4i16 || VT == MVT::v8i8 ||
688 return Subtarget.getInstrInfo()->isValidAutoIncImm(VT, V);
703 unsigned LR = HRI.getRARegister();
709 unsigned NumOps =
Op.getNumOperands();
710 if (
Op.getOperand(
NumOps-1).getValueType() == MVT::Glue)
715 unsigned NumVals = Flags.getNumOperandRegisters();
718 switch (Flags.getKind()) {
729 for (; NumVals; --NumVals, ++i) {
733 HMFI.setHasClobberLR(
true);
755 return DAG.
getNode(HexagonISD::DCFETCH,
DL, MVT::Other, Chain, Addr, Zero);
761 unsigned IntNo =
Op.getConstantOperandVal(1);
763 if (IntNo == Intrinsic::hexagon_prefetch) {
767 return DAG.
getNode(HexagonISD::DCFETCH,
DL, MVT::Other, Chain, Addr, Zero);
781 assert(AlignConst &&
"Non-constant Align in LowerDYNAMIC_STACKALLOC");
784 auto &HFI = *Subtarget.getFrameLowering();
787 A = HFI.getStackAlign().value();
790 dbgs () << __func__ <<
" Align: " <<
A <<
" Size: ";
791 Size.getNode()->dump(&DAG);
812 bool TreatAsVarArg = !Subtarget.isEnvironmentMusl() && IsVarArg;
818 if (Subtarget.useHVXOps())
832 switch (RC.
getID()) {
833 case Hexagon::IntRegsRegClassID:
834 return Reg - Hexagon::R0 + 1;
835 case Hexagon::DoubleRegsRegClassID:
836 return (Reg - Hexagon::D0 + 1) * 2;
837 case Hexagon::HvxVRRegClassID:
838 return Reg - Hexagon::V0 + 1;
839 case Hexagon::HvxWRRegClassID:
840 return (Reg - Hexagon::W0 + 1) * 2;
847 HFL.FirstVarArgSavedReg = 0;
850 for (
unsigned i = 0, e = ArgLocs.
size(); i != e; ++i) {
853 bool ByVal = Flags.isByVal();
859 if (VA.
isRegLoc() && ByVal && Flags.getByValSize() <= 8)
863 (!ByVal || (ByVal && Flags.getByValSize() > 8));
887 Subtarget.isHVXVectorType(RegVT));
892 HFL.FirstVarArgSavedReg = NextSingleReg(*RC, VA.
getLocReg());
898 unsigned ObjSize = Flags.isByVal()
899 ? Flags.getByValSize()
907 if (Flags.isByVal()) {
920 if (IsVarArg && Subtarget.isEnvironmentMusl()) {
921 for (
int i = HFL.FirstVarArgSavedReg; i < 6; i++)
925 if (IsVarArg && Subtarget.isEnvironmentMusl()) {
926 HMFI.setFirstNamedArgFrameIndex(HMFI.getFirstNamedArgFrameIndex() - 1);
930 int NumVarArgRegs = 6 - HFL.FirstVarArgSavedReg;
931 bool RequiresPadding = (NumVarArgRegs & 1);
932 int RegSaveAreaSizePlusPadding = RequiresPadding
933 ? (NumVarArgRegs + 1) * 4
936 if (RegSaveAreaSizePlusPadding > 0) {
939 if (!(RegAreaStart % 8))
940 RegAreaStart = (RegAreaStart + 7) & -8;
942 int RegSaveAreaFrameIndex =
944 HMFI.setRegSavedAreaStartFrameIndex(RegSaveAreaFrameIndex);
947 int Offset = RegAreaStart + RegSaveAreaSizePlusPadding;
949 HMFI.setVarArgsFrameIndex(FI);
955 HMFI.setRegSavedAreaStartFrameIndex(FI);
956 HMFI.setVarArgsFrameIndex(FI);
961 if (IsVarArg && !Subtarget.isEnvironmentMusl()) {
965 HMFI.setVarArgsFrameIndex(FI);
980 if (!Subtarget.isEnvironmentMusl()) {
985 auto &HFL = *Subtarget.getFrameLowering();
998 SDValue SavedRegAreaStartFrameIndex =
999 DAG.
getFrameIndex(FuncInfo.getRegSavedAreaStartFrameIndex(), MVT::i32);
1003 if (HFL.FirstVarArgSavedReg & 1)
1004 SavedRegAreaStartFrameIndex =
1006 DAG.
getFrameIndex(FuncInfo.getRegSavedAreaStartFrameIndex(),
1013 SavedRegAreaStartFrameIndex,
1041 assert(Subtarget.isEnvironmentMusl() &&
"Linux ABI should be enabled");
1052 false,
false,
nullptr,
1065 if (OpTy == MVT::v2i16 || OpTy == MVT::v4i8) {
1067 assert(ElemTy.isScalarInteger());
1082 auto isSExtFree = [
this](
SDValue N) {
1083 switch (
N.getOpcode()) {
1095 return ThisBW >= OrigBW;
1104 if (OpTy == MVT::i8 || OpTy == MVT::i16) {
1106 bool IsNegative =
C &&
C->getAPIntValue().isNegative();
1107 if (IsNegative || isSExtFree(LHS) || isSExtFree(RHS))
1119 SDValue Op1 =
Op.getOperand(1), Op2 =
Op.getOperand(2);
1123 if (OpTy == MVT::v2i16 || OpTy == MVT::v4i8) {
1125 assert(ElemTy.isScalarInteger());
1141 EVT ValTy =
Op.getValueType();
1144 bool isVTi1Type =
false;
1149 unsigned VecLen = CV->getNumOperands();
1151 "conversion only supported for pow2 VectorSize");
1152 for (
unsigned i = 0; i < VecLen; ++i)
1168 else if (isVTi1Type)
1175 "Inconsistent target flag encountered");
1177 if (IsPositionIndependent)
1184 EVT VT =
Op.getValueType();
1202 EVT VT =
Op.getValueType();
1204 unsigned Depth =
Op.getConstantOperandVal(0);
1224 EVT VT =
Op.getValueType();
1226 unsigned Depth =
Op.getConstantOperandVal(0);
1238 return DAG.
getNode(HexagonISD::BARRIER, dl, MVT::Other,
Op.getOperand(0));
1246 auto *GV = GAN->getGlobal();
1247 int64_t
Offset = GAN->getOffset();
1249 auto &HLOF = *HTM.getObjFileLowering();
1255 if (GO && Subtarget.useSmallData() && HLOF.isGlobalInSmallSection(GO, HTM))
1256 return DAG.
getNode(HexagonISD::CONST32_GP, dl, PtrVT, GA);
1257 return DAG.
getNode(HexagonISD::CONST32, dl, PtrVT, GA);
1264 return DAG.
getNode(HexagonISD::AT_PCREL, dl, PtrVT, GA);
1271 return DAG.
getNode(HexagonISD::AT_GOT, dl, PtrVT, GOT, GA, Off);
1284 return DAG.
getNode(HexagonISD::CONST32_GP, dl, PtrVT,
A);
1288 return DAG.
getNode(HexagonISD::AT_PCREL, dl, PtrVT,
A);
1297 return DAG.
getNode(HexagonISD::AT_PCREL,
SDLoc(
Op), PtrVT, GOTSym);
1303 unsigned char OperandFlags)
const {
1320 const auto &HRI = *Subtarget.getRegisterInfo();
1322 assert(Mask &&
"Missing call preserved mask for calling convention");
1325 Chain = DAG.
getNode(HexagonISD::CALL, dl, NodeTys,
Ops);
1357 if (IsPositionIndependent) {
1429 Hexagon::R0, Flags);
1442 switch (HTM.getTLSModel(GA->
getGlobal())) {
1462 auto &HRI = *Subtarget.getRegisterInfo();
1556 if (Subtarget.isEnvironmentMusl())
1571 for (
unsigned LegalIntOp :
1611 for (
unsigned IntExpOp :
1659 static const unsigned VectExpOps[] = {
1687 for (
unsigned VectExpOp : VectExpOps)
1701 if (VT.getVectorElementType() != MVT::i32) {
1728 for (
MVT NativeVT : {MVT::v8i1, MVT::v4i1, MVT::v2i1, MVT::v4i8,
1729 MVT::v8i8, MVT::v2i16, MVT::v4i16, MVT::v2i32}) {
1744 if (NativeVT.getVectorElementType() != MVT::i1) {
1751 for (
MVT VT : {MVT::v8i8, MVT::v4i16, MVT::v2i32}) {
1762 for (
MVT VT : {MVT::i16, MVT::i32, MVT::v4i8, MVT::i64, MVT::v8i8,
1763 MVT::v2i16, MVT::v4i16, MVT::v2i32}) {
1769 for (
MVT VT : {MVT::v2i1, MVT::v4i1, MVT::v8i1}) {
1775 for (
MVT VT : {MVT::v2i16, MVT::v4i8, MVT::v8i8, MVT::v2i32, MVT::v4i16,
1787 for (
MVT VT : {MVT::i1, MVT::v2i1, MVT::v4i1, MVT::v8i1}) {
1846 for (
MVT VT : {MVT::i8, MVT::i16, MVT::i32, MVT::i64, MVT::f32, MVT::f64,
1847 MVT::v2i16, MVT::v2i32, MVT::v4i8, MVT::v4i16, MVT::v8i8}) {
1854 if (Subtarget.hasV60Ops()) {
1860 if (Subtarget.hasV66Ops()) {
1864 if (Subtarget.hasV67Ops()) {
1874 if (Subtarget.useHVXOps())
1875 initializeHVXLowering();
1881HexagonTargetLowering::validateConstPtrAlignment(
SDValue Ptr,
Align NeedAlign,
1886 unsigned Addr = CA->getZExtValue();
1889 if (HaveAlign >= NeedAlign)
1895 DiagnosticInfoMisalignedTrap(
StringRef M)
1900 static bool classof(
const DiagnosticInfo *DI) {
1901 return DI->
getKind() == DK_MisalignedTrap;
1907 raw_string_ostream
O(ErrMsg);
1908 O <<
"Misaligned constant address: " <<
format_hex(Addr, 10)
1909 <<
" has alignment " << HaveAlign.
value()
1910 <<
", but the memory access requires " << NeedAlign.
value();
1913 O <<
". The instruction has been replaced with a trap.";
1922 const SDLoc &dl(
Op);
1924 assert(!
LS->isIndexed() &&
"Not expecting indexed ops on constant address");
1937 return (
ID == Intrinsic::hexagon_L2_loadrd_pbr ||
1938 ID == Intrinsic::hexagon_L2_loadri_pbr ||
1939 ID == Intrinsic::hexagon_L2_loadrh_pbr ||
1940 ID == Intrinsic::hexagon_L2_loadruh_pbr ||
1941 ID == Intrinsic::hexagon_L2_loadrb_pbr ||
1942 ID == Intrinsic::hexagon_L2_loadrub_pbr);
1966 if (Blk == Parent) {
1971 BaseVal = BackEdgeVal;
1973 }
while ((BaseVal != BackEdgeVal) && (IntrBaseVal != BackEdgeVal));
1976 if (IntrBaseVal == BackEdgeVal)
1983 assert(Idx >= 0 &&
"Unexpected index to incoming argument in PHI");
1991 Value *IntrBaseVal = V;
1998 }
while (BaseVal != V);
2016 case Intrinsic::hexagon_L2_loadrd_pbr:
2017 case Intrinsic::hexagon_L2_loadri_pbr:
2018 case Intrinsic::hexagon_L2_loadrh_pbr:
2019 case Intrinsic::hexagon_L2_loadruh_pbr:
2020 case Intrinsic::hexagon_L2_loadrb_pbr:
2021 case Intrinsic::hexagon_L2_loadrub_pbr: {
2023 auto &
DL =
I.getDataLayout();
2024 auto &Cont =
I.getCalledFunction()->getParent()->getContext();
2028 Type *ElTy =
I.getCalledFunction()->getReturnType()->getStructElementType(0);
2035 Info.align =
DL.getABITypeAlign(Info.memVT.getTypeForEVT(Cont));
2040 case Intrinsic::hexagon_V6_vgathermw:
2041 case Intrinsic::hexagon_V6_vgathermw_128B:
2042 case Intrinsic::hexagon_V6_vgathermh:
2043 case Intrinsic::hexagon_V6_vgathermh_128B:
2044 case Intrinsic::hexagon_V6_vgathermhw:
2045 case Intrinsic::hexagon_V6_vgathermhw_128B:
2046 case Intrinsic::hexagon_V6_vgathermwq:
2047 case Intrinsic::hexagon_V6_vgathermwq_128B:
2048 case Intrinsic::hexagon_V6_vgathermhq:
2049 case Intrinsic::hexagon_V6_vgathermhq_128B:
2050 case Intrinsic::hexagon_V6_vgathermhwq:
2051 case Intrinsic::hexagon_V6_vgathermhwq_128B:
2052 case Intrinsic::hexagon_V6_vgather_vscattermh:
2053 case Intrinsic::hexagon_V6_vgather_vscattermh_128B: {
2054 const Module &M = *
I.getParent()->getParent()->getParent();
2056 Type *VecTy =
I.getArgOperand(
I.arg_size() - 1)->getType();
2059 Info.ptrVal =
I.getArgOperand(0);
2062 MaybeAlign(M.getDataLayout().getTypeAllocSizeInBits(VecTy) / 8);
2074 return X.getValueType().isScalarInteger();
2094 unsigned DefinedValues)
const {
2099 unsigned Index)
const {
2130 if (Subtarget.useHVXOps()) {
2131 unsigned Action = getPreferredHvxVectorAction(VT);
2137 if (ElemTy == MVT::i1)
2150 if (Subtarget.useHVXOps()) {
2151 unsigned Action = getCustomHvxOperationAction(
Op);
2158std::pair<SDValue, int>
2159HexagonTargetLowering::getBaseAndOffset(
SDValue Addr)
const {
2163 return { Addr.
getOperand(0), CN->getSExtValue() };
2175 assert(AM.
size() <= 8 &&
"Unexpected shuffle mask");
2176 unsigned VecLen = AM.
size();
2179 assert(!Subtarget.isHVXVectorType(VecTy,
true) &&
2180 "HVX shuffles should be legal");
2190 if (ty(Op0) != VecTy || ty(Op1) != VecTy)
2199 if (AM[
F] >=
int(VecLen)) {
2207 for (
int M : Mask) {
2209 for (
unsigned j = 0; j != ElemBytes; ++j)
2212 for (
unsigned j = 0; j != ElemBytes; ++j)
2225 for (
unsigned i = 0, e = ByteMask.
size(); i != e; ++i) {
2233 if (ByteMask.
size() == 4) {
2235 if (MaskIdx == (0x03020100 | MaskUnd))
2238 if (MaskIdx == (0x00010203 | MaskUnd)) {
2246 getCombine(Op1, Op0, dl, typeJoin({ty(Op1), ty(Op0)}), DAG);
2247 if (MaskIdx == (0x06040200 | MaskUnd))
2248 return getInstr(Hexagon::S2_vtrunehb, dl, VecTy, {Concat10}, DAG);
2249 if (MaskIdx == (0x07050301 | MaskUnd))
2250 return getInstr(Hexagon::S2_vtrunohb, dl, VecTy, {Concat10}, DAG);
2253 getCombine(Op0, Op1, dl, typeJoin({ty(Op0), ty(Op1)}), DAG);
2254 if (MaskIdx == (0x02000604 | MaskUnd))
2255 return getInstr(Hexagon::S2_vtrunehb, dl, VecTy, {Concat01}, DAG);
2256 if (MaskIdx == (0x03010705 | MaskUnd))
2257 return getInstr(Hexagon::S2_vtrunohb, dl, VecTy, {Concat01}, DAG);
2260 if (ByteMask.
size() == 8) {
2262 if (MaskIdx == (0x0706050403020100ull | MaskUnd))
2265 if (MaskIdx == (0x0001020304050607ull | MaskUnd)) {
2272 if (MaskIdx == (0x0d0c050409080100ull | MaskUnd))
2273 return getInstr(Hexagon::S2_shuffeh, dl, VecTy, {Op1, Op0}, DAG);
2274 if (MaskIdx == (0x0f0e07060b0a0302ull | MaskUnd))
2275 return getInstr(Hexagon::S2_shuffoh, dl, VecTy, {Op1, Op0}, DAG);
2276 if (MaskIdx == (0x0d0c090805040100ull | MaskUnd))
2277 return getInstr(Hexagon::S2_vtrunewh, dl, VecTy, {Op1, Op0}, DAG);
2278 if (MaskIdx == (0x0f0e0b0a07060302ull | MaskUnd))
2279 return getInstr(Hexagon::S2_vtrunowh, dl, VecTy, {Op1, Op0}, DAG);
2280 if (MaskIdx == (0x0706030205040100ull | MaskUnd)) {
2281 VectorPair
P = opSplit(Op0, dl, DAG);
2282 return getInstr(Hexagon::S2_packhl, dl, VecTy, {
P.second,
P.first}, DAG);
2286 if (MaskIdx == (0x0e060c040a020800ull | MaskUnd))
2287 return getInstr(Hexagon::S2_shuffeb, dl, VecTy, {Op1, Op0}, DAG);
2288 if (MaskIdx == (0x0f070d050b030901ull | MaskUnd))
2289 return getInstr(Hexagon::S2_shuffob, dl, VecTy, {Op1, Op0}, DAG);
2297 switch (
Op.getOpcode()) {
2303 return Op.getOperand(0);
2313 switch (
Op.getOpcode()) {
2315 NewOpc = HexagonISD::VASL;
2318 NewOpc = HexagonISD::VASR;
2321 NewOpc = HexagonISD::VLSR;
2326 if (
SDValue Sp = getSplatValue(
Op.getOperand(1), DAG)) {
2334 "Hexagon vector shift-by-int must use i32 shift operand");
2335 return DAG.
getNode(NewOpc, dl, ty(
Op),
Op.getOperand(0), Sh);
2349 if (
SDValue S = getVectorShiftByInt(
Op, DAG))
2354 case HexagonISD::VASR:
2355 case HexagonISD::VLSR:
2356 case HexagonISD::VASL:
2363 MVT ResTy = ty(Res);
2381 return ShiftPartI8(
Opc, Val, Amt);
2383 auto [LoV, HiV] = opSplit(Val, dl, DAG);
2385 {ShiftPartI8(
Opc, LoV, Amt), ShiftPartI8(
Opc, HiV, Amt)});
2399 MVT InpTy = ty(InpV);
2404 if (InpTy == MVT::i8) {
2405 if (ResTy == MVT::v8i1) {
2408 return getInstr(Hexagon::C2_tfrrp, dl, ResTy, Ext, DAG);
2423 bool AllConst =
true;
2425 for (
unsigned i = 0, e = Values.
size(); i != e; ++i) {
2428 Consts[i] = ConstantInt::get(IntTy, 0);
2433 const ConstantInt *CI = CN->getConstantIntValue();
2437 const ConstantFP *CF = CN->getConstantFPValue();
2439 Consts[i] = ConstantInt::get(IntTy,
A.getZExtValue());
2454 bool AllConst = getBuildVectorConstInts(Elem, VecTy, DAG, Consts);
2458 if (!isUndef(Elem[
First]))
2466 return getZero(dl, VecTy, DAG);
2468 if (ElemTy == MVT::i16 || ElemTy == MVT::f16) {
2473 uint32_t
V = (Consts[0]->getZExtValue() & 0xFFFF) |
2474 Consts[1]->getZExtValue() << 16;
2478 if (ElemTy == MVT::f16) {
2485 SDValue N = getInstr(Hexagon::A2_combine_ll, dl, MVT::i32, {E1, E0}, DAG);
2489 if (ElemTy == MVT::i8) {
2492 uint32_t
V = (Consts[0]->getZExtValue() & 0xFF) |
2493 (Consts[1]->getZExtValue() & 0xFF) << 8 |
2494 (Consts[2]->getZExtValue() & 0xFF) << 16 |
2495 Consts[3]->getZExtValue() << 24;
2500 bool IsSplat =
true;
2501 for (
unsigned i =
First+1; i != Num; ++i) {
2502 if (Elem[i] == Elem[
First] || isUndef(Elem[i]))
2518 for (
unsigned i = 0; i != 4; ++i) {
2528 SDValue R = getInstr(Hexagon::A2_combine_ll, dl, MVT::i32, {B1, B0}, DAG);
2533 dbgs() <<
"VecTy: " << VecTy <<
'\n';
2545 bool AllConst = getBuildVectorConstInts(Elem, VecTy, DAG, Consts);
2549 if (!isUndef(Elem[
First]))
2557 return getZero(dl, VecTy, DAG);
2560 if (ElemTy == MVT::i16 || ElemTy == MVT::f16) {
2561 bool IsSplat =
true;
2562 for (
unsigned i =
First+1; i != Num; ++i) {
2563 if (Elem[i] == Elem[
First] || isUndef(Elem[i]))
2581 uint64_t
Mask = (1ull <<
W) - 1;
2582 for (
unsigned i = 0; i != Num; ++i)
2583 Val = (Val << W) | (Consts[Num-1-i]->getZExtValue() & Mask);
2592 : buildVector32(Elem.take_front(Num/2), dl, HalfTy, DAG);
2595 : buildVector32(Elem.
drop_front(Num/2), dl, HalfTy, DAG);
2596 return getCombine(
H, L, dl, VecTy, DAG);
2603 MVT VecTy = ty(VecV);
2607 return extractVectorPred(VecV, IdxV, dl, ValTy, ResTy, DAG);
2612 assert((VecWidth % ElemWidth) == 0);
2613 assert(VecWidth == 32 || VecWidth == 64);
2616 MVT ScalarTy = tyScalar(VecTy);
2623 unsigned Off = IdxN->getZExtValue() * ElemWidth;
2624 if (VecWidth == 64 && ValWidth == 32) {
2625 assert(Off == 0 || Off == 32);
2626 ExtV =
Off == 0 ? LoHalf(VecV, DAG) : HiHalf(VecV, DAG);
2627 }
else if (Off == 0 && (ValWidth % 8) == 0) {
2633 ExtV = DAG.
getNode(HexagonISD::EXTRACTU, dl, ScalarTy,
2634 {VecV, WidthV, OffV});
2637 if (ty(IdxV) != MVT::i32)
2641 ExtV = DAG.
getNode(HexagonISD::EXTRACTU, dl, ScalarTy,
2642 {VecV, WidthV, OffV});
2652HexagonTargetLowering::extractVectorPred(
SDValue VecV,
SDValue IdxV,
2657 MVT VecTy = ty(VecV);
2661 "Vector elements should equal vector width size");
2662 assert(VecWidth == 8 || VecWidth == 4 || VecWidth == 2);
2673 if (ValWidth == 1) {
2674 SDValue A0 = getInstr(Hexagon::C2_tfrpr, dl, MVT::i32, {VecV}, DAG);
2677 return DAG.
getNode(HexagonISD::TSTBIT, dl, MVT::i1, A0, I0);
2684 unsigned Scale = VecWidth / ValWidth;
2688 assert(ty(IdxV) == MVT::i32);
2689 unsigned VecRep = 8 / VecWidth;
2697 T1 = LoHalf(
T1, DAG);
2698 T1 = expandPredicate(
T1, dl, DAG);
2709 MVT VecTy = ty(VecV);
2711 return insertVectorPred(VecV, ValV, IdxV, dl, ValTy, DAG);
2715 assert(VecWidth == 32 || VecWidth == 64);
2716 assert((VecWidth % ValWidth) == 0);
2722 unsigned VW = ty(ValV).getSizeInBits();
2732 unsigned W =
C->getZExtValue() * ValWidth;
2734 InsV = DAG.
getNode(HexagonISD::INSERT, dl, ScalarTy,
2735 {VecV, ValV, WidthV, OffV});
2737 if (ty(IdxV) != MVT::i32)
2740 InsV = DAG.
getNode(HexagonISD::INSERT, dl, ScalarTy,
2741 {VecV, ValV, WidthV, OffV});
2748HexagonTargetLowering::insertVectorPred(
SDValue VecV,
SDValue ValV,
2751 MVT VecTy = ty(VecV);
2754 if (ValTy == MVT::i1) {
2755 SDValue ToReg = getInstr(Hexagon::C2_tfrpr, dl, MVT::i32, {VecV}, DAG);
2760 DAG.
getNode(HexagonISD::INSERT, dl, MVT::i32, {ToReg, Ext, Width, Idx});
2761 return getInstr(Hexagon::C2_tfrrp, dl, VecTy, {Ins}, DAG);
2772 for (
unsigned R = Scale;
R > 1;
R /= 2) {
2773 ValR = contractPredicate(ValR, dl, DAG);
2774 ValR = getCombine(DAG.
getUNDEF(MVT::i32), ValR, dl, MVT::i64, DAG);
2781 DAG.
getNode(HexagonISD::INSERT, dl, MVT::i64, {VecR, ValR, Width, Idx});
2786HexagonTargetLowering::expandPredicate(
SDValue Vec32,
const SDLoc &dl,
2788 assert(ty(Vec32).getSizeInBits() == 32);
2797HexagonTargetLowering::contractPredicate(
SDValue Vec64,
const SDLoc &dl,
2799 assert(ty(Vec64).getSizeInBits() == 64);
2805 {0, 2, 4, 6, 1, 3, 5, 7});
2806 return extractVector(S, DAG.
getConstant(0, dl, MVT::i32), dl, MVT::v4i8,
2830 MVT ValTy = ty(Val);
2835 if (ValLen == ResLen)
2838 const SDLoc &dl(Val);
2840 assert(ResLen % ValLen == 0);
2843 for (
unsigned i = 1, e = ResLen / ValLen; i <
e; ++i)
2852 MVT ElemTy = ty(
Hi);
2877 for (
unsigned i = 0, e =
Op.getNumOperands(); i != e; ++i)
2878 Ops.push_back(
Op.getOperand(i));
2881 return buildVector32(
Ops, dl, VecTy, DAG);
2883 return buildVector64(
Ops, dl, VecTy, DAG);
2885 if (VecTy == MVT::v8i1 || VecTy == MVT::v4i1 || VecTy == MVT::v2i1) {
2887 bool All0 =
true, All1 =
true;
2890 if (CN ==
nullptr) {
2891 All0 = All1 =
false;
2899 return DAG.
getNode(HexagonISD::PFALSE, dl, VecTy);
2901 return DAG.
getNode(HexagonISD::PTRUE, dl, VecTy);
2907 SDValue Z = getZero(dl, MVT::i32, DAG);
2910 for (
unsigned i = 0; i != 8; ++i) {
2915 for (
unsigned i = 0, e =
A.size()/2; i != e; ++i)
2919 return getInstr(Hexagon::C2_tfrrp, dl, VecTy, {Rs[0]}, DAG);
2932 return getCombine(
Op.getOperand(1),
Op.getOperand(0), dl, VecTy, DAG);
2936 if (ElemTy == MVT::i1) {
2937 assert(VecTy == MVT::v2i1 || VecTy == MVT::v4i1 || VecTy == MVT::v8i1);
2938 MVT OpTy = ty(
Op.getOperand(0));
2942 assert(Scale ==
Op.getNumOperands() && Scale > 1);
2951 for (
SDValue P :
Op.getNode()->op_values()) {
2953 for (
unsigned R = Scale; R > 1; R /= 2) {
2954 W = contractPredicate(W, dl, DAG);
2955 W = getCombine(DAG.
getUNDEF(MVT::i32), W, dl, MVT::i64, DAG);
2963 Words[IdxW ^ 1].
clear();
2965 for (
unsigned i = 0, e = Words[IdxW].
size(); i != e; i += 2) {
2966 SDValue W0 = Words[IdxW][i], W1 = Words[IdxW][i+1];
2969 {W0, W1, WidthV, WidthV});
2977 assert(Scale == 2 && Words[IdxW].
size() == 2);
2979 SDValue WW = getCombine(Words[IdxW][1], Words[IdxW][0], dl, MVT::i64, DAG);
2991 return extractVector(Vec,
Op.getOperand(1),
SDLoc(
Op), ElemTy, ty(
Op), DAG);
2997 return extractVector(
Op.getOperand(0),
Op.getOperand(1),
SDLoc(
Op),
2998 ty(
Op), ty(
Op), DAG);
3004 return insertVector(
Op.getOperand(0),
Op.getOperand(1),
Op.getOperand(2),
3012 return insertVector(
Op.getOperand(0), ValV,
Op.getOperand(2),
3037 bool LoadPred = MemTy == MVT::v2i1 || MemTy == MVT::v4i1 || MemTy == MVT::v8i1;
3048 if (!validateConstPtrAlignment(LN->
getBasePtr(), ClaimAlign, dl, DAG))
3049 return replaceMemWithUndef(
Op, DAG);
3055 SDValue TP = getInstr(Hexagon::C2_tfrrp, dl, MemTy, {LU}, DAG);
3074 if (Ty == MVT::v2i1 || Ty == MVT::v4i1 || Ty == MVT::v8i1) {
3076 SDValue TR = getInstr(Hexagon::C2_tfrpr, dl, MVT::i32, {Val}, DAG);
3087 if (!validateConstPtrAlignment(SN->
getBasePtr(), ClaimAlign, dl, DAG))
3088 return replaceMemWithUndef(
Op, DAG);
3091 Align NeedAlign = Subtarget.getTypeAlignment(StoreTy);
3092 if (ClaimAlign < NeedAlign)
3101 MVT LoadTy = ty(
Op);
3102 unsigned NeedAlign = Subtarget.getTypeAlignment(LoadTy).
value();
3104 if (HaveAlign >= NeedAlign)
3113 bool DoDefault =
false;
3124 if (!DoDefault && (2 * HaveAlign) == NeedAlign) {
3143 unsigned LoadLen = NeedAlign;
3146 auto BO = getBaseAndOffset(
Base);
3147 unsigned BaseOpc = BO.first.getOpcode();
3148 if (BaseOpc == HexagonISD::VALIGNADDR && BO.second % LoadLen == 0)
3151 if (BO.second % LoadLen != 0) {
3153 DAG.
getConstant(BO.second % LoadLen, dl, MVT::i32));
3154 BO.second -= BO.second % LoadLen;
3156 SDValue BaseNoOff = (BaseOpc != HexagonISD::VALIGNADDR)
3157 ? DAG.
getNode(HexagonISD::VALIGNADDR, dl, MVT::i32, BO.first,
3169 MMO->getPointerInfo(), MMO->getFlags(), 2 * LoadLen,
Align(LoadLen),
3170 MMO->getAAInfo(), MMO->getRanges(), MMO->getSyncScopeID(),
3171 MMO->getSuccessOrdering(), MMO->getFailureOrdering());
3196 unsigned Opc =
Op.getOpcode();
3200 assert(VY != 0 &&
"This should have been folded");
3225 unsigned Opc =
Op.getOpcode();
3229 return DAG.
getNode(HexagonISD::ADDC, dl,
Op.getNode()->getVTList(),
3232 EVT CarryTy =
C.getValueType();
3233 SDValue SubC = DAG.
getNode(HexagonISD::SUBC, dl,
Op.getNode()->getVTList(),
3234 { X, Y, DAG.getLogicalNOT(dl, C, CarryTy) });
3253 unsigned OffsetReg = Hexagon::R28;
3264 return DAG.
getNode(HexagonISD::EH_RETURN, dl, MVT::Other, Chain);
3269 unsigned Opc =
Op.getOpcode();
3274 if (isHvxOperation(
Op.getNode(), DAG)) {
3276 if (
SDValue V = LowerHvxOperation(
Op, DAG))
3283 Op.getNode()->dumpr(&DAG);
3336 if (isHvxOperation(
N, DAG)) {
3337 LowerHvxOperationWrapper(
N,
Results, DAG);
3343 unsigned Opc =
N->getOpcode();
3346 case HexagonISD::SSAT:
3347 case HexagonISD::USAT:
3367 if (isHvxOperation(
N, DAG)) {
3368 ReplaceHvxNodeResults(
N,
Results, DAG);
3374 switch (
N->getOpcode()) {
3381 if (
N->getValueType(0) == MVT::i8) {
3382 if (
N->getOperand(0).getValueType() == MVT::v8i1) {
3383 SDValue P = getInstr(Hexagon::C2_tfrpr, dl, MVT::i32,
3384 N->getOperand(0), DAG);
3398 unsigned Opc =
Op.getOpcode();
3412 if (
SDValue V = splitExtendingPartialReduceMLA(
N, DCI.
DAG))
3423 if (C1->getOpcode() == HexagonISD::PTRUE) {
3425 Op.getOperand(2),
Op.getOperand(1));
3434 if (isHvxOperation(
N, DCI.
DAG)) {
3435 if (
SDValue V = PerformHvxDAGCombine(
N, DCI))
3444 EVT TruncTy =
Op.getValueType();
3461 switch (
P.getOpcode()) {
3462 case HexagonISD::PTRUE:
3464 case HexagonISD::PFALSE:
3465 return getZero(dl, ty(
Op), DCI.
DAG);
3475 MVT TruncTy = ty(
Op);
3478 if (ty(Elem0) == TruncTy)
3481 if (ty(Elem0).bitsGT(TruncTy))
3490 if (ty(
Op) != MVT::i64)
3502 if (Amt && Amt->getZExtValue() >= 32 && ty(Z).getSizeInBits() <= 32) {
3503 unsigned A = Amt->getZExtValue();
3509 return DCI.
DAG.
getNode(HexagonISD::COMBINE, dl, MVT::i64, {T1, T2});
3530 return DAG.
getNode(HexagonISD::AT_PCREL,
SDLoc(Table), VT,
T);
3539 if (Constraint.
size() == 1) {
3540 switch (Constraint[0]) {
3543 if (Subtarget.useHVXOps())
3555std::pair<unsigned, const TargetRegisterClass*>
3559 if (Constraint.
size() == 1) {
3560 switch (Constraint[0]) {
3564 return {0u,
nullptr};
3570 return {0u, &Hexagon::IntRegsRegClass};
3573 return {0u, &Hexagon::DoubleRegsRegClass};
3578 return {0u,
nullptr};
3579 return {0u, &Hexagon::ModRegsRegClass};
3583 return {0u,
nullptr};
3586 return {0u, &Hexagon::HvxQRRegClass};
3592 return {0u,
nullptr};
3594 return {0u, &Hexagon::HvxVRRegClass};
3596 if (Subtarget.hasV60Ops() && Subtarget.useHVX128BOps())
3597 return {0u, &Hexagon::HvxVRRegClass};
3598 return {0u, &Hexagon::HvxWRRegClass};
3600 return {0u, &Hexagon::HvxWRRegClass};
3604 return {0u,
nullptr};
3615 bool ForCodeSize)
const {
3626 assert(Ty->isIntegerTy());
3627 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3628 return (BitSize > 0 && BitSize <= 64);
3636 if (Ty->isSized()) {
3657 int Scale = AM.
Scale;
3681 return Imm >= -512 && Imm <= 511;
3691 bool IsCalleeStructRet,
3692 bool IsCallerStructRet,
3699 bool CCMatch = CallerCC == CalleeCC;
3728 if (IsCalleeStructRet || IsCallerStructRet)
3751 const AttributeList &FuncAttributes)
const {
3752 if (
Op.size() >= 8 &&
Op.isAligned(
Align(8)))
3754 if (
Op.size() >= 4 &&
Op.isAligned(
Align(4)))
3756 if (
Op.size() >= 2 &&
Op.isAligned(
Align(2)))
3770 assert(
Op != Instruction::ICmp &&
Op != Instruction::FCmp);
3776 "Reduction emission only supported for non-zero length vectors!");
3780 for (
unsigned ExtractIdx = 1; ExtractIdx < VF; ++ExtractIdx) {
3782 Result = DAG.
getNode(
Op,
DL, EltT, {Result, Ext});
3790 assert(
Op != Instruction::ICmp &&
Op != Instruction::FCmp);
3800 "Reduction emission only supported for pow2 vectors!");
3806 for (
unsigned i = VF; i > 1; i >>= 1) {
3808 for (
unsigned j = 0; j != i / 2; ++j)
3809 ShuffleMask[j] = i / 2 + j;
3811 std::fill(&ShuffleMask[i / 2], ShuffleMask.end(), -1);
3839 if (Subtarget.isHVXVectorType(SVT,
true))
3840 return allowsHvxMemoryAccess(SVT, Flags,
Fast);
3842 Context,
DL, VT, AddrSpace, Alignment, Flags,
Fast);
3847 unsigned *
Fast)
const {
3851 if (Subtarget.isHVXVectorType(SVT,
true))
3852 return allowsHvxMisalignedMemoryAccesses(SVT, Flags,
Fast);
3858std::pair<const TargetRegisterClass*, uint8_t>
3866 return std::make_pair(&Hexagon::HvxQRRegClass, 1);
3868 return std::make_pair(&Hexagon::HvxVRRegClass, 1);
3870 return std::make_pair(&Hexagon::HvxWRRegClass, 1);
3878 std::optional<unsigned> ByteOffset)
const {
3885 std::pair<SDValue, int> BO = getBaseAndOffset(L->getBasePtr());
3887 if (BO.first.getOpcode() == HexagonISD::CONST32_GP)
3892 return !GO || !HTM.getObjFileLowering()->isGlobalInSmallSection(GO, HTM);
3899 AdjustHvxInstrPostInstrSelection(
MI,
Node);
3905 unsigned SZ = ValueTy->getPrimitiveSizeInBits();
3906 assert((SZ == 32 || SZ == 64) &&
"Only 32/64-bit atomic loads supported");
3907 Intrinsic::ID IntID = (SZ == 32) ? Intrinsic::hexagon_L2_loadw_locked
3908 : Intrinsic::hexagon_L4_loadd_locked;
3911 Builder.CreateIntrinsic(IntID, Addr,
nullptr,
"larx");
3913 return Builder.CreateBitCast(
Call, ValueTy);
3927 assert((SZ == 32 || SZ == 64) &&
"Only 32/64-bit atomic stores supported");
3928 Intrinsic::ID IntID = (SZ == 32) ? Intrinsic::hexagon_S2_storew_locked
3929 : Intrinsic::hexagon_S4_stored_locked;
3931 Val = Builder.CreateBitCast(Val, CastTy);
3933 Value *
Call = Builder.CreateIntrinsic(IntID, {Addr, Val},
3935 Value *Cmp = Builder.CreateICmpEQ(
Call, Builder.getInt32(0),
"");
3951 return SI->getValueOperand()->getType()->getPrimitiveSizeInBits() > 64
3964 switch (
MI.getOpcode()) {
3965 case TargetOpcode::PATCHABLE_EVENT_CALL:
3966 case TargetOpcode::PATCHABLE_TYPED_EVENT_CALL:
3981 return Mask->getValue().isPowerOf2();
3988 if (
N->getNumValues() != 1)
3990 if (!
N->hasNUsesOfValue(1, 0))
3993 SDNode *Copy = *
N->user_begin();
4005 if (Copy->getOperand(Copy->getNumOperands() - 1).getValueType() == MVT::Glue)
4009 bool HasRet =
false;
4011 if (
Node->getOpcode() != HexagonISD::RET_GLUE)
4018 Chain = Copy->getOperand(0);
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
This file implements a class to represent arbitrary precision integral constant values and operations...
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
Function Alias Analysis Results
static void print(raw_ostream &Out, object::Archive::Kind Kind, T Val)
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
static cl::opt< bool > ConstantLoadsToImm("constant-loads-to-imm", cl::Hidden, cl::init(true), cl::desc("Convert constant loads to immediate values."))
static Value * getUnderLyingObjectForBrevLdIntr(Value *V)
static bool CC_SkipOdd(unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State)
static cl::opt< bool > AlignLoads("hexagon-align-loads", cl::Hidden, cl::init(false), cl::desc("Rewrite unaligned loads as a pair of aligned loads"))
static bool isBrevLdIntrinsic(const Value *Inst)
static Value * getBrevLdObject(Value *V)
static cl::opt< bool > DisableArgsMinAlignment("hexagon-disable-args-min-alignment", cl::Hidden, cl::init(false), cl::desc("Disable minimum alignment of 1 for " "arguments passed by value on stack"))
static Value * returnEdge(const PHINode *PN, Value *IntrBaseVal)
static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, ISD::ArgFlagsTy Flags, SelectionDAG &DAG, const SDLoc &dl)
CreateCopyOfByValArgument - Make a copy of an aggregate at address specified by "Src" to address "Dst...
static cl::opt< bool > EmitJumpTables("hexagon-emit-jump-tables", cl::init(true), cl::Hidden, cl::desc("Control jump table emission on Hexagon target"))
static cl::opt< int > MinimumJumpTables("minimum-jump-tables", cl::Hidden, cl::init(5), cl::desc("Set minimum jump tables"))
static cl::opt< bool > EnableHexSDNodeSched("enable-hexagon-sdnode-sched", cl::Hidden, cl::desc("Enable Hexagon SDNode scheduling"))
#define Hexagon_PointerSize
#define HEXAGON_LRFP_SIZE
#define HEXAGON_GOT_SYM_NAME
Module.h This file contains the declarations for the Module class.
const size_t AbstractManglingParser< Derived, Alloc >::NumOps
const AbstractManglingParser< Derived, Alloc >::OperatorInfo AbstractManglingParser< Derived, Alloc >::Ops[]
std::pair< MCSymbol *, MachineModuleInfoImpl::StubValueTy > PairTy
Register const TargetRegisterInfo * TRI
Promote Memory to Register
const SmallVectorImpl< MachineOperand > & Cond
This file defines the SmallVector class.
This file implements the StringSwitch template, which mimics a switch() statement whose cases are str...
static TableGen::Emitter::Opt Y("gen-skeleton-entry", EmitSkeleton, "Generate example skeleton entry")
APInt bitcastToAPInt() const
Class for arbitrary precision integers.
LLVM_ABI APInt trunc(unsigned width) const
Truncate to new width.
Represent a constant reference to an array (0 or more elements consecutively in memory),...
ArrayRef< T > drop_front(size_t N=1) const
Drop the first N elements of the array.
size_t size() const
Get the array size.
An instruction that atomically checks whether a specified value is in a memory location,...
LLVM Basic Block Representation.
const Function * getParent() const
Return the enclosing method, or null if none.
The address of a basic block.
CCState - This class holds information needed while lowering arguments and return values.
LLVM_ABI void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeCallResult - Analyze the return values of a call, incorporating info about the passed values i...
LLVM_ABI bool CheckReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
CheckReturn - Analyze the return values of a function, returning true if the return can be performed ...
LLVM_ABI void AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeReturn - Analyze the returned values of a return, incorporating info about the result values i...
LLVM_ABI void AnalyzeCallOperands(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeCallOperands - Analyze the outgoing arguments to a call, incorporating info about the passed v...
uint64_t getStackSize() const
Returns the size of the currently allocated portion of the stack.
LLVM_ABI void AnalyzeFormalArguments(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeFormalArguments - Analyze an array of argument values, incorporating info about the formals in...
CCValAssign - Represent assignment of one arg/retval to a location.
Register getLocReg() const
LocInfo getLocInfo() const
int64_t getLocMemOffset() const
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
This class represents a function call, abstracting a target machine's calling convention.
const APFloat & getValueAPF() const
This is the shared class of boolean and integer constants.
bool isZero() const
This is just a convenience method to make client code smaller for a common code.
const APInt & getValue() const
Return the constant as an APInt value reference.
MachineConstantPoolValue * getMachineCPVal() const
bool isMachineConstantPoolEntry() const
const Constant * getConstVal() const
int64_t getSExtValue() const
static LLVM_ABI Constant * get(ArrayRef< Constant * > V)
This is an important base class in LLVM.
A parsed version of the target data layout string in and methods for querying it.
This is the base abstract class for diagnostic reporting in the backend.
Interface for custom diagnostic printing.
bool hasOptSize() const
Optimize this function for size (-Os) or minimum size (-Oz).
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
bool hasStructRetAttr() const
Determine if the function returns a structure through first or second pointer argument.
int64_t getOffset() const
const GlobalValue * getGlobal() const
Module * getParent()
Get the module that this global value is contained inside of...
LLVM_ABI const GlobalObject * getAliaseeObject() const
Hexagon target-specific information for each MachineFunction.
int getVarArgsFrameIndex()
void setFirstNamedArgFrameIndex(int v)
void setHasEHReturn(bool H=true)
Register getStackRegister() const
Register getFrameRegister(const MachineFunction &MF) const override
const uint32_t * getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const override
bool isHVXVectorType(EVT VecTy, bool IncludeBool=false) const
unsigned getVectorLength() const
SDValue getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const override
Returns relocation base for the given PIC jumptable.
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const
SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const
bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override
Return if the target supports combining a chain like:
SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const
void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const override
This method should be implemented by targets that mark instructions with the 'hasPostISelHook' flag.
bool isTargetCanonicalConstantNode(SDValue Op) const override
Returns true if the given Opc is considered a canonical constant for the target, which should not be ...
ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint, return the type of constraint it is for this target.
bool isTruncateFree(Type *Ty1, Type *Ty2) const override
Return true if it's free to truncate a value of type FromTy to type ToTy.
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const
SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const
SDValue LowerUAddSubO(SDValue Op, SelectionDAG &DAG) const
Value * emitLoadLinked(IRBuilderBase &Builder, Type *ValueTy, Value *Addr, AtomicOrdering Ord) const override
Perform a load-linked operation on Addr, returning a "Value *" with the corresponding pointee type.
bool isLegalICmpImmediate(int64_t Imm) const override
isLegalICmpImmediate - Return true if the specified immediate is legal icmp immediate,...
bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT, std::optional< unsigned > ByteOffset) const override
Return true if it is profitable to reduce a load to a smaller type.
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
isLegalAddressingMode - Return true if the addressing mode represented by AM is legal for this target...
SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const
AtomicExpansionKind shouldExpandAtomicStoreInIR(StoreInst *SI) const override
Returns how the given (atomic) store should be expanded by the IR-level AtomicExpand pass into.
SDValue GetDynamicTLSAddr(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, SDValue InGlue, EVT PtrVT, unsigned ReturnReg, unsigned char OperandGlues) const
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &dl, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override
Returns true by value, base pointer and offset pointer and addressing mode by reference if this node ...
SDValue LowerUnalignedLoad(SDValue Op, SelectionDAG &DAG) const
SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const
SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const
unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const override
Certain targets such as MIPS require that some types such as vectors are always broken down into scal...
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
isFPImmLegal - Returns true if the target can instruction select the specified FP immediate natively.
bool mayBeEmittedAsTailCall(const CallInst *CI) const override
Return true if the target may be able emit the call instruction as a tail call.
AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const override
Returns how the given (atomic) load should be expanded by the IR-level AtomicExpand pass.
bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override
Return true if result of the specified node is used by a return node only.
SDValue LowerCallResult(SDValue Chain, SDValue InGlue, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals, const SmallVectorImpl< SDValue > &OutVals, SDValue Callee) const
LowerCallResult - Lower the result values of an ISD::CALL into the appropriate copies out of appropri...
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
SDValue LowerToTLSInitialExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG) const
SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, SelectionDAG &DAG) const
bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace, Align Alignment, MachineMemOperand::Flags Flags, unsigned *Fast) const override
Return true if the target supports a memory access of this type for the given address space and align...
SDValue LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const
bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const override
Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type from this source type with ...
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
SDValue LowerROTL(SDValue Op, SelectionDAG &DAG) const
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const
SDValue LowerLoad(SDValue Op, SelectionDAG &DAG) const
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
bool isShuffleMaskLegal(ArrayRef< int > Mask, EVT VT) const override
Targets can use this to indicate that they only support some VECTOR_SHUFFLE operations,...
LegalizeAction getCustomOperationAction(SDNode &Op) const override
How to legalize this custom operation?
SDValue LowerToTLSLocalExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG) const
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override
Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail ...
SDValue LowerUAddSubOCarry(SDValue Op, SelectionDAG &DAG) const
bool shouldExpandBuildVectorWithShuffles(EVT VT, unsigned DefinedValues) const override
bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override
Returns true if it is beneficial to convert a load of a constant to just the constant itself.
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const
SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
LowerCall - Functions arguments are copied from virtual regs to (physical regs)/(stack frame),...
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace, Align Alignment, MachineMemOperand::Flags Flags, unsigned *Fast) const override
Determine if the target supports unaligned memory accesses.
SDValue LowerStore(SDValue Op, SelectionDAG &DAG) const
SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) const
SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
Value * emitStoreConditional(IRBuilderBase &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const override
Perform a store-conditional operation to Addr.
bool hasBitTest(SDValue X, SDValue Y) const override
Return true if the target has a bit-test instruction: (X & (1 << Y)) ==/!= 0 This knowledge can be us...
HexagonTargetLowering(const TargetMachine &TM, const HexagonSubtarget &ST)
SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override
Return true if folding a constant offset with the given GlobalAddress is legal.
bool IsEligibleForTailCallOptimization(SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, bool isCalleeStructRet, bool isCallerStructRet, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SmallVectorImpl< ISD::InputArg > &Ins, SelectionDAG &DAG) const
IsEligibleForTailCallOptimization - Check whether the call is eligible for tail call optimization.
SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const
void LowerOperationWrapper(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but leg...
SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const
SDValue LowerVECTOR_SHIFT(SDValue Op, SelectionDAG &DAG) const
SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) const
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &, EVT) const override
Return true if an FMA operation is faster than a pair of mul and add instructions.
SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const
EVT getOptimalMemOpType(LLVMContext &Context, const MemOp &Op, const AttributeList &FuncAttributes) const override
Returns the target specific optimal type for load and store operations as a result of memset,...
SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const
LegalizeTypeAction getPreferredVectorAction(MVT VT) const override
Return the preferred vector type legalization action.
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context, const Type *RetTy) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
void getTgtMemIntrinsic(SmallVectorImpl< IntrinsicInfo > &Infos, const CallBase &I, MachineFunction &MF, unsigned Intrinsic) const override
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
AtomicExpansionKind shouldExpandAtomicCmpXchgInIR(const AtomicCmpXchgInst *AI) const override
Returns how the given atomic cmpxchg should be expanded by the IR-level AtomicExpand pass.
std::pair< MVT, unsigned > handleMaskRegisterForCallingConv(const HexagonSubtarget &Subtarget, EVT VT) const
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const
Common base class shared among various IRBuilders.
ConstantInt * getInt8(uint8_t C)
Get a constant 8-bit value.
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
Class to represent integer types.
static LLVM_ABI IntegerType * get(LLVMContext &C, unsigned NumBits)
This static method is the primary way of constructing an IntegerType.
This is an important class for using LLVM in a threaded context.
LLVM_ABI void diagnose(const DiagnosticInfo &DI)
Report a message to the currently installed diagnostic handler.
Base class for LoadSDNode and StoreSDNode.
ISD::MemIndexedMode getAddressingMode() const
Return the addressing mode for this load or store: unindexed, pre-inc, pre-dec, post-inc,...
bool isUnindexed() const
Return true if this is NOT a pre/post inc/dec load/store.
bool isIndexed() const
Return true if this is a pre/post inc/dec load/store.
An instruction for reading from memory.
This class is used to represent ISD::LOAD nodes.
const SDValue & getBasePtr() const
const SDValue & getOffset() const
ISD::LoadExtType getExtensionType() const
Return whether this is a plain node, or one of the varieties of value-extending loads.
@ INVALID_SIMPLE_VALUE_TYPE
unsigned getVectorMinNumElements() const
Given a vector type, return the minimum number of elements it contains.
unsigned getVectorNumElements() const
bool isVector() const
Return true if this is a vector value type.
bool isInteger() const
Return true if this is an integer or a vector integer type.
bool isScalableVector() const
Return true if this is a vector value type where the runtime length is machine dependent.
static LLVM_ABI MVT getVT(Type *Ty, bool HandleUnknown=false)
Return the value type corresponding to the specified type.
static auto integer_valuetypes()
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
static auto fixedlen_vector_valuetypes()
bool isScalarInteger() const
Return true if this is an integer, not including vectors.
TypeSize getStoreSizeInBits() const
Return the number of bits overwritten by a store of the specified value type.
static MVT getVectorVT(MVT VT, unsigned NumElements)
MVT getVectorElementType() const
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
static MVT getIntegerVT(unsigned BitWidth)
static auto fp_valuetypes()
LLVM_ABI void print(raw_ostream &OS, const SlotIndexes *=nullptr, bool IsStandalone=true) const
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
LLVM_ABI int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
void setAdjustsStack(bool V)
LLVM_ABI void ensureMaxAlignment(Align Alignment)
Make sure the function is at least Align bytes aligned.
void setFrameAddressIsTaken(bool T)
void setHasTailCall(bool V=true)
void setReturnAddressIsTaken(bool s)
unsigned getNumFixedObjects() const
Return the number of fixed objects.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Function & getFunction()
Return the LLVM function that this machine code represents.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
Register addLiveIn(MCRegister PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
Representation of each machine instruction.
A description of a memory reference used in the backend.
Flags
Flags values. These may be or'd together.
@ MOVolatile
The memory access is volatile.
@ MOLoad
The memory access reads data.
@ MOStore
The memory access writes data.
Flags getFlags() const
Return the raw flags of the source value,.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
LLVM_ABI Register createVirtualRegister(const TargetRegisterClass *RegClass, StringRef Name="")
createVirtualRegister - Create and return a new virtual register in the function with the specified r...
void addLiveIn(MCRegister Reg, Register vreg=Register())
addLiveIn - Add the specified register as a live-in.
const MDNode * getRanges() const
Returns the Ranges that describes the dereference.
AAMDNodes getAAInfo() const
Returns the AA info that describes the dereference.
MachineMemOperand * getMemOperand() const
Return the unique MachineMemOperand object describing the memory reference performed by operation.
const MachinePointerInfo & getPointerInfo() const
const SDValue & getChain() const
EVT getMemoryVT() const
Return the type of the in-memory value.
A Module instance is used to store all the information related to an LLVM module.
Represent a mutable reference to an array (0 or more elements consecutively in memory),...
unsigned getOpcode() const
Return the opcode for this Instruction or ConstantExpr.
BasicBlock * getIncomingBlock(unsigned i) const
Return incoming basic block number i.
Value * getIncomingValue(unsigned i) const
Return incoming value number x.
unsigned getNumIncomingValues() const
Return the number of incoming edges.
Wrapper class representing virtual and physical registers.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
const DebugLoc & getDebugLoc() const
Represents one node in the SelectionDAG.
const SDValue & getOperand(unsigned Num) const
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getValue(unsigned R) const
EVT getValueType() const
Return the ValueType of the referenced return value.
const SDValue & getOperand(unsigned i) const
unsigned getOpcode() const
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned TargetFlags=0)
SDValue getExtractVectorElt(const SDLoc &DL, EVT VT, SDValue Vec, unsigned Idx)
Extract element at Idx from Vec.
const TargetSubtargetInfo & getSubtarget() const
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, Register Reg, SDValue N)
LLVM_ABI SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
LLVM_ABI SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
LLVM_ABI SDValue getAllOnesConstant(const SDLoc &DL, EVT VT, bool IsTarget=false, bool IsOpaque=false)
LLVM_ABI SDValue getConstantFP(double Val, const SDLoc &DL, EVT VT, bool isTarget=false)
Create a ConstantFPSDNode wrapping a constant value.
LLVM_ABI SDValue getRegister(Register Reg, EVT VT)
LLVM_ABI SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
SDValue getGLOBAL_OFFSET_TABLE(EVT VT)
Return a GLOBAL_OFFSET_TABLE node. This does not have a useful SDLoc.
SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond, SDValue Chain=SDValue(), bool IsSignaling=false, SDNodeFlags Flags={})
Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SD...
LLVM_ABI SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align DstAlign, Align SrcAlign, bool isVol, bool AlwaysInline, const CallInst *CI, std::optional< bool > OverrideTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes(), BatchAAResults *BatchAA=nullptr)
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned TargetFlags=0)
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd).
LLVM_ABI SDValue getBitcast(EVT VT, SDValue V)
Return a bitcast using the SDLoc of the value operand, and casting to the provided type.
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, Register Reg, EVT VT)
SDValue getSelect(const SDLoc &DL, EVT VT, SDValue Cond, SDValue LHS, SDValue RHS, SDNodeFlags Flags=SDNodeFlags())
Helper function to make it easier to build Select's if you just have operands and don't want to check...
LLVM_ABI SDValue getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT)
Return the expression required to zero extend the Op value assuming it was the smaller SrcTy value.
const DataLayout & getDataLayout() const
LLVM_ABI SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
LLVM_ABI SDValue getMemBasePlusOffset(SDValue Base, TypeSize Offset, const SDLoc &DL, const SDNodeFlags Flags=SDNodeFlags())
Returns sum of the base pointer and offset.
LLVM_ABI SDValue getTruncStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, EVT SVT, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
LLVM_ABI SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
LLVM_ABI SDValue getSExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either sign-extending or trunca...
LLVM_ABI SDValue getIndexedStore(SDValue OrigStore, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM)
LLVM_ABI SDValue getAnyExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either any-extending or truncat...
LLVM_ABI SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
LLVM_ABI SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned TargetFlags=0)
LLVM_ABI void ReplaceAllUsesOfValueWith(SDValue From, SDValue To)
Replace any uses of From with To, leaving uses of other values produced by From.getNode() alone.
MachineFunction & getMachineFunction() const
LLVM_ABI SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
LLVM_ABI SDValue getRegisterMask(const uint32_t *RegMask)
LLVM_ABI SDValue getZExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either zero-extending or trunca...
LLVMContext * getContext() const
LLVM_ABI SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned TargetFlags=0)
SDValue getTargetConstantPool(const Constant *C, EVT VT, MaybeAlign Align=std::nullopt, int Offset=0, unsigned TargetFlags=0)
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
LLVM_ABI SDValue getVectorShuffle(EVT VT, const SDLoc &dl, SDValue N1, SDValue N2, ArrayRef< int > Mask)
Return an ISD::VECTOR_SHUFFLE node.
LLVM_ABI SDValue getLogicalNOT(const SDLoc &DL, SDValue Val, EVT VT)
Create a logical NOT operation as (XOR Val, BooleanOne).
static void commuteMask(MutableArrayRef< int > Mask)
Change values in a shuffle permute mask assuming the two vector operands have swapped position.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
An instruction for storing to memory.
This class is used to represent ISD::STORE nodes.
const SDValue & getBasePtr() const
const SDValue & getOffset() const
const SDValue & getValue() const
Represent a constant reference to a string, i.e.
constexpr size_t size() const
Get the string size.
A switch()-like statement whose cases are string literals.
StringSwitch & Case(StringLiteral S, T Value)
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
virtual bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, EVT NewVT, std::optional< unsigned > ByteOffset=std::nullopt) const
Return true if it is profitable to reduce a load to a smaller type.
LegalizeAction
This enum indicates whether operations are valid for a target, and if not, what action should be used...
unsigned MaxStoresPerMemcpyOptSize
Likewise for functions with the OptSize attribute.
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
const TargetMachine & getTargetMachine() const
virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
void setIndexedLoadAction(ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action)
Indicate that the specified indexed load does or does not work with the specified type and indicate w...
void setPrefLoopAlignment(Align Alignment)
Set the target's preferred loop alignment.
void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)
Set the maximum atomic operation size supported by the backend.
virtual unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
Certain targets such as MIPS require that some types such as vectors are always broken down into scal...
void setMinFunctionAlignment(Align Alignment)
Set the target's minimum function alignment.
unsigned MaxStoresPerMemsetOptSize
Likewise for functions with the OptSize attribute.
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
unsigned MaxStoresPerMemmove
Specify maximum number of store instructions per memmove call.
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose.
unsigned MaxStoresPerMemmoveOptSize
Likewise for functions with the OptSize attribute.
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type.
void setIndexedStoreAction(ArrayRef< unsigned > IdxModes, MVT VT, LegalizeAction Action)
Indicate that the specified indexed store does or does not work with the specified type and indicate ...
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
void setPrefFunctionAlignment(Align Alignment)
Set the target's preferred function alignment.
unsigned MaxStoresPerMemset
Specify maximum number of store instructions per memset call.
void setMinimumJumpTableEntries(unsigned Val)
Indicate the minimum number of blocks to generate jump tables.
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
@ UndefinedBooleanContent
bool isOperationLegalOrCustom(unsigned Op, EVT VT, bool LegalOnly=false) const
Return true if the specified operation is legal on this target or can be made legal with custom lower...
virtual bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const
Return true if the target supports a memory access of this type for the given address space and align...
void setMinCmpXchgSizeInBits(unsigned SizeInBits)
Sets the minimum cmpxchg or ll/sc size supported by the backend.
void setStackPointerRegisterToSaveRestore(Register R)
If set to a physical register, this specifies the register that llvm.savestack/llvm....
void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)
If Opc/OrigVT is specified as being promoted, the promotion code defaults to trying a larger integer/...
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
void setCondCodeAction(ArrayRef< ISD::CondCode > CCs, MVT VT, LegalizeAction Action)
Indicate that the specified condition code is or isn't supported on the target and indicate what to d...
virtual std::pair< const TargetRegisterClass *, uint8_t > findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const
Return the largest legal super-reg register class of the register class for the specified type and it...
void setTargetDAGCombine(ArrayRef< ISD::NodeType > NTs)
Targets should invoke this method for each target independent node that they want to provide a custom...
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
bool allowsMemoryAccessForAlignment(LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *Fast=nullptr) const
This function returns true if the memory access is aligned or if the target allows this specific unal...
unsigned MaxStoresPerMemcpy
Specify maximum number of store instructions per memcpy call.
void setSchedulingPreference(Sched::Preference Pref)
Specify the target scheduling preference.
virtual bool isTargetCanonicalConstantNode(SDValue Op) const
Returns true if the given Opc is considered a canonical constant for the target, which should not be ...
SDValue expandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG) const
Expands an unaligned store to 2 half-size stores for integer values, and possibly more for vectors.
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
std::pair< SDValue, SDValue > expandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG) const
Expands an unaligned load to 2 half-size loads for an integer, and possibly more for vectors.
bool isPositionIndependent() const
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
TargetLowering(const TargetLowering &)=delete
virtual void LowerOperationWrapper(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const
This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but leg...
Primary interface to the complete machine description for the target machine.
bool shouldAssumeDSOLocal(const GlobalValue *GV) const
unsigned getID() const
Return the register class ID number.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
static constexpr TypeSize getFixed(ScalarTy ExactSize)
The instances of the Type class are immutable: once they are created, they are never changed.
bool isVectorTy() const
True if this is an instance of VectorType.
static LLVM_ABI IntegerType * getInt32Ty(LLVMContext &C)
LLVM_ABI TypeSize getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
bool isIntegerTy() const
True if this is an instance of IntegerType.
static LLVM_ABI IntegerType * getIntNTy(LLVMContext &C, unsigned N)
Value * getOperand(unsigned i) const
LLVM Value Representation.
Type * getType() const
All values are typed, get the type of this value.
const ParentTy * getParent() const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
Abstract Attribute helper functions.
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
@ Fast
Attempts to make calls as fast as possible (e.g.
@ C
The default llvm calling convention, compatible with C.
@ MO_PCREL
MO_PCREL - On a symbol operand, indicates a PC-relative relocation Used for computing a global addres...
@ MO_GOT
MO_GOT - Indicates a GOT-relative relocation.
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
@ STACKRESTORE
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain.
@ STACKSAVE
STACKSAVE - STACKSAVE has one operand, an input chain.
@ PARTIAL_REDUCE_SMLA
PARTIAL_REDUCE_[U|S]MLA(Accumulator, Input1, Input2) The partial reduction nodes sign or zero extend ...
@ SMUL_LOHI
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
@ INSERT_SUBVECTOR
INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector with VECTOR2 inserted into VECTOR1.
@ BSWAP
Byte Swap and Counting operators.
@ VAEND
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE.
@ ADD
Simple integer binary arithmetic operators.
@ LOAD
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
@ FMA
FMA - Perform a * b + c with no intermediate rounding step.
@ INTRINSIC_VOID
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
@ SINT_TO_FP
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
@ CONCAT_VECTORS
CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of vector type with the same length ...
@ FADD
Simple binary floating point operators.
@ ABS
ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth.
@ ATOMIC_FENCE
OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) This corresponds to the fence instruction.
@ SDIVREM
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
@ FP16_TO_FP
FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions and truncation for half-preci...
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
@ BUILD_PAIR
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
@ FLDEXP
FLDEXP - ldexp, inspired by libm (op0 * 2**op1).
@ EH_RETURN
OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents 'eh_return' gcc dwarf builtin,...
@ SIGN_EXTEND
Conversion operators.
@ SCALAR_TO_VECTOR
SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a scalar value into element 0 of the...
@ READSTEADYCOUNTER
READSTEADYCOUNTER - This corresponds to the readfixedcounter intrinsic.
@ PREFETCH
PREFETCH - This corresponds to a prefetch intrinsic.
@ FSINCOS
FSINCOS - Compute both fsin and fcos as a single operation.
@ FNEG
Perform various unary floating-point operations inspired by libm.
@ BR_CC
BR_CC - Conditional branch.
@ SSUBO
Same for subtraction.
@ BR_JT
BR_JT - Jumptable branch.
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
@ SPLAT_VECTOR
SPLAT_VECTOR(VAL) - Returns a vector with the scalar value VAL duplicated in all lanes.
@ VACOPY
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer,...
@ SADDO
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
@ VECREDUCE_ADD
Integer reductions may have a result type larger than the vector element type.
@ SHL
Shift and rotation operations.
@ VECTOR_SHUFFLE
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
@ EXTRACT_SUBVECTOR
EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR.
@ EXTRACT_VECTOR_ELT
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
@ CopyToReg
CopyToReg - This node has three operands: a chain, a register number to set to this value,...
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
@ DEBUGTRAP
DEBUGTRAP - Trap intended to get the attention of a debugger.
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
@ DYNAMIC_STACKALLOC
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary.
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
@ SMIN
[US]{MIN/MAX} - Binary minimum or maximum of signed or unsigned integers.
@ GLOBAL_OFFSET_TABLE
The address of the GOT.
@ VSELECT
Select with a vector condition (op #0) and two vector operands (ops #1 and #2), returning a vector re...
@ UADDO_CARRY
Carry-using nodes for multiple precision addition and subtraction.
@ INLINEASM_BR
INLINEASM_BR - Branching version of inline asm. Used by asm-goto.
@ BF16_TO_FP
BF16_TO_FP, FP_TO_BF16 - These operators are used to perform promotions and truncation for bfloat16.
@ FRAMEADDR
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG.
@ FP_TO_SINT
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
@ READCYCLECOUNTER
READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
@ AND
Bitwise operators - logical and, logical or, logical xor.
@ TRAP
TRAP - Trapping instruction.
@ INTRINSIC_WO_CHAIN
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
@ INSERT_VECTOR_ELT
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL.
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
@ INLINEASM
INLINEASM - Represents an inline asm block.
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
@ VAARG
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
@ SHL_PARTS
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.
@ AssertSext
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
@ FCOPYSIGN
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
@ SADDSAT
RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2 integers with the same bit width (W)...
@ FMINIMUMNUM
FMINIMUMNUM/FMAXIMUMNUM - minimumnum/maximumnum that is same with FMINNUM_IEEE and FMAXNUM_IEEE besid...
@ INTRINSIC_W_CHAIN
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
@ BUILD_VECTOR
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a fixed-width vector with the specified,...
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
This namespace contains an enum with a value for every intrinsic/builtin function known by LLVM.
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
constexpr bool isInt(int64_t x)
Checks if an integer fits into the given bit width.
LLVM_ABI bool isNullConstant(SDValue V)
Returns true if V is a constant integer zero.
decltype(auto) dyn_cast(const From &Val)
dyn_cast<X> - Return the argument parameter cast to the specified type.
bool isAligned(Align Lhs, uint64_t SizeInBytes)
Checks that SizeInBytes is a multiple of the alignment.
LLVM_ABI Value * getSplatValue(const Value *V)
Get splat value if the input is a splat vector or return nullptr.
int countr_zero(T Val)
Count number of 0's from the least significant bit to the most stopping at the first 1.
auto dyn_cast_or_null(const Y &Val)
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
LLVM_ABI raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
LLVM_ABI Value * getShuffleReduction(IRBuilderBase &Builder, Value *Src, unsigned Op, TargetTransformInfo::ReductionShuffle RS, RecurKind MinMaxKind=RecurKind::None)
Generates a vector reduction using shufflevectors to reduce the value.
class LLVM_GSL_OWNER SmallVector
Forward declaration of SmallVector so that calculateSmallVectorDefaultInlinedElements can reference s...
FormattedNumber format_hex(uint64_t N, unsigned Width, bool Upper=false)
format_hex - Output N as a fixed width hexadecimal.
bool isa(const From &Val)
isa<X> - Return true if the parameter to the template is an instance of one of the template type argu...
AtomicOrdering
Atomic ordering for LLVM's memory model.
@ First
Helpers to iterate all locations in the MemoryEffectsBase class.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
DWARFExpression::Operation Op
LLVM_ABI int getNextAvailablePluginDiagnosticKind()
Get the next available kind ID for a plugin diagnostic.
unsigned M0(unsigned Val)
constexpr unsigned BitWidth
decltype(auto) cast(const From &Val)
cast<X> - Return the argument parameter cast to the specified type.
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
unsigned Log2(Align A)
Returns the log2 of the alignment.
LLVM_ABI Value * getOrderedReduction(IRBuilderBase &Builder, Value *Acc, Value *Src, unsigned Op, RecurKind MinMaxKind=RecurKind::None)
Generates an ordered vector reduction using extracts to reduce the value.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
This struct is a compact representation of a valid (non-zero power of two) alignment.
constexpr uint64_t value() const
This is a hole in the type system and should not be abused.
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
bool bitsGT(EVT VT) const
Return true if this has more bits than VT.
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
bool isPow2VectorType() const
Returns true if the given vector is a power of 2.
static LLVM_ABI EVT getEVT(Type *Ty, bool HandleUnknown=false)
Return the value type corresponding to the specified type.
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
EVT getVectorElementType() const
Given a vector type, return the type of each element.
bool isVectorOf(EVT EltVT) const
Return true if this is a vector with matching element type.
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
This class contains a discriminated union of information about pointers in memory operands,...
static LLVM_ABI MachinePointerInfo getStack(MachineFunction &MF, int64_t Offset, uint8_t ID=0)
Stack pointer relative access.
static LLVM_ABI MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg + ScalableOffset*...
This structure contains all information that is necessary for lowering calls.
SmallVector< ISD::InputArg, 32 > Ins
SmallVector< ISD::OutputArg, 32 > Outs
SmallVector< SDValue, 32 > OutVals
bool isBeforeLegalizeOps() const