LLVM 19.0.0git
LinkAllCodegenComponents.h
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1//===- llvm/Codegen/LinkAllCodegenComponents.h ------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This header file pulls in all codegen related passes for tools like lli and
10// llc that need this functionality.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_CODEGEN_LINKALLCODEGENCOMPONENTS_H
15#define LLVM_CODEGEN_LINKALLCODEGENCOMPONENTS_H
16
17#include "llvm/CodeGen/Passes.h"
20#include <cstdlib>
21
22namespace {
23 struct ForceCodegenLinking {
24 ForceCodegenLinking() {
25 // We must reference the passes in such a way that compilers will not
26 // delete it all as dead code, even with whole program optimization,
27 // yet is effectively a NO-OP. As the compiler isn't smart enough
28 // to know that getenv() never returns -1, this will do the job.
29 // This is so that globals in the translation units where these functions
30 // are defined are forced to be initialized, populating various
31 // registries.
32 if (std::getenv("bar") != (char*) -1)
33 return;
34
39
46 (void)llvm::createFastDAGScheduler(nullptr,
48 (void)llvm::createDefaultScheduler(nullptr,
50 (void)llvm::createVLIWDAGScheduler(nullptr,
52 }
53 } ForceCodegenLinking; // Force link by creating a global definition.
54}
55
56#endif
ScheduleDAGSDNodes * createDefaultScheduler(SelectionDAGISel *IS, CodeGenOptLevel OptLevel)
createDefaultScheduler - This creates an instruction scheduler appropriate for the target.
FunctionPass * createFastRegisterAllocator()
FastRegisterAllocation Pass - This pass register allocates as fast as possible.
ScheduleDAGSDNodes * createBURRListDAGScheduler(SelectionDAGISel *IS, CodeGenOptLevel OptLevel)
createBURRListDAGScheduler - This creates a bottom up register usage reduction list scheduler.
FunctionPass * createGreedyRegisterAllocator()
Greedy register allocation pass - This pass implements a global register allocator for optimized buil...
ScheduleDAGSDNodes * createHybridListDAGScheduler(SelectionDAGISel *IS, CodeGenOptLevel)
createHybridListDAGScheduler - This creates a bottom up register pressure aware list scheduler that m...
ScheduleDAGSDNodes * createFastDAGScheduler(SelectionDAGISel *IS, CodeGenOptLevel OptLevel)
createFastDAGScheduler - This creates a "fast" scheduler.
FunctionPass * createDefaultPBQPRegisterAllocator()
PBQPRegisterAllocation Pass - This pass implements the Partitioned Boolean Quadratic Prograaming (PBQ...
FunctionPass * createBasicRegisterAllocator()
BasicRegisterAllocation Pass - This pass implements a degenerate global register allocator using the ...
ScheduleDAGSDNodes * createSourceListDAGScheduler(SelectionDAGISel *IS, CodeGenOptLevel OptLevel)
createSourceListDAGScheduler - This creates a bottom up list scheduler that schedules nodes in source...
ScheduleDAGSDNodes * createVLIWDAGScheduler(SelectionDAGISel *IS, CodeGenOptLevel OptLevel)
createVLIWDAGScheduler - Scheduler for VLIW targets.