LLVM API Documentation

LiveStackAnalysis.cpp
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00001 //===-- LiveStackAnalysis.cpp - Live Stack Slot Analysis ------------------===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file implements the live stack slot analysis pass. It is analogous to
00011 // live interval analysis except it's analyzing liveness of stack slots rather
00012 // than registers.
00013 //
00014 //===----------------------------------------------------------------------===//
00015 
00016 #define DEBUG_TYPE "livestacks"
00017 #include "llvm/CodeGen/LiveStackAnalysis.h"
00018 #include "llvm/ADT/Statistic.h"
00019 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
00020 #include "llvm/CodeGen/Passes.h"
00021 #include "llvm/Support/Debug.h"
00022 #include "llvm/Support/raw_ostream.h"
00023 #include "llvm/Target/TargetRegisterInfo.h"
00024 #include <limits>
00025 using namespace llvm;
00026 
00027 char LiveStacks::ID = 0;
00028 INITIALIZE_PASS_BEGIN(LiveStacks, "livestacks",
00029                 "Live Stack Slot Analysis", false, false)
00030 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
00031 INITIALIZE_PASS_END(LiveStacks, "livestacks",
00032                 "Live Stack Slot Analysis", false, false)
00033 
00034 char &llvm::LiveStacksID = LiveStacks::ID;
00035 
00036 void LiveStacks::getAnalysisUsage(AnalysisUsage &AU) const {
00037   AU.setPreservesAll();
00038   AU.addPreserved<SlotIndexes>();
00039   AU.addRequiredTransitive<SlotIndexes>();
00040   MachineFunctionPass::getAnalysisUsage(AU);
00041 }
00042 
00043 void LiveStacks::releaseMemory() {
00044   // Release VNInfo memory regions, VNInfo objects don't need to be dtor'd.
00045   VNInfoAllocator.Reset();
00046   S2IMap.clear();
00047   S2RCMap.clear();
00048 }
00049 
00050 bool LiveStacks::runOnMachineFunction(MachineFunction &MF) {
00051   TRI = MF.getTarget().getRegisterInfo();
00052   // FIXME: No analysis is being done right now. We are relying on the
00053   // register allocators to provide the information.
00054   return false;
00055 }
00056 
00057 LiveInterval &
00058 LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) {
00059   assert(Slot >= 0 && "Spill slot indice must be >= 0");
00060   SS2IntervalMap::iterator I = S2IMap.find(Slot);
00061   if (I == S2IMap.end()) {
00062     I = S2IMap.insert(I, std::make_pair(Slot,
00063             LiveInterval(TargetRegisterInfo::index2StackSlot(Slot), 0.0F)));
00064     S2RCMap.insert(std::make_pair(Slot, RC));
00065   } else {
00066     // Use the largest common subclass register class.
00067     const TargetRegisterClass *OldRC = S2RCMap[Slot];
00068     S2RCMap[Slot] = TRI->getCommonSubClass(OldRC, RC);
00069   }
00070   return I->second;
00071 }
00072 
00073 /// print - Implement the dump method.
00074 void LiveStacks::print(raw_ostream &OS, const Module*) const {
00075 
00076   OS << "********** INTERVALS **********\n";
00077   for (const_iterator I = begin(), E = end(); I != E; ++I) {
00078     I->second.print(OS);
00079     int Slot = I->first;
00080     const TargetRegisterClass *RC = getIntervalRegClass(Slot);
00081     if (RC)
00082       OS << " [" << RC->getName() << "]\n";
00083     else
00084       OS << " [Unknown]\n";
00085   }
00086 }