LLVM 19.0.0git
MSP430ISelLowering.h
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1//===-- MSP430ISelLowering.h - MSP430 DAG Lowering Interface ----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the interfaces that MSP430 uses to lower LLVM code into a
10// selection DAG.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_MSP430_MSP430ISELLOWERING_H
15#define LLVM_LIB_TARGET_MSP430_MSP430ISELLOWERING_H
16
17#include "MSP430.h"
20
21namespace llvm {
22 namespace MSP430ISD {
23 enum NodeType : unsigned {
25
26 /// Return with a glue operand. Operand 0 is the chain operand.
28
29 /// Same as RET_GLUE, but used for returning from ISRs.
31
32 /// Y = R{R,L}A X, rotate right (left) arithmetically
34
35 /// Y = RRC X, rotate right via carry
37
38 /// Rotate right via carry, carry gets cleared beforehand by clrc
40
41 /// CALL - These operations represent an abstract call
42 /// instruction, which includes a bunch of information.
44
45 /// Wrapper - A wrapper node for TargetConstantPool, TargetExternalSymbol,
46 /// and TargetGlobalAddress.
48
49 /// CMP - Compare instruction.
51
52 /// SetCC - Operand 0 is condition code, and operand 1 is the flag
53 /// operand produced by a CMP instruction.
55
56 /// MSP430 conditional branches. Operand 0 is the chain operand, operand 1
57 /// is the block to branch if condition is true, operand 2 is the
58 /// condition code, and operand 3 is the flag operand produced by a CMP
59 /// instruction.
61
62 /// SELECT_CC - Operand 0 and operand 1 are selection variable, operand 3
63 /// is condition code and operand 4 is flag operand.
65
66 /// DADD - Decimal addition with carry
67 /// TODO Nothing generates a node of this type yet.
69 };
70 }
71
72 class MSP430Subtarget;
74 public:
76 const MSP430Subtarget &STI);
77
78 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
79 return MVT::i8;
80 }
81
83 return MVT::i16;
84 }
85
86 /// LowerOperation - Provide custom lowering hooks for some operations.
87 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
88
89 /// getTargetNodeName - This method returns the name of a target specific
90 /// DAG node.
91 const char *getTargetNodeName(unsigned Opcode) const override;
92
106
108 getConstraintType(StringRef Constraint) const override;
109 std::pair<unsigned, const TargetRegisterClass *>
111 StringRef Constraint, MVT VT) const override;
112
113 /// isTruncateFree - Return true if it's free to truncate a value of type
114 /// Ty1 to type Ty2. e.g. On msp430 it's free to truncate a i16 value in
115 /// register R15W to i8 by referencing its sub-register R15B.
116 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
117 bool isTruncateFree(EVT VT1, EVT VT2) const override;
118
119 /// isZExtFree - Return true if any actual instruction that defines a value
120 /// of type Ty1 implicit zero-extends the value to Ty2 in the result
121 /// register. This does not necessarily include registers defined in unknown
122 /// ways, such as incoming arguments, or copies from unknown virtual
123 /// registers. Also, if isTruncateFree(Ty2, Ty1) is true, this does not
124 /// necessarily apply to truncate instructions. e.g. on msp430, all
125 /// instructions that define 8-bit values implicit zero-extend the result
126 /// out to 16 bits.
127 bool isZExtFree(Type *Ty1, Type *Ty2) const override;
128 bool isZExtFree(EVT VT1, EVT VT2) const override;
129
130 bool isLegalICmpImmediate(int64_t) const override;
131 bool shouldAvoidTransformToShift(EVT VT, unsigned Amount) const override;
132
135 MachineBasicBlock *BB) const override;
137 MachineBasicBlock *BB) const;
138
139 private:
140 SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
141 CallingConv::ID CallConv, bool isVarArg,
142 bool isTailCall,
144 const SmallVectorImpl<SDValue> &OutVals,
146 const SDLoc &dl, SelectionDAG &DAG,
147 SmallVectorImpl<SDValue> &InVals) const;
148
149 SDValue LowerCCCArguments(SDValue Chain, CallingConv::ID CallConv,
150 bool isVarArg,
152 const SDLoc &dl, SelectionDAG &DAG,
153 SmallVectorImpl<SDValue> &InVals) const;
154
155 SDValue LowerCallResult(SDValue Chain, SDValue InGlue,
156 CallingConv::ID CallConv, bool isVarArg,
158 const SDLoc &dl, SelectionDAG &DAG,
159 SmallVectorImpl<SDValue> &InVals) const;
160
161 SDValue
162 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
164 const SDLoc &dl, SelectionDAG &DAG,
165 SmallVectorImpl<SDValue> &InVals) const override;
166 SDValue
168 SmallVectorImpl<SDValue> &InVals) const override;
169
170 bool CanLowerReturn(CallingConv::ID CallConv,
171 MachineFunction &MF,
172 bool IsVarArg,
174 LLVMContext &Context) const override;
175
176 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
178 const SmallVectorImpl<SDValue> &OutVals,
179 const SDLoc &dl, SelectionDAG &DAG) const override;
180
181 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
182 SDValue &Base,
185 SelectionDAG &DAG) const override;
186 };
187} // namespace llvm
188
189#endif
IRTranslator LLVM IR MI
unsigned const TargetRegisterInfo * TRI
const char LLVMTargetMachineRef TM
This file describes how to lower LLVM code to machine code.
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:110
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
LowerOperation - Provide custom lowering hooks for some operations.
MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override
Return the type to use for a scalar shift opcode, given the shifted amount type.
MVT::SimpleValueType getCmpLibcallReturnType() const override
Return the ValueType for comparison libcalls.
MachineBasicBlock * EmitShiftInstr(MachineInstr &MI, MachineBasicBlock *BB) const
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const
bool isTruncateFree(Type *Ty1, Type *Ty2) const override
isTruncateFree - Return true if it's free to truncate a value of type Ty1 to type Ty2.
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const
SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const
const char * getTargetNodeName(unsigned Opcode) const override
getTargetNodeName - This method returns the name of a target specific DAG node.
SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const
bool shouldAvoidTransformToShift(EVT VT, unsigned Amount) const override
Return true if creating a shift of the type by the given amount is not profitable.
bool isZExtFree(Type *Ty1, Type *Ty2) const override
isZExtFree - Return true if any actual instruction that defines a value of type Ty1 implicit zero-ext...
TargetLowering::ConstraintType getConstraintType(StringRef Constraint) const override
getConstraintType - Given a constraint letter, return the type of constraint it is for this target.
bool isLegalICmpImmediate(int64_t) const override
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
Machine Value Type.
Representation of each machine instruction.
Definition: MachineInstr.h:69
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:225
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:76
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:1400
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:1472
@ CALL
CALL - These operations represent an abstract call instruction, which includes a bunch of information...
@ RRA
Y = R{R,L}A X, rotate right (left) arithmetically.
@ BR_CC
MSP430 conditional branches.
@ DADD
DADD - Decimal addition with carry TODO Nothing generates a node of this type yet.
@ SETCC
SetCC - Operand 0 is condition code, and operand 1 is the flag operand produced by a CMP instruction.
@ RRCL
Rotate right via carry, carry gets cleared beforehand by clrc.
@ RETI_GLUE
Same as RET_GLUE, but used for returning from ISRs.
@ SELECT_CC
SELECT_CC - Operand 0 and operand 1 are selection variable, operand 3 is condition code and operand 4...
@ CMP
CMP - Compare instruction.
@ RRC
Y = RRC X, rotate right via carry.
@ Wrapper
Wrapper - A wrapper node for TargetConstantPool, TargetExternalSymbol, and TargetGlobalAddress.
@ RET_GLUE
Return with a glue operand. Operand 0 is the chain operand.
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Offset
Definition: DWP.cpp:456
#define N
Extended Value Type.
Definition: ValueTypes.h:34
This structure contains all information that is necessary for lowering calls.