94 struct MachineVerifier {
95 MachineVerifier(
Pass *
pass,
const char *b) : PASS(
pass), Banner(
b) {}
100 : Banner(
b), LiveVars(LiveVars), LiveInts(LiveInts), LiveStks(LiveStks),
105 Pass *
const PASS =
nullptr;
114 unsigned foundErrors = 0;
117 bool isFunctionRegBankSelected =
false;
118 bool isFunctionSelected =
false;
119 bool isFunctionTracksDebugUserValues =
false;
129 BlockSet FunctionBlocks;
133 RegVector regsDefined, regsDead, regsKilled;
134 RegMaskVector regMasks;
139 void addRegWithSubRegs(RegVector &RV,
Register Reg) {
141 if (
Reg.isPhysical())
147 bool reachable =
false;
168 RegSet vregsRequired;
171 BlockSet Preds, Succs;
178 if (!
Reg.isVirtual())
180 if (regsLiveOut.count(Reg))
182 return vregsRequired.insert(Reg).second;
186 bool addRequired(
const RegSet &RS) {
187 bool Changed =
false;
189 Changed |= addRequired(Reg);
194 bool addRequired(
const RegMap &RM) {
195 bool Changed =
false;
196 for (
const auto &
I : RM)
197 Changed |= addRequired(
I.first);
203 return regsLiveOut.count(Reg) || vregsPassed.count(Reg);
211 return Reg.id() < regsReserved.
size() && regsReserved.
test(
Reg.id());
214 bool isAllocatable(
Register Reg)
const {
215 return Reg.id() <
TRI->getNumRegs() &&
TRI->isInAllocatableClass(Reg) &&
230 void visitMachineFunctionBefore();
246 void visitMachineOperand(
const MachineOperand *MO,
unsigned MONum);
249 void visitMachineFunctionAfter();
254 void report(
const char *msg,
const MachineOperand *MO,
unsigned MONum,
262 void report_context(
const VNInfo &VNI)
const;
263 void report_context(
SlotIndex Pos)
const;
264 void report_context(
MCPhysReg PhysReg)
const;
265 void report_context_liverange(
const LiveRange &LR)
const;
266 void report_context_lanemask(
LaneBitmask LaneMask)
const;
267 void report_context_vreg(
Register VReg)
const;
268 void report_context_vreg_regunit(
Register VRegOrUnit)
const;
279 Register VRegOrUnit,
bool SubRangeCheck =
false,
283 void calcRegsPassed();
286 void calcRegsRequired();
287 void verifyLiveVariables();
288 void verifyLiveIntervals();
292 void verifyLiveRangeSegment(
const LiveRange &,
298 void verifyStackFrame();
300 void verifySlotIndexes()
const;
307 const std::string Banner;
309 MachineVerifierPass(std::string banner = std::string())
328 MachineFunctionProperties::Property::FailsVerification))
331 unsigned FoundErrors = MachineVerifier(
this, Banner.c_str()).verify(MF);
340char MachineVerifierPass::ID = 0;
343 "Verify generated machine code",
false,
false)
346 return new MachineVerifierPass(Banner);
356 unsigned FoundErrors = MachineVerifier(
nullptr, Banner.c_str()).verify(MF);
364 unsigned FoundErrors = MachineVerifier(p, Banner).verify(MF);
365 if (AbortOnErrors && FoundErrors)
367 return FoundErrors == 0;
371 const char *Banner,
bool AbortOnErrors)
const {
373 unsigned FoundErrors =
374 MachineVerifier(Banner,
nullptr, LiveInts,
nullptr, Indexes).verify(MF);
375 if (AbortOnErrors && FoundErrors)
377 return FoundErrors == 0;
380void MachineVerifier::verifySlotIndexes()
const {
381 if (Indexes ==
nullptr)
399 MRI->getNumVirtRegs())
400 report(
"Function has NoVRegs property but there are VReg operands", &MF);
419 if (isFunctionFailedISel)
440 verifyProperties(MF);
442 visitMachineFunctionBefore();
444 visitMachineBasicBlockBefore(&
MBB);
448 bool InBundle =
false;
451 if (
MI.getParent() != &
MBB) {
452 report(
"Bad instruction parent pointer", &
MBB);
453 errs() <<
"Instruction: " <<
MI;
458 if (InBundle && !
MI.isBundledWithPred())
459 report(
"Missing BundledPred flag, "
460 "BundledSucc was set on predecessor",
462 if (!InBundle &&
MI.isBundledWithPred())
463 report(
"BundledPred flag is set, "
464 "but BundledSucc not set on predecessor",
468 if (!
MI.isInsideBundle()) {
470 visitMachineBundleAfter(CurBundle);
472 visitMachineBundleBefore(CurBundle);
473 }
else if (!CurBundle)
474 report(
"No bundle header", &
MI);
475 visitMachineInstrBefore(&
MI);
476 for (
unsigned I = 0, E =
MI.getNumOperands();
I != E; ++
I) {
478 if (
Op.getParent() != &
MI) {
481 report(
"Instruction has operand with wrong parent set", &
MI);
484 visitMachineOperand(&
Op,
I);
488 InBundle =
MI.isBundledWithSucc();
491 visitMachineBundleAfter(CurBundle);
493 report(
"BundledSucc flag set on last instruction in block", &
MBB.
back());
494 visitMachineBasicBlockAfter(&
MBB);
496 visitMachineFunctionAfter();
509void MachineVerifier::report(
const char *msg,
const MachineFunction *MF) {
512 if (!foundErrors++) {
514 errs() <<
"# " << Banner <<
'\n';
515 if (LiveInts !=
nullptr)
520 errs() <<
"*** Bad machine code: " << msg <<
" ***\n"
521 <<
"- function: " << MF->
getName() <<
"\n";
535void MachineVerifier::report(
const char *msg,
const MachineInstr *
MI) {
537 report(msg,
MI->getParent());
538 errs() <<
"- instruction: ";
544void MachineVerifier::report(
const char *msg,
const MachineOperand *MO,
545 unsigned MONum,
LLT MOVRegType) {
548 errs() <<
"- operand " << MONum <<
": ";
554 report(
Msg.str().c_str(),
MI);
557void MachineVerifier::report_context(
SlotIndex Pos)
const {
558 errs() <<
"- at: " << Pos <<
'\n';
561void MachineVerifier::report_context(
const LiveInterval &LI)
const {
562 errs() <<
"- interval: " << LI <<
'\n';
567 report_context_liverange(LR);
568 report_context_vreg_regunit(VRegUnit);
570 report_context_lanemask(LaneMask);
574 errs() <<
"- segment: " << S <<
'\n';
577void MachineVerifier::report_context(
const VNInfo &VNI)
const {
578 errs() <<
"- ValNo: " << VNI.
id <<
" (def " << VNI.
def <<
")\n";
581void MachineVerifier::report_context_liverange(
const LiveRange &LR)
const {
582 errs() <<
"- liverange: " << LR <<
'\n';
585void MachineVerifier::report_context(
MCPhysReg PReg)
const {
589void MachineVerifier::report_context_vreg(
Register VReg)
const {
593void MachineVerifier::report_context_vreg_regunit(
Register VRegOrUnit)
const {
595 report_context_vreg(VRegOrUnit);
601void MachineVerifier::report_context_lanemask(
LaneBitmask LaneMask)
const {
606 BBInfo &MInfo = MBBInfoMap[
MBB];
607 if (!MInfo.reachable) {
608 MInfo.reachable =
true;
614void MachineVerifier::visitMachineFunctionBefore() {
616 regsReserved =
MRI->reservedRegsFrozen() ?
MRI->getReservedRegs()
617 :
TRI->getReservedRegs(*MF);
620 markReachable(&MF->
front());
623 FunctionBlocks.clear();
624 for (
const auto &
MBB : *MF) {
625 FunctionBlocks.insert(&
MBB);
626 BBInfo &MInfo = MBBInfoMap[&
MBB];
630 report(
"MBB has duplicate entries in its predecessor list.", &
MBB);
634 report(
"MBB has duplicate entries in its successor list.", &
MBB);
638 MRI->verifyUseLists();
646 FirstTerminator =
nullptr;
647 FirstNonPHI =
nullptr;
649 if (!MF->getProperties().hasProperty(
654 if (isAllocatable(LI.PhysReg) && !
MBB->
isEHPad() &&
657 report(
"MBB has allocatable live-in, but isn't entry, landing-pad, or "
658 "inlineasm-br-indirect-target.",
660 report_context(LI.PhysReg);
667 report(
"ir-block-address-taken is associated with basic block not used by "
676 LandingPadSuccs.
insert(succ);
677 if (!FunctionBlocks.count(succ))
678 report(
"MBB has successor that isn't part of the function.",
MBB);
679 if (!MBBInfoMap[succ].Preds.count(
MBB)) {
680 report(
"Inconsistent CFG",
MBB);
681 errs() <<
"MBB is not in the predecessor list of the successor "
688 if (!FunctionBlocks.count(Pred))
689 report(
"MBB has predecessor that isn't part of the function.",
MBB);
690 if (!MBBInfoMap[Pred].Succs.count(
MBB)) {
691 report(
"Inconsistent CFG",
MBB);
692 errs() <<
"MBB is not in the successor list of the predecessor "
700 if (LandingPadSuccs.
size() > 1 &&
705 report(
"MBB has more than one landing pad successor",
MBB);
718 report(
"MBB exits via unconditional fall-through but ends with a "
719 "barrier instruction!",
MBB);
722 report(
"MBB exits via unconditional fall-through but has a condition!",
725 }
else if (
TBB && !FBB &&
Cond.empty()) {
728 report(
"MBB exits via unconditional branch but doesn't contain "
729 "any instructions!",
MBB);
731 report(
"MBB exits via unconditional branch but doesn't end with a "
732 "barrier instruction!",
MBB);
734 report(
"MBB exits via unconditional branch but the branch isn't a "
735 "terminator instruction!",
MBB);
737 }
else if (
TBB && !FBB && !
Cond.empty()) {
740 report(
"MBB exits via conditional branch/fall-through but doesn't "
741 "contain any instructions!",
MBB);
743 report(
"MBB exits via conditional branch/fall-through but ends with a "
744 "barrier instruction!",
MBB);
746 report(
"MBB exits via conditional branch/fall-through but the branch "
747 "isn't a terminator instruction!",
MBB);
749 }
else if (
TBB && FBB) {
753 report(
"MBB exits via conditional branch/branch but doesn't "
754 "contain any instructions!",
MBB);
756 report(
"MBB exits via conditional branch/branch but doesn't end with a "
757 "barrier instruction!",
MBB);
759 report(
"MBB exits via conditional branch/branch but the branch "
760 "isn't a terminator instruction!",
MBB);
763 report(
"MBB exits via conditional branch/branch but there's no "
767 report(
"analyzeBranch returned invalid data!",
MBB);
773 report(
"MBB exits via jump or conditional branch, but its target isn't a "
777 report(
"MBB exits via conditional branch, but its target isn't a CFG "
784 bool Fallthrough = !
TBB || (!
Cond.empty() && !FBB);
789 if (!
Cond.empty() && !FBB) {
792 report(
"MBB conditionally falls through out of function!",
MBB);
794 report(
"MBB exits via conditional branch/fall-through but the CFG "
795 "successors don't match the actual successors!",
802 if (SuccMBB ==
TBB || SuccMBB == FBB)
810 if (SuccMBB->isEHPad() || SuccMBB->isInlineAsmBrIndirectTarget())
812 report(
"MBB has unexpected successors which are not branch targets, "
813 "fallthrough, EHPads, or inlineasm_br targets.",
819 if (
MRI->tracksLiveness()) {
822 report(
"MBB live-in list contains non-physical register",
MBB);
846void MachineVerifier::visitMachineBundleBefore(
const MachineInstr *
MI) {
849 if (!(idx > lastIndex)) {
850 report(
"Instruction index out of order",
MI);
851 errs() <<
"Last instruction was at " << lastIndex <<
'\n';
857 if (
MI->isTerminator()) {
858 if (!FirstTerminator)
859 FirstTerminator =
MI;
860 }
else if (FirstTerminator) {
863 if (FirstTerminator->
getOpcode() != TargetOpcode::G_INVOKE_REGION_START) {
864 report(
"Non-terminator instruction after the first terminator",
MI);
865 errs() <<
"First terminator was:\t" << *FirstTerminator;
874 if (
MI->getNumOperands() < 2) {
875 report(
"Too few operands on inline asm",
MI);
878 if (!
MI->getOperand(0).isSymbol())
879 report(
"Asm string must be an external symbol",
MI);
880 if (!
MI->getOperand(1).isImm())
881 report(
"Asm flags must be an immediate",
MI);
885 if (!isUInt<6>(
MI->getOperand(1).getImm()))
886 report(
"Unknown asm flags", &
MI->getOperand(1), 1);
892 for (
unsigned e =
MI->getNumOperands(); OpNo <
e; OpNo += NumOps) {
898 NumOps = 1 +
F.getNumOperandRegisters();
901 if (OpNo >
MI->getNumOperands())
902 report(
"Missing operands in last group",
MI);
905 if (OpNo < MI->getNumOperands() &&
MI->getOperand(OpNo).isMetadata())
909 for (
unsigned e =
MI->getNumOperands(); OpNo < e; ++OpNo) {
912 report(
"Expected implicit register after groups", &MO, OpNo);
915 if (
MI->getOpcode() == TargetOpcode::INLINEASM_BR) {
928 if (!IndirectTargetMBB) {
929 report(
"INLINEASM_BR indirect target does not exist", &MO, i);
934 report(
"INLINEASM_BR indirect target missing from successor list", &MO,
938 report(
"INLINEASM_BR indirect target predecessor list missing parent",
944bool MachineVerifier::verifyAllRegOpsScalar(
const MachineInstr &
MI,
949 const auto Reg = Op.getReg();
950 if (Reg.isPhysical())
952 return !MRI.getType(Reg).isScalar();
955 report(
"All register operands must have scalar types", &
MI);
962bool MachineVerifier::verifyVectorElementMatch(
LLT Ty0,
LLT Ty1,
965 report(
"operand types must be all-vector or all-scalar",
MI);
975 report(
"operand types must preserve number of vector elements",
MI);
982bool MachineVerifier::verifyGIntrinsicSideEffects(
const MachineInstr *
MI) {
983 auto Opcode =
MI->getOpcode();
984 bool NoSideEffects = Opcode == TargetOpcode::G_INTRINSIC ||
985 Opcode == TargetOpcode::G_INTRINSIC_CONVERGENT;
986 unsigned IntrID = cast<GIntrinsic>(
MI)->getIntrinsicID();
987 if (IntrID != 0 && IntrID < Intrinsic::num_intrinsics) {
989 MF->getFunction().getContext(),
static_cast<Intrinsic::ID>(IntrID));
990 bool DeclHasSideEffects = !
Attrs.getMemoryEffects().doesNotAccessMemory();
991 if (NoSideEffects && DeclHasSideEffects) {
993 " used with intrinsic that accesses memory"),
997 if (!NoSideEffects && !DeclHasSideEffects) {
998 report(
Twine(
TII->getName(Opcode),
" used with readnone intrinsic"),
MI);
1006bool MachineVerifier::verifyGIntrinsicConvergence(
const MachineInstr *
MI) {
1007 auto Opcode =
MI->getOpcode();
1008 bool NotConvergent = Opcode == TargetOpcode::G_INTRINSIC ||
1009 Opcode == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS;
1010 unsigned IntrID = cast<GIntrinsic>(
MI)->getIntrinsicID();
1011 if (IntrID != 0 && IntrID < Intrinsic::num_intrinsics) {
1013 MF->getFunction().getContext(),
static_cast<Intrinsic::ID>(IntrID));
1014 bool DeclIsConvergent =
Attrs.hasFnAttr(Attribute::Convergent);
1015 if (NotConvergent && DeclIsConvergent) {
1016 report(
Twine(
TII->getName(Opcode),
" used with a convergent intrinsic"),
1020 if (!NotConvergent && !DeclIsConvergent) {
1022 Twine(
TII->getName(Opcode),
" used with a non-convergent intrinsic"),
1031void MachineVerifier::verifyPreISelGenericInstruction(
const MachineInstr *
MI) {
1032 if (isFunctionSelected)
1033 report(
"Unexpected generic instruction in a Selected function",
MI);
1036 unsigned NumOps =
MI->getNumOperands();
1039 if (
MI->isBranch() && !
MI->isIndirectBranch()) {
1040 bool HasMBB =
false;
1049 report(
"Branch instruction is missing a basic block operand or "
1050 "isIndirectBranch property",
1059 if (!MCID.
operands()[
I].isGenericType())
1063 size_t TypeIdx = MCID.
operands()[
I].getGenericTypeIndex();
1064 Types.resize(std::max(TypeIdx + 1,
Types.size()));
1068 report(
"generic instruction must use register operands",
MI);
1078 if (!Types[TypeIdx].
isValid())
1079 Types[TypeIdx] = OpTy;
1080 else if (Types[TypeIdx] != OpTy)
1081 report(
"Type mismatch in generic instruction", MO,
I, OpTy);
1084 report(
"Generic instruction is missing a virtual register type", MO,
I);
1089 for (
unsigned I = 0;
I <
MI->getNumOperands(); ++
I) {
1092 report(
"Generic instruction cannot have physical register", MO,
I);
1104 unsigned Opc =
MI->getOpcode();
1106 case TargetOpcode::G_ASSERT_SEXT:
1107 case TargetOpcode::G_ASSERT_ZEXT: {
1108 std::string OpcName =
1109 Opc == TargetOpcode::G_ASSERT_ZEXT ?
"G_ASSERT_ZEXT" :
"G_ASSERT_SEXT";
1110 if (!
MI->getOperand(2).isImm()) {
1111 report(
Twine(OpcName,
" expects an immediate operand #2"),
MI);
1117 LLT SrcTy =
MRI->getType(Src);
1118 int64_t
Imm =
MI->getOperand(2).getImm();
1120 report(
Twine(OpcName,
" size must be >= 1"),
MI);
1125 report(
Twine(OpcName,
" size must be less than source bit width"),
MI);
1133 if ((SrcRB && DstRB && SrcRB != DstRB) || (DstRB && !SrcRB)) {
1134 report(
Twine(OpcName,
" cannot change register bank"),
MI);
1140 if (DstRC && DstRC !=
MRI->getRegClassOrNull(Src)) {
1142 Twine(OpcName,
" source and destination register classes must match"),
1150 case TargetOpcode::G_CONSTANT:
1151 case TargetOpcode::G_FCONSTANT: {
1152 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1154 report(
"Instruction cannot use a vector result type",
MI);
1156 if (
MI->getOpcode() == TargetOpcode::G_CONSTANT) {
1157 if (!
MI->getOperand(1).isCImm()) {
1158 report(
"G_CONSTANT operand must be cimm",
MI);
1164 report(
"inconsistent constant size",
MI);
1166 if (!
MI->getOperand(1).isFPImm()) {
1167 report(
"G_FCONSTANT operand must be fpimm",
MI);
1174 report(
"inconsistent constant size",
MI);
1180 case TargetOpcode::G_LOAD:
1181 case TargetOpcode::G_STORE:
1182 case TargetOpcode::G_ZEXTLOAD:
1183 case TargetOpcode::G_SEXTLOAD: {
1184 LLT ValTy =
MRI->getType(
MI->getOperand(0).getReg());
1185 LLT PtrTy =
MRI->getType(
MI->getOperand(1).getReg());
1187 report(
"Generic memory instruction must access a pointer",
MI);
1191 if (!
MI->hasOneMemOperand()) {
1192 report(
"Generic instruction accessing memory must have one mem operand",
1196 if (
MI->getOpcode() == TargetOpcode::G_ZEXTLOAD ||
1197 MI->getOpcode() == TargetOpcode::G_SEXTLOAD) {
1200 report(
"Generic extload must have a narrower memory type",
MI);
1201 }
else if (
MI->getOpcode() == TargetOpcode::G_LOAD) {
1204 report(
"load memory size cannot exceed result size",
MI);
1205 }
else if (
MI->getOpcode() == TargetOpcode::G_STORE) {
1208 report(
"store memory size cannot exceed value size",
MI);
1212 if (Opc == TargetOpcode::G_STORE) {
1215 report(
"atomic store cannot use acquire ordering",
MI);
1220 report(
"atomic load cannot use release ordering",
MI);
1226 case TargetOpcode::G_PHI: {
1227 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1232 LLT Ty = MRI->getType(MO.getReg());
1233 if (!Ty.isValid() || (Ty != DstTy))
1237 report(
"Generic Instruction G_PHI has operands with incompatible/missing "
1242 case TargetOpcode::G_BITCAST: {
1243 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1244 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1249 report(
"bitcast cannot convert between pointers and other types",
MI);
1252 report(
"bitcast sizes must match",
MI);
1255 report(
"bitcast must change the type",
MI);
1259 case TargetOpcode::G_INTTOPTR:
1260 case TargetOpcode::G_PTRTOINT:
1261 case TargetOpcode::G_ADDRSPACE_CAST: {
1262 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1263 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1267 verifyVectorElementMatch(DstTy, SrcTy,
MI);
1272 if (
MI->getOpcode() == TargetOpcode::G_INTTOPTR) {
1274 report(
"inttoptr result type must be a pointer",
MI);
1276 report(
"inttoptr source type must not be a pointer",
MI);
1277 }
else if (
MI->getOpcode() == TargetOpcode::G_PTRTOINT) {
1279 report(
"ptrtoint source type must be a pointer",
MI);
1281 report(
"ptrtoint result type must not be a pointer",
MI);
1283 assert(
MI->getOpcode() == TargetOpcode::G_ADDRSPACE_CAST);
1285 report(
"addrspacecast types must be pointers",
MI);
1288 report(
"addrspacecast must convert different address spaces",
MI);
1294 case TargetOpcode::G_PTR_ADD: {
1295 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1296 LLT PtrTy =
MRI->getType(
MI->getOperand(1).getReg());
1297 LLT OffsetTy =
MRI->getType(
MI->getOperand(2).getReg());
1302 report(
"gep first operand must be a pointer",
MI);
1305 report(
"gep offset operand must not be a pointer",
MI);
1310 unsigned IndexSizeInBits =
DL.getIndexSize(AS) * 8;
1312 report(
"gep offset operand must match index size for address space",
1320 case TargetOpcode::G_PTRMASK: {
1321 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1322 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1323 LLT MaskTy =
MRI->getType(
MI->getOperand(2).getReg());
1328 report(
"ptrmask result type must be a pointer",
MI);
1331 report(
"ptrmask mask type must be an integer",
MI);
1333 verifyVectorElementMatch(DstTy, MaskTy,
MI);
1336 case TargetOpcode::G_SEXT:
1337 case TargetOpcode::G_ZEXT:
1338 case TargetOpcode::G_ANYEXT:
1339 case TargetOpcode::G_TRUNC:
1340 case TargetOpcode::G_FPEXT:
1341 case TargetOpcode::G_FPTRUNC: {
1348 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1349 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1354 report(
"Generic extend/truncate can not operate on pointers",
MI);
1356 verifyVectorElementMatch(DstTy, SrcTy,
MI);
1360 switch (
MI->getOpcode()) {
1362 if (DstSize <= SrcSize)
1363 report(
"Generic extend has destination type no larger than source",
MI);
1365 case TargetOpcode::G_TRUNC:
1366 case TargetOpcode::G_FPTRUNC:
1367 if (DstSize >= SrcSize)
1368 report(
"Generic truncate has destination type no smaller than source",
1374 case TargetOpcode::G_SELECT: {
1375 LLT SelTy =
MRI->getType(
MI->getOperand(0).getReg());
1376 LLT CondTy =
MRI->getType(
MI->getOperand(1).getReg());
1382 verifyVectorElementMatch(SelTy, CondTy,
MI);
1385 case TargetOpcode::G_MERGE_VALUES: {
1390 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1391 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1393 report(
"G_MERGE_VALUES cannot operate on vectors",
MI);
1395 const unsigned NumOps =
MI->getNumOperands();
1397 report(
"G_MERGE_VALUES result size is inconsistent",
MI);
1399 for (
unsigned I = 2;
I != NumOps; ++
I) {
1400 if (
MRI->getType(
MI->getOperand(
I).getReg()) != SrcTy)
1401 report(
"G_MERGE_VALUES source types do not match",
MI);
1406 case TargetOpcode::G_UNMERGE_VALUES: {
1407 unsigned NumDsts =
MI->getNumOperands() - 1;
1408 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1409 for (
unsigned i = 1; i < NumDsts; ++i) {
1410 if (
MRI->getType(
MI->getOperand(i).getReg()) != DstTy) {
1411 report(
"G_UNMERGE_VALUES destination types do not match",
MI);
1416 LLT SrcTy =
MRI->getType(
MI->getOperand(NumDsts).getReg());
1422 report(
"G_UNMERGE_VALUES source operand does not match vector "
1423 "destination operands",
1430 report(
"G_UNMERGE_VALUES vector source operand does not match scalar "
1431 "destination operands",
1436 report(
"G_UNMERGE_VALUES scalar source operand does not match scalar "
1437 "destination operands",
1443 case TargetOpcode::G_BUILD_VECTOR: {
1446 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1447 LLT SrcEltTy =
MRI->getType(
MI->getOperand(1).getReg());
1449 report(
"G_BUILD_VECTOR must produce a vector from scalar operands",
MI);
1454 report(
"G_BUILD_VECTOR result element type must match source type",
MI);
1457 report(
"G_BUILD_VECTOR must have an operand for each elemement",
MI);
1460 if (
MRI->getType(
MI->getOperand(1).getReg()) !=
MRI->getType(MO.
getReg()))
1461 report(
"G_BUILD_VECTOR source operand types are not homogeneous",
MI);
1465 case TargetOpcode::G_BUILD_VECTOR_TRUNC: {
1468 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1469 LLT SrcEltTy =
MRI->getType(
MI->getOperand(1).getReg());
1471 report(
"G_BUILD_VECTOR_TRUNC must produce a vector from scalar operands",
1474 if (
MRI->getType(
MI->getOperand(1).getReg()) !=
MRI->getType(MO.
getReg()))
1475 report(
"G_BUILD_VECTOR_TRUNC source operand types are not homogeneous",
1478 report(
"G_BUILD_VECTOR_TRUNC source operand types are not larger than "
1483 case TargetOpcode::G_CONCAT_VECTORS: {
1486 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1487 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1489 report(
"G_CONCAT_VECTOR requires vector source and destination operands",
1492 if (
MI->getNumOperands() < 3)
1493 report(
"G_CONCAT_VECTOR requires at least 2 source operands",
MI);
1496 if (
MRI->getType(
MI->getOperand(1).getReg()) !=
MRI->getType(MO.
getReg()))
1497 report(
"G_CONCAT_VECTOR source operand types are not homogeneous",
MI);
1500 report(
"G_CONCAT_VECTOR num dest and source elements should match",
MI);
1503 case TargetOpcode::G_ICMP:
1504 case TargetOpcode::G_FCMP: {
1505 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1506 LLT SrcTy =
MRI->getType(
MI->getOperand(2).getReg());
1511 report(
"Generic vector icmp/fcmp must preserve number of lanes",
MI);
1515 case TargetOpcode::G_EXTRACT: {
1517 if (!
SrcOp.isReg()) {
1518 report(
"extract source must be a register",
MI);
1523 if (!OffsetOp.
isImm()) {
1524 report(
"extract offset must be a constant",
MI);
1528 unsigned DstSize =
MRI->getType(
MI->getOperand(0).getReg()).getSizeInBits();
1530 if (SrcSize == DstSize)
1531 report(
"extract source must be larger than result",
MI);
1533 if (DstSize + OffsetOp.
getImm() > SrcSize)
1534 report(
"extract reads past end of register",
MI);
1537 case TargetOpcode::G_INSERT: {
1539 if (!
SrcOp.isReg()) {
1540 report(
"insert source must be a register",
MI);
1545 if (!OffsetOp.
isImm()) {
1546 report(
"insert offset must be a constant",
MI);
1550 unsigned DstSize =
MRI->getType(
MI->getOperand(0).getReg()).getSizeInBits();
1553 if (DstSize <= SrcSize)
1554 report(
"inserted size must be smaller than total register",
MI);
1556 if (SrcSize + OffsetOp.
getImm() > DstSize)
1557 report(
"insert writes past end of register",
MI);
1561 case TargetOpcode::G_JUMP_TABLE: {
1562 if (!
MI->getOperand(1).isJTI())
1563 report(
"G_JUMP_TABLE source operand must be a jump table index",
MI);
1564 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1566 report(
"G_JUMP_TABLE dest operand must have a pointer type",
MI);
1569 case TargetOpcode::G_BRJT: {
1570 if (!
MRI->getType(
MI->getOperand(0).getReg()).isPointer())
1571 report(
"G_BRJT src operand 0 must be a pointer type",
MI);
1573 if (!
MI->getOperand(1).isJTI())
1574 report(
"G_BRJT src operand 1 must be a jump table index",
MI);
1576 const auto &IdxOp =
MI->getOperand(2);
1577 if (!IdxOp.isReg() ||
MRI->getType(IdxOp.getReg()).isPointer())
1578 report(
"G_BRJT src operand 2 must be a scalar reg type",
MI);
1581 case TargetOpcode::G_INTRINSIC:
1582 case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:
1583 case TargetOpcode::G_INTRINSIC_CONVERGENT:
1584 case TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS: {
1589 report(
"G_INTRINSIC first src operand must be an intrinsic ID",
MI);
1593 if (!verifyGIntrinsicSideEffects(
MI))
1595 if (!verifyGIntrinsicConvergence(
MI))
1600 case TargetOpcode::G_SEXT_INREG: {
1601 if (!
MI->getOperand(2).isImm()) {
1602 report(
"G_SEXT_INREG expects an immediate operand #2",
MI);
1606 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1607 int64_t
Imm =
MI->getOperand(2).getImm();
1609 report(
"G_SEXT_INREG size must be >= 1",
MI);
1611 report(
"G_SEXT_INREG size must be less than source bit width",
MI);
1614 case TargetOpcode::G_BSWAP: {
1615 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1617 report(
"G_BSWAP size must be a multiple of 16 bits",
MI);
1620 case TargetOpcode::G_VSCALE: {
1621 if (!
MI->getOperand(1).isCImm()) {
1622 report(
"G_VSCALE operand must be cimm",
MI);
1625 if (
MI->getOperand(1).getCImm()->isZero()) {
1626 report(
"G_VSCALE immediate cannot be zero",
MI);
1631 case TargetOpcode::G_INSERT_SUBVECTOR: {
1633 if (!Src0Op.
isReg()) {
1634 report(
"G_INSERT_SUBVECTOR first source must be a register",
MI);
1639 if (!Src1Op.
isReg()) {
1640 report(
"G_INSERT_SUBVECTOR second source must be a register",
MI);
1645 if (!IndexOp.
isImm()) {
1646 report(
"G_INSERT_SUBVECTOR index must be an immediate",
MI);
1650 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1655 report(
"Destination type must be a vector",
MI);
1660 report(
"First source must be a vector",
MI);
1665 report(
"Second source must be a vector",
MI);
1669 if (DstTy != Src0Ty) {
1670 report(
"Destination type must match the first source vector type",
MI);
1675 report(
"Element type of source vectors must be the same",
MI);
1679 if (IndexOp.
getImm() != 0 &&
1681 report(
"Index must be a multiple of the second source vector's "
1682 "minimum vector length",
1688 case TargetOpcode::G_EXTRACT_SUBVECTOR: {
1690 if (!
SrcOp.isReg()) {
1691 report(
"G_EXTRACT_SUBVECTOR first source must be a register",
MI);
1696 if (!IndexOp.
isImm()) {
1697 report(
"G_EXTRACT_SUBVECTOR index must be an immediate",
MI);
1701 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1705 report(
"Destination type must be a vector",
MI);
1710 report(
"First source must be a vector",
MI);
1715 report(
"Element type of vectors must be the same",
MI);
1719 if (IndexOp.
getImm() != 0 &&
1721 report(
"Index must be a multiple of the source vector's minimum vector "
1729 case TargetOpcode::G_SHUFFLE_VECTOR: {
1732 report(
"Incorrect mask operand type for G_SHUFFLE_VECTOR",
MI);
1736 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1737 LLT Src0Ty =
MRI->getType(
MI->getOperand(1).getReg());
1738 LLT Src1Ty =
MRI->getType(
MI->getOperand(2).getReg());
1740 if (Src0Ty != Src1Ty)
1741 report(
"Source operands must be the same type",
MI);
1744 report(
"G_SHUFFLE_VECTOR cannot change element type",
MI);
1753 if (
static_cast<int>(MaskIdxes.
size()) != DstNumElts)
1754 report(
"Wrong result type for shufflemask",
MI);
1756 for (
int Idx : MaskIdxes) {
1760 if (
Idx >= 2 * SrcNumElts)
1761 report(
"Out of bounds shuffle index",
MI);
1767 case TargetOpcode::G_SPLAT_VECTOR: {
1768 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1769 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1772 report(
"Destination type must be a scalable vector",
MI);
1775 report(
"Source type must be a scalar",
MI);
1778 report(
"Element type of the destination must be the same type as the "
1784 case TargetOpcode::G_DYN_STACKALLOC: {
1790 report(
"dst operand 0 must be a pointer type",
MI);
1794 if (!AllocOp.
isReg() || !
MRI->getType(AllocOp.
getReg()).isScalar()) {
1795 report(
"src operand 1 must be a scalar reg type",
MI);
1799 if (!AlignOp.
isImm()) {
1800 report(
"src operand 2 must be an immediate type",
MI);
1805 case TargetOpcode::G_MEMCPY_INLINE:
1806 case TargetOpcode::G_MEMCPY:
1807 case TargetOpcode::G_MEMMOVE: {
1809 if (MMOs.
size() != 2) {
1810 report(
"memcpy/memmove must have 2 memory operands",
MI);
1816 report(
"wrong memory operand types",
MI);
1821 report(
"inconsistent memory operand sizes",
MI);
1823 LLT DstPtrTy =
MRI->getType(
MI->getOperand(0).getReg());
1824 LLT SrcPtrTy =
MRI->getType(
MI->getOperand(1).getReg());
1827 report(
"memory instruction operand must be a pointer",
MI);
1832 report(
"inconsistent store address space",
MI);
1834 report(
"inconsistent load address space",
MI);
1836 if (Opc != TargetOpcode::G_MEMCPY_INLINE)
1837 if (!
MI->getOperand(3).isImm() || (
MI->getOperand(3).getImm() & ~1LL))
1838 report(
"'tail' flag (operand 3) must be an immediate 0 or 1",
MI);
1842 case TargetOpcode::G_BZERO:
1843 case TargetOpcode::G_MEMSET: {
1845 std::string
Name = Opc == TargetOpcode::G_MEMSET ?
"memset" :
"bzero";
1846 if (MMOs.
size() != 1) {
1847 report(
Twine(
Name,
" must have 1 memory operand"),
MI);
1852 report(
Twine(
Name,
" memory operand must be a store"),
MI);
1856 LLT DstPtrTy =
MRI->getType(
MI->getOperand(0).getReg());
1858 report(
Twine(
Name,
" operand must be a pointer"),
MI);
1863 report(
"inconsistent " +
Twine(
Name,
" address space"),
MI);
1865 if (!
MI->getOperand(
MI->getNumOperands() - 1).isImm() ||
1866 (
MI->getOperand(
MI->getNumOperands() - 1).getImm() & ~1LL))
1867 report(
"'tail' flag (last operand) must be an immediate 0 or 1",
MI);
1871 case TargetOpcode::G_UBSANTRAP: {
1873 if (!
MI->getOperand(0).isImm()) {
1874 report(
"Crash kind must be an immediate", &KindOp, 0);
1877 int64_t
Kind =
MI->getOperand(0).getImm();
1878 if (!isInt<8>(Kind))
1879 report(
"Crash kind must be 8 bit wide", &KindOp, 0);
1882 case TargetOpcode::G_VECREDUCE_SEQ_FADD:
1883 case TargetOpcode::G_VECREDUCE_SEQ_FMUL: {
1884 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1885 LLT Src1Ty =
MRI->getType(
MI->getOperand(1).getReg());
1886 LLT Src2Ty =
MRI->getType(
MI->getOperand(2).getReg());
1888 report(
"Vector reduction requires a scalar destination type",
MI);
1890 report(
"Sequential FADD/FMUL vector reduction requires a scalar 1st operand",
MI);
1892 report(
"Sequential FADD/FMUL vector reduction must have a vector 2nd operand",
MI);
1895 case TargetOpcode::G_VECREDUCE_FADD:
1896 case TargetOpcode::G_VECREDUCE_FMUL:
1897 case TargetOpcode::G_VECREDUCE_FMAX:
1898 case TargetOpcode::G_VECREDUCE_FMIN:
1899 case TargetOpcode::G_VECREDUCE_FMAXIMUM:
1900 case TargetOpcode::G_VECREDUCE_FMINIMUM:
1901 case TargetOpcode::G_VECREDUCE_ADD:
1902 case TargetOpcode::G_VECREDUCE_MUL:
1903 case TargetOpcode::G_VECREDUCE_AND:
1904 case TargetOpcode::G_VECREDUCE_OR:
1905 case TargetOpcode::G_VECREDUCE_XOR:
1906 case TargetOpcode::G_VECREDUCE_SMAX:
1907 case TargetOpcode::G_VECREDUCE_SMIN:
1908 case TargetOpcode::G_VECREDUCE_UMAX:
1909 case TargetOpcode::G_VECREDUCE_UMIN: {
1910 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1912 report(
"Vector reduction requires a scalar destination type",
MI);
1916 case TargetOpcode::G_SBFX:
1917 case TargetOpcode::G_UBFX: {
1918 LLT DstTy =
MRI->getType(
MI->getOperand(0).getReg());
1920 report(
"Bitfield extraction is not supported on vectors",
MI);
1925 case TargetOpcode::G_SHL:
1926 case TargetOpcode::G_LSHR:
1927 case TargetOpcode::G_ASHR:
1928 case TargetOpcode::G_ROTR:
1929 case TargetOpcode::G_ROTL: {
1930 LLT Src1Ty =
MRI->getType(
MI->getOperand(1).getReg());
1931 LLT Src2Ty =
MRI->getType(
MI->getOperand(2).getReg());
1933 report(
"Shifts and rotates require operands to be either all scalars or "
1940 case TargetOpcode::G_LLROUND:
1941 case TargetOpcode::G_LROUND: {
1942 verifyAllRegOpsScalar(*
MI, *
MRI);
1945 case TargetOpcode::G_IS_FPCLASS: {
1946 LLT DestTy =
MRI->getType(
MI->getOperand(0).getReg());
1949 report(
"Destination must be a scalar or vector of scalars",
MI);
1952 LLT SrcTy =
MRI->getType(
MI->getOperand(1).getReg());
1955 report(
"Source must be a scalar or vector of scalars",
MI);
1958 if (!verifyVectorElementMatch(DestTy, SrcTy,
MI))
1961 if (!TestMO.
isImm()) {
1962 report(
"floating-point class set (operand 2) must be an immediate",
MI);
1967 report(
"Incorrect floating-point class set (operand 2)",
MI);
1972 case TargetOpcode::G_PREFETCH: {
1974 if (!AddrOp.
isReg() || !
MRI->getType(AddrOp.
getReg()).isPointer()) {
1975 report(
"addr operand must be a pointer", &AddrOp, 0);
1980 report(
"rw operand must be an immediate 0-1", &RWOp, 1);
1985 report(
"locality operand must be an immediate 0-3", &LocalityOp, 2);
1990 report(
"cache type operand must be an immediate 0-1", &CacheTypeOp, 3);
1995 case TargetOpcode::G_ASSERT_ALIGN: {
1996 if (
MI->getOperand(2).getImm() < 1)
1997 report(
"alignment immediate must be >= 1",
MI);
2000 case TargetOpcode::G_CONSTANT_POOL: {
2001 if (!
MI->getOperand(1).isCPI())
2002 report(
"Src operand 1 must be a constant pool index",
MI);
2003 if (!
MRI->getType(
MI->getOperand(0).getReg()).isPointer())
2004 report(
"Dst operand 0 must be a pointer",
MI);
2012void MachineVerifier::visitMachineInstrBefore(
const MachineInstr *
MI) {
2015 report(
"Too few operands",
MI);
2017 <<
MI->getNumOperands() <<
" given.\n";
2021 report(
"NoConvergent flag expected only on convergent instructions.",
MI);
2024 if (MF->getProperties().hasProperty(
2026 report(
"Found PHI instruction with NoPHIs property set",
MI);
2029 report(
"Found PHI instruction after non-PHI",
MI);
2030 }
else if (FirstNonPHI ==
nullptr)
2034 if (
MI->isInlineAsm())
2035 verifyInlineAsm(
MI);
2038 if (
TII->isUnspillableTerminator(
MI)) {
2039 if (!
MI->getOperand(0).isReg() || !
MI->getOperand(0).isDef())
2040 report(
"Unspillable Terminator does not define a reg",
MI);
2042 if (
Def.isVirtual() &&
2043 !MF->getProperties().hasProperty(
2045 std::distance(
MRI->use_nodbg_begin(Def),
MRI->use_nodbg_end()) > 1)
2046 report(
"Unspillable Terminator expected to have at most one use!",
MI);
2052 if (
MI->isDebugValue() &&
MI->getNumOperands() == 4)
2053 if (!
MI->getDebugLoc())
2054 report(
"Missing DebugLoc for debug instruction",
MI);
2058 if (
MI->isMetaInstruction() &&
MI->peekDebugInstrNum())
2059 report(
"Metadata instruction should not have a value tracking number",
MI);
2063 if (
Op->isLoad() && !
MI->mayLoad())
2064 report(
"Missing mayLoad flag",
MI);
2065 if (
Op->isStore() && !
MI->mayStore())
2066 report(
"Missing mayStore flag",
MI);
2073 if (
MI->isDebugOrPseudoInstr()) {
2075 report(
"Debug instruction has a slot index",
MI);
2076 }
else if (
MI->isInsideBundle()) {
2078 report(
"Instruction inside bundle has a slot index",
MI);
2081 report(
"Missing slot index",
MI);
2087 verifyPreISelGenericInstruction(
MI);
2096 switch (
MI->getOpcode()) {
2097 case TargetOpcode::COPY: {
2103 LLT DstTy =
MRI->getType(DstReg);
2104 LLT SrcTy =
MRI->getType(SrcReg);
2107 if (SrcTy != DstTy) {
2108 report(
"Copy Instruction is illegal with mismatching types",
MI);
2109 errs() <<
"Def = " << DstTy <<
", Src = " << SrcTy <<
"\n";
2124 TRI->getMinimalPhysRegClassLLT(SrcReg, DstTy);
2126 SrcSize =
TRI->getRegSizeInBits(*SrcRC);
2131 TRI->getMinimalPhysRegClassLLT(DstReg, SrcTy);
2133 DstSize =
TRI->getRegSizeInBits(*DstRC);
2151 if (!
DstOp.getSubReg() && !
SrcOp.getSubReg()) {
2152 report(
"Copy Instruction is illegal with mismatching sizes",
MI);
2153 errs() <<
"Def Size = " << DstSize <<
", Src Size = " << SrcSize
2159 case TargetOpcode::STATEPOINT: {
2161 if (!
MI->getOperand(SO.getIDPos()).isImm() ||
2162 !
MI->getOperand(SO.getNBytesPos()).isImm() ||
2163 !
MI->getOperand(SO.getNCallArgsPos()).isImm()) {
2164 report(
"meta operands to STATEPOINT not constant!",
MI);
2168 auto VerifyStackMapConstant = [&](
unsigned Offset) {
2169 if (
Offset >=
MI->getNumOperands()) {
2170 report(
"stack map constant to STATEPOINT is out of range!",
MI);
2173 if (!
MI->getOperand(
Offset - 1).isImm() ||
2174 MI->getOperand(
Offset - 1).getImm() != StackMaps::ConstantOp ||
2176 report(
"stack map constant to STATEPOINT not well formed!",
MI);
2178 VerifyStackMapConstant(SO.getCCIdx());
2179 VerifyStackMapConstant(SO.getFlagsIdx());
2180 VerifyStackMapConstant(SO.getNumDeoptArgsIdx());
2181 VerifyStackMapConstant(SO.getNumGCPtrIdx());
2182 VerifyStackMapConstant(SO.getNumAllocaIdx());
2183 VerifyStackMapConstant(SO.getNumGcMapEntriesIdx());
2187 unsigned FirstGCPtrIdx = SO.getFirstGCPtrIdx();
2188 unsigned LastGCPtrIdx = SO.getNumAllocaIdx() - 2;
2189 for (
unsigned Idx = 0;
Idx <
MI->getNumDefs();
Idx++) {
2191 if (!
MI->isRegTiedToUseOperand(
Idx, &UseOpIdx)) {
2192 report(
"STATEPOINT defs expected to be tied",
MI);
2195 if (UseOpIdx < FirstGCPtrIdx || UseOpIdx > LastGCPtrIdx) {
2196 report(
"STATEPOINT def tied to non-gc operand",
MI);
2203 case TargetOpcode::INSERT_SUBREG: {
2204 unsigned InsertedSize;
2205 if (
unsigned SubIdx =
MI->getOperand(2).getSubReg())
2206 InsertedSize =
TRI->getSubRegIdxSize(SubIdx);
2208 InsertedSize =
TRI->getRegSizeInBits(
MI->getOperand(2).getReg(), *
MRI);
2209 unsigned SubRegSize =
TRI->getSubRegIdxSize(
MI->getOperand(3).getImm());
2210 if (SubRegSize < InsertedSize) {
2211 report(
"INSERT_SUBREG expected inserted value to have equal or lesser "
2212 "size than the subreg it was inserted into",
MI);
2216 case TargetOpcode::REG_SEQUENCE: {
2217 unsigned NumOps =
MI->getNumOperands();
2218 if (!(NumOps & 1)) {
2219 report(
"Invalid number of operands for REG_SEQUENCE",
MI);
2223 for (
unsigned I = 1;
I != NumOps;
I += 2) {
2228 report(
"Invalid register operand for REG_SEQUENCE", &RegOp,
I);
2230 if (!SubRegOp.
isImm() || SubRegOp.
getImm() == 0 ||
2231 SubRegOp.
getImm() >=
TRI->getNumSubRegIndices()) {
2232 report(
"Invalid subregister index operand for REG_SEQUENCE",
2237 Register DstReg =
MI->getOperand(0).getReg();
2239 report(
"REG_SEQUENCE does not support physical register results",
MI);
2241 if (
MI->getOperand(0).getSubReg())
2242 report(
"Invalid subreg result for REG_SEQUENCE",
MI);
2250MachineVerifier::visitMachineOperand(
const MachineOperand *MO,
unsigned MONum) {
2254 if (MCID.
getOpcode() == TargetOpcode::PATCHPOINT)
2255 NumDefs = (MONum == 0 && MO->
isReg()) ? NumDefs : 0;
2258 if (MONum < NumDefs) {
2261 report(
"Explicit definition must be a register", MO, MONum);
2263 report(
"Explicit definition marked as use", MO, MONum);
2265 report(
"Explicit definition marked as implicit", MO, MONum);
2274 report(
"Explicit operand marked as def", MO, MONum);
2276 report(
"Explicit operand marked as implicit", MO, MONum);
2282 report(
"Expected a register operand.", MO, MONum);
2286 !
TII->isPCRelRegisterOperandLegal(*MO)))
2287 report(
"Expected a non-register operand.", MO, MONum);
2294 report(
"Tied use must be a register", MO, MONum);
2296 report(
"Operand should be tied", MO, MONum);
2297 else if (
unsigned(TiedTo) !=
MI->findTiedOperandIdx(MONum))
2298 report(
"Tied def doesn't match MCInstrDesc", MO, MONum);
2301 if (!MOTied.
isReg())
2302 report(
"Tied counterpart must be a register", &MOTied, TiedTo);
2305 report(
"Tied physical registers must match.", &MOTied, TiedTo);
2308 report(
"Explicit operand should not be tied", MO, MONum);
2309 }
else if (!
MI->isVariadic()) {
2312 report(
"Extra explicit operand on non-variadic instruction", MO, MONum);
2319 if (
MI->isDebugInstr() && MO->
isUse()) {
2321 report(
"Register operand must be marked debug", MO, MONum);
2323 report(
"Register operand must not be marked debug", MO, MONum);
2329 if (
MRI->tracksLiveness() && !
MI->isDebugInstr())
2330 checkLiveness(MO, MONum);
2334 report(
"Undef virtual register def operands require a subregister", MO, MONum);
2338 unsigned OtherIdx =
MI->findTiedOperandIdx(MONum);
2340 if (!OtherMO.
isReg())
2341 report(
"Must be tied to a register", MO, MONum);
2343 report(
"Missing tie flags on tied operand", MO, MONum);
2344 if (
MI->findTiedOperandIdx(OtherIdx) != MONum)
2345 report(
"Inconsistent tie links", MO, MONum);
2349 report(
"Explicit def tied to explicit use without tie constraint",
2353 report(
"Explicit def should be tied to implicit use", MO, MONum);
2366 if (MF->getProperties().hasProperty(
2368 MO->
isUse() &&
MI->isRegTiedToDefOperand(MONum, &DefIdx) &&
2369 Reg !=
MI->getOperand(DefIdx).getReg())
2370 report(
"Two-address instruction operands must be identical", MO, MONum);
2375 if (
Reg.isPhysical()) {
2377 report(
"Illegal subregister index for physical register", MO, MONum);
2382 TII->getRegClass(MCID, MONum,
TRI, *MF)) {
2383 if (!DRC->contains(Reg)) {
2384 report(
"Illegal physical register for instruction", MO, MONum);
2386 <<
TRI->getRegClassName(DRC) <<
" register.\n";
2391 if (
MRI->isReserved(Reg)) {
2392 report(
"isRenamable set on reserved register", MO, MONum);
2409 report(
"Generic virtual register use cannot be undef", MO, MONum);
2416 if (isFunctionTracksDebugUserValues || !MO->
isUse() ||
2417 !
MI->isDebugValue() || !
MRI->def_empty(Reg)) {
2419 if (isFunctionSelected) {
2420 report(
"Generic virtual register invalid in a Selected function",
2426 LLT Ty =
MRI->getType(Reg);
2428 report(
"Generic virtual register must have a valid type", MO,
2437 if (!RegBank && isFunctionRegBankSelected) {
2438 report(
"Generic virtual register must have a bank in a "
2439 "RegBankSelected function",
2447 report(
"Register bank is too small for virtual register", MO,
2449 errs() <<
"Register bank " << RegBank->
getName() <<
" too small("
2457 report(
"Generic virtual register does not allow subregister index", MO,
2467 TII->getRegClass(MCID, MONum,
TRI, *MF)) {
2468 report(
"Virtual register does not match instruction constraint", MO,
2470 errs() <<
"Expect register class "
2471 <<
TRI->getRegClassName(
2472 TII->getRegClass(MCID, MONum,
TRI, *MF))
2473 <<
" but got nothing\n";
2481 TRI->getSubClassWithSubReg(RC, SubIdx);
2483 report(
"Invalid subregister index for virtual register", MO, MONum);
2484 errs() <<
"Register class " <<
TRI->getRegClassName(RC)
2485 <<
" does not support subreg index " << SubIdx <<
"\n";
2489 report(
"Invalid register class for subregister index", MO, MONum);
2490 errs() <<
"Register class " <<
TRI->getRegClassName(RC)
2491 <<
" does not fully support subreg index " << SubIdx <<
"\n";
2497 TII->getRegClass(MCID, MONum,
TRI, *MF)) {
2500 TRI->getLargestLegalSuperClass(RC, *MF);
2502 report(
"No largest legal super class exists.", MO, MONum);
2505 DRC =
TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx);
2507 report(
"No matching super-reg register class.", MO, MONum);
2512 report(
"Illegal virtual register for instruction", MO, MONum);
2513 errs() <<
"Expected a " <<
TRI->getRegClassName(DRC)
2514 <<
" register, but got a " <<
TRI->getRegClassName(RC)
2529 report(
"PHI operand is not in the CFG", MO, MONum);
2540 bool loads =
MI->mayLoad();
2545 for (
auto *MMO :
MI->memoperands()) {
2547 if (PSV ==
nullptr)
continue;
2549 dyn_cast<FixedStackPseudoSourceValue>(PSV);
2550 if (
Value ==
nullptr)
continue;
2551 if (
Value->getFrameIndex() != FI)
continue;
2560 report(
"Missing fixed stack memoperand.",
MI);
2562 if (loads && !LI.
liveAt(
Idx.getRegSlot(
true))) {
2563 report(
"Instruction loads from dead spill slot", MO, MONum);
2564 errs() <<
"Live stack: " << LI <<
'\n';
2567 report(
"Instruction stores to dead spill slot", MO, MONum);
2568 errs() <<
"Live stack: " << LI <<
'\n';
2574 if (MO->
getCFIIndex() >= MF->getFrameInstructions().size())
2575 report(
"CFI instruction has invalid index", MO, MONum);
2583void MachineVerifier::checkLivenessAtUse(
const MachineOperand *MO,
2594 report(
"No live segment at use", MO, MONum);
2595 report_context_liverange(LR);
2596 report_context_vreg_regunit(VRegOrUnit);
2597 report_context(UseIdx);
2600 report(
"Live range continues after kill flag", MO, MONum);
2601 report_context_liverange(LR);
2602 report_context_vreg_regunit(VRegOrUnit);
2604 report_context_lanemask(LaneMask);
2605 report_context(UseIdx);
2609void MachineVerifier::checkLivenessAtDef(
const MachineOperand *MO,
2624 if (((SubRangeCheck || MO->
getSubReg() == 0) && VNI->def != DefIdx) ||
2626 (VNI->def != DefIdx &&
2627 (!VNI->def.isEarlyClobber() || !DefIdx.
isRegister()))) {
2628 report(
"Inconsistent valno->def", MO, MONum);
2629 report_context_liverange(LR);
2630 report_context_vreg_regunit(VRegOrUnit);
2632 report_context_lanemask(LaneMask);
2633 report_context(*VNI);
2634 report_context(DefIdx);
2637 report(
"No live segment at def", MO, MONum);
2638 report_context_liverange(LR);
2639 report_context_vreg_regunit(VRegOrUnit);
2641 report_context_lanemask(LaneMask);
2642 report_context(DefIdx);
2654 if (SubRangeCheck || MO->
getSubReg() == 0) {
2655 report(
"Live range continues after dead def flag", MO, MONum);
2656 report_context_liverange(LR);
2657 report_context_vreg_regunit(VRegOrUnit);
2659 report_context_lanemask(LaneMask);
2665void MachineVerifier::checkLiveness(
const MachineOperand *MO,
unsigned MONum) {
2668 const unsigned SubRegIdx = MO->
getSubReg();
2671 if (LiveInts &&
Reg.isVirtual()) {
2676 report(
"Live interval for subreg operand has no subranges", MO, MONum);
2678 report(
"Virtual register has no live interval", MO, MONum);
2685 addRegWithSubRegs(regsKilled, Reg);
2690 if (LiveVars &&
Reg.isVirtual() && MO->
isKill() &&
2691 !
MI->isBundledWithPred()) {
2694 report(
"Kill missing from LiveVariables", MO, MONum);
2708 if (
Reg.isPhysical() && !isReserved(Reg)) {
2710 if (
MRI->isReservedRegUnit(Unit))
2713 checkLivenessAtUse(MO, MONum, UseIdx, *LR, Unit);
2717 if (
Reg.isVirtual()) {
2719 checkLivenessAtUse(MO, MONum, UseIdx, *LI, Reg);
2723 ?
TRI->getSubRegIndexLaneMask(SubRegIdx)
2724 :
MRI->getMaxLaneMaskForVReg(Reg);
2727 if ((MOMask & SR.LaneMask).none())
2729 checkLivenessAtUse(MO, MONum, UseIdx, SR, Reg, SR.LaneMask);
2732 LiveInMask |= SR.LaneMask;
2735 if ((LiveInMask & MOMask).
none()) {
2736 report(
"No live subrange at use", MO, MONum);
2737 report_context(*LI);
2738 report_context(UseIdx);
2741 if (
MI->isPHI() && LiveInMask != MOMask) {
2742 report(
"Not all lanes of PHI source live at use", MO, MONum);
2743 report_context(*LI);
2744 report_context(UseIdx);
2751 if (!regsLive.count(Reg)) {
2752 if (
Reg.isPhysical()) {
2754 bool Bad = !isReserved(Reg);
2759 if (regsLive.count(
SubReg)) {
2771 if (!MOP.isReg() || !MOP.isImplicit())
2774 if (!MOP.getReg().isPhysical())
2782 report(
"Using an undefined physical register", MO, MONum);
2783 }
else if (
MRI->def_empty(Reg)) {
2784 report(
"Reading virtual register without a def", MO, MONum);
2786 BBInfo &MInfo = MBBInfoMap[
MI->getParent()];
2790 if (MInfo.regsKilled.count(Reg))
2791 report(
"Using a killed virtual register", MO, MONum);
2792 else if (!
MI->isPHI())
2793 MInfo.vregsLiveIn.insert(std::make_pair(Reg,
MI));
2802 addRegWithSubRegs(regsDead, Reg);
2804 addRegWithSubRegs(regsDefined, Reg);
2807 if (
MRI->isSSA() &&
Reg.isVirtual() &&
2808 std::next(
MRI->def_begin(Reg)) !=
MRI->def_end())
2809 report(
"Multiple virtual register defs in SSA form", MO, MONum);
2816 if (
Reg.isVirtual()) {
2817 checkLivenessAtDef(MO, MONum, DefIdx, *LI, Reg);
2821 ?
TRI->getSubRegIndexLaneMask(SubRegIdx)
2822 :
MRI->getMaxLaneMaskForVReg(Reg);
2824 if ((SR.LaneMask & MOMask).none())
2826 checkLivenessAtDef(MO, MONum, DefIdx, SR, Reg,
true, SR.LaneMask);
2838void MachineVerifier::visitMachineBundleAfter(
const MachineInstr *
MI) {
2839 BBInfo &MInfo = MBBInfoMap[
MI->getParent()];
2840 set_union(MInfo.regsKilled, regsKilled);
2841 set_subtract(regsLive, regsKilled); regsKilled.clear();
2843 while (!regMasks.empty()) {
2846 if (
Reg.isPhysical() &&
2848 regsDead.push_back(Reg);
2851 set_union(regsLive, regsDefined); regsDefined.clear();
2856 MBBInfoMap[
MBB].regsLiveOut = regsLive;
2861 if (!(stop > lastIndex)) {
2862 report(
"Block ends before last instruction index",
MBB);
2863 errs() <<
"Block ends at " << stop
2864 <<
" last instruction was at " << lastIndex <<
'\n';
2879 template <
typename RegSetT>
void add(
const RegSetT &FromRegSet) {
2881 filterAndAdd(FromRegSet, VRegsBuffer);
2886 template <
typename RegSetT>
2887 bool filterAndAdd(
const RegSetT &FromRegSet,
2889 unsigned SparseUniverse = Sparse.size();
2890 unsigned NewSparseUniverse = SparseUniverse;
2891 unsigned NewDenseSize =
Dense.size();
2892 size_t Begin = ToVRegs.
size();
2894 if (!
Reg.isVirtual())
2897 if (
Index < SparseUniverseMax) {
2898 if (
Index < SparseUniverse && Sparse.test(
Index))
2900 NewSparseUniverse = std::max(NewSparseUniverse,
Index + 1);
2915 Sparse.resize(NewSparseUniverse);
2916 Dense.reserve(NewDenseSize);
2917 for (
unsigned I = Begin;
I <
End; ++
I) {
2920 if (
Index < SparseUniverseMax)
2929 static constexpr unsigned SparseUniverseMax = 10 * 1024 * 8;
2949class FilteringVRegSet {
2956 template <
typename RegSetT>
void addToFilter(
const RegSetT &RS) {
2961 template <
typename RegSetT>
bool add(
const RegSetT &RS) {
2964 return Filter.filterAndAdd(RS, VRegs);
2969 size_t size()
const {
return VRegs.
size(); }
2976void MachineVerifier::calcRegsPassed() {
2983 FilteringVRegSet VRegs;
2984 BBInfo &
Info = MBBInfoMap[MB];
2987 VRegs.addToFilter(
Info.regsKilled);
2988 VRegs.addToFilter(
Info.regsLiveOut);
2990 const BBInfo &PredInfo = MBBInfoMap[Pred];
2991 if (!PredInfo.reachable)
2994 VRegs.add(PredInfo.regsLiveOut);
2995 VRegs.add(PredInfo.vregsPassed);
2997 Info.vregsPassed.reserve(VRegs.size());
2998 Info.vregsPassed.insert(VRegs.begin(), VRegs.end());
3005void MachineVerifier::calcRegsRequired() {
3008 for (
const auto &
MBB : *MF) {
3009 BBInfo &MInfo = MBBInfoMap[&
MBB];
3011 BBInfo &PInfo = MBBInfoMap[Pred];
3012 if (PInfo.addRequired(MInfo.vregsLiveIn))
3018 for (
unsigned i = 1, e =
MI.getNumOperands(); i != e; i += 2) {
3020 if (!
MI.getOperand(i).isReg() || !
MI.getOperand(i).readsReg())
3027 BBInfo &PInfo = MBBInfoMap[Pred];
3028 if (PInfo.addRequired(Reg))
3036 while (!todo.
empty()) {
3039 BBInfo &MInfo = MBBInfoMap[
MBB];
3043 BBInfo &SInfo = MBBInfoMap[Pred];
3044 if (SInfo.addRequired(MInfo.vregsRequired))
3053 BBInfo &MInfo = MBBInfoMap[&
MBB];
3063 report(
"Expected first PHI operand to be a register def", &MODef, 0);
3068 report(
"Unexpected flag on PHI operand", &MODef, 0);
3071 report(
"Expected first PHI operand to be a virtual register", &MODef, 0);
3073 for (
unsigned I = 1, E =
Phi.getNumOperands();
I != E;
I += 2) {
3076 report(
"Expected PHI operand to be a register", &MO0,
I);
3081 report(
"Unexpected flag on PHI operand", &MO0,
I);
3085 report(
"Expected PHI operand to be a basic block", &MO1,
I + 1);
3091 report(
"PHI input is not a predecessor block", &MO1,
I + 1);
3095 if (MInfo.reachable) {
3097 BBInfo &PrInfo = MBBInfoMap[&Pre];
3098 if (!MO0.
isUndef() && PrInfo.reachable &&
3099 !PrInfo.isLiveOut(MO0.
getReg()))
3100 report(
"PHI operand is not live-out from predecessor", &MO0,
I);
3105 if (MInfo.reachable) {
3107 if (!seen.
count(Pred)) {
3108 report(
"Missing PHI operand", &Phi);
3110 <<
" is a predecessor according to the CFG.\n";
3119 std::function<
void(
const Twine &Message)> FailureCB) {
3123 for (
const auto &
MBB : MF) {
3135void MachineVerifier::visitMachineFunctionAfter() {
3136 auto FailureCB = [
this](
const Twine &Message) {
3137 report(Message.str().c_str(), MF);
3150 for (
const auto &
MBB : *MF) {
3151 BBInfo &MInfo = MBBInfoMap[&
MBB];
3152 for (
Register VReg : MInfo.vregsRequired)
3153 if (MInfo.regsKilled.count(VReg)) {
3154 report(
"Virtual register killed in block, but needed live out.", &
MBB);
3156 <<
" is used after the block.\n";
3161 BBInfo &MInfo = MBBInfoMap[&MF->front()];
3162 for (
Register VReg : MInfo.vregsRequired) {
3163 report(
"Virtual register defs don't dominate all uses.", MF);
3164 report_context_vreg(VReg);
3169 verifyLiveVariables();
3171 verifyLiveIntervals();
3180 if (
MRI->tracksLiveness())
3181 for (
const auto &
MBB : *MF)
3185 if (hasAliases || isAllocatable(LiveInReg) || isReserved(LiveInReg))
3188 BBInfo &PInfo = MBBInfoMap[Pred];
3189 if (!PInfo.regsLiveOut.count(LiveInReg)) {
3190 report(
"Live in register not found to be live out from predecessor.",
3192 errs() <<
TRI->getName(LiveInReg)
3193 <<
" not found to be live out from "
3199 for (
auto CSInfo : MF->getCallSitesInfo())
3200 if (!CSInfo.first->isCall())
3201 report(
"Call site info referencing instruction that is not call", MF);
3205 if (MF->getFunction().getSubprogram()) {
3207 for (
const auto &
MBB : *MF) {
3208 for (
const auto &
MI :
MBB) {
3209 if (
auto Num =
MI.peekDebugInstrNum()) {
3212 report(
"Instruction has a duplicated value tracking number", &
MI);
3219void MachineVerifier::verifyLiveVariables() {
3220 assert(LiveVars &&
"Don't call verifyLiveVariables without LiveVars");
3221 for (
unsigned I = 0, E =
MRI->getNumVirtRegs();
I != E; ++
I) {
3224 for (
const auto &
MBB : *MF) {
3225 BBInfo &MInfo = MBBInfoMap[&
MBB];
3228 if (MInfo.vregsRequired.count(Reg)) {
3230 report(
"LiveVariables: Block missing from AliveBlocks", &
MBB);
3232 <<
" must be live through the block.\n";
3236 report(
"LiveVariables: Block should not be in AliveBlocks", &
MBB);
3238 <<
" is not needed live through the block.\n";
3245void MachineVerifier::verifyLiveIntervals() {
3246 assert(LiveInts &&
"Don't call verifyLiveIntervals without LiveInts");
3247 for (
unsigned I = 0, E =
MRI->getNumVirtRegs();
I != E; ++
I) {
3251 if (
MRI->reg_nodbg_empty(Reg))
3255 report(
"Missing live interval for virtual register", MF);
3261 assert(Reg == LI.
reg() &&
"Invalid reg to interval mapping");
3262 verifyLiveInterval(LI);
3266 for (
unsigned i = 0, e =
TRI->getNumRegUnits(); i != e; ++i)
3268 verifyLiveRange(*LR, i);
3271void MachineVerifier::verifyLiveRangeValue(
const LiveRange &LR,
3280 report(
"Value not live at VNInfo def and not marked unused", MF);
3281 report_context(LR, Reg, LaneMask);
3282 report_context(*VNI);
3286 if (DefVNI != VNI) {
3287 report(
"Live segment at def has different VNInfo", MF);
3288 report_context(LR, Reg, LaneMask);
3289 report_context(*VNI);
3295 report(
"Invalid VNInfo definition index", MF);
3296 report_context(LR, Reg, LaneMask);
3297 report_context(*VNI);
3303 report(
"PHIDef VNInfo is not defined at MBB start",
MBB);
3304 report_context(LR, Reg, LaneMask);
3305 report_context(*VNI);
3313 report(
"No instruction at VNInfo def index",
MBB);
3314 report_context(LR, Reg, LaneMask);
3315 report_context(*VNI);
3320 bool hasDef =
false;
3321 bool isEarlyClobber =
false;
3323 if (!MOI->isReg() || !MOI->isDef())
3325 if (
Reg.isVirtual()) {
3326 if (MOI->getReg() != Reg)
3329 if (!MOI->getReg().isPhysical() || !
TRI->hasRegUnit(MOI->getReg(), Reg))
3332 if (LaneMask.
any() &&
3333 (
TRI->getSubRegIndexLaneMask(MOI->getSubReg()) & LaneMask).none())
3336 if (MOI->isEarlyClobber())
3337 isEarlyClobber =
true;
3341 report(
"Defining instruction does not modify register",
MI);
3342 report_context(LR, Reg, LaneMask);
3343 report_context(*VNI);
3348 if (isEarlyClobber) {
3350 report(
"Early clobber def must be at an early-clobber slot",
MBB);
3351 report_context(LR, Reg, LaneMask);
3352 report_context(*VNI);
3355 report(
"Non-PHI, non-early clobber def must be at a register slot",
MBB);
3356 report_context(LR, Reg, LaneMask);
3357 report_context(*VNI);
3362void MachineVerifier::verifyLiveRangeSegment(
const LiveRange &LR,
3368 assert(VNI &&
"Live segment has no valno");
3371 report(
"Foreign valno in live segment", MF);
3372 report_context(LR, Reg, LaneMask);
3374 report_context(*VNI);
3378 report(
"Live segment valno is marked unused", MF);
3379 report_context(LR, Reg, LaneMask);
3385 report(
"Bad start of live segment, no basic block", MF);
3386 report_context(LR, Reg, LaneMask);
3392 report(
"Live segment must begin at MBB entry or valno def",
MBB);
3393 report_context(LR, Reg, LaneMask);
3400 report(
"Bad end of live segment, no basic block", MF);
3401 report_context(LR, Reg, LaneMask);
3417 report(
"Live segment doesn't end at a valid instruction", EndMBB);
3418 report_context(LR, Reg, LaneMask);
3425 report(
"Live segment ends at B slot of an instruction", EndMBB);
3426 report_context(LR, Reg, LaneMask);
3434 report(
"Live segment ending at dead slot spans instructions", EndMBB);
3435 report_context(LR, Reg, LaneMask);
3444 if (MF->getProperties().hasProperty(
3447 if (
I + 1 == LR.
end() || (
I + 1)->start != S.
end) {
3448 report(
"Live segment ending at early clobber slot must be "
3449 "redefined by an EC def in the same instruction",
3451 report_context(LR, Reg, LaneMask);
3458 if (
Reg.isVirtual()) {
3461 bool hasRead =
false;
3462 bool hasSubRegDef =
false;
3463 bool hasDeadDef =
false;
3465 if (!MOI->isReg() || MOI->getReg() != Reg)
3467 unsigned Sub = MOI->getSubReg();
3472 hasSubRegDef =
true;
3481 if (LaneMask.
any() && (LaneMask & SLM).none())
3483 if (MOI->readsReg())
3490 if (LaneMask.
none() && !hasDeadDef) {
3492 "Instruction ending live segment on dead slot has no dead flag",
3494 report_context(LR, Reg, LaneMask);
3501 if (!
MRI->shouldTrackSubRegLiveness(Reg) || LaneMask.
any() ||
3503 report(
"Instruction ending live segment doesn't read the register",
3505 report_context(LR, Reg, LaneMask);
3525 if (LaneMask.
any()) {
3533 if (!
Reg.isVirtual() && MFI->isEHPad()) {
3534 if (&*MFI == EndMBB)
3548 if (MFI->isEHPad()) {
3562 if (!PVNI && (LaneMask.
none() || !IsPHI)) {
3565 report(
"Register not marked live out of predecessor", Pred);
3566 report_context(LR, Reg, LaneMask);
3567 report_context(*VNI);
3575 if (!IsPHI && PVNI != VNI) {
3576 report(
"Different value live out of predecessor", Pred);
3577 report_context(LR, Reg, LaneMask);
3578 errs() <<
"Valno #" << PVNI->
id <<
" live out of "
3584 if (&*MFI == EndMBB)
3593 verifyLiveRangeValue(LR, VNI, Reg, LaneMask);
3596 verifyLiveRangeSegment(LR,
I, Reg, LaneMask);
3599void MachineVerifier::verifyLiveInterval(
const LiveInterval &LI) {
3602 verifyLiveRange(LI, Reg);
3608 if ((Mask & SR.LaneMask).any()) {
3609 report(
"Lane masks of sub ranges overlap in live interval", MF);
3612 if ((SR.LaneMask & ~MaxMask).any()) {
3613 report(
"Subrange lanemask is invalid", MF);
3617 report(
"Subrange must not be empty", MF);
3618 report_context(SR, LI.
reg(), SR.LaneMask);
3620 Mask |= SR.LaneMask;
3621 verifyLiveRange(SR, LI.
reg(), SR.LaneMask);
3623 report(
"A Subrange is not covered by the main range", MF);
3631 unsigned NumComp = ConEQ.Classify(LI);
3633 report(
"Multiple connected components in live interval", MF);
3635 for (
unsigned comp = 0; comp != NumComp; ++comp) {
3636 errs() << comp <<
": valnos";
3638 if (comp == ConEQ.getEqClass(
I))
3639 errs() <<
' ' <<
I->id;
3651 struct StackStateOfBB {
3652 StackStateOfBB() =
default;
3653 StackStateOfBB(
int EntryVal,
int ExitVal,
bool EntrySetup,
bool ExitSetup) :
3654 EntryValue(EntryVal), ExitValue(ExitVal), EntryIsSetup(EntrySetup),
3655 ExitIsSetup(ExitSetup) {}
3660 bool EntryIsSetup =
false;
3661 bool ExitIsSetup =
false;
3669void MachineVerifier::verifyStackFrame() {
3670 unsigned FrameSetupOpcode =
TII->getCallFrameSetupOpcode();
3671 unsigned FrameDestroyOpcode =
TII->getCallFrameDestroyOpcode();
3672 if (FrameSetupOpcode == ~0u && FrameDestroyOpcode == ~0u)
3676 SPState.
resize(MF->getNumBlockIDs());
3683 DFI != DFE; ++DFI) {
3686 StackStateOfBB BBState;
3688 if (DFI.getPathLength() >= 2) {
3691 "DFS stack predecessor is already visited.\n");
3692 BBState.EntryValue = SPState[StackPred->
getNumber()].ExitValue;
3693 BBState.EntryIsSetup = SPState[StackPred->
getNumber()].ExitIsSetup;
3694 BBState.ExitValue = BBState.EntryValue;
3695 BBState.ExitIsSetup = BBState.EntryIsSetup;
3699 report(
"Call frame size on entry does not match value computed from "
3703 <<
" does not match value computed from predecessor "
3704 << -BBState.EntryValue <<
'\n';
3708 for (
const auto &
I : *
MBB) {
3709 if (
I.getOpcode() == FrameSetupOpcode) {
3710 if (BBState.ExitIsSetup)
3711 report(
"FrameSetup is after another FrameSetup", &
I);
3712 if (!
MRI->isSSA() && !MF->getFrameInfo().adjustsStack())
3713 report(
"AdjustsStack not set in presence of a frame pseudo "
3714 "instruction.", &
I);
3715 BBState.ExitValue -=
TII->getFrameTotalSize(
I);
3716 BBState.ExitIsSetup =
true;
3719 if (
I.getOpcode() == FrameDestroyOpcode) {
3720 int Size =
TII->getFrameTotalSize(
I);
3721 if (!BBState.ExitIsSetup)
3722 report(
"FrameDestroy is not after a FrameSetup", &
I);
3723 int AbsSPAdj = BBState.ExitValue < 0 ? -BBState.ExitValue :
3725 if (BBState.ExitIsSetup && AbsSPAdj !=
Size) {
3726 report(
"FrameDestroy <n> is after FrameSetup <m>", &
I);
3727 errs() <<
"FrameDestroy <" <<
Size <<
"> is after FrameSetup <"
3728 << AbsSPAdj <<
">.\n";
3730 if (!
MRI->isSSA() && !MF->getFrameInfo().adjustsStack())
3731 report(
"AdjustsStack not set in presence of a frame pseudo "
3732 "instruction.", &
I);
3733 BBState.ExitValue +=
Size;
3734 BBState.ExitIsSetup =
false;
3742 if (Reachable.
count(Pred) &&
3743 (SPState[Pred->
getNumber()].ExitValue != BBState.EntryValue ||
3744 SPState[Pred->
getNumber()].ExitIsSetup != BBState.EntryIsSetup)) {
3745 report(
"The exit stack state of a predecessor is inconsistent.",
MBB);
3747 <<
" has exit state (" << SPState[Pred->
getNumber()].ExitValue
3748 <<
", " << SPState[Pred->
getNumber()].ExitIsSetup <<
"), while "
3750 << BBState.EntryValue <<
", " << BBState.EntryIsSetup <<
").\n";
3757 if (Reachable.
count(Succ) &&
3758 (SPState[Succ->getNumber()].EntryValue != BBState.ExitValue ||
3759 SPState[Succ->getNumber()].EntryIsSetup != BBState.ExitIsSetup)) {
3760 report(
"The entry stack state of a successor is inconsistent.",
MBB);
3762 <<
" has entry state (" << SPState[Succ->getNumber()].EntryValue
3763 <<
", " << SPState[Succ->getNumber()].EntryIsSetup <<
"), while "
3765 << BBState.ExitValue <<
", " << BBState.ExitIsSetup <<
").\n";
3771 if (BBState.ExitIsSetup)
3772 report(
"A return block ends with a FrameSetup.",
MBB);
3773 if (BBState.ExitValue)
3774 report(
"A return block ends with a nonzero stack adjustment.",
MBB);
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
static bool isLoad(int Opcode)
static bool isStore(int Opcode)
This file implements the BitVector class.
Analysis containing CSE Info
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
This file defines the DenseMap class.
This file defines the DenseSet and SmallDenseSet classes.
This file builds on the ADT/GraphTraits.h file to build generic depth first graph iterator.
Declares convenience wrapper classes for interpreting MachineInstr instances as specific generic oper...
const HexagonInstrInfo * TII
A common definition of LaneBitmask for use in TableGen and CodeGen.
Implement a low-level type suitable for MachineInstr level instruction selection.
This file declares the MIR specialization of the GenericConvergenceVerifier template.
unsigned const TargetRegisterInfo * TRI
static void verifyConvergenceControl(const MachineFunction &MF, MachineDomTree &DT, std::function< void(const Twine &Message)> FailureCB)
modulo schedule Modulo Schedule test pass
const char LLVMTargetMachineRef TM
#define INITIALIZE_PASS(passName, arg, name, cfg, analysis)
This file builds on the ADT/GraphTraits.h file to build a generic graph post order iterator.
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
static bool isValid(const char C)
Returns true if C is a valid mangled character: <0-9a-zA-Z_>.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool isLiveOut(const MachineBasicBlock &MBB, unsigned Reg)
This file defines generic set operations that may be used on set's of different types,...
This file defines the SmallPtrSet class.
This file defines the SmallVector class.
static unsigned getSize(unsigned Kind)
const fltSemantics & getSemantics() const
Represent the analysis usage information of a pass.
AnalysisUsage & addUsedIfAvailable()
Add the specified Pass class to the set of analyses used by this pass.
void setPreservesAll()
Set by analyses that do not transform their input at all.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
LLVM Basic Block Representation.
bool hasAddressTaken() const
Returns true if there are any uses of this basic block other than direct branches,...
const Instruction * getTerminator() const LLVM_READONLY
Returns the terminator instruction if the block is well formed or null if the block is not well forme...
bool test(unsigned Idx) const
void clear()
clear - Removes all bits from the bitvector.
iterator_range< const_set_bits_iterator > set_bits() const
size_type size() const
size - Returns the number of bits in this bitvector.
ConnectedVNInfoEqClasses - Helper class that can divide VNInfos in a LiveInterval into equivalence cl...
ConstMIBundleOperands - Iterate over all operands in a const bundle of machine instructions.
ConstantFP - Floating Point Values [float, double].
const APFloat & getValueAPF() const
This is the shared class of boolean and integer constants.
unsigned getBitWidth() const
getBitWidth - Return the scalar bitwidth of this constant.
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
Implements a dense probed hash-table based set.
Core dominator tree base class.
void recalculate(ParentType &Func)
recalculate - compute a dominator tree for the given function
Base class for user error types.
A specialized PseudoSourceValue for holding FixedStack values, which must include a frame index.
FunctionPass class - This class is used to implement most global optimizations.
void initialize(raw_ostream *OS, function_ref< void(const Twine &Message)> FailureCB, const FunctionT &F)
void verify(const DominatorTreeT &DT)
void visit(const BlockT &BB)
bool isPredicated(const MachineInstr &MI) const override
Returns true if the instruction is already predicated.
bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
Analyze the branching code at the end of MBB, returning true if it cannot be understood (e....
constexpr bool isScalableVector() const
Returns true if the LLT is a scalable vector.
constexpr unsigned getScalarSizeInBits() const
constexpr bool isScalar() const
constexpr bool isValid() const
constexpr uint16_t getNumElements() const
Returns the number of elements in a vector LLT.
constexpr bool isVector() const
constexpr TypeSize getSizeInBits() const
Returns the total size of the type. Must only be called on sized types.
constexpr bool isPointer() const
constexpr LLT getElementType() const
Returns the vector's element type. Only valid for vector types.
constexpr ElementCount getElementCount() const
constexpr unsigned getAddressSpace() const
constexpr bool isPointerOrPointerVector() const
constexpr LLT getScalarType() const
constexpr TypeSize getSizeInBytes() const
Returns the total size of the type in bytes, i.e.
A live range for subregisters.
LiveInterval - This class represents the liveness of a register, or stack slot.
bool hasSubRanges() const
Returns true if subregister liveness information is available.
iterator_range< subrange_iterator > subranges()
void computeSubRangeUndefs(SmallVectorImpl< SlotIndex > &Undefs, LaneBitmask LaneMask, const MachineRegisterInfo &MRI, const SlotIndexes &Indexes) const
For a given lane mask LaneMask, compute indexes at which the lane is marked undefined by subregister ...
bool hasInterval(Register Reg) const
SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const
Return the first index in the given basic block.
MachineInstr * getInstructionFromIndex(SlotIndex index) const
Returns the instruction associated with the given index.
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const
Return the last index in the given basic block.
LiveRange * getCachedRegUnit(unsigned Unit)
Return the live range for register unit Unit if it has already been computed, or nullptr if it hasn't...
LiveInterval & getInterval(Register Reg)
bool isNotInMIMap(const MachineInstr &Instr) const
Returns true if the specified machine instr has been removed or was never entered in the map.
MachineBasicBlock * getMBBFromIndex(SlotIndex index) const
bool isLiveInToMBB(const LiveRange &LR, const MachineBasicBlock *mbb) const
void print(raw_ostream &O, const Module *=nullptr) const override
Implement the dump method.
Result of a LiveRange query.
bool isDeadDef() const
Return true if this instruction has a dead def.
VNInfo * valueIn() const
Return the value that is live-in to the instruction.
VNInfo * valueOut() const
Return the value leaving the instruction, if any.
bool isKill() const
Return true if the live-in value is killed by this instruction.
static LLVM_ATTRIBUTE_UNUSED bool isJointlyDominated(const MachineBasicBlock *MBB, ArrayRef< SlotIndex > Defs, const SlotIndexes &Indexes)
A diagnostic function to check if the end of the block MBB is jointly dominated by the blocks corresp...
This class represents the liveness of a register, stack slot, etc.
VNInfo * getValNumInfo(unsigned ValNo)
getValNumInfo - Returns pointer to the specified val#.
bool liveAt(SlotIndex index) const
bool covers(const LiveRange &Other) const
Returns true if all segments of the Other live range are completely covered by this live range.
LiveQueryResult Query(SlotIndex Idx) const
Query Liveness at Idx.
VNInfo * getVNInfoBefore(SlotIndex Idx) const
getVNInfoBefore - Return the VNInfo that is live up to but not necessarilly including Idx,...
unsigned getNumValNums() const
VNInfo * getVNInfoAt(SlotIndex Idx) const
getVNInfoAt - Return the VNInfo that is live at Idx, or NULL.
LiveInterval & getInterval(int Slot)
bool hasInterval(int Slot) const
VarInfo & getVarInfo(Register Reg)
getVarInfo - Return the VarInfo structure for the specified VIRTUAL register.
TypeSize getValue() const
This class is intended to be used as a base class for asm properties and features specific to the tar...
ExceptionHandling getExceptionHandlingType() const
Describe properties that are true of each instruction in the target description file.
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
ArrayRef< MCOperandInfo > operands() const
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
bool isConvergent() const
Return true if this instruction is convergent.
bool variadicOpsAreDefs() const
Return true if variadic operands of this instruction are definitions.
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specified operand constraint if it is present.
unsigned getOpcode() const
Return the opcode number for this descriptor.
This holds information about one operand of a machine instruction, indicating the register class for ...
bool isOptionalDef() const
Set if this operand is a optional def.
uint8_t OperandType
Information about the type of the operand.
MCRegAliasIterator enumerates all registers aliasing Reg.
bool isValid() const
isValid - Returns true until all the operands have been visited.
bool isInlineAsmBrIndirectTarget() const
Returns true if this is the indirect dest of an INLINEASM_BR.
unsigned pred_size() const
bool isEHPad() const
Returns true if the block is a landing pad.
iterator_range< livein_iterator > liveins() const
iterator_range< iterator > phis()
Returns a range that iterates over the phis in the basic block.
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
succ_iterator succ_begin()
bool isIRBlockAddressTaken() const
Test whether this block is the target of an IR BlockAddress.
unsigned succ_size() const
BasicBlock * getAddressTakenIRBlock() const
Retrieves the BasicBlock which corresponds to this MachineBasicBlock.
bool isPredecessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a predecessor of this block.
pred_iterator pred_begin()
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
unsigned getCallFrameSize() const
Return the call frame size on entry to this basic block.
iterator_range< succ_iterator > successors()
bool isSuccessor(const MachineBasicBlock *MBB) const
Return true if the specified MBB is a successor of this block.
iterator_range< pred_iterator > predecessors()
StringRef getName() const
Return the name of the corresponding LLVM basic block, or an empty string.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
BitVector getPristineRegs(const MachineFunction &MF) const
Return a set of physical registers that are pristine.
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
virtual bool runOnMachineFunction(MachineFunction &MF)=0
runOnMachineFunction - This method must be overloaded to perform the desired machine code transformat...
bool hasProperty(Property P) const
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
const MachineFunctionProperties & getProperties() const
Get the function properties.
const MachineBasicBlock & front() const
bool verify(Pass *p=nullptr, const char *Banner=nullptr, bool AbortOnError=true) const
Run the current MachineFunction through the machine code verifier, useful for debugger use.
void print(raw_ostream &OS, const SlotIndexes *=nullptr) const
print - Print out the MachineFunction in a format suitable for debugging to the specified stream.
BasicBlockListType::const_iterator const_iterator
Representation of each machine instruction.
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
bool isReturn(QueryType Type=AnyInBundle) const
bool isTerminator(QueryType Type=AnyInBundle) const
Returns true if this instruction part of the terminator for a basic block.
bool isBarrier(QueryType Type=AnyInBundle) const
Returns true if the specified instruction stops control flow from executing the instruction immediate...
A description of a memory reference used in the backend.
LocationSize getSize() const
Return the size in bytes of the memory reference.
const PseudoSourceValue * getPseudoValue() const
AtomicOrdering getSuccessOrdering() const
Return the atomic ordering requirements for this memory operation.
LocationSize getSizeInBits() const
Return the size in bits of the memory reference.
MachineOperand class - Representation of each machine instruction operand.
unsigned getSubReg() const
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register.
bool isIntrinsicID() const
bool isReg() const
isReg - Tests if this is a MO_Register operand.
MachineBasicBlock * getMBB() const
ArrayRef< int > getShuffleMask() const
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
bool isValidExcessOperand() const
Return true if this operand can validly be appended to an arbitrary operand list.
bool isShuffleMask() const
unsigned getCFIIndex() const
bool isRenamable() const
isRenamable - Returns true if this register may be renamed, i.e.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
MachineOperandType getType() const
getType - Returns the MachineOperandType for this operand.
bool isEarlyClobber() const
Register getReg() const
getReg - Returns the register number.
bool isInternalRead() const
bool isFI() const
isFI - Tests if this is a MO_FrameIndex operand.
static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg)
clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
const uint32_t * getRegMask() const
getRegMask - Returns a bit mask of registers preserved by this RegMask operand.
void print(raw_ostream &os, const TargetRegisterInfo *TRI=nullptr, const TargetIntrinsicInfo *IntrinsicInfo=nullptr) const
Print the MachineOperand to os.
@ MO_CFIIndex
MCCFIInstruction index.
@ MO_RegisterMask
Mask of preserved registers.
@ MO_MachineBasicBlock
MachineBasicBlock reference.
@ MO_FrameIndex
Abstract Stack Frame Index.
@ MO_Register
Register operand.
bool isMBB() const
isMBB - Tests if this is a MO_MachineBasicBlock operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Pass interface - Implemented by all 'passes'.
virtual void print(raw_ostream &OS, const Module *M) const
print - Print out the internal state of the pass.
AnalysisType * getAnalysisIfAvailable() const
getAnalysisIfAvailable<AnalysisType>() - Subclasses use this function to get analysis information tha...
Special value supplied for machine level alias analysis.
Holds all the information related to register banks.
const RegisterBank & getRegBank(unsigned ID)
Get the register bank identified by ID.
unsigned getMaximumSize(unsigned RegBankID) const
Get the maximum size in bits that fits in the given register bank.
This class implements the register bank concept.
const char * getName() const
Get a user friendly name of this register bank.
unsigned getID() const
Get the identifier of this register bank.
Wrapper class representing virtual and physical registers.
static Register index2VirtReg(unsigned Index)
Convert a 0-based index to a virtual register number.
static unsigned virtReg2Index(Register Reg)
Convert a virtual register number to a 0-based index.
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
static constexpr bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
SlotIndex - An opaque wrapper around machine indexes.
static bool isSameInstr(SlotIndex A, SlotIndex B)
isSameInstr - Return true if A and B refer to the same instruction.
bool isBlock() const
isBlock - Returns true if this is a block boundary slot.
SlotIndex getDeadSlot() const
Returns the dead def kill slot for the current instruction.
bool isEarlyClobber() const
isEarlyClobber - Returns true if this is an early-clobber slot.
bool isRegister() const
isRegister - Returns true if this is a normal register use/def slot.
SlotIndex getBoundaryIndex() const
Returns the boundary index for associated with this index.
SlotIndex getPrevSlot() const
Returns the previous slot in the index list.
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def.
bool isDead() const
isDead - Returns true if this is a dead def kill slot.
SlotIndex getMBBEndIdx(unsigned Num) const
Returns the last index in the given basic block number.
MBBIndexIterator MBBIndexBegin() const
Returns an iterator for the begin of the idx2MBBMap.
MBBIndexIterator MBBIndexEnd() const
Return an iterator for the end of the idx2MBBMap.
SmallVectorImpl< IdxMBBPair >::const_iterator MBBIndexIterator
Iterator over the idx2MBBMap (sorted pairs of slot index of basic block begin and basic block)
SlotIndex getInstructionIndex(const MachineInstr &MI, bool IgnoreBundle=false) const
Returns the base index for the given instruction.
SlotIndex getMBBStartIdx(unsigned Num) const
Returns the first index in the given basic block number.
bool hasIndex(const MachineInstr &instr) const
Returns true if the given machine instr is mapped to an index, otherwise returns false.
bool erase(PtrType Ptr)
erase - If the set contains the specified pointer, remove it and return true, otherwise return false.
size_type count(ConstPtrType Ptr) const
count - Return 1 if the specified pointer is in the set, 0 otherwise.
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
MI-level Statepoint operands.
StringRef - Represent a constant reference to a string, i.e.
TargetInstrInfo - Interface to description of machine instruction set.
Primary interface to the complete machine description for the target machine.
bool hasSuperClassEq(const TargetRegisterClass *RC) const
Returns true if RC is a super-class of or equal to this class.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual const RegisterBankInfo * getRegBankInfo() const
If the information for the register banks is available, return it.
virtual const TargetInstrInfo * getInstrInfo() const
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
VNInfo - Value Number Information.
bool isUnused() const
Returns true if this value is unused.
unsigned id
The ID number of this value.
SlotIndex def
The index of the defining instruction.
bool isPHIDef() const
Returns true if this value is defined by a PHI instruction (or was, PHI instructions may have been el...
LLVM Value Representation.
std::pair< iterator, bool > insert(const ValueT &V)
constexpr bool isNonZero() const
static constexpr bool isKnownLT(const FixedOrScalableQuantity &LHS, const FixedOrScalableQuantity &RHS)
constexpr bool isScalable() const
Returns whether the quantity is scaled by a runtime quantity (vscale).
constexpr ScalarTy getKnownMinValue() const
Returns the minimum value this quantity can represent.
static constexpr bool isKnownGT(const FixedOrScalableQuantity &LHS, const FixedOrScalableQuantity &RHS)
static constexpr bool isKnownGE(const FixedOrScalableQuantity &LHS, const FixedOrScalableQuantity &RHS)
self_iterator getIterator()
NodeTy * getNextNode()
Get the next node, or nullptr for the list tail.
constexpr char Attrs[]
Key for Kernel::Metadata::mAttrs.
const CustomOperand< const MCSubtargetInfo & > Msg[]
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
AttributeList getAttributes(LLVMContext &C, ID id)
Return the attributes for an intrinsic.
Reg
All possible values of the reg field in the ModR/M byte.
NodeAddr< PhiNode * > Phi
NodeAddr< DefNode * > Def
const_iterator begin(StringRef path, Style style=Style::native)
Get begin iterator over path.
const_iterator end(StringRef path)
Get end iterator over path.
This is an optimization pass for GlobalISel generic memory operations.
auto drop_begin(T &&RangeOrContainer, size_t N=1)
Return a range covering RangeOrContainer with the first N elements excluded.
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
@ SjLj
setjmp/longjmp based exceptions
bool isPreISelGenericOpcode(unsigned Opcode)
Check whether the given Opcode is a generic opcode that is not supposed to appear after ISel.
Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI)
Create Printable object to print register units on a raw_ostream.
void append_range(Container &C, Range &&R)
Wrapper function to append range R to container C.
void set_subtract(S1Ty &S1, const S2Ty &S2)
set_subtract(A, B) - Compute A := A - B
Printable PrintLaneMask(LaneBitmask LaneMask)
Create Printable object to print LaneBitmasks on a raw_ostream.
bool isPreISelGenericOptimizationHint(unsigned Opcode)
bool isScopedEHPersonality(EHPersonality Pers)
Returns true if this personality uses scope-style EH IR instructions: catchswitch,...
void initializeMachineVerifierPassPass(PassRegistry &)
void verifyMachineFunction(const std::string &Banner, const MachineFunction &MF)
auto reverse(ContainerTy &&C)
detail::ValueMatchesPoly< M > HasValue(M Matcher)
df_ext_iterator< T, SetTy > df_ext_begin(const T &G, SetTy &S)
bool none_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
bool set_union(S1Ty &S1, const S2Ty &S2)
set_union(A, B) - Compute A := A u B, return whether A changed.
EHPersonality classifyEHPersonality(const Value *Pers)
See if the given exception handling personality function is one that we understand.
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
AtomicOrdering
Atomic ordering for LLVM's memory model.
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
df_ext_iterator< T, SetTy > df_ext_end(const T &G, SetTy &S)
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.
FunctionPass * createMachineVerifierPass(const std::string &Banner)
createMachineVerifierPass - This pass verifies cenerated machine code instructions for correctness.
Implement std::hash so that hash_code can be used in STL containers.
static unsigned getSizeInBits(const fltSemantics &Sem)
Returns the size of the floating point number (in bits) in the given semantics.
static constexpr LaneBitmask getAll()
constexpr bool none() const
constexpr bool any() const
static constexpr LaneBitmask getNone()
This represents a simple continuous liveness interval for a value.
VarInfo - This represents the regions where a virtual register is live in the program.
Pair of physical register and lane mask.