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PPCFrameLowering.cpp
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00001 //===-- PPCFrameLowering.cpp - PPC Frame Information ----------------------===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file contains the PPC implementation of TargetFrameLowering class.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #include "PPCFrameLowering.h"
00015 #include "PPCInstrBuilder.h"
00016 #include "PPCInstrInfo.h"
00017 #include "PPCMachineFunctionInfo.h"
00018 #include "PPCSubtarget.h"
00019 #include "llvm/CodeGen/MachineFrameInfo.h"
00020 #include "llvm/CodeGen/MachineFunction.h"
00021 #include "llvm/CodeGen/MachineInstrBuilder.h"
00022 #include "llvm/CodeGen/MachineModuleInfo.h"
00023 #include "llvm/CodeGen/MachineRegisterInfo.h"
00024 #include "llvm/CodeGen/RegisterScavenging.h"
00025 #include "llvm/IR/Function.h"
00026 #include "llvm/Target/TargetOptions.h"
00027 
00028 using namespace llvm;
00029 
00030 /// VRRegNo - Map from a numbered VR register to its enum value.
00031 ///
00032 static const uint16_t VRRegNo[] = {
00033  PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
00034  PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
00035  PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
00036  PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
00037 };
00038 
00039 PPCFrameLowering::PPCFrameLowering(const PPCSubtarget &STI)
00040     : TargetFrameLowering(TargetFrameLowering::StackGrowsDown,
00041                           (STI.hasQPX() || STI.isBGQ()) ? 32 : 16, 0),
00042       Subtarget(STI) {}
00043 
00044 // With the SVR4 ABI, callee-saved registers have fixed offsets on the stack.
00045 const PPCFrameLowering::SpillSlot *PPCFrameLowering::getCalleeSavedSpillSlots(
00046     unsigned &NumEntries) const {
00047   if (Subtarget.isDarwinABI()) {
00048     NumEntries = 1;
00049     if (Subtarget.isPPC64()) {
00050       static const SpillSlot darwin64Offsets = {PPC::X31, -8};
00051       return &darwin64Offsets;
00052     } else {
00053       static const SpillSlot darwinOffsets = {PPC::R31, -4};
00054       return &darwinOffsets;
00055     }
00056   }
00057 
00058   // Early exit if not using the SVR4 ABI.
00059   if (!Subtarget.isSVR4ABI()) {
00060     NumEntries = 0;
00061     return nullptr;
00062   }
00063 
00064   // Note that the offsets here overlap, but this is fixed up in
00065   // processFunctionBeforeFrameFinalized.
00066 
00067   static const SpillSlot Offsets[] = {
00068       // Floating-point register save area offsets.
00069       {PPC::F31, -8},
00070       {PPC::F30, -16},
00071       {PPC::F29, -24},
00072       {PPC::F28, -32},
00073       {PPC::F27, -40},
00074       {PPC::F26, -48},
00075       {PPC::F25, -56},
00076       {PPC::F24, -64},
00077       {PPC::F23, -72},
00078       {PPC::F22, -80},
00079       {PPC::F21, -88},
00080       {PPC::F20, -96},
00081       {PPC::F19, -104},
00082       {PPC::F18, -112},
00083       {PPC::F17, -120},
00084       {PPC::F16, -128},
00085       {PPC::F15, -136},
00086       {PPC::F14, -144},
00087 
00088       // General register save area offsets.
00089       {PPC::R31, -4},
00090       {PPC::R30, -8},
00091       {PPC::R29, -12},
00092       {PPC::R28, -16},
00093       {PPC::R27, -20},
00094       {PPC::R26, -24},
00095       {PPC::R25, -28},
00096       {PPC::R24, -32},
00097       {PPC::R23, -36},
00098       {PPC::R22, -40},
00099       {PPC::R21, -44},
00100       {PPC::R20, -48},
00101       {PPC::R19, -52},
00102       {PPC::R18, -56},
00103       {PPC::R17, -60},
00104       {PPC::R16, -64},
00105       {PPC::R15, -68},
00106       {PPC::R14, -72},
00107 
00108       // CR save area offset.  We map each of the nonvolatile CR fields
00109       // to the slot for CR2, which is the first of the nonvolatile CR
00110       // fields to be assigned, so that we only allocate one save slot.
00111       // See PPCRegisterInfo::hasReservedSpillSlot() for more information.
00112       {PPC::CR2, -4},
00113 
00114       // VRSAVE save area offset.
00115       {PPC::VRSAVE, -4},
00116 
00117       // Vector register save area
00118       {PPC::V31, -16},
00119       {PPC::V30, -32},
00120       {PPC::V29, -48},
00121       {PPC::V28, -64},
00122       {PPC::V27, -80},
00123       {PPC::V26, -96},
00124       {PPC::V25, -112},
00125       {PPC::V24, -128},
00126       {PPC::V23, -144},
00127       {PPC::V22, -160},
00128       {PPC::V21, -176},
00129       {PPC::V20, -192}};
00130 
00131   static const SpillSlot Offsets64[] = {
00132       // Floating-point register save area offsets.
00133       {PPC::F31, -8},
00134       {PPC::F30, -16},
00135       {PPC::F29, -24},
00136       {PPC::F28, -32},
00137       {PPC::F27, -40},
00138       {PPC::F26, -48},
00139       {PPC::F25, -56},
00140       {PPC::F24, -64},
00141       {PPC::F23, -72},
00142       {PPC::F22, -80},
00143       {PPC::F21, -88},
00144       {PPC::F20, -96},
00145       {PPC::F19, -104},
00146       {PPC::F18, -112},
00147       {PPC::F17, -120},
00148       {PPC::F16, -128},
00149       {PPC::F15, -136},
00150       {PPC::F14, -144},
00151 
00152       // General register save area offsets.
00153       {PPC::X31, -8},
00154       {PPC::X30, -16},
00155       {PPC::X29, -24},
00156       {PPC::X28, -32},
00157       {PPC::X27, -40},
00158       {PPC::X26, -48},
00159       {PPC::X25, -56},
00160       {PPC::X24, -64},
00161       {PPC::X23, -72},
00162       {PPC::X22, -80},
00163       {PPC::X21, -88},
00164       {PPC::X20, -96},
00165       {PPC::X19, -104},
00166       {PPC::X18, -112},
00167       {PPC::X17, -120},
00168       {PPC::X16, -128},
00169       {PPC::X15, -136},
00170       {PPC::X14, -144},
00171 
00172       // VRSAVE save area offset.
00173       {PPC::VRSAVE, -4},
00174 
00175       // Vector register save area
00176       {PPC::V31, -16},
00177       {PPC::V30, -32},
00178       {PPC::V29, -48},
00179       {PPC::V28, -64},
00180       {PPC::V27, -80},
00181       {PPC::V26, -96},
00182       {PPC::V25, -112},
00183       {PPC::V24, -128},
00184       {PPC::V23, -144},
00185       {PPC::V22, -160},
00186       {PPC::V21, -176},
00187       {PPC::V20, -192}};
00188 
00189   if (Subtarget.isPPC64()) {
00190     NumEntries = array_lengthof(Offsets64);
00191 
00192     return Offsets64;
00193   } else {
00194     NumEntries = array_lengthof(Offsets);
00195 
00196     return Offsets;
00197   }
00198 }
00199 
00200 /// RemoveVRSaveCode - We have found that this function does not need any code
00201 /// to manipulate the VRSAVE register, even though it uses vector registers.
00202 /// This can happen when the only registers used are known to be live in or out
00203 /// of the function.  Remove all of the VRSAVE related code from the function.
00204 /// FIXME: The removal of the code results in a compile failure at -O0 when the
00205 /// function contains a function call, as the GPR containing original VRSAVE
00206 /// contents is spilled and reloaded around the call.  Without the prolog code,
00207 /// the spill instruction refers to an undefined register.  This code needs
00208 /// to account for all uses of that GPR.
00209 static void RemoveVRSaveCode(MachineInstr *MI) {
00210   MachineBasicBlock *Entry = MI->getParent();
00211   MachineFunction *MF = Entry->getParent();
00212 
00213   // We know that the MTVRSAVE instruction immediately follows MI.  Remove it.
00214   MachineBasicBlock::iterator MBBI = MI;
00215   ++MBBI;
00216   assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
00217   MBBI->eraseFromParent();
00218 
00219   bool RemovedAllMTVRSAVEs = true;
00220   // See if we can find and remove the MTVRSAVE instruction from all of the
00221   // epilog blocks.
00222   for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
00223     // If last instruction is a return instruction, add an epilogue
00224     if (!I->empty() && I->back().isReturn()) {
00225       bool FoundIt = false;
00226       for (MBBI = I->end(); MBBI != I->begin(); ) {
00227         --MBBI;
00228         if (MBBI->getOpcode() == PPC::MTVRSAVE) {
00229           MBBI->eraseFromParent();  // remove it.
00230           FoundIt = true;
00231           break;
00232         }
00233       }
00234       RemovedAllMTVRSAVEs &= FoundIt;
00235     }
00236   }
00237 
00238   // If we found and removed all MTVRSAVE instructions, remove the read of
00239   // VRSAVE as well.
00240   if (RemovedAllMTVRSAVEs) {
00241     MBBI = MI;
00242     assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?");
00243     --MBBI;
00244     assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
00245     MBBI->eraseFromParent();
00246   }
00247 
00248   // Finally, nuke the UPDATE_VRSAVE.
00249   MI->eraseFromParent();
00250 }
00251 
00252 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
00253 // instruction selector.  Based on the vector registers that have been used,
00254 // transform this into the appropriate ORI instruction.
00255 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) {
00256   MachineFunction *MF = MI->getParent()->getParent();
00257   const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
00258   DebugLoc dl = MI->getDebugLoc();
00259 
00260   unsigned UsedRegMask = 0;
00261   for (unsigned i = 0; i != 32; ++i)
00262     if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i]))
00263       UsedRegMask |= 1 << (31-i);
00264 
00265   // Live in and live out values already must be in the mask, so don't bother
00266   // marking them.
00267   for (MachineRegisterInfo::livein_iterator
00268        I = MF->getRegInfo().livein_begin(),
00269        E = MF->getRegInfo().livein_end(); I != E; ++I) {
00270     unsigned RegNo = TRI->getEncodingValue(I->first);
00271     if (VRRegNo[RegNo] == I->first)        // If this really is a vector reg.
00272       UsedRegMask &= ~(1 << (31-RegNo));   // Doesn't need to be marked.
00273   }
00274 
00275   // Live out registers appear as use operands on return instructions.
00276   for (MachineFunction::const_iterator BI = MF->begin(), BE = MF->end();
00277        UsedRegMask != 0 && BI != BE; ++BI) {
00278     const MachineBasicBlock &MBB = *BI;
00279     if (MBB.empty() || !MBB.back().isReturn())
00280       continue;
00281     const MachineInstr &Ret = MBB.back();
00282     for (unsigned I = 0, E = Ret.getNumOperands(); I != E; ++I) {
00283       const MachineOperand &MO = Ret.getOperand(I);
00284       if (!MO.isReg() || !PPC::VRRCRegClass.contains(MO.getReg()))
00285         continue;
00286       unsigned RegNo = TRI->getEncodingValue(MO.getReg());
00287       UsedRegMask &= ~(1 << (31-RegNo));
00288     }
00289   }
00290 
00291   // If no registers are used, turn this into a copy.
00292   if (UsedRegMask == 0) {
00293     // Remove all VRSAVE code.
00294     RemoveVRSaveCode(MI);
00295     return;
00296   }
00297 
00298   unsigned SrcReg = MI->getOperand(1).getReg();
00299   unsigned DstReg = MI->getOperand(0).getReg();
00300 
00301   if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
00302     if (DstReg != SrcReg)
00303       BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
00304         .addReg(SrcReg)
00305         .addImm(UsedRegMask);
00306     else
00307       BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
00308         .addReg(SrcReg, RegState::Kill)
00309         .addImm(UsedRegMask);
00310   } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
00311     if (DstReg != SrcReg)
00312       BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
00313         .addReg(SrcReg)
00314         .addImm(UsedRegMask >> 16);
00315     else
00316       BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
00317         .addReg(SrcReg, RegState::Kill)
00318         .addImm(UsedRegMask >> 16);
00319   } else {
00320     if (DstReg != SrcReg)
00321       BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
00322         .addReg(SrcReg)
00323         .addImm(UsedRegMask >> 16);
00324     else
00325       BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
00326         .addReg(SrcReg, RegState::Kill)
00327         .addImm(UsedRegMask >> 16);
00328 
00329     BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
00330       .addReg(DstReg, RegState::Kill)
00331       .addImm(UsedRegMask & 0xFFFF);
00332   }
00333 
00334   // Remove the old UPDATE_VRSAVE instruction.
00335   MI->eraseFromParent();
00336 }
00337 
00338 static bool spillsCR(const MachineFunction &MF) {
00339   const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
00340   return FuncInfo->isCRSpilled();
00341 }
00342 
00343 static bool spillsVRSAVE(const MachineFunction &MF) {
00344   const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
00345   return FuncInfo->isVRSAVESpilled();
00346 }
00347 
00348 static bool hasSpills(const MachineFunction &MF) {
00349   const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
00350   return FuncInfo->hasSpills();
00351 }
00352 
00353 static bool hasNonRISpills(const MachineFunction &MF) {
00354   const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
00355   return FuncInfo->hasNonRISpills();
00356 }
00357 
00358 /// determineFrameLayout - Determine the size of the frame and maximum call
00359 /// frame size.
00360 unsigned PPCFrameLowering::determineFrameLayout(MachineFunction &MF,
00361                                                 bool UpdateMF,
00362                                                 bool UseEstimate) const {
00363   MachineFrameInfo *MFI = MF.getFrameInfo();
00364 
00365   // Get the number of bytes to allocate from the FrameInfo
00366   unsigned FrameSize =
00367     UseEstimate ? MFI->estimateStackSize(MF) : MFI->getStackSize();
00368 
00369   // Get stack alignments. The frame must be aligned to the greatest of these:
00370   unsigned TargetAlign = getStackAlignment(); // alignment required per the ABI
00371   unsigned MaxAlign = MFI->getMaxAlignment(); // algmt required by data in frame
00372   unsigned AlignMask = std::max(MaxAlign, TargetAlign) - 1;
00373 
00374   const PPCRegisterInfo *RegInfo =
00375     static_cast<const PPCRegisterInfo*>(MF.getTarget().getRegisterInfo());
00376 
00377   // If we are a leaf function, and use up to 224 bytes of stack space,
00378   // don't have a frame pointer, calls, or dynamic alloca then we do not need
00379   // to adjust the stack pointer (we fit in the Red Zone).
00380   // The 32-bit SVR4 ABI has no Red Zone. However, it can still generate
00381   // stackless code if all local vars are reg-allocated.
00382   bool DisableRedZone = MF.getFunction()->getAttributes().
00383     hasAttribute(AttributeSet::FunctionIndex, Attribute::NoRedZone);
00384   if (!DisableRedZone &&
00385       (Subtarget.isPPC64() ||                      // 32-bit SVR4, no stack-
00386        !Subtarget.isSVR4ABI() ||                   //   allocated locals.
00387         FrameSize == 0) &&
00388       FrameSize <= 224 &&                          // Fits in red zone.
00389       !MFI->hasVarSizedObjects() &&                // No dynamic alloca.
00390       !MFI->adjustsStack() &&                      // No calls.
00391       !RegInfo->hasBasePointer(MF)) { // No special alignment.
00392     // No need for frame
00393     if (UpdateMF)
00394       MFI->setStackSize(0);
00395     return 0;
00396   }
00397 
00398   // Get the maximum call frame size of all the calls.
00399   unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
00400 
00401   // Maximum call frame needs to be at least big enough for linkage area.
00402   unsigned minCallFrameSize = getLinkageSize(Subtarget.isPPC64(),
00403                                              Subtarget.isDarwinABI(),
00404                                              Subtarget.isELFv2ABI());
00405   maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);
00406 
00407   // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
00408   // that allocations will be aligned.
00409   if (MFI->hasVarSizedObjects())
00410     maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
00411 
00412   // Update maximum call frame size.
00413   if (UpdateMF)
00414     MFI->setMaxCallFrameSize(maxCallFrameSize);
00415 
00416   // Include call frame size in total.
00417   FrameSize += maxCallFrameSize;
00418 
00419   // Make sure the frame is aligned.
00420   FrameSize = (FrameSize + AlignMask) & ~AlignMask;
00421 
00422   // Update frame info.
00423   if (UpdateMF)
00424     MFI->setStackSize(FrameSize);
00425 
00426   return FrameSize;
00427 }
00428 
00429 // hasFP - Return true if the specified function actually has a dedicated frame
00430 // pointer register.
00431 bool PPCFrameLowering::hasFP(const MachineFunction &MF) const {
00432   const MachineFrameInfo *MFI = MF.getFrameInfo();
00433   // FIXME: This is pretty much broken by design: hasFP() might be called really
00434   // early, before the stack layout was calculated and thus hasFP() might return
00435   // true or false here depending on the time of call.
00436   return (MFI->getStackSize()) && needsFP(MF);
00437 }
00438 
00439 // needsFP - Return true if the specified function should have a dedicated frame
00440 // pointer register.  This is true if the function has variable sized allocas or
00441 // if frame pointer elimination is disabled.
00442 bool PPCFrameLowering::needsFP(const MachineFunction &MF) const {
00443   const MachineFrameInfo *MFI = MF.getFrameInfo();
00444 
00445   // Naked functions have no stack frame pushed, so we don't have a frame
00446   // pointer.
00447   if (MF.getFunction()->getAttributes().hasAttribute(
00448           AttributeSet::FunctionIndex, Attribute::Naked))
00449     return false;
00450 
00451   return MF.getTarget().Options.DisableFramePointerElim(MF) ||
00452     MFI->hasVarSizedObjects() ||
00453     (MF.getTarget().Options.GuaranteedTailCallOpt &&
00454      MF.getInfo<PPCFunctionInfo>()->hasFastCall());
00455 }
00456 
00457 void PPCFrameLowering::replaceFPWithRealFP(MachineFunction &MF) const {
00458   bool is31 = needsFP(MF);
00459   unsigned FPReg  = is31 ? PPC::R31 : PPC::R1;
00460   unsigned FP8Reg = is31 ? PPC::X31 : PPC::X1;
00461 
00462   const PPCRegisterInfo *RegInfo =
00463     static_cast<const PPCRegisterInfo*>(MF.getTarget().getRegisterInfo());
00464   bool HasBP = RegInfo->hasBasePointer(MF);
00465   unsigned BPReg  = HasBP ? (unsigned) RegInfo->getBaseRegister(MF) : FPReg;
00466   unsigned BP8Reg = HasBP ? (unsigned) PPC::X30 : FPReg;
00467 
00468   for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
00469        BI != BE; ++BI)
00470     for (MachineBasicBlock::iterator MBBI = BI->end(); MBBI != BI->begin(); ) {
00471       --MBBI;
00472       for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) {
00473         MachineOperand &MO = MBBI->getOperand(I);
00474         if (!MO.isReg())
00475           continue;
00476 
00477         switch (MO.getReg()) {
00478         case PPC::FP:
00479           MO.setReg(FPReg);
00480           break;
00481         case PPC::FP8:
00482           MO.setReg(FP8Reg);
00483           break;
00484         case PPC::BP:
00485           MO.setReg(BPReg);
00486           break;
00487         case PPC::BP8:
00488           MO.setReg(BP8Reg);
00489           break;
00490 
00491         }
00492       }
00493     }
00494 }
00495 
00496 void PPCFrameLowering::emitPrologue(MachineFunction &MF) const {
00497   MachineBasicBlock &MBB = MF.front();   // Prolog goes in entry BB
00498   MachineBasicBlock::iterator MBBI = MBB.begin();
00499   MachineFrameInfo *MFI = MF.getFrameInfo();
00500   const PPCInstrInfo &TII =
00501     *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo());
00502   const PPCRegisterInfo *RegInfo =
00503     static_cast<const PPCRegisterInfo*>(MF.getTarget().getRegisterInfo());
00504 
00505   MachineModuleInfo &MMI = MF.getMMI();
00506   const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
00507   DebugLoc dl;
00508   bool needsFrameMoves = MMI.hasDebugInfo() ||
00509     MF.getFunction()->needsUnwindTableEntry();
00510   bool isPIC = MF.getTarget().getRelocationModel() == Reloc::PIC_;
00511 
00512   // Get processor type.
00513   bool isPPC64 = Subtarget.isPPC64();
00514   // Get the ABI.
00515   bool isDarwinABI = Subtarget.isDarwinABI();
00516   bool isSVR4ABI = Subtarget.isSVR4ABI();
00517   bool isELFv2ABI = Subtarget.isELFv2ABI();
00518   assert((isDarwinABI || isSVR4ABI) &&
00519          "Currently only Darwin and SVR4 ABIs are supported for PowerPC.");
00520 
00521   // Scan the prolog, looking for an UPDATE_VRSAVE instruction.  If we find it,
00522   // process it.
00523   if (!isSVR4ABI)
00524     for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
00525       if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
00526         HandleVRSaveUpdate(MBBI, TII);
00527         break;
00528       }
00529     }
00530 
00531   // Move MBBI back to the beginning of the function.
00532   MBBI = MBB.begin();
00533 
00534   // Work out frame sizes.
00535   unsigned FrameSize = determineFrameLayout(MF);
00536   int NegFrameSize = -FrameSize;
00537   if (!isInt<32>(NegFrameSize))
00538     llvm_unreachable("Unhandled stack size!");
00539 
00540   if (MFI->isFrameAddressTaken())
00541     replaceFPWithRealFP(MF);
00542 
00543   // Check if the link register (LR) must be saved.
00544   PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
00545   bool MustSaveLR = FI->mustSaveLR();
00546   const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs();
00547   // Do we have a frame pointer and/or base pointer for this function?
00548   bool HasFP = hasFP(MF);
00549   bool HasBP = RegInfo->hasBasePointer(MF);
00550 
00551   unsigned SPReg       = isPPC64 ? PPC::X1  : PPC::R1;
00552   unsigned BPReg       = RegInfo->getBaseRegister(MF);
00553   unsigned FPReg       = isPPC64 ? PPC::X31 : PPC::R31;
00554   unsigned LRReg       = isPPC64 ? PPC::LR8 : PPC::LR;
00555   unsigned ScratchReg  = isPPC64 ? PPC::X0  : PPC::R0;
00556   unsigned TempReg     = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
00557   //  ...(R12/X12 is volatile in both Darwin & SVR4, & can't be a function arg.)
00558   const MCInstrDesc& MFLRInst = TII.get(isPPC64 ? PPC::MFLR8
00559                                                 : PPC::MFLR );
00560   const MCInstrDesc& StoreInst = TII.get(isPPC64 ? PPC::STD
00561                                                  : PPC::STW );
00562   const MCInstrDesc& StoreUpdtInst = TII.get(isPPC64 ? PPC::STDU
00563                                                      : PPC::STWU );
00564   const MCInstrDesc& StoreUpdtIdxInst = TII.get(isPPC64 ? PPC::STDUX
00565                                                         : PPC::STWUX);
00566   const MCInstrDesc& LoadImmShiftedInst = TII.get(isPPC64 ? PPC::LIS8
00567                                                           : PPC::LIS );
00568   const MCInstrDesc& OrImmInst = TII.get(isPPC64 ? PPC::ORI8
00569                                                  : PPC::ORI );
00570   const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8
00571                                               : PPC::OR );
00572   const MCInstrDesc& SubtractCarryingInst = TII.get(isPPC64 ? PPC::SUBFC8
00573                                                             : PPC::SUBFC);
00574   const MCInstrDesc& SubtractImmCarryingInst = TII.get(isPPC64 ? PPC::SUBFIC8
00575                                                                : PPC::SUBFIC);
00576 
00577   // Regarding this assert: Even though LR is saved in the caller's frame (i.e.,
00578   // LROffset is positive), that slot is callee-owned. Because PPC32 SVR4 has no
00579   // Red Zone, an asynchronous event (a form of "callee") could claim a frame &
00580   // overwrite it, so PPC32 SVR4 must claim at least a minimal frame to save LR.
00581   assert((isPPC64 || !isSVR4ABI || !(!FrameSize && (MustSaveLR || HasFP))) &&
00582          "FrameSize must be >0 to save/restore the FP or LR for 32-bit SVR4.");
00583 
00584   int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
00585 
00586   int FPOffset = 0;
00587   if (HasFP) {
00588     if (isSVR4ABI) {
00589       MachineFrameInfo *FFI = MF.getFrameInfo();
00590       int FPIndex = FI->getFramePointerSaveIndex();
00591       assert(FPIndex && "No Frame Pointer Save Slot!");
00592       FPOffset = FFI->getObjectOffset(FPIndex);
00593     } else {
00594       FPOffset =
00595           PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
00596     }
00597   }
00598 
00599   int BPOffset = 0;
00600   if (HasBP) {
00601     if (isSVR4ABI) {
00602       MachineFrameInfo *FFI = MF.getFrameInfo();
00603       int BPIndex = FI->getBasePointerSaveIndex();
00604       assert(BPIndex && "No Base Pointer Save Slot!");
00605       BPOffset = FFI->getObjectOffset(BPIndex);
00606     } else {
00607       BPOffset =
00608         PPCFrameLowering::getBasePointerSaveOffset(isPPC64,
00609                                                    isDarwinABI,
00610                                                    isPIC);
00611     }
00612   }
00613 
00614   // Get stack alignments.
00615   unsigned MaxAlign = MFI->getMaxAlignment();
00616   if (HasBP && MaxAlign > 1)
00617     assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) &&
00618            "Invalid alignment!");
00619 
00620   // Frames of 32KB & larger require special handling because they cannot be
00621   // indexed into with a simple STDU/STWU/STD/STW immediate offset operand.
00622   bool isLargeFrame = !isInt<16>(NegFrameSize);
00623 
00624   if (MustSaveLR)
00625     BuildMI(MBB, MBBI, dl, MFLRInst, ScratchReg);
00626 
00627   assert((isPPC64 || MustSaveCRs.empty()) &&
00628          "Prologue CR saving supported only in 64-bit mode");
00629 
00630   if (!MustSaveCRs.empty()) { // will only occur for PPC64
00631     // FIXME: In the ELFv2 ABI, we are not required to save all CR fields.
00632     // If only one or two CR fields are clobbered, it could be more
00633     // efficient to use mfocrf to selectively save just those fields.
00634     MachineInstrBuilder MIB =
00635       BuildMI(MBB, MBBI, dl, TII.get(PPC::MFCR8), TempReg);
00636     for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
00637       MIB.addReg(MustSaveCRs[i], RegState::ImplicitKill);
00638   }
00639 
00640   if (HasFP)
00641     // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
00642     BuildMI(MBB, MBBI, dl, StoreInst)
00643       .addReg(FPReg)
00644       .addImm(FPOffset)
00645       .addReg(SPReg);
00646 
00647   if (HasBP)
00648     // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
00649     BuildMI(MBB, MBBI, dl, StoreInst)
00650       .addReg(BPReg)
00651       .addImm(BPOffset)
00652       .addReg(SPReg);
00653 
00654   if (MustSaveLR)
00655     // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
00656     BuildMI(MBB, MBBI, dl, StoreInst)
00657       .addReg(ScratchReg)
00658       .addImm(LROffset)
00659       .addReg(SPReg);
00660 
00661   if (!MustSaveCRs.empty()) // will only occur for PPC64
00662     BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8))
00663       .addReg(TempReg, getKillRegState(true))
00664       .addImm(8)
00665       .addReg(SPReg);
00666 
00667   // Skip the rest if this is a leaf function & all spills fit in the Red Zone.
00668   if (!FrameSize) return;
00669 
00670   // Adjust stack pointer: r1 += NegFrameSize.
00671   // If there is a preferred stack alignment, align R1 now
00672 
00673   if (HasBP) {
00674     // Save a copy of r1 as the base pointer.
00675     BuildMI(MBB, MBBI, dl, OrInst, BPReg)
00676       .addReg(SPReg)
00677       .addReg(SPReg);
00678   }
00679 
00680   if (HasBP && MaxAlign > 1) {
00681     if (isPPC64)
00682       BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), ScratchReg)
00683         .addReg(SPReg)
00684         .addImm(0)
00685         .addImm(64 - Log2_32(MaxAlign));
00686     else // PPC32...
00687       BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), ScratchReg)
00688         .addReg(SPReg)
00689         .addImm(0)
00690         .addImm(32 - Log2_32(MaxAlign))
00691         .addImm(31);
00692     if (!isLargeFrame) {
00693       BuildMI(MBB, MBBI, dl, SubtractImmCarryingInst, ScratchReg)
00694         .addReg(ScratchReg, RegState::Kill)
00695         .addImm(NegFrameSize);
00696     } else {
00697       BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, TempReg)
00698         .addImm(NegFrameSize >> 16);
00699       BuildMI(MBB, MBBI, dl, OrImmInst, TempReg)
00700         .addReg(TempReg, RegState::Kill)
00701         .addImm(NegFrameSize & 0xFFFF);
00702       BuildMI(MBB, MBBI, dl, SubtractCarryingInst, ScratchReg)
00703         .addReg(ScratchReg, RegState::Kill)
00704         .addReg(TempReg, RegState::Kill);
00705     }
00706     BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg)
00707       .addReg(SPReg, RegState::Kill)
00708       .addReg(SPReg)
00709       .addReg(ScratchReg);
00710 
00711   } else if (!isLargeFrame) {
00712     BuildMI(MBB, MBBI, dl, StoreUpdtInst, SPReg)
00713       .addReg(SPReg)
00714       .addImm(NegFrameSize)
00715       .addReg(SPReg);
00716 
00717   } else {
00718     BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
00719       .addImm(NegFrameSize >> 16);
00720     BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
00721       .addReg(ScratchReg, RegState::Kill)
00722       .addImm(NegFrameSize & 0xFFFF);
00723     BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg)
00724       .addReg(SPReg, RegState::Kill)
00725       .addReg(SPReg)
00726       .addReg(ScratchReg);
00727   }
00728 
00729   // Add the "machine moves" for the instructions we generated above, but in
00730   // reverse order.
00731   if (needsFrameMoves) {
00732     // Show update of SP.
00733     assert(NegFrameSize);
00734     unsigned CFIIndex = MMI.addFrameInst(
00735         MCCFIInstruction::createDefCfaOffset(nullptr, NegFrameSize));
00736     BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
00737         .addCFIIndex(CFIIndex);
00738 
00739     if (HasFP) {
00740       unsigned Reg = MRI->getDwarfRegNum(FPReg, true);
00741       CFIIndex = MMI.addFrameInst(
00742           MCCFIInstruction::createOffset(nullptr, Reg, FPOffset));
00743       BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
00744           .addCFIIndex(CFIIndex);
00745     }
00746 
00747     if (HasBP) {
00748       unsigned Reg = MRI->getDwarfRegNum(BPReg, true);
00749       CFIIndex = MMI.addFrameInst(
00750           MCCFIInstruction::createOffset(nullptr, Reg, BPOffset));
00751       BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
00752           .addCFIIndex(CFIIndex);
00753     }
00754 
00755     if (MustSaveLR) {
00756       unsigned Reg = MRI->getDwarfRegNum(LRReg, true);
00757       CFIIndex = MMI.addFrameInst(
00758           MCCFIInstruction::createOffset(nullptr, Reg, LROffset));
00759       BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
00760           .addCFIIndex(CFIIndex);
00761     }
00762   }
00763 
00764   // If there is a frame pointer, copy R1 into R31
00765   if (HasFP) {
00766     BuildMI(MBB, MBBI, dl, OrInst, FPReg)
00767       .addReg(SPReg)
00768       .addReg(SPReg);
00769 
00770     if (needsFrameMoves) {
00771       // Mark effective beginning of when frame pointer is ready.
00772       unsigned Reg = MRI->getDwarfRegNum(FPReg, true);
00773       unsigned CFIIndex = MMI.addFrameInst(
00774           MCCFIInstruction::createDefCfaRegister(nullptr, Reg));
00775 
00776       BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
00777           .addCFIIndex(CFIIndex);
00778     }
00779   }
00780 
00781   if (needsFrameMoves) {
00782     // Add callee saved registers to move list.
00783     const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
00784     for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
00785       unsigned Reg = CSI[I].getReg();
00786       if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue;
00787 
00788       // This is a bit of a hack: CR2LT, CR2GT, CR2EQ and CR2UN are just
00789       // subregisters of CR2. We just need to emit a move of CR2.
00790       if (PPC::CRBITRCRegClass.contains(Reg))
00791         continue;
00792 
00793       // For SVR4, don't emit a move for the CR spill slot if we haven't
00794       // spilled CRs.
00795       if (isSVR4ABI && (PPC::CR2 <= Reg && Reg <= PPC::CR4)
00796           && MustSaveCRs.empty())
00797         continue;
00798 
00799       // For 64-bit SVR4 when we have spilled CRs, the spill location
00800       // is SP+8, not a frame-relative slot.
00801       if (isSVR4ABI && isPPC64 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
00802         // In the ELFv1 ABI, only CR2 is noted in CFI and stands in for
00803         // the whole CR word.  In the ELFv2 ABI, every CR that was
00804         // actually saved gets its own CFI record.
00805         unsigned CRReg = isELFv2ABI? Reg : (unsigned) PPC::CR2;
00806         unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
00807             nullptr, MRI->getDwarfRegNum(CRReg, true), 8));
00808         BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
00809             .addCFIIndex(CFIIndex);
00810         continue;
00811       }
00812 
00813       int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
00814       unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
00815           nullptr, MRI->getDwarfRegNum(Reg, true), Offset));
00816       BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
00817           .addCFIIndex(CFIIndex);
00818     }
00819   }
00820 }
00821 
00822 void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
00823                                 MachineBasicBlock &MBB) const {
00824   MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
00825   assert(MBBI != MBB.end() && "Returning block has no terminator");
00826   const PPCInstrInfo &TII =
00827     *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo());
00828   const PPCRegisterInfo *RegInfo =
00829     static_cast<const PPCRegisterInfo*>(MF.getTarget().getRegisterInfo());
00830 
00831   unsigned RetOpcode = MBBI->getOpcode();
00832   DebugLoc dl;
00833 
00834   assert((RetOpcode == PPC::BLR ||
00835           RetOpcode == PPC::TCRETURNri ||
00836           RetOpcode == PPC::TCRETURNdi ||
00837           RetOpcode == PPC::TCRETURNai ||
00838           RetOpcode == PPC::TCRETURNri8 ||
00839           RetOpcode == PPC::TCRETURNdi8 ||
00840           RetOpcode == PPC::TCRETURNai8) &&
00841          "Can only insert epilog into returning blocks");
00842 
00843   // Get alignment info so we know how to restore the SP.
00844   const MachineFrameInfo *MFI = MF.getFrameInfo();
00845 
00846   // Get the number of bytes allocated from the FrameInfo.
00847   int FrameSize = MFI->getStackSize();
00848 
00849   // Get processor type.
00850   bool isPPC64 = Subtarget.isPPC64();
00851   // Get the ABI.
00852   bool isDarwinABI = Subtarget.isDarwinABI();
00853   bool isSVR4ABI = Subtarget.isSVR4ABI();
00854   bool isPIC = MF.getTarget().getRelocationModel() == Reloc::PIC_;
00855 
00856   // Check if the link register (LR) has been saved.
00857   PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
00858   bool MustSaveLR = FI->mustSaveLR();
00859   const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs();
00860   // Do we have a frame pointer and/or base pointer for this function?
00861   bool HasFP = hasFP(MF);
00862   bool HasBP = RegInfo->hasBasePointer(MF);
00863 
00864   unsigned SPReg      = isPPC64 ? PPC::X1  : PPC::R1;
00865   unsigned BPReg      = RegInfo->getBaseRegister(MF);
00866   unsigned FPReg      = isPPC64 ? PPC::X31 : PPC::R31;
00867   unsigned ScratchReg  = isPPC64 ? PPC::X0  : PPC::R0;
00868   unsigned TempReg     = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
00869   const MCInstrDesc& MTLRInst = TII.get( isPPC64 ? PPC::MTLR8
00870                                                  : PPC::MTLR );
00871   const MCInstrDesc& LoadInst = TII.get( isPPC64 ? PPC::LD
00872                                                  : PPC::LWZ );
00873   const MCInstrDesc& LoadImmShiftedInst = TII.get( isPPC64 ? PPC::LIS8
00874                                                            : PPC::LIS );
00875   const MCInstrDesc& OrImmInst = TII.get( isPPC64 ? PPC::ORI8
00876                                                   : PPC::ORI );
00877   const MCInstrDesc& AddImmInst = TII.get( isPPC64 ? PPC::ADDI8
00878                                                    : PPC::ADDI );
00879   const MCInstrDesc& AddInst = TII.get( isPPC64 ? PPC::ADD8
00880                                                 : PPC::ADD4 );
00881 
00882   int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
00883 
00884   int FPOffset = 0;
00885   if (HasFP) {
00886     if (isSVR4ABI) {
00887       MachineFrameInfo *FFI = MF.getFrameInfo();
00888       int FPIndex = FI->getFramePointerSaveIndex();
00889       assert(FPIndex && "No Frame Pointer Save Slot!");
00890       FPOffset = FFI->getObjectOffset(FPIndex);
00891     } else {
00892       FPOffset =
00893           PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
00894     }
00895   }
00896 
00897   int BPOffset = 0;
00898   if (HasBP) {
00899     if (isSVR4ABI) {
00900       MachineFrameInfo *FFI = MF.getFrameInfo();
00901       int BPIndex = FI->getBasePointerSaveIndex();
00902       assert(BPIndex && "No Base Pointer Save Slot!");
00903       BPOffset = FFI->getObjectOffset(BPIndex);
00904     } else {
00905       BPOffset =
00906         PPCFrameLowering::getBasePointerSaveOffset(isPPC64,
00907                                                    isDarwinABI,
00908                                                    isPIC);
00909     }
00910   }
00911 
00912   bool UsesTCRet =  RetOpcode == PPC::TCRETURNri ||
00913     RetOpcode == PPC::TCRETURNdi ||
00914     RetOpcode == PPC::TCRETURNai ||
00915     RetOpcode == PPC::TCRETURNri8 ||
00916     RetOpcode == PPC::TCRETURNdi8 ||
00917     RetOpcode == PPC::TCRETURNai8;
00918 
00919   if (UsesTCRet) {
00920     int MaxTCRetDelta = FI->getTailCallSPDelta();
00921     MachineOperand &StackAdjust = MBBI->getOperand(1);
00922     assert(StackAdjust.isImm() && "Expecting immediate value.");
00923     // Adjust stack pointer.
00924     int StackAdj = StackAdjust.getImm();
00925     int Delta = StackAdj - MaxTCRetDelta;
00926     assert((Delta >= 0) && "Delta must be positive");
00927     if (MaxTCRetDelta>0)
00928       FrameSize += (StackAdj +Delta);
00929     else
00930       FrameSize += StackAdj;
00931   }
00932 
00933   // Frames of 32KB & larger require special handling because they cannot be
00934   // indexed into with a simple LD/LWZ immediate offset operand.
00935   bool isLargeFrame = !isInt<16>(FrameSize);
00936 
00937   if (FrameSize) {
00938     // In the prologue, the loaded (or persistent) stack pointer value is offset
00939     // by the STDU/STDUX/STWU/STWUX instruction.  Add this offset back now.
00940 
00941     // If this function contained a fastcc call and GuaranteedTailCallOpt is
00942     // enabled (=> hasFastCall()==true) the fastcc call might contain a tail
00943     // call which invalidates the stack pointer value in SP(0). So we use the
00944     // value of R31 in this case.
00945     if (FI->hasFastCall()) {
00946       assert(HasFP && "Expecting a valid frame pointer.");
00947       if (!isLargeFrame) {
00948         BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
00949           .addReg(FPReg).addImm(FrameSize);
00950       } else {
00951         BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
00952           .addImm(FrameSize >> 16);
00953         BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
00954           .addReg(ScratchReg, RegState::Kill)
00955           .addImm(FrameSize & 0xFFFF);
00956         BuildMI(MBB, MBBI, dl, AddInst)
00957           .addReg(SPReg)
00958           .addReg(FPReg)
00959           .addReg(ScratchReg);
00960       }
00961     } else if (!isLargeFrame && !HasBP && !MFI->hasVarSizedObjects()) {
00962       BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
00963         .addReg(SPReg)
00964         .addImm(FrameSize);
00965     } else {
00966       BuildMI(MBB, MBBI, dl, LoadInst, SPReg)
00967         .addImm(0)
00968         .addReg(SPReg);
00969     }
00970 
00971   }
00972 
00973   if (MustSaveLR)
00974     BuildMI(MBB, MBBI, dl, LoadInst, ScratchReg)
00975       .addImm(LROffset)
00976       .addReg(SPReg);
00977 
00978   assert((isPPC64 || MustSaveCRs.empty()) &&
00979          "Epilogue CR restoring supported only in 64-bit mode");
00980 
00981   if (!MustSaveCRs.empty()) // will only occur for PPC64
00982     BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg)
00983       .addImm(8)
00984       .addReg(SPReg);
00985 
00986   if (HasFP)
00987     BuildMI(MBB, MBBI, dl, LoadInst, FPReg)
00988       .addImm(FPOffset)
00989       .addReg(SPReg);
00990 
00991   if (HasBP)
00992     BuildMI(MBB, MBBI, dl, LoadInst, BPReg)
00993       .addImm(BPOffset)
00994       .addReg(SPReg);
00995 
00996   if (!MustSaveCRs.empty()) // will only occur for PPC64
00997     for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
00998       BuildMI(MBB, MBBI, dl, TII.get(PPC::MTOCRF8), MustSaveCRs[i])
00999         .addReg(TempReg, getKillRegState(i == e-1));
01000 
01001   if (MustSaveLR)
01002     BuildMI(MBB, MBBI, dl, MTLRInst).addReg(ScratchReg);
01003 
01004   // Callee pop calling convention. Pop parameter/linkage area. Used for tail
01005   // call optimization
01006   if (MF.getTarget().Options.GuaranteedTailCallOpt && RetOpcode == PPC::BLR &&
01007       MF.getFunction()->getCallingConv() == CallingConv::Fast) {
01008      PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
01009      unsigned CallerAllocatedAmt = FI->getMinReservedArea();
01010 
01011      if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) {
01012        BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
01013          .addReg(SPReg).addImm(CallerAllocatedAmt);
01014      } else {
01015        BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
01016           .addImm(CallerAllocatedAmt >> 16);
01017        BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
01018           .addReg(ScratchReg, RegState::Kill)
01019           .addImm(CallerAllocatedAmt & 0xFFFF);
01020        BuildMI(MBB, MBBI, dl, AddInst)
01021           .addReg(SPReg)
01022           .addReg(FPReg)
01023           .addReg(ScratchReg);
01024      }
01025   } else if (RetOpcode == PPC::TCRETURNdi) {
01026     MBBI = MBB.getLastNonDebugInstr();
01027     MachineOperand &JumpTarget = MBBI->getOperand(0);
01028     BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)).
01029       addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
01030   } else if (RetOpcode == PPC::TCRETURNri) {
01031     MBBI = MBB.getLastNonDebugInstr();
01032     assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
01033     BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR));
01034   } else if (RetOpcode == PPC::TCRETURNai) {
01035     MBBI = MBB.getLastNonDebugInstr();
01036     MachineOperand &JumpTarget = MBBI->getOperand(0);
01037     BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm());
01038   } else if (RetOpcode == PPC::TCRETURNdi8) {
01039     MBBI = MBB.getLastNonDebugInstr();
01040     MachineOperand &JumpTarget = MBBI->getOperand(0);
01041     BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)).
01042       addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
01043   } else if (RetOpcode == PPC::TCRETURNri8) {
01044     MBBI = MBB.getLastNonDebugInstr();
01045     assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
01046     BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8));
01047   } else if (RetOpcode == PPC::TCRETURNai8) {
01048     MBBI = MBB.getLastNonDebugInstr();
01049     MachineOperand &JumpTarget = MBBI->getOperand(0);
01050     BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm());
01051   }
01052 }
01053 
01054 /// MustSaveLR - Return true if this function requires that we save the LR
01055 /// register onto the stack in the prolog and restore it in the epilog of the
01056 /// function.
01057 static bool MustSaveLR(const MachineFunction &MF, unsigned LR) {
01058   const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>();
01059 
01060   // We need a save/restore of LR if there is any def of LR (which is
01061   // defined by calls, including the PIC setup sequence), or if there is
01062   // some use of the LR stack slot (e.g. for builtin_return_address).
01063   // (LR comes in 32 and 64 bit versions.)
01064   MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR);
01065   return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired();
01066 }
01067 
01068 void
01069 PPCFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
01070                                                    RegScavenger *) const {
01071   const PPCRegisterInfo *RegInfo =
01072     static_cast<const PPCRegisterInfo*>(MF.getTarget().getRegisterInfo());
01073 
01074   //  Save and clear the LR state.
01075   PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
01076   unsigned LR = RegInfo->getRARegister();
01077   FI->setMustSaveLR(MustSaveLR(MF, LR));
01078   MachineRegisterInfo &MRI = MF.getRegInfo();
01079   MRI.setPhysRegUnused(LR);
01080 
01081   //  Save R31 if necessary
01082   int FPSI = FI->getFramePointerSaveIndex();
01083   bool isPPC64 = Subtarget.isPPC64();
01084   bool isDarwinABI  = Subtarget.isDarwinABI();
01085   bool isPIC = MF.getTarget().getRelocationModel() == Reloc::PIC_;
01086   MachineFrameInfo *MFI = MF.getFrameInfo();
01087 
01088   // If the frame pointer save index hasn't been defined yet.
01089   if (!FPSI && needsFP(MF)) {
01090     // Find out what the fix offset of the frame pointer save area.
01091     int FPOffset = getFramePointerSaveOffset(isPPC64, isDarwinABI);
01092     // Allocate the frame index for frame pointer save area.
01093     FPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
01094     // Save the result.
01095     FI->setFramePointerSaveIndex(FPSI);
01096   }
01097 
01098   int BPSI = FI->getBasePointerSaveIndex();
01099   if (!BPSI && RegInfo->hasBasePointer(MF)) {
01100     int BPOffset = getBasePointerSaveOffset(isPPC64, isDarwinABI, isPIC);
01101     // Allocate the frame index for the base pointer save area.
01102     BPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, BPOffset, true);
01103     // Save the result.
01104     FI->setBasePointerSaveIndex(BPSI);
01105   }
01106 
01107   // Reserve stack space to move the linkage area to in case of a tail call.
01108   int TCSPDelta = 0;
01109   if (MF.getTarget().Options.GuaranteedTailCallOpt &&
01110       (TCSPDelta = FI->getTailCallSPDelta()) < 0) {
01111     MFI->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true);
01112   }
01113 
01114   // For 32-bit SVR4, allocate the nonvolatile CR spill slot iff the
01115   // function uses CR 2, 3, or 4.
01116   if (!isPPC64 && !isDarwinABI &&
01117       (MRI.isPhysRegUsed(PPC::CR2) ||
01118        MRI.isPhysRegUsed(PPC::CR3) ||
01119        MRI.isPhysRegUsed(PPC::CR4))) {
01120     int FrameIdx = MFI->CreateFixedObject((uint64_t)4, (int64_t)-4, true);
01121     FI->setCRSpillFrameIndex(FrameIdx);
01122   }
01123 }
01124 
01125 void PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF,
01126                                                        RegScavenger *RS) const {
01127   // Early exit if not using the SVR4 ABI.
01128   if (!Subtarget.isSVR4ABI()) {
01129     addScavengingSpillSlot(MF, RS);
01130     return;
01131   }
01132 
01133   // Get callee saved register information.
01134   MachineFrameInfo *FFI = MF.getFrameInfo();
01135   const std::vector<CalleeSavedInfo> &CSI = FFI->getCalleeSavedInfo();
01136 
01137   // Early exit if no callee saved registers are modified!
01138   if (CSI.empty() && !needsFP(MF)) {
01139     addScavengingSpillSlot(MF, RS);
01140     return;
01141   }
01142 
01143   unsigned MinGPR = PPC::R31;
01144   unsigned MinG8R = PPC::X31;
01145   unsigned MinFPR = PPC::F31;
01146   unsigned MinVR = PPC::V31;
01147 
01148   bool HasGPSaveArea = false;
01149   bool HasG8SaveArea = false;
01150   bool HasFPSaveArea = false;
01151   bool HasVRSAVESaveArea = false;
01152   bool HasVRSaveArea = false;
01153 
01154   SmallVector<CalleeSavedInfo, 18> GPRegs;
01155   SmallVector<CalleeSavedInfo, 18> G8Regs;
01156   SmallVector<CalleeSavedInfo, 18> FPRegs;
01157   SmallVector<CalleeSavedInfo, 18> VRegs;
01158 
01159   for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
01160     unsigned Reg = CSI[i].getReg();
01161     if (PPC::GPRCRegClass.contains(Reg)) {
01162       HasGPSaveArea = true;
01163 
01164       GPRegs.push_back(CSI[i]);
01165 
01166       if (Reg < MinGPR) {
01167         MinGPR = Reg;
01168       }
01169     } else if (PPC::G8RCRegClass.contains(Reg)) {
01170       HasG8SaveArea = true;
01171 
01172       G8Regs.push_back(CSI[i]);
01173 
01174       if (Reg < MinG8R) {
01175         MinG8R = Reg;
01176       }
01177     } else if (PPC::F8RCRegClass.contains(Reg)) {
01178       HasFPSaveArea = true;
01179 
01180       FPRegs.push_back(CSI[i]);
01181 
01182       if (Reg < MinFPR) {
01183         MinFPR = Reg;
01184       }
01185     } else if (PPC::CRBITRCRegClass.contains(Reg) ||
01186                PPC::CRRCRegClass.contains(Reg)) {
01187       ; // do nothing, as we already know whether CRs are spilled
01188     } else if (PPC::VRSAVERCRegClass.contains(Reg)) {
01189       HasVRSAVESaveArea = true;
01190     } else if (PPC::VRRCRegClass.contains(Reg)) {
01191       HasVRSaveArea = true;
01192 
01193       VRegs.push_back(CSI[i]);
01194 
01195       if (Reg < MinVR) {
01196         MinVR = Reg;
01197       }
01198     } else {
01199       llvm_unreachable("Unknown RegisterClass!");
01200     }
01201   }
01202 
01203   PPCFunctionInfo *PFI = MF.getInfo<PPCFunctionInfo>();
01204   const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
01205 
01206   int64_t LowerBound = 0;
01207 
01208   // Take into account stack space reserved for tail calls.
01209   int TCSPDelta = 0;
01210   if (MF.getTarget().Options.GuaranteedTailCallOpt &&
01211       (TCSPDelta = PFI->getTailCallSPDelta()) < 0) {
01212     LowerBound = TCSPDelta;
01213   }
01214 
01215   // The Floating-point register save area is right below the back chain word
01216   // of the previous stack frame.
01217   if (HasFPSaveArea) {
01218     for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) {
01219       int FI = FPRegs[i].getFrameIdx();
01220 
01221       FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
01222     }
01223 
01224     LowerBound -= (31 - TRI->getEncodingValue(MinFPR) + 1) * 8;
01225   }
01226 
01227   // Check whether the frame pointer register is allocated. If so, make sure it
01228   // is spilled to the correct offset.
01229   if (needsFP(MF)) {
01230     HasGPSaveArea = true;
01231 
01232     int FI = PFI->getFramePointerSaveIndex();
01233     assert(FI && "No Frame Pointer Save Slot!");
01234 
01235     FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
01236   }
01237 
01238   const PPCRegisterInfo *RegInfo =
01239     static_cast<const PPCRegisterInfo*>(MF.getTarget().getRegisterInfo());
01240   if (RegInfo->hasBasePointer(MF)) {
01241     HasGPSaveArea = true;
01242 
01243     int FI = PFI->getBasePointerSaveIndex();
01244     assert(FI && "No Base Pointer Save Slot!");
01245 
01246     FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
01247   }
01248 
01249   // General register save area starts right below the Floating-point
01250   // register save area.
01251   if (HasGPSaveArea || HasG8SaveArea) {
01252     // Move general register save area spill slots down, taking into account
01253     // the size of the Floating-point register save area.
01254     for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) {
01255       int FI = GPRegs[i].getFrameIdx();
01256 
01257       FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
01258     }
01259 
01260     // Move general register save area spill slots down, taking into account
01261     // the size of the Floating-point register save area.
01262     for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) {
01263       int FI = G8Regs[i].getFrameIdx();
01264 
01265       FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
01266     }
01267 
01268     unsigned MinReg =
01269       std::min<unsigned>(TRI->getEncodingValue(MinGPR),
01270                          TRI->getEncodingValue(MinG8R));
01271 
01272     if (Subtarget.isPPC64()) {
01273       LowerBound -= (31 - MinReg + 1) * 8;
01274     } else {
01275       LowerBound -= (31 - MinReg + 1) * 4;
01276     }
01277   }
01278 
01279   // For 32-bit only, the CR save area is below the general register
01280   // save area.  For 64-bit SVR4, the CR save area is addressed relative
01281   // to the stack pointer and hence does not need an adjustment here.
01282   // Only CR2 (the first nonvolatile spilled) has an associated frame
01283   // index so that we have a single uniform save area.
01284   if (spillsCR(MF) && !(Subtarget.isPPC64() && Subtarget.isSVR4ABI())) {
01285     // Adjust the frame index of the CR spill slot.
01286     for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
01287       unsigned Reg = CSI[i].getReg();
01288 
01289       if ((Subtarget.isSVR4ABI() && Reg == PPC::CR2)
01290           // Leave Darwin logic as-is.
01291           || (!Subtarget.isSVR4ABI() &&
01292               (PPC::CRBITRCRegClass.contains(Reg) ||
01293                PPC::CRRCRegClass.contains(Reg)))) {
01294         int FI = CSI[i].getFrameIdx();
01295 
01296         FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
01297       }
01298     }
01299 
01300     LowerBound -= 4; // The CR save area is always 4 bytes long.
01301   }
01302 
01303   if (HasVRSAVESaveArea) {
01304     // FIXME SVR4: Is it actually possible to have multiple elements in CSI
01305     //             which have the VRSAVE register class?
01306     // Adjust the frame index of the VRSAVE spill slot.
01307     for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
01308       unsigned Reg = CSI[i].getReg();
01309 
01310       if (PPC::VRSAVERCRegClass.contains(Reg)) {
01311         int FI = CSI[i].getFrameIdx();
01312 
01313         FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
01314       }
01315     }
01316 
01317     LowerBound -= 4; // The VRSAVE save area is always 4 bytes long.
01318   }
01319 
01320   if (HasVRSaveArea) {
01321     // Insert alignment padding, we need 16-byte alignment.
01322     LowerBound = (LowerBound - 15) & ~(15);
01323 
01324     for (unsigned i = 0, e = VRegs.size(); i != e; ++i) {
01325       int FI = VRegs[i].getFrameIdx();
01326 
01327       FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
01328     }
01329   }
01330 
01331   addScavengingSpillSlot(MF, RS);
01332 }
01333 
01334 void
01335 PPCFrameLowering::addScavengingSpillSlot(MachineFunction &MF,
01336                                          RegScavenger *RS) const {
01337   // Reserve a slot closest to SP or frame pointer if we have a dynalloc or
01338   // a large stack, which will require scavenging a register to materialize a
01339   // large offset.
01340 
01341   // We need to have a scavenger spill slot for spills if the frame size is
01342   // large. In case there is no free register for large-offset addressing,
01343   // this slot is used for the necessary emergency spill. Also, we need the
01344   // slot for dynamic stack allocations.
01345 
01346   // The scavenger might be invoked if the frame offset does not fit into
01347   // the 16-bit immediate. We don't know the complete frame size here
01348   // because we've not yet computed callee-saved register spills or the
01349   // needed alignment padding.
01350   unsigned StackSize = determineFrameLayout(MF, false, true);
01351   MachineFrameInfo *MFI = MF.getFrameInfo();
01352   if (MFI->hasVarSizedObjects() || spillsCR(MF) || spillsVRSAVE(MF) ||
01353       hasNonRISpills(MF) || (hasSpills(MF) && !isInt<16>(StackSize))) {
01354     const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
01355     const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
01356     const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC;
01357     RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
01358                                                        RC->getAlignment(),
01359                                                        false));
01360 
01361     // Might we have over-aligned allocas?
01362     bool HasAlVars = MFI->hasVarSizedObjects() &&
01363                      MFI->getMaxAlignment() > getStackAlignment();
01364 
01365     // These kinds of spills might need two registers.
01366     if (spillsCR(MF) || spillsVRSAVE(MF) || HasAlVars)
01367       RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
01368                                                          RC->getAlignment(),
01369                                                          false));
01370 
01371   }
01372 }
01373 
01374 bool
01375 PPCFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
01376                                      MachineBasicBlock::iterator MI,
01377                                      const std::vector<CalleeSavedInfo> &CSI,
01378                                      const TargetRegisterInfo *TRI) const {
01379 
01380   // Currently, this function only handles SVR4 32- and 64-bit ABIs.
01381   // Return false otherwise to maintain pre-existing behavior.
01382   if (!Subtarget.isSVR4ABI())
01383     return false;
01384 
01385   MachineFunction *MF = MBB.getParent();
01386   const PPCInstrInfo &TII =
01387     *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo());
01388   DebugLoc DL;
01389   bool CRSpilled = false;
01390   MachineInstrBuilder CRMIB;
01391 
01392   for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
01393     unsigned Reg = CSI[i].getReg();
01394     // Only Darwin actually uses the VRSAVE register, but it can still appear
01395     // here if, for example, @llvm.eh.unwind.init() is used.  If we're not on
01396     // Darwin, ignore it.
01397     if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI())
01398       continue;
01399 
01400     // CR2 through CR4 are the nonvolatile CR fields.
01401     bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4;
01402 
01403     // Add the callee-saved register as live-in; it's killed at the spill.
01404     MBB.addLiveIn(Reg);
01405 
01406     if (CRSpilled && IsCRField) {
01407       CRMIB.addReg(Reg, RegState::ImplicitKill);
01408       continue;
01409     }
01410 
01411     // Insert the spill to the stack frame.
01412     if (IsCRField) {
01413       PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>();
01414       if (Subtarget.isPPC64()) {
01415         // The actual spill will happen at the start of the prologue.
01416         FuncInfo->addMustSaveCR(Reg);
01417       } else {
01418         CRSpilled = true;
01419         FuncInfo->setSpillsCR();
01420 
01421         // 32-bit:  FP-relative.  Note that we made sure CR2-CR4 all have
01422         // the same frame index in PPCRegisterInfo::hasReservedSpillSlot.
01423         CRMIB = BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12)
01424                   .addReg(Reg, RegState::ImplicitKill);
01425 
01426         MBB.insert(MI, CRMIB);
01427         MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::STW))
01428                                          .addReg(PPC::R12,
01429                                                  getKillRegState(true)),
01430                                          CSI[i].getFrameIdx()));
01431       }
01432     } else {
01433       const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
01434       TII.storeRegToStackSlot(MBB, MI, Reg, true,
01435                               CSI[i].getFrameIdx(), RC, TRI);
01436     }
01437   }
01438   return true;
01439 }
01440 
01441 static void
01442 restoreCRs(bool isPPC64, bool is31,
01443            bool CR2Spilled, bool CR3Spilled, bool CR4Spilled,
01444            MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
01445            const std::vector<CalleeSavedInfo> &CSI, unsigned CSIIndex) {
01446 
01447   MachineFunction *MF = MBB.getParent();
01448   const PPCInstrInfo &TII =
01449     *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo());
01450   DebugLoc DL;
01451   unsigned RestoreOp, MoveReg;
01452 
01453   if (isPPC64)
01454     // This is handled during epilogue generation.
01455     return;
01456   else {
01457     // 32-bit:  FP-relative
01458     MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::LWZ),
01459                                              PPC::R12),
01460                                      CSI[CSIIndex].getFrameIdx()));
01461     RestoreOp = PPC::MTOCRF;
01462     MoveReg = PPC::R12;
01463   }
01464 
01465   if (CR2Spilled)
01466     MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR2)
01467                .addReg(MoveReg, getKillRegState(!CR3Spilled && !CR4Spilled)));
01468 
01469   if (CR3Spilled)
01470     MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR3)
01471                .addReg(MoveReg, getKillRegState(!CR4Spilled)));
01472 
01473   if (CR4Spilled)
01474     MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR4)
01475                .addReg(MoveReg, getKillRegState(true)));
01476 }
01477 
01478 void PPCFrameLowering::
01479 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
01480                               MachineBasicBlock::iterator I) const {
01481   const PPCInstrInfo &TII =
01482     *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo());
01483   if (MF.getTarget().Options.GuaranteedTailCallOpt &&
01484       I->getOpcode() == PPC::ADJCALLSTACKUP) {
01485     // Add (actually subtract) back the amount the callee popped on return.
01486     if (int CalleeAmt =  I->getOperand(1).getImm()) {
01487       bool is64Bit = Subtarget.isPPC64();
01488       CalleeAmt *= -1;
01489       unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1;
01490       unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0;
01491       unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI;
01492       unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4;
01493       unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS;
01494       unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI;
01495       MachineInstr *MI = I;
01496       DebugLoc dl = MI->getDebugLoc();
01497 
01498       if (isInt<16>(CalleeAmt)) {
01499         BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg)
01500           .addReg(StackReg, RegState::Kill)
01501           .addImm(CalleeAmt);
01502       } else {
01503         MachineBasicBlock::iterator MBBI = I;
01504         BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
01505           .addImm(CalleeAmt >> 16);
01506         BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
01507           .addReg(TmpReg, RegState::Kill)
01508           .addImm(CalleeAmt & 0xFFFF);
01509         BuildMI(MBB, MBBI, dl, TII.get(ADDInstr), StackReg)
01510           .addReg(StackReg, RegState::Kill)
01511           .addReg(TmpReg);
01512       }
01513     }
01514   }
01515   // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
01516   MBB.erase(I);
01517 }
01518 
01519 bool
01520 PPCFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
01521                                         MachineBasicBlock::iterator MI,
01522                                         const std::vector<CalleeSavedInfo> &CSI,
01523                                         const TargetRegisterInfo *TRI) const {
01524 
01525   // Currently, this function only handles SVR4 32- and 64-bit ABIs.
01526   // Return false otherwise to maintain pre-existing behavior.
01527   if (!Subtarget.isSVR4ABI())
01528     return false;
01529 
01530   MachineFunction *MF = MBB.getParent();
01531   const PPCInstrInfo &TII =
01532     *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo());
01533   bool CR2Spilled = false;
01534   bool CR3Spilled = false;
01535   bool CR4Spilled = false;
01536   unsigned CSIIndex = 0;
01537 
01538   // Initialize insertion-point logic; we will be restoring in reverse
01539   // order of spill.
01540   MachineBasicBlock::iterator I = MI, BeforeI = I;
01541   bool AtStart = I == MBB.begin();
01542 
01543   if (!AtStart)
01544     --BeforeI;
01545 
01546   for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
01547     unsigned Reg = CSI[i].getReg();
01548 
01549     // Only Darwin actually uses the VRSAVE register, but it can still appear
01550     // here if, for example, @llvm.eh.unwind.init() is used.  If we're not on
01551     // Darwin, ignore it.
01552     if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI())
01553       continue;
01554 
01555     if (Reg == PPC::CR2) {
01556       CR2Spilled = true;
01557       // The spill slot is associated only with CR2, which is the
01558       // first nonvolatile spilled.  Save it here.
01559       CSIIndex = i;
01560       continue;
01561     } else if (Reg == PPC::CR3) {
01562       CR3Spilled = true;
01563       continue;
01564     } else if (Reg == PPC::CR4) {
01565       CR4Spilled = true;
01566       continue;
01567     } else {
01568       // When we first encounter a non-CR register after seeing at
01569       // least one CR register, restore all spilled CRs together.
01570       if ((CR2Spilled || CR3Spilled || CR4Spilled)
01571           && !(PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
01572         bool is31 = needsFP(*MF);
01573         restoreCRs(Subtarget.isPPC64(), is31,
01574                    CR2Spilled, CR3Spilled, CR4Spilled,
01575                    MBB, I, CSI, CSIIndex);
01576         CR2Spilled = CR3Spilled = CR4Spilled = false;
01577       }
01578 
01579       // Default behavior for non-CR saves.
01580       const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
01581       TII.loadRegFromStackSlot(MBB, I, Reg, CSI[i].getFrameIdx(),
01582                                RC, TRI);
01583       assert(I != MBB.begin() &&
01584              "loadRegFromStackSlot didn't insert any code!");
01585       }
01586 
01587     // Insert in reverse order.
01588     if (AtStart)
01589       I = MBB.begin();
01590     else {
01591       I = BeforeI;
01592       ++I;
01593     }
01594   }
01595 
01596   // If we haven't yet spilled the CRs, do so now.
01597   if (CR2Spilled || CR3Spilled || CR4Spilled) {
01598     bool is31 = needsFP(*MF);
01599     restoreCRs(Subtarget.isPPC64(), is31, CR2Spilled, CR3Spilled, CR4Spilled,
01600                MBB, I, CSI, CSIIndex);
01601   }
01602 
01603   return true;
01604 }