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PPCFrameLowering.cpp
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00001 //===-- PPCFrameLowering.cpp - PPC Frame Information ----------------------===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file contains the PPC implementation of TargetFrameLowering class.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #include "PPCFrameLowering.h"
00015 #include "PPCInstrBuilder.h"
00016 #include "PPCInstrInfo.h"
00017 #include "PPCMachineFunctionInfo.h"
00018 #include "PPCSubtarget.h"
00019 #include "PPCTargetMachine.h"
00020 #include "llvm/CodeGen/MachineFrameInfo.h"
00021 #include "llvm/CodeGen/MachineFunction.h"
00022 #include "llvm/CodeGen/MachineInstrBuilder.h"
00023 #include "llvm/CodeGen/MachineModuleInfo.h"
00024 #include "llvm/CodeGen/MachineRegisterInfo.h"
00025 #include "llvm/CodeGen/RegisterScavenging.h"
00026 #include "llvm/IR/Function.h"
00027 #include "llvm/Target/TargetOptions.h"
00028 
00029 using namespace llvm;
00030 
00031 /// VRRegNo - Map from a numbered VR register to its enum value.
00032 ///
00033 static const uint16_t VRRegNo[] = {
00034  PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
00035  PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
00036  PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
00037  PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
00038 };
00039 
00040 static unsigned computeReturnSaveOffset(const PPCSubtarget &STI) {
00041   if (STI.isDarwinABI())
00042     return STI.isPPC64() ? 16 : 8;
00043   // SVR4 ABI:
00044   return STI.isPPC64() ? 16 : 4;
00045 }
00046 
00047 static unsigned computeTOCSaveOffset(const PPCSubtarget &STI) {
00048   return STI.isELFv2ABI() ? 24 : 40;
00049 }
00050 
00051 static unsigned computeFramePointerSaveOffset(const PPCSubtarget &STI) {
00052   // For the Darwin ABI:
00053   // We cannot use the TOC save slot (offset +20) in the PowerPC linkage area
00054   // for saving the frame pointer (if needed.)  While the published ABI has
00055   // not used this slot since at least MacOSX 10.2, there is older code
00056   // around that does use it, and that needs to continue to work.
00057   if (STI.isDarwinABI())
00058     return STI.isPPC64() ? -8U : -4U;
00059 
00060   // SVR4 ABI: First slot in the general register save area.
00061   return STI.isPPC64() ? -8U : -4U;
00062 }
00063 
00064 static unsigned computeLinkageSize(const PPCSubtarget &STI) {
00065   if (STI.isDarwinABI() || STI.isPPC64())
00066     return (STI.isELFv2ABI() ? 4 : 6) * (STI.isPPC64() ? 8 : 4);
00067 
00068   // SVR4 ABI:
00069   return 8;
00070 }
00071 
00072 static unsigned computeBasePointerSaveOffset(const PPCSubtarget &STI) {
00073   if (STI.isDarwinABI())
00074     return STI.isPPC64() ? -16U : -8U;
00075 
00076   // SVR4 ABI: First slot in the general register save area.
00077   return STI.isPPC64()
00078              ? -16U
00079              : (STI.getTargetMachine().getRelocationModel() == Reloc::PIC_)
00080                    ? -12U
00081                    : -8U;
00082 }
00083 
00084 PPCFrameLowering::PPCFrameLowering(const PPCSubtarget &STI)
00085     : TargetFrameLowering(TargetFrameLowering::StackGrowsDown,
00086                           STI.getPlatformStackAlignment(), 0),
00087       Subtarget(STI), ReturnSaveOffset(computeReturnSaveOffset(Subtarget)),
00088       TOCSaveOffset(computeTOCSaveOffset(Subtarget)),
00089       FramePointerSaveOffset(computeFramePointerSaveOffset(Subtarget)),
00090       LinkageSize(computeLinkageSize(Subtarget)),
00091       BasePointerSaveOffset(computeBasePointerSaveOffset(STI)) {}
00092 
00093 // With the SVR4 ABI, callee-saved registers have fixed offsets on the stack.
00094 const PPCFrameLowering::SpillSlot *PPCFrameLowering::getCalleeSavedSpillSlots(
00095     unsigned &NumEntries) const {
00096   if (Subtarget.isDarwinABI()) {
00097     NumEntries = 1;
00098     if (Subtarget.isPPC64()) {
00099       static const SpillSlot darwin64Offsets = {PPC::X31, -8};
00100       return &darwin64Offsets;
00101     } else {
00102       static const SpillSlot darwinOffsets = {PPC::R31, -4};
00103       return &darwinOffsets;
00104     }
00105   }
00106 
00107   // Early exit if not using the SVR4 ABI.
00108   if (!Subtarget.isSVR4ABI()) {
00109     NumEntries = 0;
00110     return nullptr;
00111   }
00112 
00113   // Note that the offsets here overlap, but this is fixed up in
00114   // processFunctionBeforeFrameFinalized.
00115 
00116   static const SpillSlot Offsets[] = {
00117       // Floating-point register save area offsets.
00118       {PPC::F31, -8},
00119       {PPC::F30, -16},
00120       {PPC::F29, -24},
00121       {PPC::F28, -32},
00122       {PPC::F27, -40},
00123       {PPC::F26, -48},
00124       {PPC::F25, -56},
00125       {PPC::F24, -64},
00126       {PPC::F23, -72},
00127       {PPC::F22, -80},
00128       {PPC::F21, -88},
00129       {PPC::F20, -96},
00130       {PPC::F19, -104},
00131       {PPC::F18, -112},
00132       {PPC::F17, -120},
00133       {PPC::F16, -128},
00134       {PPC::F15, -136},
00135       {PPC::F14, -144},
00136 
00137       // General register save area offsets.
00138       {PPC::R31, -4},
00139       {PPC::R30, -8},
00140       {PPC::R29, -12},
00141       {PPC::R28, -16},
00142       {PPC::R27, -20},
00143       {PPC::R26, -24},
00144       {PPC::R25, -28},
00145       {PPC::R24, -32},
00146       {PPC::R23, -36},
00147       {PPC::R22, -40},
00148       {PPC::R21, -44},
00149       {PPC::R20, -48},
00150       {PPC::R19, -52},
00151       {PPC::R18, -56},
00152       {PPC::R17, -60},
00153       {PPC::R16, -64},
00154       {PPC::R15, -68},
00155       {PPC::R14, -72},
00156 
00157       // CR save area offset.  We map each of the nonvolatile CR fields
00158       // to the slot for CR2, which is the first of the nonvolatile CR
00159       // fields to be assigned, so that we only allocate one save slot.
00160       // See PPCRegisterInfo::hasReservedSpillSlot() for more information.
00161       {PPC::CR2, -4},
00162 
00163       // VRSAVE save area offset.
00164       {PPC::VRSAVE, -4},
00165 
00166       // Vector register save area
00167       {PPC::V31, -16},
00168       {PPC::V30, -32},
00169       {PPC::V29, -48},
00170       {PPC::V28, -64},
00171       {PPC::V27, -80},
00172       {PPC::V26, -96},
00173       {PPC::V25, -112},
00174       {PPC::V24, -128},
00175       {PPC::V23, -144},
00176       {PPC::V22, -160},
00177       {PPC::V21, -176},
00178       {PPC::V20, -192}};
00179 
00180   static const SpillSlot Offsets64[] = {
00181       // Floating-point register save area offsets.
00182       {PPC::F31, -8},
00183       {PPC::F30, -16},
00184       {PPC::F29, -24},
00185       {PPC::F28, -32},
00186       {PPC::F27, -40},
00187       {PPC::F26, -48},
00188       {PPC::F25, -56},
00189       {PPC::F24, -64},
00190       {PPC::F23, -72},
00191       {PPC::F22, -80},
00192       {PPC::F21, -88},
00193       {PPC::F20, -96},
00194       {PPC::F19, -104},
00195       {PPC::F18, -112},
00196       {PPC::F17, -120},
00197       {PPC::F16, -128},
00198       {PPC::F15, -136},
00199       {PPC::F14, -144},
00200 
00201       // General register save area offsets.
00202       {PPC::X31, -8},
00203       {PPC::X30, -16},
00204       {PPC::X29, -24},
00205       {PPC::X28, -32},
00206       {PPC::X27, -40},
00207       {PPC::X26, -48},
00208       {PPC::X25, -56},
00209       {PPC::X24, -64},
00210       {PPC::X23, -72},
00211       {PPC::X22, -80},
00212       {PPC::X21, -88},
00213       {PPC::X20, -96},
00214       {PPC::X19, -104},
00215       {PPC::X18, -112},
00216       {PPC::X17, -120},
00217       {PPC::X16, -128},
00218       {PPC::X15, -136},
00219       {PPC::X14, -144},
00220 
00221       // VRSAVE save area offset.
00222       {PPC::VRSAVE, -4},
00223 
00224       // Vector register save area
00225       {PPC::V31, -16},
00226       {PPC::V30, -32},
00227       {PPC::V29, -48},
00228       {PPC::V28, -64},
00229       {PPC::V27, -80},
00230       {PPC::V26, -96},
00231       {PPC::V25, -112},
00232       {PPC::V24, -128},
00233       {PPC::V23, -144},
00234       {PPC::V22, -160},
00235       {PPC::V21, -176},
00236       {PPC::V20, -192}};
00237 
00238   if (Subtarget.isPPC64()) {
00239     NumEntries = array_lengthof(Offsets64);
00240 
00241     return Offsets64;
00242   } else {
00243     NumEntries = array_lengthof(Offsets);
00244 
00245     return Offsets;
00246   }
00247 }
00248 
00249 /// RemoveVRSaveCode - We have found that this function does not need any code
00250 /// to manipulate the VRSAVE register, even though it uses vector registers.
00251 /// This can happen when the only registers used are known to be live in or out
00252 /// of the function.  Remove all of the VRSAVE related code from the function.
00253 /// FIXME: The removal of the code results in a compile failure at -O0 when the
00254 /// function contains a function call, as the GPR containing original VRSAVE
00255 /// contents is spilled and reloaded around the call.  Without the prolog code,
00256 /// the spill instruction refers to an undefined register.  This code needs
00257 /// to account for all uses of that GPR.
00258 static void RemoveVRSaveCode(MachineInstr *MI) {
00259   MachineBasicBlock *Entry = MI->getParent();
00260   MachineFunction *MF = Entry->getParent();
00261 
00262   // We know that the MTVRSAVE instruction immediately follows MI.  Remove it.
00263   MachineBasicBlock::iterator MBBI = MI;
00264   ++MBBI;
00265   assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
00266   MBBI->eraseFromParent();
00267 
00268   bool RemovedAllMTVRSAVEs = true;
00269   // See if we can find and remove the MTVRSAVE instruction from all of the
00270   // epilog blocks.
00271   for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
00272     // If last instruction is a return instruction, add an epilogue
00273     if (!I->empty() && I->back().isReturn()) {
00274       bool FoundIt = false;
00275       for (MBBI = I->end(); MBBI != I->begin(); ) {
00276         --MBBI;
00277         if (MBBI->getOpcode() == PPC::MTVRSAVE) {
00278           MBBI->eraseFromParent();  // remove it.
00279           FoundIt = true;
00280           break;
00281         }
00282       }
00283       RemovedAllMTVRSAVEs &= FoundIt;
00284     }
00285   }
00286 
00287   // If we found and removed all MTVRSAVE instructions, remove the read of
00288   // VRSAVE as well.
00289   if (RemovedAllMTVRSAVEs) {
00290     MBBI = MI;
00291     assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?");
00292     --MBBI;
00293     assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
00294     MBBI->eraseFromParent();
00295   }
00296 
00297   // Finally, nuke the UPDATE_VRSAVE.
00298   MI->eraseFromParent();
00299 }
00300 
00301 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
00302 // instruction selector.  Based on the vector registers that have been used,
00303 // transform this into the appropriate ORI instruction.
00304 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) {
00305   MachineFunction *MF = MI->getParent()->getParent();
00306   const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
00307   DebugLoc dl = MI->getDebugLoc();
00308 
00309   unsigned UsedRegMask = 0;
00310   for (unsigned i = 0; i != 32; ++i)
00311     if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i]))
00312       UsedRegMask |= 1 << (31-i);
00313 
00314   // Live in and live out values already must be in the mask, so don't bother
00315   // marking them.
00316   for (MachineRegisterInfo::livein_iterator
00317        I = MF->getRegInfo().livein_begin(),
00318        E = MF->getRegInfo().livein_end(); I != E; ++I) {
00319     unsigned RegNo = TRI->getEncodingValue(I->first);
00320     if (VRRegNo[RegNo] == I->first)        // If this really is a vector reg.
00321       UsedRegMask &= ~(1 << (31-RegNo));   // Doesn't need to be marked.
00322   }
00323 
00324   // Live out registers appear as use operands on return instructions.
00325   for (MachineFunction::const_iterator BI = MF->begin(), BE = MF->end();
00326        UsedRegMask != 0 && BI != BE; ++BI) {
00327     const MachineBasicBlock &MBB = *BI;
00328     if (MBB.empty() || !MBB.back().isReturn())
00329       continue;
00330     const MachineInstr &Ret = MBB.back();
00331     for (unsigned I = 0, E = Ret.getNumOperands(); I != E; ++I) {
00332       const MachineOperand &MO = Ret.getOperand(I);
00333       if (!MO.isReg() || !PPC::VRRCRegClass.contains(MO.getReg()))
00334         continue;
00335       unsigned RegNo = TRI->getEncodingValue(MO.getReg());
00336       UsedRegMask &= ~(1 << (31-RegNo));
00337     }
00338   }
00339 
00340   // If no registers are used, turn this into a copy.
00341   if (UsedRegMask == 0) {
00342     // Remove all VRSAVE code.
00343     RemoveVRSaveCode(MI);
00344     return;
00345   }
00346 
00347   unsigned SrcReg = MI->getOperand(1).getReg();
00348   unsigned DstReg = MI->getOperand(0).getReg();
00349 
00350   if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
00351     if (DstReg != SrcReg)
00352       BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
00353         .addReg(SrcReg)
00354         .addImm(UsedRegMask);
00355     else
00356       BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
00357         .addReg(SrcReg, RegState::Kill)
00358         .addImm(UsedRegMask);
00359   } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
00360     if (DstReg != SrcReg)
00361       BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
00362         .addReg(SrcReg)
00363         .addImm(UsedRegMask >> 16);
00364     else
00365       BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
00366         .addReg(SrcReg, RegState::Kill)
00367         .addImm(UsedRegMask >> 16);
00368   } else {
00369     if (DstReg != SrcReg)
00370       BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
00371         .addReg(SrcReg)
00372         .addImm(UsedRegMask >> 16);
00373     else
00374       BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
00375         .addReg(SrcReg, RegState::Kill)
00376         .addImm(UsedRegMask >> 16);
00377 
00378     BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
00379       .addReg(DstReg, RegState::Kill)
00380       .addImm(UsedRegMask & 0xFFFF);
00381   }
00382 
00383   // Remove the old UPDATE_VRSAVE instruction.
00384   MI->eraseFromParent();
00385 }
00386 
00387 static bool spillsCR(const MachineFunction &MF) {
00388   const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
00389   return FuncInfo->isCRSpilled();
00390 }
00391 
00392 static bool spillsVRSAVE(const MachineFunction &MF) {
00393   const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
00394   return FuncInfo->isVRSAVESpilled();
00395 }
00396 
00397 static bool hasSpills(const MachineFunction &MF) {
00398   const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
00399   return FuncInfo->hasSpills();
00400 }
00401 
00402 static bool hasNonRISpills(const MachineFunction &MF) {
00403   const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
00404   return FuncInfo->hasNonRISpills();
00405 }
00406 
00407 /// MustSaveLR - Return true if this function requires that we save the LR
00408 /// register onto the stack in the prolog and restore it in the epilog of the
00409 /// function.
00410 static bool MustSaveLR(const MachineFunction &MF, unsigned LR) {
00411   const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>();
00412 
00413   // We need a save/restore of LR if there is any def of LR (which is
00414   // defined by calls, including the PIC setup sequence), or if there is
00415   // some use of the LR stack slot (e.g. for builtin_return_address).
00416   // (LR comes in 32 and 64 bit versions.)
00417   MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR);
00418   return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired();
00419 }
00420 
00421 /// determineFrameLayout - Determine the size of the frame and maximum call
00422 /// frame size.
00423 unsigned PPCFrameLowering::determineFrameLayout(MachineFunction &MF,
00424                                                 bool UpdateMF,
00425                                                 bool UseEstimate) const {
00426   MachineFrameInfo *MFI = MF.getFrameInfo();
00427 
00428   // Get the number of bytes to allocate from the FrameInfo
00429   unsigned FrameSize =
00430     UseEstimate ? MFI->estimateStackSize(MF) : MFI->getStackSize();
00431 
00432   // Get stack alignments. The frame must be aligned to the greatest of these:
00433   unsigned TargetAlign = getStackAlignment(); // alignment required per the ABI
00434   unsigned MaxAlign = MFI->getMaxAlignment(); // algmt required by data in frame
00435   unsigned AlignMask = std::max(MaxAlign, TargetAlign) - 1;
00436 
00437   const PPCRegisterInfo *RegInfo =
00438       static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo());
00439 
00440   // If we are a leaf function, and use up to 224 bytes of stack space,
00441   // don't have a frame pointer, calls, or dynamic alloca then we do not need
00442   // to adjust the stack pointer (we fit in the Red Zone).
00443   // The 32-bit SVR4 ABI has no Red Zone. However, it can still generate
00444   // stackless code if all local vars are reg-allocated.
00445   bool DisableRedZone = MF.getFunction()->hasFnAttribute(Attribute::NoRedZone);
00446   unsigned LR = RegInfo->getRARegister();
00447   if (!DisableRedZone &&
00448       (Subtarget.isPPC64() ||                      // 32-bit SVR4, no stack-
00449        !Subtarget.isSVR4ABI() ||                   //   allocated locals.
00450         FrameSize == 0) &&
00451       FrameSize <= 224 &&                          // Fits in red zone.
00452       !MFI->hasVarSizedObjects() &&                // No dynamic alloca.
00453       !MFI->adjustsStack() &&                      // No calls.
00454       !MustSaveLR(MF, LR) &&
00455       !RegInfo->hasBasePointer(MF)) { // No special alignment.
00456     // No need for frame
00457     if (UpdateMF)
00458       MFI->setStackSize(0);
00459     return 0;
00460   }
00461 
00462   // Get the maximum call frame size of all the calls.
00463   unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
00464 
00465   // Maximum call frame needs to be at least big enough for linkage area.
00466   unsigned minCallFrameSize = getLinkageSize();
00467   maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);
00468 
00469   // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
00470   // that allocations will be aligned.
00471   if (MFI->hasVarSizedObjects())
00472     maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
00473 
00474   // Update maximum call frame size.
00475   if (UpdateMF)
00476     MFI->setMaxCallFrameSize(maxCallFrameSize);
00477 
00478   // Include call frame size in total.
00479   FrameSize += maxCallFrameSize;
00480 
00481   // Make sure the frame is aligned.
00482   FrameSize = (FrameSize + AlignMask) & ~AlignMask;
00483 
00484   // Update frame info.
00485   if (UpdateMF)
00486     MFI->setStackSize(FrameSize);
00487 
00488   return FrameSize;
00489 }
00490 
00491 // hasFP - Return true if the specified function actually has a dedicated frame
00492 // pointer register.
00493 bool PPCFrameLowering::hasFP(const MachineFunction &MF) const {
00494   const MachineFrameInfo *MFI = MF.getFrameInfo();
00495   // FIXME: This is pretty much broken by design: hasFP() might be called really
00496   // early, before the stack layout was calculated and thus hasFP() might return
00497   // true or false here depending on the time of call.
00498   return (MFI->getStackSize()) && needsFP(MF);
00499 }
00500 
00501 // needsFP - Return true if the specified function should have a dedicated frame
00502 // pointer register.  This is true if the function has variable sized allocas or
00503 // if frame pointer elimination is disabled.
00504 bool PPCFrameLowering::needsFP(const MachineFunction &MF) const {
00505   const MachineFrameInfo *MFI = MF.getFrameInfo();
00506 
00507   // Naked functions have no stack frame pushed, so we don't have a frame
00508   // pointer.
00509   if (MF.getFunction()->hasFnAttribute(Attribute::Naked))
00510     return false;
00511 
00512   return MF.getTarget().Options.DisableFramePointerElim(MF) ||
00513     MFI->hasVarSizedObjects() ||
00514     MFI->hasStackMap() || MFI->hasPatchPoint() ||
00515     (MF.getTarget().Options.GuaranteedTailCallOpt &&
00516      MF.getInfo<PPCFunctionInfo>()->hasFastCall());
00517 }
00518 
00519 void PPCFrameLowering::replaceFPWithRealFP(MachineFunction &MF) const {
00520   bool is31 = needsFP(MF);
00521   unsigned FPReg  = is31 ? PPC::R31 : PPC::R1;
00522   unsigned FP8Reg = is31 ? PPC::X31 : PPC::X1;
00523 
00524   const PPCRegisterInfo *RegInfo =
00525       static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo());
00526   bool HasBP = RegInfo->hasBasePointer(MF);
00527   unsigned BPReg  = HasBP ? (unsigned) RegInfo->getBaseRegister(MF) : FPReg;
00528   unsigned BP8Reg = HasBP ? (unsigned) PPC::X30 : FPReg;
00529 
00530   for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
00531        BI != BE; ++BI)
00532     for (MachineBasicBlock::iterator MBBI = BI->end(); MBBI != BI->begin(); ) {
00533       --MBBI;
00534       for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) {
00535         MachineOperand &MO = MBBI->getOperand(I);
00536         if (!MO.isReg())
00537           continue;
00538 
00539         switch (MO.getReg()) {
00540         case PPC::FP:
00541           MO.setReg(FPReg);
00542           break;
00543         case PPC::FP8:
00544           MO.setReg(FP8Reg);
00545           break;
00546         case PPC::BP:
00547           MO.setReg(BPReg);
00548           break;
00549         case PPC::BP8:
00550           MO.setReg(BP8Reg);
00551           break;
00552 
00553         }
00554       }
00555     }
00556 }
00557 
00558 void PPCFrameLowering::emitPrologue(MachineFunction &MF,
00559                                     MachineBasicBlock &MBB) const {
00560   assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
00561   MachineBasicBlock::iterator MBBI = MBB.begin();
00562   MachineFrameInfo *MFI = MF.getFrameInfo();
00563   const PPCInstrInfo &TII =
00564       *static_cast<const PPCInstrInfo *>(Subtarget.getInstrInfo());
00565   const PPCRegisterInfo *RegInfo =
00566       static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo());
00567 
00568   MachineModuleInfo &MMI = MF.getMMI();
00569   const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
00570   DebugLoc dl;
00571   bool needsCFI = MMI.hasDebugInfo() ||
00572     MF.getFunction()->needsUnwindTableEntry();
00573 
00574   // Get processor type.
00575   bool isPPC64 = Subtarget.isPPC64();
00576   // Get the ABI.
00577   bool isSVR4ABI = Subtarget.isSVR4ABI();
00578   bool isELFv2ABI = Subtarget.isELFv2ABI();
00579   assert((Subtarget.isDarwinABI() || isSVR4ABI) &&
00580          "Currently only Darwin and SVR4 ABIs are supported for PowerPC.");
00581 
00582   // Scan the prolog, looking for an UPDATE_VRSAVE instruction.  If we find it,
00583   // process it.
00584   if (!isSVR4ABI)
00585     for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
00586       if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
00587         HandleVRSaveUpdate(MBBI, TII);
00588         break;
00589       }
00590     }
00591 
00592   // Move MBBI back to the beginning of the function.
00593   MBBI = MBB.begin();
00594 
00595   // Work out frame sizes.
00596   unsigned FrameSize = determineFrameLayout(MF);
00597   int NegFrameSize = -FrameSize;
00598   if (!isInt<32>(NegFrameSize))
00599     llvm_unreachable("Unhandled stack size!");
00600 
00601   if (MFI->isFrameAddressTaken())
00602     replaceFPWithRealFP(MF);
00603 
00604   // Check if the link register (LR) must be saved.
00605   PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
00606   bool MustSaveLR = FI->mustSaveLR();
00607   const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs();
00608   // Do we have a frame pointer and/or base pointer for this function?
00609   bool HasFP = hasFP(MF);
00610   bool HasBP = RegInfo->hasBasePointer(MF);
00611 
00612   unsigned SPReg       = isPPC64 ? PPC::X1  : PPC::R1;
00613   unsigned BPReg       = RegInfo->getBaseRegister(MF);
00614   unsigned FPReg       = isPPC64 ? PPC::X31 : PPC::R31;
00615   unsigned LRReg       = isPPC64 ? PPC::LR8 : PPC::LR;
00616   unsigned ScratchReg  = isPPC64 ? PPC::X0  : PPC::R0;
00617   unsigned TempReg     = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
00618   //  ...(R12/X12 is volatile in both Darwin & SVR4, & can't be a function arg.)
00619   const MCInstrDesc& MFLRInst = TII.get(isPPC64 ? PPC::MFLR8
00620                                                 : PPC::MFLR );
00621   const MCInstrDesc& StoreInst = TII.get(isPPC64 ? PPC::STD
00622                                                  : PPC::STW );
00623   const MCInstrDesc& StoreUpdtInst = TII.get(isPPC64 ? PPC::STDU
00624                                                      : PPC::STWU );
00625   const MCInstrDesc& StoreUpdtIdxInst = TII.get(isPPC64 ? PPC::STDUX
00626                                                         : PPC::STWUX);
00627   const MCInstrDesc& LoadImmShiftedInst = TII.get(isPPC64 ? PPC::LIS8
00628                                                           : PPC::LIS );
00629   const MCInstrDesc& OrImmInst = TII.get(isPPC64 ? PPC::ORI8
00630                                                  : PPC::ORI );
00631   const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8
00632                                               : PPC::OR );
00633   const MCInstrDesc& SubtractCarryingInst = TII.get(isPPC64 ? PPC::SUBFC8
00634                                                             : PPC::SUBFC);
00635   const MCInstrDesc& SubtractImmCarryingInst = TII.get(isPPC64 ? PPC::SUBFIC8
00636                                                                : PPC::SUBFIC);
00637 
00638   // Regarding this assert: Even though LR is saved in the caller's frame (i.e.,
00639   // LROffset is positive), that slot is callee-owned. Because PPC32 SVR4 has no
00640   // Red Zone, an asynchronous event (a form of "callee") could claim a frame &
00641   // overwrite it, so PPC32 SVR4 must claim at least a minimal frame to save LR.
00642   assert((isPPC64 || !isSVR4ABI || !(!FrameSize && (MustSaveLR || HasFP))) &&
00643          "FrameSize must be >0 to save/restore the FP or LR for 32-bit SVR4.");
00644 
00645   int LROffset = getReturnSaveOffset();
00646 
00647   int FPOffset = 0;
00648   if (HasFP) {
00649     if (isSVR4ABI) {
00650       MachineFrameInfo *FFI = MF.getFrameInfo();
00651       int FPIndex = FI->getFramePointerSaveIndex();
00652       assert(FPIndex && "No Frame Pointer Save Slot!");
00653       FPOffset = FFI->getObjectOffset(FPIndex);
00654     } else {
00655       FPOffset = getFramePointerSaveOffset();
00656     }
00657   }
00658 
00659   int BPOffset = 0;
00660   if (HasBP) {
00661     if (isSVR4ABI) {
00662       MachineFrameInfo *FFI = MF.getFrameInfo();
00663       int BPIndex = FI->getBasePointerSaveIndex();
00664       assert(BPIndex && "No Base Pointer Save Slot!");
00665       BPOffset = FFI->getObjectOffset(BPIndex);
00666     } else {
00667       BPOffset = getBasePointerSaveOffset();
00668     }
00669   }
00670 
00671   int PBPOffset = 0;
00672   if (FI->usesPICBase()) {
00673     MachineFrameInfo *FFI = MF.getFrameInfo();
00674     int PBPIndex = FI->getPICBasePointerSaveIndex();
00675     assert(PBPIndex && "No PIC Base Pointer Save Slot!");
00676     PBPOffset = FFI->getObjectOffset(PBPIndex);
00677   }
00678 
00679   // Get stack alignments.
00680   unsigned MaxAlign = MFI->getMaxAlignment();
00681   if (HasBP && MaxAlign > 1)
00682     assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) &&
00683            "Invalid alignment!");
00684 
00685   // Frames of 32KB & larger require special handling because they cannot be
00686   // indexed into with a simple STDU/STWU/STD/STW immediate offset operand.
00687   bool isLargeFrame = !isInt<16>(NegFrameSize);
00688 
00689   if (MustSaveLR)
00690     BuildMI(MBB, MBBI, dl, MFLRInst, ScratchReg);
00691 
00692   assert((isPPC64 || MustSaveCRs.empty()) &&
00693          "Prologue CR saving supported only in 64-bit mode");
00694 
00695   if (!MustSaveCRs.empty()) { // will only occur for PPC64
00696     // FIXME: In the ELFv2 ABI, we are not required to save all CR fields.
00697     // If only one or two CR fields are clobbered, it could be more
00698     // efficient to use mfocrf to selectively save just those fields.
00699     MachineInstrBuilder MIB =
00700       BuildMI(MBB, MBBI, dl, TII.get(PPC::MFCR8), TempReg);
00701     for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
00702       MIB.addReg(MustSaveCRs[i], RegState::ImplicitKill);
00703   }
00704 
00705   if (HasFP)
00706     // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
00707     BuildMI(MBB, MBBI, dl, StoreInst)
00708       .addReg(FPReg)
00709       .addImm(FPOffset)
00710       .addReg(SPReg);
00711 
00712   if (FI->usesPICBase())
00713     // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
00714     BuildMI(MBB, MBBI, dl, StoreInst)
00715       .addReg(PPC::R30)
00716       .addImm(PBPOffset)
00717       .addReg(SPReg);
00718 
00719   if (HasBP)
00720     // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
00721     BuildMI(MBB, MBBI, dl, StoreInst)
00722       .addReg(BPReg)
00723       .addImm(BPOffset)
00724       .addReg(SPReg);
00725 
00726   if (MustSaveLR)
00727     // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
00728     BuildMI(MBB, MBBI, dl, StoreInst)
00729       .addReg(ScratchReg)
00730       .addImm(LROffset)
00731       .addReg(SPReg);
00732 
00733   if (!MustSaveCRs.empty()) // will only occur for PPC64
00734     BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8))
00735       .addReg(TempReg, getKillRegState(true))
00736       .addImm(8)
00737       .addReg(SPReg);
00738 
00739   // Skip the rest if this is a leaf function & all spills fit in the Red Zone.
00740   if (!FrameSize) return;
00741 
00742   // Adjust stack pointer: r1 += NegFrameSize.
00743   // If there is a preferred stack alignment, align R1 now
00744 
00745   if (HasBP) {
00746     // Save a copy of r1 as the base pointer.
00747     BuildMI(MBB, MBBI, dl, OrInst, BPReg)
00748       .addReg(SPReg)
00749       .addReg(SPReg);
00750   }
00751 
00752   if (HasBP && MaxAlign > 1) {
00753     if (isPPC64)
00754       BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), ScratchReg)
00755         .addReg(SPReg)
00756         .addImm(0)
00757         .addImm(64 - Log2_32(MaxAlign));
00758     else // PPC32...
00759       BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), ScratchReg)
00760         .addReg(SPReg)
00761         .addImm(0)
00762         .addImm(32 - Log2_32(MaxAlign))
00763         .addImm(31);
00764     if (!isLargeFrame) {
00765       BuildMI(MBB, MBBI, dl, SubtractImmCarryingInst, ScratchReg)
00766         .addReg(ScratchReg, RegState::Kill)
00767         .addImm(NegFrameSize);
00768     } else {
00769       BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, TempReg)
00770         .addImm(NegFrameSize >> 16);
00771       BuildMI(MBB, MBBI, dl, OrImmInst, TempReg)
00772         .addReg(TempReg, RegState::Kill)
00773         .addImm(NegFrameSize & 0xFFFF);
00774       BuildMI(MBB, MBBI, dl, SubtractCarryingInst, ScratchReg)
00775         .addReg(ScratchReg, RegState::Kill)
00776         .addReg(TempReg, RegState::Kill);
00777     }
00778     BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg)
00779       .addReg(SPReg, RegState::Kill)
00780       .addReg(SPReg)
00781       .addReg(ScratchReg);
00782 
00783   } else if (!isLargeFrame) {
00784     BuildMI(MBB, MBBI, dl, StoreUpdtInst, SPReg)
00785       .addReg(SPReg)
00786       .addImm(NegFrameSize)
00787       .addReg(SPReg);
00788 
00789   } else {
00790     BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
00791       .addImm(NegFrameSize >> 16);
00792     BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
00793       .addReg(ScratchReg, RegState::Kill)
00794       .addImm(NegFrameSize & 0xFFFF);
00795     BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg)
00796       .addReg(SPReg, RegState::Kill)
00797       .addReg(SPReg)
00798       .addReg(ScratchReg);
00799   }
00800 
00801   // Add Call Frame Information for the instructions we generated above.
00802   if (needsCFI) {
00803     unsigned CFIIndex;
00804 
00805     if (HasBP) {
00806       // Define CFA in terms of BP. Do this in preference to using FP/SP,
00807       // because if the stack needed aligning then CFA won't be at a fixed
00808       // offset from FP/SP.
00809       unsigned Reg = MRI->getDwarfRegNum(BPReg, true);
00810       CFIIndex = MMI.addFrameInst(
00811           MCCFIInstruction::createDefCfaRegister(nullptr, Reg));
00812     } else {
00813       // Adjust the definition of CFA to account for the change in SP.
00814       assert(NegFrameSize);
00815       CFIIndex = MMI.addFrameInst(
00816           MCCFIInstruction::createDefCfaOffset(nullptr, NegFrameSize));
00817     }
00818     BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
00819         .addCFIIndex(CFIIndex);
00820 
00821     if (HasFP) {
00822       // Describe where FP was saved, at a fixed offset from CFA.
00823       unsigned Reg = MRI->getDwarfRegNum(FPReg, true);
00824       CFIIndex = MMI.addFrameInst(
00825           MCCFIInstruction::createOffset(nullptr, Reg, FPOffset));
00826       BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
00827           .addCFIIndex(CFIIndex);
00828     }
00829 
00830     if (FI->usesPICBase()) {
00831       // Describe where FP was saved, at a fixed offset from CFA.
00832       unsigned Reg = MRI->getDwarfRegNum(PPC::R30, true);
00833       CFIIndex = MMI.addFrameInst(
00834           MCCFIInstruction::createOffset(nullptr, Reg, PBPOffset));
00835       BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
00836           .addCFIIndex(CFIIndex);
00837     }
00838 
00839     if (HasBP) {
00840       // Describe where BP was saved, at a fixed offset from CFA.
00841       unsigned Reg = MRI->getDwarfRegNum(BPReg, true);
00842       CFIIndex = MMI.addFrameInst(
00843           MCCFIInstruction::createOffset(nullptr, Reg, BPOffset));
00844       BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
00845           .addCFIIndex(CFIIndex);
00846     }
00847 
00848     if (MustSaveLR) {
00849       // Describe where LR was saved, at a fixed offset from CFA.
00850       unsigned Reg = MRI->getDwarfRegNum(LRReg, true);
00851       CFIIndex = MMI.addFrameInst(
00852           MCCFIInstruction::createOffset(nullptr, Reg, LROffset));
00853       BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
00854           .addCFIIndex(CFIIndex);
00855     }
00856   }
00857 
00858   // If there is a frame pointer, copy R1 into R31
00859   if (HasFP) {
00860     BuildMI(MBB, MBBI, dl, OrInst, FPReg)
00861       .addReg(SPReg)
00862       .addReg(SPReg);
00863 
00864     if (!HasBP && needsCFI) {
00865       // Change the definition of CFA from SP+offset to FP+offset, because SP
00866       // will change at every alloca.
00867       unsigned Reg = MRI->getDwarfRegNum(FPReg, true);
00868       unsigned CFIIndex = MMI.addFrameInst(
00869           MCCFIInstruction::createDefCfaRegister(nullptr, Reg));
00870 
00871       BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
00872           .addCFIIndex(CFIIndex);
00873     }
00874   }
00875 
00876   if (needsCFI) {
00877     // Describe where callee saved registers were saved, at fixed offsets from
00878     // CFA.
00879     const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
00880     for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
00881       unsigned Reg = CSI[I].getReg();
00882       if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue;
00883 
00884       // This is a bit of a hack: CR2LT, CR2GT, CR2EQ and CR2UN are just
00885       // subregisters of CR2. We just need to emit a move of CR2.
00886       if (PPC::CRBITRCRegClass.contains(Reg))
00887         continue;
00888 
00889       // For SVR4, don't emit a move for the CR spill slot if we haven't
00890       // spilled CRs.
00891       if (isSVR4ABI && (PPC::CR2 <= Reg && Reg <= PPC::CR4)
00892           && MustSaveCRs.empty())
00893         continue;
00894 
00895       // For 64-bit SVR4 when we have spilled CRs, the spill location
00896       // is SP+8, not a frame-relative slot.
00897       if (isSVR4ABI && isPPC64 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
00898         // In the ELFv1 ABI, only CR2 is noted in CFI and stands in for
00899         // the whole CR word.  In the ELFv2 ABI, every CR that was
00900         // actually saved gets its own CFI record.
00901         unsigned CRReg = isELFv2ABI? Reg : (unsigned) PPC::CR2;
00902         unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
00903             nullptr, MRI->getDwarfRegNum(CRReg, true), 8));
00904         BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
00905             .addCFIIndex(CFIIndex);
00906         continue;
00907       }
00908 
00909       int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
00910       unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
00911           nullptr, MRI->getDwarfRegNum(Reg, true), Offset));
00912       BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
00913           .addCFIIndex(CFIIndex);
00914     }
00915   }
00916 }
00917 
00918 void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
00919                                 MachineBasicBlock &MBB) const {
00920   MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
00921   assert(MBBI != MBB.end() && "Returning block has no terminator");
00922   const PPCInstrInfo &TII =
00923       *static_cast<const PPCInstrInfo *>(Subtarget.getInstrInfo());
00924   const PPCRegisterInfo *RegInfo =
00925       static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo());
00926 
00927   unsigned RetOpcode = MBBI->getOpcode();
00928   DebugLoc dl;
00929 
00930   assert((RetOpcode == PPC::BLR ||
00931           RetOpcode == PPC::BLR8 ||
00932           RetOpcode == PPC::TCRETURNri ||
00933           RetOpcode == PPC::TCRETURNdi ||
00934           RetOpcode == PPC::TCRETURNai ||
00935           RetOpcode == PPC::TCRETURNri8 ||
00936           RetOpcode == PPC::TCRETURNdi8 ||
00937           RetOpcode == PPC::TCRETURNai8) &&
00938          "Can only insert epilog into returning blocks");
00939 
00940   // Get alignment info so we know how to restore the SP.
00941   const MachineFrameInfo *MFI = MF.getFrameInfo();
00942 
00943   // Get the number of bytes allocated from the FrameInfo.
00944   int FrameSize = MFI->getStackSize();
00945 
00946   // Get processor type.
00947   bool isPPC64 = Subtarget.isPPC64();
00948   // Get the ABI.
00949   bool isSVR4ABI = Subtarget.isSVR4ABI();
00950 
00951   // Check if the link register (LR) has been saved.
00952   PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
00953   bool MustSaveLR = FI->mustSaveLR();
00954   const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs();
00955   // Do we have a frame pointer and/or base pointer for this function?
00956   bool HasFP = hasFP(MF);
00957   bool HasBP = RegInfo->hasBasePointer(MF);
00958 
00959   unsigned SPReg      = isPPC64 ? PPC::X1  : PPC::R1;
00960   unsigned BPReg      = RegInfo->getBaseRegister(MF);
00961   unsigned FPReg      = isPPC64 ? PPC::X31 : PPC::R31;
00962   unsigned ScratchReg  = isPPC64 ? PPC::X0  : PPC::R0;
00963   unsigned TempReg     = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
00964   const MCInstrDesc& MTLRInst = TII.get( isPPC64 ? PPC::MTLR8
00965                                                  : PPC::MTLR );
00966   const MCInstrDesc& LoadInst = TII.get( isPPC64 ? PPC::LD
00967                                                  : PPC::LWZ );
00968   const MCInstrDesc& LoadImmShiftedInst = TII.get( isPPC64 ? PPC::LIS8
00969                                                            : PPC::LIS );
00970   const MCInstrDesc& OrImmInst = TII.get( isPPC64 ? PPC::ORI8
00971                                                   : PPC::ORI );
00972   const MCInstrDesc& AddImmInst = TII.get( isPPC64 ? PPC::ADDI8
00973                                                    : PPC::ADDI );
00974   const MCInstrDesc& AddInst = TII.get( isPPC64 ? PPC::ADD8
00975                                                 : PPC::ADD4 );
00976 
00977   int LROffset = getReturnSaveOffset();
00978 
00979   int FPOffset = 0;
00980   if (HasFP) {
00981     if (isSVR4ABI) {
00982       MachineFrameInfo *FFI = MF.getFrameInfo();
00983       int FPIndex = FI->getFramePointerSaveIndex();
00984       assert(FPIndex && "No Frame Pointer Save Slot!");
00985       FPOffset = FFI->getObjectOffset(FPIndex);
00986     } else {
00987       FPOffset = getFramePointerSaveOffset();
00988     }
00989   }
00990 
00991   int BPOffset = 0;
00992   if (HasBP) {
00993     if (isSVR4ABI) {
00994       MachineFrameInfo *FFI = MF.getFrameInfo();
00995       int BPIndex = FI->getBasePointerSaveIndex();
00996       assert(BPIndex && "No Base Pointer Save Slot!");
00997       BPOffset = FFI->getObjectOffset(BPIndex);
00998     } else {
00999       BPOffset = getBasePointerSaveOffset();
01000     }
01001   }
01002 
01003   int PBPOffset = 0;
01004   if (FI->usesPICBase()) {
01005     MachineFrameInfo *FFI = MF.getFrameInfo();
01006     int PBPIndex = FI->getPICBasePointerSaveIndex();
01007     assert(PBPIndex && "No PIC Base Pointer Save Slot!");
01008     PBPOffset = FFI->getObjectOffset(PBPIndex);
01009   }
01010 
01011   bool UsesTCRet =  RetOpcode == PPC::TCRETURNri ||
01012     RetOpcode == PPC::TCRETURNdi ||
01013     RetOpcode == PPC::TCRETURNai ||
01014     RetOpcode == PPC::TCRETURNri8 ||
01015     RetOpcode == PPC::TCRETURNdi8 ||
01016     RetOpcode == PPC::TCRETURNai8;
01017 
01018   if (UsesTCRet) {
01019     int MaxTCRetDelta = FI->getTailCallSPDelta();
01020     MachineOperand &StackAdjust = MBBI->getOperand(1);
01021     assert(StackAdjust.isImm() && "Expecting immediate value.");
01022     // Adjust stack pointer.
01023     int StackAdj = StackAdjust.getImm();
01024     int Delta = StackAdj - MaxTCRetDelta;
01025     assert((Delta >= 0) && "Delta must be positive");
01026     if (MaxTCRetDelta>0)
01027       FrameSize += (StackAdj +Delta);
01028     else
01029       FrameSize += StackAdj;
01030   }
01031 
01032   // Frames of 32KB & larger require special handling because they cannot be
01033   // indexed into with a simple LD/LWZ immediate offset operand.
01034   bool isLargeFrame = !isInt<16>(FrameSize);
01035 
01036   if (FrameSize) {
01037     // In the prologue, the loaded (or persistent) stack pointer value is offset
01038     // by the STDU/STDUX/STWU/STWUX instruction.  Add this offset back now.
01039 
01040     // If this function contained a fastcc call and GuaranteedTailCallOpt is
01041     // enabled (=> hasFastCall()==true) the fastcc call might contain a tail
01042     // call which invalidates the stack pointer value in SP(0). So we use the
01043     // value of R31 in this case.
01044     if (FI->hasFastCall()) {
01045       assert(HasFP && "Expecting a valid frame pointer.");
01046       if (!isLargeFrame) {
01047         BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
01048           .addReg(FPReg).addImm(FrameSize);
01049       } else {
01050         BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
01051           .addImm(FrameSize >> 16);
01052         BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
01053           .addReg(ScratchReg, RegState::Kill)
01054           .addImm(FrameSize & 0xFFFF);
01055         BuildMI(MBB, MBBI, dl, AddInst)
01056           .addReg(SPReg)
01057           .addReg(FPReg)
01058           .addReg(ScratchReg);
01059       }
01060     } else if (!isLargeFrame && !HasBP && !MFI->hasVarSizedObjects()) {
01061       BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
01062         .addReg(SPReg)
01063         .addImm(FrameSize);
01064     } else {
01065       BuildMI(MBB, MBBI, dl, LoadInst, SPReg)
01066         .addImm(0)
01067         .addReg(SPReg);
01068     }
01069 
01070   }
01071 
01072   if (MustSaveLR)
01073     BuildMI(MBB, MBBI, dl, LoadInst, ScratchReg)
01074       .addImm(LROffset)
01075       .addReg(SPReg);
01076 
01077   assert((isPPC64 || MustSaveCRs.empty()) &&
01078          "Epilogue CR restoring supported only in 64-bit mode");
01079 
01080   if (!MustSaveCRs.empty()) // will only occur for PPC64
01081     BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg)
01082       .addImm(8)
01083       .addReg(SPReg);
01084 
01085   if (HasFP)
01086     BuildMI(MBB, MBBI, dl, LoadInst, FPReg)
01087       .addImm(FPOffset)
01088       .addReg(SPReg);
01089 
01090   if (FI->usesPICBase())
01091     // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
01092     BuildMI(MBB, MBBI, dl, LoadInst)
01093       .addReg(PPC::R30)
01094       .addImm(PBPOffset)
01095       .addReg(SPReg);
01096 
01097   if (HasBP)
01098     BuildMI(MBB, MBBI, dl, LoadInst, BPReg)
01099       .addImm(BPOffset)
01100       .addReg(SPReg);
01101 
01102   if (!MustSaveCRs.empty()) // will only occur for PPC64
01103     for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
01104       BuildMI(MBB, MBBI, dl, TII.get(PPC::MTOCRF8), MustSaveCRs[i])
01105         .addReg(TempReg, getKillRegState(i == e-1));
01106 
01107   if (MustSaveLR)
01108     BuildMI(MBB, MBBI, dl, MTLRInst).addReg(ScratchReg);
01109 
01110   // Callee pop calling convention. Pop parameter/linkage area. Used for tail
01111   // call optimization
01112   if (MF.getTarget().Options.GuaranteedTailCallOpt &&
01113       (RetOpcode == PPC::BLR || RetOpcode == PPC::BLR8) &&
01114       MF.getFunction()->getCallingConv() == CallingConv::Fast) {
01115      PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
01116      unsigned CallerAllocatedAmt = FI->getMinReservedArea();
01117 
01118      if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) {
01119        BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
01120          .addReg(SPReg).addImm(CallerAllocatedAmt);
01121      } else {
01122        BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
01123           .addImm(CallerAllocatedAmt >> 16);
01124        BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
01125           .addReg(ScratchReg, RegState::Kill)
01126           .addImm(CallerAllocatedAmt & 0xFFFF);
01127        BuildMI(MBB, MBBI, dl, AddInst)
01128           .addReg(SPReg)
01129           .addReg(FPReg)
01130           .addReg(ScratchReg);
01131      }
01132   } else if (RetOpcode == PPC::TCRETURNdi) {
01133     MBBI = MBB.getLastNonDebugInstr();
01134     MachineOperand &JumpTarget = MBBI->getOperand(0);
01135     BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)).
01136       addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
01137   } else if (RetOpcode == PPC::TCRETURNri) {
01138     MBBI = MBB.getLastNonDebugInstr();
01139     assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
01140     BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR));
01141   } else if (RetOpcode == PPC::TCRETURNai) {
01142     MBBI = MBB.getLastNonDebugInstr();
01143     MachineOperand &JumpTarget = MBBI->getOperand(0);
01144     BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm());
01145   } else if (RetOpcode == PPC::TCRETURNdi8) {
01146     MBBI = MBB.getLastNonDebugInstr();
01147     MachineOperand &JumpTarget = MBBI->getOperand(0);
01148     BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)).
01149       addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
01150   } else if (RetOpcode == PPC::TCRETURNri8) {
01151     MBBI = MBB.getLastNonDebugInstr();
01152     assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
01153     BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8));
01154   } else if (RetOpcode == PPC::TCRETURNai8) {
01155     MBBI = MBB.getLastNonDebugInstr();
01156     MachineOperand &JumpTarget = MBBI->getOperand(0);
01157     BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm());
01158   }
01159 }
01160 
01161 void
01162 PPCFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
01163                                                    RegScavenger *) const {
01164   const PPCRegisterInfo *RegInfo =
01165       static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo());
01166 
01167   //  Save and clear the LR state.
01168   PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
01169   unsigned LR = RegInfo->getRARegister();
01170   FI->setMustSaveLR(MustSaveLR(MF, LR));
01171   MachineRegisterInfo &MRI = MF.getRegInfo();
01172   MRI.setPhysRegUnused(LR);
01173 
01174   //  Save R31 if necessary
01175   int FPSI = FI->getFramePointerSaveIndex();
01176   bool isPPC64 = Subtarget.isPPC64();
01177   bool isDarwinABI  = Subtarget.isDarwinABI();
01178   MachineFrameInfo *MFI = MF.getFrameInfo();
01179 
01180   // If the frame pointer save index hasn't been defined yet.
01181   if (!FPSI && needsFP(MF)) {
01182     // Find out what the fix offset of the frame pointer save area.
01183     int FPOffset = getFramePointerSaveOffset();
01184     // Allocate the frame index for frame pointer save area.
01185     FPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
01186     // Save the result.
01187     FI->setFramePointerSaveIndex(FPSI);
01188   }
01189 
01190   int BPSI = FI->getBasePointerSaveIndex();
01191   if (!BPSI && RegInfo->hasBasePointer(MF)) {
01192     int BPOffset = getBasePointerSaveOffset();
01193     // Allocate the frame index for the base pointer save area.
01194     BPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, BPOffset, true);
01195     // Save the result.
01196     FI->setBasePointerSaveIndex(BPSI);
01197   }
01198 
01199   // Reserve stack space for the PIC Base register (R30).
01200   // Only used in SVR4 32-bit.
01201   if (FI->usesPICBase()) {
01202     int PBPSI = FI->getPICBasePointerSaveIndex();
01203     PBPSI = MFI->CreateFixedObject(4, -8, true);
01204     FI->setPICBasePointerSaveIndex(PBPSI);
01205   }
01206 
01207   // Reserve stack space to move the linkage area to in case of a tail call.
01208   int TCSPDelta = 0;
01209   if (MF.getTarget().Options.GuaranteedTailCallOpt &&
01210       (TCSPDelta = FI->getTailCallSPDelta()) < 0) {
01211     MFI->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true);
01212   }
01213 
01214   // For 32-bit SVR4, allocate the nonvolatile CR spill slot iff the
01215   // function uses CR 2, 3, or 4.
01216   if (!isPPC64 && !isDarwinABI &&
01217       (MRI.isPhysRegUsed(PPC::CR2) ||
01218        MRI.isPhysRegUsed(PPC::CR3) ||
01219        MRI.isPhysRegUsed(PPC::CR4))) {
01220     int FrameIdx = MFI->CreateFixedObject((uint64_t)4, (int64_t)-4, true);
01221     FI->setCRSpillFrameIndex(FrameIdx);
01222   }
01223 }
01224 
01225 void PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF,
01226                                                        RegScavenger *RS) const {
01227   // Early exit if not using the SVR4 ABI.
01228   if (!Subtarget.isSVR4ABI()) {
01229     addScavengingSpillSlot(MF, RS);
01230     return;
01231   }
01232 
01233   // Get callee saved register information.
01234   MachineFrameInfo *FFI = MF.getFrameInfo();
01235   const std::vector<CalleeSavedInfo> &CSI = FFI->getCalleeSavedInfo();
01236 
01237   // Early exit if no callee saved registers are modified!
01238   if (CSI.empty() && !needsFP(MF)) {
01239     addScavengingSpillSlot(MF, RS);
01240     return;
01241   }
01242 
01243   unsigned MinGPR = PPC::R31;
01244   unsigned MinG8R = PPC::X31;
01245   unsigned MinFPR = PPC::F31;
01246   unsigned MinVR = PPC::V31;
01247 
01248   bool HasGPSaveArea = false;
01249   bool HasG8SaveArea = false;
01250   bool HasFPSaveArea = false;
01251   bool HasVRSAVESaveArea = false;
01252   bool HasVRSaveArea = false;
01253 
01254   SmallVector<CalleeSavedInfo, 18> GPRegs;
01255   SmallVector<CalleeSavedInfo, 18> G8Regs;
01256   SmallVector<CalleeSavedInfo, 18> FPRegs;
01257   SmallVector<CalleeSavedInfo, 18> VRegs;
01258 
01259   for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
01260     unsigned Reg = CSI[i].getReg();
01261     if (PPC::GPRCRegClass.contains(Reg)) {
01262       HasGPSaveArea = true;
01263 
01264       GPRegs.push_back(CSI[i]);
01265 
01266       if (Reg < MinGPR) {
01267         MinGPR = Reg;
01268       }
01269     } else if (PPC::G8RCRegClass.contains(Reg)) {
01270       HasG8SaveArea = true;
01271 
01272       G8Regs.push_back(CSI[i]);
01273 
01274       if (Reg < MinG8R) {
01275         MinG8R = Reg;
01276       }
01277     } else if (PPC::F8RCRegClass.contains(Reg)) {
01278       HasFPSaveArea = true;
01279 
01280       FPRegs.push_back(CSI[i]);
01281 
01282       if (Reg < MinFPR) {
01283         MinFPR = Reg;
01284       }
01285     } else if (PPC::CRBITRCRegClass.contains(Reg) ||
01286                PPC::CRRCRegClass.contains(Reg)) {
01287       ; // do nothing, as we already know whether CRs are spilled
01288     } else if (PPC::VRSAVERCRegClass.contains(Reg)) {
01289       HasVRSAVESaveArea = true;
01290     } else if (PPC::VRRCRegClass.contains(Reg)) {
01291       HasVRSaveArea = true;
01292 
01293       VRegs.push_back(CSI[i]);
01294 
01295       if (Reg < MinVR) {
01296         MinVR = Reg;
01297       }
01298     } else {
01299       llvm_unreachable("Unknown RegisterClass!");
01300     }
01301   }
01302 
01303   PPCFunctionInfo *PFI = MF.getInfo<PPCFunctionInfo>();
01304   const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
01305 
01306   int64_t LowerBound = 0;
01307 
01308   // Take into account stack space reserved for tail calls.
01309   int TCSPDelta = 0;
01310   if (MF.getTarget().Options.GuaranteedTailCallOpt &&
01311       (TCSPDelta = PFI->getTailCallSPDelta()) < 0) {
01312     LowerBound = TCSPDelta;
01313   }
01314 
01315   // The Floating-point register save area is right below the back chain word
01316   // of the previous stack frame.
01317   if (HasFPSaveArea) {
01318     for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) {
01319       int FI = FPRegs[i].getFrameIdx();
01320 
01321       FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
01322     }
01323 
01324     LowerBound -= (31 - TRI->getEncodingValue(MinFPR) + 1) * 8;
01325   }
01326 
01327   // Check whether the frame pointer register is allocated. If so, make sure it
01328   // is spilled to the correct offset.
01329   if (needsFP(MF)) {
01330     HasGPSaveArea = true;
01331 
01332     int FI = PFI->getFramePointerSaveIndex();
01333     assert(FI && "No Frame Pointer Save Slot!");
01334 
01335     FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
01336   }
01337 
01338   if (PFI->usesPICBase()) {
01339     HasGPSaveArea = true;
01340 
01341     int FI = PFI->getPICBasePointerSaveIndex();
01342     assert(FI && "No PIC Base Pointer Save Slot!");
01343 
01344     FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
01345   }
01346 
01347   const PPCRegisterInfo *RegInfo =
01348       static_cast<const PPCRegisterInfo *>(Subtarget.getRegisterInfo());
01349   if (RegInfo->hasBasePointer(MF)) {
01350     HasGPSaveArea = true;
01351 
01352     int FI = PFI->getBasePointerSaveIndex();
01353     assert(FI && "No Base Pointer Save Slot!");
01354 
01355     FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
01356   }
01357 
01358   // General register save area starts right below the Floating-point
01359   // register save area.
01360   if (HasGPSaveArea || HasG8SaveArea) {
01361     // Move general register save area spill slots down, taking into account
01362     // the size of the Floating-point register save area.
01363     for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) {
01364       int FI = GPRegs[i].getFrameIdx();
01365 
01366       FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
01367     }
01368 
01369     // Move general register save area spill slots down, taking into account
01370     // the size of the Floating-point register save area.
01371     for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) {
01372       int FI = G8Regs[i].getFrameIdx();
01373 
01374       FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
01375     }
01376 
01377     unsigned MinReg =
01378       std::min<unsigned>(TRI->getEncodingValue(MinGPR),
01379                          TRI->getEncodingValue(MinG8R));
01380 
01381     if (Subtarget.isPPC64()) {
01382       LowerBound -= (31 - MinReg + 1) * 8;
01383     } else {
01384       LowerBound -= (31 - MinReg + 1) * 4;
01385     }
01386   }
01387 
01388   // For 32-bit only, the CR save area is below the general register
01389   // save area.  For 64-bit SVR4, the CR save area is addressed relative
01390   // to the stack pointer and hence does not need an adjustment here.
01391   // Only CR2 (the first nonvolatile spilled) has an associated frame
01392   // index so that we have a single uniform save area.
01393   if (spillsCR(MF) && !(Subtarget.isPPC64() && Subtarget.isSVR4ABI())) {
01394     // Adjust the frame index of the CR spill slot.
01395     for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
01396       unsigned Reg = CSI[i].getReg();
01397 
01398       if ((Subtarget.isSVR4ABI() && Reg == PPC::CR2)
01399           // Leave Darwin logic as-is.
01400           || (!Subtarget.isSVR4ABI() &&
01401               (PPC::CRBITRCRegClass.contains(Reg) ||
01402                PPC::CRRCRegClass.contains(Reg)))) {
01403         int FI = CSI[i].getFrameIdx();
01404 
01405         FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
01406       }
01407     }
01408 
01409     LowerBound -= 4; // The CR save area is always 4 bytes long.
01410   }
01411 
01412   if (HasVRSAVESaveArea) {
01413     // FIXME SVR4: Is it actually possible to have multiple elements in CSI
01414     //             which have the VRSAVE register class?
01415     // Adjust the frame index of the VRSAVE spill slot.
01416     for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
01417       unsigned Reg = CSI[i].getReg();
01418 
01419       if (PPC::VRSAVERCRegClass.contains(Reg)) {
01420         int FI = CSI[i].getFrameIdx();
01421 
01422         FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
01423       }
01424     }
01425 
01426     LowerBound -= 4; // The VRSAVE save area is always 4 bytes long.
01427   }
01428 
01429   if (HasVRSaveArea) {
01430     // Insert alignment padding, we need 16-byte alignment.
01431     LowerBound = (LowerBound - 15) & ~(15);
01432 
01433     for (unsigned i = 0, e = VRegs.size(); i != e; ++i) {
01434       int FI = VRegs[i].getFrameIdx();
01435 
01436       FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
01437     }
01438   }
01439 
01440   addScavengingSpillSlot(MF, RS);
01441 }
01442 
01443 void
01444 PPCFrameLowering::addScavengingSpillSlot(MachineFunction &MF,
01445                                          RegScavenger *RS) const {
01446   // Reserve a slot closest to SP or frame pointer if we have a dynalloc or
01447   // a large stack, which will require scavenging a register to materialize a
01448   // large offset.
01449 
01450   // We need to have a scavenger spill slot for spills if the frame size is
01451   // large. In case there is no free register for large-offset addressing,
01452   // this slot is used for the necessary emergency spill. Also, we need the
01453   // slot for dynamic stack allocations.
01454 
01455   // The scavenger might be invoked if the frame offset does not fit into
01456   // the 16-bit immediate. We don't know the complete frame size here
01457   // because we've not yet computed callee-saved register spills or the
01458   // needed alignment padding.
01459   unsigned StackSize = determineFrameLayout(MF, false, true);
01460   MachineFrameInfo *MFI = MF.getFrameInfo();
01461   if (MFI->hasVarSizedObjects() || spillsCR(MF) || spillsVRSAVE(MF) ||
01462       hasNonRISpills(MF) || (hasSpills(MF) && !isInt<16>(StackSize))) {
01463     const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
01464     const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
01465     const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC;
01466     RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
01467                                                        RC->getAlignment(),
01468                                                        false));
01469 
01470     // Might we have over-aligned allocas?
01471     bool HasAlVars = MFI->hasVarSizedObjects() &&
01472                      MFI->getMaxAlignment() > getStackAlignment();
01473 
01474     // These kinds of spills might need two registers.
01475     if (spillsCR(MF) || spillsVRSAVE(MF) || HasAlVars)
01476       RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
01477                                                          RC->getAlignment(),
01478                                                          false));
01479 
01480   }
01481 }
01482 
01483 bool
01484 PPCFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
01485                                      MachineBasicBlock::iterator MI,
01486                                      const std::vector<CalleeSavedInfo> &CSI,
01487                                      const TargetRegisterInfo *TRI) const {
01488 
01489   // Currently, this function only handles SVR4 32- and 64-bit ABIs.
01490   // Return false otherwise to maintain pre-existing behavior.
01491   if (!Subtarget.isSVR4ABI())
01492     return false;
01493 
01494   MachineFunction *MF = MBB.getParent();
01495   const PPCInstrInfo &TII =
01496       *static_cast<const PPCInstrInfo *>(Subtarget.getInstrInfo());
01497   DebugLoc DL;
01498   bool CRSpilled = false;
01499   MachineInstrBuilder CRMIB;
01500 
01501   for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
01502     unsigned Reg = CSI[i].getReg();
01503     // Only Darwin actually uses the VRSAVE register, but it can still appear
01504     // here if, for example, @llvm.eh.unwind.init() is used.  If we're not on
01505     // Darwin, ignore it.
01506     if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI())
01507       continue;
01508 
01509     // CR2 through CR4 are the nonvolatile CR fields.
01510     bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4;
01511 
01512     // Add the callee-saved register as live-in; it's killed at the spill.
01513     MBB.addLiveIn(Reg);
01514 
01515     if (CRSpilled && IsCRField) {
01516       CRMIB.addReg(Reg, RegState::ImplicitKill);
01517       continue;
01518     }
01519 
01520     // Insert the spill to the stack frame.
01521     if (IsCRField) {
01522       PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>();
01523       if (Subtarget.isPPC64()) {
01524         // The actual spill will happen at the start of the prologue.
01525         FuncInfo->addMustSaveCR(Reg);
01526       } else {
01527         CRSpilled = true;
01528         FuncInfo->setSpillsCR();
01529 
01530         // 32-bit:  FP-relative.  Note that we made sure CR2-CR4 all have
01531         // the same frame index in PPCRegisterInfo::hasReservedSpillSlot.
01532         CRMIB = BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12)
01533                   .addReg(Reg, RegState::ImplicitKill);
01534 
01535         MBB.insert(MI, CRMIB);
01536         MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::STW))
01537                                          .addReg(PPC::R12,
01538                                                  getKillRegState(true)),
01539                                          CSI[i].getFrameIdx()));
01540       }
01541     } else {
01542       const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
01543       TII.storeRegToStackSlot(MBB, MI, Reg, true,
01544                               CSI[i].getFrameIdx(), RC, TRI);
01545     }
01546   }
01547   return true;
01548 }
01549 
01550 static void
01551 restoreCRs(bool isPPC64, bool is31,
01552            bool CR2Spilled, bool CR3Spilled, bool CR4Spilled,
01553            MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
01554            const std::vector<CalleeSavedInfo> &CSI, unsigned CSIIndex) {
01555 
01556   MachineFunction *MF = MBB.getParent();
01557   const PPCInstrInfo &TII = *MF->getSubtarget<PPCSubtarget>().getInstrInfo();
01558   DebugLoc DL;
01559   unsigned RestoreOp, MoveReg;
01560 
01561   if (isPPC64)
01562     // This is handled during epilogue generation.
01563     return;
01564   else {
01565     // 32-bit:  FP-relative
01566     MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::LWZ),
01567                                              PPC::R12),
01568                                      CSI[CSIIndex].getFrameIdx()));
01569     RestoreOp = PPC::MTOCRF;
01570     MoveReg = PPC::R12;
01571   }
01572 
01573   if (CR2Spilled)
01574     MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR2)
01575                .addReg(MoveReg, getKillRegState(!CR3Spilled && !CR4Spilled)));
01576 
01577   if (CR3Spilled)
01578     MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR3)
01579                .addReg(MoveReg, getKillRegState(!CR4Spilled)));
01580 
01581   if (CR4Spilled)
01582     MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR4)
01583                .addReg(MoveReg, getKillRegState(true)));
01584 }
01585 
01586 void PPCFrameLowering::
01587 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
01588                               MachineBasicBlock::iterator I) const {
01589   const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
01590   if (MF.getTarget().Options.GuaranteedTailCallOpt &&
01591       I->getOpcode() == PPC::ADJCALLSTACKUP) {
01592     // Add (actually subtract) back the amount the callee popped on return.
01593     if (int CalleeAmt =  I->getOperand(1).getImm()) {
01594       bool is64Bit = Subtarget.isPPC64();
01595       CalleeAmt *= -1;
01596       unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1;
01597       unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0;
01598       unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI;
01599       unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4;
01600       unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS;
01601       unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI;
01602       MachineInstr *MI = I;
01603       DebugLoc dl = MI->getDebugLoc();
01604 
01605       if (isInt<16>(CalleeAmt)) {
01606         BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg)
01607           .addReg(StackReg, RegState::Kill)
01608           .addImm(CalleeAmt);
01609       } else {
01610         MachineBasicBlock::iterator MBBI = I;
01611         BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
01612           .addImm(CalleeAmt >> 16);
01613         BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
01614           .addReg(TmpReg, RegState::Kill)
01615           .addImm(CalleeAmt & 0xFFFF);
01616         BuildMI(MBB, MBBI, dl, TII.get(ADDInstr), StackReg)
01617           .addReg(StackReg, RegState::Kill)
01618           .addReg(TmpReg);
01619       }
01620     }
01621   }
01622   // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
01623   MBB.erase(I);
01624 }
01625 
01626 bool
01627 PPCFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
01628                                         MachineBasicBlock::iterator MI,
01629                                         const std::vector<CalleeSavedInfo> &CSI,
01630                                         const TargetRegisterInfo *TRI) const {
01631 
01632   // Currently, this function only handles SVR4 32- and 64-bit ABIs.
01633   // Return false otherwise to maintain pre-existing behavior.
01634   if (!Subtarget.isSVR4ABI())
01635     return false;
01636 
01637   MachineFunction *MF = MBB.getParent();
01638   const PPCInstrInfo &TII =
01639       *static_cast<const PPCInstrInfo *>(Subtarget.getInstrInfo());
01640   bool CR2Spilled = false;
01641   bool CR3Spilled = false;
01642   bool CR4Spilled = false;
01643   unsigned CSIIndex = 0;
01644 
01645   // Initialize insertion-point logic; we will be restoring in reverse
01646   // order of spill.
01647   MachineBasicBlock::iterator I = MI, BeforeI = I;
01648   bool AtStart = I == MBB.begin();
01649 
01650   if (!AtStart)
01651     --BeforeI;
01652 
01653   for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
01654     unsigned Reg = CSI[i].getReg();
01655 
01656     // Only Darwin actually uses the VRSAVE register, but it can still appear
01657     // here if, for example, @llvm.eh.unwind.init() is used.  If we're not on
01658     // Darwin, ignore it.
01659     if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI())
01660       continue;
01661 
01662     if (Reg == PPC::CR2) {
01663       CR2Spilled = true;
01664       // The spill slot is associated only with CR2, which is the
01665       // first nonvolatile spilled.  Save it here.
01666       CSIIndex = i;
01667       continue;
01668     } else if (Reg == PPC::CR3) {
01669       CR3Spilled = true;
01670       continue;
01671     } else if (Reg == PPC::CR4) {
01672       CR4Spilled = true;
01673       continue;
01674     } else {
01675       // When we first encounter a non-CR register after seeing at
01676       // least one CR register, restore all spilled CRs together.
01677       if ((CR2Spilled || CR3Spilled || CR4Spilled)
01678           && !(PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
01679         bool is31 = needsFP(*MF);
01680         restoreCRs(Subtarget.isPPC64(), is31,
01681                    CR2Spilled, CR3Spilled, CR4Spilled,
01682                    MBB, I, CSI, CSIIndex);
01683         CR2Spilled = CR3Spilled = CR4Spilled = false;
01684       }
01685 
01686       // Default behavior for non-CR saves.
01687       const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
01688       TII.loadRegFromStackSlot(MBB, I, Reg, CSI[i].getFrameIdx(),
01689                                RC, TRI);
01690       assert(I != MBB.begin() &&
01691              "loadRegFromStackSlot didn't insert any code!");
01692       }
01693 
01694     // Insert in reverse order.
01695     if (AtStart)
01696       I = MBB.begin();
01697     else {
01698       I = BeforeI;
01699       ++I;
01700     }
01701   }
01702 
01703   // If we haven't yet spilled the CRs, do so now.
01704   if (CR2Spilled || CR3Spilled || CR4Spilled) {
01705     bool is31 = needsFP(*MF);
01706     restoreCRs(Subtarget.isPPC64(), is31, CR2Spilled, CR3Spilled, CR4Spilled,
01707                MBB, I, CSI, CSIIndex);
01708   }
01709 
01710   return true;
01711 }