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PPCFrameLowering.cpp
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00001 //===-- PPCFrameLowering.cpp - PPC Frame Information ----------------------===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file contains the PPC implementation of TargetFrameLowering class.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #include "PPCFrameLowering.h"
00015 #include "PPCInstrBuilder.h"
00016 #include "PPCInstrInfo.h"
00017 #include "PPCMachineFunctionInfo.h"
00018 #include "llvm/CodeGen/MachineFrameInfo.h"
00019 #include "llvm/CodeGen/MachineFunction.h"
00020 #include "llvm/CodeGen/MachineInstrBuilder.h"
00021 #include "llvm/CodeGen/MachineModuleInfo.h"
00022 #include "llvm/CodeGen/MachineRegisterInfo.h"
00023 #include "llvm/CodeGen/RegisterScavenging.h"
00024 #include "llvm/IR/Function.h"
00025 #include "llvm/Target/TargetOptions.h"
00026 
00027 using namespace llvm;
00028 
00029 /// VRRegNo - Map from a numbered VR register to its enum value.
00030 ///
00031 static const uint16_t VRRegNo[] = {
00032  PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
00033  PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
00034  PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
00035  PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
00036 };
00037 
00038 /// RemoveVRSaveCode - We have found that this function does not need any code
00039 /// to manipulate the VRSAVE register, even though it uses vector registers.
00040 /// This can happen when the only registers used are known to be live in or out
00041 /// of the function.  Remove all of the VRSAVE related code from the function.
00042 /// FIXME: The removal of the code results in a compile failure at -O0 when the
00043 /// function contains a function call, as the GPR containing original VRSAVE
00044 /// contents is spilled and reloaded around the call.  Without the prolog code,
00045 /// the spill instruction refers to an undefined register.  This code needs
00046 /// to account for all uses of that GPR.
00047 static void RemoveVRSaveCode(MachineInstr *MI) {
00048   MachineBasicBlock *Entry = MI->getParent();
00049   MachineFunction *MF = Entry->getParent();
00050 
00051   // We know that the MTVRSAVE instruction immediately follows MI.  Remove it.
00052   MachineBasicBlock::iterator MBBI = MI;
00053   ++MBBI;
00054   assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
00055   MBBI->eraseFromParent();
00056 
00057   bool RemovedAllMTVRSAVEs = true;
00058   // See if we can find and remove the MTVRSAVE instruction from all of the
00059   // epilog blocks.
00060   for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
00061     // If last instruction is a return instruction, add an epilogue
00062     if (!I->empty() && I->back().isReturn()) {
00063       bool FoundIt = false;
00064       for (MBBI = I->end(); MBBI != I->begin(); ) {
00065         --MBBI;
00066         if (MBBI->getOpcode() == PPC::MTVRSAVE) {
00067           MBBI->eraseFromParent();  // remove it.
00068           FoundIt = true;
00069           break;
00070         }
00071       }
00072       RemovedAllMTVRSAVEs &= FoundIt;
00073     }
00074   }
00075 
00076   // If we found and removed all MTVRSAVE instructions, remove the read of
00077   // VRSAVE as well.
00078   if (RemovedAllMTVRSAVEs) {
00079     MBBI = MI;
00080     assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?");
00081     --MBBI;
00082     assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
00083     MBBI->eraseFromParent();
00084   }
00085 
00086   // Finally, nuke the UPDATE_VRSAVE.
00087   MI->eraseFromParent();
00088 }
00089 
00090 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
00091 // instruction selector.  Based on the vector registers that have been used,
00092 // transform this into the appropriate ORI instruction.
00093 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) {
00094   MachineFunction *MF = MI->getParent()->getParent();
00095   const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
00096   DebugLoc dl = MI->getDebugLoc();
00097 
00098   unsigned UsedRegMask = 0;
00099   for (unsigned i = 0; i != 32; ++i)
00100     if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i]))
00101       UsedRegMask |= 1 << (31-i);
00102 
00103   // Live in and live out values already must be in the mask, so don't bother
00104   // marking them.
00105   for (MachineRegisterInfo::livein_iterator
00106        I = MF->getRegInfo().livein_begin(),
00107        E = MF->getRegInfo().livein_end(); I != E; ++I) {
00108     unsigned RegNo = TRI->getEncodingValue(I->first);
00109     if (VRRegNo[RegNo] == I->first)        // If this really is a vector reg.
00110       UsedRegMask &= ~(1 << (31-RegNo));   // Doesn't need to be marked.
00111   }
00112 
00113   // Live out registers appear as use operands on return instructions.
00114   for (MachineFunction::const_iterator BI = MF->begin(), BE = MF->end();
00115        UsedRegMask != 0 && BI != BE; ++BI) {
00116     const MachineBasicBlock &MBB = *BI;
00117     if (MBB.empty() || !MBB.back().isReturn())
00118       continue;
00119     const MachineInstr &Ret = MBB.back();
00120     for (unsigned I = 0, E = Ret.getNumOperands(); I != E; ++I) {
00121       const MachineOperand &MO = Ret.getOperand(I);
00122       if (!MO.isReg() || !PPC::VRRCRegClass.contains(MO.getReg()))
00123         continue;
00124       unsigned RegNo = TRI->getEncodingValue(MO.getReg());
00125       UsedRegMask &= ~(1 << (31-RegNo));
00126     }
00127   }
00128 
00129   // If no registers are used, turn this into a copy.
00130   if (UsedRegMask == 0) {
00131     // Remove all VRSAVE code.
00132     RemoveVRSaveCode(MI);
00133     return;
00134   }
00135 
00136   unsigned SrcReg = MI->getOperand(1).getReg();
00137   unsigned DstReg = MI->getOperand(0).getReg();
00138 
00139   if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
00140     if (DstReg != SrcReg)
00141       BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
00142         .addReg(SrcReg)
00143         .addImm(UsedRegMask);
00144     else
00145       BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
00146         .addReg(SrcReg, RegState::Kill)
00147         .addImm(UsedRegMask);
00148   } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
00149     if (DstReg != SrcReg)
00150       BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
00151         .addReg(SrcReg)
00152         .addImm(UsedRegMask >> 16);
00153     else
00154       BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
00155         .addReg(SrcReg, RegState::Kill)
00156         .addImm(UsedRegMask >> 16);
00157   } else {
00158     if (DstReg != SrcReg)
00159       BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
00160         .addReg(SrcReg)
00161         .addImm(UsedRegMask >> 16);
00162     else
00163       BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
00164         .addReg(SrcReg, RegState::Kill)
00165         .addImm(UsedRegMask >> 16);
00166 
00167     BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
00168       .addReg(DstReg, RegState::Kill)
00169       .addImm(UsedRegMask & 0xFFFF);
00170   }
00171 
00172   // Remove the old UPDATE_VRSAVE instruction.
00173   MI->eraseFromParent();
00174 }
00175 
00176 static bool spillsCR(const MachineFunction &MF) {
00177   const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
00178   return FuncInfo->isCRSpilled();
00179 }
00180 
00181 static bool spillsVRSAVE(const MachineFunction &MF) {
00182   const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
00183   return FuncInfo->isVRSAVESpilled();
00184 }
00185 
00186 static bool hasSpills(const MachineFunction &MF) {
00187   const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
00188   return FuncInfo->hasSpills();
00189 }
00190 
00191 static bool hasNonRISpills(const MachineFunction &MF) {
00192   const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
00193   return FuncInfo->hasNonRISpills();
00194 }
00195 
00196 /// determineFrameLayout - Determine the size of the frame and maximum call
00197 /// frame size.
00198 unsigned PPCFrameLowering::determineFrameLayout(MachineFunction &MF,
00199                                                 bool UpdateMF,
00200                                                 bool UseEstimate) const {
00201   MachineFrameInfo *MFI = MF.getFrameInfo();
00202 
00203   // Get the number of bytes to allocate from the FrameInfo
00204   unsigned FrameSize =
00205     UseEstimate ? MFI->estimateStackSize(MF) : MFI->getStackSize();
00206 
00207   // Get stack alignments. The frame must be aligned to the greatest of these:
00208   unsigned TargetAlign = getStackAlignment(); // alignment required per the ABI
00209   unsigned MaxAlign = MFI->getMaxAlignment(); // algmt required by data in frame
00210   unsigned AlignMask = std::max(MaxAlign, TargetAlign) - 1;
00211 
00212   const PPCRegisterInfo *RegInfo =
00213     static_cast<const PPCRegisterInfo*>(MF.getTarget().getRegisterInfo());
00214 
00215   // If we are a leaf function, and use up to 224 bytes of stack space,
00216   // don't have a frame pointer, calls, or dynamic alloca then we do not need
00217   // to adjust the stack pointer (we fit in the Red Zone).
00218   // The 32-bit SVR4 ABI has no Red Zone. However, it can still generate
00219   // stackless code if all local vars are reg-allocated.
00220   bool DisableRedZone = MF.getFunction()->getAttributes().
00221     hasAttribute(AttributeSet::FunctionIndex, Attribute::NoRedZone);
00222   if (!DisableRedZone &&
00223       (Subtarget.isPPC64() ||                      // 32-bit SVR4, no stack-
00224        !Subtarget.isSVR4ABI() ||                   //   allocated locals.
00225   FrameSize == 0) &&
00226       FrameSize <= 224 &&                          // Fits in red zone.
00227       !MFI->hasVarSizedObjects() &&                // No dynamic alloca.
00228       !MFI->adjustsStack() &&                      // No calls.
00229       !RegInfo->hasBasePointer(MF)) { // No special alignment.
00230     // No need for frame
00231     if (UpdateMF)
00232       MFI->setStackSize(0);
00233     return 0;
00234   }
00235 
00236   // Get the maximum call frame size of all the calls.
00237   unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
00238 
00239   // Maximum call frame needs to be at least big enough for linkage and 8 args.
00240   unsigned minCallFrameSize = getMinCallFrameSize(Subtarget.isPPC64(),
00241                                                   Subtarget.isDarwinABI());
00242   maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);
00243 
00244   // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
00245   // that allocations will be aligned.
00246   if (MFI->hasVarSizedObjects())
00247     maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
00248 
00249   // Update maximum call frame size.
00250   if (UpdateMF)
00251     MFI->setMaxCallFrameSize(maxCallFrameSize);
00252 
00253   // Include call frame size in total.
00254   FrameSize += maxCallFrameSize;
00255 
00256   // Make sure the frame is aligned.
00257   FrameSize = (FrameSize + AlignMask) & ~AlignMask;
00258 
00259   // Update frame info.
00260   if (UpdateMF)
00261     MFI->setStackSize(FrameSize);
00262 
00263   return FrameSize;
00264 }
00265 
00266 // hasFP - Return true if the specified function actually has a dedicated frame
00267 // pointer register.
00268 bool PPCFrameLowering::hasFP(const MachineFunction &MF) const {
00269   const MachineFrameInfo *MFI = MF.getFrameInfo();
00270   // FIXME: This is pretty much broken by design: hasFP() might be called really
00271   // early, before the stack layout was calculated and thus hasFP() might return
00272   // true or false here depending on the time of call.
00273   return (MFI->getStackSize()) && needsFP(MF);
00274 }
00275 
00276 // needsFP - Return true if the specified function should have a dedicated frame
00277 // pointer register.  This is true if the function has variable sized allocas or
00278 // if frame pointer elimination is disabled.
00279 bool PPCFrameLowering::needsFP(const MachineFunction &MF) const {
00280   const MachineFrameInfo *MFI = MF.getFrameInfo();
00281 
00282   // Naked functions have no stack frame pushed, so we don't have a frame
00283   // pointer.
00284   if (MF.getFunction()->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
00285                                                      Attribute::Naked))
00286     return false;
00287 
00288   return MF.getTarget().Options.DisableFramePointerElim(MF) ||
00289     MFI->hasVarSizedObjects() ||
00290     (MF.getTarget().Options.GuaranteedTailCallOpt &&
00291      MF.getInfo<PPCFunctionInfo>()->hasFastCall());
00292 }
00293 
00294 void PPCFrameLowering::replaceFPWithRealFP(MachineFunction &MF) const {
00295   bool is31 = needsFP(MF);
00296   unsigned FPReg  = is31 ? PPC::R31 : PPC::R1;
00297   unsigned FP8Reg = is31 ? PPC::X31 : PPC::X1;
00298 
00299   const PPCRegisterInfo *RegInfo =
00300     static_cast<const PPCRegisterInfo*>(MF.getTarget().getRegisterInfo());
00301   bool HasBP = RegInfo->hasBasePointer(MF);
00302   unsigned BPReg  = HasBP ? (unsigned) PPC::R30 : FPReg;
00303   unsigned BP8Reg = HasBP ? (unsigned) PPC::X30 : FPReg;
00304 
00305   for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
00306        BI != BE; ++BI)
00307     for (MachineBasicBlock::iterator MBBI = BI->end(); MBBI != BI->begin(); ) {
00308       --MBBI;
00309       for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) {
00310         MachineOperand &MO = MBBI->getOperand(I);
00311         if (!MO.isReg())
00312           continue;
00313 
00314         switch (MO.getReg()) {
00315         case PPC::FP:
00316           MO.setReg(FPReg);
00317           break;
00318         case PPC::FP8:
00319           MO.setReg(FP8Reg);
00320           break;
00321         case PPC::BP:
00322           MO.setReg(BPReg);
00323           break;
00324         case PPC::BP8:
00325           MO.setReg(BP8Reg);
00326           break;
00327 
00328         }
00329       }
00330     }
00331 }
00332 
00333 void PPCFrameLowering::emitPrologue(MachineFunction &MF) const {
00334   MachineBasicBlock &MBB = MF.front();   // Prolog goes in entry BB
00335   MachineBasicBlock::iterator MBBI = MBB.begin();
00336   MachineFrameInfo *MFI = MF.getFrameInfo();
00337   const PPCInstrInfo &TII =
00338     *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo());
00339   const PPCRegisterInfo *RegInfo =
00340     static_cast<const PPCRegisterInfo*>(MF.getTarget().getRegisterInfo());
00341 
00342   MachineModuleInfo &MMI = MF.getMMI();
00343   const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
00344   DebugLoc dl;
00345   bool needsFrameMoves = MMI.hasDebugInfo() ||
00346     MF.getFunction()->needsUnwindTableEntry();
00347 
00348   // Get processor type.
00349   bool isPPC64 = Subtarget.isPPC64();
00350   // Get the ABI.
00351   bool isDarwinABI = Subtarget.isDarwinABI();
00352   bool isSVR4ABI = Subtarget.isSVR4ABI();
00353   assert((isDarwinABI || isSVR4ABI) &&
00354          "Currently only Darwin and SVR4 ABIs are supported for PowerPC.");
00355 
00356   // Scan the prolog, looking for an UPDATE_VRSAVE instruction.  If we find it,
00357   // process it.
00358   if (!isSVR4ABI)
00359     for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
00360       if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
00361         HandleVRSaveUpdate(MBBI, TII);
00362         break;
00363       }
00364     }
00365 
00366   // Move MBBI back to the beginning of the function.
00367   MBBI = MBB.begin();
00368 
00369   // Work out frame sizes.
00370   unsigned FrameSize = determineFrameLayout(MF);
00371   int NegFrameSize = -FrameSize;
00372   if (!isInt<32>(NegFrameSize))
00373     llvm_unreachable("Unhandled stack size!");
00374 
00375   if (MFI->isFrameAddressTaken())
00376     replaceFPWithRealFP(MF);
00377 
00378   // Check if the link register (LR) must be saved.
00379   PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
00380   bool MustSaveLR = FI->mustSaveLR();
00381   const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs();
00382   // Do we have a frame pointer and/or base pointer for this function?
00383   bool HasFP = hasFP(MF);
00384   bool HasBP = RegInfo->hasBasePointer(MF);
00385 
00386   unsigned SPReg       = isPPC64 ? PPC::X1  : PPC::R1;
00387   unsigned BPReg       = isPPC64 ? PPC::X30 : PPC::R30;
00388   unsigned FPReg       = isPPC64 ? PPC::X31 : PPC::R31;
00389   unsigned LRReg       = isPPC64 ? PPC::LR8 : PPC::LR;
00390   unsigned ScratchReg  = isPPC64 ? PPC::X0  : PPC::R0;
00391   unsigned TempReg     = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
00392   //  ...(R12/X12 is volatile in both Darwin & SVR4, & can't be a function arg.)
00393   const MCInstrDesc& MFLRInst = TII.get(isPPC64 ? PPC::MFLR8
00394                                                 : PPC::MFLR );
00395   const MCInstrDesc& StoreInst = TII.get(isPPC64 ? PPC::STD
00396                                                  : PPC::STW );
00397   const MCInstrDesc& StoreUpdtInst = TII.get(isPPC64 ? PPC::STDU
00398                                                      : PPC::STWU );
00399   const MCInstrDesc& StoreUpdtIdxInst = TII.get(isPPC64 ? PPC::STDUX
00400                                                         : PPC::STWUX);
00401   const MCInstrDesc& LoadImmShiftedInst = TII.get(isPPC64 ? PPC::LIS8
00402                                                           : PPC::LIS );
00403   const MCInstrDesc& OrImmInst = TII.get(isPPC64 ? PPC::ORI8
00404                                                  : PPC::ORI );
00405   const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8
00406                                               : PPC::OR );
00407   const MCInstrDesc& SubtractCarryingInst = TII.get(isPPC64 ? PPC::SUBFC8
00408                                                             : PPC::SUBFC);
00409   const MCInstrDesc& SubtractImmCarryingInst = TII.get(isPPC64 ? PPC::SUBFIC8
00410                                                                : PPC::SUBFIC);
00411 
00412   // Regarding this assert: Even though LR is saved in the caller's frame (i.e.,
00413   // LROffset is positive), that slot is callee-owned. Because PPC32 SVR4 has no
00414   // Red Zone, an asynchronous event (a form of "callee") could claim a frame &
00415   // overwrite it, so PPC32 SVR4 must claim at least a minimal frame to save LR.
00416   assert((isPPC64 || !isSVR4ABI || !(!FrameSize && (MustSaveLR || HasFP))) &&
00417          "FrameSize must be >0 to save/restore the FP or LR for 32-bit SVR4.");
00418 
00419   int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
00420 
00421   int FPOffset = 0;
00422   if (HasFP) {
00423     if (isSVR4ABI) {
00424       MachineFrameInfo *FFI = MF.getFrameInfo();
00425       int FPIndex = FI->getFramePointerSaveIndex();
00426       assert(FPIndex && "No Frame Pointer Save Slot!");
00427       FPOffset = FFI->getObjectOffset(FPIndex);
00428     } else {
00429       FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
00430     }
00431   }
00432 
00433   int BPOffset = 0;
00434   if (HasBP) {
00435     if (isSVR4ABI) {
00436       MachineFrameInfo *FFI = MF.getFrameInfo();
00437       int BPIndex = FI->getBasePointerSaveIndex();
00438       assert(BPIndex && "No Base Pointer Save Slot!");
00439       BPOffset = FFI->getObjectOffset(BPIndex);
00440     } else {
00441       BPOffset =
00442         PPCFrameLowering::getBasePointerSaveOffset(isPPC64, isDarwinABI);
00443     }
00444   }
00445 
00446   // Get stack alignments.
00447   unsigned MaxAlign = MFI->getMaxAlignment();
00448   if (HasBP && MaxAlign > 1)
00449     assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) &&
00450            "Invalid alignment!");
00451 
00452   // Frames of 32KB & larger require special handling because they cannot be
00453   // indexed into with a simple STDU/STWU/STD/STW immediate offset operand.
00454   bool isLargeFrame = !isInt<16>(NegFrameSize);
00455 
00456   if (MustSaveLR)
00457     BuildMI(MBB, MBBI, dl, MFLRInst, ScratchReg);
00458 
00459   assert((isPPC64 || MustSaveCRs.empty()) &&
00460          "Prologue CR saving supported only in 64-bit mode");
00461 
00462   if (!MustSaveCRs.empty()) { // will only occur for PPC64
00463     MachineInstrBuilder MIB =
00464       BuildMI(MBB, MBBI, dl, TII.get(PPC::MFCR8), TempReg);
00465     for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
00466       MIB.addReg(MustSaveCRs[i], RegState::ImplicitKill);
00467   }
00468 
00469   if (HasFP)
00470     // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
00471     BuildMI(MBB, MBBI, dl, StoreInst)
00472       .addReg(FPReg)
00473       .addImm(FPOffset)
00474       .addReg(SPReg);
00475 
00476   if (HasBP)
00477     // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
00478     BuildMI(MBB, MBBI, dl, StoreInst)
00479       .addReg(BPReg)
00480       .addImm(BPOffset)
00481       .addReg(SPReg);
00482 
00483   if (MustSaveLR)
00484     // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
00485     BuildMI(MBB, MBBI, dl, StoreInst)
00486       .addReg(ScratchReg)
00487       .addImm(LROffset)
00488       .addReg(SPReg);
00489 
00490   if (!MustSaveCRs.empty()) // will only occur for PPC64
00491     BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8))
00492       .addReg(TempReg, getKillRegState(true))
00493       .addImm(8)
00494       .addReg(SPReg);
00495 
00496   // Skip the rest if this is a leaf function & all spills fit in the Red Zone.
00497   if (!FrameSize) return;
00498 
00499   // Adjust stack pointer: r1 += NegFrameSize.
00500   // If there is a preferred stack alignment, align R1 now
00501 
00502   if (HasBP) {
00503     // Save a copy of r1 as the base pointer.
00504     BuildMI(MBB, MBBI, dl, OrInst, BPReg)
00505       .addReg(SPReg)
00506       .addReg(SPReg);
00507   }
00508 
00509   if (HasBP && MaxAlign > 1) {
00510     if (isPPC64)
00511       BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), ScratchReg)
00512         .addReg(SPReg)
00513         .addImm(0)
00514         .addImm(64 - Log2_32(MaxAlign));
00515     else // PPC32...
00516       BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), ScratchReg)
00517         .addReg(SPReg)
00518         .addImm(0)
00519         .addImm(32 - Log2_32(MaxAlign))
00520         .addImm(31);
00521     if (!isLargeFrame) {
00522       BuildMI(MBB, MBBI, dl, SubtractImmCarryingInst, ScratchReg)
00523         .addReg(ScratchReg, RegState::Kill)
00524         .addImm(NegFrameSize);
00525     } else {
00526       BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, TempReg)
00527         .addImm(NegFrameSize >> 16);
00528       BuildMI(MBB, MBBI, dl, OrImmInst, TempReg)
00529         .addReg(TempReg, RegState::Kill)
00530         .addImm(NegFrameSize & 0xFFFF);
00531       BuildMI(MBB, MBBI, dl, SubtractCarryingInst, ScratchReg)
00532         .addReg(ScratchReg, RegState::Kill)
00533         .addReg(TempReg, RegState::Kill);
00534     }
00535     BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg)
00536       .addReg(SPReg, RegState::Kill)
00537       .addReg(SPReg)
00538       .addReg(ScratchReg);
00539 
00540   } else if (!isLargeFrame) {
00541     BuildMI(MBB, MBBI, dl, StoreUpdtInst, SPReg)
00542       .addReg(SPReg)
00543       .addImm(NegFrameSize)
00544       .addReg(SPReg);
00545 
00546   } else {
00547     BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
00548       .addImm(NegFrameSize >> 16);
00549     BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
00550       .addReg(ScratchReg, RegState::Kill)
00551       .addImm(NegFrameSize & 0xFFFF);
00552     BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg)
00553       .addReg(SPReg, RegState::Kill)
00554       .addReg(SPReg)
00555       .addReg(ScratchReg);
00556   }
00557 
00558   // Add the "machine moves" for the instructions we generated above, but in
00559   // reverse order.
00560   if (needsFrameMoves) {
00561     // Show update of SP.
00562     assert(NegFrameSize);
00563     unsigned CFIIndex = MMI.addFrameInst(
00564         MCCFIInstruction::createDefCfaOffset(nullptr, NegFrameSize));
00565     BuildMI(MBB, MBBI, dl, TII.get(PPC::CFI_INSTRUCTION)).addCFIIndex(CFIIndex);
00566 
00567     if (HasFP) {
00568       unsigned Reg = MRI->getDwarfRegNum(FPReg, true);
00569       CFIIndex = MMI.addFrameInst(
00570           MCCFIInstruction::createOffset(nullptr, Reg, FPOffset));
00571       BuildMI(MBB, MBBI, dl, TII.get(PPC::CFI_INSTRUCTION))
00572           .addCFIIndex(CFIIndex);
00573     }
00574 
00575     if (HasBP) {
00576       unsigned Reg = MRI->getDwarfRegNum(BPReg, true);
00577       CFIIndex = MMI.addFrameInst(
00578           MCCFIInstruction::createOffset(nullptr, Reg, BPOffset));
00579       BuildMI(MBB, MBBI, dl, TII.get(PPC::CFI_INSTRUCTION))
00580           .addCFIIndex(CFIIndex);
00581     }
00582 
00583     if (MustSaveLR) {
00584       unsigned Reg = MRI->getDwarfRegNum(LRReg, true);
00585       CFIIndex = MMI.addFrameInst(
00586           MCCFIInstruction::createOffset(nullptr, Reg, LROffset));
00587       BuildMI(MBB, MBBI, dl, TII.get(PPC::CFI_INSTRUCTION))
00588           .addCFIIndex(CFIIndex);
00589     }
00590   }
00591 
00592   // If there is a frame pointer, copy R1 into R31
00593   if (HasFP) {
00594     BuildMI(MBB, MBBI, dl, OrInst, FPReg)
00595       .addReg(SPReg)
00596       .addReg(SPReg);
00597 
00598     if (needsFrameMoves) {
00599       // Mark effective beginning of when frame pointer is ready.
00600       unsigned Reg = MRI->getDwarfRegNum(FPReg, true);
00601       unsigned CFIIndex = MMI.addFrameInst(
00602           MCCFIInstruction::createDefCfaRegister(nullptr, Reg));
00603 
00604       BuildMI(MBB, MBBI, dl, TII.get(PPC::CFI_INSTRUCTION))
00605           .addCFIIndex(CFIIndex);
00606     }
00607   }
00608 
00609   if (needsFrameMoves) {
00610     // Add callee saved registers to move list.
00611     const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
00612     for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
00613       unsigned Reg = CSI[I].getReg();
00614       if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue;
00615 
00616       // This is a bit of a hack: CR2LT, CR2GT, CR2EQ and CR2UN are just
00617       // subregisters of CR2. We just need to emit a move of CR2.
00618       if (PPC::CRBITRCRegClass.contains(Reg))
00619         continue;
00620 
00621       // For SVR4, don't emit a move for the CR spill slot if we haven't
00622       // spilled CRs.
00623       if (isSVR4ABI && (PPC::CR2 <= Reg && Reg <= PPC::CR4)
00624           && MustSaveCRs.empty())
00625         continue;
00626 
00627       // For 64-bit SVR4 when we have spilled CRs, the spill location
00628       // is SP+8, not a frame-relative slot.
00629       if (isSVR4ABI && isPPC64 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
00630         unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
00631             nullptr, MRI->getDwarfRegNum(PPC::CR2, true), 8));
00632         BuildMI(MBB, MBBI, dl, TII.get(PPC::CFI_INSTRUCTION))
00633             .addCFIIndex(CFIIndex);
00634         continue;
00635       }
00636 
00637       int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
00638       unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
00639           nullptr, MRI->getDwarfRegNum(Reg, true), Offset));
00640       BuildMI(MBB, MBBI, dl, TII.get(PPC::CFI_INSTRUCTION))
00641           .addCFIIndex(CFIIndex);
00642     }
00643   }
00644 }
00645 
00646 void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
00647                                 MachineBasicBlock &MBB) const {
00648   MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
00649   assert(MBBI != MBB.end() && "Returning block has no terminator");
00650   const PPCInstrInfo &TII =
00651     *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo());
00652   const PPCRegisterInfo *RegInfo =
00653     static_cast<const PPCRegisterInfo*>(MF.getTarget().getRegisterInfo());
00654 
00655   unsigned RetOpcode = MBBI->getOpcode();
00656   DebugLoc dl;
00657 
00658   assert((RetOpcode == PPC::BLR ||
00659           RetOpcode == PPC::TCRETURNri ||
00660           RetOpcode == PPC::TCRETURNdi ||
00661           RetOpcode == PPC::TCRETURNai ||
00662           RetOpcode == PPC::TCRETURNri8 ||
00663           RetOpcode == PPC::TCRETURNdi8 ||
00664           RetOpcode == PPC::TCRETURNai8) &&
00665          "Can only insert epilog into returning blocks");
00666 
00667   // Get alignment info so we know how to restore the SP.
00668   const MachineFrameInfo *MFI = MF.getFrameInfo();
00669 
00670   // Get the number of bytes allocated from the FrameInfo.
00671   int FrameSize = MFI->getStackSize();
00672 
00673   // Get processor type.
00674   bool isPPC64 = Subtarget.isPPC64();
00675   // Get the ABI.
00676   bool isDarwinABI = Subtarget.isDarwinABI();
00677   bool isSVR4ABI = Subtarget.isSVR4ABI();
00678 
00679   // Check if the link register (LR) has been saved.
00680   PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
00681   bool MustSaveLR = FI->mustSaveLR();
00682   const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs();
00683   // Do we have a frame pointer and/or base pointer for this function?
00684   bool HasFP = hasFP(MF);
00685   bool HasBP = RegInfo->hasBasePointer(MF);
00686 
00687   unsigned SPReg      = isPPC64 ? PPC::X1  : PPC::R1;
00688   unsigned BPReg      = isPPC64 ? PPC::X30 : PPC::R30;
00689   unsigned FPReg      = isPPC64 ? PPC::X31 : PPC::R31;
00690   unsigned ScratchReg  = isPPC64 ? PPC::X0  : PPC::R0;
00691   unsigned TempReg     = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
00692   const MCInstrDesc& MTLRInst = TII.get( isPPC64 ? PPC::MTLR8
00693                                                  : PPC::MTLR );
00694   const MCInstrDesc& LoadInst = TII.get( isPPC64 ? PPC::LD
00695                                                  : PPC::LWZ );
00696   const MCInstrDesc& LoadImmShiftedInst = TII.get( isPPC64 ? PPC::LIS8
00697                                                            : PPC::LIS );
00698   const MCInstrDesc& OrImmInst = TII.get( isPPC64 ? PPC::ORI8
00699                                                   : PPC::ORI );
00700   const MCInstrDesc& AddImmInst = TII.get( isPPC64 ? PPC::ADDI8
00701                                                    : PPC::ADDI );
00702   const MCInstrDesc& AddInst = TII.get( isPPC64 ? PPC::ADD8
00703                                                 : PPC::ADD4 );
00704 
00705   int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
00706 
00707   int FPOffset = 0;
00708   if (HasFP) {
00709     if (isSVR4ABI) {
00710       MachineFrameInfo *FFI = MF.getFrameInfo();
00711       int FPIndex = FI->getFramePointerSaveIndex();
00712       assert(FPIndex && "No Frame Pointer Save Slot!");
00713       FPOffset = FFI->getObjectOffset(FPIndex);
00714     } else {
00715       FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
00716     }
00717   }
00718 
00719   int BPOffset = 0;
00720   if (HasBP) {
00721     if (isSVR4ABI) {
00722       MachineFrameInfo *FFI = MF.getFrameInfo();
00723       int BPIndex = FI->getBasePointerSaveIndex();
00724       assert(BPIndex && "No Base Pointer Save Slot!");
00725       BPOffset = FFI->getObjectOffset(BPIndex);
00726     } else {
00727       BPOffset =
00728         PPCFrameLowering::getBasePointerSaveOffset(isPPC64, isDarwinABI);
00729     }
00730   }
00731 
00732   bool UsesTCRet =  RetOpcode == PPC::TCRETURNri ||
00733     RetOpcode == PPC::TCRETURNdi ||
00734     RetOpcode == PPC::TCRETURNai ||
00735     RetOpcode == PPC::TCRETURNri8 ||
00736     RetOpcode == PPC::TCRETURNdi8 ||
00737     RetOpcode == PPC::TCRETURNai8;
00738 
00739   if (UsesTCRet) {
00740     int MaxTCRetDelta = FI->getTailCallSPDelta();
00741     MachineOperand &StackAdjust = MBBI->getOperand(1);
00742     assert(StackAdjust.isImm() && "Expecting immediate value.");
00743     // Adjust stack pointer.
00744     int StackAdj = StackAdjust.getImm();
00745     int Delta = StackAdj - MaxTCRetDelta;
00746     assert((Delta >= 0) && "Delta must be positive");
00747     if (MaxTCRetDelta>0)
00748       FrameSize += (StackAdj +Delta);
00749     else
00750       FrameSize += StackAdj;
00751   }
00752 
00753   // Frames of 32KB & larger require special handling because they cannot be
00754   // indexed into with a simple LD/LWZ immediate offset operand.
00755   bool isLargeFrame = !isInt<16>(FrameSize);
00756 
00757   if (FrameSize) {
00758     // In the prologue, the loaded (or persistent) stack pointer value is offset
00759     // by the STDU/STDUX/STWU/STWUX instruction.  Add this offset back now.
00760 
00761     // If this function contained a fastcc call and GuaranteedTailCallOpt is
00762     // enabled (=> hasFastCall()==true) the fastcc call might contain a tail
00763     // call which invalidates the stack pointer value in SP(0). So we use the
00764     // value of R31 in this case.
00765     if (FI->hasFastCall()) {
00766       assert(HasFP && "Expecting a valid frame pointer.");
00767       if (!isLargeFrame) {
00768         BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
00769           .addReg(FPReg).addImm(FrameSize);
00770       } else {
00771         BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
00772           .addImm(FrameSize >> 16);
00773         BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
00774           .addReg(ScratchReg, RegState::Kill)
00775           .addImm(FrameSize & 0xFFFF);
00776         BuildMI(MBB, MBBI, dl, AddInst)
00777           .addReg(SPReg)
00778           .addReg(FPReg)
00779           .addReg(ScratchReg);
00780       }
00781     } else if (!isLargeFrame && !HasBP && !MFI->hasVarSizedObjects()) {
00782       BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
00783         .addReg(SPReg)
00784         .addImm(FrameSize);
00785     } else {
00786       BuildMI(MBB, MBBI, dl, LoadInst, SPReg)
00787         .addImm(0)
00788         .addReg(SPReg);
00789     }
00790 
00791   }
00792 
00793   if (MustSaveLR)
00794     BuildMI(MBB, MBBI, dl, LoadInst, ScratchReg)
00795       .addImm(LROffset)
00796       .addReg(SPReg);
00797 
00798   assert((isPPC64 || MustSaveCRs.empty()) &&
00799          "Epilogue CR restoring supported only in 64-bit mode");
00800 
00801   if (!MustSaveCRs.empty()) // will only occur for PPC64
00802     BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg)
00803       .addImm(8)
00804       .addReg(SPReg);
00805 
00806   if (HasFP)
00807     BuildMI(MBB, MBBI, dl, LoadInst, FPReg)
00808       .addImm(FPOffset)
00809       .addReg(SPReg);
00810 
00811   if (HasBP)
00812     BuildMI(MBB, MBBI, dl, LoadInst, BPReg)
00813       .addImm(BPOffset)
00814       .addReg(SPReg);
00815 
00816   if (!MustSaveCRs.empty()) // will only occur for PPC64
00817     for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
00818       BuildMI(MBB, MBBI, dl, TII.get(PPC::MTOCRF8), MustSaveCRs[i])
00819         .addReg(TempReg, getKillRegState(i == e-1));
00820 
00821   if (MustSaveLR)
00822     BuildMI(MBB, MBBI, dl, MTLRInst).addReg(ScratchReg);
00823 
00824   // Callee pop calling convention. Pop parameter/linkage area. Used for tail
00825   // call optimization
00826   if (MF.getTarget().Options.GuaranteedTailCallOpt && RetOpcode == PPC::BLR &&
00827       MF.getFunction()->getCallingConv() == CallingConv::Fast) {
00828      PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
00829      unsigned CallerAllocatedAmt = FI->getMinReservedArea();
00830 
00831      if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) {
00832        BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
00833          .addReg(SPReg).addImm(CallerAllocatedAmt);
00834      } else {
00835        BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
00836           .addImm(CallerAllocatedAmt >> 16);
00837        BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
00838           .addReg(ScratchReg, RegState::Kill)
00839           .addImm(CallerAllocatedAmt & 0xFFFF);
00840        BuildMI(MBB, MBBI, dl, AddInst)
00841           .addReg(SPReg)
00842           .addReg(FPReg)
00843           .addReg(ScratchReg);
00844      }
00845   } else if (RetOpcode == PPC::TCRETURNdi) {
00846     MBBI = MBB.getLastNonDebugInstr();
00847     MachineOperand &JumpTarget = MBBI->getOperand(0);
00848     BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)).
00849       addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
00850   } else if (RetOpcode == PPC::TCRETURNri) {
00851     MBBI = MBB.getLastNonDebugInstr();
00852     assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
00853     BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR));
00854   } else if (RetOpcode == PPC::TCRETURNai) {
00855     MBBI = MBB.getLastNonDebugInstr();
00856     MachineOperand &JumpTarget = MBBI->getOperand(0);
00857     BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm());
00858   } else if (RetOpcode == PPC::TCRETURNdi8) {
00859     MBBI = MBB.getLastNonDebugInstr();
00860     MachineOperand &JumpTarget = MBBI->getOperand(0);
00861     BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)).
00862       addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
00863   } else if (RetOpcode == PPC::TCRETURNri8) {
00864     MBBI = MBB.getLastNonDebugInstr();
00865     assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
00866     BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8));
00867   } else if (RetOpcode == PPC::TCRETURNai8) {
00868     MBBI = MBB.getLastNonDebugInstr();
00869     MachineOperand &JumpTarget = MBBI->getOperand(0);
00870     BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm());
00871   }
00872 }
00873 
00874 /// MustSaveLR - Return true if this function requires that we save the LR
00875 /// register onto the stack in the prolog and restore it in the epilog of the
00876 /// function.
00877 static bool MustSaveLR(const MachineFunction &MF, unsigned LR) {
00878   const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>();
00879 
00880   // We need a save/restore of LR if there is any def of LR (which is
00881   // defined by calls, including the PIC setup sequence), or if there is
00882   // some use of the LR stack slot (e.g. for builtin_return_address).
00883   // (LR comes in 32 and 64 bit versions.)
00884   MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR);
00885   return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired();
00886 }
00887 
00888 void
00889 PPCFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
00890                                                    RegScavenger *) const {
00891   const PPCRegisterInfo *RegInfo =
00892     static_cast<const PPCRegisterInfo*>(MF.getTarget().getRegisterInfo());
00893 
00894   //  Save and clear the LR state.
00895   PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
00896   unsigned LR = RegInfo->getRARegister();
00897   FI->setMustSaveLR(MustSaveLR(MF, LR));
00898   MachineRegisterInfo &MRI = MF.getRegInfo();
00899   MRI.setPhysRegUnused(LR);
00900 
00901   //  Save R31 if necessary
00902   int FPSI = FI->getFramePointerSaveIndex();
00903   bool isPPC64 = Subtarget.isPPC64();
00904   bool isDarwinABI  = Subtarget.isDarwinABI();
00905   MachineFrameInfo *MFI = MF.getFrameInfo();
00906 
00907   // If the frame pointer save index hasn't been defined yet.
00908   if (!FPSI && needsFP(MF)) {
00909     // Find out what the fix offset of the frame pointer save area.
00910     int FPOffset = getFramePointerSaveOffset(isPPC64, isDarwinABI);
00911     // Allocate the frame index for frame pointer save area.
00912     FPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
00913     // Save the result.
00914     FI->setFramePointerSaveIndex(FPSI);
00915   }
00916 
00917   int BPSI = FI->getBasePointerSaveIndex();
00918   if (!BPSI && RegInfo->hasBasePointer(MF)) {
00919     int BPOffset = getBasePointerSaveOffset(isPPC64, isDarwinABI);
00920     // Allocate the frame index for the base pointer save area.
00921     BPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, BPOffset, true);
00922     // Save the result.
00923     FI->setBasePointerSaveIndex(BPSI);
00924   }
00925 
00926   // Reserve stack space to move the linkage area to in case of a tail call.
00927   int TCSPDelta = 0;
00928   if (MF.getTarget().Options.GuaranteedTailCallOpt &&
00929       (TCSPDelta = FI->getTailCallSPDelta()) < 0) {
00930     MFI->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true);
00931   }
00932 
00933   // For 32-bit SVR4, allocate the nonvolatile CR spill slot iff the 
00934   // function uses CR 2, 3, or 4.
00935   if (!isPPC64 && !isDarwinABI && 
00936       (MRI.isPhysRegUsed(PPC::CR2) ||
00937        MRI.isPhysRegUsed(PPC::CR3) ||
00938        MRI.isPhysRegUsed(PPC::CR4))) {
00939     int FrameIdx = MFI->CreateFixedObject((uint64_t)4, (int64_t)-4, true);
00940     FI->setCRSpillFrameIndex(FrameIdx);
00941   }
00942 }
00943 
00944 void PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF,
00945                                                        RegScavenger *RS) const {
00946   // Early exit if not using the SVR4 ABI.
00947   if (!Subtarget.isSVR4ABI()) {
00948     addScavengingSpillSlot(MF, RS);
00949     return;
00950   }
00951 
00952   // Get callee saved register information.
00953   MachineFrameInfo *FFI = MF.getFrameInfo();
00954   const std::vector<CalleeSavedInfo> &CSI = FFI->getCalleeSavedInfo();
00955 
00956   // Early exit if no callee saved registers are modified!
00957   if (CSI.empty() && !needsFP(MF)) {
00958     addScavengingSpillSlot(MF, RS);
00959     return;
00960   }
00961 
00962   unsigned MinGPR = PPC::R31;
00963   unsigned MinG8R = PPC::X31;
00964   unsigned MinFPR = PPC::F31;
00965   unsigned MinVR = PPC::V31;
00966 
00967   bool HasGPSaveArea = false;
00968   bool HasG8SaveArea = false;
00969   bool HasFPSaveArea = false;
00970   bool HasVRSAVESaveArea = false;
00971   bool HasVRSaveArea = false;
00972 
00973   SmallVector<CalleeSavedInfo, 18> GPRegs;
00974   SmallVector<CalleeSavedInfo, 18> G8Regs;
00975   SmallVector<CalleeSavedInfo, 18> FPRegs;
00976   SmallVector<CalleeSavedInfo, 18> VRegs;
00977 
00978   for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
00979     unsigned Reg = CSI[i].getReg();
00980     if (PPC::GPRCRegClass.contains(Reg)) {
00981       HasGPSaveArea = true;
00982 
00983       GPRegs.push_back(CSI[i]);
00984 
00985       if (Reg < MinGPR) {
00986         MinGPR = Reg;
00987       }
00988     } else if (PPC::G8RCRegClass.contains(Reg)) {
00989       HasG8SaveArea = true;
00990 
00991       G8Regs.push_back(CSI[i]);
00992 
00993       if (Reg < MinG8R) {
00994         MinG8R = Reg;
00995       }
00996     } else if (PPC::F8RCRegClass.contains(Reg)) {
00997       HasFPSaveArea = true;
00998 
00999       FPRegs.push_back(CSI[i]);
01000 
01001       if (Reg < MinFPR) {
01002         MinFPR = Reg;
01003       }
01004     } else if (PPC::CRBITRCRegClass.contains(Reg) ||
01005                PPC::CRRCRegClass.contains(Reg)) {
01006       ; // do nothing, as we already know whether CRs are spilled
01007     } else if (PPC::VRSAVERCRegClass.contains(Reg)) {
01008       HasVRSAVESaveArea = true;
01009     } else if (PPC::VRRCRegClass.contains(Reg)) {
01010       HasVRSaveArea = true;
01011 
01012       VRegs.push_back(CSI[i]);
01013 
01014       if (Reg < MinVR) {
01015         MinVR = Reg;
01016       }
01017     } else {
01018       llvm_unreachable("Unknown RegisterClass!");
01019     }
01020   }
01021 
01022   PPCFunctionInfo *PFI = MF.getInfo<PPCFunctionInfo>();
01023   const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
01024 
01025   int64_t LowerBound = 0;
01026 
01027   // Take into account stack space reserved for tail calls.
01028   int TCSPDelta = 0;
01029   if (MF.getTarget().Options.GuaranteedTailCallOpt &&
01030       (TCSPDelta = PFI->getTailCallSPDelta()) < 0) {
01031     LowerBound = TCSPDelta;
01032   }
01033 
01034   // The Floating-point register save area is right below the back chain word
01035   // of the previous stack frame.
01036   if (HasFPSaveArea) {
01037     for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) {
01038       int FI = FPRegs[i].getFrameIdx();
01039 
01040       FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
01041     }
01042 
01043     LowerBound -= (31 - TRI->getEncodingValue(MinFPR) + 1) * 8;
01044   }
01045 
01046   // Check whether the frame pointer register is allocated. If so, make sure it
01047   // is spilled to the correct offset.
01048   if (needsFP(MF)) {
01049     HasGPSaveArea = true;
01050 
01051     int FI = PFI->getFramePointerSaveIndex();
01052     assert(FI && "No Frame Pointer Save Slot!");
01053 
01054     FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
01055   }
01056 
01057   const PPCRegisterInfo *RegInfo =
01058     static_cast<const PPCRegisterInfo*>(MF.getTarget().getRegisterInfo());
01059   if (RegInfo->hasBasePointer(MF)) {
01060     HasGPSaveArea = true;
01061 
01062     int FI = PFI->getBasePointerSaveIndex();
01063     assert(FI && "No Base Pointer Save Slot!");
01064 
01065     FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
01066   }
01067 
01068   // General register save area starts right below the Floating-point
01069   // register save area.
01070   if (HasGPSaveArea || HasG8SaveArea) {
01071     // Move general register save area spill slots down, taking into account
01072     // the size of the Floating-point register save area.
01073     for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) {
01074       int FI = GPRegs[i].getFrameIdx();
01075 
01076       FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
01077     }
01078 
01079     // Move general register save area spill slots down, taking into account
01080     // the size of the Floating-point register save area.
01081     for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) {
01082       int FI = G8Regs[i].getFrameIdx();
01083 
01084       FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
01085     }
01086 
01087     unsigned MinReg =
01088       std::min<unsigned>(TRI->getEncodingValue(MinGPR),
01089                          TRI->getEncodingValue(MinG8R));
01090 
01091     if (Subtarget.isPPC64()) {
01092       LowerBound -= (31 - MinReg + 1) * 8;
01093     } else {
01094       LowerBound -= (31 - MinReg + 1) * 4;
01095     }
01096   }
01097 
01098   // For 32-bit only, the CR save area is below the general register
01099   // save area.  For 64-bit SVR4, the CR save area is addressed relative
01100   // to the stack pointer and hence does not need an adjustment here.
01101   // Only CR2 (the first nonvolatile spilled) has an associated frame
01102   // index so that we have a single uniform save area.
01103   if (spillsCR(MF) && !(Subtarget.isPPC64() && Subtarget.isSVR4ABI())) {
01104     // Adjust the frame index of the CR spill slot.
01105     for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
01106       unsigned Reg = CSI[i].getReg();
01107 
01108       if ((Subtarget.isSVR4ABI() && Reg == PPC::CR2)
01109     // Leave Darwin logic as-is.
01110     || (!Subtarget.isSVR4ABI() &&
01111         (PPC::CRBITRCRegClass.contains(Reg) ||
01112          PPC::CRRCRegClass.contains(Reg)))) {
01113         int FI = CSI[i].getFrameIdx();
01114 
01115         FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
01116       }
01117     }
01118 
01119     LowerBound -= 4; // The CR save area is always 4 bytes long.
01120   }
01121 
01122   if (HasVRSAVESaveArea) {
01123     // FIXME SVR4: Is it actually possible to have multiple elements in CSI
01124     //             which have the VRSAVE register class?
01125     // Adjust the frame index of the VRSAVE spill slot.
01126     for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
01127       unsigned Reg = CSI[i].getReg();
01128 
01129       if (PPC::VRSAVERCRegClass.contains(Reg)) {
01130         int FI = CSI[i].getFrameIdx();
01131 
01132         FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
01133       }
01134     }
01135 
01136     LowerBound -= 4; // The VRSAVE save area is always 4 bytes long.
01137   }
01138 
01139   if (HasVRSaveArea) {
01140     // Insert alignment padding, we need 16-byte alignment.
01141     LowerBound = (LowerBound - 15) & ~(15);
01142 
01143     for (unsigned i = 0, e = VRegs.size(); i != e; ++i) {
01144       int FI = VRegs[i].getFrameIdx();
01145 
01146       FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
01147     }
01148   }
01149 
01150   addScavengingSpillSlot(MF, RS);
01151 }
01152 
01153 void
01154 PPCFrameLowering::addScavengingSpillSlot(MachineFunction &MF,
01155                                          RegScavenger *RS) const {
01156   // Reserve a slot closest to SP or frame pointer if we have a dynalloc or
01157   // a large stack, which will require scavenging a register to materialize a
01158   // large offset.
01159 
01160   // We need to have a scavenger spill slot for spills if the frame size is
01161   // large. In case there is no free register for large-offset addressing,
01162   // this slot is used for the necessary emergency spill. Also, we need the
01163   // slot for dynamic stack allocations.
01164 
01165   // The scavenger might be invoked if the frame offset does not fit into
01166   // the 16-bit immediate. We don't know the complete frame size here
01167   // because we've not yet computed callee-saved register spills or the
01168   // needed alignment padding.
01169   unsigned StackSize = determineFrameLayout(MF, false, true);
01170   MachineFrameInfo *MFI = MF.getFrameInfo();
01171   if (MFI->hasVarSizedObjects() || spillsCR(MF) || spillsVRSAVE(MF) ||
01172       hasNonRISpills(MF) || (hasSpills(MF) && !isInt<16>(StackSize))) {
01173     const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
01174     const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
01175     const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC;
01176     RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
01177                                                        RC->getAlignment(),
01178                                                        false));
01179 
01180     // Might we have over-aligned allocas?
01181     bool HasAlVars = MFI->hasVarSizedObjects() &&
01182                      MFI->getMaxAlignment() > getStackAlignment();
01183 
01184     // These kinds of spills might need two registers.
01185     if (spillsCR(MF) || spillsVRSAVE(MF) || HasAlVars)
01186       RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
01187                                                          RC->getAlignment(),
01188                                                          false));
01189 
01190   }
01191 }
01192 
01193 bool 
01194 PPCFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
01195              MachineBasicBlock::iterator MI,
01196              const std::vector<CalleeSavedInfo> &CSI,
01197              const TargetRegisterInfo *TRI) const {
01198 
01199   // Currently, this function only handles SVR4 32- and 64-bit ABIs.
01200   // Return false otherwise to maintain pre-existing behavior.
01201   if (!Subtarget.isSVR4ABI())
01202     return false;
01203 
01204   MachineFunction *MF = MBB.getParent();
01205   const PPCInstrInfo &TII =
01206     *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo());
01207   DebugLoc DL;
01208   bool CRSpilled = false;
01209   MachineInstrBuilder CRMIB;
01210   
01211   for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
01212     unsigned Reg = CSI[i].getReg();
01213     // Only Darwin actually uses the VRSAVE register, but it can still appear
01214     // here if, for example, @llvm.eh.unwind.init() is used.  If we're not on
01215     // Darwin, ignore it.
01216     if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI())
01217       continue;
01218 
01219     // CR2 through CR4 are the nonvolatile CR fields.
01220     bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4;
01221 
01222     // Add the callee-saved register as live-in; it's killed at the spill.
01223     MBB.addLiveIn(Reg);
01224 
01225     if (CRSpilled && IsCRField) {
01226       CRMIB.addReg(Reg, RegState::ImplicitKill);
01227       continue;
01228     }
01229 
01230     // Insert the spill to the stack frame.
01231     if (IsCRField) {
01232       PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>();
01233       if (Subtarget.isPPC64()) {
01234         // The actual spill will happen at the start of the prologue.
01235         FuncInfo->addMustSaveCR(Reg);
01236       } else {
01237         CRSpilled = true;
01238         FuncInfo->setSpillsCR();
01239 
01240   // 32-bit:  FP-relative.  Note that we made sure CR2-CR4 all have
01241   // the same frame index in PPCRegisterInfo::hasReservedSpillSlot.
01242   CRMIB = BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12)
01243                   .addReg(Reg, RegState::ImplicitKill);
01244 
01245   MBB.insert(MI, CRMIB);
01246   MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::STW))
01247            .addReg(PPC::R12,
01248              getKillRegState(true)),
01249            CSI[i].getFrameIdx()));
01250       }
01251     } else {
01252       const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
01253       TII.storeRegToStackSlot(MBB, MI, Reg, true,
01254             CSI[i].getFrameIdx(), RC, TRI);
01255     }
01256   }
01257   return true;
01258 }
01259 
01260 static void
01261 restoreCRs(bool isPPC64, bool is31,
01262            bool CR2Spilled, bool CR3Spilled, bool CR4Spilled,
01263      MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
01264      const std::vector<CalleeSavedInfo> &CSI, unsigned CSIIndex) {
01265 
01266   MachineFunction *MF = MBB.getParent();
01267   const PPCInstrInfo &TII =
01268     *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo());
01269   DebugLoc DL;
01270   unsigned RestoreOp, MoveReg;
01271 
01272   if (isPPC64)
01273     // This is handled during epilogue generation.
01274     return;
01275   else {
01276     // 32-bit:  FP-relative
01277     MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::LWZ),
01278                PPC::R12),
01279              CSI[CSIIndex].getFrameIdx()));
01280     RestoreOp = PPC::MTOCRF;
01281     MoveReg = PPC::R12;
01282   }
01283   
01284   if (CR2Spilled)
01285     MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR2)
01286                .addReg(MoveReg, getKillRegState(!CR3Spilled && !CR4Spilled)));
01287 
01288   if (CR3Spilled)
01289     MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR3)
01290                .addReg(MoveReg, getKillRegState(!CR4Spilled)));
01291 
01292   if (CR4Spilled)
01293     MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR4)
01294                .addReg(MoveReg, getKillRegState(true)));
01295 }
01296 
01297 void PPCFrameLowering::
01298 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
01299                               MachineBasicBlock::iterator I) const {
01300   const PPCInstrInfo &TII =
01301     *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo());
01302   if (MF.getTarget().Options.GuaranteedTailCallOpt &&
01303       I->getOpcode() == PPC::ADJCALLSTACKUP) {
01304     // Add (actually subtract) back the amount the callee popped on return.
01305     if (int CalleeAmt =  I->getOperand(1).getImm()) {
01306       bool is64Bit = Subtarget.isPPC64();
01307       CalleeAmt *= -1;
01308       unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1;
01309       unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0;
01310       unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI;
01311       unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4;
01312       unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS;
01313       unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI;
01314       MachineInstr *MI = I;
01315       DebugLoc dl = MI->getDebugLoc();
01316 
01317       if (isInt<16>(CalleeAmt)) {
01318         BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg)
01319           .addReg(StackReg, RegState::Kill)
01320           .addImm(CalleeAmt);
01321       } else {
01322         MachineBasicBlock::iterator MBBI = I;
01323         BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
01324           .addImm(CalleeAmt >> 16);
01325         BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
01326           .addReg(TmpReg, RegState::Kill)
01327           .addImm(CalleeAmt & 0xFFFF);
01328         BuildMI(MBB, MBBI, dl, TII.get(ADDInstr), StackReg)
01329           .addReg(StackReg, RegState::Kill)
01330           .addReg(TmpReg);
01331       }
01332     }
01333   }
01334   // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
01335   MBB.erase(I);
01336 }
01337 
01338 bool 
01339 PPCFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
01340           MachineBasicBlock::iterator MI,
01341                 const std::vector<CalleeSavedInfo> &CSI,
01342           const TargetRegisterInfo *TRI) const {
01343 
01344   // Currently, this function only handles SVR4 32- and 64-bit ABIs.
01345   // Return false otherwise to maintain pre-existing behavior.
01346   if (!Subtarget.isSVR4ABI())
01347     return false;
01348 
01349   MachineFunction *MF = MBB.getParent();
01350   const PPCInstrInfo &TII =
01351     *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo());
01352   bool CR2Spilled = false;
01353   bool CR3Spilled = false;
01354   bool CR4Spilled = false;
01355   unsigned CSIIndex = 0;
01356 
01357   // Initialize insertion-point logic; we will be restoring in reverse
01358   // order of spill.
01359   MachineBasicBlock::iterator I = MI, BeforeI = I;
01360   bool AtStart = I == MBB.begin();
01361 
01362   if (!AtStart)
01363     --BeforeI;
01364 
01365   for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
01366     unsigned Reg = CSI[i].getReg();
01367 
01368     // Only Darwin actually uses the VRSAVE register, but it can still appear
01369     // here if, for example, @llvm.eh.unwind.init() is used.  If we're not on
01370     // Darwin, ignore it.
01371     if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI())
01372       continue;
01373 
01374     if (Reg == PPC::CR2) {
01375       CR2Spilled = true;
01376       // The spill slot is associated only with CR2, which is the
01377       // first nonvolatile spilled.  Save it here.
01378       CSIIndex = i;
01379       continue;
01380     } else if (Reg == PPC::CR3) {
01381       CR3Spilled = true;
01382       continue;
01383     } else if (Reg == PPC::CR4) {
01384       CR4Spilled = true;
01385       continue;
01386     } else {
01387       // When we first encounter a non-CR register after seeing at
01388       // least one CR register, restore all spilled CRs together.
01389       if ((CR2Spilled || CR3Spilled || CR4Spilled)
01390     && !(PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
01391         bool is31 = needsFP(*MF);
01392         restoreCRs(Subtarget.isPPC64(), is31,
01393                    CR2Spilled, CR3Spilled, CR4Spilled,
01394        MBB, I, CSI, CSIIndex);
01395   CR2Spilled = CR3Spilled = CR4Spilled = false;
01396       }
01397 
01398       // Default behavior for non-CR saves.
01399       const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
01400       TII.loadRegFromStackSlot(MBB, I, Reg, CSI[i].getFrameIdx(),
01401              RC, TRI);
01402       assert(I != MBB.begin() &&
01403        "loadRegFromStackSlot didn't insert any code!");
01404       }
01405 
01406     // Insert in reverse order.
01407     if (AtStart)
01408       I = MBB.begin();
01409     else {
01410       I = BeforeI;
01411       ++I;
01412     }     
01413   }
01414 
01415   // If we haven't yet spilled the CRs, do so now.
01416   if (CR2Spilled || CR3Spilled || CR4Spilled) {
01417     bool is31 = needsFP(*MF); 
01418     restoreCRs(Subtarget.isPPC64(), is31, CR2Spilled, CR3Spilled, CR4Spilled,
01419          MBB, I, CSI, CSIIndex);
01420   }
01421 
01422   return true;
01423 }
01424