LLVM API Documentation

PPCJITInfo.cpp
Go to the documentation of this file.
00001 //===-- PPCJITInfo.cpp - Implement the JIT interfaces for the PowerPC -----===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file implements the JIT interfaces for the 32-bit PowerPC target.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #include "PPCJITInfo.h"
00015 #include "PPCRelocations.h"
00016 #include "PPCSubtarget.h"
00017 #include "llvm/IR/Function.h"
00018 #include "llvm/Support/Debug.h"
00019 #include "llvm/Support/ErrorHandling.h"
00020 #include "llvm/Support/Memory.h"
00021 #include "llvm/Support/raw_ostream.h"
00022 using namespace llvm;
00023 
00024 #define DEBUG_TYPE "jit"
00025 
00026 static TargetJITInfo::JITCompilerFn JITCompilerFunction;
00027 
00028 PPCJITInfo::PPCJITInfo(PPCSubtarget &STI)
00029     : Subtarget(STI), is64Bit(STI.isPPC64()) {
00030   useGOT = 0;
00031 }
00032 
00033 #define BUILD_ADDIS(RD,RS,IMM16) \
00034   ((15 << 26) | ((RD) << 21) | ((RS) << 16) | ((IMM16) & 65535))
00035 #define BUILD_ORI(RD,RS,UIMM16) \
00036   ((24 << 26) | ((RS) << 21) | ((RD) << 16) | ((UIMM16) & 65535))
00037 #define BUILD_ORIS(RD,RS,UIMM16) \
00038   ((25 << 26) | ((RS) << 21) | ((RD) << 16) | ((UIMM16) & 65535))
00039 #define BUILD_RLDICR(RD,RS,SH,ME) \
00040   ((30 << 26) | ((RS) << 21) | ((RD) << 16) | (((SH) & 31) << 11) | \
00041    (((ME) & 63) << 6) | (1 << 2) | ((((SH) >> 5) & 1) << 1))
00042 #define BUILD_MTSPR(RS,SPR)      \
00043   ((31 << 26) | ((RS) << 21) | ((SPR) << 16) | (467 << 1))
00044 #define BUILD_BCCTRx(BO,BI,LINK) \
00045   ((19 << 26) | ((BO) << 21) | ((BI) << 16) | (528 << 1) | ((LINK) & 1))
00046 #define BUILD_B(TARGET, LINK) \
00047   ((18 << 26) | (((TARGET) & 0x00FFFFFF) << 2) | ((LINK) & 1))
00048 
00049 // Pseudo-ops
00050 #define BUILD_LIS(RD,IMM16)    BUILD_ADDIS(RD,0,IMM16)
00051 #define BUILD_SLDI(RD,RS,IMM6) BUILD_RLDICR(RD,RS,IMM6,63-IMM6)
00052 #define BUILD_MTCTR(RS)        BUILD_MTSPR(RS,9)
00053 #define BUILD_BCTR(LINK)       BUILD_BCCTRx(20,0,LINK)
00054 
00055 static void EmitBranchToAt(uint64_t At, uint64_t To, bool isCall, bool is64Bit){
00056   intptr_t Offset = ((intptr_t)To - (intptr_t)At) >> 2;
00057   unsigned *AtI = (unsigned*)(intptr_t)At;
00058 
00059   if (Offset >= -(1 << 23) && Offset < (1 << 23)) {   // In range?
00060     AtI[0] = BUILD_B(Offset, isCall);     // b/bl target
00061   } else if (!is64Bit) {
00062     AtI[0] = BUILD_LIS(12, To >> 16);     // lis r12, hi16(address)
00063     AtI[1] = BUILD_ORI(12, 12, To);       // ori r12, r12, lo16(address)
00064     AtI[2] = BUILD_MTCTR(12);             // mtctr r12
00065     AtI[3] = BUILD_BCTR(isCall);          // bctr/bctrl
00066   } else {
00067     AtI[0] = BUILD_LIS(12, To >> 48);      // lis r12, hi16(address)
00068     AtI[1] = BUILD_ORI(12, 12, To >> 32);  // ori r12, r12, lo16(address)
00069     AtI[2] = BUILD_SLDI(12, 12, 32);       // sldi r12, r12, 32
00070     AtI[3] = BUILD_ORIS(12, 12, To >> 16); // oris r12, r12, hi16(address)
00071     AtI[4] = BUILD_ORI(12, 12, To);        // ori r12, r12, lo16(address)
00072     AtI[5] = BUILD_MTCTR(12);              // mtctr r12
00073     AtI[6] = BUILD_BCTR(isCall);           // bctr/bctrl
00074   }
00075 }
00076 
00077 extern "C" void PPC32CompilationCallback();
00078 extern "C" void PPC64CompilationCallback();
00079 
00080 // The first clause of the preprocessor directive looks wrong, but it is
00081 // necessary when compiling this code on non-PowerPC hosts.
00082 #if (!defined(__ppc__) && !defined(__powerpc__)) || defined(__powerpc64__) || defined(__ppc64__)
00083 void PPC32CompilationCallback() {
00084   llvm_unreachable("This is not a 32bit PowerPC, you can't execute this!");
00085 }
00086 #elif !defined(__ELF__)
00087 // CompilationCallback stub - We can't use a C function with inline assembly in
00088 // it, because we the prolog/epilog inserted by GCC won't work for us.  Instead,
00089 // write our own wrapper, which does things our way, so we have complete control
00090 // over register saving and restoring.
00091 asm(
00092     ".text\n"
00093     ".align 2\n"
00094     ".globl _PPC32CompilationCallback\n"
00095 "_PPC32CompilationCallback:\n"
00096     // Make space for 8 ints r[3-10] and 13 doubles f[1-13] and the 
00097     // FIXME: need to save v[0-19] for altivec?
00098     // FIXME: could shrink frame
00099     // Set up a proper stack frame
00100     // FIXME Layout
00101     //   PowerPC32 ABI linkage    -  24 bytes
00102     //                 parameters -  32 bytes
00103     //   13 double registers      - 104 bytes
00104     //   8 int registers          -  32 bytes
00105     "mflr r0\n"
00106     "stw r0,  8(r1)\n"
00107     "stwu r1, -208(r1)\n"
00108     // Save all int arg registers
00109     "stw r10, 204(r1)\n"    "stw r9,  200(r1)\n"
00110     "stw r8,  196(r1)\n"    "stw r7,  192(r1)\n"
00111     "stw r6,  188(r1)\n"    "stw r5,  184(r1)\n"
00112     "stw r4,  180(r1)\n"    "stw r3,  176(r1)\n"
00113     // Save all call-clobbered FP regs.
00114     "stfd f13, 168(r1)\n"   "stfd f12, 160(r1)\n"
00115     "stfd f11, 152(r1)\n"   "stfd f10, 144(r1)\n"
00116     "stfd f9,  136(r1)\n"   "stfd f8,  128(r1)\n"
00117     "stfd f7,  120(r1)\n"   "stfd f6,  112(r1)\n"
00118     "stfd f5,  104(r1)\n"   "stfd f4,   96(r1)\n"
00119     "stfd f3,   88(r1)\n"   "stfd f2,   80(r1)\n"
00120     "stfd f1,   72(r1)\n"
00121     // Arguments to Compilation Callback:
00122     // r3 - our lr (address of the call instruction in stub plus 4)
00123     // r4 - stub's lr (address of instruction that called the stub plus 4)
00124     // r5 - is64Bit - always 0.
00125     "mr   r3, r0\n"
00126     "lwz  r2, 208(r1)\n" // stub's frame
00127     "lwz  r4, 8(r2)\n" // stub's lr
00128     "li   r5, 0\n"       // 0 == 32 bit
00129     "bl _LLVMPPCCompilationCallback\n"
00130     "mtctr r3\n"
00131     // Restore all int arg registers
00132     "lwz r10, 204(r1)\n"    "lwz r9,  200(r1)\n"
00133     "lwz r8,  196(r1)\n"    "lwz r7,  192(r1)\n"
00134     "lwz r6,  188(r1)\n"    "lwz r5,  184(r1)\n"
00135     "lwz r4,  180(r1)\n"    "lwz r3,  176(r1)\n"
00136     // Restore all FP arg registers
00137     "lfd f13, 168(r1)\n"    "lfd f12, 160(r1)\n"
00138     "lfd f11, 152(r1)\n"    "lfd f10, 144(r1)\n"
00139     "lfd f9,  136(r1)\n"    "lfd f8,  128(r1)\n"
00140     "lfd f7,  120(r1)\n"    "lfd f6,  112(r1)\n"
00141     "lfd f5,  104(r1)\n"    "lfd f4,   96(r1)\n"
00142     "lfd f3,   88(r1)\n"    "lfd f2,   80(r1)\n"
00143     "lfd f1,   72(r1)\n"
00144     // Pop 3 frames off the stack and branch to target
00145     "lwz  r1, 208(r1)\n"
00146     "lwz  r2, 8(r1)\n"
00147     "mtlr r2\n"
00148     "bctr\n"
00149     );
00150 
00151 #else
00152 // ELF PPC 32 support
00153 
00154 // CompilationCallback stub - We can't use a C function with inline assembly in
00155 // it, because we the prolog/epilog inserted by GCC won't work for us.  Instead,
00156 // write our own wrapper, which does things our way, so we have complete control
00157 // over register saving and restoring.
00158 asm(
00159     ".text\n"
00160     ".align 2\n"
00161     ".globl PPC32CompilationCallback\n"
00162 "PPC32CompilationCallback:\n"
00163     // Make space for 8 ints r[3-10] and 8 doubles f[1-8] and the 
00164     // FIXME: need to save v[0-19] for altivec?
00165     // FIXME: could shrink frame
00166     // Set up a proper stack frame
00167     // FIXME Layout
00168     //   8 double registers       -  64 bytes
00169     //   8 int registers          -  32 bytes
00170     "mflr 0\n"
00171     "stw 0,  4(1)\n"
00172     "stwu 1, -104(1)\n"
00173     // Save all int arg registers
00174     "stw 10, 100(1)\n"   "stw 9,  96(1)\n"
00175     "stw 8,  92(1)\n"    "stw 7,  88(1)\n"
00176     "stw 6,  84(1)\n"    "stw 5,  80(1)\n"
00177     "stw 4,  76(1)\n"    "stw 3,  72(1)\n"
00178     // Save all call-clobbered FP regs.
00179     "stfd 8,  64(1)\n"
00180     "stfd 7,  56(1)\n"   "stfd 6,  48(1)\n"
00181     "stfd 5,  40(1)\n"   "stfd 4,  32(1)\n"
00182     "stfd 3,  24(1)\n"   "stfd 2,  16(1)\n"
00183     "stfd 1,  8(1)\n"
00184     // Arguments to Compilation Callback:
00185     // r3 - our lr (address of the call instruction in stub plus 4)
00186     // r4 - stub's lr (address of instruction that called the stub plus 4)
00187     // r5 - is64Bit - always 0.
00188     "mr   3, 0\n"
00189     "lwz  5, 104(1)\n" // stub's frame
00190     "lwz  4, 4(5)\n" // stub's lr
00191     "li   5, 0\n"       // 0 == 32 bit
00192     "bl LLVMPPCCompilationCallback\n"
00193     "mtctr 3\n"
00194     // Restore all int arg registers
00195     "lwz 10, 100(1)\n"   "lwz 9,  96(1)\n"
00196     "lwz 8,  92(1)\n"    "lwz 7,  88(1)\n"
00197     "lwz 6,  84(1)\n"    "lwz 5,  80(1)\n"
00198     "lwz 4,  76(1)\n"    "lwz 3,  72(1)\n"
00199     // Restore all FP arg registers
00200     "lfd 8,  64(1)\n"
00201     "lfd 7,  56(1)\n"    "lfd 6,  48(1)\n"
00202     "lfd 5,  40(1)\n"    "lfd 4,  32(1)\n"
00203     "lfd 3,  24(1)\n"    "lfd 2,  16(1)\n"
00204     "lfd 1,  8(1)\n"
00205     // Pop 3 frames off the stack and branch to target
00206     "lwz  1, 104(1)\n"
00207     "lwz  0, 4(1)\n"
00208     "mtlr 0\n"
00209     "bctr\n"
00210     );
00211 #endif
00212 
00213 #if !defined(__powerpc64__) && !defined(__ppc64__)
00214 void PPC64CompilationCallback() {
00215   llvm_unreachable("This is not a 64bit PowerPC, you can't execute this!");
00216 }
00217 #else
00218 #  ifdef __ELF__
00219 asm(
00220     ".text\n"
00221     ".align 2\n"
00222     ".globl PPC64CompilationCallback\n"
00223 #if _CALL_ELF == 2
00224     ".type PPC64CompilationCallback,@function\n"
00225 "PPC64CompilationCallback:\n"
00226 #else
00227     ".section \".opd\",\"aw\",@progbits\n"
00228     ".align 3\n"
00229 "PPC64CompilationCallback:\n"
00230     ".quad .L.PPC64CompilationCallback,.TOC.@tocbase,0\n"
00231     ".size PPC64CompilationCallback,24\n"
00232     ".previous\n"
00233     ".align 4\n"
00234     ".type PPC64CompilationCallback,@function\n"
00235 ".L.PPC64CompilationCallback:\n"
00236 #endif
00237 #  else
00238 asm(
00239     ".text\n"
00240     ".align 2\n"
00241     ".globl _PPC64CompilationCallback\n"
00242 "_PPC64CompilationCallback:\n"
00243 #  endif
00244     // Make space for 8 ints r[3-10] and 13 doubles f[1-13] and the 
00245     // FIXME: need to save v[0-19] for altivec?
00246     // Set up a proper stack frame
00247     // Layout
00248     //   PowerPC64 ABI linkage    -  48 bytes
00249     //                 parameters -  64 bytes
00250     //   13 double registers      - 104 bytes
00251     //   8 int registers          -  64 bytes
00252     "mflr 0\n"
00253     "std  0,  16(1)\n"
00254     "stdu 1, -280(1)\n"
00255     // Save all int arg registers
00256     "std 10, 272(1)\n"    "std 9,  264(1)\n"
00257     "std 8,  256(1)\n"    "std 7,  248(1)\n"
00258     "std 6,  240(1)\n"    "std 5,  232(1)\n"
00259     "std 4,  224(1)\n"    "std 3,  216(1)\n"
00260     // Save all call-clobbered FP regs.
00261     "stfd 13, 208(1)\n"    "stfd 12, 200(1)\n"
00262     "stfd 11, 192(1)\n"    "stfd 10, 184(1)\n"
00263     "stfd 9,  176(1)\n"    "stfd 8,  168(1)\n"
00264     "stfd 7,  160(1)\n"    "stfd 6,  152(1)\n"
00265     "stfd 5,  144(1)\n"    "stfd 4,  136(1)\n"
00266     "stfd 3,  128(1)\n"    "stfd 2,  120(1)\n"
00267     "stfd 1,  112(1)\n"
00268     // Arguments to Compilation Callback:
00269     // r3 - our lr (address of the call instruction in stub plus 4)
00270     // r4 - stub's lr (address of instruction that called the stub plus 4)
00271     // r5 - is64Bit - always 1.
00272     "mr   3, 0\n"      // return address (still in r0)
00273     "ld   5, 280(1)\n" // stub's frame
00274     "ld   4, 16(5)\n"  // stub's lr
00275     "li   5, 1\n"      // 1 == 64 bit
00276 #  ifdef __ELF__
00277     "bl LLVMPPCCompilationCallback\n"
00278     "nop\n"
00279 #  else
00280     "bl _LLVMPPCCompilationCallback\n"
00281 #  endif
00282     "mtctr 3\n"
00283     // Restore all int arg registers
00284     "ld 10, 272(1)\n"    "ld 9,  264(1)\n"
00285     "ld 8,  256(1)\n"    "ld 7,  248(1)\n"
00286     "ld 6,  240(1)\n"    "ld 5,  232(1)\n"
00287     "ld 4,  224(1)\n"    "ld 3,  216(1)\n"
00288     // Restore all FP arg registers
00289     "lfd 13, 208(1)\n"    "lfd 12, 200(1)\n"
00290     "lfd 11, 192(1)\n"    "lfd 10, 184(1)\n"
00291     "lfd 9,  176(1)\n"    "lfd 8,  168(1)\n"
00292     "lfd 7,  160(1)\n"    "lfd 6,  152(1)\n"
00293     "lfd 5,  144(1)\n"    "lfd 4,  136(1)\n"
00294     "lfd 3,  128(1)\n"    "lfd 2,  120(1)\n"
00295     "lfd 1,  112(1)\n"
00296     // Pop 3 frames off the stack and branch to target
00297     "ld  1, 280(1)\n"
00298     "ld  0, 16(1)\n"
00299     "mtlr 0\n"
00300     // XXX: any special TOC handling in the ELF case for JIT?
00301     "bctr\n"
00302     );
00303 #endif
00304 
00305 extern "C" {
00306 LLVM_LIBRARY_VISIBILITY void *
00307 LLVMPPCCompilationCallback(unsigned *StubCallAddrPlus4,
00308                            unsigned *OrigCallAddrPlus4,
00309                            bool is64Bit) {
00310   // Adjust the pointer to the address of the call instruction in the stub
00311   // emitted by emitFunctionStub, rather than the instruction after it.
00312   unsigned *StubCallAddr = StubCallAddrPlus4 - 1;
00313   unsigned *OrigCallAddr = OrigCallAddrPlus4 - 1;
00314 
00315   void *Target = JITCompilerFunction(StubCallAddr);
00316 
00317   // Check to see if *OrigCallAddr is a 'bl' instruction, and if we can rewrite
00318   // it to branch directly to the destination.  If so, rewrite it so it does not
00319   // need to go through the stub anymore.
00320   unsigned OrigCallInst = *OrigCallAddr;
00321   if ((OrigCallInst >> 26) == 18) {     // Direct call.
00322     intptr_t Offset = ((intptr_t)Target - (intptr_t)OrigCallAddr) >> 2;
00323     
00324     if (Offset >= -(1 << 23) && Offset < (1 << 23)) {   // In range?
00325       // Clear the original target out.
00326       OrigCallInst &= (63 << 26) | 3;
00327       // Fill in the new target.
00328       OrigCallInst |= (Offset & ((1 << 24)-1)) << 2;
00329       // Replace the call.
00330       *OrigCallAddr = OrigCallInst;
00331     }
00332   }
00333 
00334   // Assert that we are coming from a stub that was created with our
00335   // emitFunctionStub.
00336   if ((*StubCallAddr >> 26) == 18)
00337     StubCallAddr -= 3;
00338   else {
00339   assert((*StubCallAddr >> 26) == 19 && "Call in stub is not indirect!");
00340     StubCallAddr -= is64Bit ? 9 : 6;
00341   }
00342 
00343   // Rewrite the stub with an unconditional branch to the target, for any users
00344   // who took the address of the stub.
00345   EmitBranchToAt((intptr_t)StubCallAddr, (intptr_t)Target, false, is64Bit);
00346   sys::Memory::InvalidateInstructionCache(StubCallAddr, 7*4);
00347 
00348   // Put the address of the target function to call and the address to return to
00349   // after calling the target function in a place that is easy to get on the
00350   // stack after we restore all regs.
00351   return Target;
00352 }
00353 }
00354 
00355 
00356 
00357 TargetJITInfo::LazyResolverFn
00358 PPCJITInfo::getLazyResolverFunction(JITCompilerFn Fn) {
00359   JITCompilerFunction = Fn;
00360   return is64Bit ? PPC64CompilationCallback : PPC32CompilationCallback;
00361 }
00362 
00363 TargetJITInfo::StubLayout PPCJITInfo::getStubLayout() {
00364   // The stub contains up to 10 4-byte instructions, aligned at 4 bytes: 3
00365   // instructions to save the caller's address if this is a lazy-compilation
00366   // stub, plus a 1-, 4-, or 7-instruction sequence to load an arbitrary address
00367   // into a register and jump through it.
00368   StubLayout Result = {10*4, 4};
00369   return Result;
00370 }
00371 
00372 #if (defined(__POWERPC__) || defined (__ppc__) || defined(_POWER)) && \
00373 defined(__APPLE__)
00374 extern "C" void sys_icache_invalidate(const void *Addr, size_t len);
00375 #endif
00376 
00377 void *PPCJITInfo::emitFunctionStub(const Function* F, void *Fn,
00378                                    JITCodeEmitter &JCE) {
00379   // If this is just a call to an external function, emit a branch instead of a
00380   // call.  The code is the same except for one bit of the last instruction.
00381   if (Fn != (void*)(intptr_t)PPC32CompilationCallback && 
00382       Fn != (void*)(intptr_t)PPC64CompilationCallback) {
00383     void *Addr = (void*)JCE.getCurrentPCValue();
00384     JCE.emitWordBE(0);
00385     JCE.emitWordBE(0);
00386     JCE.emitWordBE(0);
00387     JCE.emitWordBE(0);
00388     JCE.emitWordBE(0);
00389     JCE.emitWordBE(0);
00390     JCE.emitWordBE(0);
00391     EmitBranchToAt((intptr_t)Addr, (intptr_t)Fn, false, is64Bit);
00392     sys::Memory::InvalidateInstructionCache(Addr, 7*4);
00393     return Addr;
00394   }
00395 
00396   void *Addr = (void*)JCE.getCurrentPCValue();
00397   if (is64Bit) {
00398     JCE.emitWordBE(0xf821ffb1);     // stdu r1,-80(r1)
00399     JCE.emitWordBE(0x7d6802a6);     // mflr r11
00400     JCE.emitWordBE(0xf9610060);     // std r11, 96(r1)
00401   } else if (Subtarget.isDarwinABI()){
00402     JCE.emitWordBE(0x9421ffe0);     // stwu r1,-32(r1)
00403     JCE.emitWordBE(0x7d6802a6);     // mflr r11
00404     JCE.emitWordBE(0x91610028);     // stw r11, 40(r1)
00405   } else {
00406     JCE.emitWordBE(0x9421ffe0);     // stwu r1,-32(r1)
00407     JCE.emitWordBE(0x7d6802a6);     // mflr r11
00408     JCE.emitWordBE(0x91610024);     // stw r11, 36(r1)
00409   }
00410   intptr_t BranchAddr = (intptr_t)JCE.getCurrentPCValue();
00411   JCE.emitWordBE(0);
00412   JCE.emitWordBE(0);
00413   JCE.emitWordBE(0);
00414   JCE.emitWordBE(0);
00415   JCE.emitWordBE(0);
00416   JCE.emitWordBE(0);
00417   JCE.emitWordBE(0);
00418   EmitBranchToAt(BranchAddr, (intptr_t)Fn, true, is64Bit);
00419   sys::Memory::InvalidateInstructionCache(Addr, 10*4);
00420   return Addr;
00421 }
00422 
00423 
00424 void PPCJITInfo::relocate(void *Function, MachineRelocation *MR,
00425                           unsigned NumRelocs, unsigned char* GOTBase) {
00426   for (unsigned i = 0; i != NumRelocs; ++i, ++MR) {
00427     unsigned *RelocPos = (unsigned*)Function + MR->getMachineCodeOffset()/4;
00428     intptr_t ResultPtr = (intptr_t)MR->getResultPointer();
00429     switch ((PPC::RelocationType)MR->getRelocationType()) {
00430     default: llvm_unreachable("Unknown relocation type!");
00431     case PPC::reloc_pcrel_bx:
00432       // PC-relative relocation for b and bl instructions.
00433       ResultPtr = (ResultPtr-(intptr_t)RelocPos) >> 2;
00434       assert(ResultPtr >= -(1 << 23) && ResultPtr < (1 << 23) &&
00435              "Relocation out of range!");
00436       *RelocPos |= (ResultPtr & ((1 << 24)-1))  << 2;
00437       break;
00438     case PPC::reloc_pcrel_bcx:
00439       // PC-relative relocation for BLT,BLE,BEQ,BGE,BGT,BNE, or other
00440       // bcx instructions.
00441       ResultPtr = (ResultPtr-(intptr_t)RelocPos) >> 2;
00442       assert(ResultPtr >= -(1 << 13) && ResultPtr < (1 << 13) &&
00443              "Relocation out of range!");
00444       *RelocPos |= (ResultPtr & ((1 << 14)-1))  << 2;
00445       break;
00446     case PPC::reloc_absolute_high:     // high bits of ref -> low 16 of instr
00447     case PPC::reloc_absolute_low: {    // low bits of ref  -> low 16 of instr
00448       ResultPtr += MR->getConstantVal();
00449 
00450       // If this is a high-part access, get the high-part.
00451       if (MR->getRelocationType() == PPC::reloc_absolute_high) {
00452         // If the low part will have a carry (really a borrow) from the low
00453         // 16-bits into the high 16, add a bit to borrow from.
00454         if (((int)ResultPtr << 16) < 0)
00455           ResultPtr += 1 << 16;
00456         ResultPtr >>= 16;
00457       }
00458 
00459       // Do the addition then mask, so the addition does not overflow the 16-bit
00460       // immediate section of the instruction.
00461       unsigned LowBits  = (*RelocPos + ResultPtr) & 65535;
00462       unsigned HighBits = *RelocPos & ~65535;
00463       *RelocPos = LowBits | HighBits;  // Slam into low 16-bits
00464       break;
00465     }
00466     case PPC::reloc_absolute_low_ix: {  // low bits of ref  -> low 14 of instr
00467       ResultPtr += MR->getConstantVal();
00468       // Do the addition then mask, so the addition does not overflow the 16-bit
00469       // immediate section of the instruction.
00470       unsigned LowBits  = (*RelocPos + ResultPtr) & 0xFFFC;
00471       unsigned HighBits = *RelocPos & 0xFFFF0003;
00472       *RelocPos = LowBits | HighBits;  // Slam into low 14-bits.
00473       break;
00474     }
00475     }
00476   }
00477 }
00478 
00479 void PPCJITInfo::replaceMachineCodeForFunction(void *Old, void *New) {
00480   EmitBranchToAt((intptr_t)Old, (intptr_t)New, false, is64Bit);
00481   sys::Memory::InvalidateInstructionCache(Old, 7*4);
00482 }