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PPCJITInfo.cpp
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00001 //===-- PPCJITInfo.cpp - Implement the JIT interfaces for the PowerPC -----===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file implements the JIT interfaces for the 32-bit PowerPC target.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #define DEBUG_TYPE "jit"
00015 #include "PPCJITInfo.h"
00016 #include "PPCRelocations.h"
00017 #include "PPCTargetMachine.h"
00018 #include "llvm/IR/Function.h"
00019 #include "llvm/Support/Debug.h"
00020 #include "llvm/Support/ErrorHandling.h"
00021 #include "llvm/Support/Memory.h"
00022 #include "llvm/Support/raw_ostream.h"
00023 using namespace llvm;
00024 
00025 static TargetJITInfo::JITCompilerFn JITCompilerFunction;
00026 
00027 #define BUILD_ADDIS(RD,RS,IMM16) \
00028   ((15 << 26) | ((RD) << 21) | ((RS) << 16) | ((IMM16) & 65535))
00029 #define BUILD_ORI(RD,RS,UIMM16) \
00030   ((24 << 26) | ((RS) << 21) | ((RD) << 16) | ((UIMM16) & 65535))
00031 #define BUILD_ORIS(RD,RS,UIMM16) \
00032   ((25 << 26) | ((RS) << 21) | ((RD) << 16) | ((UIMM16) & 65535))
00033 #define BUILD_RLDICR(RD,RS,SH,ME) \
00034   ((30 << 26) | ((RS) << 21) | ((RD) << 16) | (((SH) & 31) << 11) | \
00035    (((ME) & 63) << 6) | (1 << 2) | ((((SH) >> 5) & 1) << 1))
00036 #define BUILD_MTSPR(RS,SPR)      \
00037   ((31 << 26) | ((RS) << 21) | ((SPR) << 16) | (467 << 1))
00038 #define BUILD_BCCTRx(BO,BI,LINK) \
00039   ((19 << 26) | ((BO) << 21) | ((BI) << 16) | (528 << 1) | ((LINK) & 1))
00040 #define BUILD_B(TARGET, LINK) \
00041   ((18 << 26) | (((TARGET) & 0x00FFFFFF) << 2) | ((LINK) & 1))
00042 
00043 // Pseudo-ops
00044 #define BUILD_LIS(RD,IMM16)    BUILD_ADDIS(RD,0,IMM16)
00045 #define BUILD_SLDI(RD,RS,IMM6) BUILD_RLDICR(RD,RS,IMM6,63-IMM6)
00046 #define BUILD_MTCTR(RS)        BUILD_MTSPR(RS,9)
00047 #define BUILD_BCTR(LINK)       BUILD_BCCTRx(20,0,LINK)
00048 
00049 static void EmitBranchToAt(uint64_t At, uint64_t To, bool isCall, bool is64Bit){
00050   intptr_t Offset = ((intptr_t)To - (intptr_t)At) >> 2;
00051   unsigned *AtI = (unsigned*)(intptr_t)At;
00052 
00053   if (Offset >= -(1 << 23) && Offset < (1 << 23)) {   // In range?
00054     AtI[0] = BUILD_B(Offset, isCall);     // b/bl target
00055   } else if (!is64Bit) {
00056     AtI[0] = BUILD_LIS(12, To >> 16);     // lis r12, hi16(address)
00057     AtI[1] = BUILD_ORI(12, 12, To);       // ori r12, r12, lo16(address)
00058     AtI[2] = BUILD_MTCTR(12);             // mtctr r12
00059     AtI[3] = BUILD_BCTR(isCall);          // bctr/bctrl
00060   } else {
00061     AtI[0] = BUILD_LIS(12, To >> 48);      // lis r12, hi16(address)
00062     AtI[1] = BUILD_ORI(12, 12, To >> 32);  // ori r12, r12, lo16(address)
00063     AtI[2] = BUILD_SLDI(12, 12, 32);       // sldi r12, r12, 32
00064     AtI[3] = BUILD_ORIS(12, 12, To >> 16); // oris r12, r12, hi16(address)
00065     AtI[4] = BUILD_ORI(12, 12, To);        // ori r12, r12, lo16(address)
00066     AtI[5] = BUILD_MTCTR(12);              // mtctr r12
00067     AtI[6] = BUILD_BCTR(isCall);           // bctr/bctrl
00068   }
00069 }
00070 
00071 extern "C" void PPC32CompilationCallback();
00072 extern "C" void PPC64CompilationCallback();
00073 
00074 // The first clause of the preprocessor directive looks wrong, but it is
00075 // necessary when compiling this code on non-PowerPC hosts.
00076 #if (!defined(__ppc__) && !defined(__powerpc__)) || defined(__powerpc64__) || defined(__ppc64__)
00077 void PPC32CompilationCallback() {
00078   llvm_unreachable("This is not a 32bit PowerPC, you can't execute this!");
00079 }
00080 #elif !defined(__ELF__)
00081 // CompilationCallback stub - We can't use a C function with inline assembly in
00082 // it, because we the prolog/epilog inserted by GCC won't work for us.  Instead,
00083 // write our own wrapper, which does things our way, so we have complete control
00084 // over register saving and restoring.
00085 asm(
00086     ".text\n"
00087     ".align 2\n"
00088     ".globl _PPC32CompilationCallback\n"
00089 "_PPC32CompilationCallback:\n"
00090     // Make space for 8 ints r[3-10] and 13 doubles f[1-13] and the 
00091     // FIXME: need to save v[0-19] for altivec?
00092     // FIXME: could shrink frame
00093     // Set up a proper stack frame
00094     // FIXME Layout
00095     //   PowerPC32 ABI linkage    -  24 bytes
00096     //                 parameters -  32 bytes
00097     //   13 double registers      - 104 bytes
00098     //   8 int registers          -  32 bytes
00099     "mflr r0\n"
00100     "stw r0,  8(r1)\n"
00101     "stwu r1, -208(r1)\n"
00102     // Save all int arg registers
00103     "stw r10, 204(r1)\n"    "stw r9,  200(r1)\n"
00104     "stw r8,  196(r1)\n"    "stw r7,  192(r1)\n"
00105     "stw r6,  188(r1)\n"    "stw r5,  184(r1)\n"
00106     "stw r4,  180(r1)\n"    "stw r3,  176(r1)\n"
00107     // Save all call-clobbered FP regs.
00108     "stfd f13, 168(r1)\n"   "stfd f12, 160(r1)\n"
00109     "stfd f11, 152(r1)\n"   "stfd f10, 144(r1)\n"
00110     "stfd f9,  136(r1)\n"   "stfd f8,  128(r1)\n"
00111     "stfd f7,  120(r1)\n"   "stfd f6,  112(r1)\n"
00112     "stfd f5,  104(r1)\n"   "stfd f4,   96(r1)\n"
00113     "stfd f3,   88(r1)\n"   "stfd f2,   80(r1)\n"
00114     "stfd f1,   72(r1)\n"
00115     // Arguments to Compilation Callback:
00116     // r3 - our lr (address of the call instruction in stub plus 4)
00117     // r4 - stub's lr (address of instruction that called the stub plus 4)
00118     // r5 - is64Bit - always 0.
00119     "mr   r3, r0\n"
00120     "lwz  r2, 208(r1)\n" // stub's frame
00121     "lwz  r4, 8(r2)\n" // stub's lr
00122     "li   r5, 0\n"       // 0 == 32 bit
00123     "bl _LLVMPPCCompilationCallback\n"
00124     "mtctr r3\n"
00125     // Restore all int arg registers
00126     "lwz r10, 204(r1)\n"    "lwz r9,  200(r1)\n"
00127     "lwz r8,  196(r1)\n"    "lwz r7,  192(r1)\n"
00128     "lwz r6,  188(r1)\n"    "lwz r5,  184(r1)\n"
00129     "lwz r4,  180(r1)\n"    "lwz r3,  176(r1)\n"
00130     // Restore all FP arg registers
00131     "lfd f13, 168(r1)\n"    "lfd f12, 160(r1)\n"
00132     "lfd f11, 152(r1)\n"    "lfd f10, 144(r1)\n"
00133     "lfd f9,  136(r1)\n"    "lfd f8,  128(r1)\n"
00134     "lfd f7,  120(r1)\n"    "lfd f6,  112(r1)\n"
00135     "lfd f5,  104(r1)\n"    "lfd f4,   96(r1)\n"
00136     "lfd f3,   88(r1)\n"    "lfd f2,   80(r1)\n"
00137     "lfd f1,   72(r1)\n"
00138     // Pop 3 frames off the stack and branch to target
00139     "lwz  r1, 208(r1)\n"
00140     "lwz  r2, 8(r1)\n"
00141     "mtlr r2\n"
00142     "bctr\n"
00143     );
00144 
00145 #else
00146 // ELF PPC 32 support
00147 
00148 // CompilationCallback stub - We can't use a C function with inline assembly in
00149 // it, because we the prolog/epilog inserted by GCC won't work for us.  Instead,
00150 // write our own wrapper, which does things our way, so we have complete control
00151 // over register saving and restoring.
00152 asm(
00153     ".text\n"
00154     ".align 2\n"
00155     ".globl PPC32CompilationCallback\n"
00156 "PPC32CompilationCallback:\n"
00157     // Make space for 8 ints r[3-10] and 8 doubles f[1-8] and the 
00158     // FIXME: need to save v[0-19] for altivec?
00159     // FIXME: could shrink frame
00160     // Set up a proper stack frame
00161     // FIXME Layout
00162     //   8 double registers       -  64 bytes
00163     //   8 int registers          -  32 bytes
00164     "mflr 0\n"
00165     "stw 0,  4(1)\n"
00166     "stwu 1, -104(1)\n"
00167     // Save all int arg registers
00168     "stw 10, 100(1)\n"   "stw 9,  96(1)\n"
00169     "stw 8,  92(1)\n"    "stw 7,  88(1)\n"
00170     "stw 6,  84(1)\n"    "stw 5,  80(1)\n"
00171     "stw 4,  76(1)\n"    "stw 3,  72(1)\n"
00172     // Save all call-clobbered FP regs.
00173     "stfd 8,  64(1)\n"
00174     "stfd 7,  56(1)\n"   "stfd 6,  48(1)\n"
00175     "stfd 5,  40(1)\n"   "stfd 4,  32(1)\n"
00176     "stfd 3,  24(1)\n"   "stfd 2,  16(1)\n"
00177     "stfd 1,  8(1)\n"
00178     // Arguments to Compilation Callback:
00179     // r3 - our lr (address of the call instruction in stub plus 4)
00180     // r4 - stub's lr (address of instruction that called the stub plus 4)
00181     // r5 - is64Bit - always 0.
00182     "mr   3, 0\n"
00183     "lwz  5, 104(1)\n" // stub's frame
00184     "lwz  4, 4(5)\n" // stub's lr
00185     "li   5, 0\n"       // 0 == 32 bit
00186     "bl LLVMPPCCompilationCallback\n"
00187     "mtctr 3\n"
00188     // Restore all int arg registers
00189     "lwz 10, 100(1)\n"   "lwz 9,  96(1)\n"
00190     "lwz 8,  92(1)\n"    "lwz 7,  88(1)\n"
00191     "lwz 6,  84(1)\n"    "lwz 5,  80(1)\n"
00192     "lwz 4,  76(1)\n"    "lwz 3,  72(1)\n"
00193     // Restore all FP arg registers
00194     "lfd 8,  64(1)\n"
00195     "lfd 7,  56(1)\n"    "lfd 6,  48(1)\n"
00196     "lfd 5,  40(1)\n"    "lfd 4,  32(1)\n"
00197     "lfd 3,  24(1)\n"    "lfd 2,  16(1)\n"
00198     "lfd 1,  8(1)\n"
00199     // Pop 3 frames off the stack and branch to target
00200     "lwz  1, 104(1)\n"
00201     "lwz  0, 4(1)\n"
00202     "mtlr 0\n"
00203     "bctr\n"
00204     );
00205 #endif
00206 
00207 #if !defined(__powerpc64__) && !defined(__ppc64__)
00208 void PPC64CompilationCallback() {
00209   llvm_unreachable("This is not a 64bit PowerPC, you can't execute this!");
00210 }
00211 #else
00212 #  ifdef __ELF__
00213 asm(
00214     ".text\n"
00215     ".align 2\n"
00216     ".globl PPC64CompilationCallback\n"
00217 #if _CALL_ELF == 2
00218     ".type PPC64CompilationCallback,@function\n"
00219 "PPC64CompilationCallback:\n"
00220 #else
00221     ".section \".opd\",\"aw\",@progbits\n"
00222     ".align 3\n"
00223 "PPC64CompilationCallback:\n"
00224     ".quad .L.PPC64CompilationCallback,.TOC.@tocbase,0\n"
00225     ".size PPC64CompilationCallback,24\n"
00226     ".previous\n"
00227     ".align 4\n"
00228     ".type PPC64CompilationCallback,@function\n"
00229 ".L.PPC64CompilationCallback:\n"
00230 #endif
00231 #  else
00232 asm(
00233     ".text\n"
00234     ".align 2\n"
00235     ".globl _PPC64CompilationCallback\n"
00236 "_PPC64CompilationCallback:\n"
00237 #  endif
00238     // Make space for 8 ints r[3-10] and 13 doubles f[1-13] and the 
00239     // FIXME: need to save v[0-19] for altivec?
00240     // Set up a proper stack frame
00241     // Layout
00242     //   PowerPC64 ABI linkage    -  48 bytes
00243     //                 parameters -  64 bytes
00244     //   13 double registers      - 104 bytes
00245     //   8 int registers          -  64 bytes
00246     "mflr 0\n"
00247     "std  0,  16(1)\n"
00248     "stdu 1, -280(1)\n"
00249     // Save all int arg registers
00250     "std 10, 272(1)\n"    "std 9,  264(1)\n"
00251     "std 8,  256(1)\n"    "std 7,  248(1)\n"
00252     "std 6,  240(1)\n"    "std 5,  232(1)\n"
00253     "std 4,  224(1)\n"    "std 3,  216(1)\n"
00254     // Save all call-clobbered FP regs.
00255     "stfd 13, 208(1)\n"    "stfd 12, 200(1)\n"
00256     "stfd 11, 192(1)\n"    "stfd 10, 184(1)\n"
00257     "stfd 9,  176(1)\n"    "stfd 8,  168(1)\n"
00258     "stfd 7,  160(1)\n"    "stfd 6,  152(1)\n"
00259     "stfd 5,  144(1)\n"    "stfd 4,  136(1)\n"
00260     "stfd 3,  128(1)\n"    "stfd 2,  120(1)\n"
00261     "stfd 1,  112(1)\n"
00262     // Arguments to Compilation Callback:
00263     // r3 - our lr (address of the call instruction in stub plus 4)
00264     // r4 - stub's lr (address of instruction that called the stub plus 4)
00265     // r5 - is64Bit - always 1.
00266     "mr   3, 0\n"      // return address (still in r0)
00267     "ld   5, 280(1)\n" // stub's frame
00268     "ld   4, 16(5)\n"  // stub's lr
00269     "li   5, 1\n"      // 1 == 64 bit
00270 #  ifdef __ELF__
00271     "bl LLVMPPCCompilationCallback\n"
00272     "nop\n"
00273 #  else
00274     "bl _LLVMPPCCompilationCallback\n"
00275 #  endif
00276     "mtctr 3\n"
00277     // Restore all int arg registers
00278     "ld 10, 272(1)\n"    "ld 9,  264(1)\n"
00279     "ld 8,  256(1)\n"    "ld 7,  248(1)\n"
00280     "ld 6,  240(1)\n"    "ld 5,  232(1)\n"
00281     "ld 4,  224(1)\n"    "ld 3,  216(1)\n"
00282     // Restore all FP arg registers
00283     "lfd 13, 208(1)\n"    "lfd 12, 200(1)\n"
00284     "lfd 11, 192(1)\n"    "lfd 10, 184(1)\n"
00285     "lfd 9,  176(1)\n"    "lfd 8,  168(1)\n"
00286     "lfd 7,  160(1)\n"    "lfd 6,  152(1)\n"
00287     "lfd 5,  144(1)\n"    "lfd 4,  136(1)\n"
00288     "lfd 3,  128(1)\n"    "lfd 2,  120(1)\n"
00289     "lfd 1,  112(1)\n"
00290     // Pop 3 frames off the stack and branch to target
00291     "ld  1, 280(1)\n"
00292     "ld  0, 16(1)\n"
00293     "mtlr 0\n"
00294     // XXX: any special TOC handling in the ELF case for JIT?
00295     "bctr\n"
00296     );
00297 #endif
00298 
00299 extern "C" {
00300 LLVM_LIBRARY_VISIBILITY void *
00301 LLVMPPCCompilationCallback(unsigned *StubCallAddrPlus4,
00302                            unsigned *OrigCallAddrPlus4,
00303                            bool is64Bit) {
00304   // Adjust the pointer to the address of the call instruction in the stub
00305   // emitted by emitFunctionStub, rather than the instruction after it.
00306   unsigned *StubCallAddr = StubCallAddrPlus4 - 1;
00307   unsigned *OrigCallAddr = OrigCallAddrPlus4 - 1;
00308 
00309   void *Target = JITCompilerFunction(StubCallAddr);
00310 
00311   // Check to see if *OrigCallAddr is a 'bl' instruction, and if we can rewrite
00312   // it to branch directly to the destination.  If so, rewrite it so it does not
00313   // need to go through the stub anymore.
00314   unsigned OrigCallInst = *OrigCallAddr;
00315   if ((OrigCallInst >> 26) == 18) {     // Direct call.
00316     intptr_t Offset = ((intptr_t)Target - (intptr_t)OrigCallAddr) >> 2;
00317     
00318     if (Offset >= -(1 << 23) && Offset < (1 << 23)) {   // In range?
00319       // Clear the original target out.
00320       OrigCallInst &= (63 << 26) | 3;
00321       // Fill in the new target.
00322       OrigCallInst |= (Offset & ((1 << 24)-1)) << 2;
00323       // Replace the call.
00324       *OrigCallAddr = OrigCallInst;
00325     }
00326   }
00327 
00328   // Assert that we are coming from a stub that was created with our
00329   // emitFunctionStub.
00330   if ((*StubCallAddr >> 26) == 18)
00331     StubCallAddr -= 3;
00332   else {
00333   assert((*StubCallAddr >> 26) == 19 && "Call in stub is not indirect!");
00334     StubCallAddr -= is64Bit ? 9 : 6;
00335   }
00336 
00337   // Rewrite the stub with an unconditional branch to the target, for any users
00338   // who took the address of the stub.
00339   EmitBranchToAt((intptr_t)StubCallAddr, (intptr_t)Target, false, is64Bit);
00340   sys::Memory::InvalidateInstructionCache(StubCallAddr, 7*4);
00341 
00342   // Put the address of the target function to call and the address to return to
00343   // after calling the target function in a place that is easy to get on the
00344   // stack after we restore all regs.
00345   return Target;
00346 }
00347 }
00348 
00349 
00350 
00351 TargetJITInfo::LazyResolverFn
00352 PPCJITInfo::getLazyResolverFunction(JITCompilerFn Fn) {
00353   JITCompilerFunction = Fn;
00354   return is64Bit ? PPC64CompilationCallback : PPC32CompilationCallback;
00355 }
00356 
00357 TargetJITInfo::StubLayout PPCJITInfo::getStubLayout() {
00358   // The stub contains up to 10 4-byte instructions, aligned at 4 bytes: 3
00359   // instructions to save the caller's address if this is a lazy-compilation
00360   // stub, plus a 1-, 4-, or 7-instruction sequence to load an arbitrary address
00361   // into a register and jump through it.
00362   StubLayout Result = {10*4, 4};
00363   return Result;
00364 }
00365 
00366 #if (defined(__POWERPC__) || defined (__ppc__) || defined(_POWER)) && \
00367 defined(__APPLE__)
00368 extern "C" void sys_icache_invalidate(const void *Addr, size_t len);
00369 #endif
00370 
00371 void *PPCJITInfo::emitFunctionStub(const Function* F, void *Fn,
00372                                    JITCodeEmitter &JCE) {
00373   // If this is just a call to an external function, emit a branch instead of a
00374   // call.  The code is the same except for one bit of the last instruction.
00375   if (Fn != (void*)(intptr_t)PPC32CompilationCallback && 
00376       Fn != (void*)(intptr_t)PPC64CompilationCallback) {
00377     void *Addr = (void*)JCE.getCurrentPCValue();
00378     JCE.emitWordBE(0);
00379     JCE.emitWordBE(0);
00380     JCE.emitWordBE(0);
00381     JCE.emitWordBE(0);
00382     JCE.emitWordBE(0);
00383     JCE.emitWordBE(0);
00384     JCE.emitWordBE(0);
00385     EmitBranchToAt((intptr_t)Addr, (intptr_t)Fn, false, is64Bit);
00386     sys::Memory::InvalidateInstructionCache(Addr, 7*4);
00387     return Addr;
00388   }
00389 
00390   void *Addr = (void*)JCE.getCurrentPCValue();
00391   if (is64Bit) {
00392     JCE.emitWordBE(0xf821ffb1);     // stdu r1,-80(r1)
00393     JCE.emitWordBE(0x7d6802a6);     // mflr r11
00394     JCE.emitWordBE(0xf9610060);     // std r11, 96(r1)
00395   } else if (TM.getSubtargetImpl()->isDarwinABI()){
00396     JCE.emitWordBE(0x9421ffe0);     // stwu r1,-32(r1)
00397     JCE.emitWordBE(0x7d6802a6);     // mflr r11
00398     JCE.emitWordBE(0x91610028);     // stw r11, 40(r1)
00399   } else {
00400     JCE.emitWordBE(0x9421ffe0);     // stwu r1,-32(r1)
00401     JCE.emitWordBE(0x7d6802a6);     // mflr r11
00402     JCE.emitWordBE(0x91610024);     // stw r11, 36(r1)
00403   }
00404   intptr_t BranchAddr = (intptr_t)JCE.getCurrentPCValue();
00405   JCE.emitWordBE(0);
00406   JCE.emitWordBE(0);
00407   JCE.emitWordBE(0);
00408   JCE.emitWordBE(0);
00409   JCE.emitWordBE(0);
00410   JCE.emitWordBE(0);
00411   JCE.emitWordBE(0);
00412   EmitBranchToAt(BranchAddr, (intptr_t)Fn, true, is64Bit);
00413   sys::Memory::InvalidateInstructionCache(Addr, 10*4);
00414   return Addr;
00415 }
00416 
00417 
00418 void PPCJITInfo::relocate(void *Function, MachineRelocation *MR,
00419                           unsigned NumRelocs, unsigned char* GOTBase) {
00420   for (unsigned i = 0; i != NumRelocs; ++i, ++MR) {
00421     unsigned *RelocPos = (unsigned*)Function + MR->getMachineCodeOffset()/4;
00422     intptr_t ResultPtr = (intptr_t)MR->getResultPointer();
00423     switch ((PPC::RelocationType)MR->getRelocationType()) {
00424     default: llvm_unreachable("Unknown relocation type!");
00425     case PPC::reloc_pcrel_bx:
00426       // PC-relative relocation for b and bl instructions.
00427       ResultPtr = (ResultPtr-(intptr_t)RelocPos) >> 2;
00428       assert(ResultPtr >= -(1 << 23) && ResultPtr < (1 << 23) &&
00429              "Relocation out of range!");
00430       *RelocPos |= (ResultPtr & ((1 << 24)-1))  << 2;
00431       break;
00432     case PPC::reloc_pcrel_bcx:
00433       // PC-relative relocation for BLT,BLE,BEQ,BGE,BGT,BNE, or other
00434       // bcx instructions.
00435       ResultPtr = (ResultPtr-(intptr_t)RelocPos) >> 2;
00436       assert(ResultPtr >= -(1 << 13) && ResultPtr < (1 << 13) &&
00437              "Relocation out of range!");
00438       *RelocPos |= (ResultPtr & ((1 << 14)-1))  << 2;
00439       break;
00440     case PPC::reloc_absolute_high:     // high bits of ref -> low 16 of instr
00441     case PPC::reloc_absolute_low: {    // low bits of ref  -> low 16 of instr
00442       ResultPtr += MR->getConstantVal();
00443 
00444       // If this is a high-part access, get the high-part.
00445       if (MR->getRelocationType() == PPC::reloc_absolute_high) {
00446         // If the low part will have a carry (really a borrow) from the low
00447         // 16-bits into the high 16, add a bit to borrow from.
00448         if (((int)ResultPtr << 16) < 0)
00449           ResultPtr += 1 << 16;
00450         ResultPtr >>= 16;
00451       }
00452 
00453       // Do the addition then mask, so the addition does not overflow the 16-bit
00454       // immediate section of the instruction.
00455       unsigned LowBits  = (*RelocPos + ResultPtr) & 65535;
00456       unsigned HighBits = *RelocPos & ~65535;
00457       *RelocPos = LowBits | HighBits;  // Slam into low 16-bits
00458       break;
00459     }
00460     case PPC::reloc_absolute_low_ix: {  // low bits of ref  -> low 14 of instr
00461       ResultPtr += MR->getConstantVal();
00462       // Do the addition then mask, so the addition does not overflow the 16-bit
00463       // immediate section of the instruction.
00464       unsigned LowBits  = (*RelocPos + ResultPtr) & 0xFFFC;
00465       unsigned HighBits = *RelocPos & 0xFFFF0003;
00466       *RelocPos = LowBits | HighBits;  // Slam into low 14-bits.
00467       break;
00468     }
00469     }
00470   }
00471 }
00472 
00473 void PPCJITInfo::replaceMachineCodeForFunction(void *Old, void *New) {
00474   EmitBranchToAt((intptr_t)Old, (intptr_t)New, false, is64Bit);
00475   sys::Memory::InvalidateInstructionCache(Old, 7*4);
00476 }