30#include "llvm/Config/llvm-config.h"
53 assert((PrevMask & ~NewMask).
none() &&
"Must not remove bits");
54 if (PrevMask.
any() || NewMask.
none())
59 for (; PSetI.
isValid(); ++PSetI)
60 CurrSetPressure[*PSetI] += Weight;
68 if (NewMask.
any() || PrevMask.
none())
73 for (; PSetI.
isValid(); ++PSetI) {
74 assert(CurrSetPressure[*PSetI] >= Weight &&
"register pressure underflow");
75 CurrSetPressure[*PSetI] -= Weight;
79#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
84 for (
unsigned i = 0, e = SetPressure.
size(); i < e; ++i) {
85 if (SetPressure[i] != 0) {
86 dbgs() <<
TRI->getRegPressureSetName(i) <<
"=" << SetPressure[i] <<
'\n';
96 dbgs() <<
"Max Pressure: ";
98 dbgs() <<
"Live In: ";
101 if (!
P.LaneMask.all())
106 dbgs() <<
"Live Out: ";
109 if (!
P.LaneMask.all())
119 dbgs() <<
"Curr Pressure: ";
127 const char *sep =
"";
144 dbgs() <<
"[Excess=";
146 dbgs() <<
", CriticalMax=";
148 dbgs() <<
", CurrentMax=";
158 if (PreviousMask.
any() || NewMask.
none())
163 for (; PSetI.
isValid(); ++PSetI) {
164 CurrSetPressure[*PSetI] += Weight;
227 unsigned NumRegUnits =
TRI.getNumRegs();
228 unsigned NumVirtRegs =
MRI.getNumVirtRegs();
230 this->NumRegUnits = NumRegUnits;
247 CurrSetPressure.clear();
248 LiveThruPressure.clear();
251 if (RequireIntervals)
268 bool TrackLaneMasks,
bool TrackUntiedDefs) {
276 this->TrackUntiedDefs = TrackUntiedDefs;
277 this->TrackLaneMasks = TrackLaneMasks;
279 if (RequireIntervals) {
280 assert(lis &&
"IntervalPressure requires LiveIntervals");
296 if (RequireIntervals)
304 if (RequireIntervals)
313 if (IdxPos == MBB->
end())
320 if (RequireIntervals)
332 if (RequireIntervals)
345 assert(LiveRegs.
size() == 0 &&
"no region boundary");
373 return Other.RegUnit == RegUnit;
375 if (
I == RegUnits.
end())
385 return Other.RegUnit == RegUnit;
387 if (
I == RegUnits.
end()) {
397 return Other.RegUnit == RegUnit;
399 if (
I == RegUnits.
end()) {
411 return Other.RegUnit == RegUnit;
413 if (
I != RegUnits.
end()) {
414 I->LaneMask &= ~Pair.LaneMask;
415 if (
I->LaneMask.none())
430 if (Property(SR, Pos))
431 Result |= SR.LaneMask;
433 }
else if (Property(LI, Pos)) {
434 Result = TrackLaneMasks ?
MRI.getMaxLaneMaskForVReg(RegUnit)
451 bool TrackLaneMasks,
Register RegUnit,
466class RegisterOperandsCollector {
477 : RegOpers(RegOpers),
TRI(
TRI),
MRI(
MRI), IgnoreDead(IgnoreDead) {}
481 collectOperand(*OperI);
490 collectOperandLanes(*OperI);
521 if (
Reg.isVirtual()) {
523 }
else if (
MRI.isAllocatable(
Reg)) {
536 pushRegLanes(
Reg, SubRegIdx, RegOpers.
Uses);
547 pushRegLanes(
Reg, SubRegIdx, RegOpers.
Defs);
551 void pushRegLanes(
Register Reg,
unsigned SubRegIdx,
553 if (
Reg.isVirtual()) {
555 ?
TRI.getSubRegIndexLaneMask(SubRegIdx)
556 :
MRI.getMaxLaneMaskForVReg(
Reg);
558 }
else if (
MRI.isAllocatable(
Reg)) {
570 bool TrackLaneMasks,
bool IgnoreDead) {
581 for (
auto *RI =
Defs.begin(); RI !=
Defs.end(); ) {
602 for (
auto *
I =
Defs.begin();
I !=
Defs.end();) {
608 if (RegUnit.
isVirtual() && AddFlagsMI !=
nullptr &&
609 (LiveAfter & ~
I->LaneMask).none())
613 if (ActualDef.
none()) {
616 I->LaneMask = ActualDef;
620 for (
auto *
I =
Uses.begin();
I !=
Uses.end();) {
624 if (LaneMask.
none()) {
627 I->LaneMask = LaneMask;
631 if (AddFlagsMI !=
nullptr) {
638 if (LiveAfter.
none())
673 for (; PSetI.
isValid(); ++PSetI) {
676 for (;
I !=
E &&
I->isValid(); ++
I) {
677 if (
I->getPSet() >= *PSetI)
684 if (!
I->isValid() ||
I->getPSet() != *PSetI) {
690 unsigned NewUnitInc =
I->getUnitInc() + Weight;
691 if (NewUnitInc != 0) {
692 I->setUnitInc(NewUnitInc);
696 for (J = std::next(
I); J !=
E && J->
isValid(); ++J, ++
I)
718 return Other.RegUnit == RegUnit;
722 if (
I == LiveInOrOut.
end()) {
727 PrevMask =
I->LaneMask;
729 I->LaneMask = NewMask;
764 assert(!CurrPos->isDebugOrPseudoInstr());
775 LaneBitmask NewMask = PreviousMask & ~Def.LaneMask;
777 LaneBitmask LiveOut = Def.LaneMask & ~PreviousMask;
783 PreviousMask = LiveOut;
786 if (NewMask.
none()) {
789 if (TrackLaneMasks && LiveUses !=
nullptr)
797 if (RequireIntervals)
806 if (NewMask == PreviousMask)
810 if (PreviousMask.
none()) {
811 if (LiveUses !=
nullptr) {
812 if (!TrackLaneMasks) {
819 bool IsRedef =
I != LiveUses->
end();
831 if (RequireIntervals) {
840 if (TrackUntiedDefs) {
844 (LiveRegs.
contains(RegUnit) & Def.LaneMask).none())
845 UntiedDefs.insert(RegUnit);
863 if (RequireIntervals && !CurrPos->isDebugOrPseudoInstr())
873 if (CurrPos->isDebugInstr() || CurrPos->isPseudoProbe()) {
883 if (TrackLaneMasks) {
886 }
else if (RequireIntervals) {
890 recede(RegOpers, LiveUses);
895 assert(!TrackUntiedDefs &&
"unsupported mode");
901 if (RequireIntervals)
906 if (RequireIntervals)
922 if (RequireIntervals) {
924 if (LastUseMask.
any()) {
949 if (TrackLaneMasks) {
963 for (
unsigned i = 0, e = OldPressureVec.
size(); i < e; ++i) {
964 unsigned POld = OldPressureVec[i];
965 unsigned PNew = NewPressureVec[i];
966 int PDiff = (int)PNew - (
int)POld;
971 if (!LiveThruPressureVec.
empty())
972 Limit += LiveThruPressureVec[i];
978 PDiff = PNew - Limit;
979 }
else if (Limit > PNew)
980 PDiff = Limit - POld;
1004 unsigned CritIdx = 0, CritEnd = CriticalPSets.
size();
1005 for (
unsigned i = 0, e = OldMaxPressureVec.
size(); i < e; ++i) {
1006 unsigned POld = OldMaxPressureVec[i];
1007 unsigned PNew = NewMaxPressureVec[i];
1012 while (CritIdx != CritEnd && CriticalPSets[CritIdx].getPSet() < i)
1015 if (CritIdx != CritEnd && CriticalPSets[CritIdx].getPSet() == i) {
1016 int PDiff = (int)PNew - (
int)CriticalPSets[CritIdx].getUnitInc();
1041 assert(!
MI->isDebugOrPseudoInstr() &&
"Expect a nondebug instruction.");
1044 if (RequireIntervals)
1053 else if (RequireIntervals)
1066 LaneBitmask LiveAfter = (LiveLanes & ~DefLanes) | UseLanes;
1099 std::vector<unsigned> SavedPressure = CurrSetPressure;
1100 std::vector<unsigned> SavedMaxPressure =
P.MaxSetPressure;
1107 MaxPressureLimit, Delta);
1112 P.MaxSetPressure.swap(SavedMaxPressure);
1113 CurrSetPressure.swap(SavedPressure);
1122 if (Delta != Delta2) {
1123 dbgs() <<
"PDiff: ";
1125 dbgs() <<
"DELTA: " << *
MI;
1164 unsigned CritIdx = 0, CritEnd = CriticalPSets.
size();
1166 PDiffI = PDiff.
begin(), PDiffE = PDiff.
end();
1167 PDiffI != PDiffE && PDiffI->
isValid(); ++PDiffI) {
1169 unsigned PSetID = PDiffI->getPSet();
1171 if (!LiveThruPressure.empty())
1172 Limit += LiveThruPressure[PSetID];
1174 unsigned POld = CurrSetPressure[PSetID];
1175 unsigned MOld =
P.MaxSetPressure[PSetID];
1176 unsigned MNew = MOld;
1178 unsigned PNew = POld + PDiffI->getUnitInc();
1179 assert((PDiffI->getUnitInc() >= 0) == (PNew >= POld)
1180 &&
"PSet overflow/underflow");
1185 unsigned ExcessInc = 0;
1187 ExcessInc = POld > Limit ? PNew - POld : PNew - Limit;
1188 else if (POld > Limit)
1189 ExcessInc = Limit - POld;
1199 while (CritIdx != CritEnd && CriticalPSets[CritIdx].getPSet() < PSetID)
1202 if (CritIdx != CritEnd && CriticalPSets[CritIdx].getPSet() == PSetID) {
1203 int CritInc = (int)MNew - (
int)CriticalPSets[CritIdx].getUnitInc();
1204 if (CritInc > 0 && CritInc <= std::numeric_limits<int16_t>::max()) {
1231 if (InstSlot >= PriorUseIdx && InstSlot < NextUseIdx) {
1234 LastUseMask &= ~UseMask;
1235 if (LastUseMask.
none())
1244 assert(RequireIntervals);
1254 assert(RequireIntervals);
1258 const LiveRange::Segment *S = LR.getSegmentContaining(Pos);
1259 return S != nullptr && S->end == Pos.getRegSlot();
1265 assert(RequireIntervals);
1282 assert(!
MI->isDebugOrPseudoInstr() &&
"Expect a nondebug instruction.");
1285 if (RequireIntervals)
1294 if (RequireIntervals) {
1298 if (LastUseMask.
none())
1308 if (LastUseMask.
none())
1345 std::vector<unsigned> SavedPressure = CurrSetPressure;
1346 std::vector<unsigned> SavedMaxPressure =
P.MaxSetPressure;
1353 MaxPressureLimit, Delta);
1358 P.MaxSetPressure.swap(SavedMaxPressure);
1359 CurrSetPressure.swap(SavedPressure);
1365 std::vector<unsigned> &PressureResult,
1366 std::vector<unsigned> &MaxPressureResult) {
1368 PressureResult = CurrSetPressure;
1369 MaxPressureResult =
P.MaxSetPressure;
1374 P.MaxSetPressure.swap(MaxPressureResult);
1375 CurrSetPressure.swap(PressureResult);
1381 std::vector<unsigned> &PressureResult,
1382 std::vector<unsigned> &MaxPressureResult) {
1384 PressureResult = CurrSetPressure;
1385 MaxPressureResult =
P.MaxSetPressure;
1390 P.MaxSetPressure.swap(MaxPressureResult);
1391 CurrSetPressure.swap(PressureResult);
unsigned const MachineRegisterInfo * MRI
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
#define LLVM_DUMP_METHOD
Mark debug helper function definitions like dump() that should not be stripped from debug builds.
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
A common definition of LaneBitmask for use in TableGen and CodeGen.
unsigned const TargetRegisterInfo * TRI
Register Usage Information Collector
static void computeExcessPressureDelta(ArrayRef< unsigned > OldPressureVec, ArrayRef< unsigned > NewPressureVec, RegPressureDelta &Delta, const RegisterClassInfo *RCI, ArrayRef< unsigned > LiveThruPressureVec)
Find the max change in excess pressure across all sets.
static void removeRegLanes(SmallVectorImpl< RegisterMaskPair > &RegUnits, RegisterMaskPair Pair)
static void increaseSetPressure(std::vector< unsigned > &CurrSetPressure, const MachineRegisterInfo &MRI, unsigned Reg, LaneBitmask PrevMask, LaneBitmask NewMask)
Increase pressure for each pressure set provided by TargetRegisterInfo.
static void decreaseSetPressure(std::vector< unsigned > &CurrSetPressure, const MachineRegisterInfo &MRI, Register Reg, LaneBitmask PrevMask, LaneBitmask NewMask)
Decrease pressure for each pressure set provided by TargetRegisterInfo.
static void computeMaxPressureDelta(ArrayRef< unsigned > OldMaxPressureVec, ArrayRef< unsigned > NewMaxPressureVec, ArrayRef< PressureChange > CriticalPSets, ArrayRef< unsigned > MaxPressureLimit, RegPressureDelta &Delta)
Find the max change in max pressure that either surpasses a critical PSet limit or exceeds the curren...
static const LiveRange * getLiveRange(const LiveIntervals &LIS, unsigned Reg)
static LaneBitmask getLiveLanesAt(const LiveIntervals &LIS, const MachineRegisterInfo &MRI, bool TrackLaneMasks, Register RegUnit, SlotIndex Pos)
static void addRegLanes(SmallVectorImpl< RegisterMaskPair > &RegUnits, RegisterMaskPair Pair)
static LaneBitmask findUseBetween(unsigned Reg, LaneBitmask LastUseMask, SlotIndex PriorUseIdx, SlotIndex NextUseIdx, const MachineRegisterInfo &MRI, const LiveIntervals *LIS)
Helper to find a vreg use between two indices [PriorUseIdx, NextUseIdx).
static void setRegZero(SmallVectorImpl< RegisterMaskPair > &RegUnits, Register RegUnit)
static LaneBitmask getLanesWithProperty(const LiveIntervals &LIS, const MachineRegisterInfo &MRI, bool TrackLaneMasks, Register RegUnit, SlotIndex Pos, LaneBitmask SafeDefault, bool(*Property)(const LiveRange &LR, SlotIndex Pos))
static LaneBitmask getRegLanes(ArrayRef< RegisterMaskPair > RegUnits, Register RegUnit)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file defines the SmallVector class.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
bool empty() const
empty - Check if the array is empty.
ConstMIBundleOperands - Iterate over all operands in a const bundle of machine instructions.
A live range for subregisters.
LiveInterval - This class represents the liveness of a register, or stack slot.
bool hasSubRanges() const
Returns true if subregister liveness information is available.
iterator_range< subrange_iterator > subranges()
SlotIndex getInstructionIndex(const MachineInstr &Instr) const
Returns the base index of the given instruction.
SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const
Return the last index in the given basic block.
LiveRange * getCachedRegUnit(unsigned Unit)
Return the live range for register unit Unit if it has already been computed, or nullptr if it hasn't...
LiveInterval & getInterval(Register Reg)
Result of a LiveRange query.
bool isDeadDef() const
Return true if this instruction has a dead def.
This class represents the liveness of a register, stack slot, etc.
const Segment * getSegmentContaining(SlotIndex Idx) const
Return the segment that contains the specified index, or null if there is none.
bool liveAt(SlotIndex index) const
LiveQueryResult Query(SlotIndex Idx) const
Query Liveness at Idx.
LaneBitmask contains(Register Reg) const
void init(const MachineRegisterInfo &MRI)
LaneBitmask insert(RegisterMaskPair Pair)
Mark the Pair.LaneMask lanes of Pair.Reg as live.
LaneBitmask erase(RegisterMaskPair Pair)
Clears the Pair.LaneMask lanes of Pair.Reg (mark them as dead).
void appendTo(ContainerT &To) const
bool isValid() const
isValid - Returns true until all the operands have been visited.
MachineInstrBundleIterator< const MachineInstr > const_iterator
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
Representation of each machine instruction.
void setRegisterDefReadUndef(Register Reg, bool IsUndef=true)
Mark all subregister defs of register Reg with the undef flag.
MachineOperand class - Representation of each machine instruction operand.
unsigned getSubReg() const
bool readsReg() const
readsReg - Returns true if this operand reads the previous value of its register.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
MachineInstr * getParent()
getParent - Return the instruction that this operand belongs to.
Register getReg() const
getReg - Returns the register number.
bool isInternalRead() const
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
PSetIterator getPressureSets(Register RegUnit) const
Get an iterator over the pressure sets affected by the given physical or virtual register.
unsigned getNumVirtRegs() const
getNumVirtRegs - Return the number of virtual registers created.
Iterate over the pressure sets affected by the given physical or virtual register.
unsigned getWeight() const
Capture a change in pressure for a single pressure set.
unsigned getPSetOrMax() const
List of PressureChanges in order of increasing, unique PSetID.
void dump(const TargetRegisterInfo &TRI) const
void addPressureChange(Register RegUnit, bool IsDec, const MachineRegisterInfo *MRI)
Add a change in pressure to the pressure diff of a given instruction.
const_iterator end() const
const_iterator begin() const
void addInstruction(unsigned Idx, const RegisterOperands &RegOpers, const MachineRegisterInfo &MRI)
Record pressure difference induced by the given operand list to node with index Idx.
void init(unsigned N)
Initialize an array of N PressureDiffs.
Track the current register pressure at some position in the instruction stream, and remember the high...
void closeRegion()
Finalize the region boundaries and recored live ins and live outs.
void recede(SmallVectorImpl< RegisterMaskPair > *LiveUses=nullptr)
Recede across the previous instruction.
void closeBottom()
Set the boundary for the bottom of the region and summarize live outs.
void bumpDownwardPressure(const MachineInstr *MI)
Record the downward impact of a single instruction on current register pressure.
void recedeSkipDebugValues()
Recede until we find an instruction which is not a DebugValue.
void getMaxUpwardPressureDelta(const MachineInstr *MI, PressureDiff *PDiff, RegPressureDelta &Delta, ArrayRef< PressureChange > CriticalPSets, ArrayRef< unsigned > MaxPressureLimit)
Consider the pressure increase caused by traversing this instruction bottom-up.
void initLiveThru(const RegPressureTracker &RPTracker)
Initialize the LiveThru pressure set based on the untied defs found in RPTracker.
void discoverLiveInOrOut(RegisterMaskPair Pair, SmallVectorImpl< RegisterMaskPair > &LiveInOrOut)
void init(const MachineFunction *mf, const RegisterClassInfo *rci, const LiveIntervals *lis, const MachineBasicBlock *mbb, MachineBasicBlock::const_iterator pos, bool TrackLaneMasks, bool TrackUntiedDefs)
Setup the RegPressureTracker.
void discoverLiveOut(RegisterMaskPair Pair)
Add Reg to the live out set and increase max pressure.
bool isBottomClosed() const
Does this pressure result have a valid bottom position and live outs.
bool hasUntiedDef(Register VirtReg) const
void discoverLiveIn(RegisterMaskPair Pair)
Add Reg to the live in set and increase max pressure.
void closeTop()
Set the boundary for the top of the region and summarize live ins.
LaneBitmask getLiveLanesAt(Register RegUnit, SlotIndex Pos) const
void getMaxDownwardPressureDelta(const MachineInstr *MI, RegPressureDelta &Delta, ArrayRef< PressureChange > CriticalPSets, ArrayRef< unsigned > MaxPressureLimit)
Consider the pressure increase caused by traversing this instruction top-down.
void advance()
Advance across the current instruction.
bool isTopClosed() const
Does this pressure result have a valid top position and live ins.
void bumpUpwardPressure(const MachineInstr *MI)
Record the upward impact of a single instruction on current register pressure.
void bumpDeadDefs(ArrayRef< RegisterMaskPair > DeadDefs)
void getDownwardPressure(const MachineInstr *MI, std::vector< unsigned > &PressureResult, std::vector< unsigned > &MaxPressureResult)
Get the pressure of each PSet after traversing this instruction top-down.
SlotIndex getCurrSlot() const
Get the SlotIndex for the first nondebug instruction including or after the current position.
LaneBitmask getLastUsedLanes(Register RegUnit, SlotIndex Pos) const
void getUpwardPressure(const MachineInstr *MI, std::vector< unsigned > &PressureResult, std::vector< unsigned > &MaxPressureResult)
Get the pressure of each PSet after traversing this instruction bottom-up.
LaneBitmask getLiveThroughAt(Register RegUnit, SlotIndex Pos) const
void increaseRegPressure(Register RegUnit, LaneBitmask PreviousMask, LaneBitmask NewMask)
void decreaseRegPressure(Register RegUnit, LaneBitmask PreviousMask, LaneBitmask NewMask)
void addLiveRegs(ArrayRef< RegisterMaskPair > Regs)
Force liveness of virtual registers or physical register units.
void getUpwardPressureDelta(const MachineInstr *MI, PressureDiff &PDiff, RegPressureDelta &Delta, ArrayRef< PressureChange > CriticalPSets, ArrayRef< unsigned > MaxPressureLimit) const
This is the fast version of querying register pressure that does not directly depend on current liven...
unsigned getRegPressureSetLimit(unsigned Idx) const
Get the register unit limit for the given pressure set index.
List of registers defined and used by a machine instruction.
void collect(const MachineInstr &MI, const TargetRegisterInfo &TRI, const MachineRegisterInfo &MRI, bool TrackLaneMasks, bool IgnoreDead)
Analyze the given instruction MI and fill in the Uses, Defs and DeadDefs list based on the MachineOpe...
void adjustLaneLiveness(const LiveIntervals &LIS, const MachineRegisterInfo &MRI, SlotIndex Pos, MachineInstr *AddFlagsMI=nullptr)
Use liveness information to find out which uses/defs are partially undefined/dead and adjust the Regi...
SmallVector< RegisterMaskPair, 8 > DeadDefs
List of virtual registers and register units defined by the instruction but dead.
void detectDeadDefs(const MachineInstr &MI, const LiveIntervals &LIS)
Use liveness information to find dead defs not marked with a dead flag and move them to the DeadDefs ...
SmallVector< RegisterMaskPair, 8 > Uses
List of virtual registers and register units read by the instruction.
SmallVector< RegisterMaskPair, 8 > Defs
List of virtual registers and register units defined by the instruction which are not dead.
Wrapper class representing virtual and physical registers.
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
static constexpr bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
SlotIndex - An opaque wrapper around machine indexes.
SlotIndex getDeadSlot() const
Returns the dead def kill slot for the current instruction.
SlotIndex getBaseIndex() const
Returns the base index for associated with this index.
SlotIndex getRegSlot(bool EC=false) const
Returns the register use/def slot in the current instruction for a normal or early-clobber def.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
iterator erase(const_iterator CI)
void push_back(const T &Elt)
void clear()
clear - Clears the set.
void setUniverse(unsigned U)
setUniverse - Set the universe size which determines the largest key the set can hold.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual unsigned getNumRegPressureSets() const =0
Get the number of dimensions of register pressure.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
A Use represents the edge between a Value definition and its users.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
This is an optimization pass for GlobalISel generic memory operations.
IterT next_nodbg(IterT It, IterT End, bool SkipPseudoOp=true)
Increment It, then continue incrementing it while it points to a debug instruction.
Printable PrintLaneMask(LaneBitmask LaneMask)
Create Printable object to print LaneBitmasks on a raw_ostream.
LLVM_ATTRIBUTE_RETURNS_NONNULL void * safe_calloc(size_t Count, size_t Sz)
IterT skipDebugInstructionsForward(IterT It, IterT End, bool SkipPseudoOp=true)
Increment It until it points to a non-debug instruction or to End and return the resulting iterator.
Printable printVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI)
Create Printable object to print virtual registers and physical registers on a raw_ostream.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
void dumpRegSetPressure(ArrayRef< unsigned > SetPressure, const TargetRegisterInfo *TRI)
IterT prev_nodbg(IterT It, IterT Begin, bool SkipPseudoOp=true)
Decrement It, then continue decrementing it while it points to a debug instruction.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
RegisterPressure computed within a region of instructions delimited by TopIdx and BottomIdx.
void reset()
Clear the result so it can be used for another round of pressure tracking.
void openBottom(SlotIndex PrevBottom)
If the current bottom is not greater than the previous index, open it.
SlotIndex TopIdx
Record the boundary of the region being tracked.
void openTop(SlotIndex NextTop)
If the current top is not less than or equal to the next index, open it.
static constexpr LaneBitmask getAll()
constexpr bool none() const
constexpr bool any() const
static constexpr LaneBitmask getNone()
This represents a simple continuous liveness interval for a value.
Store the effects of a change in pressure on things that MI scheduler cares about.
PressureChange CriticalMax
PressureChange CurrentMax
RegisterPressure computed within a region of instructions delimited by TopPos and BottomPos.
MachineBasicBlock::const_iterator TopPos
Record the boundary of the region being tracked.
MachineBasicBlock::const_iterator BottomPos
void openTop(MachineBasicBlock::const_iterator PrevTop)
If the current top is the previous instruction (before receding), open it.
void reset()
Clear the result so it can be used for another round of pressure tracking.
void openBottom(MachineBasicBlock::const_iterator PrevBottom)
If the current bottom is the previous instr (before advancing), open it.
Register RegUnit
Virtual register or register unit.
SmallVector< RegisterMaskPair, 8 > LiveInRegs
List of live in virtual registers or physical register units.
void dump(const TargetRegisterInfo *TRI) const
std::vector< unsigned > MaxSetPressure
Map of max reg pressure indexed by pressure set ID, not class ID.
SmallVector< RegisterMaskPair, 8 > LiveOutRegs