LLVM 19.0.0git
SchedulerRegistry.h
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1//===- llvm/CodeGen/SchedulerRegistry.h -------------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the implementation for instruction scheduler function
10// pass registry (RegisterScheduler).
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_CODEGEN_SCHEDULERREGISTRY_H
15#define LLVM_CODEGEN_SCHEDULERREGISTRY_H
16
19
20namespace llvm {
21
22//===----------------------------------------------------------------------===//
23///
24/// RegisterScheduler class - Track the registration of instruction schedulers.
25///
26//===----------------------------------------------------------------------===//
27
28class ScheduleDAGSDNodes;
29class SelectionDAGISel;
30
32 : public MachinePassRegistryNode<ScheduleDAGSDNodes *(*)(SelectionDAGISel *,
33 CodeGenOptLevel)> {
34public:
37
39
40 RegisterScheduler(const char *N, const char *D, FunctionPassCtor C)
42 Registry.Add(this);
43 }
44 ~RegisterScheduler() { Registry.Remove(this); }
45
46
47 // Accessors.
50 }
51
53 return (RegisterScheduler *)Registry.getList();
54 }
55
57 Registry.setListener(L);
58 }
59};
60
61/// createBURRListDAGScheduler - This creates a bottom up register usage
62/// reduction list scheduler.
63ScheduleDAGSDNodes *createBURRListDAGScheduler(SelectionDAGISel *IS,
64 CodeGenOptLevel OptLevel);
65
66/// createSourceListDAGScheduler - This creates a bottom up list scheduler that
67/// schedules nodes in source code order when possible.
68ScheduleDAGSDNodes *createSourceListDAGScheduler(SelectionDAGISel *IS,
69 CodeGenOptLevel OptLevel);
70
71/// createHybridListDAGScheduler - This creates a bottom up register pressure
72/// aware list scheduler that make use of latency information to avoid stalls
73/// for long latency instructions in low register pressure mode. In high
74/// register pressure mode it schedules to reduce register pressure.
75ScheduleDAGSDNodes *createHybridListDAGScheduler(SelectionDAGISel *IS,
77
78/// createILPListDAGScheduler - This creates a bottom up register pressure
79/// aware list scheduler that tries to increase instruction level parallelism
80/// in low register pressure mode. In high register pressure mode it schedules
81/// to reduce register pressure.
82ScheduleDAGSDNodes *createILPListDAGScheduler(SelectionDAGISel *IS,
84
85/// createFastDAGScheduler - This creates a "fast" scheduler.
86///
87ScheduleDAGSDNodes *createFastDAGScheduler(SelectionDAGISel *IS,
88 CodeGenOptLevel OptLevel);
89
90/// createVLIWDAGScheduler - Scheduler for VLIW targets. This creates top down
91/// DFA driven list scheduler with clustering heuristic to control
92/// register pressure.
93ScheduleDAGSDNodes *createVLIWDAGScheduler(SelectionDAGISel *IS,
94 CodeGenOptLevel OptLevel);
95/// createDefaultScheduler - This creates an instruction scheduler appropriate
96/// for the target.
97ScheduleDAGSDNodes *createDefaultScheduler(SelectionDAGISel *IS,
98 CodeGenOptLevel OptLevel);
99
100/// createDAGLinearizer - This creates a "no-scheduling" scheduler which
101/// linearize the DAG using topological order.
102ScheduleDAGSDNodes *createDAGLinearizer(SelectionDAGISel *IS,
103 CodeGenOptLevel OptLevel);
104
105} // end namespace llvm
106
107#endif // LLVM_CODEGEN_SCHEDULERREGISTRY_H
static GCRegistry::Add< StatepointGC > D("statepoint-example", "an example strategy for statepoint")
MachinePassRegistryListener - Listener to adds and removals of nodes in registration list.
MachinePassRegistryNode - Machine pass node stored in registration list.
MachinePassRegistryNode * getNext() const
MachinePassRegistry - Track the registration of machine passes.
ScheduleDAGSDNodes *(*)(SelectionDAGISel *, CodeGenOptLevel) FunctionPassCtor
static RegisterScheduler * getList()
static void setListener(MachinePassRegistryListener< FunctionPassCtor > *L)
RegisterScheduler(const char *N, const char *D, FunctionPassCtor C)
static MachinePassRegistry< FunctionPassCtor > Registry
RegisterScheduler class - Track the registration of instruction schedulers.
RegisterScheduler * getNext() const
A static registration template.
Definition: Registry.h:114
A global registry used in conjunction with static constructors to make pluggable components (like tar...
Definition: Registry.h:44
ScheduleDAGSDNodes - A ScheduleDAG for scheduling SDNode-based DAGs.
SelectionDAGISel - This is the common base class used for SelectionDAG-based pattern-matching instruc...
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
ScheduleDAGSDNodes * createDefaultScheduler(SelectionDAGISel *IS, CodeGenOptLevel OptLevel)
createDefaultScheduler - This creates an instruction scheduler appropriate for the target.
ScheduleDAGSDNodes * createBURRListDAGScheduler(SelectionDAGISel *IS, CodeGenOptLevel OptLevel)
createBURRListDAGScheduler - This creates a bottom up register usage reduction list scheduler.
ScheduleDAGSDNodes * createHybridListDAGScheduler(SelectionDAGISel *IS, CodeGenOptLevel)
createHybridListDAGScheduler - This creates a bottom up register pressure aware list scheduler that m...
ScheduleDAGSDNodes * createFastDAGScheduler(SelectionDAGISel *IS, CodeGenOptLevel OptLevel)
createFastDAGScheduler - This creates a "fast" scheduler.
ScheduleDAGSDNodes * createDAGLinearizer(SelectionDAGISel *IS, CodeGenOptLevel OptLevel)
createDAGLinearizer - This creates a "no-scheduling" scheduler which linearize the DAG using topologi...
CodeGenOptLevel
Code generation optimization level.
Definition: CodeGen.h:54
ScheduleDAGSDNodes * createSourceListDAGScheduler(SelectionDAGISel *IS, CodeGenOptLevel OptLevel)
createSourceListDAGScheduler - This creates a bottom up list scheduler that schedules nodes in source...
ScheduleDAGSDNodes * createILPListDAGScheduler(SelectionDAGISel *IS, CodeGenOptLevel)
createILPListDAGScheduler - This creates a bottom up register pressure aware list scheduler that trie...
ScheduleDAGSDNodes * createVLIWDAGScheduler(SelectionDAGISel *IS, CodeGenOptLevel OptLevel)
createVLIWDAGScheduler - Scheduler for VLIW targets.
#define N