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SystemZISelLowering.cpp
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00001 //===-- SystemZISelLowering.cpp - SystemZ DAG lowering implementation -----===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file implements the SystemZTargetLowering class.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #include "SystemZISelLowering.h"
00015 #include "SystemZCallingConv.h"
00016 #include "SystemZConstantPoolValue.h"
00017 #include "SystemZMachineFunctionInfo.h"
00018 #include "SystemZTargetMachine.h"
00019 #include "llvm/CodeGen/CallingConvLower.h"
00020 #include "llvm/CodeGen/MachineInstrBuilder.h"
00021 #include "llvm/CodeGen/MachineRegisterInfo.h"
00022 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
00023 #include <cctype>
00024 
00025 using namespace llvm;
00026 
00027 #define DEBUG_TYPE "systemz-lower"
00028 
00029 namespace {
00030 // Represents a sequence for extracting a 0/1 value from an IPM result:
00031 // (((X ^ XORValue) + AddValue) >> Bit)
00032 struct IPMConversion {
00033   IPMConversion(unsigned xorValue, int64_t addValue, unsigned bit)
00034     : XORValue(xorValue), AddValue(addValue), Bit(bit) {}
00035 
00036   int64_t XORValue;
00037   int64_t AddValue;
00038   unsigned Bit;
00039 };
00040 
00041 // Represents information about a comparison.
00042 struct Comparison {
00043   Comparison(SDValue Op0In, SDValue Op1In)
00044     : Op0(Op0In), Op1(Op1In), Opcode(0), ICmpType(0), CCValid(0), CCMask(0) {}
00045 
00046   // The operands to the comparison.
00047   SDValue Op0, Op1;
00048 
00049   // The opcode that should be used to compare Op0 and Op1.
00050   unsigned Opcode;
00051 
00052   // A SystemZICMP value.  Only used for integer comparisons.
00053   unsigned ICmpType;
00054 
00055   // The mask of CC values that Opcode can produce.
00056   unsigned CCValid;
00057 
00058   // The mask of CC values for which the original condition is true.
00059   unsigned CCMask;
00060 };
00061 } // end anonymous namespace
00062 
00063 // Classify VT as either 32 or 64 bit.
00064 static bool is32Bit(EVT VT) {
00065   switch (VT.getSimpleVT().SimpleTy) {
00066   case MVT::i32:
00067     return true;
00068   case MVT::i64:
00069     return false;
00070   default:
00071     llvm_unreachable("Unsupported type");
00072   }
00073 }
00074 
00075 // Return a version of MachineOperand that can be safely used before the
00076 // final use.
00077 static MachineOperand earlyUseOperand(MachineOperand Op) {
00078   if (Op.isReg())
00079     Op.setIsKill(false);
00080   return Op;
00081 }
00082 
00083 SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &tm,
00084                                              const SystemZSubtarget &STI)
00085     : TargetLowering(tm), Subtarget(STI) {
00086   MVT PtrVT = getPointerTy();
00087 
00088   // Set up the register classes.
00089   if (Subtarget.hasHighWord())
00090     addRegisterClass(MVT::i32, &SystemZ::GRX32BitRegClass);
00091   else
00092     addRegisterClass(MVT::i32, &SystemZ::GR32BitRegClass);
00093   addRegisterClass(MVT::i64,  &SystemZ::GR64BitRegClass);
00094   addRegisterClass(MVT::f32,  &SystemZ::FP32BitRegClass);
00095   addRegisterClass(MVT::f64,  &SystemZ::FP64BitRegClass);
00096   addRegisterClass(MVT::f128, &SystemZ::FP128BitRegClass);
00097 
00098   // Compute derived properties from the register classes
00099   computeRegisterProperties(Subtarget.getRegisterInfo());
00100 
00101   // Set up special registers.
00102   setExceptionPointerRegister(SystemZ::R6D);
00103   setExceptionSelectorRegister(SystemZ::R7D);
00104   setStackPointerRegisterToSaveRestore(SystemZ::R15D);
00105 
00106   // TODO: It may be better to default to latency-oriented scheduling, however
00107   // LLVM's current latency-oriented scheduler can't handle physreg definitions
00108   // such as SystemZ has with CC, so set this to the register-pressure
00109   // scheduler, because it can.
00110   setSchedulingPreference(Sched::RegPressure);
00111 
00112   setBooleanContents(ZeroOrOneBooleanContent);
00113   setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
00114 
00115   // Instructions are strings of 2-byte aligned 2-byte values.
00116   setMinFunctionAlignment(2);
00117 
00118   // Handle operations that are handled in a similar way for all types.
00119   for (unsigned I = MVT::FIRST_INTEGER_VALUETYPE;
00120        I <= MVT::LAST_FP_VALUETYPE;
00121        ++I) {
00122     MVT VT = MVT::SimpleValueType(I);
00123     if (isTypeLegal(VT)) {
00124       // Lower SET_CC into an IPM-based sequence.
00125       setOperationAction(ISD::SETCC, VT, Custom);
00126 
00127       // Expand SELECT(C, A, B) into SELECT_CC(X, 0, A, B, NE).
00128       setOperationAction(ISD::SELECT, VT, Expand);
00129 
00130       // Lower SELECT_CC and BR_CC into separate comparisons and branches.
00131       setOperationAction(ISD::SELECT_CC, VT, Custom);
00132       setOperationAction(ISD::BR_CC,     VT, Custom);
00133     }
00134   }
00135 
00136   // Expand jump table branches as address arithmetic followed by an
00137   // indirect jump.
00138   setOperationAction(ISD::BR_JT, MVT::Other, Expand);
00139 
00140   // Expand BRCOND into a BR_CC (see above).
00141   setOperationAction(ISD::BRCOND, MVT::Other, Expand);
00142 
00143   // Handle integer types.
00144   for (unsigned I = MVT::FIRST_INTEGER_VALUETYPE;
00145        I <= MVT::LAST_INTEGER_VALUETYPE;
00146        ++I) {
00147     MVT VT = MVT::SimpleValueType(I);
00148     if (isTypeLegal(VT)) {
00149       // Expand individual DIV and REMs into DIVREMs.
00150       setOperationAction(ISD::SDIV, VT, Expand);
00151       setOperationAction(ISD::UDIV, VT, Expand);
00152       setOperationAction(ISD::SREM, VT, Expand);
00153       setOperationAction(ISD::UREM, VT, Expand);
00154       setOperationAction(ISD::SDIVREM, VT, Custom);
00155       setOperationAction(ISD::UDIVREM, VT, Custom);
00156 
00157       // Lower ATOMIC_LOAD and ATOMIC_STORE into normal volatile loads and
00158       // stores, putting a serialization instruction after the stores.
00159       setOperationAction(ISD::ATOMIC_LOAD,  VT, Custom);
00160       setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
00161 
00162       // Lower ATOMIC_LOAD_SUB into ATOMIC_LOAD_ADD if LAA and LAAG are
00163       // available, or if the operand is constant.
00164       setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
00165 
00166       // No special instructions for these.
00167       setOperationAction(ISD::CTPOP,           VT, Expand);
00168       setOperationAction(ISD::CTTZ,            VT, Expand);
00169       setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
00170       setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
00171       setOperationAction(ISD::ROTR,            VT, Expand);
00172 
00173       // Use *MUL_LOHI where possible instead of MULH*.
00174       setOperationAction(ISD::MULHS, VT, Expand);
00175       setOperationAction(ISD::MULHU, VT, Expand);
00176       setOperationAction(ISD::SMUL_LOHI, VT, Custom);
00177       setOperationAction(ISD::UMUL_LOHI, VT, Custom);
00178 
00179       // Only z196 and above have native support for conversions to unsigned.
00180       if (!Subtarget.hasFPExtension())
00181         setOperationAction(ISD::FP_TO_UINT, VT, Expand);
00182     }
00183   }
00184 
00185   // Type legalization will convert 8- and 16-bit atomic operations into
00186   // forms that operate on i32s (but still keeping the original memory VT).
00187   // Lower them into full i32 operations.
00188   setOperationAction(ISD::ATOMIC_SWAP,      MVT::i32, Custom);
00189   setOperationAction(ISD::ATOMIC_LOAD_ADD,  MVT::i32, Custom);
00190   setOperationAction(ISD::ATOMIC_LOAD_SUB,  MVT::i32, Custom);
00191   setOperationAction(ISD::ATOMIC_LOAD_AND,  MVT::i32, Custom);
00192   setOperationAction(ISD::ATOMIC_LOAD_OR,   MVT::i32, Custom);
00193   setOperationAction(ISD::ATOMIC_LOAD_XOR,  MVT::i32, Custom);
00194   setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Custom);
00195   setOperationAction(ISD::ATOMIC_LOAD_MIN,  MVT::i32, Custom);
00196   setOperationAction(ISD::ATOMIC_LOAD_MAX,  MVT::i32, Custom);
00197   setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Custom);
00198   setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Custom);
00199   setOperationAction(ISD::ATOMIC_CMP_SWAP,  MVT::i32, Custom);
00200 
00201   // z10 has instructions for signed but not unsigned FP conversion.
00202   // Handle unsigned 32-bit types as signed 64-bit types.
00203   if (!Subtarget.hasFPExtension()) {
00204     setOperationAction(ISD::UINT_TO_FP, MVT::i32, Promote);
00205     setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
00206   }
00207 
00208   // We have native support for a 64-bit CTLZ, via FLOGR.
00209   setOperationAction(ISD::CTLZ, MVT::i32, Promote);
00210   setOperationAction(ISD::CTLZ, MVT::i64, Legal);
00211 
00212   // Give LowerOperation the chance to replace 64-bit ORs with subregs.
00213   setOperationAction(ISD::OR, MVT::i64, Custom);
00214 
00215   // FIXME: Can we support these natively?
00216   setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
00217   setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
00218   setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
00219 
00220   // We have native instructions for i8, i16 and i32 extensions, but not i1.
00221   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
00222   for (MVT VT : MVT::integer_valuetypes()) {
00223     setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
00224     setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
00225     setLoadExtAction(ISD::EXTLOAD,  VT, MVT::i1, Promote);
00226   }
00227 
00228   // Handle the various types of symbolic address.
00229   setOperationAction(ISD::ConstantPool,     PtrVT, Custom);
00230   setOperationAction(ISD::GlobalAddress,    PtrVT, Custom);
00231   setOperationAction(ISD::GlobalTLSAddress, PtrVT, Custom);
00232   setOperationAction(ISD::BlockAddress,     PtrVT, Custom);
00233   setOperationAction(ISD::JumpTable,        PtrVT, Custom);
00234 
00235   // We need to handle dynamic allocations specially because of the
00236   // 160-byte area at the bottom of the stack.
00237   setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom);
00238 
00239   // Use custom expanders so that we can force the function to use
00240   // a frame pointer.
00241   setOperationAction(ISD::STACKSAVE,    MVT::Other, Custom);
00242   setOperationAction(ISD::STACKRESTORE, MVT::Other, Custom);
00243 
00244   // Handle prefetches with PFD or PFDRL.
00245   setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
00246 
00247   // Handle floating-point types.
00248   for (unsigned I = MVT::FIRST_FP_VALUETYPE;
00249        I <= MVT::LAST_FP_VALUETYPE;
00250        ++I) {
00251     MVT VT = MVT::SimpleValueType(I);
00252     if (isTypeLegal(VT)) {
00253       // We can use FI for FRINT.
00254       setOperationAction(ISD::FRINT, VT, Legal);
00255 
00256       // We can use the extended form of FI for other rounding operations.
00257       if (Subtarget.hasFPExtension()) {
00258         setOperationAction(ISD::FNEARBYINT, VT, Legal);
00259         setOperationAction(ISD::FFLOOR, VT, Legal);
00260         setOperationAction(ISD::FCEIL, VT, Legal);
00261         setOperationAction(ISD::FTRUNC, VT, Legal);
00262         setOperationAction(ISD::FROUND, VT, Legal);
00263       }
00264 
00265       // No special instructions for these.
00266       setOperationAction(ISD::FSIN, VT, Expand);
00267       setOperationAction(ISD::FCOS, VT, Expand);
00268       setOperationAction(ISD::FREM, VT, Expand);
00269     }
00270   }
00271 
00272   // We have fused multiply-addition for f32 and f64 but not f128.
00273   setOperationAction(ISD::FMA, MVT::f32,  Legal);
00274   setOperationAction(ISD::FMA, MVT::f64,  Legal);
00275   setOperationAction(ISD::FMA, MVT::f128, Expand);
00276 
00277   // Needed so that we don't try to implement f128 constant loads using
00278   // a load-and-extend of a f80 constant (in cases where the constant
00279   // would fit in an f80).
00280   for (MVT VT : MVT::fp_valuetypes())
00281     setLoadExtAction(ISD::EXTLOAD, VT, MVT::f80, Expand);
00282 
00283   // Floating-point truncation and stores need to be done separately.
00284   setTruncStoreAction(MVT::f64,  MVT::f32, Expand);
00285   setTruncStoreAction(MVT::f128, MVT::f32, Expand);
00286   setTruncStoreAction(MVT::f128, MVT::f64, Expand);
00287 
00288   // We have 64-bit FPR<->GPR moves, but need special handling for
00289   // 32-bit forms.
00290   setOperationAction(ISD::BITCAST, MVT::i32, Custom);
00291   setOperationAction(ISD::BITCAST, MVT::f32, Custom);
00292 
00293   // VASTART and VACOPY need to deal with the SystemZ-specific varargs
00294   // structure, but VAEND is a no-op.
00295   setOperationAction(ISD::VASTART, MVT::Other, Custom);
00296   setOperationAction(ISD::VACOPY,  MVT::Other, Custom);
00297   setOperationAction(ISD::VAEND,   MVT::Other, Expand);
00298 
00299   // Codes for which we want to perform some z-specific combinations.
00300   setTargetDAGCombine(ISD::SIGN_EXTEND);
00301 
00302   // We want to use MVC in preference to even a single load/store pair.
00303   MaxStoresPerMemcpy = 0;
00304   MaxStoresPerMemcpyOptSize = 0;
00305 
00306   // The main memset sequence is a byte store followed by an MVC.
00307   // Two STC or MV..I stores win over that, but the kind of fused stores
00308   // generated by target-independent code don't when the byte value is
00309   // variable.  E.g.  "STC <reg>;MHI <reg>,257;STH <reg>" is not better
00310   // than "STC;MVC".  Handle the choice in target-specific code instead.
00311   MaxStoresPerMemset = 0;
00312   MaxStoresPerMemsetOptSize = 0;
00313 }
00314 
00315 EVT SystemZTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
00316   if (!VT.isVector())
00317     return MVT::i32;
00318   return VT.changeVectorElementTypeToInteger();
00319 }
00320 
00321 bool SystemZTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
00322   VT = VT.getScalarType();
00323 
00324   if (!VT.isSimple())
00325     return false;
00326 
00327   switch (VT.getSimpleVT().SimpleTy) {
00328   case MVT::f32:
00329   case MVT::f64:
00330     return true;
00331   case MVT::f128:
00332     return false;
00333   default:
00334     break;
00335   }
00336 
00337   return false;
00338 }
00339 
00340 bool SystemZTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
00341   // We can load zero using LZ?R and negative zero using LZ?R;LC?BR.
00342   return Imm.isZero() || Imm.isNegZero();
00343 }
00344 
00345 bool SystemZTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
00346                                                            unsigned,
00347                                                            unsigned,
00348                                                            bool *Fast) const {
00349   // Unaligned accesses should never be slower than the expanded version.
00350   // We check specifically for aligned accesses in the few cases where
00351   // they are required.
00352   if (Fast)
00353     *Fast = true;
00354   return true;
00355 }
00356   
00357 bool SystemZTargetLowering::isLegalAddressingMode(const AddrMode &AM,
00358                                                   Type *Ty) const {
00359   // Punt on globals for now, although they can be used in limited
00360   // RELATIVE LONG cases.
00361   if (AM.BaseGV)
00362     return false;
00363 
00364   // Require a 20-bit signed offset.
00365   if (!isInt<20>(AM.BaseOffs))
00366     return false;
00367 
00368   // Indexing is OK but no scale factor can be applied.
00369   return AM.Scale == 0 || AM.Scale == 1;
00370 }
00371 
00372 bool SystemZTargetLowering::isTruncateFree(Type *FromType, Type *ToType) const {
00373   if (!FromType->isIntegerTy() || !ToType->isIntegerTy())
00374     return false;
00375   unsigned FromBits = FromType->getPrimitiveSizeInBits();
00376   unsigned ToBits = ToType->getPrimitiveSizeInBits();
00377   return FromBits > ToBits;
00378 }
00379 
00380 bool SystemZTargetLowering::isTruncateFree(EVT FromVT, EVT ToVT) const {
00381   if (!FromVT.isInteger() || !ToVT.isInteger())
00382     return false;
00383   unsigned FromBits = FromVT.getSizeInBits();
00384   unsigned ToBits = ToVT.getSizeInBits();
00385   return FromBits > ToBits;
00386 }
00387 
00388 //===----------------------------------------------------------------------===//
00389 // Inline asm support
00390 //===----------------------------------------------------------------------===//
00391 
00392 TargetLowering::ConstraintType
00393 SystemZTargetLowering::getConstraintType(const std::string &Constraint) const {
00394   if (Constraint.size() == 1) {
00395     switch (Constraint[0]) {
00396     case 'a': // Address register
00397     case 'd': // Data register (equivalent to 'r')
00398     case 'f': // Floating-point register
00399     case 'h': // High-part register
00400     case 'r': // General-purpose register
00401       return C_RegisterClass;
00402 
00403     case 'Q': // Memory with base and unsigned 12-bit displacement
00404     case 'R': // Likewise, plus an index
00405     case 'S': // Memory with base and signed 20-bit displacement
00406     case 'T': // Likewise, plus an index
00407     case 'm': // Equivalent to 'T'.
00408       return C_Memory;
00409 
00410     case 'I': // Unsigned 8-bit constant
00411     case 'J': // Unsigned 12-bit constant
00412     case 'K': // Signed 16-bit constant
00413     case 'L': // Signed 20-bit displacement (on all targets we support)
00414     case 'M': // 0x7fffffff
00415       return C_Other;
00416 
00417     default:
00418       break;
00419     }
00420   }
00421   return TargetLowering::getConstraintType(Constraint);
00422 }
00423 
00424 TargetLowering::ConstraintWeight SystemZTargetLowering::
00425 getSingleConstraintMatchWeight(AsmOperandInfo &info,
00426                                const char *constraint) const {
00427   ConstraintWeight weight = CW_Invalid;
00428   Value *CallOperandVal = info.CallOperandVal;
00429   // If we don't have a value, we can't do a match,
00430   // but allow it at the lowest weight.
00431   if (!CallOperandVal)
00432     return CW_Default;
00433   Type *type = CallOperandVal->getType();
00434   // Look at the constraint type.
00435   switch (*constraint) {
00436   default:
00437     weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
00438     break;
00439 
00440   case 'a': // Address register
00441   case 'd': // Data register (equivalent to 'r')
00442   case 'h': // High-part register
00443   case 'r': // General-purpose register
00444     if (CallOperandVal->getType()->isIntegerTy())
00445       weight = CW_Register;
00446     break;
00447 
00448   case 'f': // Floating-point register
00449     if (type->isFloatingPointTy())
00450       weight = CW_Register;
00451     break;
00452 
00453   case 'I': // Unsigned 8-bit constant
00454     if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
00455       if (isUInt<8>(C->getZExtValue()))
00456         weight = CW_Constant;
00457     break;
00458 
00459   case 'J': // Unsigned 12-bit constant
00460     if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
00461       if (isUInt<12>(C->getZExtValue()))
00462         weight = CW_Constant;
00463     break;
00464 
00465   case 'K': // Signed 16-bit constant
00466     if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
00467       if (isInt<16>(C->getSExtValue()))
00468         weight = CW_Constant;
00469     break;
00470 
00471   case 'L': // Signed 20-bit displacement (on all targets we support)
00472     if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
00473       if (isInt<20>(C->getSExtValue()))
00474         weight = CW_Constant;
00475     break;
00476 
00477   case 'M': // 0x7fffffff
00478     if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
00479       if (C->getZExtValue() == 0x7fffffff)
00480         weight = CW_Constant;
00481     break;
00482   }
00483   return weight;
00484 }
00485 
00486 // Parse a "{tNNN}" register constraint for which the register type "t"
00487 // has already been verified.  MC is the class associated with "t" and
00488 // Map maps 0-based register numbers to LLVM register numbers.
00489 static std::pair<unsigned, const TargetRegisterClass *>
00490 parseRegisterNumber(const std::string &Constraint,
00491                     const TargetRegisterClass *RC, const unsigned *Map) {
00492   assert(*(Constraint.end()-1) == '}' && "Missing '}'");
00493   if (isdigit(Constraint[2])) {
00494     std::string Suffix(Constraint.data() + 2, Constraint.size() - 2);
00495     unsigned Index = atoi(Suffix.c_str());
00496     if (Index < 16 && Map[Index])
00497       return std::make_pair(Map[Index], RC);
00498   }
00499   return std::make_pair(0U, nullptr);
00500 }
00501 
00502 std::pair<unsigned, const TargetRegisterClass *>
00503 SystemZTargetLowering::getRegForInlineAsmConstraint(
00504     const TargetRegisterInfo *TRI, const std::string &Constraint,
00505     MVT VT) const {
00506   if (Constraint.size() == 1) {
00507     // GCC Constraint Letters
00508     switch (Constraint[0]) {
00509     default: break;
00510     case 'd': // Data register (equivalent to 'r')
00511     case 'r': // General-purpose register
00512       if (VT == MVT::i64)
00513         return std::make_pair(0U, &SystemZ::GR64BitRegClass);
00514       else if (VT == MVT::i128)
00515         return std::make_pair(0U, &SystemZ::GR128BitRegClass);
00516       return std::make_pair(0U, &SystemZ::GR32BitRegClass);
00517 
00518     case 'a': // Address register
00519       if (VT == MVT::i64)
00520         return std::make_pair(0U, &SystemZ::ADDR64BitRegClass);
00521       else if (VT == MVT::i128)
00522         return std::make_pair(0U, &SystemZ::ADDR128BitRegClass);
00523       return std::make_pair(0U, &SystemZ::ADDR32BitRegClass);
00524 
00525     case 'h': // High-part register (an LLVM extension)
00526       return std::make_pair(0U, &SystemZ::GRH32BitRegClass);
00527 
00528     case 'f': // Floating-point register
00529       if (VT == MVT::f64)
00530         return std::make_pair(0U, &SystemZ::FP64BitRegClass);
00531       else if (VT == MVT::f128)
00532         return std::make_pair(0U, &SystemZ::FP128BitRegClass);
00533       return std::make_pair(0U, &SystemZ::FP32BitRegClass);
00534     }
00535   }
00536   if (Constraint[0] == '{') {
00537     // We need to override the default register parsing for GPRs and FPRs
00538     // because the interpretation depends on VT.  The internal names of
00539     // the registers are also different from the external names
00540     // (F0D and F0S instead of F0, etc.).
00541     if (Constraint[1] == 'r') {
00542       if (VT == MVT::i32)
00543         return parseRegisterNumber(Constraint, &SystemZ::GR32BitRegClass,
00544                                    SystemZMC::GR32Regs);
00545       if (VT == MVT::i128)
00546         return parseRegisterNumber(Constraint, &SystemZ::GR128BitRegClass,
00547                                    SystemZMC::GR128Regs);
00548       return parseRegisterNumber(Constraint, &SystemZ::GR64BitRegClass,
00549                                  SystemZMC::GR64Regs);
00550     }
00551     if (Constraint[1] == 'f') {
00552       if (VT == MVT::f32)
00553         return parseRegisterNumber(Constraint, &SystemZ::FP32BitRegClass,
00554                                    SystemZMC::FP32Regs);
00555       if (VT == MVT::f128)
00556         return parseRegisterNumber(Constraint, &SystemZ::FP128BitRegClass,
00557                                    SystemZMC::FP128Regs);
00558       return parseRegisterNumber(Constraint, &SystemZ::FP64BitRegClass,
00559                                  SystemZMC::FP64Regs);
00560     }
00561   }
00562   return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
00563 }
00564 
00565 void SystemZTargetLowering::
00566 LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
00567                              std::vector<SDValue> &Ops,
00568                              SelectionDAG &DAG) const {
00569   // Only support length 1 constraints for now.
00570   if (Constraint.length() == 1) {
00571     switch (Constraint[0]) {
00572     case 'I': // Unsigned 8-bit constant
00573       if (auto *C = dyn_cast<ConstantSDNode>(Op))
00574         if (isUInt<8>(C->getZExtValue()))
00575           Ops.push_back(DAG.getTargetConstant(C->getZExtValue(),
00576                                               Op.getValueType()));
00577       return;
00578 
00579     case 'J': // Unsigned 12-bit constant
00580       if (auto *C = dyn_cast<ConstantSDNode>(Op))
00581         if (isUInt<12>(C->getZExtValue()))
00582           Ops.push_back(DAG.getTargetConstant(C->getZExtValue(),
00583                                               Op.getValueType()));
00584       return;
00585 
00586     case 'K': // Signed 16-bit constant
00587       if (auto *C = dyn_cast<ConstantSDNode>(Op))
00588         if (isInt<16>(C->getSExtValue()))
00589           Ops.push_back(DAG.getTargetConstant(C->getSExtValue(),
00590                                               Op.getValueType()));
00591       return;
00592 
00593     case 'L': // Signed 20-bit displacement (on all targets we support)
00594       if (auto *C = dyn_cast<ConstantSDNode>(Op))
00595         if (isInt<20>(C->getSExtValue()))
00596           Ops.push_back(DAG.getTargetConstant(C->getSExtValue(),
00597                                               Op.getValueType()));
00598       return;
00599 
00600     case 'M': // 0x7fffffff
00601       if (auto *C = dyn_cast<ConstantSDNode>(Op))
00602         if (C->getZExtValue() == 0x7fffffff)
00603           Ops.push_back(DAG.getTargetConstant(C->getZExtValue(),
00604                                               Op.getValueType()));
00605       return;
00606     }
00607   }
00608   TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
00609 }
00610 
00611 //===----------------------------------------------------------------------===//
00612 // Calling conventions
00613 //===----------------------------------------------------------------------===//
00614 
00615 #include "SystemZGenCallingConv.inc"
00616 
00617 bool SystemZTargetLowering::allowTruncateForTailCall(Type *FromType,
00618                                                      Type *ToType) const {
00619   return isTruncateFree(FromType, ToType);
00620 }
00621 
00622 bool SystemZTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
00623   if (!CI->isTailCall())
00624     return false;
00625   return true;
00626 }
00627 
00628 // Value is a value that has been passed to us in the location described by VA
00629 // (and so has type VA.getLocVT()).  Convert Value to VA.getValVT(), chaining
00630 // any loads onto Chain.
00631 static SDValue convertLocVTToValVT(SelectionDAG &DAG, SDLoc DL,
00632                                    CCValAssign &VA, SDValue Chain,
00633                                    SDValue Value) {
00634   // If the argument has been promoted from a smaller type, insert an
00635   // assertion to capture this.
00636   if (VA.getLocInfo() == CCValAssign::SExt)
00637     Value = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Value,
00638                         DAG.getValueType(VA.getValVT()));
00639   else if (VA.getLocInfo() == CCValAssign::ZExt)
00640     Value = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Value,
00641                         DAG.getValueType(VA.getValVT()));
00642 
00643   if (VA.isExtInLoc())
00644     Value = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Value);
00645   else if (VA.getLocInfo() == CCValAssign::Indirect)
00646     Value = DAG.getLoad(VA.getValVT(), DL, Chain, Value,
00647                         MachinePointerInfo(), false, false, false, 0);
00648   else
00649     assert(VA.getLocInfo() == CCValAssign::Full && "Unsupported getLocInfo");
00650   return Value;
00651 }
00652 
00653 // Value is a value of type VA.getValVT() that we need to copy into
00654 // the location described by VA.  Return a copy of Value converted to
00655 // VA.getValVT().  The caller is responsible for handling indirect values.
00656 static SDValue convertValVTToLocVT(SelectionDAG &DAG, SDLoc DL,
00657                                    CCValAssign &VA, SDValue Value) {
00658   switch (VA.getLocInfo()) {
00659   case CCValAssign::SExt:
00660     return DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Value);
00661   case CCValAssign::ZExt:
00662     return DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Value);
00663   case CCValAssign::AExt:
00664     return DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Value);
00665   case CCValAssign::Full:
00666     return Value;
00667   default:
00668     llvm_unreachable("Unhandled getLocInfo()");
00669   }
00670 }
00671 
00672 SDValue SystemZTargetLowering::
00673 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
00674                      const SmallVectorImpl<ISD::InputArg> &Ins,
00675                      SDLoc DL, SelectionDAG &DAG,
00676                      SmallVectorImpl<SDValue> &InVals) const {
00677   MachineFunction &MF = DAG.getMachineFunction();
00678   MachineFrameInfo *MFI = MF.getFrameInfo();
00679   MachineRegisterInfo &MRI = MF.getRegInfo();
00680   SystemZMachineFunctionInfo *FuncInfo =
00681       MF.getInfo<SystemZMachineFunctionInfo>();
00682   auto *TFL =
00683       static_cast<const SystemZFrameLowering *>(Subtarget.getFrameLowering());
00684 
00685   // Assign locations to all of the incoming arguments.
00686   SmallVector<CCValAssign, 16> ArgLocs;
00687   CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
00688   CCInfo.AnalyzeFormalArguments(Ins, CC_SystemZ);
00689 
00690   unsigned NumFixedGPRs = 0;
00691   unsigned NumFixedFPRs = 0;
00692   for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
00693     SDValue ArgValue;
00694     CCValAssign &VA = ArgLocs[I];
00695     EVT LocVT = VA.getLocVT();
00696     if (VA.isRegLoc()) {
00697       // Arguments passed in registers
00698       const TargetRegisterClass *RC;
00699       switch (LocVT.getSimpleVT().SimpleTy) {
00700       default:
00701         // Integers smaller than i64 should be promoted to i64.
00702         llvm_unreachable("Unexpected argument type");
00703       case MVT::i32:
00704         NumFixedGPRs += 1;
00705         RC = &SystemZ::GR32BitRegClass;
00706         break;
00707       case MVT::i64:
00708         NumFixedGPRs += 1;
00709         RC = &SystemZ::GR64BitRegClass;
00710         break;
00711       case MVT::f32:
00712         NumFixedFPRs += 1;
00713         RC = &SystemZ::FP32BitRegClass;
00714         break;
00715       case MVT::f64:
00716         NumFixedFPRs += 1;
00717         RC = &SystemZ::FP64BitRegClass;
00718         break;
00719       }
00720 
00721       unsigned VReg = MRI.createVirtualRegister(RC);
00722       MRI.addLiveIn(VA.getLocReg(), VReg);
00723       ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, LocVT);
00724     } else {
00725       assert(VA.isMemLoc() && "Argument not register or memory");
00726 
00727       // Create the frame index object for this incoming parameter.
00728       int FI = MFI->CreateFixedObject(LocVT.getSizeInBits() / 8,
00729                                       VA.getLocMemOffset(), true);
00730 
00731       // Create the SelectionDAG nodes corresponding to a load
00732       // from this parameter.  Unpromoted ints and floats are
00733       // passed as right-justified 8-byte values.
00734       EVT PtrVT = getPointerTy();
00735       SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
00736       if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)
00737         FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4));
00738       ArgValue = DAG.getLoad(LocVT, DL, Chain, FIN,
00739                              MachinePointerInfo::getFixedStack(FI),
00740                              false, false, false, 0);
00741     }
00742 
00743     // Convert the value of the argument register into the value that's
00744     // being passed.
00745     InVals.push_back(convertLocVTToValVT(DAG, DL, VA, Chain, ArgValue));
00746   }
00747 
00748   if (IsVarArg) {
00749     // Save the number of non-varargs registers for later use by va_start, etc.
00750     FuncInfo->setVarArgsFirstGPR(NumFixedGPRs);
00751     FuncInfo->setVarArgsFirstFPR(NumFixedFPRs);
00752 
00753     // Likewise the address (in the form of a frame index) of where the
00754     // first stack vararg would be.  The 1-byte size here is arbitrary.
00755     int64_t StackSize = CCInfo.getNextStackOffset();
00756     FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize, true));
00757 
00758     // ...and a similar frame index for the caller-allocated save area
00759     // that will be used to store the incoming registers.
00760     int64_t RegSaveOffset = TFL->getOffsetOfLocalArea();
00761     unsigned RegSaveIndex = MFI->CreateFixedObject(1, RegSaveOffset, true);
00762     FuncInfo->setRegSaveFrameIndex(RegSaveIndex);
00763 
00764     // Store the FPR varargs in the reserved frame slots.  (We store the
00765     // GPRs as part of the prologue.)
00766     if (NumFixedFPRs < SystemZ::NumArgFPRs) {
00767       SDValue MemOps[SystemZ::NumArgFPRs];
00768       for (unsigned I = NumFixedFPRs; I < SystemZ::NumArgFPRs; ++I) {
00769         unsigned Offset = TFL->getRegSpillOffset(SystemZ::ArgFPRs[I]);
00770         int FI = MFI->CreateFixedObject(8, RegSaveOffset + Offset, true);
00771         SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
00772         unsigned VReg = MF.addLiveIn(SystemZ::ArgFPRs[I],
00773                                      &SystemZ::FP64BitRegClass);
00774         SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f64);
00775         MemOps[I] = DAG.getStore(ArgValue.getValue(1), DL, ArgValue, FIN,
00776                                  MachinePointerInfo::getFixedStack(FI),
00777                                  false, false, 0);
00778 
00779       }
00780       // Join the stores, which are independent of one another.
00781       Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
00782                           makeArrayRef(&MemOps[NumFixedFPRs],
00783                                        SystemZ::NumArgFPRs-NumFixedFPRs));
00784     }
00785   }
00786 
00787   return Chain;
00788 }
00789 
00790 static bool canUseSiblingCall(const CCState &ArgCCInfo,
00791                               SmallVectorImpl<CCValAssign> &ArgLocs) {
00792   // Punt if there are any indirect or stack arguments, or if the call
00793   // needs the call-saved argument register R6.
00794   for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
00795     CCValAssign &VA = ArgLocs[I];
00796     if (VA.getLocInfo() == CCValAssign::Indirect)
00797       return false;
00798     if (!VA.isRegLoc())
00799       return false;
00800     unsigned Reg = VA.getLocReg();
00801     if (Reg == SystemZ::R6H || Reg == SystemZ::R6L || Reg == SystemZ::R6D)
00802       return false;
00803   }
00804   return true;
00805 }
00806 
00807 SDValue
00808 SystemZTargetLowering::LowerCall(CallLoweringInfo &CLI,
00809                                  SmallVectorImpl<SDValue> &InVals) const {
00810   SelectionDAG &DAG = CLI.DAG;
00811   SDLoc &DL = CLI.DL;
00812   SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
00813   SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
00814   SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
00815   SDValue Chain = CLI.Chain;
00816   SDValue Callee = CLI.Callee;
00817   bool &IsTailCall = CLI.IsTailCall;
00818   CallingConv::ID CallConv = CLI.CallConv;
00819   bool IsVarArg = CLI.IsVarArg;
00820   MachineFunction &MF = DAG.getMachineFunction();
00821   EVT PtrVT = getPointerTy();
00822 
00823   // Analyze the operands of the call, assigning locations to each operand.
00824   SmallVector<CCValAssign, 16> ArgLocs;
00825   CCState ArgCCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
00826   ArgCCInfo.AnalyzeCallOperands(Outs, CC_SystemZ);
00827 
00828   // We don't support GuaranteedTailCallOpt, only automatically-detected
00829   // sibling calls.
00830   if (IsTailCall && !canUseSiblingCall(ArgCCInfo, ArgLocs))
00831     IsTailCall = false;
00832 
00833   // Get a count of how many bytes are to be pushed on the stack.
00834   unsigned NumBytes = ArgCCInfo.getNextStackOffset();
00835 
00836   // Mark the start of the call.
00837   if (!IsTailCall)
00838     Chain = DAG.getCALLSEQ_START(Chain, DAG.getConstant(NumBytes, PtrVT, true),
00839                                  DL);
00840 
00841   // Copy argument values to their designated locations.
00842   SmallVector<std::pair<unsigned, SDValue>, 9> RegsToPass;
00843   SmallVector<SDValue, 8> MemOpChains;
00844   SDValue StackPtr;
00845   for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
00846     CCValAssign &VA = ArgLocs[I];
00847     SDValue ArgValue = OutVals[I];
00848 
00849     if (VA.getLocInfo() == CCValAssign::Indirect) {
00850       // Store the argument in a stack slot and pass its address.
00851       SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
00852       int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
00853       MemOpChains.push_back(DAG.getStore(Chain, DL, ArgValue, SpillSlot,
00854                                          MachinePointerInfo::getFixedStack(FI),
00855                                          false, false, 0));
00856       ArgValue = SpillSlot;
00857     } else
00858       ArgValue = convertValVTToLocVT(DAG, DL, VA, ArgValue);
00859 
00860     if (VA.isRegLoc())
00861       // Queue up the argument copies and emit them at the end.
00862       RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue));
00863     else {
00864       assert(VA.isMemLoc() && "Argument not register or memory");
00865 
00866       // Work out the address of the stack slot.  Unpromoted ints and
00867       // floats are passed as right-justified 8-byte values.
00868       if (!StackPtr.getNode())
00869         StackPtr = DAG.getCopyFromReg(Chain, DL, SystemZ::R15D, PtrVT);
00870       unsigned Offset = SystemZMC::CallFrameSize + VA.getLocMemOffset();
00871       if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)
00872         Offset += 4;
00873       SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr,
00874                                     DAG.getIntPtrConstant(Offset));
00875 
00876       // Emit the store.
00877       MemOpChains.push_back(DAG.getStore(Chain, DL, ArgValue, Address,
00878                                          MachinePointerInfo(),
00879                                          false, false, 0));
00880     }
00881   }
00882 
00883   // Join the stores, which are independent of one another.
00884   if (!MemOpChains.empty())
00885     Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
00886 
00887   // Accept direct calls by converting symbolic call addresses to the
00888   // associated Target* opcodes.  Force %r1 to be used for indirect
00889   // tail calls.
00890   SDValue Glue;
00891   if (auto *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
00892     Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, PtrVT);
00893     Callee = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Callee);
00894   } else if (auto *E = dyn_cast<ExternalSymbolSDNode>(Callee)) {
00895     Callee = DAG.getTargetExternalSymbol(E->getSymbol(), PtrVT);
00896     Callee = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Callee);
00897   } else if (IsTailCall) {
00898     Chain = DAG.getCopyToReg(Chain, DL, SystemZ::R1D, Callee, Glue);
00899     Glue = Chain.getValue(1);
00900     Callee = DAG.getRegister(SystemZ::R1D, Callee.getValueType());
00901   }
00902 
00903   // Build a sequence of copy-to-reg nodes, chained and glued together.
00904   for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I) {
00905     Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[I].first,
00906                              RegsToPass[I].second, Glue);
00907     Glue = Chain.getValue(1);
00908   }
00909 
00910   // The first call operand is the chain and the second is the target address.
00911   SmallVector<SDValue, 8> Ops;
00912   Ops.push_back(Chain);
00913   Ops.push_back(Callee);
00914 
00915   // Add argument registers to the end of the list so that they are
00916   // known live into the call.
00917   for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I)
00918     Ops.push_back(DAG.getRegister(RegsToPass[I].first,
00919                                   RegsToPass[I].second.getValueType()));
00920 
00921   // Add a register mask operand representing the call-preserved registers.
00922   const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
00923   const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv);
00924   assert(Mask && "Missing call preserved mask for calling convention");
00925   Ops.push_back(DAG.getRegisterMask(Mask));
00926 
00927   // Glue the call to the argument copies, if any.
00928   if (Glue.getNode())
00929     Ops.push_back(Glue);
00930 
00931   // Emit the call.
00932   SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
00933   if (IsTailCall)
00934     return DAG.getNode(SystemZISD::SIBCALL, DL, NodeTys, Ops);
00935   Chain = DAG.getNode(SystemZISD::CALL, DL, NodeTys, Ops);
00936   Glue = Chain.getValue(1);
00937 
00938   // Mark the end of the call, which is glued to the call itself.
00939   Chain = DAG.getCALLSEQ_END(Chain,
00940                              DAG.getConstant(NumBytes, PtrVT, true),
00941                              DAG.getConstant(0, PtrVT, true),
00942                              Glue, DL);
00943   Glue = Chain.getValue(1);
00944 
00945   // Assign locations to each value returned by this call.
00946   SmallVector<CCValAssign, 16> RetLocs;
00947   CCState RetCCInfo(CallConv, IsVarArg, MF, RetLocs, *DAG.getContext());
00948   RetCCInfo.AnalyzeCallResult(Ins, RetCC_SystemZ);
00949 
00950   // Copy all of the result registers out of their specified physreg.
00951   for (unsigned I = 0, E = RetLocs.size(); I != E; ++I) {
00952     CCValAssign &VA = RetLocs[I];
00953 
00954     // Copy the value out, gluing the copy to the end of the call sequence.
00955     SDValue RetValue = DAG.getCopyFromReg(Chain, DL, VA.getLocReg(),
00956                                           VA.getLocVT(), Glue);
00957     Chain = RetValue.getValue(1);
00958     Glue = RetValue.getValue(2);
00959 
00960     // Convert the value of the return register into the value that's
00961     // being returned.
00962     InVals.push_back(convertLocVTToValVT(DAG, DL, VA, Chain, RetValue));
00963   }
00964 
00965   return Chain;
00966 }
00967 
00968 SDValue
00969 SystemZTargetLowering::LowerReturn(SDValue Chain,
00970                                    CallingConv::ID CallConv, bool IsVarArg,
00971                                    const SmallVectorImpl<ISD::OutputArg> &Outs,
00972                                    const SmallVectorImpl<SDValue> &OutVals,
00973                                    SDLoc DL, SelectionDAG &DAG) const {
00974   MachineFunction &MF = DAG.getMachineFunction();
00975 
00976   // Assign locations to each returned value.
00977   SmallVector<CCValAssign, 16> RetLocs;
00978   CCState RetCCInfo(CallConv, IsVarArg, MF, RetLocs, *DAG.getContext());
00979   RetCCInfo.AnalyzeReturn(Outs, RetCC_SystemZ);
00980 
00981   // Quick exit for void returns
00982   if (RetLocs.empty())
00983     return DAG.getNode(SystemZISD::RET_FLAG, DL, MVT::Other, Chain);
00984 
00985   // Copy the result values into the output registers.
00986   SDValue Glue;
00987   SmallVector<SDValue, 4> RetOps;
00988   RetOps.push_back(Chain);
00989   for (unsigned I = 0, E = RetLocs.size(); I != E; ++I) {
00990     CCValAssign &VA = RetLocs[I];
00991     SDValue RetValue = OutVals[I];
00992 
00993     // Make the return register live on exit.
00994     assert(VA.isRegLoc() && "Can only return in registers!");
00995 
00996     // Promote the value as required.
00997     RetValue = convertValVTToLocVT(DAG, DL, VA, RetValue);
00998 
00999     // Chain and glue the copies together.
01000     unsigned Reg = VA.getLocReg();
01001     Chain = DAG.getCopyToReg(Chain, DL, Reg, RetValue, Glue);
01002     Glue = Chain.getValue(1);
01003     RetOps.push_back(DAG.getRegister(Reg, VA.getLocVT()));
01004   }
01005 
01006   // Update chain and glue.
01007   RetOps[0] = Chain;
01008   if (Glue.getNode())
01009     RetOps.push_back(Glue);
01010 
01011   return DAG.getNode(SystemZISD::RET_FLAG, DL, MVT::Other, RetOps);
01012 }
01013 
01014 SDValue SystemZTargetLowering::
01015 prepareVolatileOrAtomicLoad(SDValue Chain, SDLoc DL, SelectionDAG &DAG) const {
01016   return DAG.getNode(SystemZISD::SERIALIZE, DL, MVT::Other, Chain);
01017 }
01018 
01019 // CC is a comparison that will be implemented using an integer or
01020 // floating-point comparison.  Return the condition code mask for
01021 // a branch on true.  In the integer case, CCMASK_CMP_UO is set for
01022 // unsigned comparisons and clear for signed ones.  In the floating-point
01023 // case, CCMASK_CMP_UO has its normal mask meaning (unordered).
01024 static unsigned CCMaskForCondCode(ISD::CondCode CC) {
01025 #define CONV(X) \
01026   case ISD::SET##X: return SystemZ::CCMASK_CMP_##X; \
01027   case ISD::SETO##X: return SystemZ::CCMASK_CMP_##X; \
01028   case ISD::SETU##X: return SystemZ::CCMASK_CMP_UO | SystemZ::CCMASK_CMP_##X
01029 
01030   switch (CC) {
01031   default:
01032     llvm_unreachable("Invalid integer condition!");
01033 
01034   CONV(EQ);
01035   CONV(NE);
01036   CONV(GT);
01037   CONV(GE);
01038   CONV(LT);
01039   CONV(LE);
01040 
01041   case ISD::SETO:  return SystemZ::CCMASK_CMP_O;
01042   case ISD::SETUO: return SystemZ::CCMASK_CMP_UO;
01043   }
01044 #undef CONV
01045 }
01046 
01047 // Return a sequence for getting a 1 from an IPM result when CC has a
01048 // value in CCMask and a 0 when CC has a value in CCValid & ~CCMask.
01049 // The handling of CC values outside CCValid doesn't matter.
01050 static IPMConversion getIPMConversion(unsigned CCValid, unsigned CCMask) {
01051   // Deal with cases where the result can be taken directly from a bit
01052   // of the IPM result.
01053   if (CCMask == (CCValid & (SystemZ::CCMASK_1 | SystemZ::CCMASK_3)))
01054     return IPMConversion(0, 0, SystemZ::IPM_CC);
01055   if (CCMask == (CCValid & (SystemZ::CCMASK_2 | SystemZ::CCMASK_3)))
01056     return IPMConversion(0, 0, SystemZ::IPM_CC + 1);
01057 
01058   // Deal with cases where we can add a value to force the sign bit
01059   // to contain the right value.  Putting the bit in 31 means we can
01060   // use SRL rather than RISBG(L), and also makes it easier to get a
01061   // 0/-1 value, so it has priority over the other tests below.
01062   //
01063   // These sequences rely on the fact that the upper two bits of the
01064   // IPM result are zero.
01065   uint64_t TopBit = uint64_t(1) << 31;
01066   if (CCMask == (CCValid & SystemZ::CCMASK_0))
01067     return IPMConversion(0, -(1 << SystemZ::IPM_CC), 31);
01068   if (CCMask == (CCValid & (SystemZ::CCMASK_0 | SystemZ::CCMASK_1)))
01069     return IPMConversion(0, -(2 << SystemZ::IPM_CC), 31);
01070   if (CCMask == (CCValid & (SystemZ::CCMASK_0
01071                             | SystemZ::CCMASK_1
01072                             | SystemZ::CCMASK_2)))
01073     return IPMConversion(0, -(3 << SystemZ::IPM_CC), 31);
01074   if (CCMask == (CCValid & SystemZ::CCMASK_3))
01075     return IPMConversion(0, TopBit - (3 << SystemZ::IPM_CC), 31);
01076   if (CCMask == (CCValid & (SystemZ::CCMASK_1
01077                             | SystemZ::CCMASK_2
01078                             | SystemZ::CCMASK_3)))
01079     return IPMConversion(0, TopBit - (1 << SystemZ::IPM_CC), 31);
01080 
01081   // Next try inverting the value and testing a bit.  0/1 could be
01082   // handled this way too, but we dealt with that case above.
01083   if (CCMask == (CCValid & (SystemZ::CCMASK_0 | SystemZ::CCMASK_2)))
01084     return IPMConversion(-1, 0, SystemZ::IPM_CC);
01085 
01086   // Handle cases where adding a value forces a non-sign bit to contain
01087   // the right value.
01088   if (CCMask == (CCValid & (SystemZ::CCMASK_1 | SystemZ::CCMASK_2)))
01089     return IPMConversion(0, 1 << SystemZ::IPM_CC, SystemZ::IPM_CC + 1);
01090   if (CCMask == (CCValid & (SystemZ::CCMASK_0 | SystemZ::CCMASK_3)))
01091     return IPMConversion(0, -(1 << SystemZ::IPM_CC), SystemZ::IPM_CC + 1);
01092 
01093   // The remaining cases are 1, 2, 0/1/3 and 0/2/3.  All these are
01094   // can be done by inverting the low CC bit and applying one of the
01095   // sign-based extractions above.
01096   if (CCMask == (CCValid & SystemZ::CCMASK_1))
01097     return IPMConversion(1 << SystemZ::IPM_CC, -(1 << SystemZ::IPM_CC), 31);
01098   if (CCMask == (CCValid & SystemZ::CCMASK_2))
01099     return IPMConversion(1 << SystemZ::IPM_CC,
01100                          TopBit - (3 << SystemZ::IPM_CC), 31);
01101   if (CCMask == (CCValid & (SystemZ::CCMASK_0
01102                             | SystemZ::CCMASK_1
01103                             | SystemZ::CCMASK_3)))
01104     return IPMConversion(1 << SystemZ::IPM_CC, -(3 << SystemZ::IPM_CC), 31);
01105   if (CCMask == (CCValid & (SystemZ::CCMASK_0
01106                             | SystemZ::CCMASK_2
01107                             | SystemZ::CCMASK_3)))
01108     return IPMConversion(1 << SystemZ::IPM_CC,
01109                          TopBit - (1 << SystemZ::IPM_CC), 31);
01110 
01111   llvm_unreachable("Unexpected CC combination");
01112 }
01113 
01114 // If C can be converted to a comparison against zero, adjust the operands
01115 // as necessary.
01116 static void adjustZeroCmp(SelectionDAG &DAG, Comparison &C) {
01117   if (C.ICmpType == SystemZICMP::UnsignedOnly)
01118     return;
01119 
01120   auto *ConstOp1 = dyn_cast<ConstantSDNode>(C.Op1.getNode());
01121   if (!ConstOp1)
01122     return;
01123 
01124   int64_t Value = ConstOp1->getSExtValue();
01125   if ((Value == -1 && C.CCMask == SystemZ::CCMASK_CMP_GT) ||
01126       (Value == -1 && C.CCMask == SystemZ::CCMASK_CMP_LE) ||
01127       (Value == 1 && C.CCMask == SystemZ::CCMASK_CMP_LT) ||
01128       (Value == 1 && C.CCMask == SystemZ::CCMASK_CMP_GE)) {
01129     C.CCMask ^= SystemZ::CCMASK_CMP_EQ;
01130     C.Op1 = DAG.getConstant(0, C.Op1.getValueType());
01131   }
01132 }
01133 
01134 // If a comparison described by C is suitable for CLI(Y), CHHSI or CLHHSI,
01135 // adjust the operands as necessary.
01136 static void adjustSubwordCmp(SelectionDAG &DAG, Comparison &C) {
01137   // For us to make any changes, it must a comparison between a single-use
01138   // load and a constant.
01139   if (!C.Op0.hasOneUse() ||
01140       C.Op0.getOpcode() != ISD::LOAD ||
01141       C.Op1.getOpcode() != ISD::Constant)
01142     return;
01143 
01144   // We must have an 8- or 16-bit load.
01145   auto *Load = cast<LoadSDNode>(C.Op0);
01146   unsigned NumBits = Load->getMemoryVT().getStoreSizeInBits();
01147   if (NumBits != 8 && NumBits != 16)
01148     return;
01149 
01150   // The load must be an extending one and the constant must be within the
01151   // range of the unextended value.
01152   auto *ConstOp1 = cast<ConstantSDNode>(C.Op1);
01153   uint64_t Value = ConstOp1->getZExtValue();
01154   uint64_t Mask = (1 << NumBits) - 1;
01155   if (Load->getExtensionType() == ISD::SEXTLOAD) {
01156     // Make sure that ConstOp1 is in range of C.Op0.
01157     int64_t SignedValue = ConstOp1->getSExtValue();
01158     if (uint64_t(SignedValue) + (uint64_t(1) << (NumBits - 1)) > Mask)
01159       return;
01160     if (C.ICmpType != SystemZICMP::SignedOnly) {
01161       // Unsigned comparison between two sign-extended values is equivalent
01162       // to unsigned comparison between two zero-extended values.
01163       Value &= Mask;
01164     } else if (NumBits == 8) {
01165       // Try to treat the comparison as unsigned, so that we can use CLI.
01166       // Adjust CCMask and Value as necessary.
01167       if (Value == 0 && C.CCMask == SystemZ::CCMASK_CMP_LT)
01168         // Test whether the high bit of the byte is set.
01169         Value = 127, C.CCMask = SystemZ::CCMASK_CMP_GT;
01170       else if (Value == 0 && C.CCMask == SystemZ::CCMASK_CMP_GE)
01171         // Test whether the high bit of the byte is clear.
01172         Value = 128, C.CCMask = SystemZ::CCMASK_CMP_LT;
01173       else
01174         // No instruction exists for this combination.
01175         return;
01176       C.ICmpType = SystemZICMP::UnsignedOnly;
01177     }
01178   } else if (Load->getExtensionType() == ISD::ZEXTLOAD) {
01179     if (Value > Mask)
01180       return;
01181     assert(C.ICmpType == SystemZICMP::Any &&
01182            "Signedness shouldn't matter here.");
01183   } else
01184     return;
01185 
01186   // Make sure that the first operand is an i32 of the right extension type.
01187   ISD::LoadExtType ExtType = (C.ICmpType == SystemZICMP::SignedOnly ?
01188                               ISD::SEXTLOAD :
01189                               ISD::ZEXTLOAD);
01190   if (C.Op0.getValueType() != MVT::i32 ||
01191       Load->getExtensionType() != ExtType)
01192     C.Op0 = DAG.getExtLoad(ExtType, SDLoc(Load), MVT::i32,
01193                            Load->getChain(), Load->getBasePtr(),
01194                            Load->getPointerInfo(), Load->getMemoryVT(),
01195                            Load->isVolatile(), Load->isNonTemporal(),
01196                            Load->isInvariant(), Load->getAlignment());
01197 
01198   // Make sure that the second operand is an i32 with the right value.
01199   if (C.Op1.getValueType() != MVT::i32 ||
01200       Value != ConstOp1->getZExtValue())
01201     C.Op1 = DAG.getConstant(Value, MVT::i32);
01202 }
01203 
01204 // Return true if Op is either an unextended load, or a load suitable
01205 // for integer register-memory comparisons of type ICmpType.
01206 static bool isNaturalMemoryOperand(SDValue Op, unsigned ICmpType) {
01207   auto *Load = dyn_cast<LoadSDNode>(Op.getNode());
01208   if (Load) {
01209     // There are no instructions to compare a register with a memory byte.
01210     if (Load->getMemoryVT() == MVT::i8)
01211       return false;
01212     // Otherwise decide on extension type.
01213     switch (Load->getExtensionType()) {
01214     case ISD::NON_EXTLOAD:
01215       return true;
01216     case ISD::SEXTLOAD:
01217       return ICmpType != SystemZICMP::UnsignedOnly;
01218     case ISD::ZEXTLOAD:
01219       return ICmpType != SystemZICMP::SignedOnly;
01220     default:
01221       break;
01222     }
01223   }
01224   return false;
01225 }
01226 
01227 // Return true if it is better to swap the operands of C.
01228 static bool shouldSwapCmpOperands(const Comparison &C) {
01229   // Leave f128 comparisons alone, since they have no memory forms.
01230   if (C.Op0.getValueType() == MVT::f128)
01231     return false;
01232 
01233   // Always keep a floating-point constant second, since comparisons with
01234   // zero can use LOAD TEST and comparisons with other constants make a
01235   // natural memory operand.
01236   if (isa<ConstantFPSDNode>(C.Op1))
01237     return false;
01238 
01239   // Never swap comparisons with zero since there are many ways to optimize
01240   // those later.
01241   auto *ConstOp1 = dyn_cast<ConstantSDNode>(C.Op1);
01242   if (ConstOp1 && ConstOp1->getZExtValue() == 0)
01243     return false;
01244 
01245   // Also keep natural memory operands second if the loaded value is
01246   // only used here.  Several comparisons have memory forms.
01247   if (isNaturalMemoryOperand(C.Op1, C.ICmpType) && C.Op1.hasOneUse())
01248     return false;
01249 
01250   // Look for cases where Cmp0 is a single-use load and Cmp1 isn't.
01251   // In that case we generally prefer the memory to be second.
01252   if (isNaturalMemoryOperand(C.Op0, C.ICmpType) && C.Op0.hasOneUse()) {
01253     // The only exceptions are when the second operand is a constant and
01254     // we can use things like CHHSI.
01255     if (!ConstOp1)
01256       return true;
01257     // The unsigned memory-immediate instructions can handle 16-bit
01258     // unsigned integers.
01259     if (C.ICmpType != SystemZICMP::SignedOnly &&
01260         isUInt<16>(ConstOp1->getZExtValue()))
01261       return false;
01262     // The signed memory-immediate instructions can handle 16-bit
01263     // signed integers.
01264     if (C.ICmpType != SystemZICMP::UnsignedOnly &&
01265         isInt<16>(ConstOp1->getSExtValue()))
01266       return false;
01267     return true;
01268   }
01269 
01270   // Try to promote the use of CGFR and CLGFR.
01271   unsigned Opcode0 = C.Op0.getOpcode();
01272   if (C.ICmpType != SystemZICMP::UnsignedOnly && Opcode0 == ISD::SIGN_EXTEND)
01273     return true;
01274   if (C.ICmpType != SystemZICMP::SignedOnly && Opcode0 == ISD::ZERO_EXTEND)
01275     return true;
01276   if (C.ICmpType != SystemZICMP::SignedOnly &&
01277       Opcode0 == ISD::AND &&
01278       C.Op0.getOperand(1).getOpcode() == ISD::Constant &&
01279       cast<ConstantSDNode>(C.Op0.getOperand(1))->getZExtValue() == 0xffffffff)
01280     return true;
01281 
01282   return false;
01283 }
01284 
01285 // Return a version of comparison CC mask CCMask in which the LT and GT
01286 // actions are swapped.
01287 static unsigned reverseCCMask(unsigned CCMask) {
01288   return ((CCMask & SystemZ::CCMASK_CMP_EQ) |
01289           (CCMask & SystemZ::CCMASK_CMP_GT ? SystemZ::CCMASK_CMP_LT : 0) |
01290           (CCMask & SystemZ::CCMASK_CMP_LT ? SystemZ::CCMASK_CMP_GT : 0) |
01291           (CCMask & SystemZ::CCMASK_CMP_UO));
01292 }
01293 
01294 // Check whether C tests for equality between X and Y and whether X - Y
01295 // or Y - X is also computed.  In that case it's better to compare the
01296 // result of the subtraction against zero.
01297 static void adjustForSubtraction(SelectionDAG &DAG, Comparison &C) {
01298   if (C.CCMask == SystemZ::CCMASK_CMP_EQ ||
01299       C.CCMask == SystemZ::CCMASK_CMP_NE) {
01300     for (auto I = C.Op0->use_begin(), E = C.Op0->use_end(); I != E; ++I) {
01301       SDNode *N = *I;
01302       if (N->getOpcode() == ISD::SUB &&
01303           ((N->getOperand(0) == C.Op0 && N->getOperand(1) == C.Op1) ||
01304            (N->getOperand(0) == C.Op1 && N->getOperand(1) == C.Op0))) {
01305         C.Op0 = SDValue(N, 0);
01306         C.Op1 = DAG.getConstant(0, N->getValueType(0));
01307         return;
01308       }
01309     }
01310   }
01311 }
01312 
01313 // Check whether C compares a floating-point value with zero and if that
01314 // floating-point value is also negated.  In this case we can use the
01315 // negation to set CC, so avoiding separate LOAD AND TEST and
01316 // LOAD (NEGATIVE/COMPLEMENT) instructions.
01317 static void adjustForFNeg(Comparison &C) {
01318   auto *C1 = dyn_cast<ConstantFPSDNode>(C.Op1);
01319   if (C1 && C1->isZero()) {
01320     for (auto I = C.Op0->use_begin(), E = C.Op0->use_end(); I != E; ++I) {
01321       SDNode *N = *I;
01322       if (N->getOpcode() == ISD::FNEG) {
01323         C.Op0 = SDValue(N, 0);
01324         C.CCMask = reverseCCMask(C.CCMask);
01325         return;
01326       }
01327     }
01328   }
01329 }
01330 
01331 // Check whether C compares (shl X, 32) with 0 and whether X is
01332 // also sign-extended.  In that case it is better to test the result
01333 // of the sign extension using LTGFR.
01334 //
01335 // This case is important because InstCombine transforms a comparison
01336 // with (sext (trunc X)) into a comparison with (shl X, 32).
01337 static void adjustForLTGFR(Comparison &C) {
01338   // Check for a comparison between (shl X, 32) and 0.
01339   if (C.Op0.getOpcode() == ISD::SHL &&
01340       C.Op0.getValueType() == MVT::i64 &&
01341       C.Op1.getOpcode() == ISD::Constant &&
01342       cast<ConstantSDNode>(C.Op1)->getZExtValue() == 0) {
01343     auto *C1 = dyn_cast<ConstantSDNode>(C.Op0.getOperand(1));
01344     if (C1 && C1->getZExtValue() == 32) {
01345       SDValue ShlOp0 = C.Op0.getOperand(0);
01346       // See whether X has any SIGN_EXTEND_INREG uses.
01347       for (auto I = ShlOp0->use_begin(), E = ShlOp0->use_end(); I != E; ++I) {
01348         SDNode *N = *I;
01349         if (N->getOpcode() == ISD::SIGN_EXTEND_INREG &&
01350             cast<VTSDNode>(N->getOperand(1))->getVT() == MVT::i32) {
01351           C.Op0 = SDValue(N, 0);
01352           return;
01353         }
01354       }
01355     }
01356   }
01357 }
01358 
01359 // If C compares the truncation of an extending load, try to compare
01360 // the untruncated value instead.  This exposes more opportunities to
01361 // reuse CC.
01362 static void adjustICmpTruncate(SelectionDAG &DAG, Comparison &C) {
01363   if (C.Op0.getOpcode() == ISD::TRUNCATE &&
01364       C.Op0.getOperand(0).getOpcode() == ISD::LOAD &&
01365       C.Op1.getOpcode() == ISD::Constant &&
01366       cast<ConstantSDNode>(C.Op1)->getZExtValue() == 0) {
01367     auto *L = cast<LoadSDNode>(C.Op0.getOperand(0));
01368     if (L->getMemoryVT().getStoreSizeInBits()
01369         <= C.Op0.getValueType().getSizeInBits()) {
01370       unsigned Type = L->getExtensionType();
01371       if ((Type == ISD::ZEXTLOAD && C.ICmpType != SystemZICMP::SignedOnly) ||
01372           (Type == ISD::SEXTLOAD && C.ICmpType != SystemZICMP::UnsignedOnly)) {
01373         C.Op0 = C.Op0.getOperand(0);
01374         C.Op1 = DAG.getConstant(0, C.Op0.getValueType());
01375       }
01376     }
01377   }
01378 }
01379 
01380 // Return true if shift operation N has an in-range constant shift value.
01381 // Store it in ShiftVal if so.
01382 static bool isSimpleShift(SDValue N, unsigned &ShiftVal) {
01383   auto *Shift = dyn_cast<ConstantSDNode>(N.getOperand(1));
01384   if (!Shift)
01385     return false;
01386 
01387   uint64_t Amount = Shift->getZExtValue();
01388   if (Amount >= N.getValueType().getSizeInBits())
01389     return false;
01390 
01391   ShiftVal = Amount;
01392   return true;
01393 }
01394 
01395 // Check whether an AND with Mask is suitable for a TEST UNDER MASK
01396 // instruction and whether the CC value is descriptive enough to handle
01397 // a comparison of type Opcode between the AND result and CmpVal.
01398 // CCMask says which comparison result is being tested and BitSize is
01399 // the number of bits in the operands.  If TEST UNDER MASK can be used,
01400 // return the corresponding CC mask, otherwise return 0.
01401 static unsigned getTestUnderMaskCond(unsigned BitSize, unsigned CCMask,
01402                                      uint64_t Mask, uint64_t CmpVal,
01403                                      unsigned ICmpType) {
01404   assert(Mask != 0 && "ANDs with zero should have been removed by now");
01405 
01406   // Check whether the mask is suitable for TMHH, TMHL, TMLH or TMLL.
01407   if (!SystemZ::isImmLL(Mask) && !SystemZ::isImmLH(Mask) &&
01408       !SystemZ::isImmHL(Mask) && !SystemZ::isImmHH(Mask))
01409     return 0;
01410 
01411   // Work out the masks for the lowest and highest bits.
01412   unsigned HighShift = 63 - countLeadingZeros(Mask);
01413   uint64_t High = uint64_t(1) << HighShift;
01414   uint64_t Low = uint64_t(1) << countTrailingZeros(Mask);
01415 
01416   // Signed ordered comparisons are effectively unsigned if the sign
01417   // bit is dropped.
01418   bool EffectivelyUnsigned = (ICmpType != SystemZICMP::SignedOnly);
01419 
01420   // Check for equality comparisons with 0, or the equivalent.
01421   if (CmpVal == 0) {
01422     if (CCMask == SystemZ::CCMASK_CMP_EQ)
01423       return SystemZ::CCMASK_TM_ALL_0;
01424     if (CCMask == SystemZ::CCMASK_CMP_NE)
01425       return SystemZ::CCMASK_TM_SOME_1;
01426   }
01427   if (EffectivelyUnsigned && CmpVal <= Low) {
01428     if (CCMask == SystemZ::CCMASK_CMP_LT)
01429       return SystemZ::CCMASK_TM_ALL_0;
01430     if (CCMask == SystemZ::CCMASK_CMP_GE)
01431       return SystemZ::CCMASK_TM_SOME_1;
01432   }
01433   if (EffectivelyUnsigned && CmpVal < Low) {
01434     if (CCMask == SystemZ::CCMASK_CMP_LE)
01435       return SystemZ::CCMASK_TM_ALL_0;
01436     if (CCMask == SystemZ::CCMASK_CMP_GT)
01437       return SystemZ::CCMASK_TM_SOME_1;
01438   }
01439 
01440   // Check for equality comparisons with the mask, or the equivalent.
01441   if (CmpVal == Mask) {
01442     if (CCMask == SystemZ::CCMASK_CMP_EQ)
01443       return SystemZ::CCMASK_TM_ALL_1;
01444     if (CCMask == SystemZ::CCMASK_CMP_NE)
01445       return SystemZ::CCMASK_TM_SOME_0;
01446   }
01447   if (EffectivelyUnsigned && CmpVal >= Mask - Low && CmpVal < Mask) {
01448     if (CCMask == SystemZ::CCMASK_CMP_GT)
01449       return SystemZ::CCMASK_TM_ALL_1;
01450     if (CCMask == SystemZ::CCMASK_CMP_LE)
01451       return SystemZ::CCMASK_TM_SOME_0;
01452   }
01453   if (EffectivelyUnsigned && CmpVal > Mask - Low && CmpVal <= Mask) {
01454     if (CCMask == SystemZ::CCMASK_CMP_GE)
01455       return SystemZ::CCMASK_TM_ALL_1;
01456     if (CCMask == SystemZ::CCMASK_CMP_LT)
01457       return SystemZ::CCMASK_TM_SOME_0;
01458   }
01459 
01460   // Check for ordered comparisons with the top bit.
01461   if (EffectivelyUnsigned && CmpVal >= Mask - High && CmpVal < High) {
01462     if (CCMask == SystemZ::CCMASK_CMP_LE)
01463       return SystemZ::CCMASK_TM_MSB_0;
01464     if (CCMask == SystemZ::CCMASK_CMP_GT)
01465       return SystemZ::CCMASK_TM_MSB_1;
01466   }
01467   if (EffectivelyUnsigned && CmpVal > Mask - High && CmpVal <= High) {
01468     if (CCMask == SystemZ::CCMASK_CMP_LT)
01469       return SystemZ::CCMASK_TM_MSB_0;
01470     if (CCMask == SystemZ::CCMASK_CMP_GE)
01471       return SystemZ::CCMASK_TM_MSB_1;
01472   }
01473 
01474   // If there are just two bits, we can do equality checks for Low and High
01475   // as well.
01476   if (Mask == Low + High) {
01477     if (CCMask == SystemZ::CCMASK_CMP_EQ && CmpVal == Low)
01478       return SystemZ::CCMASK_TM_MIXED_MSB_0;
01479     if (CCMask == SystemZ::CCMASK_CMP_NE && CmpVal == Low)
01480       return SystemZ::CCMASK_TM_MIXED_MSB_0 ^ SystemZ::CCMASK_ANY;
01481     if (CCMask == SystemZ::CCMASK_CMP_EQ && CmpVal == High)
01482       return SystemZ::CCMASK_TM_MIXED_MSB_1;
01483     if (CCMask == SystemZ::CCMASK_CMP_NE && CmpVal == High)
01484       return SystemZ::CCMASK_TM_MIXED_MSB_1 ^ SystemZ::CCMASK_ANY;
01485   }
01486 
01487   // Looks like we've exhausted our options.
01488   return 0;
01489 }
01490 
01491 // See whether C can be implemented as a TEST UNDER MASK instruction.
01492 // Update the arguments with the TM version if so.
01493 static void adjustForTestUnderMask(SelectionDAG &DAG, Comparison &C) {
01494   // Check that we have a comparison with a constant.
01495   auto *ConstOp1 = dyn_cast<ConstantSDNode>(C.Op1);
01496   if (!ConstOp1)
01497     return;
01498   uint64_t CmpVal = ConstOp1->getZExtValue();
01499 
01500   // Check whether the nonconstant input is an AND with a constant mask.
01501   Comparison NewC(C);
01502   uint64_t MaskVal;
01503   ConstantSDNode *Mask = nullptr;
01504   if (C.Op0.getOpcode() == ISD::AND) {
01505     NewC.Op0 = C.Op0.getOperand(0);
01506     NewC.Op1 = C.Op0.getOperand(1);
01507     Mask = dyn_cast<ConstantSDNode>(NewC.Op1);
01508     if (!Mask)
01509       return;
01510     MaskVal = Mask->getZExtValue();
01511   } else {
01512     // There is no instruction to compare with a 64-bit immediate
01513     // so use TMHH instead if possible.  We need an unsigned ordered
01514     // comparison with an i64 immediate.
01515     if (NewC.Op0.getValueType() != MVT::i64 ||
01516         NewC.CCMask == SystemZ::CCMASK_CMP_EQ ||
01517         NewC.CCMask == SystemZ::CCMASK_CMP_NE ||
01518         NewC.ICmpType == SystemZICMP::SignedOnly)
01519       return;
01520     // Convert LE and GT comparisons into LT and GE.
01521     if (NewC.CCMask == SystemZ::CCMASK_CMP_LE ||
01522         NewC.CCMask == SystemZ::CCMASK_CMP_GT) {
01523       if (CmpVal == uint64_t(-1))
01524         return;
01525       CmpVal += 1;
01526       NewC.CCMask ^= SystemZ::CCMASK_CMP_EQ;
01527     }
01528     // If the low N bits of Op1 are zero than the low N bits of Op0 can
01529     // be masked off without changing the result.
01530     MaskVal = -(CmpVal & -CmpVal);
01531     NewC.ICmpType = SystemZICMP::UnsignedOnly;
01532   }
01533 
01534   // Check whether the combination of mask, comparison value and comparison
01535   // type are suitable.
01536   unsigned BitSize = NewC.Op0.getValueType().getSizeInBits();
01537   unsigned NewCCMask, ShiftVal;
01538   if (NewC.ICmpType != SystemZICMP::SignedOnly &&
01539       NewC.Op0.getOpcode() == ISD::SHL &&
01540       isSimpleShift(NewC.Op0, ShiftVal) &&
01541       (NewCCMask = getTestUnderMaskCond(BitSize, NewC.CCMask,
01542                                         MaskVal >> ShiftVal,
01543                                         CmpVal >> ShiftVal,
01544                                         SystemZICMP::Any))) {
01545     NewC.Op0 = NewC.Op0.getOperand(0);
01546     MaskVal >>= ShiftVal;
01547   } else if (NewC.ICmpType != SystemZICMP::SignedOnly &&
01548              NewC.Op0.getOpcode() == ISD::SRL &&
01549              isSimpleShift(NewC.Op0, ShiftVal) &&
01550              (NewCCMask = getTestUnderMaskCond(BitSize, NewC.CCMask,
01551                                                MaskVal << ShiftVal,
01552                                                CmpVal << ShiftVal,
01553                                                SystemZICMP::UnsignedOnly))) {
01554     NewC.Op0 = NewC.Op0.getOperand(0);
01555     MaskVal <<= ShiftVal;
01556   } else {
01557     NewCCMask = getTestUnderMaskCond(BitSize, NewC.CCMask, MaskVal, CmpVal,
01558                                      NewC.ICmpType);
01559     if (!NewCCMask)
01560       return;
01561   }
01562 
01563   // Go ahead and make the change.
01564   C.Opcode = SystemZISD::TM;
01565   C.Op0 = NewC.Op0;
01566   if (Mask && Mask->getZExtValue() == MaskVal)
01567     C.Op1 = SDValue(Mask, 0);
01568   else
01569     C.Op1 = DAG.getConstant(MaskVal, C.Op0.getValueType());
01570   C.CCValid = SystemZ::CCMASK_TM;
01571   C.CCMask = NewCCMask;
01572 }
01573 
01574 // Decide how to implement a comparison of type Cond between CmpOp0 with CmpOp1.
01575 static Comparison getCmp(SelectionDAG &DAG, SDValue CmpOp0, SDValue CmpOp1,
01576                          ISD::CondCode Cond) {
01577   Comparison C(CmpOp0, CmpOp1);
01578   C.CCMask = CCMaskForCondCode(Cond);
01579   if (C.Op0.getValueType().isFloatingPoint()) {
01580     C.CCValid = SystemZ::CCMASK_FCMP;
01581     C.Opcode = SystemZISD::FCMP;
01582     adjustForFNeg(C);
01583   } else {
01584     C.CCValid = SystemZ::CCMASK_ICMP;
01585     C.Opcode = SystemZISD::ICMP;
01586     // Choose the type of comparison.  Equality and inequality tests can
01587     // use either signed or unsigned comparisons.  The choice also doesn't
01588     // matter if both sign bits are known to be clear.  In those cases we
01589     // want to give the main isel code the freedom to choose whichever
01590     // form fits best.
01591     if (C.CCMask == SystemZ::CCMASK_CMP_EQ ||
01592         C.CCMask == SystemZ::CCMASK_CMP_NE ||
01593         (DAG.SignBitIsZero(C.Op0) && DAG.SignBitIsZero(C.Op1)))
01594       C.ICmpType = SystemZICMP::Any;
01595     else if (C.CCMask & SystemZ::CCMASK_CMP_UO)
01596       C.ICmpType = SystemZICMP::UnsignedOnly;
01597     else
01598       C.ICmpType = SystemZICMP::SignedOnly;
01599     C.CCMask &= ~SystemZ::CCMASK_CMP_UO;
01600     adjustZeroCmp(DAG, C);
01601     adjustSubwordCmp(DAG, C);
01602     adjustForSubtraction(DAG, C);
01603     adjustForLTGFR(C);
01604     adjustICmpTruncate(DAG, C);
01605   }
01606 
01607   if (shouldSwapCmpOperands(C)) {
01608     std::swap(C.Op0, C.Op1);
01609     C.CCMask = reverseCCMask(C.CCMask);
01610   }
01611 
01612   adjustForTestUnderMask(DAG, C);
01613   return C;
01614 }
01615 
01616 // Emit the comparison instruction described by C.
01617 static SDValue emitCmp(SelectionDAG &DAG, SDLoc DL, Comparison &C) {
01618   if (C.Opcode == SystemZISD::ICMP)
01619     return DAG.getNode(SystemZISD::ICMP, DL, MVT::Glue, C.Op0, C.Op1,
01620                        DAG.getConstant(C.ICmpType, MVT::i32));
01621   if (C.Opcode == SystemZISD::TM) {
01622     bool RegisterOnly = (bool(C.CCMask & SystemZ::CCMASK_TM_MIXED_MSB_0) !=
01623                          bool(C.CCMask & SystemZ::CCMASK_TM_MIXED_MSB_1));
01624     return DAG.getNode(SystemZISD::TM, DL, MVT::Glue, C.Op0, C.Op1,
01625                        DAG.getConstant(RegisterOnly, MVT::i32));
01626   }
01627   return DAG.getNode(C.Opcode, DL, MVT::Glue, C.Op0, C.Op1);
01628 }
01629 
01630 // Implement a 32-bit *MUL_LOHI operation by extending both operands to
01631 // 64 bits.  Extend is the extension type to use.  Store the high part
01632 // in Hi and the low part in Lo.
01633 static void lowerMUL_LOHI32(SelectionDAG &DAG, SDLoc DL,
01634                             unsigned Extend, SDValue Op0, SDValue Op1,
01635                             SDValue &Hi, SDValue &Lo) {
01636   Op0 = DAG.getNode(Extend, DL, MVT::i64, Op0);
01637   Op1 = DAG.getNode(Extend, DL, MVT::i64, Op1);
01638   SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, Op0, Op1);
01639   Hi = DAG.getNode(ISD::SRL, DL, MVT::i64, Mul, DAG.getConstant(32, MVT::i64));
01640   Hi = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Hi);
01641   Lo = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mul);
01642 }
01643 
01644 // Lower a binary operation that produces two VT results, one in each
01645 // half of a GR128 pair.  Op0 and Op1 are the VT operands to the operation,
01646 // Extend extends Op0 to a GR128, and Opcode performs the GR128 operation
01647 // on the extended Op0 and (unextended) Op1.  Store the even register result
01648 // in Even and the odd register result in Odd.
01649 static void lowerGR128Binary(SelectionDAG &DAG, SDLoc DL, EVT VT,
01650                              unsigned Extend, unsigned Opcode,
01651                              SDValue Op0, SDValue Op1,
01652                              SDValue &Even, SDValue &Odd) {
01653   SDNode *In128 = DAG.getMachineNode(Extend, DL, MVT::Untyped, Op0);
01654   SDValue Result = DAG.getNode(Opcode, DL, MVT::Untyped,
01655                                SDValue(In128, 0), Op1);
01656   bool Is32Bit = is32Bit(VT);
01657   Even = DAG.getTargetExtractSubreg(SystemZ::even128(Is32Bit), DL, VT, Result);
01658   Odd = DAG.getTargetExtractSubreg(SystemZ::odd128(Is32Bit), DL, VT, Result);
01659 }
01660 
01661 // Return an i32 value that is 1 if the CC value produced by Glue is
01662 // in the mask CCMask and 0 otherwise.  CC is known to have a value
01663 // in CCValid, so other values can be ignored.
01664 static SDValue emitSETCC(SelectionDAG &DAG, SDLoc DL, SDValue Glue,
01665                          unsigned CCValid, unsigned CCMask) {
01666   IPMConversion Conversion = getIPMConversion(CCValid, CCMask);
01667   SDValue Result = DAG.getNode(SystemZISD::IPM, DL, MVT::i32, Glue);
01668 
01669   if (Conversion.XORValue)
01670     Result = DAG.getNode(ISD::XOR, DL, MVT::i32, Result,
01671                          DAG.getConstant(Conversion.XORValue, MVT::i32));
01672 
01673   if (Conversion.AddValue)
01674     Result = DAG.getNode(ISD::ADD, DL, MVT::i32, Result,
01675                          DAG.getConstant(Conversion.AddValue, MVT::i32));
01676 
01677   // The SHR/AND sequence should get optimized to an RISBG.
01678   Result = DAG.getNode(ISD::SRL, DL, MVT::i32, Result,
01679                        DAG.getConstant(Conversion.Bit, MVT::i32));
01680   if (Conversion.Bit != 31)
01681     Result = DAG.getNode(ISD::AND, DL, MVT::i32, Result,
01682                          DAG.getConstant(1, MVT::i32));
01683   return Result;
01684 }
01685 
01686 SDValue SystemZTargetLowering::lowerSETCC(SDValue Op,
01687                                           SelectionDAG &DAG) const {
01688   SDValue CmpOp0   = Op.getOperand(0);
01689   SDValue CmpOp1   = Op.getOperand(1);
01690   ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
01691   SDLoc DL(Op);
01692 
01693   Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC));
01694   SDValue Glue = emitCmp(DAG, DL, C);
01695   return emitSETCC(DAG, DL, Glue, C.CCValid, C.CCMask);
01696 }
01697 
01698 SDValue SystemZTargetLowering::lowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
01699   SDValue Chain    = Op.getOperand(0);
01700   ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
01701   SDValue CmpOp0   = Op.getOperand(2);
01702   SDValue CmpOp1   = Op.getOperand(3);
01703   SDValue Dest     = Op.getOperand(4);
01704   SDLoc DL(Op);
01705 
01706   Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC));
01707   SDValue Glue = emitCmp(DAG, DL, C);
01708   return DAG.getNode(SystemZISD::BR_CCMASK, DL, Op.getValueType(),
01709                      Chain, DAG.getConstant(C.CCValid, MVT::i32),
01710                      DAG.getConstant(C.CCMask, MVT::i32), Dest, Glue);
01711 }
01712 
01713 // Return true if Pos is CmpOp and Neg is the negative of CmpOp,
01714 // allowing Pos and Neg to be wider than CmpOp.
01715 static bool isAbsolute(SDValue CmpOp, SDValue Pos, SDValue Neg) {
01716   return (Neg.getOpcode() == ISD::SUB &&
01717           Neg.getOperand(0).getOpcode() == ISD::Constant &&
01718           cast<ConstantSDNode>(Neg.getOperand(0))->getZExtValue() == 0 &&
01719           Neg.getOperand(1) == Pos &&
01720           (Pos == CmpOp ||
01721            (Pos.getOpcode() == ISD::SIGN_EXTEND &&
01722             Pos.getOperand(0) == CmpOp)));
01723 }
01724 
01725 // Return the absolute or negative absolute of Op; IsNegative decides which.
01726 static SDValue getAbsolute(SelectionDAG &DAG, SDLoc DL, SDValue Op,
01727                            bool IsNegative) {
01728   Op = DAG.getNode(SystemZISD::IABS, DL, Op.getValueType(), Op);
01729   if (IsNegative)
01730     Op = DAG.getNode(ISD::SUB, DL, Op.getValueType(),
01731                      DAG.getConstant(0, Op.getValueType()), Op);
01732   return Op;
01733 }
01734 
01735 SDValue SystemZTargetLowering::lowerSELECT_CC(SDValue Op,
01736                                               SelectionDAG &DAG) const {
01737   SDValue CmpOp0   = Op.getOperand(0);
01738   SDValue CmpOp1   = Op.getOperand(1);
01739   SDValue TrueOp   = Op.getOperand(2);
01740   SDValue FalseOp  = Op.getOperand(3);
01741   ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
01742   SDLoc DL(Op);
01743 
01744   Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC));
01745 
01746   // Check for absolute and negative-absolute selections, including those
01747   // where the comparison value is sign-extended (for LPGFR and LNGFR).
01748   // This check supplements the one in DAGCombiner.
01749   if (C.Opcode == SystemZISD::ICMP &&
01750       C.CCMask != SystemZ::CCMASK_CMP_EQ &&
01751       C.CCMask != SystemZ::CCMASK_CMP_NE &&
01752       C.Op1.getOpcode() == ISD::Constant &&
01753       cast<ConstantSDNode>(C.Op1)->getZExtValue() == 0) {
01754     if (isAbsolute(C.Op0, TrueOp, FalseOp))
01755       return getAbsolute(DAG, DL, TrueOp, C.CCMask & SystemZ::CCMASK_CMP_LT);
01756     if (isAbsolute(C.Op0, FalseOp, TrueOp))
01757       return getAbsolute(DAG, DL, FalseOp, C.CCMask & SystemZ::CCMASK_CMP_GT);
01758   }
01759 
01760   SDValue Glue = emitCmp(DAG, DL, C);
01761 
01762   // Special case for handling -1/0 results.  The shifts we use here
01763   // should get optimized with the IPM conversion sequence.
01764   auto *TrueC = dyn_cast<ConstantSDNode>(TrueOp);
01765   auto *FalseC = dyn_cast<ConstantSDNode>(FalseOp);
01766   if (TrueC && FalseC) {
01767     int64_t TrueVal = TrueC->getSExtValue();
01768     int64_t FalseVal = FalseC->getSExtValue();
01769     if ((TrueVal == -1 && FalseVal == 0) || (TrueVal == 0 && FalseVal == -1)) {
01770       // Invert the condition if we want -1 on false.
01771       if (TrueVal == 0)
01772         C.CCMask ^= C.CCValid;
01773       SDValue Result = emitSETCC(DAG, DL, Glue, C.CCValid, C.CCMask);
01774       EVT VT = Op.getValueType();
01775       // Extend the result to VT.  Upper bits are ignored.
01776       if (!is32Bit(VT))
01777         Result = DAG.getNode(ISD::ANY_EXTEND, DL, VT, Result);
01778       // Sign-extend from the low bit.
01779       SDValue ShAmt = DAG.getConstant(VT.getSizeInBits() - 1, MVT::i32);
01780       SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, Result, ShAmt);
01781       return DAG.getNode(ISD::SRA, DL, VT, Shl, ShAmt);
01782     }
01783   }
01784 
01785   SDValue Ops[] = {TrueOp, FalseOp, DAG.getConstant(C.CCValid, MVT::i32),
01786                    DAG.getConstant(C.CCMask, MVT::i32), Glue};
01787 
01788   SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
01789   return DAG.getNode(SystemZISD::SELECT_CCMASK, DL, VTs, Ops);
01790 }
01791 
01792 SDValue SystemZTargetLowering::lowerGlobalAddress(GlobalAddressSDNode *Node,
01793                                                   SelectionDAG &DAG) const {
01794   SDLoc DL(Node);
01795   const GlobalValue *GV = Node->getGlobal();
01796   int64_t Offset = Node->getOffset();
01797   EVT PtrVT = getPointerTy();
01798   Reloc::Model RM = DAG.getTarget().getRelocationModel();
01799   CodeModel::Model CM = DAG.getTarget().getCodeModel();
01800 
01801   SDValue Result;
01802   if (Subtarget.isPC32DBLSymbol(GV, RM, CM)) {
01803     // Assign anchors at 1<<12 byte boundaries.
01804     uint64_t Anchor = Offset & ~uint64_t(0xfff);
01805     Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, Anchor);
01806     Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
01807 
01808     // The offset can be folded into the address if it is aligned to a halfword.
01809     Offset -= Anchor;
01810     if (Offset != 0 && (Offset & 1) == 0) {
01811       SDValue Full = DAG.getTargetGlobalAddress(GV, DL, PtrVT, Anchor + Offset);
01812       Result = DAG.getNode(SystemZISD::PCREL_OFFSET, DL, PtrVT, Full, Result);
01813       Offset = 0;
01814     }
01815   } else {
01816     Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, SystemZII::MO_GOT);
01817     Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
01818     Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
01819                          MachinePointerInfo::getGOT(), false, false, false, 0);
01820   }
01821 
01822   // If there was a non-zero offset that we didn't fold, create an explicit
01823   // addition for it.
01824   if (Offset != 0)
01825     Result = DAG.getNode(ISD::ADD, DL, PtrVT, Result,
01826                          DAG.getConstant(Offset, PtrVT));
01827 
01828   return Result;
01829 }
01830 
01831 SDValue SystemZTargetLowering::lowerTLSGetOffset(GlobalAddressSDNode *Node,
01832                                                  SelectionDAG &DAG,
01833                                                  unsigned Opcode,
01834                                                  SDValue GOTOffset) const {
01835   SDLoc DL(Node);
01836   EVT PtrVT = getPointerTy();
01837   SDValue Chain = DAG.getEntryNode();
01838   SDValue Glue;
01839 
01840   // __tls_get_offset takes the GOT offset in %r2 and the GOT in %r12.
01841   SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
01842   Chain = DAG.getCopyToReg(Chain, DL, SystemZ::R12D, GOT, Glue);
01843   Glue = Chain.getValue(1);
01844   Chain = DAG.getCopyToReg(Chain, DL, SystemZ::R2D, GOTOffset, Glue);
01845   Glue = Chain.getValue(1);
01846 
01847   // The first call operand is the chain and the second is the TLS symbol.
01848   SmallVector<SDValue, 8> Ops;
01849   Ops.push_back(Chain);
01850   Ops.push_back(DAG.getTargetGlobalAddress(Node->getGlobal(), DL,
01851                                            Node->getValueType(0),
01852                                            0, 0));
01853 
01854   // Add argument registers to the end of the list so that they are
01855   // known live into the call.
01856   Ops.push_back(DAG.getRegister(SystemZ::R2D, PtrVT));
01857   Ops.push_back(DAG.getRegister(SystemZ::R12D, PtrVT));
01858 
01859   // Add a register mask operand representing the call-preserved registers.
01860   const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
01861   const uint32_t *Mask =
01862       TRI->getCallPreservedMask(DAG.getMachineFunction(), CallingConv::C);
01863   assert(Mask && "Missing call preserved mask for calling convention");
01864   Ops.push_back(DAG.getRegisterMask(Mask));
01865 
01866   // Glue the call to the argument copies.
01867   Ops.push_back(Glue);
01868 
01869   // Emit the call.
01870   SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
01871   Chain = DAG.getNode(Opcode, DL, NodeTys, Ops);
01872   Glue = Chain.getValue(1);
01873 
01874   // Copy the return value from %r2.
01875   return DAG.getCopyFromReg(Chain, DL, SystemZ::R2D, PtrVT, Glue);
01876 }
01877 
01878 SDValue SystemZTargetLowering::lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
01879                  SelectionDAG &DAG) const {
01880   SDLoc DL(Node);
01881   const GlobalValue *GV = Node->getGlobal();
01882   EVT PtrVT = getPointerTy();
01883   TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
01884 
01885   // The high part of the thread pointer is in access register 0.
01886   SDValue TPHi = DAG.getNode(SystemZISD::EXTRACT_ACCESS, DL, MVT::i32,
01887                              DAG.getConstant(0, MVT::i32));
01888   TPHi = DAG.getNode(ISD::ANY_EXTEND, DL, PtrVT, TPHi);
01889 
01890   // The low part of the thread pointer is in access register 1.
01891   SDValue TPLo = DAG.getNode(SystemZISD::EXTRACT_ACCESS, DL, MVT::i32,
01892                              DAG.getConstant(1, MVT::i32));
01893   TPLo = DAG.getNode(ISD::ZERO_EXTEND, DL, PtrVT, TPLo);
01894 
01895   // Merge them into a single 64-bit address.
01896   SDValue TPHiShifted = DAG.getNode(ISD::SHL, DL, PtrVT, TPHi,
01897             DAG.getConstant(32, PtrVT));
01898   SDValue TP = DAG.getNode(ISD::OR, DL, PtrVT, TPHiShifted, TPLo);
01899 
01900   // Get the offset of GA from the thread pointer, based on the TLS model.
01901   SDValue Offset;
01902   switch (model) {
01903     case TLSModel::GeneralDynamic: {
01904       // Load the GOT offset of the tls_index (module ID / per-symbol offset).
01905       SystemZConstantPoolValue *CPV =
01906         SystemZConstantPoolValue::Create(GV, SystemZCP::TLSGD);
01907 
01908       Offset = DAG.getConstantPool(CPV, PtrVT, 8);
01909       Offset = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(),
01910                            Offset, MachinePointerInfo::getConstantPool(),
01911                            false, false, false, 0);
01912 
01913       // Call __tls_get_offset to retrieve the offset.
01914       Offset = lowerTLSGetOffset(Node, DAG, SystemZISD::TLS_GDCALL, Offset);
01915       break;
01916     }
01917 
01918     case TLSModel::LocalDynamic: {
01919       // Load the GOT offset of the module ID.
01920       SystemZConstantPoolValue *CPV =
01921         SystemZConstantPoolValue::Create(GV, SystemZCP::TLSLDM);
01922 
01923       Offset = DAG.getConstantPool(CPV, PtrVT, 8);
01924       Offset = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(),
01925                            Offset, MachinePointerInfo::getConstantPool(),
01926                            false, false, false, 0);
01927 
01928       // Call __tls_get_offset to retrieve the module base offset.
01929       Offset = lowerTLSGetOffset(Node, DAG, SystemZISD::TLS_LDCALL, Offset);
01930 
01931       // Note: The SystemZLDCleanupPass will remove redundant computations
01932       // of the module base offset.  Count total number of local-dynamic
01933       // accesses to trigger execution of that pass.
01934       SystemZMachineFunctionInfo* MFI =
01935         DAG.getMachineFunction().getInfo<SystemZMachineFunctionInfo>();
01936       MFI->incNumLocalDynamicTLSAccesses();
01937 
01938       // Add the per-symbol offset.
01939       CPV = SystemZConstantPoolValue::Create(GV, SystemZCP::DTPOFF);
01940 
01941       SDValue DTPOffset = DAG.getConstantPool(CPV, PtrVT, 8);
01942       DTPOffset = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(),
01943                               DTPOffset, MachinePointerInfo::getConstantPool(),
01944                               false, false, false, 0);
01945 
01946       Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Offset, DTPOffset);
01947       break;
01948     }
01949 
01950     case TLSModel::InitialExec: {
01951       // Load the offset from the GOT.
01952       Offset = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
01953                                           SystemZII::MO_INDNTPOFF);
01954       Offset = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Offset);
01955       Offset = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(),
01956                            Offset, MachinePointerInfo::getGOT(),
01957                            false, false, false, 0);
01958       break;
01959     }
01960 
01961     case TLSModel::LocalExec: {
01962       // Force the offset into the constant pool and load it from there.
01963       SystemZConstantPoolValue *CPV =
01964         SystemZConstantPoolValue::Create(GV, SystemZCP::NTPOFF);
01965 
01966       Offset = DAG.getConstantPool(CPV, PtrVT, 8);
01967       Offset = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(),
01968                            Offset, MachinePointerInfo::getConstantPool(),
01969                            false, false, false, 0);
01970       break;
01971     }
01972   }
01973 
01974   // Add the base and offset together.
01975   return DAG.getNode(ISD::ADD, DL, PtrVT, TP, Offset);
01976 }
01977 
01978 SDValue SystemZTargetLowering::lowerBlockAddress(BlockAddressSDNode *Node,
01979                                                  SelectionDAG &DAG) const {
01980   SDLoc DL(Node);
01981   const BlockAddress *BA = Node->getBlockAddress();
01982   int64_t Offset = Node->getOffset();
01983   EVT PtrVT = getPointerTy();
01984 
01985   SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT, Offset);
01986   Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
01987   return Result;
01988 }
01989 
01990 SDValue SystemZTargetLowering::lowerJumpTable(JumpTableSDNode *JT,
01991                                               SelectionDAG &DAG) const {
01992   SDLoc DL(JT);
01993   EVT PtrVT = getPointerTy();
01994   SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
01995 
01996   // Use LARL to load the address of the table.
01997   return DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
01998 }
01999 
02000 SDValue SystemZTargetLowering::lowerConstantPool(ConstantPoolSDNode *CP,
02001                                                  SelectionDAG &DAG) const {
02002   SDLoc DL(CP);
02003   EVT PtrVT = getPointerTy();
02004 
02005   SDValue Result;
02006   if (CP->isMachineConstantPoolEntry())
02007     Result = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
02008                CP->getAlignment());
02009   else
02010     Result = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
02011                CP->getAlignment(), CP->getOffset());
02012 
02013   // Use LARL to load the address of the constant pool entry.
02014   return DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
02015 }
02016 
02017 SDValue SystemZTargetLowering::lowerBITCAST(SDValue Op,
02018                                             SelectionDAG &DAG) const {
02019   SDLoc DL(Op);
02020   SDValue In = Op.getOperand(0);
02021   EVT InVT = In.getValueType();
02022   EVT ResVT = Op.getValueType();
02023 
02024   if (InVT == MVT::i32 && ResVT == MVT::f32) {
02025     SDValue In64;
02026     if (Subtarget.hasHighWord()) {
02027       SDNode *U64 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL,
02028                                        MVT::i64);
02029       In64 = DAG.getTargetInsertSubreg(SystemZ::subreg_h32, DL,
02030                                        MVT::i64, SDValue(U64, 0), In);
02031     } else {
02032       In64 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, In);
02033       In64 = DAG.getNode(ISD::SHL, DL, MVT::i64, In64,
02034                          DAG.getConstant(32, MVT::i64));
02035     }
02036     SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::f64, In64);
02037     return DAG.getTargetExtractSubreg(SystemZ::subreg_h32,
02038                                       DL, MVT::f32, Out64);
02039   }
02040   if (InVT == MVT::f32 && ResVT == MVT::i32) {
02041     SDNode *U64 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, MVT::f64);
02042     SDValue In64 = DAG.getTargetInsertSubreg(SystemZ::subreg_h32, DL,
02043                                              MVT::f64, SDValue(U64, 0), In);
02044     SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::i64, In64);
02045     if (Subtarget.hasHighWord())
02046       return DAG.getTargetExtractSubreg(SystemZ::subreg_h32, DL,
02047                                         MVT::i32, Out64);
02048     SDValue Shift = DAG.getNode(ISD::SRL, DL, MVT::i64, Out64,
02049                                 DAG.getConstant(32, MVT::i64));
02050     return DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Shift);
02051   }
02052   llvm_unreachable("Unexpected bitcast combination");
02053 }
02054 
02055 SDValue SystemZTargetLowering::lowerVASTART(SDValue Op,
02056                                             SelectionDAG &DAG) const {
02057   MachineFunction &MF = DAG.getMachineFunction();
02058   SystemZMachineFunctionInfo *FuncInfo =
02059     MF.getInfo<SystemZMachineFunctionInfo>();
02060   EVT PtrVT = getPointerTy();
02061 
02062   SDValue Chain   = Op.getOperand(0);
02063   SDValue Addr    = Op.getOperand(1);
02064   const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
02065   SDLoc DL(Op);
02066 
02067   // The initial values of each field.
02068   const unsigned NumFields = 4;
02069   SDValue Fields[NumFields] = {
02070     DAG.getConstant(FuncInfo->getVarArgsFirstGPR(), PtrVT),
02071     DAG.getConstant(FuncInfo->getVarArgsFirstFPR(), PtrVT),
02072     DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT),
02073     DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), PtrVT)
02074   };
02075 
02076   // Store each field into its respective slot.
02077   SDValue MemOps[NumFields];
02078   unsigned Offset = 0;
02079   for (unsigned I = 0; I < NumFields; ++I) {
02080     SDValue FieldAddr = Addr;
02081     if (Offset != 0)
02082       FieldAddr = DAG.getNode(ISD::ADD, DL, PtrVT, FieldAddr,
02083                               DAG.getIntPtrConstant(Offset));
02084     MemOps[I] = DAG.getStore(Chain, DL, Fields[I], FieldAddr,
02085                              MachinePointerInfo(SV, Offset),
02086                              false, false, 0);
02087     Offset += 8;
02088   }
02089   return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
02090 }
02091 
02092 SDValue SystemZTargetLowering::lowerVACOPY(SDValue Op,
02093                                            SelectionDAG &DAG) const {
02094   SDValue Chain      = Op.getOperand(0);
02095   SDValue DstPtr     = Op.getOperand(1);
02096   SDValue SrcPtr     = Op.getOperand(2);
02097   const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
02098   const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
02099   SDLoc DL(Op);
02100 
02101   return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr, DAG.getIntPtrConstant(32),
02102                        /*Align*/8, /*isVolatile*/false, /*AlwaysInline*/false,
02103                        MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
02104 }
02105 
02106 SDValue SystemZTargetLowering::
02107 lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const {
02108   SDValue Chain = Op.getOperand(0);
02109   SDValue Size  = Op.getOperand(1);
02110   SDLoc DL(Op);
02111 
02112   unsigned SPReg = getStackPointerRegisterToSaveRestore();
02113 
02114   // Get a reference to the stack pointer.
02115   SDValue OldSP = DAG.getCopyFromReg(Chain, DL, SPReg, MVT::i64);
02116 
02117   // Get the new stack pointer value.
02118   SDValue NewSP = DAG.getNode(ISD::SUB, DL, MVT::i64, OldSP, Size);
02119 
02120   // Copy the new stack pointer back.
02121   Chain = DAG.getCopyToReg(Chain, DL, SPReg, NewSP);
02122 
02123   // The allocated data lives above the 160 bytes allocated for the standard
02124   // frame, plus any outgoing stack arguments.  We don't know how much that
02125   // amounts to yet, so emit a special ADJDYNALLOC placeholder.
02126   SDValue ArgAdjust = DAG.getNode(SystemZISD::ADJDYNALLOC, DL, MVT::i64);
02127   SDValue Result = DAG.getNode(ISD::ADD, DL, MVT::i64, NewSP, ArgAdjust);
02128 
02129   SDValue Ops[2] = { Result, Chain };
02130   return DAG.getMergeValues(Ops, DL);
02131 }
02132 
02133 SDValue SystemZTargetLowering::lowerSMUL_LOHI(SDValue Op,
02134                                               SelectionDAG &DAG) const {
02135   EVT VT = Op.getValueType();
02136   SDLoc DL(Op);
02137   SDValue Ops[2];
02138   if (is32Bit(VT))
02139     // Just do a normal 64-bit multiplication and extract the results.
02140     // We define this so that it can be used for constant division.
02141     lowerMUL_LOHI32(DAG, DL, ISD::SIGN_EXTEND, Op.getOperand(0),
02142                     Op.getOperand(1), Ops[1], Ops[0]);
02143   else {
02144     // Do a full 128-bit multiplication based on UMUL_LOHI64:
02145     //
02146     //   (ll * rl) + ((lh * rl) << 64) + ((ll * rh) << 64)
02147     //
02148     // but using the fact that the upper halves are either all zeros
02149     // or all ones:
02150     //
02151     //   (ll * rl) - ((lh & rl) << 64) - ((ll & rh) << 64)
02152     //
02153     // and grouping the right terms together since they are quicker than the
02154     // multiplication:
02155     //
02156     //   (ll * rl) - (((lh & rl) + (ll & rh)) << 64)
02157     SDValue C63 = DAG.getConstant(63, MVT::i64);
02158     SDValue LL = Op.getOperand(0);
02159     SDValue RL = Op.getOperand(1);
02160     SDValue LH = DAG.getNode(ISD::SRA, DL, VT, LL, C63);
02161     SDValue RH = DAG.getNode(ISD::SRA, DL, VT, RL, C63);
02162     // UMUL_LOHI64 returns the low result in the odd register and the high
02163     // result in the even register.  SMUL_LOHI is defined to return the
02164     // low half first, so the results are in reverse order.
02165     lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, SystemZISD::UMUL_LOHI64,
02166                      LL, RL, Ops[1], Ops[0]);
02167     SDValue NegLLTimesRH = DAG.getNode(ISD::AND, DL, VT, LL, RH);
02168     SDValue NegLHTimesRL = DAG.getNode(ISD::AND, DL, VT, LH, RL);
02169     SDValue NegSum = DAG.getNode(ISD::ADD, DL, VT, NegLLTimesRH, NegLHTimesRL);
02170     Ops[1] = DAG.getNode(ISD::SUB, DL, VT, Ops[1], NegSum);
02171   }
02172   return DAG.getMergeValues(Ops, DL);
02173 }
02174 
02175 SDValue SystemZTargetLowering::lowerUMUL_LOHI(SDValue Op,
02176                                               SelectionDAG &DAG) const {
02177   EVT VT = Op.getValueType();
02178   SDLoc DL(Op);
02179   SDValue Ops[2];
02180   if (is32Bit(VT))
02181     // Just do a normal 64-bit multiplication and extract the results.
02182     // We define this so that it can be used for constant division.
02183     lowerMUL_LOHI32(DAG, DL, ISD::ZERO_EXTEND, Op.getOperand(0),
02184                     Op.getOperand(1), Ops[1], Ops[0]);
02185   else
02186     // UMUL_LOHI64 returns the low result in the odd register and the high
02187     // result in the even register.  UMUL_LOHI is defined to return the
02188     // low half first, so the results are in reverse order.
02189     lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, SystemZISD::UMUL_LOHI64,
02190                      Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
02191   return DAG.getMergeValues(Ops, DL);
02192 }
02193 
02194 SDValue SystemZTargetLowering::lowerSDIVREM(SDValue Op,
02195                                             SelectionDAG &DAG) const {
02196   SDValue Op0 = Op.getOperand(0);
02197   SDValue Op1 = Op.getOperand(1);
02198   EVT VT = Op.getValueType();
02199   SDLoc DL(Op);
02200   unsigned Opcode;
02201 
02202   // We use DSGF for 32-bit division.
02203   if (is32Bit(VT)) {
02204     Op0 = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, Op0);
02205     Opcode = SystemZISD::SDIVREM32;
02206   } else if (DAG.ComputeNumSignBits(Op1) > 32) {
02207     Op1 = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Op1);
02208     Opcode = SystemZISD::SDIVREM32;
02209   } else    
02210     Opcode = SystemZISD::SDIVREM64;
02211 
02212   // DSG(F) takes a 64-bit dividend, so the even register in the GR128
02213   // input is "don't care".  The instruction returns the remainder in
02214   // the even register and the quotient in the odd register.
02215   SDValue Ops[2];
02216   lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, Opcode,
02217                    Op0, Op1, Ops[1], Ops[0]);
02218   return DAG.getMergeValues(Ops, DL);
02219 }
02220 
02221 SDValue SystemZTargetLowering::lowerUDIVREM(SDValue Op,
02222                                             SelectionDAG &DAG) const {
02223   EVT VT = Op.getValueType();
02224   SDLoc DL(Op);
02225 
02226   // DL(G) uses a double-width dividend, so we need to clear the even
02227   // register in the GR128 input.  The instruction returns the remainder
02228   // in the even register and the quotient in the odd register.
02229   SDValue Ops[2];
02230   if (is32Bit(VT))
02231     lowerGR128Binary(DAG, DL, VT, SystemZ::ZEXT128_32, SystemZISD::UDIVREM32,
02232                      Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
02233   else
02234     lowerGR128Binary(DAG, DL, VT, SystemZ::ZEXT128_64, SystemZISD::UDIVREM64,
02235                      Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
02236   return DAG.getMergeValues(Ops, DL);
02237 }
02238 
02239 SDValue SystemZTargetLowering::lowerOR(SDValue Op, SelectionDAG &DAG) const {
02240   assert(Op.getValueType() == MVT::i64 && "Should be 64-bit operation");
02241 
02242   // Get the known-zero masks for each operand.
02243   SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1) };
02244   APInt KnownZero[2], KnownOne[2];
02245   DAG.computeKnownBits(Ops[0], KnownZero[0], KnownOne[0]);
02246   DAG.computeKnownBits(Ops[1], KnownZero[1], KnownOne[1]);
02247 
02248   // See if the upper 32 bits of one operand and the lower 32 bits of the
02249   // other are known zero.  They are the low and high operands respectively.
02250   uint64_t Masks[] = { KnownZero[0].getZExtValue(),
02251                        KnownZero[1].getZExtValue() };
02252   unsigned High, Low;
02253   if ((Masks[0] >> 32) == 0xffffffff && uint32_t(Masks[1]) == 0xffffffff)
02254     High = 1, Low = 0;
02255   else if ((Masks[1] >> 32) == 0xffffffff && uint32_t(Masks[0]) == 0xffffffff)
02256     High = 0, Low = 1;
02257   else
02258     return Op;
02259 
02260   SDValue LowOp = Ops[Low];
02261   SDValue HighOp = Ops[High];
02262 
02263   // If the high part is a constant, we're better off using IILH.
02264   if (HighOp.getOpcode() == ISD::Constant)
02265     return Op;
02266 
02267   // If the low part is a constant that is outside the range of LHI,
02268   // then we're better off using IILF.
02269   if (LowOp.getOpcode() == ISD::Constant) {
02270     int64_t Value = int32_t(cast<ConstantSDNode>(LowOp)->getZExtValue());
02271     if (!isInt<16>(Value))
02272       return Op;
02273   }
02274 
02275   // Check whether the high part is an AND that doesn't change the
02276   // high 32 bits and just masks out low bits.  We can skip it if so.
02277   if (HighOp.getOpcode() == ISD::AND &&
02278       HighOp.getOperand(1).getOpcode() == ISD::Constant) {
02279     SDValue HighOp0 = HighOp.getOperand(0);
02280     uint64_t Mask = cast<ConstantSDNode>(HighOp.getOperand(1))->getZExtValue();
02281     if (DAG.MaskedValueIsZero(HighOp0, APInt(64, ~(Mask | 0xffffffff))))
02282       HighOp = HighOp0;
02283   }
02284 
02285   // Take advantage of the fact that all GR32 operations only change the
02286   // low 32 bits by truncating Low to an i32 and inserting it directly
02287   // using a subreg.  The interesting cases are those where the truncation
02288   // can be folded.
02289   SDLoc DL(Op);
02290   SDValue Low32 = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, LowOp);
02291   return DAG.getTargetInsertSubreg(SystemZ::subreg_l32, DL,
02292                                    MVT::i64, HighOp, Low32);
02293 }
02294 
02295 // Op is an atomic load.  Lower it into a normal volatile load.
02296 SDValue SystemZTargetLowering::lowerATOMIC_LOAD(SDValue Op,
02297                                                 SelectionDAG &DAG) const {
02298   auto *Node = cast<AtomicSDNode>(Op.getNode());
02299   return DAG.getExtLoad(ISD::EXTLOAD, SDLoc(Op), Op.getValueType(),
02300                         Node->getChain(), Node->getBasePtr(),
02301                         Node->getMemoryVT(), Node->getMemOperand());
02302 }
02303 
02304 // Op is an atomic store.  Lower it into a normal volatile store followed
02305 // by a serialization.
02306 SDValue SystemZTargetLowering::lowerATOMIC_STORE(SDValue Op,
02307                                                  SelectionDAG &DAG) const {
02308   auto *Node = cast<AtomicSDNode>(Op.getNode());
02309   SDValue Chain = DAG.getTruncStore(Node->getChain(), SDLoc(Op), Node->getVal(),
02310                                     Node->getBasePtr(), Node->getMemoryVT(),
02311                                     Node->getMemOperand());
02312   return SDValue(DAG.getMachineNode(SystemZ::Serialize, SDLoc(Op), MVT::Other,
02313                                     Chain), 0);
02314 }
02315 
02316 // Op is an 8-, 16-bit or 32-bit ATOMIC_LOAD_* operation.  Lower the first
02317 // two into the fullword ATOMIC_LOADW_* operation given by Opcode.
02318 SDValue SystemZTargetLowering::lowerATOMIC_LOAD_OP(SDValue Op,
02319                                                    SelectionDAG &DAG,
02320                                                    unsigned Opcode) const {
02321   auto *Node = cast<AtomicSDNode>(Op.getNode());
02322 
02323   // 32-bit operations need no code outside the main loop.
02324   EVT NarrowVT = Node->getMemoryVT();
02325   EVT WideVT = MVT::i32;
02326   if (NarrowVT == WideVT)
02327     return Op;
02328 
02329   int64_t BitSize = NarrowVT.getSizeInBits();
02330   SDValue ChainIn = Node->getChain();
02331   SDValue Addr = Node->getBasePtr();
02332   SDValue Src2 = Node->getVal();
02333   MachineMemOperand *MMO = Node->getMemOperand();
02334   SDLoc DL(Node);
02335   EVT PtrVT = Addr.getValueType();
02336 
02337   // Convert atomic subtracts of constants into additions.
02338   if (Opcode == SystemZISD::ATOMIC_LOADW_SUB)
02339     if (auto *Const = dyn_cast<ConstantSDNode>(Src2)) {
02340       Opcode = SystemZISD::ATOMIC_LOADW_ADD;
02341       Src2 = DAG.getConstant(-Const->getSExtValue(), Src2.getValueType());
02342     }
02343 
02344   // Get the address of the containing word.
02345   SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr,
02346                                     DAG.getConstant(-4, PtrVT));
02347 
02348   // Get the number of bits that the word must be rotated left in order
02349   // to bring the field to the top bits of a GR32.
02350   SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr,
02351                                  DAG.getConstant(3, PtrVT));
02352   BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift);
02353 
02354   // Get the complementing shift amount, for rotating a field in the top
02355   // bits back to its proper position.
02356   SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT,
02357                                     DAG.getConstant(0, WideVT), BitShift);
02358 
02359   // Extend the source operand to 32 bits and prepare it for the inner loop.
02360   // ATOMIC_SWAPW uses RISBG to rotate the field left, but all other
02361   // operations require the source to be shifted in advance.  (This shift
02362   // can be folded if the source is constant.)  For AND and NAND, the lower
02363   // bits must be set, while for other opcodes they should be left clear.
02364   if (Opcode != SystemZISD::ATOMIC_SWAPW)
02365     Src2 = DAG.getNode(ISD::SHL, DL, WideVT, Src2,
02366                        DAG.getConstant(32 - BitSize, WideVT));
02367   if (Opcode == SystemZISD::ATOMIC_LOADW_AND ||
02368       Opcode == SystemZISD::ATOMIC_LOADW_NAND)
02369     Src2 = DAG.getNode(ISD::OR, DL, WideVT, Src2,
02370                        DAG.getConstant(uint32_t(-1) >> BitSize, WideVT));
02371 
02372   // Construct the ATOMIC_LOADW_* node.
02373   SDVTList VTList = DAG.getVTList(WideVT, MVT::Other);
02374   SDValue Ops[] = { ChainIn, AlignedAddr, Src2, BitShift, NegBitShift,
02375                     DAG.getConstant(BitSize, WideVT) };
02376   SDValue AtomicOp = DAG.getMemIntrinsicNode(Opcode, DL, VTList, Ops,
02377                                              NarrowVT, MMO);
02378 
02379   // Rotate the result of the final CS so that the field is in the lower
02380   // bits of a GR32, then truncate it.
02381   SDValue ResultShift = DAG.getNode(ISD::ADD, DL, WideVT, BitShift,
02382                                     DAG.getConstant(BitSize, WideVT));
02383   SDValue Result = DAG.getNode(ISD::ROTL, DL, WideVT, AtomicOp, ResultShift);
02384 
02385   SDValue RetOps[2] = { Result, AtomicOp.getValue(1) };
02386   return DAG.getMergeValues(RetOps, DL);
02387 }
02388 
02389 // Op is an ATOMIC_LOAD_SUB operation.  Lower 8- and 16-bit operations
02390 // into ATOMIC_LOADW_SUBs and decide whether to convert 32- and 64-bit
02391 // operations into additions.
02392 SDValue SystemZTargetLowering::lowerATOMIC_LOAD_SUB(SDValue Op,
02393                                                     SelectionDAG &DAG) const {
02394   auto *Node = cast<AtomicSDNode>(Op.getNode());
02395   EVT MemVT = Node->getMemoryVT();
02396   if (MemVT == MVT::i32 || MemVT == MVT::i64) {
02397     // A full-width operation.
02398     assert(Op.getValueType() == MemVT && "Mismatched VTs");
02399     SDValue Src2 = Node->getVal();
02400     SDValue NegSrc2;
02401     SDLoc DL(Src2);
02402 
02403     if (auto *Op2 = dyn_cast<ConstantSDNode>(Src2)) {
02404       // Use an addition if the operand is constant and either LAA(G) is
02405       // available or the negative value is in the range of A(G)FHI.
02406       int64_t Value = (-Op2->getAPIntValue()).getSExtValue();
02407       if (isInt<32>(Value) || Subtarget.hasInterlockedAccess1())
02408         NegSrc2 = DAG.getConstant(Value, MemVT);
02409     } else if (Subtarget.hasInterlockedAccess1())
02410       // Use LAA(G) if available.
02411       NegSrc2 = DAG.getNode(ISD::SUB, DL, MemVT, DAG.getConstant(0, MemVT),
02412                             Src2);
02413 
02414     if (NegSrc2.getNode())
02415       return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, DL, MemVT,
02416                            Node->getChain(), Node->getBasePtr(), NegSrc2,
02417                            Node->getMemOperand(), Node->getOrdering(),
02418                            Node->getSynchScope());
02419 
02420     // Use the node as-is.
02421     return Op;
02422   }
02423 
02424   return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_SUB);
02425 }
02426 
02427 // Node is an 8- or 16-bit ATOMIC_CMP_SWAP operation.  Lower the first two
02428 // into a fullword ATOMIC_CMP_SWAPW operation.
02429 SDValue SystemZTargetLowering::lowerATOMIC_CMP_SWAP(SDValue Op,
02430                                                     SelectionDAG &DAG) const {
02431   auto *Node = cast<AtomicSDNode>(Op.getNode());
02432 
02433   // We have native support for 32-bit compare and swap.
02434   EVT NarrowVT = Node->getMemoryVT();
02435   EVT WideVT = MVT::i32;
02436   if (NarrowVT == WideVT)
02437     return Op;
02438 
02439   int64_t BitSize = NarrowVT.getSizeInBits();
02440   SDValue ChainIn = Node->getOperand(0);
02441   SDValue Addr = Node->getOperand(1);
02442   SDValue CmpVal = Node->getOperand(2);
02443   SDValue SwapVal = Node->getOperand(3);
02444   MachineMemOperand *MMO = Node->getMemOperand();
02445   SDLoc DL(Node);
02446   EVT PtrVT = Addr.getValueType();
02447 
02448   // Get the address of the containing word.
02449   SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr,
02450                                     DAG.getConstant(-4, PtrVT));
02451 
02452   // Get the number of bits that the word must be rotated left in order
02453   // to bring the field to the top bits of a GR32.
02454   SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr,
02455                                  DAG.getConstant(3, PtrVT));
02456   BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift);
02457 
02458   // Get the complementing shift amount, for rotating a field in the top
02459   // bits back to its proper position.
02460   SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT,
02461                                     DAG.getConstant(0, WideVT), BitShift);
02462 
02463   // Construct the ATOMIC_CMP_SWAPW node.
02464   SDVTList VTList = DAG.getVTList(WideVT, MVT::Other);
02465   SDValue Ops[] = { ChainIn, AlignedAddr, CmpVal, SwapVal, BitShift,
02466                     NegBitShift, DAG.getConstant(BitSize, WideVT) };
02467   SDValue AtomicOp = DAG.getMemIntrinsicNode(SystemZISD::ATOMIC_CMP_SWAPW, DL,
02468                                              VTList, Ops, NarrowVT, MMO);
02469   return AtomicOp;
02470 }
02471 
02472 SDValue SystemZTargetLowering::lowerSTACKSAVE(SDValue Op,
02473                                               SelectionDAG &DAG) const {
02474   MachineFunction &MF = DAG.getMachineFunction();
02475   MF.getInfo<SystemZMachineFunctionInfo>()->setManipulatesSP(true);
02476   return DAG.getCopyFromReg(Op.getOperand(0), SDLoc(Op),
02477                             SystemZ::R15D, Op.getValueType());
02478 }
02479 
02480 SDValue SystemZTargetLowering::lowerSTACKRESTORE(SDValue Op,
02481                                                  SelectionDAG &DAG) const {
02482   MachineFunction &MF = DAG.getMachineFunction();
02483   MF.getInfo<SystemZMachineFunctionInfo>()->setManipulatesSP(true);
02484   return DAG.getCopyToReg(Op.getOperand(0), SDLoc(Op),
02485                           SystemZ::R15D, Op.getOperand(1));
02486 }
02487 
02488 SDValue SystemZTargetLowering::lowerPREFETCH(SDValue Op,
02489                                              SelectionDAG &DAG) const {
02490   bool IsData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
02491   if (!IsData)
02492     // Just preserve the chain.
02493     return Op.getOperand(0);
02494 
02495   bool IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
02496   unsigned Code = IsWrite ? SystemZ::PFD_WRITE : SystemZ::PFD_READ;
02497   auto *Node = cast<MemIntrinsicSDNode>(Op.getNode());
02498   SDValue Ops[] = {
02499     Op.getOperand(0),
02500     DAG.getConstant(Code, MVT::i32),
02501     Op.getOperand(1)
02502   };
02503   return DAG.getMemIntrinsicNode(SystemZISD::PREFETCH, SDLoc(Op),
02504                                  Node->getVTList(), Ops,
02505                                  Node->getMemoryVT(), Node->getMemOperand());
02506 }
02507 
02508 SDValue SystemZTargetLowering::LowerOperation(SDValue Op,
02509                                               SelectionDAG &DAG) const {
02510   switch (Op.getOpcode()) {
02511   case ISD::BR_CC:
02512     return lowerBR_CC(Op, DAG);
02513   case ISD::SELECT_CC:
02514     return lowerSELECT_CC(Op, DAG);
02515   case ISD::SETCC:
02516     return lowerSETCC(Op, DAG);
02517   case ISD::GlobalAddress:
02518     return lowerGlobalAddress(cast<GlobalAddressSDNode>(Op), DAG);
02519   case ISD::GlobalTLSAddress:
02520     return lowerGlobalTLSAddress(cast<GlobalAddressSDNode>(Op), DAG);
02521   case ISD::BlockAddress:
02522     return lowerBlockAddress(cast<BlockAddressSDNode>(Op), DAG);
02523   case ISD::JumpTable:
02524     return lowerJumpTable(cast<JumpTableSDNode>(Op), DAG);
02525   case ISD::ConstantPool:
02526     return lowerConstantPool(cast<ConstantPoolSDNode>(Op), DAG);
02527   case ISD::BITCAST:
02528     return lowerBITCAST(Op, DAG);
02529   case ISD::VASTART:
02530     return lowerVASTART(Op, DAG);
02531   case ISD::VACOPY:
02532     return lowerVACOPY(Op, DAG);
02533   case ISD::DYNAMIC_STACKALLOC:
02534     return lowerDYNAMIC_STACKALLOC(Op, DAG);
02535   case ISD::SMUL_LOHI:
02536     return lowerSMUL_LOHI(Op, DAG);
02537   case ISD::UMUL_LOHI:
02538     return lowerUMUL_LOHI(Op, DAG);
02539   case ISD::SDIVREM:
02540     return lowerSDIVREM(Op, DAG);
02541   case ISD::UDIVREM:
02542     return lowerUDIVREM(Op, DAG);
02543   case ISD::OR:
02544     return lowerOR(Op, DAG);
02545   case ISD::ATOMIC_SWAP:
02546     return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_SWAPW);
02547   case ISD::ATOMIC_STORE:
02548     return lowerATOMIC_STORE(Op, DAG);
02549   case ISD::ATOMIC_LOAD:
02550     return lowerATOMIC_LOAD(Op, DAG);
02551   case ISD::ATOMIC_LOAD_ADD:
02552     return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_ADD);
02553   case ISD::ATOMIC_LOAD_SUB:
02554     return lowerATOMIC_LOAD_SUB(Op, DAG);
02555   case ISD::ATOMIC_LOAD_AND:
02556     return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_AND);
02557   case ISD::ATOMIC_LOAD_OR:
02558     return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_OR);
02559   case ISD::ATOMIC_LOAD_XOR:
02560     return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_XOR);
02561   case ISD::ATOMIC_LOAD_NAND:
02562     return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_NAND);
02563   case ISD::ATOMIC_LOAD_MIN:
02564     return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_MIN);
02565   case ISD::ATOMIC_LOAD_MAX:
02566     return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_MAX);
02567   case ISD::ATOMIC_LOAD_UMIN:
02568     return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_UMIN);
02569   case ISD::ATOMIC_LOAD_UMAX:
02570     return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_UMAX);
02571   case ISD::ATOMIC_CMP_SWAP:
02572     return lowerATOMIC_CMP_SWAP(Op, DAG);
02573   case ISD::STACKSAVE:
02574     return lowerSTACKSAVE(Op, DAG);
02575   case ISD::STACKRESTORE:
02576     return lowerSTACKRESTORE(Op, DAG);
02577   case ISD::PREFETCH:
02578     return lowerPREFETCH(Op, DAG);
02579   default:
02580     llvm_unreachable("Unexpected node to lower");
02581   }
02582 }
02583 
02584 const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const {
02585 #define OPCODE(NAME) case SystemZISD::NAME: return "SystemZISD::" #NAME
02586   switch (Opcode) {
02587     OPCODE(RET_FLAG);
02588     OPCODE(CALL);
02589     OPCODE(SIBCALL);
02590     OPCODE(PCREL_WRAPPER);
02591     OPCODE(PCREL_OFFSET);
02592     OPCODE(IABS);
02593     OPCODE(ICMP);
02594     OPCODE(FCMP);
02595     OPCODE(TM);
02596     OPCODE(BR_CCMASK);
02597     OPCODE(SELECT_CCMASK);
02598     OPCODE(ADJDYNALLOC);
02599     OPCODE(EXTRACT_ACCESS);
02600     OPCODE(UMUL_LOHI64);
02601     OPCODE(SDIVREM64);
02602     OPCODE(UDIVREM32);
02603     OPCODE(UDIVREM64);
02604     OPCODE(MVC);
02605     OPCODE(MVC_LOOP);
02606     OPCODE(NC);
02607     OPCODE(NC_LOOP);
02608     OPCODE(OC);
02609     OPCODE(OC_LOOP);
02610     OPCODE(XC);
02611     OPCODE(XC_LOOP);
02612     OPCODE(CLC);
02613     OPCODE(CLC_LOOP);
02614     OPCODE(STRCMP);
02615     OPCODE(STPCPY);
02616     OPCODE(SEARCH_STRING);
02617     OPCODE(IPM);
02618     OPCODE(SERIALIZE);
02619     OPCODE(ATOMIC_SWAPW);
02620     OPCODE(ATOMIC_LOADW_ADD);
02621     OPCODE(ATOMIC_LOADW_SUB);
02622     OPCODE(ATOMIC_LOADW_AND);
02623     OPCODE(ATOMIC_LOADW_OR);
02624     OPCODE(ATOMIC_LOADW_XOR);
02625     OPCODE(ATOMIC_LOADW_NAND);
02626     OPCODE(ATOMIC_LOADW_MIN);
02627     OPCODE(ATOMIC_LOADW_MAX);
02628     OPCODE(ATOMIC_LOADW_UMIN);
02629     OPCODE(ATOMIC_LOADW_UMAX);
02630     OPCODE(ATOMIC_CMP_SWAPW);
02631     OPCODE(PREFETCH);
02632   }
02633   return nullptr;
02634 #undef OPCODE
02635 }
02636 
02637 SDValue SystemZTargetLowering::PerformDAGCombine(SDNode *N,
02638                                                  DAGCombinerInfo &DCI) const {
02639   SelectionDAG &DAG = DCI.DAG;
02640   unsigned Opcode = N->getOpcode();
02641   if (Opcode == ISD::SIGN_EXTEND) {
02642     // Convert (sext (ashr (shl X, C1), C2)) to
02643     // (ashr (shl (anyext X), C1'), C2')), since wider shifts are as
02644     // cheap as narrower ones.
02645     SDValue N0 = N->getOperand(0);
02646     EVT VT = N->getValueType(0);
02647     if (N0.hasOneUse() && N0.getOpcode() == ISD::SRA) {
02648       auto *SraAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1));
02649       SDValue Inner = N0.getOperand(0);
02650       if (SraAmt && Inner.hasOneUse() && Inner.getOpcode() == ISD::SHL) {
02651         if (auto *ShlAmt = dyn_cast<ConstantSDNode>(Inner.getOperand(1))) {
02652           unsigned Extra = (VT.getSizeInBits() -
02653                             N0.getValueType().getSizeInBits());
02654           unsigned NewShlAmt = ShlAmt->getZExtValue() + Extra;
02655           unsigned NewSraAmt = SraAmt->getZExtValue() + Extra;
02656           EVT ShiftVT = N0.getOperand(1).getValueType();
02657           SDValue Ext = DAG.getNode(ISD::ANY_EXTEND, SDLoc(Inner), VT,
02658                                     Inner.getOperand(0));
02659           SDValue Shl = DAG.getNode(ISD::SHL, SDLoc(Inner), VT, Ext,
02660                                     DAG.getConstant(NewShlAmt, ShiftVT));
02661           return DAG.getNode(ISD::SRA, SDLoc(N0), VT, Shl,
02662                              DAG.getConstant(NewSraAmt, ShiftVT));
02663         }
02664       }
02665     }
02666   }
02667   return SDValue();
02668 }
02669 
02670 //===----------------------------------------------------------------------===//
02671 // Custom insertion
02672 //===----------------------------------------------------------------------===//
02673 
02674 // Create a new basic block after MBB.
02675 static MachineBasicBlock *emitBlockAfter(MachineBasicBlock *MBB) {
02676   MachineFunction &MF = *MBB->getParent();
02677   MachineBasicBlock *NewMBB = MF.CreateMachineBasicBlock(MBB->getBasicBlock());
02678   MF.insert(std::next(MachineFunction::iterator(MBB)), NewMBB);
02679   return NewMBB;
02680 }
02681 
02682 // Split MBB after MI and return the new block (the one that contains
02683 // instructions after MI).
02684 static MachineBasicBlock *splitBlockAfter(MachineInstr *MI,
02685                                           MachineBasicBlock *MBB) {
02686   MachineBasicBlock *NewMBB = emitBlockAfter(MBB);
02687   NewMBB->splice(NewMBB->begin(), MBB,
02688                  std::next(MachineBasicBlock::iterator(MI)), MBB->end());
02689   NewMBB->transferSuccessorsAndUpdatePHIs(MBB);
02690   return NewMBB;
02691 }
02692 
02693 // Split MBB before MI and return the new block (the one that contains MI).
02694 static MachineBasicBlock *splitBlockBefore(MachineInstr *MI,
02695                                            MachineBasicBlock *MBB) {
02696   MachineBasicBlock *NewMBB = emitBlockAfter(MBB);
02697   NewMBB->splice(NewMBB->begin(), MBB, MI, MBB->end());
02698   NewMBB->transferSuccessorsAndUpdatePHIs(MBB);
02699   return NewMBB;
02700 }
02701 
02702 // Force base value Base into a register before MI.  Return the register.
02703 static unsigned forceReg(MachineInstr *MI, MachineOperand &Base,
02704                          const SystemZInstrInfo *TII) {
02705   if (Base.isReg())
02706     return Base.getReg();
02707 
02708   MachineBasicBlock *MBB = MI->getParent();
02709   MachineFunction &MF = *MBB->getParent();
02710   MachineRegisterInfo &MRI = MF.getRegInfo();
02711 
02712   unsigned Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
02713   BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(SystemZ::LA), Reg)
02714     .addOperand(Base).addImm(0).addReg(0);
02715   return Reg;
02716 }
02717 
02718 // Implement EmitInstrWithCustomInserter for pseudo Select* instruction MI.
02719 MachineBasicBlock *
02720 SystemZTargetLowering::emitSelect(MachineInstr *MI,
02721                                   MachineBasicBlock *MBB) const {
02722   const SystemZInstrInfo *TII =
02723       static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
02724 
02725   unsigned DestReg  = MI->getOperand(0).getReg();
02726   unsigned TrueReg  = MI->getOperand(1).getReg();
02727   unsigned FalseReg = MI->getOperand(2).getReg();
02728   unsigned CCValid  = MI->getOperand(3).getImm();
02729   unsigned CCMask   = MI->getOperand(4).getImm();
02730   DebugLoc DL       = MI->getDebugLoc();
02731 
02732   MachineBasicBlock *StartMBB = MBB;
02733   MachineBasicBlock *JoinMBB  = splitBlockBefore(MI, MBB);
02734   MachineBasicBlock *FalseMBB = emitBlockAfter(StartMBB);
02735 
02736   //  StartMBB:
02737   //   BRC CCMask, JoinMBB
02738   //   # fallthrough to FalseMBB
02739   MBB = StartMBB;
02740   BuildMI(MBB, DL, TII->get(SystemZ::BRC))
02741     .addImm(CCValid).addImm(CCMask).addMBB(JoinMBB);
02742   MBB->addSuccessor(JoinMBB);
02743   MBB->addSuccessor(FalseMBB);
02744 
02745   //  FalseMBB:
02746   //   # fallthrough to JoinMBB
02747   MBB = FalseMBB;
02748   MBB->addSuccessor(JoinMBB);
02749 
02750   //  JoinMBB:
02751   //   %Result = phi [ %FalseReg, FalseMBB ], [ %TrueReg, StartMBB ]
02752   //  ...
02753   MBB = JoinMBB;
02754   BuildMI(*MBB, MI, DL, TII->get(SystemZ::PHI), DestReg)
02755     .addReg(TrueReg).addMBB(StartMBB)
02756     .addReg(FalseReg).addMBB(FalseMBB);
02757 
02758   MI->eraseFromParent();
02759   return JoinMBB;
02760 }
02761 
02762 // Implement EmitInstrWithCustomInserter for pseudo CondStore* instruction MI.
02763 // StoreOpcode is the store to use and Invert says whether the store should
02764 // happen when the condition is false rather than true.  If a STORE ON
02765 // CONDITION is available, STOCOpcode is its opcode, otherwise it is 0.
02766 MachineBasicBlock *
02767 SystemZTargetLowering::emitCondStore(MachineInstr *MI,
02768                                      MachineBasicBlock *MBB,
02769                                      unsigned StoreOpcode, unsigned STOCOpcode,
02770                                      bool Invert) const {
02771   const SystemZInstrInfo *TII =
02772       static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
02773 
02774   unsigned SrcReg     = MI->getOperand(0).getReg();
02775   MachineOperand Base = MI->getOperand(1);
02776   int64_t Disp        = MI->getOperand(2).getImm();
02777   unsigned IndexReg   = MI->getOperand(3).getReg();
02778   unsigned CCValid    = MI->getOperand(4).getImm();
02779   unsigned CCMask     = MI->getOperand(5).getImm();
02780   DebugLoc DL         = MI->getDebugLoc();
02781 
02782   StoreOpcode = TII->getOpcodeForOffset(StoreOpcode, Disp);
02783 
02784   // Use STOCOpcode if possible.  We could use different store patterns in
02785   // order to avoid matching the index register, but the performance trade-offs
02786   // might be more complicated in that case.
02787   if (STOCOpcode && !IndexReg && Subtarget.hasLoadStoreOnCond()) {
02788     if (Invert)
02789       CCMask ^= CCValid;
02790     BuildMI(*MBB, MI, DL, TII->get(STOCOpcode))
02791       .addReg(SrcReg).addOperand(Base).addImm(Disp)
02792       .addImm(CCValid).addImm(CCMask);
02793     MI->eraseFromParent();
02794     return MBB;
02795   }
02796 
02797   // Get the condition needed to branch around the store.
02798   if (!Invert)
02799     CCMask ^= CCValid;
02800 
02801   MachineBasicBlock *StartMBB = MBB;
02802   MachineBasicBlock *JoinMBB  = splitBlockBefore(MI, MBB);
02803   MachineBasicBlock *FalseMBB = emitBlockAfter(StartMBB);
02804 
02805   //  StartMBB:
02806   //   BRC CCMask, JoinMBB
02807   //   # fallthrough to FalseMBB
02808   MBB = StartMBB;
02809   BuildMI(MBB, DL, TII->get(SystemZ::BRC))
02810     .addImm(CCValid).addImm(CCMask).addMBB(JoinMBB);
02811   MBB->addSuccessor(JoinMBB);
02812   MBB->addSuccessor(FalseMBB);
02813 
02814   //  FalseMBB:
02815   //   store %SrcReg, %Disp(%Index,%Base)
02816   //   # fallthrough to JoinMBB
02817   MBB = FalseMBB;
02818   BuildMI(MBB, DL, TII->get(StoreOpcode))
02819     .addReg(SrcReg).addOperand(Base).addImm(Disp).addReg(IndexReg);
02820   MBB->addSuccessor(JoinMBB);
02821 
02822   MI->eraseFromParent();
02823   return JoinMBB;
02824 }
02825 
02826 // Implement EmitInstrWithCustomInserter for pseudo ATOMIC_LOAD{,W}_*
02827 // or ATOMIC_SWAP{,W} instruction MI.  BinOpcode is the instruction that
02828 // performs the binary operation elided by "*", or 0 for ATOMIC_SWAP{,W}.
02829 // BitSize is the width of the field in bits, or 0 if this is a partword
02830 // ATOMIC_LOADW_* or ATOMIC_SWAPW instruction, in which case the bitsize
02831 // is one of the operands.  Invert says whether the field should be
02832 // inverted after performing BinOpcode (e.g. for NAND).
02833 MachineBasicBlock *
02834 SystemZTargetLowering::emitAtomicLoadBinary(MachineInstr *MI,
02835                                             MachineBasicBlock *MBB,
02836                                             unsigned BinOpcode,
02837                                             unsigned BitSize,
02838                                             bool Invert) const {
02839   MachineFunction &MF = *MBB->getParent();
02840   const SystemZInstrInfo *TII =
02841       static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
02842   MachineRegisterInfo &MRI = MF.getRegInfo();
02843   bool IsSubWord = (BitSize < 32);
02844 
02845   // Extract the operands.  Base can be a register or a frame index.
02846   // Src2 can be a register or immediate.
02847   unsigned Dest        = MI->getOperand(0).getReg();
02848   MachineOperand Base  = earlyUseOperand(MI->getOperand(1));
02849   int64_t Disp         = MI->getOperand(2).getImm();
02850   MachineOperand Src2  = earlyUseOperand(MI->getOperand(3));
02851   unsigned BitShift    = (IsSubWord ? MI->getOperand(4).getReg() : 0);
02852   unsigned NegBitShift = (IsSubWord ? MI->getOperand(5).getReg() : 0);
02853   DebugLoc DL          = MI->getDebugLoc();
02854   if (IsSubWord)
02855     BitSize = MI->getOperand(6).getImm();
02856 
02857   // Subword operations use 32-bit registers.
02858   const TargetRegisterClass *RC = (BitSize <= 32 ?
02859                                    &SystemZ::GR32BitRegClass :
02860                                    &SystemZ::GR64BitRegClass);
02861   unsigned LOpcode  = BitSize <= 32 ? SystemZ::L  : SystemZ::LG;
02862   unsigned CSOpcode = BitSize <= 32 ? SystemZ::CS : SystemZ::CSG;
02863 
02864   // Get the right opcodes for the displacement.
02865   LOpcode  = TII->getOpcodeForOffset(LOpcode,  Disp);
02866   CSOpcode = TII->getOpcodeForOffset(CSOpcode, Disp);
02867   assert(LOpcode && CSOpcode && "Displacement out of range");
02868 
02869   // Create virtual registers for temporary results.
02870   unsigned OrigVal       = MRI.createVirtualRegister(RC);
02871   unsigned OldVal        = MRI.createVirtualRegister(RC);
02872   unsigned NewVal        = (BinOpcode || IsSubWord ?
02873                             MRI.createVirtualRegister(RC) : Src2.getReg());
02874   unsigned RotatedOldVal = (IsSubWord ? MRI.createVirtualRegister(RC) : OldVal);
02875   unsigned RotatedNewVal = (IsSubWord ? MRI.createVirtualRegister(RC) : NewVal);
02876 
02877   // Insert a basic block for the main loop.
02878   MachineBasicBlock *StartMBB = MBB;
02879   MachineBasicBlock *DoneMBB  = splitBlockBefore(MI, MBB);
02880   MachineBasicBlock *LoopMBB  = emitBlockAfter(StartMBB);
02881 
02882   //  StartMBB:
02883   //   ...
02884   //   %OrigVal = L Disp(%Base)
02885   //   # fall through to LoopMMB
02886   MBB = StartMBB;
02887   BuildMI(MBB, DL, TII->get(LOpcode), OrigVal)
02888     .addOperand(Base).addImm(Disp).addReg(0);
02889   MBB->addSuccessor(LoopMBB);
02890 
02891   //  LoopMBB:
02892   //   %OldVal        = phi [ %OrigVal, StartMBB ], [ %Dest, LoopMBB ]
02893   //   %RotatedOldVal = RLL %OldVal, 0(%BitShift)
02894   //   %RotatedNewVal = OP %RotatedOldVal, %Src2
02895   //   %NewVal        = RLL %RotatedNewVal, 0(%NegBitShift)
02896   //   %Dest          = CS %OldVal, %NewVal, Disp(%Base)
02897   //   JNE LoopMBB
02898   //   # fall through to DoneMMB
02899   MBB = LoopMBB;
02900   BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
02901     .addReg(OrigVal).addMBB(StartMBB)
02902     .addReg(Dest).addMBB(LoopMBB);
02903   if (IsSubWord)
02904     BuildMI(MBB, DL, TII->get(SystemZ::RLL), RotatedOldVal)
02905       .addReg(OldVal).addReg(BitShift).addImm(0);
02906   if (Invert) {
02907     // Perform the operation normally and then invert every bit of the field.
02908     unsigned Tmp = MRI.createVirtualRegister(RC);
02909     BuildMI(MBB, DL, TII->get(BinOpcode), Tmp)
02910       .addReg(RotatedOldVal).addOperand(Src2);
02911     if (BitSize <= 32)
02912       // XILF with the upper BitSize bits set.
02913       BuildMI(MBB, DL, TII->get(SystemZ::XILF), RotatedNewVal)
02914         .addReg(Tmp).addImm(-1U << (32 - BitSize));
02915     else {
02916       // Use LCGR and add -1 to the result, which is more compact than
02917       // an XILF, XILH pair.
02918       unsigned Tmp2 = MRI.createVirtualRegister(RC);
02919       BuildMI(MBB, DL, TII->get(SystemZ::LCGR), Tmp2).addReg(Tmp);
02920       BuildMI(MBB, DL, TII->get(SystemZ::AGHI), RotatedNewVal)
02921         .addReg(Tmp2).addImm(-1);
02922     }
02923   } else if (BinOpcode)
02924     // A simply binary operation.
02925     BuildMI(MBB, DL, TII->get(BinOpcode), RotatedNewVal)
02926       .addReg(RotatedOldVal).addOperand(Src2);
02927   else if (IsSubWord)
02928     // Use RISBG to rotate Src2 into position and use it to replace the
02929     // field in RotatedOldVal.
02930     BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RotatedNewVal)
02931       .addReg(RotatedOldVal).addReg(Src2.getReg())
02932       .addImm(32).addImm(31 + BitSize).addImm(32 - BitSize);
02933   if (IsSubWord)
02934     BuildMI(MBB, DL, TII->get(SystemZ::RLL), NewVal)
02935       .addReg(RotatedNewVal).addReg(NegBitShift).addImm(0);
02936   BuildMI(MBB, DL, TII->get(CSOpcode), Dest)
02937     .addReg(OldVal).addReg(NewVal).addOperand(Base).addImm(Disp);
02938   BuildMI(MBB, DL, TII->get(SystemZ::BRC))
02939     .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
02940   MBB->addSuccessor(LoopMBB);
02941   MBB->addSuccessor(DoneMBB);
02942 
02943   MI->eraseFromParent();
02944   return DoneMBB;
02945 }
02946 
02947 // Implement EmitInstrWithCustomInserter for pseudo
02948 // ATOMIC_LOAD{,W}_{,U}{MIN,MAX} instruction MI.  CompareOpcode is the
02949 // instruction that should be used to compare the current field with the
02950 // minimum or maximum value.  KeepOldMask is the BRC condition-code mask
02951 // for when the current field should be kept.  BitSize is the width of
02952 // the field in bits, or 0 if this is a partword ATOMIC_LOADW_* instruction.
02953 MachineBasicBlock *
02954 SystemZTargetLowering::emitAtomicLoadMinMax(MachineInstr *MI,
02955                                             MachineBasicBlock *MBB,
02956                                             unsigned CompareOpcode,
02957                                             unsigned KeepOldMask,
02958                                             unsigned BitSize) const {
02959   MachineFunction &MF = *MBB->getParent();
02960   const SystemZInstrInfo *TII =
02961       static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
02962   MachineRegisterInfo &MRI = MF.getRegInfo();
02963   bool IsSubWord = (BitSize < 32);
02964 
02965   // Extract the operands.  Base can be a register or a frame index.
02966   unsigned Dest        = MI->getOperand(0).getReg();
02967   MachineOperand Base  = earlyUseOperand(MI->getOperand(1));
02968   int64_t  Disp        = MI->getOperand(2).getImm();
02969   unsigned Src2        = MI->getOperand(3).getReg();
02970   unsigned BitShift    = (IsSubWord ? MI->getOperand(4).getReg() : 0);
02971   unsigned NegBitShift = (IsSubWord ? MI->getOperand(5).getReg() : 0);
02972   DebugLoc DL          = MI->getDebugLoc();
02973   if (IsSubWord)
02974     BitSize = MI->getOperand(6).getImm();
02975 
02976   // Subword operations use 32-bit registers.
02977   const TargetRegisterClass *RC = (BitSize <= 32 ?
02978                                    &SystemZ::GR32BitRegClass :
02979                                    &SystemZ::GR64BitRegClass);
02980   unsigned LOpcode  = BitSize <= 32 ? SystemZ::L  : SystemZ::LG;
02981   unsigned CSOpcode = BitSize <= 32 ? SystemZ::CS : SystemZ::CSG;
02982 
02983   // Get the right opcodes for the displacement.
02984   LOpcode  = TII->getOpcodeForOffset(LOpcode,  Disp);
02985   CSOpcode = TII->getOpcodeForOffset(CSOpcode, Disp);
02986   assert(LOpcode && CSOpcode && "Displacement out of range");
02987 
02988   // Create virtual registers for temporary results.
02989   unsigned OrigVal       = MRI.createVirtualRegister(RC);
02990   unsigned OldVal        = MRI.createVirtualRegister(RC);
02991   unsigned NewVal        = MRI.createVirtualRegister(RC);
02992   unsigned RotatedOldVal = (IsSubWord ? MRI.createVirtualRegister(RC) : OldVal);
02993   unsigned RotatedAltVal = (IsSubWord ? MRI.createVirtualRegister(RC) : Src2);
02994   unsigned RotatedNewVal = (IsSubWord ? MRI.createVirtualRegister(RC) : NewVal);
02995 
02996   // Insert 3 basic blocks for the loop.
02997   MachineBasicBlock *StartMBB  = MBB;
02998   MachineBasicBlock *DoneMBB   = splitBlockBefore(MI, MBB);
02999   MachineBasicBlock *LoopMBB   = emitBlockAfter(StartMBB);
03000   MachineBasicBlock *UseAltMBB = emitBlockAfter(LoopMBB);
03001   MachineBasicBlock *UpdateMBB = emitBlockAfter(UseAltMBB);
03002 
03003   //  StartMBB:
03004   //   ...
03005   //   %OrigVal     = L Disp(%Base)
03006   //   # fall through to LoopMMB
03007   MBB = StartMBB;
03008   BuildMI(MBB, DL, TII->get(LOpcode), OrigVal)
03009     .addOperand(Base).addImm(Disp).addReg(0);
03010   MBB->addSuccessor(LoopMBB);
03011 
03012   //  LoopMBB:
03013   //   %OldVal        = phi [ %OrigVal, StartMBB ], [ %Dest, UpdateMBB ]
03014   //   %RotatedOldVal = RLL %OldVal, 0(%BitShift)
03015   //   CompareOpcode %RotatedOldVal, %Src2
03016   //   BRC KeepOldMask, UpdateMBB
03017   MBB = LoopMBB;
03018   BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
03019     .addReg(OrigVal).addMBB(StartMBB)
03020     .addReg(Dest).addMBB(UpdateMBB);
03021   if (IsSubWord)
03022     BuildMI(MBB, DL, TII->get(SystemZ::RLL), RotatedOldVal)
03023       .addReg(OldVal).addReg(BitShift).addImm(0);
03024   BuildMI(MBB, DL, TII->get(CompareOpcode))
03025     .addReg(RotatedOldVal).addReg(Src2);
03026   BuildMI(MBB, DL, TII->get(SystemZ::BRC))
03027     .addImm(SystemZ::CCMASK_ICMP).addImm(KeepOldMask).addMBB(UpdateMBB);
03028   MBB->addSuccessor(UpdateMBB);
03029   MBB->addSuccessor(UseAltMBB);
03030 
03031   //  UseAltMBB:
03032   //   %RotatedAltVal = RISBG %RotatedOldVal, %Src2, 32, 31 + BitSize, 0
03033   //   # fall through to UpdateMMB
03034   MBB = UseAltMBB;
03035   if (IsSubWord)
03036     BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RotatedAltVal)
03037       .addReg(RotatedOldVal).addReg(Src2)
03038       .addImm(32).addImm(31 + BitSize).addImm(0);
03039   MBB->addSuccessor(UpdateMBB);
03040 
03041   //  UpdateMBB:
03042   //   %RotatedNewVal = PHI [ %RotatedOldVal, LoopMBB ],
03043   //                        [ %RotatedAltVal, UseAltMBB ]
03044   //   %NewVal        = RLL %RotatedNewVal, 0(%NegBitShift)
03045   //   %Dest          = CS %OldVal, %NewVal, Disp(%Base)
03046   //   JNE LoopMBB
03047   //   # fall through to DoneMMB
03048   MBB = UpdateMBB;
03049   BuildMI(MBB, DL, TII->get(SystemZ::PHI), RotatedNewVal)
03050     .addReg(RotatedOldVal).addMBB(LoopMBB)
03051     .addReg(RotatedAltVal).addMBB(UseAltMBB);
03052   if (IsSubWord)
03053     BuildMI(MBB, DL, TII->get(SystemZ::RLL), NewVal)
03054       .addReg(RotatedNewVal).addReg(NegBitShift).addImm(0);
03055   BuildMI(MBB, DL, TII->get(CSOpcode), Dest)
03056     .addReg(OldVal).addReg(NewVal).addOperand(Base).addImm(Disp);
03057   BuildMI(MBB, DL, TII->get(SystemZ::BRC))
03058     .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
03059   MBB->addSuccessor(LoopMBB);
03060   MBB->addSuccessor(DoneMBB);
03061 
03062   MI->eraseFromParent();
03063   return DoneMBB;
03064 }
03065 
03066 // Implement EmitInstrWithCustomInserter for pseudo ATOMIC_CMP_SWAPW
03067 // instruction MI.
03068 MachineBasicBlock *
03069 SystemZTargetLowering::emitAtomicCmpSwapW(MachineInstr *MI,
03070                                           MachineBasicBlock *MBB) const {
03071   MachineFunction &MF = *MBB->getParent();
03072   const SystemZInstrInfo *TII =
03073       static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
03074   MachineRegisterInfo &MRI = MF.getRegInfo();
03075 
03076   // Extract the operands.  Base can be a register or a frame index.
03077   unsigned Dest        = MI->getOperand(0).getReg();
03078   MachineOperand Base  = earlyUseOperand(MI->getOperand(1));
03079   int64_t  Disp        = MI->getOperand(2).getImm();
03080   unsigned OrigCmpVal  = MI->getOperand(3).getReg();
03081   unsigned OrigSwapVal = MI->getOperand(4).getReg();
03082   unsigned BitShift    = MI->getOperand(5).getReg();
03083   unsigned NegBitShift = MI->getOperand(6).getReg();
03084   int64_t  BitSize     = MI->getOperand(7).getImm();
03085   DebugLoc DL          = MI->getDebugLoc();
03086 
03087   const TargetRegisterClass *RC = &SystemZ::GR32BitRegClass;
03088 
03089   // Get the right opcodes for the displacement.
03090   unsigned LOpcode  = TII->getOpcodeForOffset(SystemZ::L,  Disp);
03091   unsigned CSOpcode = TII->getOpcodeForOffset(SystemZ::CS, Disp);
03092   assert(LOpcode && CSOpcode && "Displacement out of range");
03093 
03094   // Create virtual registers for temporary results.
03095   unsigned OrigOldVal   = MRI.createVirtualRegister(RC);
03096   unsigned OldVal       = MRI.createVirtualRegister(RC);
03097   unsigned CmpVal       = MRI.createVirtualRegister(RC);
03098   unsigned SwapVal      = MRI.createVirtualRegister(RC);
03099   unsigned StoreVal     = MRI.createVirtualRegister(RC);
03100   unsigned RetryOldVal  = MRI.createVirtualRegister(RC);
03101   unsigned RetryCmpVal  = MRI.createVirtualRegister(RC);
03102   unsigned RetrySwapVal = MRI.createVirtualRegister(RC);
03103 
03104   // Insert 2 basic blocks for the loop.
03105   MachineBasicBlock *StartMBB = MBB;
03106   MachineBasicBlock *DoneMBB  = splitBlockBefore(MI, MBB);
03107   MachineBasicBlock *LoopMBB  = emitBlockAfter(StartMBB);
03108   MachineBasicBlock *SetMBB   = emitBlockAfter(LoopMBB);
03109 
03110   //  StartMBB:
03111   //   ...
03112   //   %OrigOldVal     = L Disp(%Base)
03113   //   # fall through to LoopMMB
03114   MBB = StartMBB;
03115   BuildMI(MBB, DL, TII->get(LOpcode), OrigOldVal)
03116     .addOperand(Base).addImm(Disp).addReg(0);
03117   MBB->addSuccessor(LoopMBB);
03118 
03119   //  LoopMBB:
03120   //   %OldVal        = phi [ %OrigOldVal, EntryBB ], [ %RetryOldVal, SetMBB ]
03121   //   %CmpVal        = phi [ %OrigCmpVal, EntryBB ], [ %RetryCmpVal, SetMBB ]
03122   //   %SwapVal       = phi [ %OrigSwapVal, EntryBB ], [ %RetrySwapVal, SetMBB ]
03123   //   %Dest          = RLL %OldVal, BitSize(%BitShift)
03124   //                      ^^ The low BitSize bits contain the field
03125   //                         of interest.
03126   //   %RetryCmpVal   = RISBG32 %CmpVal, %Dest, 32, 63-BitSize, 0
03127   //                      ^^ Replace the upper 32-BitSize bits of the
03128   //                         comparison value with those that we loaded,
03129   //                         so that we can use a full word comparison.
03130   //   CR %Dest, %RetryCmpVal
03131   //   JNE DoneMBB
03132   //   # Fall through to SetMBB
03133   MBB = LoopMBB;
03134   BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
03135     .addReg(OrigOldVal).addMBB(StartMBB)
03136     .addReg(RetryOldVal).addMBB(SetMBB);
03137   BuildMI(MBB, DL, TII->get(SystemZ::PHI), CmpVal)
03138     .addReg(OrigCmpVal).addMBB(StartMBB)
03139     .addReg(RetryCmpVal).addMBB(SetMBB);
03140   BuildMI(MBB, DL, TII->get(SystemZ::PHI), SwapVal)
03141     .addReg(OrigSwapVal).addMBB(StartMBB)
03142     .addReg(RetrySwapVal).addMBB(SetMBB);
03143   BuildMI(MBB, DL, TII->get(SystemZ::RLL), Dest)
03144     .addReg(OldVal).addReg(BitShift).addImm(BitSize);
03145   BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RetryCmpVal)
03146     .addReg(CmpVal).addReg(Dest).addImm(32).addImm(63 - BitSize).addImm(0);
03147   BuildMI(MBB, DL, TII->get(SystemZ::CR))
03148     .addReg(Dest).addReg(RetryCmpVal);
03149   BuildMI(MBB, DL, TII->get(SystemZ::BRC))
03150     .addImm(SystemZ::CCMASK_ICMP)
03151     .addImm(SystemZ::CCMASK_CMP_NE).addMBB(DoneMBB);
03152   MBB->addSuccessor(DoneMBB);
03153   MBB->addSuccessor(SetMBB);
03154 
03155   //  SetMBB:
03156   //   %RetrySwapVal = RISBG32 %SwapVal, %Dest, 32, 63-BitSize, 0
03157   //                      ^^ Replace the upper 32-BitSize bits of the new
03158   //                         value with those that we loaded.
03159   //   %StoreVal    = RLL %RetrySwapVal, -BitSize(%NegBitShift)
03160   //                      ^^ Rotate the new field to its proper position.
03161   //   %RetryOldVal = CS %Dest, %StoreVal, Disp(%Base)
03162   //   JNE LoopMBB
03163   //   # fall through to ExitMMB
03164   MBB = SetMBB;
03165   BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RetrySwapVal)
03166     .addReg(SwapVal).addReg(Dest).addImm(32).addImm(63 - BitSize).addImm(0);
03167   BuildMI(MBB, DL, TII->get(SystemZ::RLL), StoreVal)
03168     .addReg(RetrySwapVal).addReg(NegBitShift).addImm(-BitSize);
03169   BuildMI(MBB, DL, TII->get(CSOpcode), RetryOldVal)
03170     .addReg(OldVal).addReg(StoreVal).addOperand(Base).addImm(Disp);
03171   BuildMI(MBB, DL, TII->get(SystemZ::BRC))
03172     .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
03173   MBB->addSuccessor(LoopMBB);
03174   MBB->addSuccessor(DoneMBB);
03175 
03176   MI->eraseFromParent();
03177   return DoneMBB;
03178 }
03179 
03180 // Emit an extension from a GR32 or GR64 to a GR128.  ClearEven is true
03181 // if the high register of the GR128 value must be cleared or false if
03182 // it's "don't care".  SubReg is subreg_l32 when extending a GR32
03183 // and subreg_l64 when extending a GR64.
03184 MachineBasicBlock *
03185 SystemZTargetLowering::emitExt128(MachineInstr *MI,
03186                                   MachineBasicBlock *MBB,
03187                                   bool ClearEven, unsigned SubReg) const {
03188   MachineFunction &MF = *MBB->getParent();
03189   const SystemZInstrInfo *TII =
03190       static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
03191   MachineRegisterInfo &MRI = MF.getRegInfo();
03192   DebugLoc DL = MI->getDebugLoc();
03193 
03194   unsigned Dest  = MI->getOperand(0).getReg();
03195   unsigned Src   = MI->getOperand(1).getReg();
03196   unsigned In128 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
03197 
03198   BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::IMPLICIT_DEF), In128);
03199   if (ClearEven) {
03200     unsigned NewIn128 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
03201     unsigned Zero64   = MRI.createVirtualRegister(&SystemZ::GR64BitRegClass);
03202 
03203     BuildMI(*MBB, MI, DL, TII->get(SystemZ::LLILL), Zero64)
03204       .addImm(0);
03205     BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), NewIn128)
03206       .addReg(In128).addReg(Zero64).addImm(SystemZ::subreg_h64);
03207     In128 = NewIn128;
03208   }
03209   BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), Dest)
03210     .addReg(In128).addReg(Src).addImm(SubReg);
03211 
03212   MI->eraseFromParent();
03213   return MBB;
03214 }
03215 
03216 MachineBasicBlock *
03217 SystemZTargetLowering::emitMemMemWrapper(MachineInstr *MI,
03218                                          MachineBasicBlock *MBB,
03219                                          unsigned Opcode) const {
03220   MachineFunction &MF = *MBB->getParent();
03221   const SystemZInstrInfo *TII =
03222       static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
03223   MachineRegisterInfo &MRI = MF.getRegInfo();
03224   DebugLoc DL = MI->getDebugLoc();
03225 
03226   MachineOperand DestBase = earlyUseOperand(MI->getOperand(0));
03227   uint64_t       DestDisp = MI->getOperand(1).getImm();
03228   MachineOperand SrcBase  = earlyUseOperand(MI->getOperand(2));
03229   uint64_t       SrcDisp  = MI->getOperand(3).getImm();
03230   uint64_t       Length   = MI->getOperand(4).getImm();
03231 
03232   // When generating more than one CLC, all but the last will need to
03233   // branch to the end when a difference is found.
03234   MachineBasicBlock *EndMBB = (Length > 256 && Opcode == SystemZ::CLC ?
03235                                splitBlockAfter(MI, MBB) : nullptr);
03236 
03237   // Check for the loop form, in which operand 5 is the trip count.
03238   if (MI->getNumExplicitOperands() > 5) {
03239     bool HaveSingleBase = DestBase.isIdenticalTo(SrcBase);
03240 
03241     uint64_t StartCountReg = MI->getOperand(5).getReg();
03242     uint64_t StartSrcReg   = forceReg(MI, SrcBase, TII);
03243     uint64_t StartDestReg  = (HaveSingleBase ? StartSrcReg :
03244                               forceReg(MI, DestBase, TII));
03245 
03246     const TargetRegisterClass *RC = &SystemZ::ADDR64BitRegClass;
03247     uint64_t ThisSrcReg  = MRI.createVirtualRegister(RC);
03248     uint64_t ThisDestReg = (HaveSingleBase ? ThisSrcReg :
03249                             MRI.createVirtualRegister(RC));
03250     uint64_t NextSrcReg  = MRI.createVirtualRegister(RC);
03251     uint64_t NextDestReg = (HaveSingleBase ? NextSrcReg :
03252                             MRI.createVirtualRegister(RC));
03253 
03254     RC = &SystemZ::GR64BitRegClass;
03255     uint64_t ThisCountReg = MRI.createVirtualRegister(RC);
03256     uint64_t NextCountReg = MRI.createVirtualRegister(RC);
03257 
03258     MachineBasicBlock *StartMBB = MBB;
03259     MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
03260     MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
03261     MachineBasicBlock *NextMBB = (EndMBB ? emitBlockAfter(LoopMBB) : LoopMBB);
03262 
03263     //  StartMBB:
03264     //   # fall through to LoopMMB
03265     MBB->addSuccessor(LoopMBB);
03266 
03267     //  LoopMBB:
03268     //   %ThisDestReg = phi [ %StartDestReg, StartMBB ],
03269     //                      [ %NextDestReg, NextMBB ]
03270     //   %ThisSrcReg = phi [ %StartSrcReg, StartMBB ],
03271     //                     [ %NextSrcReg, NextMBB ]
03272     //   %ThisCountReg = phi [ %StartCountReg, StartMBB ],
03273     //                       [ %NextCountReg, NextMBB ]
03274     //   ( PFD 2, 768+DestDisp(%ThisDestReg) )
03275     //   Opcode DestDisp(256,%ThisDestReg), SrcDisp(%ThisSrcReg)
03276     //   ( JLH EndMBB )
03277     //
03278     // The prefetch is used only for MVC.  The JLH is used only for CLC.
03279     MBB = LoopMBB;
03280 
03281     BuildMI(MBB, DL, TII->get(SystemZ::PHI), ThisDestReg)
03282       .addReg(StartDestReg).addMBB(StartMBB)
03283       .addReg(NextDestReg).addMBB(NextMBB);
03284     if (!HaveSingleBase)
03285       BuildMI(MBB, DL, TII->get(SystemZ::PHI), ThisSrcReg)
03286         .addReg(StartSrcReg).addMBB(StartMBB)
03287         .addReg(NextSrcReg).addMBB(NextMBB);
03288     BuildMI(MBB, DL, TII->get(SystemZ::PHI), ThisCountReg)
03289       .addReg(StartCountReg).addMBB(StartMBB)
03290       .addReg(NextCountReg).addMBB(NextMBB);
03291     if (Opcode == SystemZ::MVC)
03292       BuildMI(MBB, DL, TII->get(SystemZ::PFD))
03293         .addImm(SystemZ::PFD_WRITE)
03294         .addReg(ThisDestReg).addImm(DestDisp + 768).addReg(0);
03295     BuildMI(MBB, DL, TII->get(Opcode))
03296       .addReg(ThisDestReg).addImm(DestDisp).addImm(256)
03297       .addReg(ThisSrcReg).addImm(SrcDisp);
03298     if (EndMBB) {
03299       BuildMI(MBB, DL, TII->get(SystemZ::BRC))
03300         .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_NE)
03301         .addMBB(EndMBB);
03302       MBB->addSuccessor(EndMBB);
03303       MBB->addSuccessor(NextMBB);
03304     }
03305 
03306     // NextMBB:
03307     //   %NextDestReg = LA 256(%ThisDestReg)
03308     //   %NextSrcReg = LA 256(%ThisSrcReg)
03309     //   %NextCountReg = AGHI %ThisCountReg, -1
03310     //   CGHI %NextCountReg, 0
03311     //   JLH LoopMBB
03312     //   # fall through to DoneMMB
03313     //
03314     // The AGHI, CGHI and JLH should be converted to BRCTG by later passes.
03315     MBB = NextMBB;
03316 
03317     BuildMI(MBB, DL, TII->get(SystemZ::LA), NextDestReg)
03318       .addReg(ThisDestReg).addImm(256).addReg(0);
03319     if (!HaveSingleBase)
03320       BuildMI(MBB, DL, TII->get(SystemZ::LA), NextSrcReg)
03321         .addReg(ThisSrcReg).addImm(256).addReg(0);
03322     BuildMI(MBB, DL, TII->get(SystemZ::AGHI), NextCountReg)
03323       .addReg(ThisCountReg).addImm(-1);
03324     BuildMI(MBB, DL, TII->get(SystemZ::CGHI))
03325       .addReg(NextCountReg).addImm(0);
03326     BuildMI(MBB, DL, TII->get(SystemZ::BRC))
03327       .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_NE)
03328       .addMBB(LoopMBB);
03329     MBB->addSuccessor(LoopMBB);
03330     MBB->addSuccessor(DoneMBB);
03331 
03332     DestBase = MachineOperand::CreateReg(NextDestReg, false);
03333     SrcBase = MachineOperand::CreateReg(NextSrcReg, false);
03334     Length &= 255;
03335     MBB = DoneMBB;
03336   }
03337   // Handle any remaining bytes with straight-line code.
03338   while (Length > 0) {
03339     uint64_t ThisLength = std::min(Length, uint64_t(256));
03340     // The previous iteration might have created out-of-range displacements.
03341     // Apply them using LAY if so.
03342     if (!isUInt<12>(DestDisp)) {
03343       unsigned Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
03344       BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(SystemZ::LAY), Reg)
03345         .addOperand(DestBase).addImm(DestDisp).addReg(0);
03346       DestBase = MachineOperand::CreateReg(Reg, false);
03347       DestDisp = 0;
03348     }
03349     if (!isUInt<12>(SrcDisp)) {
03350       unsigned Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
03351       BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(SystemZ::LAY), Reg)
03352         .addOperand(SrcBase).addImm(SrcDisp).addReg(0);
03353       SrcBase = MachineOperand::CreateReg(Reg, false);
03354       SrcDisp = 0;
03355     }
03356     BuildMI(*MBB, MI, DL, TII->get(Opcode))
03357       .addOperand(DestBase).addImm(DestDisp).addImm(ThisLength)
03358       .addOperand(SrcBase).addImm(SrcDisp);
03359     DestDisp += ThisLength;
03360     SrcDisp += ThisLength;
03361     Length -= ThisLength;
03362     // If there's another CLC to go, branch to the end if a difference
03363     // was found.
03364     if (EndMBB && Length > 0) {
03365       MachineBasicBlock *NextMBB = splitBlockBefore(MI, MBB);
03366       BuildMI(MBB, DL, TII->get(SystemZ::BRC))
03367         .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_NE)
03368         .addMBB(EndMBB);
03369       MBB->addSuccessor(EndMBB);
03370       MBB->addSuccessor(NextMBB);
03371       MBB = NextMBB;
03372     }
03373   }
03374   if (EndMBB) {
03375     MBB->addSuccessor(EndMBB);
03376     MBB = EndMBB;
03377     MBB->addLiveIn(SystemZ::CC);
03378   }
03379 
03380   MI->eraseFromParent();
03381   return MBB;
03382 }
03383 
03384 // Decompose string pseudo-instruction MI into a loop that continually performs
03385 // Opcode until CC != 3.
03386 MachineBasicBlock *
03387 SystemZTargetLowering::emitStringWrapper(MachineInstr *MI,
03388                                          MachineBasicBlock *MBB,
03389                                          unsigned Opcode) const {
03390   MachineFunction &MF = *MBB->getParent();
03391   const SystemZInstrInfo *TII =
03392       static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
03393   MachineRegisterInfo &MRI = MF.getRegInfo();
03394   DebugLoc DL = MI->getDebugLoc();
03395 
03396   uint64_t End1Reg   = MI->getOperand(0).getReg();
03397   uint64_t Start1Reg = MI->getOperand(1).getReg();
03398   uint64_t Start2Reg = MI->getOperand(2).getReg();
03399   uint64_t CharReg   = MI->getOperand(3).getReg();
03400 
03401   const TargetRegisterClass *RC = &SystemZ::GR64BitRegClass;
03402   uint64_t This1Reg = MRI.createVirtualRegister(RC);
03403   uint64_t This2Reg = MRI.createVirtualRegister(RC);
03404   uint64_t End2Reg  = MRI.createVirtualRegister(RC);
03405 
03406   MachineBasicBlock *StartMBB = MBB;
03407   MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
03408   MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
03409 
03410   //  StartMBB:
03411   //   # fall through to LoopMMB
03412   MBB->addSuccessor(LoopMBB);
03413 
03414   //  LoopMBB:
03415   //   %This1Reg = phi [ %Start1Reg, StartMBB ], [ %End1Reg, LoopMBB ]
03416   //   %This2Reg = phi [ %Start2Reg, StartMBB ], [ %End2Reg, LoopMBB ]
03417   //   R0L = %CharReg
03418   //   %End1Reg, %End2Reg = CLST %This1Reg, %This2Reg -- uses R0L
03419   //   JO LoopMBB
03420   //   # fall through to DoneMMB
03421   //
03422   // The load of R0L can be hoisted by post-RA LICM.
03423   MBB = LoopMBB;
03424 
03425   BuildMI(MBB, DL, TII->get(SystemZ::PHI), This1Reg)
03426     .addReg(Start1Reg).addMBB(StartMBB)
03427     .addReg(End1Reg).addMBB(LoopMBB);
03428   BuildMI(MBB, DL, TII->get(SystemZ::PHI), This2Reg)
03429     .addReg(Start2Reg).addMBB(StartMBB)
03430     .addReg(End2Reg).addMBB(LoopMBB);
03431   BuildMI(MBB, DL, TII->get(TargetOpcode::COPY), SystemZ::R0L).addReg(CharReg);
03432   BuildMI(MBB, DL, TII->get(Opcode))
03433     .addReg(End1Reg, RegState::Define).addReg(End2Reg, RegState::Define)
03434     .addReg(This1Reg).addReg(This2Reg);
03435   BuildMI(MBB, DL, TII->get(SystemZ::BRC))
03436     .addImm(SystemZ::CCMASK_ANY).addImm(SystemZ::CCMASK_3).addMBB(LoopMBB);
03437   MBB->addSuccessor(LoopMBB);
03438   MBB->addSuccessor(DoneMBB);
03439 
03440   DoneMBB->addLiveIn(SystemZ::CC);
03441 
03442   MI->eraseFromParent();
03443   return DoneMBB;
03444 }
03445 
03446 MachineBasicBlock *SystemZTargetLowering::
03447 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const {
03448   switch (MI->getOpcode()) {
03449   case SystemZ::Select32Mux:
03450   case SystemZ::Select32:
03451   case SystemZ::SelectF32:
03452   case SystemZ::Select64:
03453   case SystemZ::SelectF64:
03454   case SystemZ::SelectF128:
03455     return emitSelect(MI, MBB);
03456 
03457   case SystemZ::CondStore8Mux:
03458     return emitCondStore(MI, MBB, SystemZ::STCMux, 0, false);
03459   case SystemZ::CondStore8MuxInv:
03460     return emitCondStore(MI, MBB, SystemZ::STCMux, 0, true);
03461   case SystemZ::CondStore16Mux:
03462     return emitCondStore(MI, MBB, SystemZ::STHMux, 0, false);
03463   case SystemZ::CondStore16MuxInv:
03464     return emitCondStore(MI, MBB, SystemZ::STHMux, 0, true);
03465   case SystemZ::CondStore8:
03466     return emitCondStore(MI, MBB, SystemZ::STC, 0, false);
03467   case SystemZ::CondStore8Inv:
03468     return emitCondStore(MI, MBB, SystemZ::STC, 0, true);
03469   case SystemZ::CondStore16:
03470     return emitCondStore(MI, MBB, SystemZ::STH, 0, false);
03471   case SystemZ::CondStore16Inv:
03472     return emitCondStore(MI, MBB, SystemZ::STH, 0, true);
03473   case SystemZ::CondStore32:
03474     return emitCondStore(MI, MBB, SystemZ::ST, SystemZ::STOC, false);
03475   case SystemZ::CondStore32Inv:
03476     return emitCondStore(MI, MBB, SystemZ::ST, SystemZ::STOC, true);
03477   case SystemZ::CondStore64:
03478     return emitCondStore(MI, MBB, SystemZ::STG, SystemZ::STOCG, false);
03479   case SystemZ::CondStore64Inv:
03480     return emitCondStore(MI, MBB, SystemZ::STG, SystemZ::STOCG, true);
03481   case SystemZ::CondStoreF32:
03482     return emitCondStore(MI, MBB, SystemZ::STE, 0, false);
03483   case SystemZ::CondStoreF32Inv:
03484     return emitCondStore(MI, MBB, SystemZ::STE, 0, true);
03485   case SystemZ::CondStoreF64:
03486     return emitCondStore(MI, MBB, SystemZ::STD, 0, false);
03487   case SystemZ::CondStoreF64Inv:
03488     return emitCondStore(MI, MBB, SystemZ::STD, 0, true);
03489 
03490   case SystemZ::AEXT128_64:
03491     return emitExt128(MI, MBB, false, SystemZ::subreg_l64);
03492   case SystemZ::ZEXT128_32:
03493     return emitExt128(MI, MBB, true, SystemZ::subreg_l32);
03494   case SystemZ::ZEXT128_64:
03495     return emitExt128(MI, MBB, true, SystemZ::subreg_l64);
03496 
03497   case SystemZ::ATOMIC_SWAPW:
03498     return emitAtomicLoadBinary(MI, MBB, 0, 0);
03499   case SystemZ::ATOMIC_SWAP_32:
03500     return emitAtomicLoadBinary(MI, MBB, 0, 32);
03501   case SystemZ::ATOMIC_SWAP_64:
03502     return emitAtomicLoadBinary(MI, MBB, 0, 64);
03503 
03504   case SystemZ::ATOMIC_LOADW_AR:
03505     return emitAtomicLoadBinary(MI, MBB, SystemZ::AR, 0);
03506   case SystemZ::ATOMIC_LOADW_AFI:
03507     return emitAtomicLoadBinary(MI, MBB, SystemZ::AFI, 0);
03508   case SystemZ::ATOMIC_LOAD_AR:
03509     return emitAtomicLoadBinary(MI, MBB, SystemZ::AR, 32);
03510   case SystemZ::ATOMIC_LOAD_AHI:
03511     return emitAtomicLoadBinary(MI, MBB, SystemZ::AHI, 32);
03512   case SystemZ::ATOMIC_LOAD_AFI:
03513     return emitAtomicLoadBinary(MI, MBB, SystemZ::AFI, 32);
03514   case SystemZ::ATOMIC_LOAD_AGR:
03515     return emitAtomicLoadBinary(MI, MBB, SystemZ::AGR, 64);
03516   case SystemZ::ATOMIC_LOAD_AGHI:
03517     return emitAtomicLoadBinary(MI, MBB, SystemZ::AGHI, 64);
03518   case SystemZ::ATOMIC_LOAD_AGFI:
03519     return emitAtomicLoadBinary(MI, MBB, SystemZ::AGFI, 64);
03520 
03521   case SystemZ::ATOMIC_LOADW_SR:
03522     return emitAtomicLoadBinary(MI, MBB, SystemZ::SR, 0);
03523   case SystemZ::ATOMIC_LOAD_SR:
03524     return emitAtomicLoadBinary(MI, MBB, SystemZ::SR, 32);
03525   case SystemZ::ATOMIC_LOAD_SGR:
03526     return emitAtomicLoadBinary(MI, MBB, SystemZ::SGR, 64);
03527 
03528   case SystemZ::ATOMIC_LOADW_NR:
03529     return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 0);
03530   case SystemZ::ATOMIC_LOADW_NILH:
03531     return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 0);
03532   case SystemZ::ATOMIC_LOAD_NR:
03533     return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 32);
03534   case SystemZ::ATOMIC_LOAD_NILL:
03535     return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL, 32);
03536   case SystemZ::ATOMIC_LOAD_NILH:
03537     return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 32);
03538   case SystemZ::ATOMIC_LOAD_NILF:
03539     return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF, 32);
03540   case SystemZ::ATOMIC_LOAD_NGR:
03541     return emitAtomicLoadBinary(MI, MBB, SystemZ::NGR, 64);
03542   case SystemZ::ATOMIC_LOAD_NILL64:
03543     return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL64, 64);
03544   case SystemZ::ATOMIC_LOAD_NILH64:
03545     return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH64, 64);
03546   case SystemZ::ATOMIC_LOAD_NIHL64:
03547     return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHL64, 64);
03548   case SystemZ::ATOMIC_LOAD_NIHH64:
03549     return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHH64, 64);
03550   case SystemZ::ATOMIC_LOAD_NILF64:
03551     return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF64, 64);
03552   case SystemZ::ATOMIC_LOAD_NIHF64:
03553     return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHF64, 64);
03554 
03555   case SystemZ::ATOMIC_LOADW_OR:
03556     return emitAtomicLoadBinary(MI, MBB, SystemZ::OR, 0);
03557   case SystemZ::ATOMIC_LOADW_OILH:
03558     return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH, 0);
03559   case SystemZ::ATOMIC_LOAD_OR:
03560     return emitAtomicLoadBinary(MI, MBB, SystemZ::OR, 32);
03561   case SystemZ::ATOMIC_LOAD_OILL:
03562     return emitAtomicLoadBinary(MI, MBB, SystemZ::OILL, 32);
03563   case SystemZ::ATOMIC_LOAD_OILH:
03564     return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH, 32);
03565   case SystemZ::ATOMIC_LOAD_OILF:
03566     return emitAtomicLoadBinary(MI, MBB, SystemZ::OILF, 32);
03567   case SystemZ::ATOMIC_LOAD_OGR:
03568     return emitAtomicLoadBinary(MI, MBB, SystemZ::OGR, 64);
03569   case SystemZ::ATOMIC_LOAD_OILL64:
03570     return emitAtomicLoadBinary(MI, MBB, SystemZ::OILL64, 64);
03571   case SystemZ::ATOMIC_LOAD_OILH64:
03572     return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH64, 64);
03573   case SystemZ::ATOMIC_LOAD_OIHL64:
03574     return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHL64, 64);
03575   case SystemZ::ATOMIC_LOAD_OIHH64:
03576     return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHH64, 64);
03577   case SystemZ::ATOMIC_LOAD_OILF64:
03578     return emitAtomicLoadBinary(MI, MBB, SystemZ::OILF64, 64);
03579   case SystemZ::ATOMIC_LOAD_OIHF64:
03580     return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHF64, 64);
03581 
03582   case SystemZ::ATOMIC_LOADW_XR:
03583     return emitAtomicLoadBinary(MI, MBB, SystemZ::XR, 0);
03584   case SystemZ::ATOMIC_LOADW_XILF:
03585     return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF, 0);
03586   case SystemZ::ATOMIC_LOAD_XR:
03587     return emitAtomicLoadBinary(MI, MBB, SystemZ::XR, 32);
03588   case SystemZ::ATOMIC_LOAD_XILF:
03589     return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF, 32);
03590   case SystemZ::ATOMIC_LOAD_XGR:
03591     return emitAtomicLoadBinary(MI, MBB, SystemZ::XGR, 64);
03592   case SystemZ::ATOMIC_LOAD_XILF64:
03593     return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF64, 64);
03594   case SystemZ::ATOMIC_LOAD_XIHF64:
03595     return emitAtomicLoadBinary(MI, MBB, SystemZ::XIHF64, 64);
03596 
03597   case SystemZ::ATOMIC_LOADW_NRi:
03598     return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 0, true);
03599   case SystemZ::ATOMIC_LOADW_NILHi:
03600     return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 0, true);
03601   case SystemZ::ATOMIC_LOAD_NRi:
03602     return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 32, true);
03603   case SystemZ::ATOMIC_LOAD_NILLi:
03604     return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL, 32, true);
03605   case SystemZ::ATOMIC_LOAD_NILHi:
03606     return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 32, true);
03607   case SystemZ::ATOMIC_LOAD_NILFi:
03608     return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF, 32, true);
03609   case SystemZ::ATOMIC_LOAD_NGRi:
03610     return emitAtomicLoadBinary(MI, MBB, SystemZ::NGR, 64, true);
03611   case SystemZ::ATOMIC_LOAD_NILL64i:
03612     return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL64, 64, true);
03613   case SystemZ::ATOMIC_LOAD_NILH64i:
03614     return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH64, 64, true);
03615   case SystemZ::ATOMIC_LOAD_NIHL64i:
03616     return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHL64, 64, true);
03617   case SystemZ::ATOMIC_LOAD_NIHH64i:
03618     return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHH64, 64, true);
03619   case SystemZ::ATOMIC_LOAD_NILF64i:
03620     return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF64, 64, true);
03621   case SystemZ::ATOMIC_LOAD_NIHF64i:
03622     return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHF64, 64, true);
03623 
03624   case SystemZ::ATOMIC_LOADW_MIN:
03625     return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
03626                                 SystemZ::CCMASK_CMP_LE, 0);
03627   case SystemZ::ATOMIC_LOAD_MIN_32:
03628     return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
03629                                 SystemZ::CCMASK_CMP_LE, 32);
03630   case SystemZ::ATOMIC_LOAD_MIN_64:
03631     return emitAtomicLoadMinMax(MI, MBB, SystemZ::CGR,
03632                                 SystemZ::CCMASK_CMP_LE, 64);
03633 
03634   case SystemZ::ATOMIC_LOADW_MAX:
03635     return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
03636                                 SystemZ::CCMASK_CMP_GE, 0);
03637   case SystemZ::ATOMIC_LOAD_MAX_32:
03638     return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
03639                                 SystemZ::CCMASK_CMP_GE, 32);
03640   case SystemZ::ATOMIC_LOAD_MAX_64:
03641     return emitAtomicLoadMinMax(MI, MBB, SystemZ::CGR,
03642                                 SystemZ::CCMASK_CMP_GE, 64);
03643 
03644   case SystemZ::ATOMIC_LOADW_UMIN:
03645     return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
03646                                 SystemZ::CCMASK_CMP_LE, 0);
03647   case SystemZ::ATOMIC_LOAD_UMIN_32:
03648     return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
03649                                 SystemZ::CCMASK_CMP_LE, 32);
03650   case SystemZ::ATOMIC_LOAD_UMIN_64:
03651     return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLGR,
03652                                 SystemZ::CCMASK_CMP_LE, 64);
03653 
03654   case SystemZ::ATOMIC_LOADW_UMAX:
03655     return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
03656                                 SystemZ::CCMASK_CMP_GE, 0);
03657   case SystemZ::ATOMIC_LOAD_UMAX_32:
03658     return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
03659                                 SystemZ::CCMASK_CMP_GE, 32);
03660   case SystemZ::ATOMIC_LOAD_UMAX_64:
03661     return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLGR,
03662                                 SystemZ::CCMASK_CMP_GE, 64);
03663 
03664   case SystemZ::ATOMIC_CMP_SWAPW:
03665     return emitAtomicCmpSwapW(MI, MBB);
03666   case SystemZ::MVCSequence:
03667   case SystemZ::MVCLoop:
03668     return emitMemMemWrapper(MI, MBB, SystemZ::MVC);
03669   case SystemZ::NCSequence:
03670   case SystemZ::NCLoop:
03671     return emitMemMemWrapper(MI, MBB, SystemZ::NC);
03672   case SystemZ::OCSequence:
03673   case SystemZ::OCLoop:
03674     return emitMemMemWrapper(MI, MBB, SystemZ::OC);
03675   case SystemZ::XCSequence:
03676   case SystemZ::XCLoop:
03677     return emitMemMemWrapper(MI, MBB, SystemZ::XC);
03678   case SystemZ::CLCSequence:
03679   case SystemZ::CLCLoop:
03680     return emitMemMemWrapper(MI, MBB, SystemZ::CLC);
03681   case SystemZ::CLSTLoop:
03682     return emitStringWrapper(MI, MBB, SystemZ::CLST);
03683   case SystemZ::MVSTLoop:
03684     return emitStringWrapper(MI, MBB, SystemZ::MVST);
03685   case SystemZ::SRSTLoop:
03686     return emitStringWrapper(MI, MBB, SystemZ::SRST);
03687   default:
03688     llvm_unreachable("Unexpected instr type to insert");
03689   }
03690 }