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SystemZISelLowering.cpp
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00001 //===-- SystemZISelLowering.cpp - SystemZ DAG lowering implementation -----===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file implements the SystemZTargetLowering class.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #include "SystemZISelLowering.h"
00015 #include "SystemZCallingConv.h"
00016 #include "SystemZConstantPoolValue.h"
00017 #include "SystemZMachineFunctionInfo.h"
00018 #include "SystemZTargetMachine.h"
00019 #include "llvm/CodeGen/CallingConvLower.h"
00020 #include "llvm/CodeGen/MachineInstrBuilder.h"
00021 #include "llvm/CodeGen/MachineRegisterInfo.h"
00022 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
00023 #include <cctype>
00024 
00025 using namespace llvm;
00026 
00027 #define DEBUG_TYPE "systemz-lower"
00028 
00029 namespace {
00030 // Represents a sequence for extracting a 0/1 value from an IPM result:
00031 // (((X ^ XORValue) + AddValue) >> Bit)
00032 struct IPMConversion {
00033   IPMConversion(unsigned xorValue, int64_t addValue, unsigned bit)
00034     : XORValue(xorValue), AddValue(addValue), Bit(bit) {}
00035 
00036   int64_t XORValue;
00037   int64_t AddValue;
00038   unsigned Bit;
00039 };
00040 
00041 // Represents information about a comparison.
00042 struct Comparison {
00043   Comparison(SDValue Op0In, SDValue Op1In)
00044     : Op0(Op0In), Op1(Op1In), Opcode(0), ICmpType(0), CCValid(0), CCMask(0) {}
00045 
00046   // The operands to the comparison.
00047   SDValue Op0, Op1;
00048 
00049   // The opcode that should be used to compare Op0 and Op1.
00050   unsigned Opcode;
00051 
00052   // A SystemZICMP value.  Only used for integer comparisons.
00053   unsigned ICmpType;
00054 
00055   // The mask of CC values that Opcode can produce.
00056   unsigned CCValid;
00057 
00058   // The mask of CC values for which the original condition is true.
00059   unsigned CCMask;
00060 };
00061 } // end anonymous namespace
00062 
00063 // Classify VT as either 32 or 64 bit.
00064 static bool is32Bit(EVT VT) {
00065   switch (VT.getSimpleVT().SimpleTy) {
00066   case MVT::i32:
00067     return true;
00068   case MVT::i64:
00069     return false;
00070   default:
00071     llvm_unreachable("Unsupported type");
00072   }
00073 }
00074 
00075 // Return a version of MachineOperand that can be safely used before the
00076 // final use.
00077 static MachineOperand earlyUseOperand(MachineOperand Op) {
00078   if (Op.isReg())
00079     Op.setIsKill(false);
00080   return Op;
00081 }
00082 
00083 SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &tm)
00084     : TargetLowering(tm, new TargetLoweringObjectFileELF()),
00085       Subtarget(tm.getSubtarget<SystemZSubtarget>()) {
00086   MVT PtrVT = getPointerTy();
00087 
00088   // Set up the register classes.
00089   if (Subtarget.hasHighWord())
00090     addRegisterClass(MVT::i32, &SystemZ::GRX32BitRegClass);
00091   else
00092     addRegisterClass(MVT::i32, &SystemZ::GR32BitRegClass);
00093   addRegisterClass(MVT::i64,  &SystemZ::GR64BitRegClass);
00094   addRegisterClass(MVT::f32,  &SystemZ::FP32BitRegClass);
00095   addRegisterClass(MVT::f64,  &SystemZ::FP64BitRegClass);
00096   addRegisterClass(MVT::f128, &SystemZ::FP128BitRegClass);
00097 
00098   // Compute derived properties from the register classes
00099   computeRegisterProperties();
00100 
00101   // Set up special registers.
00102   setExceptionPointerRegister(SystemZ::R6D);
00103   setExceptionSelectorRegister(SystemZ::R7D);
00104   setStackPointerRegisterToSaveRestore(SystemZ::R15D);
00105 
00106   // TODO: It may be better to default to latency-oriented scheduling, however
00107   // LLVM's current latency-oriented scheduler can't handle physreg definitions
00108   // such as SystemZ has with CC, so set this to the register-pressure
00109   // scheduler, because it can.
00110   setSchedulingPreference(Sched::RegPressure);
00111 
00112   setBooleanContents(ZeroOrOneBooleanContent);
00113   setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
00114 
00115   // Instructions are strings of 2-byte aligned 2-byte values.
00116   setMinFunctionAlignment(2);
00117 
00118   // Handle operations that are handled in a similar way for all types.
00119   for (unsigned I = MVT::FIRST_INTEGER_VALUETYPE;
00120        I <= MVT::LAST_FP_VALUETYPE;
00121        ++I) {
00122     MVT VT = MVT::SimpleValueType(I);
00123     if (isTypeLegal(VT)) {
00124       // Lower SET_CC into an IPM-based sequence.
00125       setOperationAction(ISD::SETCC, VT, Custom);
00126 
00127       // Expand SELECT(C, A, B) into SELECT_CC(X, 0, A, B, NE).
00128       setOperationAction(ISD::SELECT, VT, Expand);
00129 
00130       // Lower SELECT_CC and BR_CC into separate comparisons and branches.
00131       setOperationAction(ISD::SELECT_CC, VT, Custom);
00132       setOperationAction(ISD::BR_CC,     VT, Custom);
00133     }
00134   }
00135 
00136   // Expand jump table branches as address arithmetic followed by an
00137   // indirect jump.
00138   setOperationAction(ISD::BR_JT, MVT::Other, Expand);
00139 
00140   // Expand BRCOND into a BR_CC (see above).
00141   setOperationAction(ISD::BRCOND, MVT::Other, Expand);
00142 
00143   // Handle integer types.
00144   for (unsigned I = MVT::FIRST_INTEGER_VALUETYPE;
00145        I <= MVT::LAST_INTEGER_VALUETYPE;
00146        ++I) {
00147     MVT VT = MVT::SimpleValueType(I);
00148     if (isTypeLegal(VT)) {
00149       // Expand individual DIV and REMs into DIVREMs.
00150       setOperationAction(ISD::SDIV, VT, Expand);
00151       setOperationAction(ISD::UDIV, VT, Expand);
00152       setOperationAction(ISD::SREM, VT, Expand);
00153       setOperationAction(ISD::UREM, VT, Expand);
00154       setOperationAction(ISD::SDIVREM, VT, Custom);
00155       setOperationAction(ISD::UDIVREM, VT, Custom);
00156 
00157       // Lower ATOMIC_LOAD and ATOMIC_STORE into normal volatile loads and
00158       // stores, putting a serialization instruction after the stores.
00159       setOperationAction(ISD::ATOMIC_LOAD,  VT, Custom);
00160       setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
00161 
00162       // Lower ATOMIC_LOAD_SUB into ATOMIC_LOAD_ADD if LAA and LAAG are
00163       // available, or if the operand is constant.
00164       setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
00165 
00166       // No special instructions for these.
00167       setOperationAction(ISD::CTPOP,           VT, Expand);
00168       setOperationAction(ISD::CTTZ,            VT, Expand);
00169       setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
00170       setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
00171       setOperationAction(ISD::ROTR,            VT, Expand);
00172 
00173       // Use *MUL_LOHI where possible instead of MULH*.
00174       setOperationAction(ISD::MULHS, VT, Expand);
00175       setOperationAction(ISD::MULHU, VT, Expand);
00176       setOperationAction(ISD::SMUL_LOHI, VT, Custom);
00177       setOperationAction(ISD::UMUL_LOHI, VT, Custom);
00178 
00179       // Only z196 and above have native support for conversions to unsigned.
00180       if (!Subtarget.hasFPExtension())
00181         setOperationAction(ISD::FP_TO_UINT, VT, Expand);
00182     }
00183   }
00184 
00185   // Type legalization will convert 8- and 16-bit atomic operations into
00186   // forms that operate on i32s (but still keeping the original memory VT).
00187   // Lower them into full i32 operations.
00188   setOperationAction(ISD::ATOMIC_SWAP,      MVT::i32, Custom);
00189   setOperationAction(ISD::ATOMIC_LOAD_ADD,  MVT::i32, Custom);
00190   setOperationAction(ISD::ATOMIC_LOAD_SUB,  MVT::i32, Custom);
00191   setOperationAction(ISD::ATOMIC_LOAD_AND,  MVT::i32, Custom);
00192   setOperationAction(ISD::ATOMIC_LOAD_OR,   MVT::i32, Custom);
00193   setOperationAction(ISD::ATOMIC_LOAD_XOR,  MVT::i32, Custom);
00194   setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Custom);
00195   setOperationAction(ISD::ATOMIC_LOAD_MIN,  MVT::i32, Custom);
00196   setOperationAction(ISD::ATOMIC_LOAD_MAX,  MVT::i32, Custom);
00197   setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Custom);
00198   setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Custom);
00199   setOperationAction(ISD::ATOMIC_CMP_SWAP,  MVT::i32, Custom);
00200 
00201   // z10 has instructions for signed but not unsigned FP conversion.
00202   // Handle unsigned 32-bit types as signed 64-bit types.
00203   if (!Subtarget.hasFPExtension()) {
00204     setOperationAction(ISD::UINT_TO_FP, MVT::i32, Promote);
00205     setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
00206   }
00207 
00208   // We have native support for a 64-bit CTLZ, via FLOGR.
00209   setOperationAction(ISD::CTLZ, MVT::i32, Promote);
00210   setOperationAction(ISD::CTLZ, MVT::i64, Legal);
00211 
00212   // Give LowerOperation the chance to replace 64-bit ORs with subregs.
00213   setOperationAction(ISD::OR, MVT::i64, Custom);
00214 
00215   // FIXME: Can we support these natively?
00216   setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
00217   setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
00218   setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
00219 
00220   // We have native instructions for i8, i16 and i32 extensions, but not i1.
00221   setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
00222   setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
00223   setLoadExtAction(ISD::EXTLOAD,  MVT::i1, Promote);
00224   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
00225 
00226   // Handle the various types of symbolic address.
00227   setOperationAction(ISD::ConstantPool,     PtrVT, Custom);
00228   setOperationAction(ISD::GlobalAddress,    PtrVT, Custom);
00229   setOperationAction(ISD::GlobalTLSAddress, PtrVT, Custom);
00230   setOperationAction(ISD::BlockAddress,     PtrVT, Custom);
00231   setOperationAction(ISD::JumpTable,        PtrVT, Custom);
00232 
00233   // We need to handle dynamic allocations specially because of the
00234   // 160-byte area at the bottom of the stack.
00235   setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom);
00236 
00237   // Use custom expanders so that we can force the function to use
00238   // a frame pointer.
00239   setOperationAction(ISD::STACKSAVE,    MVT::Other, Custom);
00240   setOperationAction(ISD::STACKRESTORE, MVT::Other, Custom);
00241 
00242   // Handle prefetches with PFD or PFDRL.
00243   setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
00244 
00245   // Handle floating-point types.
00246   for (unsigned I = MVT::FIRST_FP_VALUETYPE;
00247        I <= MVT::LAST_FP_VALUETYPE;
00248        ++I) {
00249     MVT VT = MVT::SimpleValueType(I);
00250     if (isTypeLegal(VT)) {
00251       // We can use FI for FRINT.
00252       setOperationAction(ISD::FRINT, VT, Legal);
00253 
00254       // We can use the extended form of FI for other rounding operations.
00255       if (Subtarget.hasFPExtension()) {
00256         setOperationAction(ISD::FNEARBYINT, VT, Legal);
00257         setOperationAction(ISD::FFLOOR, VT, Legal);
00258         setOperationAction(ISD::FCEIL, VT, Legal);
00259         setOperationAction(ISD::FTRUNC, VT, Legal);
00260         setOperationAction(ISD::FROUND, VT, Legal);
00261       }
00262 
00263       // No special instructions for these.
00264       setOperationAction(ISD::FSIN, VT, Expand);
00265       setOperationAction(ISD::FCOS, VT, Expand);
00266       setOperationAction(ISD::FREM, VT, Expand);
00267     }
00268   }
00269 
00270   // We have fused multiply-addition for f32 and f64 but not f128.
00271   setOperationAction(ISD::FMA, MVT::f32,  Legal);
00272   setOperationAction(ISD::FMA, MVT::f64,  Legal);
00273   setOperationAction(ISD::FMA, MVT::f128, Expand);
00274 
00275   // Needed so that we don't try to implement f128 constant loads using
00276   // a load-and-extend of a f80 constant (in cases where the constant
00277   // would fit in an f80).
00278   setLoadExtAction(ISD::EXTLOAD, MVT::f80, Expand);
00279 
00280   // Floating-point truncation and stores need to be done separately.
00281   setTruncStoreAction(MVT::f64,  MVT::f32, Expand);
00282   setTruncStoreAction(MVT::f128, MVT::f32, Expand);
00283   setTruncStoreAction(MVT::f128, MVT::f64, Expand);
00284 
00285   // We have 64-bit FPR<->GPR moves, but need special handling for
00286   // 32-bit forms.
00287   setOperationAction(ISD::BITCAST, MVT::i32, Custom);
00288   setOperationAction(ISD::BITCAST, MVT::f32, Custom);
00289 
00290   // VASTART and VACOPY need to deal with the SystemZ-specific varargs
00291   // structure, but VAEND is a no-op.
00292   setOperationAction(ISD::VASTART, MVT::Other, Custom);
00293   setOperationAction(ISD::VACOPY,  MVT::Other, Custom);
00294   setOperationAction(ISD::VAEND,   MVT::Other, Expand);
00295 
00296   // Codes for which we want to perform some z-specific combinations.
00297   setTargetDAGCombine(ISD::SIGN_EXTEND);
00298 
00299   // We want to use MVC in preference to even a single load/store pair.
00300   MaxStoresPerMemcpy = 0;
00301   MaxStoresPerMemcpyOptSize = 0;
00302 
00303   // The main memset sequence is a byte store followed by an MVC.
00304   // Two STC or MV..I stores win over that, but the kind of fused stores
00305   // generated by target-independent code don't when the byte value is
00306   // variable.  E.g.  "STC <reg>;MHI <reg>,257;STH <reg>" is not better
00307   // than "STC;MVC".  Handle the choice in target-specific code instead.
00308   MaxStoresPerMemset = 0;
00309   MaxStoresPerMemsetOptSize = 0;
00310 }
00311 
00312 EVT SystemZTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
00313   if (!VT.isVector())
00314     return MVT::i32;
00315   return VT.changeVectorElementTypeToInteger();
00316 }
00317 
00318 bool SystemZTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
00319   VT = VT.getScalarType();
00320 
00321   if (!VT.isSimple())
00322     return false;
00323 
00324   switch (VT.getSimpleVT().SimpleTy) {
00325   case MVT::f32:
00326   case MVT::f64:
00327     return true;
00328   case MVT::f128:
00329     return false;
00330   default:
00331     break;
00332   }
00333 
00334   return false;
00335 }
00336 
00337 bool SystemZTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
00338   // We can load zero using LZ?R and negative zero using LZ?R;LC?BR.
00339   return Imm.isZero() || Imm.isNegZero();
00340 }
00341 
00342 bool SystemZTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
00343                                                            unsigned,
00344                                                            unsigned,
00345                                                            bool *Fast) const {
00346   // Unaligned accesses should never be slower than the expanded version.
00347   // We check specifically for aligned accesses in the few cases where
00348   // they are required.
00349   if (Fast)
00350     *Fast = true;
00351   return true;
00352 }
00353   
00354 bool SystemZTargetLowering::isLegalAddressingMode(const AddrMode &AM,
00355                                                   Type *Ty) const {
00356   // Punt on globals for now, although they can be used in limited
00357   // RELATIVE LONG cases.
00358   if (AM.BaseGV)
00359     return false;
00360 
00361   // Require a 20-bit signed offset.
00362   if (!isInt<20>(AM.BaseOffs))
00363     return false;
00364 
00365   // Indexing is OK but no scale factor can be applied.
00366   return AM.Scale == 0 || AM.Scale == 1;
00367 }
00368 
00369 bool SystemZTargetLowering::isTruncateFree(Type *FromType, Type *ToType) const {
00370   if (!FromType->isIntegerTy() || !ToType->isIntegerTy())
00371     return false;
00372   unsigned FromBits = FromType->getPrimitiveSizeInBits();
00373   unsigned ToBits = ToType->getPrimitiveSizeInBits();
00374   return FromBits > ToBits;
00375 }
00376 
00377 bool SystemZTargetLowering::isTruncateFree(EVT FromVT, EVT ToVT) const {
00378   if (!FromVT.isInteger() || !ToVT.isInteger())
00379     return false;
00380   unsigned FromBits = FromVT.getSizeInBits();
00381   unsigned ToBits = ToVT.getSizeInBits();
00382   return FromBits > ToBits;
00383 }
00384 
00385 //===----------------------------------------------------------------------===//
00386 // Inline asm support
00387 //===----------------------------------------------------------------------===//
00388 
00389 TargetLowering::ConstraintType
00390 SystemZTargetLowering::getConstraintType(const std::string &Constraint) const {
00391   if (Constraint.size() == 1) {
00392     switch (Constraint[0]) {
00393     case 'a': // Address register
00394     case 'd': // Data register (equivalent to 'r')
00395     case 'f': // Floating-point register
00396     case 'h': // High-part register
00397     case 'r': // General-purpose register
00398       return C_RegisterClass;
00399 
00400     case 'Q': // Memory with base and unsigned 12-bit displacement
00401     case 'R': // Likewise, plus an index
00402     case 'S': // Memory with base and signed 20-bit displacement
00403     case 'T': // Likewise, plus an index
00404     case 'm': // Equivalent to 'T'.
00405       return C_Memory;
00406 
00407     case 'I': // Unsigned 8-bit constant
00408     case 'J': // Unsigned 12-bit constant
00409     case 'K': // Signed 16-bit constant
00410     case 'L': // Signed 20-bit displacement (on all targets we support)
00411     case 'M': // 0x7fffffff
00412       return C_Other;
00413 
00414     default:
00415       break;
00416     }
00417   }
00418   return TargetLowering::getConstraintType(Constraint);
00419 }
00420 
00421 TargetLowering::ConstraintWeight SystemZTargetLowering::
00422 getSingleConstraintMatchWeight(AsmOperandInfo &info,
00423                                const char *constraint) const {
00424   ConstraintWeight weight = CW_Invalid;
00425   Value *CallOperandVal = info.CallOperandVal;
00426   // If we don't have a value, we can't do a match,
00427   // but allow it at the lowest weight.
00428   if (!CallOperandVal)
00429     return CW_Default;
00430   Type *type = CallOperandVal->getType();
00431   // Look at the constraint type.
00432   switch (*constraint) {
00433   default:
00434     weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
00435     break;
00436 
00437   case 'a': // Address register
00438   case 'd': // Data register (equivalent to 'r')
00439   case 'h': // High-part register
00440   case 'r': // General-purpose register
00441     if (CallOperandVal->getType()->isIntegerTy())
00442       weight = CW_Register;
00443     break;
00444 
00445   case 'f': // Floating-point register
00446     if (type->isFloatingPointTy())
00447       weight = CW_Register;
00448     break;
00449 
00450   case 'I': // Unsigned 8-bit constant
00451     if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
00452       if (isUInt<8>(C->getZExtValue()))
00453         weight = CW_Constant;
00454     break;
00455 
00456   case 'J': // Unsigned 12-bit constant
00457     if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
00458       if (isUInt<12>(C->getZExtValue()))
00459         weight = CW_Constant;
00460     break;
00461 
00462   case 'K': // Signed 16-bit constant
00463     if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
00464       if (isInt<16>(C->getSExtValue()))
00465         weight = CW_Constant;
00466     break;
00467 
00468   case 'L': // Signed 20-bit displacement (on all targets we support)
00469     if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
00470       if (isInt<20>(C->getSExtValue()))
00471         weight = CW_Constant;
00472     break;
00473 
00474   case 'M': // 0x7fffffff
00475     if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
00476       if (C->getZExtValue() == 0x7fffffff)
00477         weight = CW_Constant;
00478     break;
00479   }
00480   return weight;
00481 }
00482 
00483 // Parse a "{tNNN}" register constraint for which the register type "t"
00484 // has already been verified.  MC is the class associated with "t" and
00485 // Map maps 0-based register numbers to LLVM register numbers.
00486 static std::pair<unsigned, const TargetRegisterClass *>
00487 parseRegisterNumber(const std::string &Constraint,
00488                     const TargetRegisterClass *RC, const unsigned *Map) {
00489   assert(*(Constraint.end()-1) == '}' && "Missing '}'");
00490   if (isdigit(Constraint[2])) {
00491     std::string Suffix(Constraint.data() + 2, Constraint.size() - 2);
00492     unsigned Index = atoi(Suffix.c_str());
00493     if (Index < 16 && Map[Index])
00494       return std::make_pair(Map[Index], RC);
00495   }
00496   return std::make_pair(0U, nullptr);
00497 }
00498 
00499 std::pair<unsigned, const TargetRegisterClass *> SystemZTargetLowering::
00500 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const {
00501   if (Constraint.size() == 1) {
00502     // GCC Constraint Letters
00503     switch (Constraint[0]) {
00504     default: break;
00505     case 'd': // Data register (equivalent to 'r')
00506     case 'r': // General-purpose register
00507       if (VT == MVT::i64)
00508         return std::make_pair(0U, &SystemZ::GR64BitRegClass);
00509       else if (VT == MVT::i128)
00510         return std::make_pair(0U, &SystemZ::GR128BitRegClass);
00511       return std::make_pair(0U, &SystemZ::GR32BitRegClass);
00512 
00513     case 'a': // Address register
00514       if (VT == MVT::i64)
00515         return std::make_pair(0U, &SystemZ::ADDR64BitRegClass);
00516       else if (VT == MVT::i128)
00517         return std::make_pair(0U, &SystemZ::ADDR128BitRegClass);
00518       return std::make_pair(0U, &SystemZ::ADDR32BitRegClass);
00519 
00520     case 'h': // High-part register (an LLVM extension)
00521       return std::make_pair(0U, &SystemZ::GRH32BitRegClass);
00522 
00523     case 'f': // Floating-point register
00524       if (VT == MVT::f64)
00525         return std::make_pair(0U, &SystemZ::FP64BitRegClass);
00526       else if (VT == MVT::f128)
00527         return std::make_pair(0U, &SystemZ::FP128BitRegClass);
00528       return std::make_pair(0U, &SystemZ::FP32BitRegClass);
00529     }
00530   }
00531   if (Constraint[0] == '{') {
00532     // We need to override the default register parsing for GPRs and FPRs
00533     // because the interpretation depends on VT.  The internal names of
00534     // the registers are also different from the external names
00535     // (F0D and F0S instead of F0, etc.).
00536     if (Constraint[1] == 'r') {
00537       if (VT == MVT::i32)
00538         return parseRegisterNumber(Constraint, &SystemZ::GR32BitRegClass,
00539                                    SystemZMC::GR32Regs);
00540       if (VT == MVT::i128)
00541         return parseRegisterNumber(Constraint, &SystemZ::GR128BitRegClass,
00542                                    SystemZMC::GR128Regs);
00543       return parseRegisterNumber(Constraint, &SystemZ::GR64BitRegClass,
00544                                  SystemZMC::GR64Regs);
00545     }
00546     if (Constraint[1] == 'f') {
00547       if (VT == MVT::f32)
00548         return parseRegisterNumber(Constraint, &SystemZ::FP32BitRegClass,
00549                                    SystemZMC::FP32Regs);
00550       if (VT == MVT::f128)
00551         return parseRegisterNumber(Constraint, &SystemZ::FP128BitRegClass,
00552                                    SystemZMC::FP128Regs);
00553       return parseRegisterNumber(Constraint, &SystemZ::FP64BitRegClass,
00554                                  SystemZMC::FP64Regs);
00555     }
00556   }
00557   return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
00558 }
00559 
00560 void SystemZTargetLowering::
00561 LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
00562                              std::vector<SDValue> &Ops,
00563                              SelectionDAG &DAG) const {
00564   // Only support length 1 constraints for now.
00565   if (Constraint.length() == 1) {
00566     switch (Constraint[0]) {
00567     case 'I': // Unsigned 8-bit constant
00568       if (auto *C = dyn_cast<ConstantSDNode>(Op))
00569         if (isUInt<8>(C->getZExtValue()))
00570           Ops.push_back(DAG.getTargetConstant(C->getZExtValue(),
00571                                               Op.getValueType()));
00572       return;
00573 
00574     case 'J': // Unsigned 12-bit constant
00575       if (auto *C = dyn_cast<ConstantSDNode>(Op))
00576         if (isUInt<12>(C->getZExtValue()))
00577           Ops.push_back(DAG.getTargetConstant(C->getZExtValue(),
00578                                               Op.getValueType()));
00579       return;
00580 
00581     case 'K': // Signed 16-bit constant
00582       if (auto *C = dyn_cast<ConstantSDNode>(Op))
00583         if (isInt<16>(C->getSExtValue()))
00584           Ops.push_back(DAG.getTargetConstant(C->getSExtValue(),
00585                                               Op.getValueType()));
00586       return;
00587 
00588     case 'L': // Signed 20-bit displacement (on all targets we support)
00589       if (auto *C = dyn_cast<ConstantSDNode>(Op))
00590         if (isInt<20>(C->getSExtValue()))
00591           Ops.push_back(DAG.getTargetConstant(C->getSExtValue(),
00592                                               Op.getValueType()));
00593       return;
00594 
00595     case 'M': // 0x7fffffff
00596       if (auto *C = dyn_cast<ConstantSDNode>(Op))
00597         if (C->getZExtValue() == 0x7fffffff)
00598           Ops.push_back(DAG.getTargetConstant(C->getZExtValue(),
00599                                               Op.getValueType()));
00600       return;
00601     }
00602   }
00603   TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
00604 }
00605 
00606 //===----------------------------------------------------------------------===//
00607 // Calling conventions
00608 //===----------------------------------------------------------------------===//
00609 
00610 #include "SystemZGenCallingConv.inc"
00611 
00612 bool SystemZTargetLowering::allowTruncateForTailCall(Type *FromType,
00613                                                      Type *ToType) const {
00614   return isTruncateFree(FromType, ToType);
00615 }
00616 
00617 bool SystemZTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
00618   if (!CI->isTailCall())
00619     return false;
00620   return true;
00621 }
00622 
00623 // Value is a value that has been passed to us in the location described by VA
00624 // (and so has type VA.getLocVT()).  Convert Value to VA.getValVT(), chaining
00625 // any loads onto Chain.
00626 static SDValue convertLocVTToValVT(SelectionDAG &DAG, SDLoc DL,
00627                                    CCValAssign &VA, SDValue Chain,
00628                                    SDValue Value) {
00629   // If the argument has been promoted from a smaller type, insert an
00630   // assertion to capture this.
00631   if (VA.getLocInfo() == CCValAssign::SExt)
00632     Value = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Value,
00633                         DAG.getValueType(VA.getValVT()));
00634   else if (VA.getLocInfo() == CCValAssign::ZExt)
00635     Value = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Value,
00636                         DAG.getValueType(VA.getValVT()));
00637 
00638   if (VA.isExtInLoc())
00639     Value = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Value);
00640   else if (VA.getLocInfo() == CCValAssign::Indirect)
00641     Value = DAG.getLoad(VA.getValVT(), DL, Chain, Value,
00642                         MachinePointerInfo(), false, false, false, 0);
00643   else
00644     assert(VA.getLocInfo() == CCValAssign::Full && "Unsupported getLocInfo");
00645   return Value;
00646 }
00647 
00648 // Value is a value of type VA.getValVT() that we need to copy into
00649 // the location described by VA.  Return a copy of Value converted to
00650 // VA.getValVT().  The caller is responsible for handling indirect values.
00651 static SDValue convertValVTToLocVT(SelectionDAG &DAG, SDLoc DL,
00652                                    CCValAssign &VA, SDValue Value) {
00653   switch (VA.getLocInfo()) {
00654   case CCValAssign::SExt:
00655     return DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Value);
00656   case CCValAssign::ZExt:
00657     return DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Value);
00658   case CCValAssign::AExt:
00659     return DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Value);
00660   case CCValAssign::Full:
00661     return Value;
00662   default:
00663     llvm_unreachable("Unhandled getLocInfo()");
00664   }
00665 }
00666 
00667 SDValue SystemZTargetLowering::
00668 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
00669                      const SmallVectorImpl<ISD::InputArg> &Ins,
00670                      SDLoc DL, SelectionDAG &DAG,
00671                      SmallVectorImpl<SDValue> &InVals) const {
00672   MachineFunction &MF = DAG.getMachineFunction();
00673   MachineFrameInfo *MFI = MF.getFrameInfo();
00674   MachineRegisterInfo &MRI = MF.getRegInfo();
00675   SystemZMachineFunctionInfo *FuncInfo =
00676     MF.getInfo<SystemZMachineFunctionInfo>();
00677   auto *TFL = static_cast<const SystemZFrameLowering *>(
00678       DAG.getTarget().getFrameLowering());
00679 
00680   // Assign locations to all of the incoming arguments.
00681   SmallVector<CCValAssign, 16> ArgLocs;
00682   CCState CCInfo(CallConv, IsVarArg, MF, DAG.getTarget(), ArgLocs,
00683                  *DAG.getContext());
00684   CCInfo.AnalyzeFormalArguments(Ins, CC_SystemZ);
00685 
00686   unsigned NumFixedGPRs = 0;
00687   unsigned NumFixedFPRs = 0;
00688   for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
00689     SDValue ArgValue;
00690     CCValAssign &VA = ArgLocs[I];
00691     EVT LocVT = VA.getLocVT();
00692     if (VA.isRegLoc()) {
00693       // Arguments passed in registers
00694       const TargetRegisterClass *RC;
00695       switch (LocVT.getSimpleVT().SimpleTy) {
00696       default:
00697         // Integers smaller than i64 should be promoted to i64.
00698         llvm_unreachable("Unexpected argument type");
00699       case MVT::i32:
00700         NumFixedGPRs += 1;
00701         RC = &SystemZ::GR32BitRegClass;
00702         break;
00703       case MVT::i64:
00704         NumFixedGPRs += 1;
00705         RC = &SystemZ::GR64BitRegClass;
00706         break;
00707       case MVT::f32:
00708         NumFixedFPRs += 1;
00709         RC = &SystemZ::FP32BitRegClass;
00710         break;
00711       case MVT::f64:
00712         NumFixedFPRs += 1;
00713         RC = &SystemZ::FP64BitRegClass;
00714         break;
00715       }
00716 
00717       unsigned VReg = MRI.createVirtualRegister(RC);
00718       MRI.addLiveIn(VA.getLocReg(), VReg);
00719       ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, LocVT);
00720     } else {
00721       assert(VA.isMemLoc() && "Argument not register or memory");
00722 
00723       // Create the frame index object for this incoming parameter.
00724       int FI = MFI->CreateFixedObject(LocVT.getSizeInBits() / 8,
00725                                       VA.getLocMemOffset(), true);
00726 
00727       // Create the SelectionDAG nodes corresponding to a load
00728       // from this parameter.  Unpromoted ints and floats are
00729       // passed as right-justified 8-byte values.
00730       EVT PtrVT = getPointerTy();
00731       SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
00732       if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)
00733         FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4));
00734       ArgValue = DAG.getLoad(LocVT, DL, Chain, FIN,
00735                              MachinePointerInfo::getFixedStack(FI),
00736                              false, false, false, 0);
00737     }
00738 
00739     // Convert the value of the argument register into the value that's
00740     // being passed.
00741     InVals.push_back(convertLocVTToValVT(DAG, DL, VA, Chain, ArgValue));
00742   }
00743 
00744   if (IsVarArg) {
00745     // Save the number of non-varargs registers for later use by va_start, etc.
00746     FuncInfo->setVarArgsFirstGPR(NumFixedGPRs);
00747     FuncInfo->setVarArgsFirstFPR(NumFixedFPRs);
00748 
00749     // Likewise the address (in the form of a frame index) of where the
00750     // first stack vararg would be.  The 1-byte size here is arbitrary.
00751     int64_t StackSize = CCInfo.getNextStackOffset();
00752     FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize, true));
00753 
00754     // ...and a similar frame index for the caller-allocated save area
00755     // that will be used to store the incoming registers.
00756     int64_t RegSaveOffset = TFL->getOffsetOfLocalArea();
00757     unsigned RegSaveIndex = MFI->CreateFixedObject(1, RegSaveOffset, true);
00758     FuncInfo->setRegSaveFrameIndex(RegSaveIndex);
00759 
00760     // Store the FPR varargs in the reserved frame slots.  (We store the
00761     // GPRs as part of the prologue.)
00762     if (NumFixedFPRs < SystemZ::NumArgFPRs) {
00763       SDValue MemOps[SystemZ::NumArgFPRs];
00764       for (unsigned I = NumFixedFPRs; I < SystemZ::NumArgFPRs; ++I) {
00765         unsigned Offset = TFL->getRegSpillOffset(SystemZ::ArgFPRs[I]);
00766         int FI = MFI->CreateFixedObject(8, RegSaveOffset + Offset, true);
00767         SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
00768         unsigned VReg = MF.addLiveIn(SystemZ::ArgFPRs[I],
00769                                      &SystemZ::FP64BitRegClass);
00770         SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f64);
00771         MemOps[I] = DAG.getStore(ArgValue.getValue(1), DL, ArgValue, FIN,
00772                                  MachinePointerInfo::getFixedStack(FI),
00773                                  false, false, 0);
00774 
00775       }
00776       // Join the stores, which are independent of one another.
00777       Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
00778                           makeArrayRef(&MemOps[NumFixedFPRs],
00779                                        SystemZ::NumArgFPRs-NumFixedFPRs));
00780     }
00781   }
00782 
00783   return Chain;
00784 }
00785 
00786 static bool canUseSiblingCall(CCState ArgCCInfo,
00787                               SmallVectorImpl<CCValAssign> &ArgLocs) {
00788   // Punt if there are any indirect or stack arguments, or if the call
00789   // needs the call-saved argument register R6.
00790   for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
00791     CCValAssign &VA = ArgLocs[I];
00792     if (VA.getLocInfo() == CCValAssign::Indirect)
00793       return false;
00794     if (!VA.isRegLoc())
00795       return false;
00796     unsigned Reg = VA.getLocReg();
00797     if (Reg == SystemZ::R6H || Reg == SystemZ::R6L || Reg == SystemZ::R6D)
00798       return false;
00799   }
00800   return true;
00801 }
00802 
00803 SDValue
00804 SystemZTargetLowering::LowerCall(CallLoweringInfo &CLI,
00805                                  SmallVectorImpl<SDValue> &InVals) const {
00806   SelectionDAG &DAG = CLI.DAG;
00807   SDLoc &DL = CLI.DL;
00808   SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
00809   SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
00810   SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
00811   SDValue Chain = CLI.Chain;
00812   SDValue Callee = CLI.Callee;
00813   bool &IsTailCall = CLI.IsTailCall;
00814   CallingConv::ID CallConv = CLI.CallConv;
00815   bool IsVarArg = CLI.IsVarArg;
00816   MachineFunction &MF = DAG.getMachineFunction();
00817   EVT PtrVT = getPointerTy();
00818 
00819   // Analyze the operands of the call, assigning locations to each operand.
00820   SmallVector<CCValAssign, 16> ArgLocs;
00821   CCState ArgCCInfo(CallConv, IsVarArg, MF, DAG.getTarget(), ArgLocs,
00822                     *DAG.getContext());
00823   ArgCCInfo.AnalyzeCallOperands(Outs, CC_SystemZ);
00824 
00825   // We don't support GuaranteedTailCallOpt, only automatically-detected
00826   // sibling calls.
00827   if (IsTailCall && !canUseSiblingCall(ArgCCInfo, ArgLocs))
00828     IsTailCall = false;
00829 
00830   // Get a count of how many bytes are to be pushed on the stack.
00831   unsigned NumBytes = ArgCCInfo.getNextStackOffset();
00832 
00833   // Mark the start of the call.
00834   if (!IsTailCall)
00835     Chain = DAG.getCALLSEQ_START(Chain, DAG.getConstant(NumBytes, PtrVT, true),
00836                                  DL);
00837 
00838   // Copy argument values to their designated locations.
00839   SmallVector<std::pair<unsigned, SDValue>, 9> RegsToPass;
00840   SmallVector<SDValue, 8> MemOpChains;
00841   SDValue StackPtr;
00842   for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
00843     CCValAssign &VA = ArgLocs[I];
00844     SDValue ArgValue = OutVals[I];
00845 
00846     if (VA.getLocInfo() == CCValAssign::Indirect) {
00847       // Store the argument in a stack slot and pass its address.
00848       SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
00849       int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
00850       MemOpChains.push_back(DAG.getStore(Chain, DL, ArgValue, SpillSlot,
00851                                          MachinePointerInfo::getFixedStack(FI),
00852                                          false, false, 0));
00853       ArgValue = SpillSlot;
00854     } else
00855       ArgValue = convertValVTToLocVT(DAG, DL, VA, ArgValue);
00856 
00857     if (VA.isRegLoc())
00858       // Queue up the argument copies and emit them at the end.
00859       RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue));
00860     else {
00861       assert(VA.isMemLoc() && "Argument not register or memory");
00862 
00863       // Work out the address of the stack slot.  Unpromoted ints and
00864       // floats are passed as right-justified 8-byte values.
00865       if (!StackPtr.getNode())
00866         StackPtr = DAG.getCopyFromReg(Chain, DL, SystemZ::R15D, PtrVT);
00867       unsigned Offset = SystemZMC::CallFrameSize + VA.getLocMemOffset();
00868       if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)
00869         Offset += 4;
00870       SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr,
00871                                     DAG.getIntPtrConstant(Offset));
00872 
00873       // Emit the store.
00874       MemOpChains.push_back(DAG.getStore(Chain, DL, ArgValue, Address,
00875                                          MachinePointerInfo(),
00876                                          false, false, 0));
00877     }
00878   }
00879 
00880   // Join the stores, which are independent of one another.
00881   if (!MemOpChains.empty())
00882     Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
00883 
00884   // Accept direct calls by converting symbolic call addresses to the
00885   // associated Target* opcodes.  Force %r1 to be used for indirect
00886   // tail calls.
00887   SDValue Glue;
00888   if (auto *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
00889     Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, PtrVT);
00890     Callee = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Callee);
00891   } else if (auto *E = dyn_cast<ExternalSymbolSDNode>(Callee)) {
00892     Callee = DAG.getTargetExternalSymbol(E->getSymbol(), PtrVT);
00893     Callee = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Callee);
00894   } else if (IsTailCall) {
00895     Chain = DAG.getCopyToReg(Chain, DL, SystemZ::R1D, Callee, Glue);
00896     Glue = Chain.getValue(1);
00897     Callee = DAG.getRegister(SystemZ::R1D, Callee.getValueType());
00898   }
00899 
00900   // Build a sequence of copy-to-reg nodes, chained and glued together.
00901   for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I) {
00902     Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[I].first,
00903                              RegsToPass[I].second, Glue);
00904     Glue = Chain.getValue(1);
00905   }
00906 
00907   // The first call operand is the chain and the second is the target address.
00908   SmallVector<SDValue, 8> Ops;
00909   Ops.push_back(Chain);
00910   Ops.push_back(Callee);
00911 
00912   // Add argument registers to the end of the list so that they are
00913   // known live into the call.
00914   for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I)
00915     Ops.push_back(DAG.getRegister(RegsToPass[I].first,
00916                                   RegsToPass[I].second.getValueType()));
00917 
00918   // Add a register mask operand representing the call-preserved registers.
00919   const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
00920   const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
00921   assert(Mask && "Missing call preserved mask for calling convention");
00922   Ops.push_back(DAG.getRegisterMask(Mask));
00923 
00924   // Glue the call to the argument copies, if any.
00925   if (Glue.getNode())
00926     Ops.push_back(Glue);
00927 
00928   // Emit the call.
00929   SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
00930   if (IsTailCall)
00931     return DAG.getNode(SystemZISD::SIBCALL, DL, NodeTys, Ops);
00932   Chain = DAG.getNode(SystemZISD::CALL, DL, NodeTys, Ops);
00933   Glue = Chain.getValue(1);
00934 
00935   // Mark the end of the call, which is glued to the call itself.
00936   Chain = DAG.getCALLSEQ_END(Chain,
00937                              DAG.getConstant(NumBytes, PtrVT, true),
00938                              DAG.getConstant(0, PtrVT, true),
00939                              Glue, DL);
00940   Glue = Chain.getValue(1);
00941 
00942   // Assign locations to each value returned by this call.
00943   SmallVector<CCValAssign, 16> RetLocs;
00944   CCState RetCCInfo(CallConv, IsVarArg, MF, DAG.getTarget(), RetLocs,
00945                     *DAG.getContext());
00946   RetCCInfo.AnalyzeCallResult(Ins, RetCC_SystemZ);
00947 
00948   // Copy all of the result registers out of their specified physreg.
00949   for (unsigned I = 0, E = RetLocs.size(); I != E; ++I) {
00950     CCValAssign &VA = RetLocs[I];
00951 
00952     // Copy the value out, gluing the copy to the end of the call sequence.
00953     SDValue RetValue = DAG.getCopyFromReg(Chain, DL, VA.getLocReg(),
00954                                           VA.getLocVT(), Glue);
00955     Chain = RetValue.getValue(1);
00956     Glue = RetValue.getValue(2);
00957 
00958     // Convert the value of the return register into the value that's
00959     // being returned.
00960     InVals.push_back(convertLocVTToValVT(DAG, DL, VA, Chain, RetValue));
00961   }
00962 
00963   return Chain;
00964 }
00965 
00966 SDValue
00967 SystemZTargetLowering::LowerReturn(SDValue Chain,
00968                                    CallingConv::ID CallConv, bool IsVarArg,
00969                                    const SmallVectorImpl<ISD::OutputArg> &Outs,
00970                                    const SmallVectorImpl<SDValue> &OutVals,
00971                                    SDLoc DL, SelectionDAG &DAG) const {
00972   MachineFunction &MF = DAG.getMachineFunction();
00973 
00974   // Assign locations to each returned value.
00975   SmallVector<CCValAssign, 16> RetLocs;
00976   CCState RetCCInfo(CallConv, IsVarArg, MF, DAG.getTarget(), RetLocs,
00977                     *DAG.getContext());
00978   RetCCInfo.AnalyzeReturn(Outs, RetCC_SystemZ);
00979 
00980   // Quick exit for void returns
00981   if (RetLocs.empty())
00982     return DAG.getNode(SystemZISD::RET_FLAG, DL, MVT::Other, Chain);
00983 
00984   // Copy the result values into the output registers.
00985   SDValue Glue;
00986   SmallVector<SDValue, 4> RetOps;
00987   RetOps.push_back(Chain);
00988   for (unsigned I = 0, E = RetLocs.size(); I != E; ++I) {
00989     CCValAssign &VA = RetLocs[I];
00990     SDValue RetValue = OutVals[I];
00991 
00992     // Make the return register live on exit.
00993     assert(VA.isRegLoc() && "Can only return in registers!");
00994 
00995     // Promote the value as required.
00996     RetValue = convertValVTToLocVT(DAG, DL, VA, RetValue);
00997 
00998     // Chain and glue the copies together.
00999     unsigned Reg = VA.getLocReg();
01000     Chain = DAG.getCopyToReg(Chain, DL, Reg, RetValue, Glue);
01001     Glue = Chain.getValue(1);
01002     RetOps.push_back(DAG.getRegister(Reg, VA.getLocVT()));
01003   }
01004 
01005   // Update chain and glue.
01006   RetOps[0] = Chain;
01007   if (Glue.getNode())
01008     RetOps.push_back(Glue);
01009 
01010   return DAG.getNode(SystemZISD::RET_FLAG, DL, MVT::Other, RetOps);
01011 }
01012 
01013 SDValue SystemZTargetLowering::
01014 prepareVolatileOrAtomicLoad(SDValue Chain, SDLoc DL, SelectionDAG &DAG) const {
01015   return DAG.getNode(SystemZISD::SERIALIZE, DL, MVT::Other, Chain);
01016 }
01017 
01018 // CC is a comparison that will be implemented using an integer or
01019 // floating-point comparison.  Return the condition code mask for
01020 // a branch on true.  In the integer case, CCMASK_CMP_UO is set for
01021 // unsigned comparisons and clear for signed ones.  In the floating-point
01022 // case, CCMASK_CMP_UO has its normal mask meaning (unordered).
01023 static unsigned CCMaskForCondCode(ISD::CondCode CC) {
01024 #define CONV(X) \
01025   case ISD::SET##X: return SystemZ::CCMASK_CMP_##X; \
01026   case ISD::SETO##X: return SystemZ::CCMASK_CMP_##X; \
01027   case ISD::SETU##X: return SystemZ::CCMASK_CMP_UO | SystemZ::CCMASK_CMP_##X
01028 
01029   switch (CC) {
01030   default:
01031     llvm_unreachable("Invalid integer condition!");
01032 
01033   CONV(EQ);
01034   CONV(NE);
01035   CONV(GT);
01036   CONV(GE);
01037   CONV(LT);
01038   CONV(LE);
01039 
01040   case ISD::SETO:  return SystemZ::CCMASK_CMP_O;
01041   case ISD::SETUO: return SystemZ::CCMASK_CMP_UO;
01042   }
01043 #undef CONV
01044 }
01045 
01046 // Return a sequence for getting a 1 from an IPM result when CC has a
01047 // value in CCMask and a 0 when CC has a value in CCValid & ~CCMask.
01048 // The handling of CC values outside CCValid doesn't matter.
01049 static IPMConversion getIPMConversion(unsigned CCValid, unsigned CCMask) {
01050   // Deal with cases where the result can be taken directly from a bit
01051   // of the IPM result.
01052   if (CCMask == (CCValid & (SystemZ::CCMASK_1 | SystemZ::CCMASK_3)))
01053     return IPMConversion(0, 0, SystemZ::IPM_CC);
01054   if (CCMask == (CCValid & (SystemZ::CCMASK_2 | SystemZ::CCMASK_3)))
01055     return IPMConversion(0, 0, SystemZ::IPM_CC + 1);
01056 
01057   // Deal with cases where we can add a value to force the sign bit
01058   // to contain the right value.  Putting the bit in 31 means we can
01059   // use SRL rather than RISBG(L), and also makes it easier to get a
01060   // 0/-1 value, so it has priority over the other tests below.
01061   //
01062   // These sequences rely on the fact that the upper two bits of the
01063   // IPM result are zero.
01064   uint64_t TopBit = uint64_t(1) << 31;
01065   if (CCMask == (CCValid & SystemZ::CCMASK_0))
01066     return IPMConversion(0, -(1 << SystemZ::IPM_CC), 31);
01067   if (CCMask == (CCValid & (SystemZ::CCMASK_0 | SystemZ::CCMASK_1)))
01068     return IPMConversion(0, -(2 << SystemZ::IPM_CC), 31);
01069   if (CCMask == (CCValid & (SystemZ::CCMASK_0
01070                             | SystemZ::CCMASK_1
01071                             | SystemZ::CCMASK_2)))
01072     return IPMConversion(0, -(3 << SystemZ::IPM_CC), 31);
01073   if (CCMask == (CCValid & SystemZ::CCMASK_3))
01074     return IPMConversion(0, TopBit - (3 << SystemZ::IPM_CC), 31);
01075   if (CCMask == (CCValid & (SystemZ::CCMASK_1
01076                             | SystemZ::CCMASK_2
01077                             | SystemZ::CCMASK_3)))
01078     return IPMConversion(0, TopBit - (1 << SystemZ::IPM_CC), 31);
01079 
01080   // Next try inverting the value and testing a bit.  0/1 could be
01081   // handled this way too, but we dealt with that case above.
01082   if (CCMask == (CCValid & (SystemZ::CCMASK_0 | SystemZ::CCMASK_2)))
01083     return IPMConversion(-1, 0, SystemZ::IPM_CC);
01084 
01085   // Handle cases where adding a value forces a non-sign bit to contain
01086   // the right value.
01087   if (CCMask == (CCValid & (SystemZ::CCMASK_1 | SystemZ::CCMASK_2)))
01088     return IPMConversion(0, 1 << SystemZ::IPM_CC, SystemZ::IPM_CC + 1);
01089   if (CCMask == (CCValid & (SystemZ::CCMASK_0 | SystemZ::CCMASK_3)))
01090     return IPMConversion(0, -(1 << SystemZ::IPM_CC), SystemZ::IPM_CC + 1);
01091 
01092   // The remaining cases are 1, 2, 0/1/3 and 0/2/3.  All these are
01093   // can be done by inverting the low CC bit and applying one of the
01094   // sign-based extractions above.
01095   if (CCMask == (CCValid & SystemZ::CCMASK_1))
01096     return IPMConversion(1 << SystemZ::IPM_CC, -(1 << SystemZ::IPM_CC), 31);
01097   if (CCMask == (CCValid & SystemZ::CCMASK_2))
01098     return IPMConversion(1 << SystemZ::IPM_CC,
01099                          TopBit - (3 << SystemZ::IPM_CC), 31);
01100   if (CCMask == (CCValid & (SystemZ::CCMASK_0
01101                             | SystemZ::CCMASK_1
01102                             | SystemZ::CCMASK_3)))
01103     return IPMConversion(1 << SystemZ::IPM_CC, -(3 << SystemZ::IPM_CC), 31);
01104   if (CCMask == (CCValid & (SystemZ::CCMASK_0
01105                             | SystemZ::CCMASK_2
01106                             | SystemZ::CCMASK_3)))
01107     return IPMConversion(1 << SystemZ::IPM_CC,
01108                          TopBit - (1 << SystemZ::IPM_CC), 31);
01109 
01110   llvm_unreachable("Unexpected CC combination");
01111 }
01112 
01113 // If C can be converted to a comparison against zero, adjust the operands
01114 // as necessary.
01115 static void adjustZeroCmp(SelectionDAG &DAG, Comparison &C) {
01116   if (C.ICmpType == SystemZICMP::UnsignedOnly)
01117     return;
01118 
01119   auto *ConstOp1 = dyn_cast<ConstantSDNode>(C.Op1.getNode());
01120   if (!ConstOp1)
01121     return;
01122 
01123   int64_t Value = ConstOp1->getSExtValue();
01124   if ((Value == -1 && C.CCMask == SystemZ::CCMASK_CMP_GT) ||
01125       (Value == -1 && C.CCMask == SystemZ::CCMASK_CMP_LE) ||
01126       (Value == 1 && C.CCMask == SystemZ::CCMASK_CMP_LT) ||
01127       (Value == 1 && C.CCMask == SystemZ::CCMASK_CMP_GE)) {
01128     C.CCMask ^= SystemZ::CCMASK_CMP_EQ;
01129     C.Op1 = DAG.getConstant(0, C.Op1.getValueType());
01130   }
01131 }
01132 
01133 // If a comparison described by C is suitable for CLI(Y), CHHSI or CLHHSI,
01134 // adjust the operands as necessary.
01135 static void adjustSubwordCmp(SelectionDAG &DAG, Comparison &C) {
01136   // For us to make any changes, it must a comparison between a single-use
01137   // load and a constant.
01138   if (!C.Op0.hasOneUse() ||
01139       C.Op0.getOpcode() != ISD::LOAD ||
01140       C.Op1.getOpcode() != ISD::Constant)
01141     return;
01142 
01143   // We must have an 8- or 16-bit load.
01144   auto *Load = cast<LoadSDNode>(C.Op0);
01145   unsigned NumBits = Load->getMemoryVT().getStoreSizeInBits();
01146   if (NumBits != 8 && NumBits != 16)
01147     return;
01148 
01149   // The load must be an extending one and the constant must be within the
01150   // range of the unextended value.
01151   auto *ConstOp1 = cast<ConstantSDNode>(C.Op1);
01152   uint64_t Value = ConstOp1->getZExtValue();
01153   uint64_t Mask = (1 << NumBits) - 1;
01154   if (Load->getExtensionType() == ISD::SEXTLOAD) {
01155     // Make sure that ConstOp1 is in range of C.Op0.
01156     int64_t SignedValue = ConstOp1->getSExtValue();
01157     if (uint64_t(SignedValue) + (uint64_t(1) << (NumBits - 1)) > Mask)
01158       return;
01159     if (C.ICmpType != SystemZICMP::SignedOnly) {
01160       // Unsigned comparison between two sign-extended values is equivalent
01161       // to unsigned comparison between two zero-extended values.
01162       Value &= Mask;
01163     } else if (NumBits == 8) {
01164       // Try to treat the comparison as unsigned, so that we can use CLI.
01165       // Adjust CCMask and Value as necessary.
01166       if (Value == 0 && C.CCMask == SystemZ::CCMASK_CMP_LT)
01167         // Test whether the high bit of the byte is set.
01168         Value = 127, C.CCMask = SystemZ::CCMASK_CMP_GT;
01169       else if (Value == 0 && C.CCMask == SystemZ::CCMASK_CMP_GE)
01170         // Test whether the high bit of the byte is clear.
01171         Value = 128, C.CCMask = SystemZ::CCMASK_CMP_LT;
01172       else
01173         // No instruction exists for this combination.
01174         return;
01175       C.ICmpType = SystemZICMP::UnsignedOnly;
01176     }
01177   } else if (Load->getExtensionType() == ISD::ZEXTLOAD) {
01178     if (Value > Mask)
01179       return;
01180     assert(C.ICmpType == SystemZICMP::Any &&
01181            "Signedness shouldn't matter here.");
01182   } else
01183     return;
01184 
01185   // Make sure that the first operand is an i32 of the right extension type.
01186   ISD::LoadExtType ExtType = (C.ICmpType == SystemZICMP::SignedOnly ?
01187                               ISD::SEXTLOAD :
01188                               ISD::ZEXTLOAD);
01189   if (C.Op0.getValueType() != MVT::i32 ||
01190       Load->getExtensionType() != ExtType)
01191     C.Op0 = DAG.getExtLoad(ExtType, SDLoc(Load), MVT::i32,
01192                            Load->getChain(), Load->getBasePtr(),
01193                            Load->getPointerInfo(), Load->getMemoryVT(),
01194                            Load->isVolatile(), Load->isNonTemporal(),
01195                            Load->getAlignment());
01196 
01197   // Make sure that the second operand is an i32 with the right value.
01198   if (C.Op1.getValueType() != MVT::i32 ||
01199       Value != ConstOp1->getZExtValue())
01200     C.Op1 = DAG.getConstant(Value, MVT::i32);
01201 }
01202 
01203 // Return true if Op is either an unextended load, or a load suitable
01204 // for integer register-memory comparisons of type ICmpType.
01205 static bool isNaturalMemoryOperand(SDValue Op, unsigned ICmpType) {
01206   auto *Load = dyn_cast<LoadSDNode>(Op.getNode());
01207   if (Load) {
01208     // There are no instructions to compare a register with a memory byte.
01209     if (Load->getMemoryVT() == MVT::i8)
01210       return false;
01211     // Otherwise decide on extension type.
01212     switch (Load->getExtensionType()) {
01213     case ISD::NON_EXTLOAD:
01214       return true;
01215     case ISD::SEXTLOAD:
01216       return ICmpType != SystemZICMP::UnsignedOnly;
01217     case ISD::ZEXTLOAD:
01218       return ICmpType != SystemZICMP::SignedOnly;
01219     default:
01220       break;
01221     }
01222   }
01223   return false;
01224 }
01225 
01226 // Return true if it is better to swap the operands of C.
01227 static bool shouldSwapCmpOperands(const Comparison &C) {
01228   // Leave f128 comparisons alone, since they have no memory forms.
01229   if (C.Op0.getValueType() == MVT::f128)
01230     return false;
01231 
01232   // Always keep a floating-point constant second, since comparisons with
01233   // zero can use LOAD TEST and comparisons with other constants make a
01234   // natural memory operand.
01235   if (isa<ConstantFPSDNode>(C.Op1))
01236     return false;
01237 
01238   // Never swap comparisons with zero since there are many ways to optimize
01239   // those later.
01240   auto *ConstOp1 = dyn_cast<ConstantSDNode>(C.Op1);
01241   if (ConstOp1 && ConstOp1->getZExtValue() == 0)
01242     return false;
01243 
01244   // Also keep natural memory operands second if the loaded value is
01245   // only used here.  Several comparisons have memory forms.
01246   if (isNaturalMemoryOperand(C.Op1, C.ICmpType) && C.Op1.hasOneUse())
01247     return false;
01248 
01249   // Look for cases where Cmp0 is a single-use load and Cmp1 isn't.
01250   // In that case we generally prefer the memory to be second.
01251   if (isNaturalMemoryOperand(C.Op0, C.ICmpType) && C.Op0.hasOneUse()) {
01252     // The only exceptions are when the second operand is a constant and
01253     // we can use things like CHHSI.
01254     if (!ConstOp1)
01255       return true;
01256     // The unsigned memory-immediate instructions can handle 16-bit
01257     // unsigned integers.
01258     if (C.ICmpType != SystemZICMP::SignedOnly &&
01259         isUInt<16>(ConstOp1->getZExtValue()))
01260       return false;
01261     // The signed memory-immediate instructions can handle 16-bit
01262     // signed integers.
01263     if (C.ICmpType != SystemZICMP::UnsignedOnly &&
01264         isInt<16>(ConstOp1->getSExtValue()))
01265       return false;
01266     return true;
01267   }
01268 
01269   // Try to promote the use of CGFR and CLGFR.
01270   unsigned Opcode0 = C.Op0.getOpcode();
01271   if (C.ICmpType != SystemZICMP::UnsignedOnly && Opcode0 == ISD::SIGN_EXTEND)
01272     return true;
01273   if (C.ICmpType != SystemZICMP::SignedOnly && Opcode0 == ISD::ZERO_EXTEND)
01274     return true;
01275   if (C.ICmpType != SystemZICMP::SignedOnly &&
01276       Opcode0 == ISD::AND &&
01277       C.Op0.getOperand(1).getOpcode() == ISD::Constant &&
01278       cast<ConstantSDNode>(C.Op0.getOperand(1))->getZExtValue() == 0xffffffff)
01279     return true;
01280 
01281   return false;
01282 }
01283 
01284 // Return a version of comparison CC mask CCMask in which the LT and GT
01285 // actions are swapped.
01286 static unsigned reverseCCMask(unsigned CCMask) {
01287   return ((CCMask & SystemZ::CCMASK_CMP_EQ) |
01288           (CCMask & SystemZ::CCMASK_CMP_GT ? SystemZ::CCMASK_CMP_LT : 0) |
01289           (CCMask & SystemZ::CCMASK_CMP_LT ? SystemZ::CCMASK_CMP_GT : 0) |
01290           (CCMask & SystemZ::CCMASK_CMP_UO));
01291 }
01292 
01293 // Check whether C tests for equality between X and Y and whether X - Y
01294 // or Y - X is also computed.  In that case it's better to compare the
01295 // result of the subtraction against zero.
01296 static void adjustForSubtraction(SelectionDAG &DAG, Comparison &C) {
01297   if (C.CCMask == SystemZ::CCMASK_CMP_EQ ||
01298       C.CCMask == SystemZ::CCMASK_CMP_NE) {
01299     for (auto I = C.Op0->use_begin(), E = C.Op0->use_end(); I != E; ++I) {
01300       SDNode *N = *I;
01301       if (N->getOpcode() == ISD::SUB &&
01302           ((N->getOperand(0) == C.Op0 && N->getOperand(1) == C.Op1) ||
01303            (N->getOperand(0) == C.Op1 && N->getOperand(1) == C.Op0))) {
01304         C.Op0 = SDValue(N, 0);
01305         C.Op1 = DAG.getConstant(0, N->getValueType(0));
01306         return;
01307       }
01308     }
01309   }
01310 }
01311 
01312 // Check whether C compares a floating-point value with zero and if that
01313 // floating-point value is also negated.  In this case we can use the
01314 // negation to set CC, so avoiding separate LOAD AND TEST and
01315 // LOAD (NEGATIVE/COMPLEMENT) instructions.
01316 static void adjustForFNeg(Comparison &C) {
01317   auto *C1 = dyn_cast<ConstantFPSDNode>(C.Op1);
01318   if (C1 && C1->isZero()) {
01319     for (auto I = C.Op0->use_begin(), E = C.Op0->use_end(); I != E; ++I) {
01320       SDNode *N = *I;
01321       if (N->getOpcode() == ISD::FNEG) {
01322         C.Op0 = SDValue(N, 0);
01323         C.CCMask = reverseCCMask(C.CCMask);
01324         return;
01325       }
01326     }
01327   }
01328 }
01329 
01330 // Check whether C compares (shl X, 32) with 0 and whether X is
01331 // also sign-extended.  In that case it is better to test the result
01332 // of the sign extension using LTGFR.
01333 //
01334 // This case is important because InstCombine transforms a comparison
01335 // with (sext (trunc X)) into a comparison with (shl X, 32).
01336 static void adjustForLTGFR(Comparison &C) {
01337   // Check for a comparison between (shl X, 32) and 0.
01338   if (C.Op0.getOpcode() == ISD::SHL &&
01339       C.Op0.getValueType() == MVT::i64 &&
01340       C.Op1.getOpcode() == ISD::Constant &&
01341       cast<ConstantSDNode>(C.Op1)->getZExtValue() == 0) {
01342     auto *C1 = dyn_cast<ConstantSDNode>(C.Op0.getOperand(1));
01343     if (C1 && C1->getZExtValue() == 32) {
01344       SDValue ShlOp0 = C.Op0.getOperand(0);
01345       // See whether X has any SIGN_EXTEND_INREG uses.
01346       for (auto I = ShlOp0->use_begin(), E = ShlOp0->use_end(); I != E; ++I) {
01347         SDNode *N = *I;
01348         if (N->getOpcode() == ISD::SIGN_EXTEND_INREG &&
01349             cast<VTSDNode>(N->getOperand(1))->getVT() == MVT::i32) {
01350           C.Op0 = SDValue(N, 0);
01351           return;
01352         }
01353       }
01354     }
01355   }
01356 }
01357 
01358 // If C compares the truncation of an extending load, try to compare
01359 // the untruncated value instead.  This exposes more opportunities to
01360 // reuse CC.
01361 static void adjustICmpTruncate(SelectionDAG &DAG, Comparison &C) {
01362   if (C.Op0.getOpcode() == ISD::TRUNCATE &&
01363       C.Op0.getOperand(0).getOpcode() == ISD::LOAD &&
01364       C.Op1.getOpcode() == ISD::Constant &&
01365       cast<ConstantSDNode>(C.Op1)->getZExtValue() == 0) {
01366     auto *L = cast<LoadSDNode>(C.Op0.getOperand(0));
01367     if (L->getMemoryVT().getStoreSizeInBits()
01368         <= C.Op0.getValueType().getSizeInBits()) {
01369       unsigned Type = L->getExtensionType();
01370       if ((Type == ISD::ZEXTLOAD && C.ICmpType != SystemZICMP::SignedOnly) ||
01371           (Type == ISD::SEXTLOAD && C.ICmpType != SystemZICMP::UnsignedOnly)) {
01372         C.Op0 = C.Op0.getOperand(0);
01373         C.Op1 = DAG.getConstant(0, C.Op0.getValueType());
01374       }
01375     }
01376   }
01377 }
01378 
01379 // Return true if shift operation N has an in-range constant shift value.
01380 // Store it in ShiftVal if so.
01381 static bool isSimpleShift(SDValue N, unsigned &ShiftVal) {
01382   auto *Shift = dyn_cast<ConstantSDNode>(N.getOperand(1));
01383   if (!Shift)
01384     return false;
01385 
01386   uint64_t Amount = Shift->getZExtValue();
01387   if (Amount >= N.getValueType().getSizeInBits())
01388     return false;
01389 
01390   ShiftVal = Amount;
01391   return true;
01392 }
01393 
01394 // Check whether an AND with Mask is suitable for a TEST UNDER MASK
01395 // instruction and whether the CC value is descriptive enough to handle
01396 // a comparison of type Opcode between the AND result and CmpVal.
01397 // CCMask says which comparison result is being tested and BitSize is
01398 // the number of bits in the operands.  If TEST UNDER MASK can be used,
01399 // return the corresponding CC mask, otherwise return 0.
01400 static unsigned getTestUnderMaskCond(unsigned BitSize, unsigned CCMask,
01401                                      uint64_t Mask, uint64_t CmpVal,
01402                                      unsigned ICmpType) {
01403   assert(Mask != 0 && "ANDs with zero should have been removed by now");
01404 
01405   // Check whether the mask is suitable for TMHH, TMHL, TMLH or TMLL.
01406   if (!SystemZ::isImmLL(Mask) && !SystemZ::isImmLH(Mask) &&
01407       !SystemZ::isImmHL(Mask) && !SystemZ::isImmHH(Mask))
01408     return 0;
01409 
01410   // Work out the masks for the lowest and highest bits.
01411   unsigned HighShift = 63 - countLeadingZeros(Mask);
01412   uint64_t High = uint64_t(1) << HighShift;
01413   uint64_t Low = uint64_t(1) << countTrailingZeros(Mask);
01414 
01415   // Signed ordered comparisons are effectively unsigned if the sign
01416   // bit is dropped.
01417   bool EffectivelyUnsigned = (ICmpType != SystemZICMP::SignedOnly);
01418 
01419   // Check for equality comparisons with 0, or the equivalent.
01420   if (CmpVal == 0) {
01421     if (CCMask == SystemZ::CCMASK_CMP_EQ)
01422       return SystemZ::CCMASK_TM_ALL_0;
01423     if (CCMask == SystemZ::CCMASK_CMP_NE)
01424       return SystemZ::CCMASK_TM_SOME_1;
01425   }
01426   if (EffectivelyUnsigned && CmpVal <= Low) {
01427     if (CCMask == SystemZ::CCMASK_CMP_LT)
01428       return SystemZ::CCMASK_TM_ALL_0;
01429     if (CCMask == SystemZ::CCMASK_CMP_GE)
01430       return SystemZ::CCMASK_TM_SOME_1;
01431   }
01432   if (EffectivelyUnsigned && CmpVal < Low) {
01433     if (CCMask == SystemZ::CCMASK_CMP_LE)
01434       return SystemZ::CCMASK_TM_ALL_0;
01435     if (CCMask == SystemZ::CCMASK_CMP_GT)
01436       return SystemZ::CCMASK_TM_SOME_1;
01437   }
01438 
01439   // Check for equality comparisons with the mask, or the equivalent.
01440   if (CmpVal == Mask) {
01441     if (CCMask == SystemZ::CCMASK_CMP_EQ)
01442       return SystemZ::CCMASK_TM_ALL_1;
01443     if (CCMask == SystemZ::CCMASK_CMP_NE)
01444       return SystemZ::CCMASK_TM_SOME_0;
01445   }
01446   if (EffectivelyUnsigned && CmpVal >= Mask - Low && CmpVal < Mask) {
01447     if (CCMask == SystemZ::CCMASK_CMP_GT)
01448       return SystemZ::CCMASK_TM_ALL_1;
01449     if (CCMask == SystemZ::CCMASK_CMP_LE)
01450       return SystemZ::CCMASK_TM_SOME_0;
01451   }
01452   if (EffectivelyUnsigned && CmpVal > Mask - Low && CmpVal <= Mask) {
01453     if (CCMask == SystemZ::CCMASK_CMP_GE)
01454       return SystemZ::CCMASK_TM_ALL_1;
01455     if (CCMask == SystemZ::CCMASK_CMP_LT)
01456       return SystemZ::CCMASK_TM_SOME_0;
01457   }
01458 
01459   // Check for ordered comparisons with the top bit.
01460   if (EffectivelyUnsigned && CmpVal >= Mask - High && CmpVal < High) {
01461     if (CCMask == SystemZ::CCMASK_CMP_LE)
01462       return SystemZ::CCMASK_TM_MSB_0;
01463     if (CCMask == SystemZ::CCMASK_CMP_GT)
01464       return SystemZ::CCMASK_TM_MSB_1;
01465   }
01466   if (EffectivelyUnsigned && CmpVal > Mask - High && CmpVal <= High) {
01467     if (CCMask == SystemZ::CCMASK_CMP_LT)
01468       return SystemZ::CCMASK_TM_MSB_0;
01469     if (CCMask == SystemZ::CCMASK_CMP_GE)
01470       return SystemZ::CCMASK_TM_MSB_1;
01471   }
01472 
01473   // If there are just two bits, we can do equality checks for Low and High
01474   // as well.
01475   if (Mask == Low + High) {
01476     if (CCMask == SystemZ::CCMASK_CMP_EQ && CmpVal == Low)
01477       return SystemZ::CCMASK_TM_MIXED_MSB_0;
01478     if (CCMask == SystemZ::CCMASK_CMP_NE && CmpVal == Low)
01479       return SystemZ::CCMASK_TM_MIXED_MSB_0 ^ SystemZ::CCMASK_ANY;
01480     if (CCMask == SystemZ::CCMASK_CMP_EQ && CmpVal == High)
01481       return SystemZ::CCMASK_TM_MIXED_MSB_1;
01482     if (CCMask == SystemZ::CCMASK_CMP_NE && CmpVal == High)
01483       return SystemZ::CCMASK_TM_MIXED_MSB_1 ^ SystemZ::CCMASK_ANY;
01484   }
01485 
01486   // Looks like we've exhausted our options.
01487   return 0;
01488 }
01489 
01490 // See whether C can be implemented as a TEST UNDER MASK instruction.
01491 // Update the arguments with the TM version if so.
01492 static void adjustForTestUnderMask(SelectionDAG &DAG, Comparison &C) {
01493   // Check that we have a comparison with a constant.
01494   auto *ConstOp1 = dyn_cast<ConstantSDNode>(C.Op1);
01495   if (!ConstOp1)
01496     return;
01497   uint64_t CmpVal = ConstOp1->getZExtValue();
01498 
01499   // Check whether the nonconstant input is an AND with a constant mask.
01500   Comparison NewC(C);
01501   uint64_t MaskVal;
01502   ConstantSDNode *Mask = nullptr;
01503   if (C.Op0.getOpcode() == ISD::AND) {
01504     NewC.Op0 = C.Op0.getOperand(0);
01505     NewC.Op1 = C.Op0.getOperand(1);
01506     Mask = dyn_cast<ConstantSDNode>(NewC.Op1);
01507     if (!Mask)
01508       return;
01509     MaskVal = Mask->getZExtValue();
01510   } else {
01511     // There is no instruction to compare with a 64-bit immediate
01512     // so use TMHH instead if possible.  We need an unsigned ordered
01513     // comparison with an i64 immediate.
01514     if (NewC.Op0.getValueType() != MVT::i64 ||
01515         NewC.CCMask == SystemZ::CCMASK_CMP_EQ ||
01516         NewC.CCMask == SystemZ::CCMASK_CMP_NE ||
01517         NewC.ICmpType == SystemZICMP::SignedOnly)
01518       return;
01519     // Convert LE and GT comparisons into LT and GE.
01520     if (NewC.CCMask == SystemZ::CCMASK_CMP_LE ||
01521         NewC.CCMask == SystemZ::CCMASK_CMP_GT) {
01522       if (CmpVal == uint64_t(-1))
01523         return;
01524       CmpVal += 1;
01525       NewC.CCMask ^= SystemZ::CCMASK_CMP_EQ;
01526     }
01527     // If the low N bits of Op1 are zero than the low N bits of Op0 can
01528     // be masked off without changing the result.
01529     MaskVal = -(CmpVal & -CmpVal);
01530     NewC.ICmpType = SystemZICMP::UnsignedOnly;
01531   }
01532 
01533   // Check whether the combination of mask, comparison value and comparison
01534   // type are suitable.
01535   unsigned BitSize = NewC.Op0.getValueType().getSizeInBits();
01536   unsigned NewCCMask, ShiftVal;
01537   if (NewC.ICmpType != SystemZICMP::SignedOnly &&
01538       NewC.Op0.getOpcode() == ISD::SHL &&
01539       isSimpleShift(NewC.Op0, ShiftVal) &&
01540       (NewCCMask = getTestUnderMaskCond(BitSize, NewC.CCMask,
01541                                         MaskVal >> ShiftVal,
01542                                         CmpVal >> ShiftVal,
01543                                         SystemZICMP::Any))) {
01544     NewC.Op0 = NewC.Op0.getOperand(0);
01545     MaskVal >>= ShiftVal;
01546   } else if (NewC.ICmpType != SystemZICMP::SignedOnly &&
01547              NewC.Op0.getOpcode() == ISD::SRL &&
01548              isSimpleShift(NewC.Op0, ShiftVal) &&
01549              (NewCCMask = getTestUnderMaskCond(BitSize, NewC.CCMask,
01550                                                MaskVal << ShiftVal,
01551                                                CmpVal << ShiftVal,
01552                                                SystemZICMP::UnsignedOnly))) {
01553     NewC.Op0 = NewC.Op0.getOperand(0);
01554     MaskVal <<= ShiftVal;
01555   } else {
01556     NewCCMask = getTestUnderMaskCond(BitSize, NewC.CCMask, MaskVal, CmpVal,
01557                                      NewC.ICmpType);
01558     if (!NewCCMask)
01559       return;
01560   }
01561 
01562   // Go ahead and make the change.
01563   C.Opcode = SystemZISD::TM;
01564   C.Op0 = NewC.Op0;
01565   if (Mask && Mask->getZExtValue() == MaskVal)
01566     C.Op1 = SDValue(Mask, 0);
01567   else
01568     C.Op1 = DAG.getConstant(MaskVal, C.Op0.getValueType());
01569   C.CCValid = SystemZ::CCMASK_TM;
01570   C.CCMask = NewCCMask;
01571 }
01572 
01573 // Decide how to implement a comparison of type Cond between CmpOp0 with CmpOp1.
01574 static Comparison getCmp(SelectionDAG &DAG, SDValue CmpOp0, SDValue CmpOp1,
01575                          ISD::CondCode Cond) {
01576   Comparison C(CmpOp0, CmpOp1);
01577   C.CCMask = CCMaskForCondCode(Cond);
01578   if (C.Op0.getValueType().isFloatingPoint()) {
01579     C.CCValid = SystemZ::CCMASK_FCMP;
01580     C.Opcode = SystemZISD::FCMP;
01581     adjustForFNeg(C);
01582   } else {
01583     C.CCValid = SystemZ::CCMASK_ICMP;
01584     C.Opcode = SystemZISD::ICMP;
01585     // Choose the type of comparison.  Equality and inequality tests can
01586     // use either signed or unsigned comparisons.  The choice also doesn't
01587     // matter if both sign bits are known to be clear.  In those cases we
01588     // want to give the main isel code the freedom to choose whichever
01589     // form fits best.
01590     if (C.CCMask == SystemZ::CCMASK_CMP_EQ ||
01591         C.CCMask == SystemZ::CCMASK_CMP_NE ||
01592         (DAG.SignBitIsZero(C.Op0) && DAG.SignBitIsZero(C.Op1)))
01593       C.ICmpType = SystemZICMP::Any;
01594     else if (C.CCMask & SystemZ::CCMASK_CMP_UO)
01595       C.ICmpType = SystemZICMP::UnsignedOnly;
01596     else
01597       C.ICmpType = SystemZICMP::SignedOnly;
01598     C.CCMask &= ~SystemZ::CCMASK_CMP_UO;
01599     adjustZeroCmp(DAG, C);
01600     adjustSubwordCmp(DAG, C);
01601     adjustForSubtraction(DAG, C);
01602     adjustForLTGFR(C);
01603     adjustICmpTruncate(DAG, C);
01604   }
01605 
01606   if (shouldSwapCmpOperands(C)) {
01607     std::swap(C.Op0, C.Op1);
01608     C.CCMask = reverseCCMask(C.CCMask);
01609   }
01610 
01611   adjustForTestUnderMask(DAG, C);
01612   return C;
01613 }
01614 
01615 // Emit the comparison instruction described by C.
01616 static SDValue emitCmp(SelectionDAG &DAG, SDLoc DL, Comparison &C) {
01617   if (C.Opcode == SystemZISD::ICMP)
01618     return DAG.getNode(SystemZISD::ICMP, DL, MVT::Glue, C.Op0, C.Op1,
01619                        DAG.getConstant(C.ICmpType, MVT::i32));
01620   if (C.Opcode == SystemZISD::TM) {
01621     bool RegisterOnly = (bool(C.CCMask & SystemZ::CCMASK_TM_MIXED_MSB_0) !=
01622                          bool(C.CCMask & SystemZ::CCMASK_TM_MIXED_MSB_1));
01623     return DAG.getNode(SystemZISD::TM, DL, MVT::Glue, C.Op0, C.Op1,
01624                        DAG.getConstant(RegisterOnly, MVT::i32));
01625   }
01626   return DAG.getNode(C.Opcode, DL, MVT::Glue, C.Op0, C.Op1);
01627 }
01628 
01629 // Implement a 32-bit *MUL_LOHI operation by extending both operands to
01630 // 64 bits.  Extend is the extension type to use.  Store the high part
01631 // in Hi and the low part in Lo.
01632 static void lowerMUL_LOHI32(SelectionDAG &DAG, SDLoc DL,
01633                             unsigned Extend, SDValue Op0, SDValue Op1,
01634                             SDValue &Hi, SDValue &Lo) {
01635   Op0 = DAG.getNode(Extend, DL, MVT::i64, Op0);
01636   Op1 = DAG.getNode(Extend, DL, MVT::i64, Op1);
01637   SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, Op0, Op1);
01638   Hi = DAG.getNode(ISD::SRL, DL, MVT::i64, Mul, DAG.getConstant(32, MVT::i64));
01639   Hi = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Hi);
01640   Lo = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mul);
01641 }
01642 
01643 // Lower a binary operation that produces two VT results, one in each
01644 // half of a GR128 pair.  Op0 and Op1 are the VT operands to the operation,
01645 // Extend extends Op0 to a GR128, and Opcode performs the GR128 operation
01646 // on the extended Op0 and (unextended) Op1.  Store the even register result
01647 // in Even and the odd register result in Odd.
01648 static void lowerGR128Binary(SelectionDAG &DAG, SDLoc DL, EVT VT,
01649                              unsigned Extend, unsigned Opcode,
01650                              SDValue Op0, SDValue Op1,
01651                              SDValue &Even, SDValue &Odd) {
01652   SDNode *In128 = DAG.getMachineNode(Extend, DL, MVT::Untyped, Op0);
01653   SDValue Result = DAG.getNode(Opcode, DL, MVT::Untyped,
01654                                SDValue(In128, 0), Op1);
01655   bool Is32Bit = is32Bit(VT);
01656   Even = DAG.getTargetExtractSubreg(SystemZ::even128(Is32Bit), DL, VT, Result);
01657   Odd = DAG.getTargetExtractSubreg(SystemZ::odd128(Is32Bit), DL, VT, Result);
01658 }
01659 
01660 // Return an i32 value that is 1 if the CC value produced by Glue is
01661 // in the mask CCMask and 0 otherwise.  CC is known to have a value
01662 // in CCValid, so other values can be ignored.
01663 static SDValue emitSETCC(SelectionDAG &DAG, SDLoc DL, SDValue Glue,
01664                          unsigned CCValid, unsigned CCMask) {
01665   IPMConversion Conversion = getIPMConversion(CCValid, CCMask);
01666   SDValue Result = DAG.getNode(SystemZISD::IPM, DL, MVT::i32, Glue);
01667 
01668   if (Conversion.XORValue)
01669     Result = DAG.getNode(ISD::XOR, DL, MVT::i32, Result,
01670                          DAG.getConstant(Conversion.XORValue, MVT::i32));
01671 
01672   if (Conversion.AddValue)
01673     Result = DAG.getNode(ISD::ADD, DL, MVT::i32, Result,
01674                          DAG.getConstant(Conversion.AddValue, MVT::i32));
01675 
01676   // The SHR/AND sequence should get optimized to an RISBG.
01677   Result = DAG.getNode(ISD::SRL, DL, MVT::i32, Result,
01678                        DAG.getConstant(Conversion.Bit, MVT::i32));
01679   if (Conversion.Bit != 31)
01680     Result = DAG.getNode(ISD::AND, DL, MVT::i32, Result,
01681                          DAG.getConstant(1, MVT::i32));
01682   return Result;
01683 }
01684 
01685 SDValue SystemZTargetLowering::lowerSETCC(SDValue Op,
01686                                           SelectionDAG &DAG) const {
01687   SDValue CmpOp0   = Op.getOperand(0);
01688   SDValue CmpOp1   = Op.getOperand(1);
01689   ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
01690   SDLoc DL(Op);
01691 
01692   Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC));
01693   SDValue Glue = emitCmp(DAG, DL, C);
01694   return emitSETCC(DAG, DL, Glue, C.CCValid, C.CCMask);
01695 }
01696 
01697 SDValue SystemZTargetLowering::lowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
01698   SDValue Chain    = Op.getOperand(0);
01699   ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
01700   SDValue CmpOp0   = Op.getOperand(2);
01701   SDValue CmpOp1   = Op.getOperand(3);
01702   SDValue Dest     = Op.getOperand(4);
01703   SDLoc DL(Op);
01704 
01705   Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC));
01706   SDValue Glue = emitCmp(DAG, DL, C);
01707   return DAG.getNode(SystemZISD::BR_CCMASK, DL, Op.getValueType(),
01708                      Chain, DAG.getConstant(C.CCValid, MVT::i32),
01709                      DAG.getConstant(C.CCMask, MVT::i32), Dest, Glue);
01710 }
01711 
01712 // Return true if Pos is CmpOp and Neg is the negative of CmpOp,
01713 // allowing Pos and Neg to be wider than CmpOp.
01714 static bool isAbsolute(SDValue CmpOp, SDValue Pos, SDValue Neg) {
01715   return (Neg.getOpcode() == ISD::SUB &&
01716           Neg.getOperand(0).getOpcode() == ISD::Constant &&
01717           cast<ConstantSDNode>(Neg.getOperand(0))->getZExtValue() == 0 &&
01718           Neg.getOperand(1) == Pos &&
01719           (Pos == CmpOp ||
01720            (Pos.getOpcode() == ISD::SIGN_EXTEND &&
01721             Pos.getOperand(0) == CmpOp)));
01722 }
01723 
01724 // Return the absolute or negative absolute of Op; IsNegative decides which.
01725 static SDValue getAbsolute(SelectionDAG &DAG, SDLoc DL, SDValue Op,
01726                            bool IsNegative) {
01727   Op = DAG.getNode(SystemZISD::IABS, DL, Op.getValueType(), Op);
01728   if (IsNegative)
01729     Op = DAG.getNode(ISD::SUB, DL, Op.getValueType(),
01730                      DAG.getConstant(0, Op.getValueType()), Op);
01731   return Op;
01732 }
01733 
01734 SDValue SystemZTargetLowering::lowerSELECT_CC(SDValue Op,
01735                                               SelectionDAG &DAG) const {
01736   SDValue CmpOp0   = Op.getOperand(0);
01737   SDValue CmpOp1   = Op.getOperand(1);
01738   SDValue TrueOp   = Op.getOperand(2);
01739   SDValue FalseOp  = Op.getOperand(3);
01740   ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
01741   SDLoc DL(Op);
01742 
01743   Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC));
01744 
01745   // Check for absolute and negative-absolute selections, including those
01746   // where the comparison value is sign-extended (for LPGFR and LNGFR).
01747   // This check supplements the one in DAGCombiner.
01748   if (C.Opcode == SystemZISD::ICMP &&
01749       C.CCMask != SystemZ::CCMASK_CMP_EQ &&
01750       C.CCMask != SystemZ::CCMASK_CMP_NE &&
01751       C.Op1.getOpcode() == ISD::Constant &&
01752       cast<ConstantSDNode>(C.Op1)->getZExtValue() == 0) {
01753     if (isAbsolute(C.Op0, TrueOp, FalseOp))
01754       return getAbsolute(DAG, DL, TrueOp, C.CCMask & SystemZ::CCMASK_CMP_LT);
01755     if (isAbsolute(C.Op0, FalseOp, TrueOp))
01756       return getAbsolute(DAG, DL, FalseOp, C.CCMask & SystemZ::CCMASK_CMP_GT);
01757   }
01758 
01759   SDValue Glue = emitCmp(DAG, DL, C);
01760 
01761   // Special case for handling -1/0 results.  The shifts we use here
01762   // should get optimized with the IPM conversion sequence.
01763   auto *TrueC = dyn_cast<ConstantSDNode>(TrueOp);
01764   auto *FalseC = dyn_cast<ConstantSDNode>(FalseOp);
01765   if (TrueC && FalseC) {
01766     int64_t TrueVal = TrueC->getSExtValue();
01767     int64_t FalseVal = FalseC->getSExtValue();
01768     if ((TrueVal == -1 && FalseVal == 0) || (TrueVal == 0 && FalseVal == -1)) {
01769       // Invert the condition if we want -1 on false.
01770       if (TrueVal == 0)
01771         C.CCMask ^= C.CCValid;
01772       SDValue Result = emitSETCC(DAG, DL, Glue, C.CCValid, C.CCMask);
01773       EVT VT = Op.getValueType();
01774       // Extend the result to VT.  Upper bits are ignored.
01775       if (!is32Bit(VT))
01776         Result = DAG.getNode(ISD::ANY_EXTEND, DL, VT, Result);
01777       // Sign-extend from the low bit.
01778       SDValue ShAmt = DAG.getConstant(VT.getSizeInBits() - 1, MVT::i32);
01779       SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, Result, ShAmt);
01780       return DAG.getNode(ISD::SRA, DL, VT, Shl, ShAmt);
01781     }
01782   }
01783 
01784   SmallVector<SDValue, 5> Ops;
01785   Ops.push_back(TrueOp);
01786   Ops.push_back(FalseOp);
01787   Ops.push_back(DAG.getConstant(C.CCValid, MVT::i32));
01788   Ops.push_back(DAG.getConstant(C.CCMask, MVT::i32));
01789   Ops.push_back(Glue);
01790 
01791   SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
01792   return DAG.getNode(SystemZISD::SELECT_CCMASK, DL, VTs, Ops);
01793 }
01794 
01795 SDValue SystemZTargetLowering::lowerGlobalAddress(GlobalAddressSDNode *Node,
01796                                                   SelectionDAG &DAG) const {
01797   SDLoc DL(Node);
01798   const GlobalValue *GV = Node->getGlobal();
01799   int64_t Offset = Node->getOffset();
01800   EVT PtrVT = getPointerTy();
01801   Reloc::Model RM = DAG.getTarget().getRelocationModel();
01802   CodeModel::Model CM = DAG.getTarget().getCodeModel();
01803 
01804   SDValue Result;
01805   if (Subtarget.isPC32DBLSymbol(GV, RM, CM)) {
01806     // Assign anchors at 1<<12 byte boundaries.
01807     uint64_t Anchor = Offset & ~uint64_t(0xfff);
01808     Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, Anchor);
01809     Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
01810 
01811     // The offset can be folded into the address if it is aligned to a halfword.
01812     Offset -= Anchor;
01813     if (Offset != 0 && (Offset & 1) == 0) {
01814       SDValue Full = DAG.getTargetGlobalAddress(GV, DL, PtrVT, Anchor + Offset);
01815       Result = DAG.getNode(SystemZISD::PCREL_OFFSET, DL, PtrVT, Full, Result);
01816       Offset = 0;
01817     }
01818   } else {
01819     Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, SystemZII::MO_GOT);
01820     Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
01821     Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
01822                          MachinePointerInfo::getGOT(), false, false, false, 0);
01823   }
01824 
01825   // If there was a non-zero offset that we didn't fold, create an explicit
01826   // addition for it.
01827   if (Offset != 0)
01828     Result = DAG.getNode(ISD::ADD, DL, PtrVT, Result,
01829                          DAG.getConstant(Offset, PtrVT));
01830 
01831   return Result;
01832 }
01833 
01834 SDValue SystemZTargetLowering::lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
01835                  SelectionDAG &DAG) const {
01836   SDLoc DL(Node);
01837   const GlobalValue *GV = Node->getGlobal();
01838   EVT PtrVT = getPointerTy();
01839   TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
01840 
01841   if (model != TLSModel::LocalExec)
01842     llvm_unreachable("only local-exec TLS mode supported");
01843 
01844   // The high part of the thread pointer is in access register 0.
01845   SDValue TPHi = DAG.getNode(SystemZISD::EXTRACT_ACCESS, DL, MVT::i32,
01846                              DAG.getConstant(0, MVT::i32));
01847   TPHi = DAG.getNode(ISD::ANY_EXTEND, DL, PtrVT, TPHi);
01848 
01849   // The low part of the thread pointer is in access register 1.
01850   SDValue TPLo = DAG.getNode(SystemZISD::EXTRACT_ACCESS, DL, MVT::i32,
01851                              DAG.getConstant(1, MVT::i32));
01852   TPLo = DAG.getNode(ISD::ZERO_EXTEND, DL, PtrVT, TPLo);
01853 
01854   // Merge them into a single 64-bit address.
01855   SDValue TPHiShifted = DAG.getNode(ISD::SHL, DL, PtrVT, TPHi,
01856             DAG.getConstant(32, PtrVT));
01857   SDValue TP = DAG.getNode(ISD::OR, DL, PtrVT, TPHiShifted, TPLo);
01858 
01859   // Get the offset of GA from the thread pointer.
01860   SystemZConstantPoolValue *CPV =
01861     SystemZConstantPoolValue::Create(GV, SystemZCP::NTPOFF);
01862 
01863   // Force the offset into the constant pool and load it from there.
01864   SDValue CPAddr = DAG.getConstantPool(CPV, PtrVT, 8);
01865   SDValue Offset = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(),
01866              CPAddr, MachinePointerInfo::getConstantPool(),
01867              false, false, false, 0);
01868 
01869   // Add the base and offset together.
01870   return DAG.getNode(ISD::ADD, DL, PtrVT, TP, Offset);
01871 }
01872 
01873 SDValue SystemZTargetLowering::lowerBlockAddress(BlockAddressSDNode *Node,
01874                                                  SelectionDAG &DAG) const {
01875   SDLoc DL(Node);
01876   const BlockAddress *BA = Node->getBlockAddress();
01877   int64_t Offset = Node->getOffset();
01878   EVT PtrVT = getPointerTy();
01879 
01880   SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT, Offset);
01881   Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
01882   return Result;
01883 }
01884 
01885 SDValue SystemZTargetLowering::lowerJumpTable(JumpTableSDNode *JT,
01886                                               SelectionDAG &DAG) const {
01887   SDLoc DL(JT);
01888   EVT PtrVT = getPointerTy();
01889   SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
01890 
01891   // Use LARL to load the address of the table.
01892   return DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
01893 }
01894 
01895 SDValue SystemZTargetLowering::lowerConstantPool(ConstantPoolSDNode *CP,
01896                                                  SelectionDAG &DAG) const {
01897   SDLoc DL(CP);
01898   EVT PtrVT = getPointerTy();
01899 
01900   SDValue Result;
01901   if (CP->isMachineConstantPoolEntry())
01902     Result = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
01903                CP->getAlignment());
01904   else
01905     Result = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
01906                CP->getAlignment(), CP->getOffset());
01907 
01908   // Use LARL to load the address of the constant pool entry.
01909   return DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
01910 }
01911 
01912 SDValue SystemZTargetLowering::lowerBITCAST(SDValue Op,
01913                                             SelectionDAG &DAG) const {
01914   SDLoc DL(Op);
01915   SDValue In = Op.getOperand(0);
01916   EVT InVT = In.getValueType();
01917   EVT ResVT = Op.getValueType();
01918 
01919   if (InVT == MVT::i32 && ResVT == MVT::f32) {
01920     SDValue In64;
01921     if (Subtarget.hasHighWord()) {
01922       SDNode *U64 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL,
01923                                        MVT::i64);
01924       In64 = DAG.getTargetInsertSubreg(SystemZ::subreg_h32, DL,
01925                                        MVT::i64, SDValue(U64, 0), In);
01926     } else {
01927       In64 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, In);
01928       In64 = DAG.getNode(ISD::SHL, DL, MVT::i64, In64,
01929                          DAG.getConstant(32, MVT::i64));
01930     }
01931     SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::f64, In64);
01932     return DAG.getTargetExtractSubreg(SystemZ::subreg_h32,
01933                                       DL, MVT::f32, Out64);
01934   }
01935   if (InVT == MVT::f32 && ResVT == MVT::i32) {
01936     SDNode *U64 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, MVT::f64);
01937     SDValue In64 = DAG.getTargetInsertSubreg(SystemZ::subreg_h32, DL,
01938                                              MVT::f64, SDValue(U64, 0), In);
01939     SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::i64, In64);
01940     if (Subtarget.hasHighWord())
01941       return DAG.getTargetExtractSubreg(SystemZ::subreg_h32, DL,
01942                                         MVT::i32, Out64);
01943     SDValue Shift = DAG.getNode(ISD::SRL, DL, MVT::i64, Out64,
01944                                 DAG.getConstant(32, MVT::i64));
01945     return DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Shift);
01946   }
01947   llvm_unreachable("Unexpected bitcast combination");
01948 }
01949 
01950 SDValue SystemZTargetLowering::lowerVASTART(SDValue Op,
01951                                             SelectionDAG &DAG) const {
01952   MachineFunction &MF = DAG.getMachineFunction();
01953   SystemZMachineFunctionInfo *FuncInfo =
01954     MF.getInfo<SystemZMachineFunctionInfo>();
01955   EVT PtrVT = getPointerTy();
01956 
01957   SDValue Chain   = Op.getOperand(0);
01958   SDValue Addr    = Op.getOperand(1);
01959   const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
01960   SDLoc DL(Op);
01961 
01962   // The initial values of each field.
01963   const unsigned NumFields = 4;
01964   SDValue Fields[NumFields] = {
01965     DAG.getConstant(FuncInfo->getVarArgsFirstGPR(), PtrVT),
01966     DAG.getConstant(FuncInfo->getVarArgsFirstFPR(), PtrVT),
01967     DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT),
01968     DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), PtrVT)
01969   };
01970 
01971   // Store each field into its respective slot.
01972   SDValue MemOps[NumFields];
01973   unsigned Offset = 0;
01974   for (unsigned I = 0; I < NumFields; ++I) {
01975     SDValue FieldAddr = Addr;
01976     if (Offset != 0)
01977       FieldAddr = DAG.getNode(ISD::ADD, DL, PtrVT, FieldAddr,
01978                               DAG.getIntPtrConstant(Offset));
01979     MemOps[I] = DAG.getStore(Chain, DL, Fields[I], FieldAddr,
01980                              MachinePointerInfo(SV, Offset),
01981                              false, false, 0);
01982     Offset += 8;
01983   }
01984   return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
01985 }
01986 
01987 SDValue SystemZTargetLowering::lowerVACOPY(SDValue Op,
01988                                            SelectionDAG &DAG) const {
01989   SDValue Chain      = Op.getOperand(0);
01990   SDValue DstPtr     = Op.getOperand(1);
01991   SDValue SrcPtr     = Op.getOperand(2);
01992   const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
01993   const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
01994   SDLoc DL(Op);
01995 
01996   return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr, DAG.getIntPtrConstant(32),
01997                        /*Align*/8, /*isVolatile*/false, /*AlwaysInline*/false,
01998                        MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
01999 }
02000 
02001 SDValue SystemZTargetLowering::
02002 lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const {
02003   SDValue Chain = Op.getOperand(0);
02004   SDValue Size  = Op.getOperand(1);
02005   SDLoc DL(Op);
02006 
02007   unsigned SPReg = getStackPointerRegisterToSaveRestore();
02008 
02009   // Get a reference to the stack pointer.
02010   SDValue OldSP = DAG.getCopyFromReg(Chain, DL, SPReg, MVT::i64);
02011 
02012   // Get the new stack pointer value.
02013   SDValue NewSP = DAG.getNode(ISD::SUB, DL, MVT::i64, OldSP, Size);
02014 
02015   // Copy the new stack pointer back.
02016   Chain = DAG.getCopyToReg(Chain, DL, SPReg, NewSP);
02017 
02018   // The allocated data lives above the 160 bytes allocated for the standard
02019   // frame, plus any outgoing stack arguments.  We don't know how much that
02020   // amounts to yet, so emit a special ADJDYNALLOC placeholder.
02021   SDValue ArgAdjust = DAG.getNode(SystemZISD::ADJDYNALLOC, DL, MVT::i64);
02022   SDValue Result = DAG.getNode(ISD::ADD, DL, MVT::i64, NewSP, ArgAdjust);
02023 
02024   SDValue Ops[2] = { Result, Chain };
02025   return DAG.getMergeValues(Ops, DL);
02026 }
02027 
02028 SDValue SystemZTargetLowering::lowerSMUL_LOHI(SDValue Op,
02029                                               SelectionDAG &DAG) const {
02030   EVT VT = Op.getValueType();
02031   SDLoc DL(Op);
02032   SDValue Ops[2];
02033   if (is32Bit(VT))
02034     // Just do a normal 64-bit multiplication and extract the results.
02035     // We define this so that it can be used for constant division.
02036     lowerMUL_LOHI32(DAG, DL, ISD::SIGN_EXTEND, Op.getOperand(0),
02037                     Op.getOperand(1), Ops[1], Ops[0]);
02038   else {
02039     // Do a full 128-bit multiplication based on UMUL_LOHI64:
02040     //
02041     //   (ll * rl) + ((lh * rl) << 64) + ((ll * rh) << 64)
02042     //
02043     // but using the fact that the upper halves are either all zeros
02044     // or all ones:
02045     //
02046     //   (ll * rl) - ((lh & rl) << 64) - ((ll & rh) << 64)
02047     //
02048     // and grouping the right terms together since they are quicker than the
02049     // multiplication:
02050     //
02051     //   (ll * rl) - (((lh & rl) + (ll & rh)) << 64)
02052     SDValue C63 = DAG.getConstant(63, MVT::i64);
02053     SDValue LL = Op.getOperand(0);
02054     SDValue RL = Op.getOperand(1);
02055     SDValue LH = DAG.getNode(ISD::SRA, DL, VT, LL, C63);
02056     SDValue RH = DAG.getNode(ISD::SRA, DL, VT, RL, C63);
02057     // UMUL_LOHI64 returns the low result in the odd register and the high
02058     // result in the even register.  SMUL_LOHI is defined to return the
02059     // low half first, so the results are in reverse order.
02060     lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, SystemZISD::UMUL_LOHI64,
02061                      LL, RL, Ops[1], Ops[0]);
02062     SDValue NegLLTimesRH = DAG.getNode(ISD::AND, DL, VT, LL, RH);
02063     SDValue NegLHTimesRL = DAG.getNode(ISD::AND, DL, VT, LH, RL);
02064     SDValue NegSum = DAG.getNode(ISD::ADD, DL, VT, NegLLTimesRH, NegLHTimesRL);
02065     Ops[1] = DAG.getNode(ISD::SUB, DL, VT, Ops[1], NegSum);
02066   }
02067   return DAG.getMergeValues(Ops, DL);
02068 }
02069 
02070 SDValue SystemZTargetLowering::lowerUMUL_LOHI(SDValue Op,
02071                                               SelectionDAG &DAG) const {
02072   EVT VT = Op.getValueType();
02073   SDLoc DL(Op);
02074   SDValue Ops[2];
02075   if (is32Bit(VT))
02076     // Just do a normal 64-bit multiplication and extract the results.
02077     // We define this so that it can be used for constant division.
02078     lowerMUL_LOHI32(DAG, DL, ISD::ZERO_EXTEND, Op.getOperand(0),
02079                     Op.getOperand(1), Ops[1], Ops[0]);
02080   else
02081     // UMUL_LOHI64 returns the low result in the odd register and the high
02082     // result in the even register.  UMUL_LOHI is defined to return the
02083     // low half first, so the results are in reverse order.
02084     lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, SystemZISD::UMUL_LOHI64,
02085                      Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
02086   return DAG.getMergeValues(Ops, DL);
02087 }
02088 
02089 SDValue SystemZTargetLowering::lowerSDIVREM(SDValue Op,
02090                                             SelectionDAG &DAG) const {
02091   SDValue Op0 = Op.getOperand(0);
02092   SDValue Op1 = Op.getOperand(1);
02093   EVT VT = Op.getValueType();
02094   SDLoc DL(Op);
02095   unsigned Opcode;
02096 
02097   // We use DSGF for 32-bit division.
02098   if (is32Bit(VT)) {
02099     Op0 = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, Op0);
02100     Opcode = SystemZISD::SDIVREM32;
02101   } else if (DAG.ComputeNumSignBits(Op1) > 32) {
02102     Op1 = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Op1);
02103     Opcode = SystemZISD::SDIVREM32;
02104   } else    
02105     Opcode = SystemZISD::SDIVREM64;
02106 
02107   // DSG(F) takes a 64-bit dividend, so the even register in the GR128
02108   // input is "don't care".  The instruction returns the remainder in
02109   // the even register and the quotient in the odd register.
02110   SDValue Ops[2];
02111   lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, Opcode,
02112                    Op0, Op1, Ops[1], Ops[0]);
02113   return DAG.getMergeValues(Ops, DL);
02114 }
02115 
02116 SDValue SystemZTargetLowering::lowerUDIVREM(SDValue Op,
02117                                             SelectionDAG &DAG) const {
02118   EVT VT = Op.getValueType();
02119   SDLoc DL(Op);
02120 
02121   // DL(G) uses a double-width dividend, so we need to clear the even
02122   // register in the GR128 input.  The instruction returns the remainder
02123   // in the even register and the quotient in the odd register.
02124   SDValue Ops[2];
02125   if (is32Bit(VT))
02126     lowerGR128Binary(DAG, DL, VT, SystemZ::ZEXT128_32, SystemZISD::UDIVREM32,
02127                      Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
02128   else
02129     lowerGR128Binary(DAG, DL, VT, SystemZ::ZEXT128_64, SystemZISD::UDIVREM64,
02130                      Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
02131   return DAG.getMergeValues(Ops, DL);
02132 }
02133 
02134 SDValue SystemZTargetLowering::lowerOR(SDValue Op, SelectionDAG &DAG) const {
02135   assert(Op.getValueType() == MVT::i64 && "Should be 64-bit operation");
02136 
02137   // Get the known-zero masks for each operand.
02138   SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1) };
02139   APInt KnownZero[2], KnownOne[2];
02140   DAG.computeKnownBits(Ops[0], KnownZero[0], KnownOne[0]);
02141   DAG.computeKnownBits(Ops[1], KnownZero[1], KnownOne[1]);
02142 
02143   // See if the upper 32 bits of one operand and the lower 32 bits of the
02144   // other are known zero.  They are the low and high operands respectively.
02145   uint64_t Masks[] = { KnownZero[0].getZExtValue(),
02146                        KnownZero[1].getZExtValue() };
02147   unsigned High, Low;
02148   if ((Masks[0] >> 32) == 0xffffffff && uint32_t(Masks[1]) == 0xffffffff)
02149     High = 1, Low = 0;
02150   else if ((Masks[1] >> 32) == 0xffffffff && uint32_t(Masks[0]) == 0xffffffff)
02151     High = 0, Low = 1;
02152   else
02153     return Op;
02154 
02155   SDValue LowOp = Ops[Low];
02156   SDValue HighOp = Ops[High];
02157 
02158   // If the high part is a constant, we're better off using IILH.
02159   if (HighOp.getOpcode() == ISD::Constant)
02160     return Op;
02161 
02162   // If the low part is a constant that is outside the range of LHI,
02163   // then we're better off using IILF.
02164   if (LowOp.getOpcode() == ISD::Constant) {
02165     int64_t Value = int32_t(cast<ConstantSDNode>(LowOp)->getZExtValue());
02166     if (!isInt<16>(Value))
02167       return Op;
02168   }
02169 
02170   // Check whether the high part is an AND that doesn't change the
02171   // high 32 bits and just masks out low bits.  We can skip it if so.
02172   if (HighOp.getOpcode() == ISD::AND &&
02173       HighOp.getOperand(1).getOpcode() == ISD::Constant) {
02174     SDValue HighOp0 = HighOp.getOperand(0);
02175     uint64_t Mask = cast<ConstantSDNode>(HighOp.getOperand(1))->getZExtValue();
02176     if (DAG.MaskedValueIsZero(HighOp0, APInt(64, ~(Mask | 0xffffffff))))
02177       HighOp = HighOp0;
02178   }
02179 
02180   // Take advantage of the fact that all GR32 operations only change the
02181   // low 32 bits by truncating Low to an i32 and inserting it directly
02182   // using a subreg.  The interesting cases are those where the truncation
02183   // can be folded.
02184   SDLoc DL(Op);
02185   SDValue Low32 = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, LowOp);
02186   return DAG.getTargetInsertSubreg(SystemZ::subreg_l32, DL,
02187                                    MVT::i64, HighOp, Low32);
02188 }
02189 
02190 // Op is an atomic load.  Lower it into a normal volatile load.
02191 SDValue SystemZTargetLowering::lowerATOMIC_LOAD(SDValue Op,
02192                                                 SelectionDAG &DAG) const {
02193   auto *Node = cast<AtomicSDNode>(Op.getNode());
02194   return DAG.getExtLoad(ISD::EXTLOAD, SDLoc(Op), Op.getValueType(),
02195                         Node->getChain(), Node->getBasePtr(),
02196                         Node->getMemoryVT(), Node->getMemOperand());
02197 }
02198 
02199 // Op is an atomic store.  Lower it into a normal volatile store followed
02200 // by a serialization.
02201 SDValue SystemZTargetLowering::lowerATOMIC_STORE(SDValue Op,
02202                                                  SelectionDAG &DAG) const {
02203   auto *Node = cast<AtomicSDNode>(Op.getNode());
02204   SDValue Chain = DAG.getTruncStore(Node->getChain(), SDLoc(Op), Node->getVal(),
02205                                     Node->getBasePtr(), Node->getMemoryVT(),
02206                                     Node->getMemOperand());
02207   return SDValue(DAG.getMachineNode(SystemZ::Serialize, SDLoc(Op), MVT::Other,
02208                                     Chain), 0);
02209 }
02210 
02211 // Op is an 8-, 16-bit or 32-bit ATOMIC_LOAD_* operation.  Lower the first
02212 // two into the fullword ATOMIC_LOADW_* operation given by Opcode.
02213 SDValue SystemZTargetLowering::lowerATOMIC_LOAD_OP(SDValue Op,
02214                                                    SelectionDAG &DAG,
02215                                                    unsigned Opcode) const {
02216   auto *Node = cast<AtomicSDNode>(Op.getNode());
02217 
02218   // 32-bit operations need no code outside the main loop.
02219   EVT NarrowVT = Node->getMemoryVT();
02220   EVT WideVT = MVT::i32;
02221   if (NarrowVT == WideVT)
02222     return Op;
02223 
02224   int64_t BitSize = NarrowVT.getSizeInBits();
02225   SDValue ChainIn = Node->getChain();
02226   SDValue Addr = Node->getBasePtr();
02227   SDValue Src2 = Node->getVal();
02228   MachineMemOperand *MMO = Node->getMemOperand();
02229   SDLoc DL(Node);
02230   EVT PtrVT = Addr.getValueType();
02231 
02232   // Convert atomic subtracts of constants into additions.
02233   if (Opcode == SystemZISD::ATOMIC_LOADW_SUB)
02234     if (auto *Const = dyn_cast<ConstantSDNode>(Src2)) {
02235       Opcode = SystemZISD::ATOMIC_LOADW_ADD;
02236       Src2 = DAG.getConstant(-Const->getSExtValue(), Src2.getValueType());
02237     }
02238 
02239   // Get the address of the containing word.
02240   SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr,
02241                                     DAG.getConstant(-4, PtrVT));
02242 
02243   // Get the number of bits that the word must be rotated left in order
02244   // to bring the field to the top bits of a GR32.
02245   SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr,
02246                                  DAG.getConstant(3, PtrVT));
02247   BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift);
02248 
02249   // Get the complementing shift amount, for rotating a field in the top
02250   // bits back to its proper position.
02251   SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT,
02252                                     DAG.getConstant(0, WideVT), BitShift);
02253 
02254   // Extend the source operand to 32 bits and prepare it for the inner loop.
02255   // ATOMIC_SWAPW uses RISBG to rotate the field left, but all other
02256   // operations require the source to be shifted in advance.  (This shift
02257   // can be folded if the source is constant.)  For AND and NAND, the lower
02258   // bits must be set, while for other opcodes they should be left clear.
02259   if (Opcode != SystemZISD::ATOMIC_SWAPW)
02260     Src2 = DAG.getNode(ISD::SHL, DL, WideVT, Src2,
02261                        DAG.getConstant(32 - BitSize, WideVT));
02262   if (Opcode == SystemZISD::ATOMIC_LOADW_AND ||
02263       Opcode == SystemZISD::ATOMIC_LOADW_NAND)
02264     Src2 = DAG.getNode(ISD::OR, DL, WideVT, Src2,
02265                        DAG.getConstant(uint32_t(-1) >> BitSize, WideVT));
02266 
02267   // Construct the ATOMIC_LOADW_* node.
02268   SDVTList VTList = DAG.getVTList(WideVT, MVT::Other);
02269   SDValue Ops[] = { ChainIn, AlignedAddr, Src2, BitShift, NegBitShift,
02270                     DAG.getConstant(BitSize, WideVT) };
02271   SDValue AtomicOp = DAG.getMemIntrinsicNode(Opcode, DL, VTList, Ops,
02272                                              NarrowVT, MMO);
02273 
02274   // Rotate the result of the final CS so that the field is in the lower
02275   // bits of a GR32, then truncate it.
02276   SDValue ResultShift = DAG.getNode(ISD::ADD, DL, WideVT, BitShift,
02277                                     DAG.getConstant(BitSize, WideVT));
02278   SDValue Result = DAG.getNode(ISD::ROTL, DL, WideVT, AtomicOp, ResultShift);
02279 
02280   SDValue RetOps[2] = { Result, AtomicOp.getValue(1) };
02281   return DAG.getMergeValues(RetOps, DL);
02282 }
02283 
02284 // Op is an ATOMIC_LOAD_SUB operation.  Lower 8- and 16-bit operations
02285 // into ATOMIC_LOADW_SUBs and decide whether to convert 32- and 64-bit
02286 // operations into additions.
02287 SDValue SystemZTargetLowering::lowerATOMIC_LOAD_SUB(SDValue Op,
02288                                                     SelectionDAG &DAG) const {
02289   auto *Node = cast<AtomicSDNode>(Op.getNode());
02290   EVT MemVT = Node->getMemoryVT();
02291   if (MemVT == MVT::i32 || MemVT == MVT::i64) {
02292     // A full-width operation.
02293     assert(Op.getValueType() == MemVT && "Mismatched VTs");
02294     SDValue Src2 = Node->getVal();
02295     SDValue NegSrc2;
02296     SDLoc DL(Src2);
02297 
02298     if (auto *Op2 = dyn_cast<ConstantSDNode>(Src2)) {
02299       // Use an addition if the operand is constant and either LAA(G) is
02300       // available or the negative value is in the range of A(G)FHI.
02301       int64_t Value = (-Op2->getAPIntValue()).getSExtValue();
02302       if (isInt<32>(Value) || Subtarget.hasInterlockedAccess1())
02303         NegSrc2 = DAG.getConstant(Value, MemVT);
02304     } else if (Subtarget.hasInterlockedAccess1())
02305       // Use LAA(G) if available.
02306       NegSrc2 = DAG.getNode(ISD::SUB, DL, MemVT, DAG.getConstant(0, MemVT),
02307                             Src2);
02308 
02309     if (NegSrc2.getNode())
02310       return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, DL, MemVT,
02311                            Node->getChain(), Node->getBasePtr(), NegSrc2,
02312                            Node->getMemOperand(), Node->getOrdering(),
02313                            Node->getSynchScope());
02314 
02315     // Use the node as-is.
02316     return Op;
02317   }
02318 
02319   return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_SUB);
02320 }
02321 
02322 // Node is an 8- or 16-bit ATOMIC_CMP_SWAP operation.  Lower the first two
02323 // into a fullword ATOMIC_CMP_SWAPW operation.
02324 SDValue SystemZTargetLowering::lowerATOMIC_CMP_SWAP(SDValue Op,
02325                                                     SelectionDAG &DAG) const {
02326   auto *Node = cast<AtomicSDNode>(Op.getNode());
02327 
02328   // We have native support for 32-bit compare and swap.
02329   EVT NarrowVT = Node->getMemoryVT();
02330   EVT WideVT = MVT::i32;
02331   if (NarrowVT == WideVT)
02332     return Op;
02333 
02334   int64_t BitSize = NarrowVT.getSizeInBits();
02335   SDValue ChainIn = Node->getOperand(0);
02336   SDValue Addr = Node->getOperand(1);
02337   SDValue CmpVal = Node->getOperand(2);
02338   SDValue SwapVal = Node->getOperand(3);
02339   MachineMemOperand *MMO = Node->getMemOperand();
02340   SDLoc DL(Node);
02341   EVT PtrVT = Addr.getValueType();
02342 
02343   // Get the address of the containing word.
02344   SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr,
02345                                     DAG.getConstant(-4, PtrVT));
02346 
02347   // Get the number of bits that the word must be rotated left in order
02348   // to bring the field to the top bits of a GR32.
02349   SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr,
02350                                  DAG.getConstant(3, PtrVT));
02351   BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift);
02352 
02353   // Get the complementing shift amount, for rotating a field in the top
02354   // bits back to its proper position.
02355   SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT,
02356                                     DAG.getConstant(0, WideVT), BitShift);
02357 
02358   // Construct the ATOMIC_CMP_SWAPW node.
02359   SDVTList VTList = DAG.getVTList(WideVT, MVT::Other);
02360   SDValue Ops[] = { ChainIn, AlignedAddr, CmpVal, SwapVal, BitShift,
02361                     NegBitShift, DAG.getConstant(BitSize, WideVT) };
02362   SDValue AtomicOp = DAG.getMemIntrinsicNode(SystemZISD::ATOMIC_CMP_SWAPW, DL,
02363                                              VTList, Ops, NarrowVT, MMO);
02364   return AtomicOp;
02365 }
02366 
02367 SDValue SystemZTargetLowering::lowerSTACKSAVE(SDValue Op,
02368                                               SelectionDAG &DAG) const {
02369   MachineFunction &MF = DAG.getMachineFunction();
02370   MF.getInfo<SystemZMachineFunctionInfo>()->setManipulatesSP(true);
02371   return DAG.getCopyFromReg(Op.getOperand(0), SDLoc(Op),
02372                             SystemZ::R15D, Op.getValueType());
02373 }
02374 
02375 SDValue SystemZTargetLowering::lowerSTACKRESTORE(SDValue Op,
02376                                                  SelectionDAG &DAG) const {
02377   MachineFunction &MF = DAG.getMachineFunction();
02378   MF.getInfo<SystemZMachineFunctionInfo>()->setManipulatesSP(true);
02379   return DAG.getCopyToReg(Op.getOperand(0), SDLoc(Op),
02380                           SystemZ::R15D, Op.getOperand(1));
02381 }
02382 
02383 SDValue SystemZTargetLowering::lowerPREFETCH(SDValue Op,
02384                                              SelectionDAG &DAG) const {
02385   bool IsData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
02386   if (!IsData)
02387     // Just preserve the chain.
02388     return Op.getOperand(0);
02389 
02390   bool IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
02391   unsigned Code = IsWrite ? SystemZ::PFD_WRITE : SystemZ::PFD_READ;
02392   auto *Node = cast<MemIntrinsicSDNode>(Op.getNode());
02393   SDValue Ops[] = {
02394     Op.getOperand(0),
02395     DAG.getConstant(Code, MVT::i32),
02396     Op.getOperand(1)
02397   };
02398   return DAG.getMemIntrinsicNode(SystemZISD::PREFETCH, SDLoc(Op),
02399                                  Node->getVTList(), Ops,
02400                                  Node->getMemoryVT(), Node->getMemOperand());
02401 }
02402 
02403 SDValue SystemZTargetLowering::LowerOperation(SDValue Op,
02404                                               SelectionDAG &DAG) const {
02405   switch (Op.getOpcode()) {
02406   case ISD::BR_CC:
02407     return lowerBR_CC(Op, DAG);
02408   case ISD::SELECT_CC:
02409     return lowerSELECT_CC(Op, DAG);
02410   case ISD::SETCC:
02411     return lowerSETCC(Op, DAG);
02412   case ISD::GlobalAddress:
02413     return lowerGlobalAddress(cast<GlobalAddressSDNode>(Op), DAG);
02414   case ISD::GlobalTLSAddress:
02415     return lowerGlobalTLSAddress(cast<GlobalAddressSDNode>(Op), DAG);
02416   case ISD::BlockAddress:
02417     return lowerBlockAddress(cast<BlockAddressSDNode>(Op), DAG);
02418   case ISD::JumpTable:
02419     return lowerJumpTable(cast<JumpTableSDNode>(Op), DAG);
02420   case ISD::ConstantPool:
02421     return lowerConstantPool(cast<ConstantPoolSDNode>(Op), DAG);
02422   case ISD::BITCAST:
02423     return lowerBITCAST(Op, DAG);
02424   case ISD::VASTART:
02425     return lowerVASTART(Op, DAG);
02426   case ISD::VACOPY:
02427     return lowerVACOPY(Op, DAG);
02428   case ISD::DYNAMIC_STACKALLOC:
02429     return lowerDYNAMIC_STACKALLOC(Op, DAG);
02430   case ISD::SMUL_LOHI:
02431     return lowerSMUL_LOHI(Op, DAG);
02432   case ISD::UMUL_LOHI:
02433     return lowerUMUL_LOHI(Op, DAG);
02434   case ISD::SDIVREM:
02435     return lowerSDIVREM(Op, DAG);
02436   case ISD::UDIVREM:
02437     return lowerUDIVREM(Op, DAG);
02438   case ISD::OR:
02439     return lowerOR(Op, DAG);
02440   case ISD::ATOMIC_SWAP:
02441     return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_SWAPW);
02442   case ISD::ATOMIC_STORE:
02443     return lowerATOMIC_STORE(Op, DAG);
02444   case ISD::ATOMIC_LOAD:
02445     return lowerATOMIC_LOAD(Op, DAG);
02446   case ISD::ATOMIC_LOAD_ADD:
02447     return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_ADD);
02448   case ISD::ATOMIC_LOAD_SUB:
02449     return lowerATOMIC_LOAD_SUB(Op, DAG);
02450   case ISD::ATOMIC_LOAD_AND:
02451     return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_AND);
02452   case ISD::ATOMIC_LOAD_OR:
02453     return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_OR);
02454   case ISD::ATOMIC_LOAD_XOR:
02455     return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_XOR);
02456   case ISD::ATOMIC_LOAD_NAND:
02457     return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_NAND);
02458   case ISD::ATOMIC_LOAD_MIN:
02459     return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_MIN);
02460   case ISD::ATOMIC_LOAD_MAX:
02461     return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_MAX);
02462   case ISD::ATOMIC_LOAD_UMIN:
02463     return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_UMIN);
02464   case ISD::ATOMIC_LOAD_UMAX:
02465     return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_UMAX);
02466   case ISD::ATOMIC_CMP_SWAP:
02467     return lowerATOMIC_CMP_SWAP(Op, DAG);
02468   case ISD::STACKSAVE:
02469     return lowerSTACKSAVE(Op, DAG);
02470   case ISD::STACKRESTORE:
02471     return lowerSTACKRESTORE(Op, DAG);
02472   case ISD::PREFETCH:
02473     return lowerPREFETCH(Op, DAG);
02474   default:
02475     llvm_unreachable("Unexpected node to lower");
02476   }
02477 }
02478 
02479 const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const {
02480 #define OPCODE(NAME) case SystemZISD::NAME: return "SystemZISD::" #NAME
02481   switch (Opcode) {
02482     OPCODE(RET_FLAG);
02483     OPCODE(CALL);
02484     OPCODE(SIBCALL);
02485     OPCODE(PCREL_WRAPPER);
02486     OPCODE(PCREL_OFFSET);
02487     OPCODE(IABS);
02488     OPCODE(ICMP);
02489     OPCODE(FCMP);
02490     OPCODE(TM);
02491     OPCODE(BR_CCMASK);
02492     OPCODE(SELECT_CCMASK);
02493     OPCODE(ADJDYNALLOC);
02494     OPCODE(EXTRACT_ACCESS);
02495     OPCODE(UMUL_LOHI64);
02496     OPCODE(SDIVREM64);
02497     OPCODE(UDIVREM32);
02498     OPCODE(UDIVREM64);
02499     OPCODE(MVC);
02500     OPCODE(MVC_LOOP);
02501     OPCODE(NC);
02502     OPCODE(NC_LOOP);
02503     OPCODE(OC);
02504     OPCODE(OC_LOOP);
02505     OPCODE(XC);
02506     OPCODE(XC_LOOP);
02507     OPCODE(CLC);
02508     OPCODE(CLC_LOOP);
02509     OPCODE(STRCMP);
02510     OPCODE(STPCPY);
02511     OPCODE(SEARCH_STRING);
02512     OPCODE(IPM);
02513     OPCODE(SERIALIZE);
02514     OPCODE(ATOMIC_SWAPW);
02515     OPCODE(ATOMIC_LOADW_ADD);
02516     OPCODE(ATOMIC_LOADW_SUB);
02517     OPCODE(ATOMIC_LOADW_AND);
02518     OPCODE(ATOMIC_LOADW_OR);
02519     OPCODE(ATOMIC_LOADW_XOR);
02520     OPCODE(ATOMIC_LOADW_NAND);
02521     OPCODE(ATOMIC_LOADW_MIN);
02522     OPCODE(ATOMIC_LOADW_MAX);
02523     OPCODE(ATOMIC_LOADW_UMIN);
02524     OPCODE(ATOMIC_LOADW_UMAX);
02525     OPCODE(ATOMIC_CMP_SWAPW);
02526     OPCODE(PREFETCH);
02527   }
02528   return nullptr;
02529 #undef OPCODE
02530 }
02531 
02532 SDValue SystemZTargetLowering::PerformDAGCombine(SDNode *N,
02533                                                  DAGCombinerInfo &DCI) const {
02534   SelectionDAG &DAG = DCI.DAG;
02535   unsigned Opcode = N->getOpcode();
02536   if (Opcode == ISD::SIGN_EXTEND) {
02537     // Convert (sext (ashr (shl X, C1), C2)) to
02538     // (ashr (shl (anyext X), C1'), C2')), since wider shifts are as
02539     // cheap as narrower ones.
02540     SDValue N0 = N->getOperand(0);
02541     EVT VT = N->getValueType(0);
02542     if (N0.hasOneUse() && N0.getOpcode() == ISD::SRA) {
02543       auto *SraAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1));
02544       SDValue Inner = N0.getOperand(0);
02545       if (SraAmt && Inner.hasOneUse() && Inner.getOpcode() == ISD::SHL) {
02546         if (auto *ShlAmt = dyn_cast<ConstantSDNode>(Inner.getOperand(1))) {
02547           unsigned Extra = (VT.getSizeInBits() -
02548                             N0.getValueType().getSizeInBits());
02549           unsigned NewShlAmt = ShlAmt->getZExtValue() + Extra;
02550           unsigned NewSraAmt = SraAmt->getZExtValue() + Extra;
02551           EVT ShiftVT = N0.getOperand(1).getValueType();
02552           SDValue Ext = DAG.getNode(ISD::ANY_EXTEND, SDLoc(Inner), VT,
02553                                     Inner.getOperand(0));
02554           SDValue Shl = DAG.getNode(ISD::SHL, SDLoc(Inner), VT, Ext,
02555                                     DAG.getConstant(NewShlAmt, ShiftVT));
02556           return DAG.getNode(ISD::SRA, SDLoc(N0), VT, Shl,
02557                              DAG.getConstant(NewSraAmt, ShiftVT));
02558         }
02559       }
02560     }
02561   }
02562   return SDValue();
02563 }
02564 
02565 //===----------------------------------------------------------------------===//
02566 // Custom insertion
02567 //===----------------------------------------------------------------------===//
02568 
02569 // Create a new basic block after MBB.
02570 static MachineBasicBlock *emitBlockAfter(MachineBasicBlock *MBB) {
02571   MachineFunction &MF = *MBB->getParent();
02572   MachineBasicBlock *NewMBB = MF.CreateMachineBasicBlock(MBB->getBasicBlock());
02573   MF.insert(std::next(MachineFunction::iterator(MBB)), NewMBB);
02574   return NewMBB;
02575 }
02576 
02577 // Split MBB after MI and return the new block (the one that contains
02578 // instructions after MI).
02579 static MachineBasicBlock *splitBlockAfter(MachineInstr *MI,
02580                                           MachineBasicBlock *MBB) {
02581   MachineBasicBlock *NewMBB = emitBlockAfter(MBB);
02582   NewMBB->splice(NewMBB->begin(), MBB,
02583                  std::next(MachineBasicBlock::iterator(MI)), MBB->end());
02584   NewMBB->transferSuccessorsAndUpdatePHIs(MBB);
02585   return NewMBB;
02586 }
02587 
02588 // Split MBB before MI and return the new block (the one that contains MI).
02589 static MachineBasicBlock *splitBlockBefore(MachineInstr *MI,
02590                                            MachineBasicBlock *MBB) {
02591   MachineBasicBlock *NewMBB = emitBlockAfter(MBB);
02592   NewMBB->splice(NewMBB->begin(), MBB, MI, MBB->end());
02593   NewMBB->transferSuccessorsAndUpdatePHIs(MBB);
02594   return NewMBB;
02595 }
02596 
02597 // Force base value Base into a register before MI.  Return the register.
02598 static unsigned forceReg(MachineInstr *MI, MachineOperand &Base,
02599                          const SystemZInstrInfo *TII) {
02600   if (Base.isReg())
02601     return Base.getReg();
02602 
02603   MachineBasicBlock *MBB = MI->getParent();
02604   MachineFunction &MF = *MBB->getParent();
02605   MachineRegisterInfo &MRI = MF.getRegInfo();
02606 
02607   unsigned Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
02608   BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(SystemZ::LA), Reg)
02609     .addOperand(Base).addImm(0).addReg(0);
02610   return Reg;
02611 }
02612 
02613 // Implement EmitInstrWithCustomInserter for pseudo Select* instruction MI.
02614 MachineBasicBlock *
02615 SystemZTargetLowering::emitSelect(MachineInstr *MI,
02616                                   MachineBasicBlock *MBB) const {
02617   const SystemZInstrInfo *TII = static_cast<const SystemZInstrInfo *>(
02618       MBB->getParent()->getTarget().getInstrInfo());
02619 
02620   unsigned DestReg  = MI->getOperand(0).getReg();
02621   unsigned TrueReg  = MI->getOperand(1).getReg();
02622   unsigned FalseReg = MI->getOperand(2).getReg();
02623   unsigned CCValid  = MI->getOperand(3).getImm();
02624   unsigned CCMask   = MI->getOperand(4).getImm();
02625   DebugLoc DL       = MI->getDebugLoc();
02626 
02627   MachineBasicBlock *StartMBB = MBB;
02628   MachineBasicBlock *JoinMBB  = splitBlockBefore(MI, MBB);
02629   MachineBasicBlock *FalseMBB = emitBlockAfter(StartMBB);
02630 
02631   //  StartMBB:
02632   //   BRC CCMask, JoinMBB
02633   //   # fallthrough to FalseMBB
02634   MBB = StartMBB;
02635   BuildMI(MBB, DL, TII->get(SystemZ::BRC))
02636     .addImm(CCValid).addImm(CCMask).addMBB(JoinMBB);
02637   MBB->addSuccessor(JoinMBB);
02638   MBB->addSuccessor(FalseMBB);
02639 
02640   //  FalseMBB:
02641   //   # fallthrough to JoinMBB
02642   MBB = FalseMBB;
02643   MBB->addSuccessor(JoinMBB);
02644 
02645   //  JoinMBB:
02646   //   %Result = phi [ %FalseReg, FalseMBB ], [ %TrueReg, StartMBB ]
02647   //  ...
02648   MBB = JoinMBB;
02649   BuildMI(*MBB, MI, DL, TII->get(SystemZ::PHI), DestReg)
02650     .addReg(TrueReg).addMBB(StartMBB)
02651     .addReg(FalseReg).addMBB(FalseMBB);
02652 
02653   MI->eraseFromParent();
02654   return JoinMBB;
02655 }
02656 
02657 // Implement EmitInstrWithCustomInserter for pseudo CondStore* instruction MI.
02658 // StoreOpcode is the store to use and Invert says whether the store should
02659 // happen when the condition is false rather than true.  If a STORE ON
02660 // CONDITION is available, STOCOpcode is its opcode, otherwise it is 0.
02661 MachineBasicBlock *
02662 SystemZTargetLowering::emitCondStore(MachineInstr *MI,
02663                                      MachineBasicBlock *MBB,
02664                                      unsigned StoreOpcode, unsigned STOCOpcode,
02665                                      bool Invert) const {
02666   const SystemZInstrInfo *TII = static_cast<const SystemZInstrInfo *>(
02667       MBB->getParent()->getTarget().getInstrInfo());
02668 
02669   unsigned SrcReg     = MI->getOperand(0).getReg();
02670   MachineOperand Base = MI->getOperand(1);
02671   int64_t Disp        = MI->getOperand(2).getImm();
02672   unsigned IndexReg   = MI->getOperand(3).getReg();
02673   unsigned CCValid    = MI->getOperand(4).getImm();
02674   unsigned CCMask     = MI->getOperand(5).getImm();
02675   DebugLoc DL         = MI->getDebugLoc();
02676 
02677   StoreOpcode = TII->getOpcodeForOffset(StoreOpcode, Disp);
02678 
02679   // Use STOCOpcode if possible.  We could use different store patterns in
02680   // order to avoid matching the index register, but the performance trade-offs
02681   // might be more complicated in that case.
02682   if (STOCOpcode && !IndexReg && Subtarget.hasLoadStoreOnCond()) {
02683     if (Invert)
02684       CCMask ^= CCValid;
02685     BuildMI(*MBB, MI, DL, TII->get(STOCOpcode))
02686       .addReg(SrcReg).addOperand(Base).addImm(Disp)
02687       .addImm(CCValid).addImm(CCMask);
02688     MI->eraseFromParent();
02689     return MBB;
02690   }
02691 
02692   // Get the condition needed to branch around the store.
02693   if (!Invert)
02694     CCMask ^= CCValid;
02695 
02696   MachineBasicBlock *StartMBB = MBB;
02697   MachineBasicBlock *JoinMBB  = splitBlockBefore(MI, MBB);
02698   MachineBasicBlock *FalseMBB = emitBlockAfter(StartMBB);
02699 
02700   //  StartMBB:
02701   //   BRC CCMask, JoinMBB
02702   //   # fallthrough to FalseMBB
02703   MBB = StartMBB;
02704   BuildMI(MBB, DL, TII->get(SystemZ::BRC))
02705     .addImm(CCValid).addImm(CCMask).addMBB(JoinMBB);
02706   MBB->addSuccessor(JoinMBB);
02707   MBB->addSuccessor(FalseMBB);
02708 
02709   //  FalseMBB:
02710   //   store %SrcReg, %Disp(%Index,%Base)
02711   //   # fallthrough to JoinMBB
02712   MBB = FalseMBB;
02713   BuildMI(MBB, DL, TII->get(StoreOpcode))
02714     .addReg(SrcReg).addOperand(Base).addImm(Disp).addReg(IndexReg);
02715   MBB->addSuccessor(JoinMBB);
02716 
02717   MI->eraseFromParent();
02718   return JoinMBB;
02719 }
02720 
02721 // Implement EmitInstrWithCustomInserter for pseudo ATOMIC_LOAD{,W}_*
02722 // or ATOMIC_SWAP{,W} instruction MI.  BinOpcode is the instruction that
02723 // performs the binary operation elided by "*", or 0 for ATOMIC_SWAP{,W}.
02724 // BitSize is the width of the field in bits, or 0 if this is a partword
02725 // ATOMIC_LOADW_* or ATOMIC_SWAPW instruction, in which case the bitsize
02726 // is one of the operands.  Invert says whether the field should be
02727 // inverted after performing BinOpcode (e.g. for NAND).
02728 MachineBasicBlock *
02729 SystemZTargetLowering::emitAtomicLoadBinary(MachineInstr *MI,
02730                                             MachineBasicBlock *MBB,
02731                                             unsigned BinOpcode,
02732                                             unsigned BitSize,
02733                                             bool Invert) const {
02734   MachineFunction &MF = *MBB->getParent();
02735   const SystemZInstrInfo *TII =
02736       static_cast<const SystemZInstrInfo *>(MF.getTarget().getInstrInfo());
02737   MachineRegisterInfo &MRI = MF.getRegInfo();
02738   bool IsSubWord = (BitSize < 32);
02739 
02740   // Extract the operands.  Base can be a register or a frame index.
02741   // Src2 can be a register or immediate.
02742   unsigned Dest        = MI->getOperand(0).getReg();
02743   MachineOperand Base  = earlyUseOperand(MI->getOperand(1));
02744   int64_t Disp         = MI->getOperand(2).getImm();
02745   MachineOperand Src2  = earlyUseOperand(MI->getOperand(3));
02746   unsigned BitShift    = (IsSubWord ? MI->getOperand(4).getReg() : 0);
02747   unsigned NegBitShift = (IsSubWord ? MI->getOperand(5).getReg() : 0);
02748   DebugLoc DL          = MI->getDebugLoc();
02749   if (IsSubWord)
02750     BitSize = MI->getOperand(6).getImm();
02751 
02752   // Subword operations use 32-bit registers.
02753   const TargetRegisterClass *RC = (BitSize <= 32 ?
02754                                    &SystemZ::GR32BitRegClass :
02755                                    &SystemZ::GR64BitRegClass);
02756   unsigned LOpcode  = BitSize <= 32 ? SystemZ::L  : SystemZ::LG;
02757   unsigned CSOpcode = BitSize <= 32 ? SystemZ::CS : SystemZ::CSG;
02758 
02759   // Get the right opcodes for the displacement.
02760   LOpcode  = TII->getOpcodeForOffset(LOpcode,  Disp);
02761   CSOpcode = TII->getOpcodeForOffset(CSOpcode, Disp);
02762   assert(LOpcode && CSOpcode && "Displacement out of range");
02763 
02764   // Create virtual registers for temporary results.
02765   unsigned OrigVal       = MRI.createVirtualRegister(RC);
02766   unsigned OldVal        = MRI.createVirtualRegister(RC);
02767   unsigned NewVal        = (BinOpcode || IsSubWord ?
02768                             MRI.createVirtualRegister(RC) : Src2.getReg());
02769   unsigned RotatedOldVal = (IsSubWord ? MRI.createVirtualRegister(RC) : OldVal);
02770   unsigned RotatedNewVal = (IsSubWord ? MRI.createVirtualRegister(RC) : NewVal);
02771 
02772   // Insert a basic block for the main loop.
02773   MachineBasicBlock *StartMBB = MBB;
02774   MachineBasicBlock *DoneMBB  = splitBlockBefore(MI, MBB);
02775   MachineBasicBlock *LoopMBB  = emitBlockAfter(StartMBB);
02776 
02777   //  StartMBB:
02778   //   ...
02779   //   %OrigVal = L Disp(%Base)
02780   //   # fall through to LoopMMB
02781   MBB = StartMBB;
02782   BuildMI(MBB, DL, TII->get(LOpcode), OrigVal)
02783     .addOperand(Base).addImm(Disp).addReg(0);
02784   MBB->addSuccessor(LoopMBB);
02785 
02786   //  LoopMBB:
02787   //   %OldVal        = phi [ %OrigVal, StartMBB ], [ %Dest, LoopMBB ]
02788   //   %RotatedOldVal = RLL %OldVal, 0(%BitShift)
02789   //   %RotatedNewVal = OP %RotatedOldVal, %Src2
02790   //   %NewVal        = RLL %RotatedNewVal, 0(%NegBitShift)
02791   //   %Dest          = CS %OldVal, %NewVal, Disp(%Base)
02792   //   JNE LoopMBB
02793   //   # fall through to DoneMMB
02794   MBB = LoopMBB;
02795   BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
02796     .addReg(OrigVal).addMBB(StartMBB)
02797     .addReg(Dest).addMBB(LoopMBB);
02798   if (IsSubWord)
02799     BuildMI(MBB, DL, TII->get(SystemZ::RLL), RotatedOldVal)
02800       .addReg(OldVal).addReg(BitShift).addImm(0);
02801   if (Invert) {
02802     // Perform the operation normally and then invert every bit of the field.
02803     unsigned Tmp = MRI.createVirtualRegister(RC);
02804     BuildMI(MBB, DL, TII->get(BinOpcode), Tmp)
02805       .addReg(RotatedOldVal).addOperand(Src2);
02806     if (BitSize < 32)
02807       // XILF with the upper BitSize bits set.
02808       BuildMI(MBB, DL, TII->get(SystemZ::XILF), RotatedNewVal)
02809         .addReg(Tmp).addImm(uint32_t(~0 << (32 - BitSize)));
02810     else if (BitSize == 32)
02811       // XILF with every bit set.
02812       BuildMI(MBB, DL, TII->get(SystemZ::XILF), RotatedNewVal)
02813         .addReg(Tmp).addImm(~uint32_t(0));
02814     else {
02815       // Use LCGR and add -1 to the result, which is more compact than
02816       // an XILF, XILH pair.
02817       unsigned Tmp2 = MRI.createVirtualRegister(RC);
02818       BuildMI(MBB, DL, TII->get(SystemZ::LCGR), Tmp2).addReg(Tmp);
02819       BuildMI(MBB, DL, TII->get(SystemZ::AGHI), RotatedNewVal)
02820         .addReg(Tmp2).addImm(-1);
02821     }
02822   } else if (BinOpcode)
02823     // A simply binary operation.
02824     BuildMI(MBB, DL, TII->get(BinOpcode), RotatedNewVal)
02825       .addReg(RotatedOldVal).addOperand(Src2);
02826   else if (IsSubWord)
02827     // Use RISBG to rotate Src2 into position and use it to replace the
02828     // field in RotatedOldVal.
02829     BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RotatedNewVal)
02830       .addReg(RotatedOldVal).addReg(Src2.getReg())
02831       .addImm(32).addImm(31 + BitSize).addImm(32 - BitSize);
02832   if (IsSubWord)
02833     BuildMI(MBB, DL, TII->get(SystemZ::RLL), NewVal)
02834       .addReg(RotatedNewVal).addReg(NegBitShift).addImm(0);
02835   BuildMI(MBB, DL, TII->get(CSOpcode), Dest)
02836     .addReg(OldVal).addReg(NewVal).addOperand(Base).addImm(Disp);
02837   BuildMI(MBB, DL, TII->get(SystemZ::BRC))
02838     .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
02839   MBB->addSuccessor(LoopMBB);
02840   MBB->addSuccessor(DoneMBB);
02841 
02842   MI->eraseFromParent();
02843   return DoneMBB;
02844 }
02845 
02846 // Implement EmitInstrWithCustomInserter for pseudo
02847 // ATOMIC_LOAD{,W}_{,U}{MIN,MAX} instruction MI.  CompareOpcode is the
02848 // instruction that should be used to compare the current field with the
02849 // minimum or maximum value.  KeepOldMask is the BRC condition-code mask
02850 // for when the current field should be kept.  BitSize is the width of
02851 // the field in bits, or 0 if this is a partword ATOMIC_LOADW_* instruction.
02852 MachineBasicBlock *
02853 SystemZTargetLowering::emitAtomicLoadMinMax(MachineInstr *MI,
02854                                             MachineBasicBlock *MBB,
02855                                             unsigned CompareOpcode,
02856                                             unsigned KeepOldMask,
02857                                             unsigned BitSize) const {
02858   MachineFunction &MF = *MBB->getParent();
02859   const SystemZInstrInfo *TII =
02860       static_cast<const SystemZInstrInfo *>(MF.getTarget().getInstrInfo());
02861   MachineRegisterInfo &MRI = MF.getRegInfo();
02862   bool IsSubWord = (BitSize < 32);
02863 
02864   // Extract the operands.  Base can be a register or a frame index.
02865   unsigned Dest        = MI->getOperand(0).getReg();
02866   MachineOperand Base  = earlyUseOperand(MI->getOperand(1));
02867   int64_t  Disp        = MI->getOperand(2).getImm();
02868   unsigned Src2        = MI->getOperand(3).getReg();
02869   unsigned BitShift    = (IsSubWord ? MI->getOperand(4).getReg() : 0);
02870   unsigned NegBitShift = (IsSubWord ? MI->getOperand(5).getReg() : 0);
02871   DebugLoc DL          = MI->getDebugLoc();
02872   if (IsSubWord)
02873     BitSize = MI->getOperand(6).getImm();
02874 
02875   // Subword operations use 32-bit registers.
02876   const TargetRegisterClass *RC = (BitSize <= 32 ?
02877                                    &SystemZ::GR32BitRegClass :
02878                                    &SystemZ::GR64BitRegClass);
02879   unsigned LOpcode  = BitSize <= 32 ? SystemZ::L  : SystemZ::LG;
02880   unsigned CSOpcode = BitSize <= 32 ? SystemZ::CS : SystemZ::CSG;
02881 
02882   // Get the right opcodes for the displacement.
02883   LOpcode  = TII->getOpcodeForOffset(LOpcode,  Disp);
02884   CSOpcode = TII->getOpcodeForOffset(CSOpcode, Disp);
02885   assert(LOpcode && CSOpcode && "Displacement out of range");
02886 
02887   // Create virtual registers for temporary results.
02888   unsigned OrigVal       = MRI.createVirtualRegister(RC);
02889   unsigned OldVal        = MRI.createVirtualRegister(RC);
02890   unsigned NewVal        = MRI.createVirtualRegister(RC);
02891   unsigned RotatedOldVal = (IsSubWord ? MRI.createVirtualRegister(RC) : OldVal);
02892   unsigned RotatedAltVal = (IsSubWord ? MRI.createVirtualRegister(RC) : Src2);
02893   unsigned RotatedNewVal = (IsSubWord ? MRI.createVirtualRegister(RC) : NewVal);
02894 
02895   // Insert 3 basic blocks for the loop.
02896   MachineBasicBlock *StartMBB  = MBB;
02897   MachineBasicBlock *DoneMBB   = splitBlockBefore(MI, MBB);
02898   MachineBasicBlock *LoopMBB   = emitBlockAfter(StartMBB);
02899   MachineBasicBlock *UseAltMBB = emitBlockAfter(LoopMBB);
02900   MachineBasicBlock *UpdateMBB = emitBlockAfter(UseAltMBB);
02901 
02902   //  StartMBB:
02903   //   ...
02904   //   %OrigVal     = L Disp(%Base)
02905   //   # fall through to LoopMMB
02906   MBB = StartMBB;
02907   BuildMI(MBB, DL, TII->get(LOpcode), OrigVal)
02908     .addOperand(Base).addImm(Disp).addReg(0);
02909   MBB->addSuccessor(LoopMBB);
02910 
02911   //  LoopMBB:
02912   //   %OldVal        = phi [ %OrigVal, StartMBB ], [ %Dest, UpdateMBB ]
02913   //   %RotatedOldVal = RLL %OldVal, 0(%BitShift)
02914   //   CompareOpcode %RotatedOldVal, %Src2
02915   //   BRC KeepOldMask, UpdateMBB
02916   MBB = LoopMBB;
02917   BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
02918     .addReg(OrigVal).addMBB(StartMBB)
02919     .addReg(Dest).addMBB(UpdateMBB);
02920   if (IsSubWord)
02921     BuildMI(MBB, DL, TII->get(SystemZ::RLL), RotatedOldVal)
02922       .addReg(OldVal).addReg(BitShift).addImm(0);
02923   BuildMI(MBB, DL, TII->get(CompareOpcode))
02924     .addReg(RotatedOldVal).addReg(Src2);
02925   BuildMI(MBB, DL, TII->get(SystemZ::BRC))
02926     .addImm(SystemZ::CCMASK_ICMP).addImm(KeepOldMask).addMBB(UpdateMBB);
02927   MBB->addSuccessor(UpdateMBB);
02928   MBB->addSuccessor(UseAltMBB);
02929 
02930   //  UseAltMBB:
02931   //   %RotatedAltVal = RISBG %RotatedOldVal, %Src2, 32, 31 + BitSize, 0
02932   //   # fall through to UpdateMMB
02933   MBB = UseAltMBB;
02934   if (IsSubWord)
02935     BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RotatedAltVal)
02936       .addReg(RotatedOldVal).addReg(Src2)
02937       .addImm(32).addImm(31 + BitSize).addImm(0);
02938   MBB->addSuccessor(UpdateMBB);
02939 
02940   //  UpdateMBB:
02941   //   %RotatedNewVal = PHI [ %RotatedOldVal, LoopMBB ],
02942   //                        [ %RotatedAltVal, UseAltMBB ]
02943   //   %NewVal        = RLL %RotatedNewVal, 0(%NegBitShift)
02944   //   %Dest          = CS %OldVal, %NewVal, Disp(%Base)
02945   //   JNE LoopMBB
02946   //   # fall through to DoneMMB
02947   MBB = UpdateMBB;
02948   BuildMI(MBB, DL, TII->get(SystemZ::PHI), RotatedNewVal)
02949     .addReg(RotatedOldVal).addMBB(LoopMBB)
02950     .addReg(RotatedAltVal).addMBB(UseAltMBB);
02951   if (IsSubWord)
02952     BuildMI(MBB, DL, TII->get(SystemZ::RLL), NewVal)
02953       .addReg(RotatedNewVal).addReg(NegBitShift).addImm(0);
02954   BuildMI(MBB, DL, TII->get(CSOpcode), Dest)
02955     .addReg(OldVal).addReg(NewVal).addOperand(Base).addImm(Disp);
02956   BuildMI(MBB, DL, TII->get(SystemZ::BRC))
02957     .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
02958   MBB->addSuccessor(LoopMBB);
02959   MBB->addSuccessor(DoneMBB);
02960 
02961   MI->eraseFromParent();
02962   return DoneMBB;
02963 }
02964 
02965 // Implement EmitInstrWithCustomInserter for pseudo ATOMIC_CMP_SWAPW
02966 // instruction MI.
02967 MachineBasicBlock *
02968 SystemZTargetLowering::emitAtomicCmpSwapW(MachineInstr *MI,
02969                                           MachineBasicBlock *MBB) const {
02970   MachineFunction &MF = *MBB->getParent();
02971   const SystemZInstrInfo *TII =
02972       static_cast<const SystemZInstrInfo *>(MF.getTarget().getInstrInfo());
02973   MachineRegisterInfo &MRI = MF.getRegInfo();
02974 
02975   // Extract the operands.  Base can be a register or a frame index.
02976   unsigned Dest        = MI->getOperand(0).getReg();
02977   MachineOperand Base  = earlyUseOperand(MI->getOperand(1));
02978   int64_t  Disp        = MI->getOperand(2).getImm();
02979   unsigned OrigCmpVal  = MI->getOperand(3).getReg();
02980   unsigned OrigSwapVal = MI->getOperand(4).getReg();
02981   unsigned BitShift    = MI->getOperand(5).getReg();
02982   unsigned NegBitShift = MI->getOperand(6).getReg();
02983   int64_t  BitSize     = MI->getOperand(7).getImm();
02984   DebugLoc DL          = MI->getDebugLoc();
02985 
02986   const TargetRegisterClass *RC = &SystemZ::GR32BitRegClass;
02987 
02988   // Get the right opcodes for the displacement.
02989   unsigned LOpcode  = TII->getOpcodeForOffset(SystemZ::L,  Disp);
02990   unsigned CSOpcode = TII->getOpcodeForOffset(SystemZ::CS, Disp);
02991   assert(LOpcode && CSOpcode && "Displacement out of range");
02992 
02993   // Create virtual registers for temporary results.
02994   unsigned OrigOldVal   = MRI.createVirtualRegister(RC);
02995   unsigned OldVal       = MRI.createVirtualRegister(RC);
02996   unsigned CmpVal       = MRI.createVirtualRegister(RC);
02997   unsigned SwapVal      = MRI.createVirtualRegister(RC);
02998   unsigned StoreVal     = MRI.createVirtualRegister(RC);
02999   unsigned RetryOldVal  = MRI.createVirtualRegister(RC);
03000   unsigned RetryCmpVal  = MRI.createVirtualRegister(RC);
03001   unsigned RetrySwapVal = MRI.createVirtualRegister(RC);
03002 
03003   // Insert 2 basic blocks for the loop.
03004   MachineBasicBlock *StartMBB = MBB;
03005   MachineBasicBlock *DoneMBB  = splitBlockBefore(MI, MBB);
03006   MachineBasicBlock *LoopMBB  = emitBlockAfter(StartMBB);
03007   MachineBasicBlock *SetMBB   = emitBlockAfter(LoopMBB);
03008 
03009   //  StartMBB:
03010   //   ...
03011   //   %OrigOldVal     = L Disp(%Base)
03012   //   # fall through to LoopMMB
03013   MBB = StartMBB;
03014   BuildMI(MBB, DL, TII->get(LOpcode), OrigOldVal)
03015     .addOperand(Base).addImm(Disp).addReg(0);
03016   MBB->addSuccessor(LoopMBB);
03017 
03018   //  LoopMBB:
03019   //   %OldVal        = phi [ %OrigOldVal, EntryBB ], [ %RetryOldVal, SetMBB ]
03020   //   %CmpVal        = phi [ %OrigCmpVal, EntryBB ], [ %RetryCmpVal, SetMBB ]
03021   //   %SwapVal       = phi [ %OrigSwapVal, EntryBB ], [ %RetrySwapVal, SetMBB ]
03022   //   %Dest          = RLL %OldVal, BitSize(%BitShift)
03023   //                      ^^ The low BitSize bits contain the field
03024   //                         of interest.
03025   //   %RetryCmpVal   = RISBG32 %CmpVal, %Dest, 32, 63-BitSize, 0
03026   //                      ^^ Replace the upper 32-BitSize bits of the
03027   //                         comparison value with those that we loaded,
03028   //                         so that we can use a full word comparison.
03029   //   CR %Dest, %RetryCmpVal
03030   //   JNE DoneMBB
03031   //   # Fall through to SetMBB
03032   MBB = LoopMBB;
03033   BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
03034     .addReg(OrigOldVal).addMBB(StartMBB)
03035     .addReg(RetryOldVal).addMBB(SetMBB);
03036   BuildMI(MBB, DL, TII->get(SystemZ::PHI), CmpVal)
03037     .addReg(OrigCmpVal).addMBB(StartMBB)
03038     .addReg(RetryCmpVal).addMBB(SetMBB);
03039   BuildMI(MBB, DL, TII->get(SystemZ::PHI), SwapVal)
03040     .addReg(OrigSwapVal).addMBB(StartMBB)
03041     .addReg(RetrySwapVal).addMBB(SetMBB);
03042   BuildMI(MBB, DL, TII->get(SystemZ::RLL), Dest)
03043     .addReg(OldVal).addReg(BitShift).addImm(BitSize);
03044   BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RetryCmpVal)
03045     .addReg(CmpVal).addReg(Dest).addImm(32).addImm(63 - BitSize).addImm(0);
03046   BuildMI(MBB, DL, TII->get(SystemZ::CR))
03047     .addReg(Dest).addReg(RetryCmpVal);
03048   BuildMI(MBB, DL, TII->get(SystemZ::BRC))
03049     .addImm(SystemZ::CCMASK_ICMP)
03050     .addImm(SystemZ::CCMASK_CMP_NE).addMBB(DoneMBB);
03051   MBB->addSuccessor(DoneMBB);
03052   MBB->addSuccessor(SetMBB);
03053 
03054   //  SetMBB:
03055   //   %RetrySwapVal = RISBG32 %SwapVal, %Dest, 32, 63-BitSize, 0
03056   //                      ^^ Replace the upper 32-BitSize bits of the new
03057   //                         value with those that we loaded.
03058   //   %StoreVal    = RLL %RetrySwapVal, -BitSize(%NegBitShift)
03059   //                      ^^ Rotate the new field to its proper position.
03060   //   %RetryOldVal = CS %Dest, %StoreVal, Disp(%Base)
03061   //   JNE LoopMBB
03062   //   # fall through to ExitMMB
03063   MBB = SetMBB;
03064   BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RetrySwapVal)
03065     .addReg(SwapVal).addReg(Dest).addImm(32).addImm(63 - BitSize).addImm(0);
03066   BuildMI(MBB, DL, TII->get(SystemZ::RLL), StoreVal)
03067     .addReg(RetrySwapVal).addReg(NegBitShift).addImm(-BitSize);
03068   BuildMI(MBB, DL, TII->get(CSOpcode), RetryOldVal)
03069     .addReg(OldVal).addReg(StoreVal).addOperand(Base).addImm(Disp);
03070   BuildMI(MBB, DL, TII->get(SystemZ::BRC))
03071     .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
03072   MBB->addSuccessor(LoopMBB);
03073   MBB->addSuccessor(DoneMBB);
03074 
03075   MI->eraseFromParent();
03076   return DoneMBB;
03077 }
03078 
03079 // Emit an extension from a GR32 or GR64 to a GR128.  ClearEven is true
03080 // if the high register of the GR128 value must be cleared or false if
03081 // it's "don't care".  SubReg is subreg_l32 when extending a GR32
03082 // and subreg_l64 when extending a GR64.
03083 MachineBasicBlock *
03084 SystemZTargetLowering::emitExt128(MachineInstr *MI,
03085                                   MachineBasicBlock *MBB,
03086                                   bool ClearEven, unsigned SubReg) const {
03087   MachineFunction &MF = *MBB->getParent();
03088   const SystemZInstrInfo *TII =
03089       static_cast<const SystemZInstrInfo *>(MF.getTarget().getInstrInfo());
03090   MachineRegisterInfo &MRI = MF.getRegInfo();
03091   DebugLoc DL = MI->getDebugLoc();
03092 
03093   unsigned Dest  = MI->getOperand(0).getReg();
03094   unsigned Src   = MI->getOperand(1).getReg();
03095   unsigned In128 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
03096 
03097   BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::IMPLICIT_DEF), In128);
03098   if (ClearEven) {
03099     unsigned NewIn128 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
03100     unsigned Zero64   = MRI.createVirtualRegister(&SystemZ::GR64BitRegClass);
03101 
03102     BuildMI(*MBB, MI, DL, TII->get(SystemZ::LLILL), Zero64)
03103       .addImm(0);
03104     BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), NewIn128)
03105       .addReg(In128).addReg(Zero64).addImm(SystemZ::subreg_h64);
03106     In128 = NewIn128;
03107   }
03108   BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), Dest)
03109     .addReg(In128).addReg(Src).addImm(SubReg);
03110 
03111   MI->eraseFromParent();
03112   return MBB;
03113 }
03114 
03115 MachineBasicBlock *
03116 SystemZTargetLowering::emitMemMemWrapper(MachineInstr *MI,
03117                                          MachineBasicBlock *MBB,
03118                                          unsigned Opcode) const {
03119   MachineFunction &MF = *MBB->getParent();
03120   const SystemZInstrInfo *TII =
03121       static_cast<const SystemZInstrInfo *>(MF.getTarget().getInstrInfo());
03122   MachineRegisterInfo &MRI = MF.getRegInfo();
03123   DebugLoc DL = MI->getDebugLoc();
03124 
03125   MachineOperand DestBase = earlyUseOperand(MI->getOperand(0));
03126   uint64_t       DestDisp = MI->getOperand(1).getImm();
03127   MachineOperand SrcBase  = earlyUseOperand(MI->getOperand(2));
03128   uint64_t       SrcDisp  = MI->getOperand(3).getImm();
03129   uint64_t       Length   = MI->getOperand(4).getImm();
03130 
03131   // When generating more than one CLC, all but the last will need to
03132   // branch to the end when a difference is found.
03133   MachineBasicBlock *EndMBB = (Length > 256 && Opcode == SystemZ::CLC ?
03134                                splitBlockAfter(MI, MBB) : nullptr);
03135 
03136   // Check for the loop form, in which operand 5 is the trip count.
03137   if (MI->getNumExplicitOperands() > 5) {
03138     bool HaveSingleBase = DestBase.isIdenticalTo(SrcBase);
03139 
03140     uint64_t StartCountReg = MI->getOperand(5).getReg();
03141     uint64_t StartSrcReg   = forceReg(MI, SrcBase, TII);
03142     uint64_t StartDestReg  = (HaveSingleBase ? StartSrcReg :
03143                               forceReg(MI, DestBase, TII));
03144 
03145     const TargetRegisterClass *RC = &SystemZ::ADDR64BitRegClass;
03146     uint64_t ThisSrcReg  = MRI.createVirtualRegister(RC);
03147     uint64_t ThisDestReg = (HaveSingleBase ? ThisSrcReg :
03148                             MRI.createVirtualRegister(RC));
03149     uint64_t NextSrcReg  = MRI.createVirtualRegister(RC);
03150     uint64_t NextDestReg = (HaveSingleBase ? NextSrcReg :
03151                             MRI.createVirtualRegister(RC));
03152 
03153     RC = &SystemZ::GR64BitRegClass;
03154     uint64_t ThisCountReg = MRI.createVirtualRegister(RC);
03155     uint64_t NextCountReg = MRI.createVirtualRegister(RC);
03156 
03157     MachineBasicBlock *StartMBB = MBB;
03158     MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
03159     MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
03160     MachineBasicBlock *NextMBB = (EndMBB ? emitBlockAfter(LoopMBB) : LoopMBB);
03161 
03162     //  StartMBB:
03163     //   # fall through to LoopMMB
03164     MBB->addSuccessor(LoopMBB);
03165 
03166     //  LoopMBB:
03167     //   %ThisDestReg = phi [ %StartDestReg, StartMBB ],
03168     //                      [ %NextDestReg, NextMBB ]
03169     //   %ThisSrcReg = phi [ %StartSrcReg, StartMBB ],
03170     //                     [ %NextSrcReg, NextMBB ]
03171     //   %ThisCountReg = phi [ %StartCountReg, StartMBB ],
03172     //                       [ %NextCountReg, NextMBB ]
03173     //   ( PFD 2, 768+DestDisp(%ThisDestReg) )
03174     //   Opcode DestDisp(256,%ThisDestReg), SrcDisp(%ThisSrcReg)
03175     //   ( JLH EndMBB )
03176     //
03177     // The prefetch is used only for MVC.  The JLH is used only for CLC.
03178     MBB = LoopMBB;
03179 
03180     BuildMI(MBB, DL, TII->get(SystemZ::PHI), ThisDestReg)
03181       .addReg(StartDestReg).addMBB(StartMBB)
03182       .addReg(NextDestReg).addMBB(NextMBB);
03183     if (!HaveSingleBase)
03184       BuildMI(MBB, DL, TII->get(SystemZ::PHI), ThisSrcReg)
03185         .addReg(StartSrcReg).addMBB(StartMBB)
03186         .addReg(NextSrcReg).addMBB(NextMBB);
03187     BuildMI(MBB, DL, TII->get(SystemZ::PHI), ThisCountReg)
03188       .addReg(StartCountReg).addMBB(StartMBB)
03189       .addReg(NextCountReg).addMBB(NextMBB);
03190     if (Opcode == SystemZ::MVC)
03191       BuildMI(MBB, DL, TII->get(SystemZ::PFD))
03192         .addImm(SystemZ::PFD_WRITE)
03193         .addReg(ThisDestReg).addImm(DestDisp + 768).addReg(0);
03194     BuildMI(MBB, DL, TII->get(Opcode))
03195       .addReg(ThisDestReg).addImm(DestDisp).addImm(256)
03196       .addReg(ThisSrcReg).addImm(SrcDisp);
03197     if (EndMBB) {
03198       BuildMI(MBB, DL, TII->get(SystemZ::BRC))
03199         .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_NE)
03200         .addMBB(EndMBB);
03201       MBB->addSuccessor(EndMBB);
03202       MBB->addSuccessor(NextMBB);
03203     }
03204 
03205     // NextMBB:
03206     //   %NextDestReg = LA 256(%ThisDestReg)
03207     //   %NextSrcReg = LA 256(%ThisSrcReg)
03208     //   %NextCountReg = AGHI %ThisCountReg, -1
03209     //   CGHI %NextCountReg, 0
03210     //   JLH LoopMBB
03211     //   # fall through to DoneMMB
03212     //
03213     // The AGHI, CGHI and JLH should be converted to BRCTG by later passes.
03214     MBB = NextMBB;
03215 
03216     BuildMI(MBB, DL, TII->get(SystemZ::LA), NextDestReg)
03217       .addReg(ThisDestReg).addImm(256).addReg(0);
03218     if (!HaveSingleBase)
03219       BuildMI(MBB, DL, TII->get(SystemZ::LA), NextSrcReg)
03220         .addReg(ThisSrcReg).addImm(256).addReg(0);
03221     BuildMI(MBB, DL, TII->get(SystemZ::AGHI), NextCountReg)
03222       .addReg(ThisCountReg).addImm(-1);
03223     BuildMI(MBB, DL, TII->get(SystemZ::CGHI))
03224       .addReg(NextCountReg).addImm(0);
03225     BuildMI(MBB, DL, TII->get(SystemZ::BRC))
03226       .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_NE)
03227       .addMBB(LoopMBB);
03228     MBB->addSuccessor(LoopMBB);
03229     MBB->addSuccessor(DoneMBB);
03230 
03231     DestBase = MachineOperand::CreateReg(NextDestReg, false);
03232     SrcBase = MachineOperand::CreateReg(NextSrcReg, false);
03233     Length &= 255;
03234     MBB = DoneMBB;
03235   }
03236   // Handle any remaining bytes with straight-line code.
03237   while (Length > 0) {
03238     uint64_t ThisLength = std::min(Length, uint64_t(256));
03239     // The previous iteration might have created out-of-range displacements.
03240     // Apply them using LAY if so.
03241     if (!isUInt<12>(DestDisp)) {
03242       unsigned Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
03243       BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(SystemZ::LAY), Reg)
03244         .addOperand(DestBase).addImm(DestDisp).addReg(0);
03245       DestBase = MachineOperand::CreateReg(Reg, false);
03246       DestDisp = 0;
03247     }
03248     if (!isUInt<12>(SrcDisp)) {
03249       unsigned Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
03250       BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(SystemZ::LAY), Reg)
03251         .addOperand(SrcBase).addImm(SrcDisp).addReg(0);
03252       SrcBase = MachineOperand::CreateReg(Reg, false);
03253       SrcDisp = 0;
03254     }
03255     BuildMI(*MBB, MI, DL, TII->get(Opcode))
03256       .addOperand(DestBase).addImm(DestDisp).addImm(ThisLength)
03257       .addOperand(SrcBase).addImm(SrcDisp);
03258     DestDisp += ThisLength;
03259     SrcDisp += ThisLength;
03260     Length -= ThisLength;
03261     // If there's another CLC to go, branch to the end if a difference
03262     // was found.
03263     if (EndMBB && Length > 0) {
03264       MachineBasicBlock *NextMBB = splitBlockBefore(MI, MBB);
03265       BuildMI(MBB, DL, TII->get(SystemZ::BRC))
03266         .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_NE)
03267         .addMBB(EndMBB);
03268       MBB->addSuccessor(EndMBB);
03269       MBB->addSuccessor(NextMBB);
03270       MBB = NextMBB;
03271     }
03272   }
03273   if (EndMBB) {
03274     MBB->addSuccessor(EndMBB);
03275     MBB = EndMBB;
03276     MBB->addLiveIn(SystemZ::CC);
03277   }
03278 
03279   MI->eraseFromParent();
03280   return MBB;
03281 }
03282 
03283 // Decompose string pseudo-instruction MI into a loop that continually performs
03284 // Opcode until CC != 3.
03285 MachineBasicBlock *
03286 SystemZTargetLowering::emitStringWrapper(MachineInstr *MI,
03287                                          MachineBasicBlock *MBB,
03288                                          unsigned Opcode) const {
03289   MachineFunction &MF = *MBB->getParent();
03290   const SystemZInstrInfo *TII =
03291       static_cast<const SystemZInstrInfo *>(MF.getTarget().getInstrInfo());
03292   MachineRegisterInfo &MRI = MF.getRegInfo();
03293   DebugLoc DL = MI->getDebugLoc();
03294 
03295   uint64_t End1Reg   = MI->getOperand(0).getReg();
03296   uint64_t Start1Reg = MI->getOperand(1).getReg();
03297   uint64_t Start2Reg = MI->getOperand(2).getReg();
03298   uint64_t CharReg   = MI->getOperand(3).getReg();
03299 
03300   const TargetRegisterClass *RC = &SystemZ::GR64BitRegClass;
03301   uint64_t This1Reg = MRI.createVirtualRegister(RC);
03302   uint64_t This2Reg = MRI.createVirtualRegister(RC);
03303   uint64_t End2Reg  = MRI.createVirtualRegister(RC);
03304 
03305   MachineBasicBlock *StartMBB = MBB;
03306   MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
03307   MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
03308 
03309   //  StartMBB:
03310   //   # fall through to LoopMMB
03311   MBB->addSuccessor(LoopMBB);
03312 
03313   //  LoopMBB:
03314   //   %This1Reg = phi [ %Start1Reg, StartMBB ], [ %End1Reg, LoopMBB ]
03315   //   %This2Reg = phi [ %Start2Reg, StartMBB ], [ %End2Reg, LoopMBB ]
03316   //   R0L = %CharReg
03317   //   %End1Reg, %End2Reg = CLST %This1Reg, %This2Reg -- uses R0L
03318   //   JO LoopMBB
03319   //   # fall through to DoneMMB
03320   //
03321   // The load of R0L can be hoisted by post-RA LICM.
03322   MBB = LoopMBB;
03323 
03324   BuildMI(MBB, DL, TII->get(SystemZ::PHI), This1Reg)
03325     .addReg(Start1Reg).addMBB(StartMBB)
03326     .addReg(End1Reg).addMBB(LoopMBB);
03327   BuildMI(MBB, DL, TII->get(SystemZ::PHI), This2Reg)
03328     .addReg(Start2Reg).addMBB(StartMBB)
03329     .addReg(End2Reg).addMBB(LoopMBB);
03330   BuildMI(MBB, DL, TII->get(TargetOpcode::COPY), SystemZ::R0L).addReg(CharReg);
03331   BuildMI(MBB, DL, TII->get(Opcode))
03332     .addReg(End1Reg, RegState::Define).addReg(End2Reg, RegState::Define)
03333     .addReg(This1Reg).addReg(This2Reg);
03334   BuildMI(MBB, DL, TII->get(SystemZ::BRC))
03335     .addImm(SystemZ::CCMASK_ANY).addImm(SystemZ::CCMASK_3).addMBB(LoopMBB);
03336   MBB->addSuccessor(LoopMBB);
03337   MBB->addSuccessor(DoneMBB);
03338 
03339   DoneMBB->addLiveIn(SystemZ::CC);
03340 
03341   MI->eraseFromParent();
03342   return DoneMBB;
03343 }
03344 
03345 MachineBasicBlock *SystemZTargetLowering::
03346 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const {
03347   switch (MI->getOpcode()) {
03348   case SystemZ::Select32Mux:
03349   case SystemZ::Select32:
03350   case SystemZ::SelectF32:
03351   case SystemZ::Select64:
03352   case SystemZ::SelectF64:
03353   case SystemZ::SelectF128:
03354     return emitSelect(MI, MBB);
03355 
03356   case SystemZ::CondStore8Mux:
03357     return emitCondStore(MI, MBB, SystemZ::STCMux, 0, false);
03358   case SystemZ::CondStore8MuxInv:
03359     return emitCondStore(MI, MBB, SystemZ::STCMux, 0, true);
03360   case SystemZ::CondStore16Mux:
03361     return emitCondStore(MI, MBB, SystemZ::STHMux, 0, false);
03362   case SystemZ::CondStore16MuxInv:
03363     return emitCondStore(MI, MBB, SystemZ::STHMux, 0, true);
03364   case SystemZ::CondStore8:
03365     return emitCondStore(MI, MBB, SystemZ::STC, 0, false);
03366   case SystemZ::CondStore8Inv:
03367     return emitCondStore(MI, MBB, SystemZ::STC, 0, true);
03368   case SystemZ::CondStore16:
03369     return emitCondStore(MI, MBB, SystemZ::STH, 0, false);
03370   case SystemZ::CondStore16Inv:
03371     return emitCondStore(MI, MBB, SystemZ::STH, 0, true);
03372   case SystemZ::CondStore32:
03373     return emitCondStore(MI, MBB, SystemZ::ST, SystemZ::STOC, false);
03374   case SystemZ::CondStore32Inv:
03375     return emitCondStore(MI, MBB, SystemZ::ST, SystemZ::STOC, true);
03376   case SystemZ::CondStore64:
03377     return emitCondStore(MI, MBB, SystemZ::STG, SystemZ::STOCG, false);
03378   case SystemZ::CondStore64Inv:
03379     return emitCondStore(MI, MBB, SystemZ::STG, SystemZ::STOCG, true);
03380   case SystemZ::CondStoreF32:
03381     return emitCondStore(MI, MBB, SystemZ::STE, 0, false);
03382   case SystemZ::CondStoreF32Inv:
03383     return emitCondStore(MI, MBB, SystemZ::STE, 0, true);
03384   case SystemZ::CondStoreF64:
03385     return emitCondStore(MI, MBB, SystemZ::STD, 0, false);
03386   case SystemZ::CondStoreF64Inv:
03387     return emitCondStore(MI, MBB, SystemZ::STD, 0, true);
03388 
03389   case SystemZ::AEXT128_64:
03390     return emitExt128(MI, MBB, false, SystemZ::subreg_l64);
03391   case SystemZ::ZEXT128_32:
03392     return emitExt128(MI, MBB, true, SystemZ::subreg_l32);
03393   case SystemZ::ZEXT128_64:
03394     return emitExt128(MI, MBB, true, SystemZ::subreg_l64);
03395 
03396   case SystemZ::ATOMIC_SWAPW:
03397     return emitAtomicLoadBinary(MI, MBB, 0, 0);
03398   case SystemZ::ATOMIC_SWAP_32:
03399     return emitAtomicLoadBinary(MI, MBB, 0, 32);
03400   case SystemZ::ATOMIC_SWAP_64:
03401     return emitAtomicLoadBinary(MI, MBB, 0, 64);
03402 
03403   case SystemZ::ATOMIC_LOADW_AR:
03404     return emitAtomicLoadBinary(MI, MBB, SystemZ::AR, 0);
03405   case SystemZ::ATOMIC_LOADW_AFI:
03406     return emitAtomicLoadBinary(MI, MBB, SystemZ::AFI, 0);
03407   case SystemZ::ATOMIC_LOAD_AR:
03408     return emitAtomicLoadBinary(MI, MBB, SystemZ::AR, 32);
03409   case SystemZ::ATOMIC_LOAD_AHI:
03410     return emitAtomicLoadBinary(MI, MBB, SystemZ::AHI, 32);
03411   case SystemZ::ATOMIC_LOAD_AFI:
03412     return emitAtomicLoadBinary(MI, MBB, SystemZ::AFI, 32);
03413   case SystemZ::ATOMIC_LOAD_AGR:
03414     return emitAtomicLoadBinary(MI, MBB, SystemZ::AGR, 64);
03415   case SystemZ::ATOMIC_LOAD_AGHI:
03416     return emitAtomicLoadBinary(MI, MBB, SystemZ::AGHI, 64);
03417   case SystemZ::ATOMIC_LOAD_AGFI:
03418     return emitAtomicLoadBinary(MI, MBB, SystemZ::AGFI, 64);
03419 
03420   case SystemZ::ATOMIC_LOADW_SR:
03421     return emitAtomicLoadBinary(MI, MBB, SystemZ::SR, 0);
03422   case SystemZ::ATOMIC_LOAD_SR:
03423     return emitAtomicLoadBinary(MI, MBB, SystemZ::SR, 32);
03424   case SystemZ::ATOMIC_LOAD_SGR:
03425     return emitAtomicLoadBinary(MI, MBB, SystemZ::SGR, 64);
03426 
03427   case SystemZ::ATOMIC_LOADW_NR:
03428     return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 0);
03429   case SystemZ::ATOMIC_LOADW_NILH:
03430     return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 0);
03431   case SystemZ::ATOMIC_LOAD_NR:
03432     return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 32);
03433   case SystemZ::ATOMIC_LOAD_NILL:
03434     return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL, 32);
03435   case SystemZ::ATOMIC_LOAD_NILH:
03436     return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 32);
03437   case SystemZ::ATOMIC_LOAD_NILF:
03438     return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF, 32);
03439   case SystemZ::ATOMIC_LOAD_NGR:
03440     return emitAtomicLoadBinary(MI, MBB, SystemZ::NGR, 64);
03441   case SystemZ::ATOMIC_LOAD_NILL64:
03442     return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL64, 64);
03443   case SystemZ::ATOMIC_LOAD_NILH64:
03444     return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH64, 64);
03445   case SystemZ::ATOMIC_LOAD_NIHL64:
03446     return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHL64, 64);
03447   case SystemZ::ATOMIC_LOAD_NIHH64:
03448     return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHH64, 64);
03449   case SystemZ::ATOMIC_LOAD_NILF64:
03450     return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF64, 64);
03451   case SystemZ::ATOMIC_LOAD_NIHF64:
03452     return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHF64, 64);
03453 
03454   case SystemZ::ATOMIC_LOADW_OR:
03455     return emitAtomicLoadBinary(MI, MBB, SystemZ::OR, 0);
03456   case SystemZ::ATOMIC_LOADW_OILH:
03457     return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH, 0);
03458   case SystemZ::ATOMIC_LOAD_OR:
03459     return emitAtomicLoadBinary(MI, MBB, SystemZ::OR, 32);
03460   case SystemZ::ATOMIC_LOAD_OILL:
03461     return emitAtomicLoadBinary(MI, MBB, SystemZ::OILL, 32);
03462   case SystemZ::ATOMIC_LOAD_OILH:
03463     return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH, 32);
03464   case SystemZ::ATOMIC_LOAD_OILF:
03465     return emitAtomicLoadBinary(MI, MBB, SystemZ::OILF, 32);
03466   case SystemZ::ATOMIC_LOAD_OGR:
03467     return emitAtomicLoadBinary(MI, MBB, SystemZ::OGR, 64);
03468   case SystemZ::ATOMIC_LOAD_OILL64:
03469     return emitAtomicLoadBinary(MI, MBB, SystemZ::OILL64, 64);
03470   case SystemZ::ATOMIC_LOAD_OILH64:
03471     return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH64, 64);
03472   case SystemZ::ATOMIC_LOAD_OIHL64:
03473     return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHL64, 64);
03474   case SystemZ::ATOMIC_LOAD_OIHH64:
03475     return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHH64, 64);
03476   case SystemZ::ATOMIC_LOAD_OILF64:
03477     return emitAtomicLoadBinary(MI, MBB, SystemZ::OILF64, 64);
03478   case SystemZ::ATOMIC_LOAD_OIHF64:
03479     return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHF64, 64);
03480 
03481   case SystemZ::ATOMIC_LOADW_XR:
03482     return emitAtomicLoadBinary(MI, MBB, SystemZ::XR, 0);
03483   case SystemZ::ATOMIC_LOADW_XILF:
03484     return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF, 0);
03485   case SystemZ::ATOMIC_LOAD_XR:
03486     return emitAtomicLoadBinary(MI, MBB, SystemZ::XR, 32);
03487   case SystemZ::ATOMIC_LOAD_XILF:
03488     return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF, 32);
03489   case SystemZ::ATOMIC_LOAD_XGR:
03490     return emitAtomicLoadBinary(MI, MBB, SystemZ::XGR, 64);
03491   case SystemZ::ATOMIC_LOAD_XILF64:
03492     return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF64, 64);
03493   case SystemZ::ATOMIC_LOAD_XIHF64:
03494     return emitAtomicLoadBinary(MI, MBB, SystemZ::XIHF64, 64);
03495 
03496   case SystemZ::ATOMIC_LOADW_NRi:
03497     return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 0, true);
03498   case SystemZ::ATOMIC_LOADW_NILHi:
03499     return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 0, true);
03500   case SystemZ::ATOMIC_LOAD_NRi:
03501     return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 32, true);
03502   case SystemZ::ATOMIC_LOAD_NILLi:
03503     return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL, 32, true);
03504   case SystemZ::ATOMIC_LOAD_NILHi:
03505     return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 32, true);
03506   case SystemZ::ATOMIC_LOAD_NILFi:
03507     return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF, 32, true);
03508   case SystemZ::ATOMIC_LOAD_NGRi:
03509     return emitAtomicLoadBinary(MI, MBB, SystemZ::NGR, 64, true);
03510   case SystemZ::ATOMIC_LOAD_NILL64i:
03511     return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL64, 64, true);
03512   case SystemZ::ATOMIC_LOAD_NILH64i:
03513     return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH64, 64, true);
03514   case SystemZ::ATOMIC_LOAD_NIHL64i:
03515     return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHL64, 64, true);
03516   case SystemZ::ATOMIC_LOAD_NIHH64i:
03517     return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHH64, 64, true);
03518   case SystemZ::ATOMIC_LOAD_NILF64i:
03519     return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF64, 64, true);
03520   case SystemZ::ATOMIC_LOAD_NIHF64i:
03521     return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHF64, 64, true);
03522 
03523   case SystemZ::ATOMIC_LOADW_MIN:
03524     return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
03525                                 SystemZ::CCMASK_CMP_LE, 0);
03526   case SystemZ::ATOMIC_LOAD_MIN_32:
03527     return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
03528                                 SystemZ::CCMASK_CMP_LE, 32);
03529   case SystemZ::ATOMIC_LOAD_MIN_64:
03530     return emitAtomicLoadMinMax(MI, MBB, SystemZ::CGR,
03531                                 SystemZ::CCMASK_CMP_LE, 64);
03532 
03533   case SystemZ::ATOMIC_LOADW_MAX:
03534     return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
03535                                 SystemZ::CCMASK_CMP_GE, 0);
03536   case SystemZ::ATOMIC_LOAD_MAX_32:
03537     return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
03538                                 SystemZ::CCMASK_CMP_GE, 32);
03539   case SystemZ::ATOMIC_LOAD_MAX_64:
03540     return emitAtomicLoadMinMax(MI, MBB, SystemZ::CGR,
03541                                 SystemZ::CCMASK_CMP_GE, 64);
03542 
03543   case SystemZ::ATOMIC_LOADW_UMIN:
03544     return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
03545                                 SystemZ::CCMASK_CMP_LE, 0);
03546   case SystemZ::ATOMIC_LOAD_UMIN_32:
03547     return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
03548                                 SystemZ::CCMASK_CMP_LE, 32);
03549   case SystemZ::ATOMIC_LOAD_UMIN_64:
03550     return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLGR,
03551                                 SystemZ::CCMASK_CMP_LE, 64);
03552 
03553   case SystemZ::ATOMIC_LOADW_UMAX:
03554     return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
03555                                 SystemZ::CCMASK_CMP_GE, 0);
03556   case SystemZ::ATOMIC_LOAD_UMAX_32:
03557     return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
03558                                 SystemZ::CCMASK_CMP_GE, 32);
03559   case SystemZ::ATOMIC_LOAD_UMAX_64:
03560     return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLGR,
03561                                 SystemZ::CCMASK_CMP_GE, 64);
03562 
03563   case SystemZ::ATOMIC_CMP_SWAPW:
03564     return emitAtomicCmpSwapW(MI, MBB);
03565   case SystemZ::MVCSequence:
03566   case SystemZ::MVCLoop:
03567     return emitMemMemWrapper(MI, MBB, SystemZ::MVC);
03568   case SystemZ::NCSequence:
03569   case SystemZ::NCLoop:
03570     return emitMemMemWrapper(MI, MBB, SystemZ::NC);
03571   case SystemZ::OCSequence:
03572   case SystemZ::OCLoop:
03573     return emitMemMemWrapper(MI, MBB, SystemZ::OC);
03574   case SystemZ::XCSequence:
03575   case SystemZ::XCLoop:
03576     return emitMemMemWrapper(MI, MBB, SystemZ::XC);
03577   case SystemZ::CLCSequence:
03578   case SystemZ::CLCLoop:
03579     return emitMemMemWrapper(MI, MBB, SystemZ::CLC);
03580   case SystemZ::CLSTLoop:
03581     return emitStringWrapper(MI, MBB, SystemZ::CLST);
03582   case SystemZ::MVSTLoop:
03583     return emitStringWrapper(MI, MBB, SystemZ::MVST);
03584   case SystemZ::SRSTLoop:
03585     return emitStringWrapper(MI, MBB, SystemZ::SRST);
03586   default:
03587     llvm_unreachable("Unexpected instr type to insert");
03588   }
03589 }