25#include "llvm/IR/IntrinsicsS390.h"
34#define DEBUG_TYPE "systemz-lower"
40 : Op0(Op0In), Op1(Op1In), Chain(ChainIn),
41 Opcode(0), ICmpType(0), CCValid(0), CCMask(0) {}
91 if (Subtarget.hasHighWord())
97 if (Subtarget.hasVector()) {
104 if (Subtarget.hasVectorEnhancements1())
109 if (Subtarget.hasVector()) {
118 if (Subtarget.hasVector())
145 for (
unsigned I = MVT::FIRST_INTEGER_VALUETYPE;
146 I <= MVT::LAST_FP_VALUETYPE;
172 for (
unsigned I = MVT::FIRST_INTEGER_VALUETYPE;
173 I <= MVT::LAST_INTEGER_VALUETYPE;
204 if (Subtarget.hasPopulationCount())
223 if (!Subtarget.hasFPExtension())
229 if (Subtarget.hasFPExtension())
234 if (Subtarget.hasFPExtension())
301 {MVT::i8, MVT::i16, MVT::i32},
Legal);
303 {MVT::i8, MVT::i16},
Legal);
320 if (!Subtarget.hasFPExtension()) {
333 if (Subtarget.hasMiscellaneousExtensions3()) {
429 if (VT != MVT::v2i64)
435 if (Subtarget.hasVectorEnhancements1())
466 if (Subtarget.hasVector()) {
488 if (Subtarget.hasVectorEnhancements2()) {
509 for (
unsigned I = MVT::FIRST_FP_VALUETYPE;
510 I <= MVT::LAST_FP_VALUETYPE;
518 if (Subtarget.hasFPExtension()) {
546 if (Subtarget.hasFPExtension()) {
557 if (Subtarget.hasVector()) {
603 if (Subtarget.hasVectorEnhancements1()) {
610 if (Subtarget.hasVectorEnhancements1()) {
664 for (
auto VT : { MVT::f32, MVT::f64, MVT::f128,
665 MVT::v4f32, MVT::v2f64 }) {
674 if (!Subtarget.hasVectorEnhancements1()) {
680 if (Subtarget.hasVectorEnhancements1())
690 if (Subtarget.hasVectorEnhancements1()) {
702 if (!Subtarget.hasVector()) {
757 struct RTLibCallMapping {
761 static RTLibCallMapping RTLibCallCommon[] = {
762#define HANDLE_LIBCALL(code, name) {RTLIB::code, name},
763#include "ZOSLibcallNames.def"
765 for (
auto &E : RTLibCallCommon)
771 return Subtarget.hasSoftFloat();
793 return Subtarget.hasVectorEnhancements1();
806 if (!Subtarget.hasVector() ||
807 (isFP128 && !Subtarget.hasVectorEnhancements1()))
829 if (SplatBitSize > 64)
835 if (isInt<16>(SignedValue)) {
844 if (
TII->isRxSBGMask(
Value, SplatBitSize, Start,
End)) {
866 uint64_t Lower = SplatUndefZ & maskTrailingOnes<uint64_t>(LowerBits);
867 uint64_t Upper = SplatUndefZ & maskLeadingOnes<uint64_t>(UpperBits);
874 uint64_t Middle = SplatUndefZ & ~Upper & ~Lower;
875 return tryValue(SplatBitsZ | Middle);
890 unsigned HalfSize = Width / 2;
895 if (HighValue != LowValue || 8 > HalfSize)
898 SplatBits = HighValue;
902 SplatBitSize = Width;
910 BVN->
isConstantSplat(IntBits, SplatUndef, SplatBitSize, HasAnyUndefs, 128,
914 BVN->
isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs, 8,
919 bool ForCodeSize)
const {
921 if (Imm.isZero() || Imm.isNegZero())
947 if (SI->getValueOperand()->getType()->isFP128Ty())
959 if (Subtarget.hasInterlockedAccess1() &&
973 return isInt<32>(Imm) || isUInt<32>(Imm);
978 return isUInt<32>(Imm) || isUInt<32>(-Imm);
1000 LongDisplacement(LongDispl), IndexReg(IdxReg) {}
1023 switch (II->getIntrinsicID()) {
1025 case Intrinsic::memset:
1026 case Intrinsic::memmove:
1027 case Intrinsic::memcpy:
1032 if (isa<LoadInst>(
I) &&
I->hasOneUse()) {
1033 auto *SingleUser = cast<Instruction>(*
I->user_begin());
1034 if (SingleUser->getParent() ==
I->getParent()) {
1035 if (isa<ICmpInst>(SingleUser)) {
1036 if (
auto *
C = dyn_cast<ConstantInt>(SingleUser->getOperand(1)))
1037 if (
C->getBitWidth() <= 64 &&
1038 (isInt<16>(
C->getSExtValue()) || isUInt<16>(
C->getZExtValue())))
1041 }
else if (isa<StoreInst>(SingleUser))
1045 }
else if (
auto *StoreI = dyn_cast<StoreInst>(
I)) {
1046 if (
auto *LoadI = dyn_cast<LoadInst>(StoreI->getValueOperand()))
1047 if (LoadI->hasOneUse() && LoadI->getParent() ==
I->getParent())
1052 if (HasVector && (isa<LoadInst>(
I) || isa<StoreInst>(
I))) {
1060 Type *MemAccessTy = (isa<LoadInst>(
I) ?
I->getType() :
1061 I->getOperand(0)->getType());
1063 bool IsVectorAccess = MemAccessTy->
isVectorTy();
1067 if (!IsVectorAccess && isa<StoreInst>(
I)) {
1068 Value *DataOp =
I->getOperand(0);
1069 if (isa<ExtractElementInst>(DataOp))
1070 IsVectorAccess =
true;
1075 if (!IsVectorAccess && isa<LoadInst>(
I) &&
I->hasOneUse()) {
1076 User *LoadUser = *
I->user_begin();
1077 if (isa<InsertElementInst>(LoadUser))
1078 IsVectorAccess =
true;
1081 if (IsFPAccess || IsVectorAccess)
1110 return AM.
Scale == 0;
1117 std::vector<EVT> &MemOps,
unsigned Limit,
const MemOp &
Op,
unsigned DstAS,
1118 unsigned SrcAS,
const AttributeList &FuncAttributes)
const {
1119 const int MVCFastLen = 16;
1121 if (Limit != ~
unsigned(0)) {
1123 if (
Op.isMemcpy() &&
Op.allowOverlap() &&
Op.size() <= MVCFastLen)
1125 if (
Op.isMemset() &&
Op.size() - 1 <= MVCFastLen)
1127 if (
Op.isZeroMemset())
1132 SrcAS, FuncAttributes);
1137 return Subtarget.hasVector() ? MVT::v2i64 : MVT::Other;
1141 if (!FromType->isIntegerTy() || !ToType->
isIntegerTy())
1143 unsigned FromBits = FromType->getPrimitiveSizeInBits().getFixedValue();
1145 return FromBits > ToBits;
1153 return FromBits > ToBits;
1162 if (Constraint.
size() == 1) {
1163 switch (Constraint[0]) {
1189 }
else if (Constraint.
size() == 2 && Constraint[0] ==
'Z') {
1190 switch (Constraint[1]) {
1206 const char *constraint)
const {
1208 Value *CallOperandVal =
info.CallOperandVal;
1211 if (!CallOperandVal)
1215 switch (*constraint) {
1233 if (Subtarget.hasVector())
1239 if (
auto *
C = dyn_cast<ConstantInt>(CallOperandVal))
1240 if (isUInt<8>(
C->getZExtValue()))
1245 if (
auto *
C = dyn_cast<ConstantInt>(CallOperandVal))
1246 if (isUInt<12>(
C->getZExtValue()))
1251 if (
auto *
C = dyn_cast<ConstantInt>(CallOperandVal))
1252 if (isInt<16>(
C->getSExtValue()))
1257 if (
auto *
C = dyn_cast<ConstantInt>(CallOperandVal))
1258 if (isInt<20>(
C->getSExtValue()))
1263 if (
auto *
C = dyn_cast<ConstantInt>(CallOperandVal))
1264 if (
C->getZExtValue() == 0x7fffffff)
1274static std::pair<unsigned, const TargetRegisterClass *>
1276 const unsigned *Map,
unsigned Size) {
1277 assert(*(Constraint.
end()-1) ==
'}' &&
"Missing '}'");
1278 if (isdigit(Constraint[2])) {
1283 return std::make_pair(Map[
Index], RC);
1285 return std::make_pair(0U,
nullptr);
1288std::pair<unsigned, const TargetRegisterClass *>
1291 if (Constraint.
size() == 1) {
1293 switch (Constraint[0]) {
1298 return std::make_pair(0U, &SystemZ::GR64BitRegClass);
1300 return std::make_pair(0U, &SystemZ::GR128BitRegClass);
1301 return std::make_pair(0U, &SystemZ::GR32BitRegClass);
1305 return std::make_pair(0U, &SystemZ::ADDR64BitRegClass);
1306 else if (VT == MVT::i128)
1307 return std::make_pair(0U, &SystemZ::ADDR128BitRegClass);
1308 return std::make_pair(0U, &SystemZ::ADDR32BitRegClass);
1311 return std::make_pair(0U, &SystemZ::GRH32BitRegClass);
1316 return std::make_pair(0U, &SystemZ::FP64BitRegClass);
1318 return std::make_pair(0U, &SystemZ::FP128BitRegClass);
1319 return std::make_pair(0U, &SystemZ::FP32BitRegClass);
1324 if (Subtarget.hasVector()) {
1326 return std::make_pair(0U, &SystemZ::VR32BitRegClass);
1328 return std::make_pair(0U, &SystemZ::VR64BitRegClass);
1329 return std::make_pair(0U, &SystemZ::VR128BitRegClass);
1338 auto getVTSizeInBits = [&VT]() {
1346 if (Constraint[1] ==
'r') {
1347 if (getVTSizeInBits() == 32)
1350 if (getVTSizeInBits() == 128)
1356 if (Constraint[1] ==
'f') {
1358 return std::make_pair(
1360 if (getVTSizeInBits() == 32)
1363 if (getVTSizeInBits() == 128)
1369 if (Constraint[1] ==
'v') {
1370 if (!Subtarget.hasVector())
1371 return std::make_pair(
1373 if (getVTSizeInBits() == 32)
1376 if (getVTSizeInBits() == 64)
1403 const Constant *PersonalityFn)
const {
1408 const Constant *PersonalityFn)
const {
1416 if (Constraint.
size() == 1) {
1417 switch (Constraint[0]) {
1419 if (
auto *
C = dyn_cast<ConstantSDNode>(
Op))
1420 if (isUInt<8>(
C->getZExtValue()))
1422 Op.getValueType()));
1426 if (
auto *
C = dyn_cast<ConstantSDNode>(
Op))
1427 if (isUInt<12>(
C->getZExtValue()))
1429 Op.getValueType()));
1433 if (
auto *
C = dyn_cast<ConstantSDNode>(
Op))
1434 if (isInt<16>(
C->getSExtValue()))
1436 Op.getValueType()));
1440 if (
auto *
C = dyn_cast<ConstantSDNode>(
Op))
1441 if (isInt<20>(
C->getSExtValue()))
1443 Op.getValueType()));
1447 if (
auto *
C = dyn_cast<ConstantSDNode>(
Op))
1448 if (
C->getZExtValue() == 0x7fffffff)
1450 Op.getValueType()));
1461#include "SystemZGenCallingConv.inc"
1465 static const MCPhysReg ScratchRegs[] = { SystemZ::R0D, SystemZ::R1D,
1471 Type *ToType)
const {
1534 if (BitCastToType == MVT::v2i64)
1559 MVT::Untyped,
Hi,
Lo);
1583 unsigned NumParts,
MVT PartVT, std::optional<CallingConv::ID>
CC)
const {
1585 if (ValueVT.
getSizeInBits() == 128 && NumParts == 1 && PartVT == MVT::Untyped) {
1596 MVT PartVT,
EVT ValueVT, std::optional<CallingConv::ID>
CC)
const {
1597 if (ValueVT.
getSizeInBits() == 128 && NumParts == 1 && PartVT == MVT::Untyped) {
1624 unsigned NumFixedGPRs = 0;
1625 unsigned NumFixedFPRs = 0;
1626 for (
unsigned I = 0, E = ArgLocs.
size();
I != E; ++
I) {
1639 RC = &SystemZ::GR32BitRegClass;
1643 RC = &SystemZ::GR64BitRegClass;
1647 RC = &SystemZ::FP32BitRegClass;
1651 RC = &SystemZ::FP64BitRegClass;
1655 RC = &SystemZ::FP128BitRegClass;
1663 RC = &SystemZ::VR128BitRegClass;
1692 ArgValue = DAG.
getLoad(LocVT,
DL, Chain, FIN,
1703 unsigned ArgIndex = Ins[
I].OrigArgIndex;
1704 assert (Ins[
I].PartOffset == 0);
1705 while (
I + 1 != E && Ins[
I + 1].OrigArgIndex == ArgIndex) {
1707 unsigned PartOffset = Ins[
I + 1].PartOffset;
1730 int64_t VarArgOffset = CCInfo.
getStackSize() + Regs->getCallFrameSize();
1748 int64_t RegSaveOffset =
1763 &SystemZ::FP64BitRegClass);
1781 MRI.addLiveIn(Regs->getADARegister(), ADAvReg);
1793 for (
unsigned I = 0, E = ArgLocs.
size();
I != E; ++
I) {
1800 if (Reg == SystemZ::R6H || Reg == SystemZ::R6L || Reg == SystemZ::R6D)
1802 if (Outs[
I].Flags.isSwiftSelf() || Outs[
I].Flags.isSwiftError())
1809 unsigned Offset,
bool LoadAdr =
false) {
1832 bool LoadAddr =
false;
1833 const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV);
1854 unsigned ADADelta = 0;
1855 unsigned EPADelta = 8;
1860 if (
auto *
G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1861 bool IsInternal = (
G->getGlobal()->hasInternalLinkage() ||
1862 G->getGlobal()->hasPrivateLinkage());
1877 }
else if (
auto *E = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1939 for (
unsigned I = 0, E = ArgLocs.
size();
I != E; ++
I) {
1945 unsigned ArgIndex = Outs[
I].OrigArgIndex;
1947 if (
I + 1 != E && Outs[
I + 1].OrigArgIndex == ArgIndex) {
1949 Type *OrigArgType = CLI.
Args[Outs[
I].OrigArgIndex].Ty;
1955 SlotVT = Outs[
I].VT;
1958 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
1964 assert (Outs[
I].PartOffset == 0);
1965 while (
I + 1 != E && Outs[
I + 1].OrigArgIndex == ArgIndex) {
1966 SDValue PartValue = OutVals[
I + 1];
1967 unsigned PartOffset = Outs[
I + 1].PartOffset;
1974 SlotVT.
getStoreSize()) &&
"Not enough space for argument part!");
1977 ArgValue = SpillSlot;
1994 if (!StackPtr.getNode())
2016 RegsToPass.
push_back(std::make_pair(SystemZ::R3D, ShadowArgValue));
2022 if (!MemOpChains.
empty())
2035 ->getAddressOfCalleeRegister();
2038 Callee = DAG.
getRegister(CalleeReg, Callee.getValueType());
2043 if (
auto *
G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2046 }
else if (
auto *E = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2049 }
else if (IsTailCall) {
2052 Callee = DAG.
getRegister(SystemZ::R1D, Callee.getValueType());
2057 for (
unsigned I = 0, E = RegsToPass.
size();
I != E; ++
I) {
2059 RegsToPass[
I].second, Glue);
2070 for (
unsigned I = 0, E = RegsToPass.
size();
I != E; ++
I)
2072 RegsToPass[
I].second.getValueType()));
2076 const uint32_t *Mask =
TRI->getCallPreservedMask(MF, CallConv);
2077 assert(Mask &&
"Missing call preserved mask for calling convention");
2101 CCState RetCCInfo(CallConv, IsVarArg, MF, RetLocs, Ctx);
2105 for (
unsigned I = 0, E = RetLocs.
size();
I != E; ++
I) {
2127 bool DoesNotReturn,
bool IsReturnValueUsed)
const {
2129 Args.reserve(Ops.
size());
2134 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.
getContext());
2137 Args.push_back(Entry);
2163 for (
auto &Out : Outs)
2164 if (Out.ArgVT == MVT::i128)
2169 return RetCCInfo.
CheckReturn(Outs, RetCC_SystemZ);
2186 if (RetLocs.
empty())
2196 for (
unsigned I = 0, E = RetLocs.
size();
I != E; ++
I) {
2225 unsigned &CCValid) {
2226 unsigned Id =
Op.getConstantOperandVal(1);
2228 case Intrinsic::s390_tbegin:
2233 case Intrinsic::s390_tbegin_nofloat:
2238 case Intrinsic::s390_tend:
2252 unsigned Id =
Op.getConstantOperandVal(0);
2254 case Intrinsic::s390_vpkshs:
2255 case Intrinsic::s390_vpksfs:
2256 case Intrinsic::s390_vpksgs:
2261 case Intrinsic::s390_vpklshs:
2262 case Intrinsic::s390_vpklsfs:
2263 case Intrinsic::s390_vpklsgs:
2268 case Intrinsic::s390_vceqbs:
2269 case Intrinsic::s390_vceqhs:
2270 case Intrinsic::s390_vceqfs:
2271 case Intrinsic::s390_vceqgs:
2276 case Intrinsic::s390_vchbs:
2277 case Intrinsic::s390_vchhs:
2278 case Intrinsic::s390_vchfs:
2279 case Intrinsic::s390_vchgs:
2284 case Intrinsic::s390_vchlbs:
2285 case Intrinsic::s390_vchlhs:
2286 case Intrinsic::s390_vchlfs:
2287 case Intrinsic::s390_vchlgs:
2292 case Intrinsic::s390_vtm:
2297 case Intrinsic::s390_vfaebs:
2298 case Intrinsic::s390_vfaehs:
2299 case Intrinsic::s390_vfaefs:
2304 case Intrinsic::s390_vfaezbs:
2305 case Intrinsic::s390_vfaezhs:
2306 case Intrinsic::s390_vfaezfs:
2311 case Intrinsic::s390_vfeebs:
2312 case Intrinsic::s390_vfeehs:
2313 case Intrinsic::s390_vfeefs:
2318 case Intrinsic::s390_vfeezbs:
2319 case Intrinsic::s390_vfeezhs:
2320 case Intrinsic::s390_vfeezfs:
2325 case Intrinsic::s390_vfenebs:
2326 case Intrinsic::s390_vfenehs:
2327 case Intrinsic::s390_vfenefs:
2332 case Intrinsic::s390_vfenezbs:
2333 case Intrinsic::s390_vfenezhs:
2334 case Intrinsic::s390_vfenezfs:
2339 case Intrinsic::s390_vistrbs:
2340 case Intrinsic::s390_vistrhs:
2341 case Intrinsic::s390_vistrfs:
2346 case Intrinsic::s390_vstrcbs:
2347 case Intrinsic::s390_vstrchs:
2348 case Intrinsic::s390_vstrcfs:
2353 case Intrinsic::s390_vstrczbs:
2354 case Intrinsic::s390_vstrczhs:
2355 case Intrinsic::s390_vstrczfs:
2360 case Intrinsic::s390_vstrsb:
2361 case Intrinsic::s390_vstrsh:
2362 case Intrinsic::s390_vstrsf:
2367 case Intrinsic::s390_vstrszb:
2368 case Intrinsic::s390_vstrszh:
2369 case Intrinsic::s390_vstrszf:
2374 case Intrinsic::s390_vfcedbs:
2375 case Intrinsic::s390_vfcesbs:
2380 case Intrinsic::s390_vfchdbs:
2381 case Intrinsic::s390_vfchsbs:
2386 case Intrinsic::s390_vfchedbs:
2387 case Intrinsic::s390_vfchesbs:
2392 case Intrinsic::s390_vftcidb:
2393 case Intrinsic::s390_vftcisb:
2398 case Intrinsic::s390_tdc:
2416 for (
unsigned I = 2;
I < NumOps; ++
I)
2419 assert(
Op->getNumValues() == 2 &&
"Expected only CC result and chain");
2425 return Intr.getNode();
2435 for (
unsigned I = 1;
I < NumOps; ++
I)
2439 return Intr.getNode();
2449 case ISD::SET##X: return SystemZ::CCMASK_CMP_##X; \
2450 case ISD::SETO##X: return SystemZ::CCMASK_CMP_##X; \
2451 case ISD::SETU##X: return SystemZ::CCMASK_CMP_UO | SystemZ::CCMASK_CMP_##X
2476 auto *ConstOp1 = dyn_cast<ConstantSDNode>(
C.Op1.getNode());
2477 if (!ConstOp1 || ConstOp1->getValueSizeInBits(0) > 64)
2480 int64_t
Value = ConstOp1->getSExtValue();
2496 if (!
C.Op0.hasOneUse() ||
2502 auto *Load = cast<LoadSDNode>(
C.Op0);
2503 unsigned NumBits = Load->getMemoryVT().getSizeInBits();
2504 if ((NumBits != 8 && NumBits != 16) ||
2505 NumBits != Load->getMemoryVT().getStoreSizeInBits())
2510 auto *ConstOp1 = cast<ConstantSDNode>(
C.Op1);
2511 if (!ConstOp1 || ConstOp1->getValueSizeInBits(0) > 64)
2514 uint64_t Mask = (1 << NumBits) - 1;
2517 int64_t SignedValue = ConstOp1->getSExtValue();
2524 }
else if (NumBits == 8) {
2550 if (
C.Op0.getValueType() != MVT::i32 ||
2551 Load->getExtensionType() != ExtType) {
2553 Load->getBasePtr(), Load->getPointerInfo(),
2554 Load->getMemoryVT(), Load->getAlign(),
2555 Load->getMemOperand()->getFlags());
2561 if (
C.Op1.getValueType() != MVT::i32 ||
2562 Value != ConstOp1->getZExtValue())
2569 auto *Load = dyn_cast<LoadSDNode>(
Op.getNode());
2572 if (Load->getMemoryVT() == MVT::i8)
2575 switch (Load->getExtensionType()) {
2592 if (
C.Op0.getValueType() == MVT::i128)
2594 if (
C.Op0.getValueType() == MVT::f128)
2600 if (isa<ConstantFPSDNode>(
C.Op1))
2605 auto *ConstOp1 = dyn_cast<ConstantSDNode>(
C.Op1);
2606 if (ConstOp1 && ConstOp1->getZExtValue() == 0)
2624 isUInt<16>(ConstOp1->getZExtValue()))
2629 isInt<16>(ConstOp1->getSExtValue()))
2635 unsigned Opcode0 =
C.Op0.getOpcode();
2642 C.Op0.getConstantOperandVal(1) == 0xffffffff)
2657 ((
N->getOperand(0) ==
C.Op0 &&
N->getOperand(1) ==
C.Op1) ||
2658 (
N->getOperand(0) ==
C.Op1 &&
N->getOperand(1) ==
C.Op0))) {
2662 Flags.setNoSignedWrap(
false);
2663 Flags.setNoUnsignedWrap(
false);
2682 auto *C1 = dyn_cast<ConstantFPSDNode>(
C.Op1);
2683 if (C1 && C1->isZero()) {
2702 if (
C.Op0.getOpcode() ==
ISD::SHL &&
C.Op0.getValueType() == MVT::i64 &&
2704 auto *C1 = dyn_cast<ConstantSDNode>(
C.Op0.getOperand(1));
2705 if (C1 && C1->getZExtValue() == 32) {
2706 SDValue ShlOp0 =
C.Op0.getOperand(0);
2710 cast<VTSDNode>(
N->getOperand(1))->getVT() == MVT::i32) {
2725 C.Op0.getOperand(0).getOpcode() ==
ISD::LOAD &&
2727 cast<ConstantSDNode>(
C.Op1)->getValueSizeInBits(0) <= 64 &&
2728 C.Op1->getAsZExtVal() == 0) {
2729 auto *L = cast<LoadSDNode>(
C.Op0.getOperand(0));
2730 if (L->getMemoryVT().getStoreSizeInBits().getFixedValue() <=
2731 C.Op0.getValueSizeInBits().getFixedValue()) {
2732 unsigned Type = L->getExtensionType();
2735 C.Op0 =
C.Op0.getOperand(0);
2745 auto *Shift = dyn_cast<ConstantSDNode>(
N.getOperand(1));
2749 uint64_t Amount = Shift->getZExtValue();
2750 if (Amount >=
N.getValueSizeInBits())
2765 unsigned ICmpType) {
2766 assert(Mask != 0 &&
"ANDs with zero should have been removed by now");
2788 if (EffectivelyUnsigned && CmpVal > 0 && CmpVal <=
Low) {
2794 if (EffectivelyUnsigned && CmpVal <
Low) {
2802 if (CmpVal == Mask) {
2808 if (EffectivelyUnsigned && CmpVal >= Mask -
Low && CmpVal < Mask) {
2814 if (EffectivelyUnsigned && CmpVal > Mask -
Low && CmpVal <= Mask) {
2822 if (EffectivelyUnsigned && CmpVal >= Mask -
High && CmpVal <
High) {
2828 if (EffectivelyUnsigned && CmpVal > Mask -
High && CmpVal <=
High) {
2857 if (
C.Op0.getValueType() == MVT::i128) {
2862 auto *Mask = dyn_cast<ConstantSDNode>(
C.Op1);
2863 if (Mask && Mask->getAPIntValue() == 0) {
2878 auto *ConstOp1 = dyn_cast<ConstantSDNode>(
C.Op1);
2881 uint64_t CmpVal = ConstOp1->getZExtValue();
2888 NewC.Op0 =
C.Op0.getOperand(0);
2889 NewC.Op1 =
C.Op0.getOperand(1);
2890 Mask = dyn_cast<ConstantSDNode>(NewC.Op1);
2893 MaskVal = Mask->getZExtValue();
2898 if (NewC.Op0.getValueType() != MVT::i64 ||
2913 MaskVal = -(CmpVal & -CmpVal);
2921 unsigned BitSize = NewC.Op0.getValueSizeInBits();
2922 unsigned NewCCMask, ShiftVal;
2924 NewC.Op0.getOpcode() ==
ISD::SHL &&
2926 (MaskVal >> ShiftVal != 0) &&
2927 ((CmpVal >> ShiftVal) << ShiftVal) == CmpVal &&
2929 MaskVal >> ShiftVal,
2932 NewC.Op0 = NewC.Op0.getOperand(0);
2933 MaskVal >>= ShiftVal;
2935 NewC.Op0.getOpcode() ==
ISD::SRL &&
2937 (MaskVal << ShiftVal != 0) &&
2938 ((CmpVal << ShiftVal) >> ShiftVal) == CmpVal &&
2940 MaskVal << ShiftVal,
2943 NewC.Op0 = NewC.Op0.getOperand(0);
2944 MaskVal <<= ShiftVal;
2955 if (Mask && Mask->getZExtValue() == MaskVal)
2960 C.CCMask = NewCCMask;
2968 if (
C.Op0.getValueType() != MVT::i128)
2986 bool Swap =
false, Invert =
false;
3005 C.CCMask ^=
C.CCValid;
3015 auto *Mask = dyn_cast<ConstantSDNode>(
C.Op0.getOperand(1));
3016 if (!Mask || Mask->getValueSizeInBits(0) > 64)
3019 if ((~Known.
Zero).getZExtValue() & ~Mask->getZExtValue())
3022 C.Op0 =
C.Op0.getOperand(0);
3034 C.CCValid = CCValid;
3037 C.CCMask =
CC < 4 ? 1 << (3 -
CC) : 0;
3040 C.CCMask =
CC < 4 ? ~(1 << (3 -
CC)) : -1;
3044 C.CCMask =
CC < 4 ? ~0U << (4 -
CC) : -1;
3047 C.CCMask =
CC < 4 ? ~(~0U << (4 -
CC)) : 0;
3051 C.CCMask =
CC < 4 ? ~0U << (3 -
CC) : -1;
3054 C.CCMask =
CC < 4 ? ~(~0U << (3 -
CC)) : 0;
3057 C.CCMask &= CCValid;
3065 bool IsSignaling =
false) {
3068 unsigned Opcode, CCValid;
3080 Comparison
C(CmpOp0, CmpOp1, Chain);
3082 if (
C.Op0.getValueType().isFloatingPoint()) {
3086 else if (!IsSignaling)
3108 C.CCMask &= ~SystemZ::CCMASK_CMP_UO;
3129 if (!
C.Op1.getNode()) {
3131 switch (
C.Op0.getOpcode()) {
3158 return DAG.
getNode(
C.Opcode,
DL, VTs,
C.Chain,
C.Op0,
C.Op1);
3160 return DAG.
getNode(
C.Opcode,
DL, MVT::i32,
C.Op0,
C.Op1);
3169 Op0 = DAG.
getNode(Extend,
DL, MVT::i64, Op0);
3170 Op1 = DAG.
getNode(Extend,
DL, MVT::i64, Op1);
3195 unsigned CCValid,
unsigned CCMask) {
3224 case CmpMode::Int:
return 0;
3244 case CmpMode::FP:
return 0;
3245 case CmpMode::StrictFP:
return 0;
3246 case CmpMode::SignalingFP:
return 0;
3278 int Mask[] = { Start, -1, Start + 1, -1 };
3298 !Subtarget.hasVectorEnhancements1()) {
3312 SDValue Ops[2] = { Res, NewChain };
3321 return DAG.
getNode(Opcode,
DL, VTs, Chain, CmpOp0, CmpOp1);
3323 return DAG.
getNode(Opcode,
DL, VT, CmpOp0, CmpOp1);
3336 bool IsSignaling)
const {
3339 assert (!IsSignaling || Chain);
3340 CmpMode Mode = IsSignaling ? CmpMode::SignalingFP :
3341 Chain ? CmpMode::StrictFP : IsFP ? CmpMode::FP : CmpMode::Int;
3342 bool Invert =
false;
3350 assert(IsFP &&
"Unexpected integer comparison");
3352 DL, VT, CmpOp1, CmpOp0, Chain);
3354 DL, VT, CmpOp0, CmpOp1, Chain);
3358 LT.getValue(1),
GE.getValue(1));
3367 assert(IsFP &&
"Unexpected integer comparison");
3369 DL, VT, CmpOp1, CmpOp0, Chain);
3371 DL, VT, CmpOp0, CmpOp1, Chain);
3375 LT.getValue(1),
GT.getValue(1));
3384 Cmp = getVectorCmp(DAG, Opcode,
DL, VT, CmpOp0, CmpOp1, Chain);
3388 Cmp = getVectorCmp(DAG, Opcode,
DL, VT, CmpOp1, CmpOp0, Chain);
3393 Chain =
Cmp.getValue(1);
3401 if (Chain && Chain.
getNode() !=
Cmp.getNode()) {
3414 EVT VT =
Op.getValueType();
3416 return lowerVectorSETCC(DAG,
DL, VT,
CC, CmpOp0, CmpOp1);
3418 Comparison
C(
getCmp(DAG, CmpOp0, CmpOp1,
CC,
DL));
3425 bool IsSignaling)
const {
3431 EVT VT =
Op.getNode()->getValueType(0);
3433 SDValue Res = lowerVectorSETCC(DAG,
DL, VT,
CC, CmpOp0, CmpOp1,
3434 Chain, IsSignaling);
3438 Comparison
C(
getCmp(DAG, CmpOp0, CmpOp1,
CC,
DL, Chain, IsSignaling));
3453 Comparison
C(
getCmp(DAG, CmpOp0, CmpOp1,
CC,
DL));
3490 Comparison
C(
getCmp(DAG, CmpOp0, CmpOp1,
CC,
DL));
3498 cast<ConstantSDNode>(
C.Op1)->getValueSizeInBits(0) <= 64 &&
3499 C.Op1->getAsZExtVal() == 0) {
3507 SDValue Ops[] = {TrueOp, FalseOp,
3581 Chain = DAG.
getCopyToReg(Chain,
DL, SystemZ::R2D, GOTOffset, Glue);
3588 Node->getValueType(0),
3600 assert(Mask &&
"Missing call preserved mask for calling convention");
3608 Chain = DAG.
getNode(Opcode,
DL, NodeTys, Ops);
3615SDValue SystemZTargetLowering::lowerThreadPointer(
const SDLoc &
DL,
3647 SDValue TP = lowerThreadPointer(
DL, DAG);
3755 if (
CP->isMachineConstantPoolEntry())
3774 unsigned Depth =
Op.getConstantOperandVal(0);
3781 int BackChainIdx = TFL->getOrCreateFramePointerSaveIndex(MF);
3810 unsigned Depth =
Op.getConstantOperandVal(0);
3818 SDValue FrameAddr = lowerFRAMEADDR(
Op, DAG);
3820 int Offset = (TFL->usePackedStack(MF) ? -2 : 14) *
3837 EVT InVT =
In.getValueType();
3838 EVT ResVT =
Op.getValueType();
3843 if (
auto *LoadN = dyn_cast<LoadSDNode>(In))
3846 LoadN->getBasePtr(), LoadN->getMemOperand());
3852 if (InVT == MVT::i32 && ResVT == MVT::f32) {
3854 if (Subtarget.hasHighWord()) {
3858 MVT::i64,
SDValue(U64, 0), In);
3866 DL, MVT::f32, Out64);
3868 if (InVT == MVT::f32 && ResVT == MVT::i32) {
3871 MVT::f64,
SDValue(U64, 0), In);
3873 if (Subtarget.hasHighWord())
3887 return lowerVASTART_XPLINK(
Op, DAG);
3889 return lowerVASTART_ELF(
Op, DAG);
3904 const Value *SV = cast<SrcValueSDNode>(
Op.getOperand(2))->getValue();
3918 const Value *SV = cast<SrcValueSDNode>(
Op.getOperand(2))->getValue();
3922 const unsigned NumFields = 4;
3933 for (
unsigned I = 0;
I < NumFields; ++
I) {
3938 MemOps[
I] = DAG.
getStore(Chain,
DL, Fields[
I], FieldAddr,
3950 const Value *DstSV = cast<SrcValueSDNode>(
Op.getOperand(3))->getValue();
3951 const Value *SrcSV = cast<SrcValueSDNode>(
Op.getOperand(4))->getValue();
3957 Align(8),
false,
false,
3963SystemZTargetLowering::lowerDYNAMIC_STACKALLOC(
SDValue Op,
3966 return lowerDYNAMIC_STACKALLOC_XPLINK(
Op, DAG);
3968 return lowerDYNAMIC_STACKALLOC_ELF(
Op, DAG);
3972SystemZTargetLowering::lowerDYNAMIC_STACKALLOC_XPLINK(
SDValue Op,
3984 uint64_t AlignVal = (RealignOpt ?
Align->getAsZExtVal() : 0);
3987 uint64_t RequiredAlign = std::max(AlignVal, StackAlign);
3988 uint64_t ExtraAlignSpace = RequiredAlign - StackAlign;
3994 if (ExtraAlignSpace)
3998 bool IsSigned =
false;
3999 bool DoesNotReturn =
false;
4000 bool IsReturnValueUsed =
false;
4001 EVT VT =
Op.getValueType();
4012 Register SPReg = Regs.getStackPointerRegister();
4023 if (ExtraAlignSpace) {
4035SystemZTargetLowering::lowerDYNAMIC_STACKALLOC_ELF(
SDValue Op,
4049 uint64_t AlignVal = (RealignOpt ?
Align->getAsZExtVal() : 0);
4052 uint64_t RequiredAlign = std::max(AlignVal, StackAlign);
4053 uint64_t ExtraAlignSpace = RequiredAlign - StackAlign;
4064 Backchain = DAG.
getLoad(MVT::i64,
DL, Chain, getBackchainAddress(OldSP, DAG),
4068 if (ExtraAlignSpace)
4076 DAG.
getVTList(MVT::i64, MVT::Other), Chain, OldSP, NeededSpace);
4092 if (RequiredAlign > StackAlign) {
4102 Chain = DAG.
getStore(Chain,
DL, Backchain, getBackchainAddress(NewSP, DAG),
4109SDValue SystemZTargetLowering::lowerGET_DYNAMIC_AREA_OFFSET(
4118 EVT VT =
Op.getValueType();
4125 Op.getOperand(1), Ops[1], Ops[0]);
4126 else if (Subtarget.hasMiscellaneousExtensions2())
4131 Op.getOperand(0),
Op.getOperand(1), Ops[1], Ops[0]);
4155 LL, RL, Ops[1], Ops[0]);
4166 EVT VT =
Op.getValueType();
4173 Op.getOperand(1), Ops[1], Ops[0]);
4179 Op.getOperand(0),
Op.getOperand(1), Ops[1], Ops[0]);
4187 EVT VT =
Op.getValueType();
4207 EVT VT =
Op.getValueType();
4214 Op.getOperand(0),
Op.getOperand(1), Ops[1], Ops[0]);
4219 assert(
Op.getValueType() == MVT::i64 &&
"Should be 64-bit operation");
4222 SDValue Ops[] = {
Op.getOperand(0),
Op.getOperand(1)};
4231 if ((Masks[0] >> 32) == 0xffffffff &&
uint32_t(Masks[1]) == 0xffffffff)
4233 else if ((Masks[1] >> 32) == 0xffffffff &&
uint32_t(Masks[0]) == 0xffffffff)
4249 if (!isInt<16>(
Value))
4270 MVT::i64, HighOp, Low32);
4281 if (
N->getValueType(0) == MVT::i128) {
4282 unsigned BaseOp = 0;
4283 unsigned FlagOp = 0;
4284 bool IsBorrow =
false;
4285 switch (
Op.getOpcode()) {
4308 unsigned BaseOp = 0;
4309 unsigned CCValid = 0;
4310 unsigned CCMask = 0;
4312 switch (
Op.getOpcode()) {
4340 if (
N->getValueType(1) == MVT::i1)
4363 MVT VT =
N->getSimpleValueType(0);
4374 if (VT == MVT::i128) {
4375 unsigned BaseOp = 0;
4376 unsigned FlagOp = 0;
4377 bool IsBorrow =
false;
4378 switch (
Op.getOpcode()) {
4405 unsigned BaseOp = 0;
4406 unsigned CCValid = 0;
4407 unsigned CCMask = 0;
4409 switch (
Op.getOpcode()) {
4438 if (
N->getValueType(1) == MVT::i1)
4446 EVT VT =
Op.getValueType();
4448 Op =
Op.getOperand(0);
4496 if (NumSignificantBits == 0)
4502 BitSize = std::min(BitSize, OrigBitSize);
4511 for (int64_t
I = BitSize / 2;
I >= 8;
I =
I / 2) {
4513 if (BitSize != OrigBitSize)
4550 auto *
Node = cast<AtomicSDNode>(
Op.getNode());
4551 assert(
Node->getMemoryVT() == MVT::i128 &&
"Only custom lowering i128.");
4563 EVT PtrVT =
Addr.getValueType();
4564 EVT WideVT = MVT::i32;
4587 unsigned Opcode)
const {
4588 auto *
Node = cast<AtomicSDNode>(
Op.getNode());
4591 EVT NarrowVT =
Node->getMemoryVT();
4592 EVT WideVT = MVT::i32;
4593 if (NarrowVT == WideVT)
4605 if (
auto *Const = dyn_cast<ConstantSDNode>(Src2)) {
4610 SDValue AlignedAddr, BitShift, NegBitShift;
4628 SDValue Ops[] = { ChainIn, AlignedAddr, Src2, BitShift, NegBitShift,
4647 auto *
Node = cast<AtomicSDNode>(
Op.getNode());
4648 EVT MemVT =
Node->getMemoryVT();
4649 if (MemVT == MVT::i32 || MemVT == MVT::i64) {
4651 assert(
Op.getValueType() == MemVT &&
"Mismatched VTs");
4652 assert(Subtarget.hasInterlockedAccess1() &&
4653 "Should have been expanded by AtomicExpand pass.");
4659 Node->getChain(),
Node->getBasePtr(), NegSrc2,
4660 Node->getMemOperand());
4669 auto *
Node = cast<AtomicSDNode>(
Op.getNode());
4677 if (
Node->getMemoryVT() == MVT::i128) {
4686 EVT NarrowVT =
Node->getMemoryVT();
4687 EVT WideVT = NarrowVT == MVT::i64 ? MVT::i64 : MVT::i32;
4688 if (NarrowVT == WideVT) {
4690 SDValue Ops[] = { ChainIn,
Addr, CmpVal, SwapVal };
4692 DL, Tys, Ops, NarrowVT, MMO);
4706 SDValue AlignedAddr, BitShift, NegBitShift;
4711 SDValue Ops[] = { ChainIn, AlignedAddr, CmpVal, SwapVal, BitShift,
4714 VTList, Ops, NarrowVT, MMO);
4728SystemZTargetLowering::getTargetMMOFlags(
const Instruction &
I)
const {
4733 if (
auto *SI = dyn_cast<StoreInst>(&
I))
4736 if (
auto *LI = dyn_cast<LoadInst>(&
I))
4739 if (
auto *AI = dyn_cast<AtomicRMWInst>(&
I))
4742 if (
auto *AI = dyn_cast<AtomicCmpXchgInst>(&
I))
4754 "in GHC calling convention");
4756 Regs->getStackPointerRegister(),
Op.getValueType());
4767 "in GHC calling convention");
4774 if (StoreBackchain) {
4776 Chain,
DL, Regs->getStackPointerRegister(), MVT::i64);
4777 Backchain = DAG.
getLoad(MVT::i64,
DL, Chain, getBackchainAddress(OldSP, DAG),
4781 Chain = DAG.
getCopyToReg(Chain,
DL, Regs->getStackPointerRegister(), NewSP);
4784 Chain = DAG.
getStore(Chain,
DL, Backchain, getBackchainAddress(NewSP, DAG),
4792 bool IsData =
Op.getConstantOperandVal(4);
4795 return Op.getOperand(0);
4798 bool IsWrite =
Op.getConstantOperandVal(2);
4800 auto *
Node = cast<MemIntrinsicSDNode>(
Op.getNode());
4804 Node->getVTList(), Ops,
4805 Node->getMemoryVT(),
Node->getMemOperand());
4817SystemZTargetLowering::lowerINTRINSIC_W_CHAIN(
SDValue Op,
4819 unsigned Opcode, CCValid;
4821 assert(
Op->getNumValues() == 2 &&
"Expected only CC result and chain");
4832SystemZTargetLowering::lowerINTRINSIC_WO_CHAIN(
SDValue Op,
4834 unsigned Opcode, CCValid;
4837 if (
Op->getNumValues() == 1)
4839 assert(
Op->getNumValues() == 2 &&
"Expected a CC and non-CC result");
4844 unsigned Id =
Op.getConstantOperandVal(0);
4846 case Intrinsic::thread_pointer:
4847 return lowerThreadPointer(
SDLoc(
Op), DAG);
4849 case Intrinsic::s390_vpdi:
4851 Op.getOperand(1),
Op.getOperand(2),
Op.getOperand(3));
4853 case Intrinsic::s390_vperm:
4855 Op.getOperand(1),
Op.getOperand(2),
Op.getOperand(3));
4857 case Intrinsic::s390_vuphb:
4858 case Intrinsic::s390_vuphh:
4859 case Intrinsic::s390_vuphf:
4863 case Intrinsic::s390_vuplhb:
4864 case Intrinsic::s390_vuplhh:
4865 case Intrinsic::s390_vuplhf:
4869 case Intrinsic::s390_vuplb:
4870 case Intrinsic::s390_vuplhw:
4871 case Intrinsic::s390_vuplf:
4875 case Intrinsic::s390_vupllb:
4876 case Intrinsic::s390_vupllh:
4877 case Intrinsic::s390_vupllf:
4881 case Intrinsic::s390_vsumb:
4882 case Intrinsic::s390_vsumh:
4883 case Intrinsic::s390_vsumgh:
4884 case Intrinsic::s390_vsumgf:
4885 case Intrinsic::s390_vsumqf:
4886 case Intrinsic::s390_vsumqg:
4888 Op.getOperand(1),
Op.getOperand(2));
4890 case Intrinsic::s390_vaq:
4892 Op.getOperand(1),
Op.getOperand(2));
4893 case Intrinsic::s390_vaccb:
4894 case Intrinsic::s390_vacch:
4895 case Intrinsic::s390_vaccf:
4896 case Intrinsic::s390_vaccg:
4897 case Intrinsic::s390_vaccq:
4899 Op.getOperand(1),
Op.getOperand(2));
4900 case Intrinsic::s390_vacq:
4902 Op.getOperand(1),
Op.getOperand(2),
Op.getOperand(3));
4903 case Intrinsic::s390_vacccq:
4905 Op.getOperand(1),
Op.getOperand(2),
Op.getOperand(3));
4907 case Intrinsic::s390_vsq:
4909 Op.getOperand(1),
Op.getOperand(2));
4910 case Intrinsic::s390_vscbib:
4911 case Intrinsic::s390_vscbih:
4912 case Intrinsic::s390_vscbif:
4913 case Intrinsic::s390_vscbig:
4914 case Intrinsic::s390_vscbiq:
4916 Op.getOperand(1),
Op.getOperand(2));
4917 case Intrinsic::s390_vsbiq:
4919 Op.getOperand(1),
Op.getOperand(2),
Op.getOperand(3));
4920 case Intrinsic::s390_vsbcbiq:
4922 Op.getOperand(1),
Op.getOperand(2),
Op.getOperand(3));
4943 { 0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 23 } },
4946 { 0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23 } },
4949 { 0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23 } },
4952 { 0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23 } },
4955 { 8, 9, 10, 11, 12, 13, 14, 15, 24, 25, 26, 27, 28, 29, 30, 31 } },
4958 { 8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 } },
4961 { 8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31 } },
4964 { 8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31 } },
4967 { 4, 5, 6, 7, 12, 13, 14, 15, 20, 21, 22, 23, 28, 29, 30, 31 } },
4970 { 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 } },
4973 { 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 } },
4976 { 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 } },
4979 { 0, 1, 2, 3, 4, 5, 6, 7, 24, 25, 26, 27, 28, 29, 30, 31 } }
4993 OpNo0 = OpNo1 = OpNos[1];
4994 }
else if (OpNos[1] < 0) {
4995 OpNo0 = OpNo1 = OpNos[0];
5013 unsigned &OpNo0,
unsigned &OpNo1) {
5014 int OpNos[] = { -1, -1 };
5027 if (OpNos[ModelOpNo] == 1 - RealOpNo)
5029 OpNos[ModelOpNo] = RealOpNo;
5037 unsigned &OpNo0,
unsigned &OpNo1) {
5054 int Elt = Bytes[
From];
5057 Transform[
From] = -1;
5059 while (
P.Bytes[To] != Elt) {
5064 Transform[
From] = To;
5087 if (
auto *VSN = dyn_cast<ShuffleVectorSDNode>(ShuffleOp)) {
5088 Bytes.
resize(NumElements * BytesPerElement, -1);
5089 for (
unsigned I = 0;
I < NumElements; ++
I) {
5090 int Index = VSN->getMaskElt(
I);
5092 for (
unsigned J = 0; J < BytesPerElement; ++J)
5093 Bytes[
I * BytesPerElement + J] =
Index * BytesPerElement + J;
5098 isa<ConstantSDNode>(ShuffleOp.
getOperand(1))) {
5100 Bytes.
resize(NumElements * BytesPerElement, -1);
5101 for (
unsigned I = 0;
I < NumElements; ++
I)
5102 for (
unsigned J = 0; J < BytesPerElement; ++J)
5103 Bytes[
I * BytesPerElement + J] =
Index * BytesPerElement + J;
5114 unsigned BytesPerElement,
int &
Base) {
5116 for (
unsigned I = 0;
I < BytesPerElement; ++
I) {
5117 if (Bytes[Start +
I] >= 0) {
5118 unsigned Elem = Bytes[Start +
I];
5122 if (
unsigned(
Base) % Bytes.
size() + BytesPerElement > Bytes.
size())
5124 }
else if (
unsigned(
Base) != Elem -
I)
5137 unsigned &StartIndex,
unsigned &OpNo0,
5139 int OpNos[] = { -1, -1 };
5141 for (
unsigned I = 0;
I < 16; ++
I) {
5148 Shift = ExpectedShift;
5149 else if (Shift != ExpectedShift)
5153 if (OpNos[ModelOpNo] == 1 - RealOpNo)
5155 OpNos[ModelOpNo] = RealOpNo;
5192 N =
N->getOperand(0);
5194 if (
auto *
Op = dyn_cast<ConstantSDNode>(
N->getOperand(0)))
5195 return Op->getZExtValue() == 0;
5201 for (
unsigned I = 0;
I < Num ;
I++)
5213 for (
unsigned I = 0;
I < 2; ++
I)
5217 unsigned StartIndex, OpNo0, OpNo1;
5226 if (ZeroVecIdx != UINT32_MAX) {
5227 bool MaskFirst =
true;
5232 if (OpNo == ZeroVecIdx &&
I == 0) {
5237 if (OpNo != ZeroVecIdx && Byte == 0) {
5244 if (ZeroIdx != -1) {
5247 if (Bytes[
I] >= 0) {
5250 if (OpNo == ZeroVecIdx)
5260 SDValue Src = ZeroVecIdx == 0 ? Ops[1] : Ops[0];
5278 (!Ops[1].
isUndef() ? Ops[1] : Ops[0]), Op2);
5283struct GeneralShuffle {
5284 GeneralShuffle(
EVT vt) : VT(vt), UnpackFromEltSize(UINT_MAX) {}
5288 void tryPrepareForUnpack();
5289 bool unpackWasPrepared() {
return UnpackFromEltSize <= 4; }
5304 unsigned UnpackFromEltSize;
5309void GeneralShuffle::addUndef() {
5311 for (
unsigned I = 0;
I < BytesPerElement; ++
I)
5312 Bytes.push_back(-1);
5321bool GeneralShuffle::add(
SDValue Op,
unsigned Elem) {
5327 EVT FromVT =
Op.getNode() ?
Op.getValueType() : VT;
5332 if (FromBytesPerElement < BytesPerElement)
5336 (FromBytesPerElement - BytesPerElement));
5339 while (
Op.getNode()) {
5341 Op =
Op.getOperand(0);
5357 }
else if (
Op.isUndef()) {
5366 for (; OpNo < Ops.size(); ++OpNo)
5367 if (Ops[OpNo] ==
Op)
5369 if (OpNo == Ops.size())
5374 for (
unsigned I = 0;
I < BytesPerElement; ++
I)
5375 Bytes.push_back(
Base +
I);
5384 if (Ops.size() == 0)
5388 tryPrepareForUnpack();
5391 if (Ops.size() == 1)
5392 Ops.push_back(DAG.
getUNDEF(MVT::v16i8));
5403 unsigned Stride = 1;
5404 for (; Stride * 2 < Ops.size(); Stride *= 2) {
5405 for (
unsigned I = 0;
I < Ops.size() - Stride;
I += Stride * 2) {
5406 SDValue SubOps[] = { Ops[
I], Ops[
I + Stride] };
5415 else if (OpNo ==
I + Stride)
5426 if (NewBytes[J] >= 0) {
5428 "Invalid double permute");
5431 assert(NewBytesMap[J] < 0 &&
"Invalid double permute");
5437 if (NewBytes[J] >= 0)
5445 Ops[1] = Ops[Stride];
5453 unsigned OpNo0, OpNo1;
5455 if (unpackWasPrepared() && Ops[1].
isUndef())
5457 else if (
const Permute *
P =
matchPermute(Bytes, OpNo0, OpNo1))
5462 Op = insertUnpackIfPrepared(DAG,
DL,
Op);
5469 dbgs() << Msg.c_str() <<
" { ";
5470 for (
unsigned i = 0; i < Bytes.
size(); i++)
5471 dbgs() << Bytes[i] <<
" ";
5479void GeneralShuffle::tryPrepareForUnpack() {
5481 if (ZeroVecOpNo == UINT32_MAX || Ops.size() == 1)
5486 if (Ops.size() > 2 &&
5491 UnpackFromEltSize = 1;
5492 for (; UnpackFromEltSize <= 4; UnpackFromEltSize *= 2) {
5493 bool MatchUnpack =
true;
5496 unsigned ToEltSize = UnpackFromEltSize * 2;
5497 bool IsZextByte = (Elt % ToEltSize) < UnpackFromEltSize;
5500 if (Bytes[Elt] != -1) {
5502 if (IsZextByte != (OpNo == ZeroVecOpNo)) {
5503 MatchUnpack =
false;
5509 if (Ops.size() == 2) {
5512 if (SrcBytes[i] != -1 && SrcBytes[i] % 16 !=
int(i)) {
5513 UnpackFromEltSize = UINT_MAX;
5520 if (UnpackFromEltSize > 4)
5523 LLVM_DEBUG(
dbgs() <<
"Preparing for final unpack of element size "
5524 << UnpackFromEltSize <<
". Zero vector is Op#" << ZeroVecOpNo
5526 dumpBytes(Bytes,
"Original Bytes vector:"););
5531 Elt += UnpackFromEltSize;
5532 for (
unsigned i = 0; i < UnpackFromEltSize; i++, Elt++,
B++)
5533 Bytes[
B] = Bytes[Elt];
5539 Ops.erase(&Ops[ZeroVecOpNo]);
5541 if (Bytes[
I] >= 0) {
5543 if (OpNo > ZeroVecOpNo)
5554 if (!unpackWasPrepared())
5556 unsigned InBits = UnpackFromEltSize * 8;
5560 unsigned OutBits = InBits * 2;
5569 if (!
Op.getOperand(
I).isUndef())
5585 if (
Value.isUndef())
5638 GeneralShuffle GS(VT);
5640 bool FoundOne =
false;
5641 for (
unsigned I = 0;
I < NumElements; ++
I) {
5644 Op =
Op.getOperand(0);
5647 unsigned Elem =
Op.getConstantOperandVal(1);
5648 if (!GS.add(
Op.getOperand(0), Elem))
5651 }
else if (
Op.isUndef()) {
5665 if (!ResidueOps.
empty()) {
5666 while (ResidueOps.
size() < NumElements)
5668 for (
auto &
Op : GS.Ops) {
5669 if (!
Op.getNode()) {
5675 return GS.getNode(DAG,
SDLoc(BVN));
5678bool SystemZTargetLowering::isVectorElementLoad(
SDValue Op)
const {
5679 if (
Op.getOpcode() ==
ISD::LOAD && cast<LoadSDNode>(
Op)->isUnindexed())
5681 if (
auto *AL = dyn_cast<AtomicSDNode>(
Op))
5695 unsigned int NumElements = Elems.
size();
5696 unsigned int Count = 0;
5697 for (
auto Elem : Elems) {
5698 if (!Elem.isUndef()) {
5701 else if (Elem != Single) {
5721 if (
Single.getNode() && (Count > 1 || isVectorElementLoad(Single)))
5725 bool AllLoads =
true;
5726 for (
auto Elem : Elems)
5727 if (!isVectorElementLoad(Elem)) {
5733 if (VT == MVT::v2i64 && !AllLoads)
5737 if (VT == MVT::v2f64 && !AllLoads)
5747 if (VT == MVT::v4f32 && !AllLoads) {
5761 DL, MVT::v2i64, Op01, Op23);
5769 unsigned NumConstants = 0;
5770 for (
unsigned I = 0;
I < NumElements; ++
I) {
5784 if (NumConstants > 0) {
5785 for (
unsigned I = 0;
I < NumElements; ++
I)
5796 std::map<const SDNode*, unsigned> UseCounts;
5797 SDNode *LoadMaxUses =
nullptr;
5798 for (
unsigned I = 0;
I < NumElements; ++
I)
5799 if (isVectorElementLoad(Elems[
I])) {
5800 SDNode *Ld = Elems[
I].getNode();
5802 if (LoadMaxUses ==
nullptr || UseCounts[LoadMaxUses] < UseCounts[Ld])
5805 if (LoadMaxUses !=
nullptr) {
5806 ReplicatedVal =
SDValue(LoadMaxUses, 0);
5810 unsigned I1 = NumElements / 2 - 1;
5811 unsigned I2 = NumElements - 1;
5812 bool Def1 = !Elems[
I1].isUndef();
5813 bool Def2 = !Elems[I2].isUndef();
5827 for (
unsigned I = 0;
I < NumElements; ++
I)
5828 if (!
Done[
I] && !Elems[
I].
isUndef() && Elems[
I] != ReplicatedVal)
5836 auto *BVN = cast<BuildVectorSDNode>(
Op.getNode());
5838 EVT VT =
Op.getValueType();
5840 if (BVN->isConstant()) {
5859 for (
unsigned I = 0;
I < NumElements; ++
I)
5860 Ops[
I] =
Op.getOperand(
I);
5861 return buildVector(DAG,
DL, VT, Ops);
5866 auto *VSN = cast<ShuffleVectorSDNode>(
Op.getNode());
5868 EVT VT =
Op.getValueType();
5871 if (VSN->isSplat()) {
5873 unsigned Index = VSN->getSplatIndex();
5875 "Splat index should be defined and in first operand");
5885 GeneralShuffle
GS(VT);
5886 for (
unsigned I = 0;
I < NumElements; ++
I) {
5887 int Elt = VSN->getMaskElt(
I);
5890 else if (!
GS.add(
Op.getOperand(
unsigned(Elt) / NumElements),
5891 unsigned(Elt) % NumElements))
5894 return GS.getNode(DAG,
SDLoc(VSN));
5913 EVT VT =
Op.getValueType();
5918 if (VT == MVT::v2f64 &&
5938SystemZTargetLowering::lowerEXTRACT_VECTOR_ELT(
SDValue Op,
5944 EVT VT =
Op.getValueType();
5948 if (
auto *CIndexN = dyn_cast<ConstantSDNode>(Op1)) {
5963SDValue SystemZTargetLowering::
5966 EVT OutVT =
Op.getValueType();
5976 }
while (FromBits != ToBits);
5981SDValue SystemZTargetLowering::
5985 EVT OutVT =
Op.getValueType();
5989 unsigned NumInPerOut = InNumElts / OutNumElts;
5995 unsigned ZeroVecElt = InNumElts;
5996 for (
unsigned PackedElt = 0; PackedElt < OutNumElts; PackedElt++) {
5997 unsigned MaskElt = PackedElt * NumInPerOut;
5998 unsigned End = MaskElt + NumInPerOut - 1;
5999 for (; MaskElt <
End; MaskElt++)
6000 Mask[MaskElt] = ZeroVecElt++;
6001 Mask[MaskElt] = PackedElt;
6008 unsigned ByScalar)
const {
6013 EVT VT =
Op.getValueType();
6017 if (
auto *BVN = dyn_cast<BuildVectorSDNode>(Op1)) {
6018 APInt SplatBits, SplatUndef;
6019 unsigned SplatBitSize;
6023 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs,
6024 ElemBitSize,
true) &&
6025 SplatBitSize == ElemBitSize) {
6028 return DAG.
getNode(ByScalar,
DL, VT, Op0, Shift);
6037 return DAG.
getNode(ByScalar,
DL, VT, Op0, Shift);
6043 if (
auto *VSN = dyn_cast<ShuffleVectorSDNode>(Op1)) {
6044 if (VSN->isSplat()) {
6046 unsigned Index = VSN->getSplatIndex();
6048 "Splat index should be defined and in first operand");
6055 return DAG.
getNode(ByScalar,
DL, VT, Op0, Shift);
6067 MVT ResultVT =
Op.getSimpleValueType();
6069 unsigned Check =
Op.getConstantOperandVal(1);
6071 unsigned TDCMask = 0;
6105 int SPFI = cast<FrameIndexSDNode>(
StackPtr.getNode())->getIndex();
6116 return DAG.
getLoad(MVT::i64,
DL, Chain, StackPtr, MPI);
6121 switch (
Op.getOpcode()) {
6123 return lowerFRAMEADDR(
Op, DAG);
6125 return lowerRETURNADDR(
Op, DAG);
6127 return lowerBR_CC(
Op, DAG);
6129 return lowerSELECT_CC(
Op, DAG);
6131 return lowerSETCC(
Op, DAG);
6133 return lowerSTRICT_FSETCC(
Op, DAG,
false);
6135 return lowerSTRICT_FSETCC(
Op, DAG,
true);
6137 return lowerGlobalAddress(cast<GlobalAddressSDNode>(
Op), DAG);
6139 return lowerGlobalTLSAddress(cast<GlobalAddressSDNode>(
Op), DAG);
6141 return lowerBlockAddress(cast<BlockAddressSDNode>(
Op), DAG);
6143 return lowerJumpTable(cast<JumpTableSDNode>(
Op), DAG);
6145 return lowerConstantPool(cast<ConstantPoolSDNode>(
Op), DAG);
6147 return lowerBITCAST(
Op, DAG);
6149 return lowerVASTART(
Op, DAG);
6151 return lowerVACOPY(
Op, DAG);
6153 return lowerDYNAMIC_STACKALLOC(
Op, DAG);
6155 return lowerGET_DYNAMIC_AREA_OFFSET(
Op, DAG);
6157 return lowerSMUL_LOHI(
Op, DAG);
6159 return lowerUMUL_LOHI(
Op, DAG);
6161 return lowerSDIVREM(
Op, DAG);
6163 return lowerUDIVREM(
Op, DAG);
6168 return lowerXALUO(
Op, DAG);
6171 return lowerUADDSUBO_CARRY(
Op, DAG);
6173 return lowerOR(
Op, DAG);
6175 return lowerCTPOP(
Op, DAG);
6177 return lowerVECREDUCE_ADD(
Op, DAG);
6179 return lowerATOMIC_FENCE(
Op, DAG);
6184 return lowerATOMIC_LDST_I128(
Op, DAG);
6188 return lowerATOMIC_LOAD_SUB(
Op, DAG);
6206 return lowerATOMIC_CMP_SWAP(
Op, DAG);
6208 return lowerSTACKSAVE(
Op, DAG);
6210 return lowerSTACKRESTORE(
Op, DAG);
6212 return lowerPREFETCH(
Op, DAG);
6214 return lowerINTRINSIC_W_CHAIN(
Op, DAG);
6216 return lowerINTRINSIC_WO_CHAIN(
Op, DAG);
6218 return lowerBUILD_VECTOR(
Op, DAG);
6220 return lowerVECTOR_SHUFFLE(
Op, DAG);
6222 return lowerSCALAR_TO_VECTOR(
Op, DAG);
6224 return lowerINSERT_VECTOR_ELT(
Op, DAG);
6226 return lowerEXTRACT_VECTOR_ELT(
Op, DAG);
6228 return lowerSIGN_EXTEND_VECTOR_INREG(
Op, DAG);
6230 return lowerZERO_EXTEND_VECTOR_INREG(
Op, DAG);
6240 return lowerIS_FPCLASS(
Op, DAG);
6242 return lowerGET_ROUNDING(
Op, DAG);
6244 return lowerREADCYCLECOUNTER(
Op, DAG);
6256 switch (
N->getOpcode()) {
6260 SDValue Ops[] = {
N->getOperand(0),
N->getOperand(1) };
6263 DL, Tys, Ops, MVT::i128, MMO);
6275 DL, Tys, Ops, MVT::i128, MMO);
6278 if (cast<AtomicSDNode>(
N)->getSuccessOrdering() ==
6281 MVT::Other, Res), 0);
6288 SDValue Ops[] = {
N->getOperand(0),
N->getOperand(1),
6293 DL, Tys, Ops, MVT::i128, MMO);
6304 if (
N->getValueType(0) == MVT::i128 && Src.getValueType() == MVT::f128 &&
6308 if (getRepRegClassFor(MVT::f128) == &SystemZ::VR128BitRegClass) {
6315 assert(getRepRegClassFor(MVT::f128) == &SystemZ::FP128BitRegClass &&
6316 "Unrecognized register class for f128.");
6341#define OPCODE(NAME) case SystemZISD::NAME: return "SystemZISD::" #NAME
6452 OPCODE(ATOMIC_LOADW_ADD);
6453 OPCODE(ATOMIC_LOADW_SUB);
6454 OPCODE(ATOMIC_LOADW_AND);
6456 OPCODE(ATOMIC_LOADW_XOR);
6457 OPCODE(ATOMIC_LOADW_NAND);
6458 OPCODE(ATOMIC_LOADW_MIN);
6459 OPCODE(ATOMIC_LOADW_MAX);
6460 OPCODE(ATOMIC_LOADW_UMIN);
6461 OPCODE(ATOMIC_LOADW_UMAX);
6462 OPCODE(ATOMIC_CMP_SWAPW);
6465 OPCODE(ATOMIC_STORE_128);
6466 OPCODE(ATOMIC_CMP_SWAP_128);
6481bool SystemZTargetLowering::canTreatAsByteVector(
EVT VT)
const {
6482 if (!Subtarget.hasVector())
6496 DAGCombinerInfo &DCI,
6504 unsigned Opcode =
Op.getOpcode();
6507 Op =
Op.getOperand(0);
6509 canTreatAsByteVector(
Op.getValueType())) {
6518 BytesPerElement,
First))
6525 if (Byte % BytesPerElement != 0)
6528 Index = Byte / BytesPerElement;
6532 canTreatAsByteVector(
Op.getValueType())) {
6535 EVT OpVT =
Op.getValueType();
6537 if (OpBytesPerElement < BytesPerElement)
6541 unsigned End = (
Index + 1) * BytesPerElement;
6542 if (
End % OpBytesPerElement != 0)
6545 Op =
Op.getOperand(
End / OpBytesPerElement - 1);
6546 if (!
Op.getValueType().isInteger()) {
6549 DCI.AddToWorklist(
Op.getNode());
6554 DCI.AddToWorklist(
Op.getNode());
6561 canTreatAsByteVector(
Op.getValueType()) &&
6562 canTreatAsByteVector(
Op.getOperand(0).getValueType())) {
6564 EVT ExtVT =
Op.getValueType();
6565 EVT OpVT =
Op.getOperand(0).getValueType();
6568 unsigned Byte =
Index * BytesPerElement;
6569 unsigned SubByte =
Byte % ExtBytesPerElement;
6570 unsigned MinSubByte = ExtBytesPerElement - OpBytesPerElement;
6571 if (SubByte < MinSubByte ||
6572 SubByte + BytesPerElement > ExtBytesPerElement)
6575 Byte =
Byte / ExtBytesPerElement * OpBytesPerElement;
6577 Byte += SubByte - MinSubByte;
6578 if (Byte % BytesPerElement != 0)
6580 Op =
Op.getOperand(0);
6587 if (
Op.getValueType() != VecVT) {
6589 DCI.AddToWorklist(
Op.getNode());
6599SDValue SystemZTargetLowering::combineTruncateExtract(
6608 if (canTreatAsByteVector(VecVT)) {
6609 if (
auto *IndexN = dyn_cast<ConstantSDNode>(
Op.getOperand(1))) {
6612 if (BytesPerElement % TruncBytes == 0) {
6618 unsigned Scale = BytesPerElement / TruncBytes;
6619 unsigned NewIndex = (IndexN->getZExtValue() + 1) * Scale - 1;
6625 EVT ResVT = (TruncBytes < 4 ? MVT::i32 : TruncVT);
6626 return combineExtract(
DL, ResVT, VecVT, Vec, NewIndex, DCI,
true);
6634SDValue SystemZTargetLowering::combineZERO_EXTEND(
6635 SDNode *
N, DAGCombinerInfo &DCI)
const {
6639 EVT VT =
N->getValueType(0);
6641 auto *TrueOp = dyn_cast<ConstantSDNode>(N0.
getOperand(0));
6642 auto *FalseOp = dyn_cast<ConstantSDNode>(N0.
getOperand(1));
6643 if (TrueOp && FalseOp) {
6653 DCI.CombineTo(N0.
getNode(), TruncSelect);
6683SDValue SystemZTargetLowering::combineSIGN_EXTEND_INREG(
6684 SDNode *
N, DAGCombinerInfo &DCI)
const {
6690 EVT VT =
N->getValueType(0);
6691 EVT EVT = cast<VTSDNode>(
N->getOperand(1))->getVT();
6704SDValue SystemZTargetLowering::combineSIGN_EXTEND(
6705 SDNode *
N, DAGCombinerInfo &DCI)
const {
6711 EVT VT =
N->getValueType(0);
6713 auto *SraAmt = dyn_cast<ConstantSDNode>(N0.
getOperand(1));
6716 if (
auto *ShlAmt = dyn_cast<ConstantSDNode>(Inner.
getOperand(1))) {
6718 unsigned NewShlAmt = ShlAmt->getZExtValue() + Extra;
6719 unsigned NewSraAmt = SraAmt->getZExtValue() + Extra;
6735SDValue SystemZTargetLowering::combineMERGE(
6736 SDNode *
N, DAGCombinerInfo &DCI)
const {
6738 unsigned Opcode =
N->getOpcode();
6746 if (Op1 ==
N->getOperand(0))
6751 if (ElemBytes <= 4) {
6759 DCI.AddToWorklist(Op1.
getNode());
6762 DCI.AddToWorklist(
Op.getNode());
6769SDValue SystemZTargetLowering::combineLOAD(
6770 SDNode *
N, DAGCombinerInfo &DCI)
const {
6772 EVT LdVT =
N->getValueType(0);
6777 if (LdVT == MVT::i128) {
6784 int UsedElements = 0;
6786 UI != UIEnd; ++UI) {
6788 if (UI.getUse().getResNo() != 0)
6801 User->getValueType(0) != MVT::i64)
6805 if (UsedElements & (1 <<
Index))
6808 UsedElements |= 1 <<
Index;
6814 for (
auto UserAndIndex :
Users) {
6816 unsigned Offset =
User->getValueType(0).getStoreSize() * UserAndIndex.second;
6821 LD->getPointerInfo().getWithOffset(
Offset),
6822 LD->getOriginalAlign(),
LD->getMemOperand()->getFlags(),
6825 DCI.CombineTo(
User, EltLoad,
true);
6833 DCI.AddToWorklist(Chain.
getNode());
6854 else if (UI.getUse().getResNo() == 0)
6857 if (!Replicate || OtherUses.
empty())
6863 for (
SDNode *U : OtherUses) {
6872bool SystemZTargetLowering::canLoadStoreByteSwapped(
EVT VT)
const {
6873 if (VT == MVT::i16 || VT == MVT::i32 || VT == MVT::i64)
6875 if (Subtarget.hasVectorEnhancements2())
6876 if (VT == MVT::v8i16 || VT == MVT::v4i32 || VT == MVT::v2i64 || VT == MVT::i128)
6888 for (
unsigned i = 0; i < NumElts; ++i) {
6889 if (M[i] < 0)
continue;
6890 if ((
unsigned) M[i] != NumElts - 1 - i)
6898 for (
auto *U : StoredVal->
uses()) {
6900 EVT CurrMemVT = ST->getMemoryVT().getScalarType();
6903 }
else if (isa<BuildVectorSDNode>(U)) {
6941SDValue SystemZTargetLowering::combineSTORE(
6942 SDNode *
N, DAGCombinerInfo &DCI)
const {
6944 auto *SN = cast<StoreSDNode>(
N);
6945 auto &Op1 =
N->getOperand(1);
6946 EVT MemVT = SN->getMemoryVT();
6951 if (MemVT.
isInteger() && SN->isTruncatingStore()) {
6953 combineTruncateExtract(
SDLoc(
N), MemVT, SN->getValue(), DCI)) {
6954 DCI.AddToWorklist(
Value.getNode());
6958 SN->getBasePtr(), SN->getMemoryVT(),
6959 SN->getMemOperand());
6963 if (!SN->isTruncatingStore() &&
6974 N->getOperand(0), BSwapOp,
N->getOperand(2)
6979 Ops, MemVT, SN->getMemOperand());
6982 if (!SN->isTruncatingStore() &&
6985 Subtarget.hasVectorEnhancements2()) {
6995 Ops, MemVT, SN->getMemOperand());
7000 if (!SN->isTruncatingStore() &&
7003 N->getOperand(0).reachesChainWithoutSideEffects(
SDValue(Op1.
getNode(), 1))) {
7007 Ops, MemVT, SN->getMemOperand());
7016 DAG.
getStore(SN->getChain(),
DL, HiPart, SN->getBasePtr(),
7017 SN->getPointerInfo(), SN->getOriginalAlign(),
7018 SN->getMemOperand()->getFlags(), SN->getAAInfo());
7023 SN->getPointerInfo().getWithOffset(8),
7024 SN->getOriginalAlign(),
7025 SN->getMemOperand()->
getFlags(), SN->getAAInfo());
7045 if (
C->getAPIntValue().getBitWidth() > 64 ||
C->isAllOnes() ||
7049 if (VCI.isVectorConstantLegal(Subtarget) &&
7058 auto FindReplicatedReg = [&](
SDValue MulOp) {
7059 EVT MulVT = MulOp.getValueType();
7060 if (MulOp->getOpcode() ==
ISD::MUL &&
7061 (MulVT == MVT::i16 || MulVT == MVT::i32 || MulVT == MVT::i64)) {
7065 WordVT =
LHS->getOperand(0).getValueType();
7067 WordVT = cast<VTSDNode>(
LHS->getOperand(1))->getVT();
7071 if (
auto *
C = dyn_cast<ConstantSDNode>(MulOp->getOperand(1))) {
7073 APInt(MulVT.getSizeInBits(),
C->getZExtValue()));
7074 if (VCI.isVectorConstantLegal(Subtarget) &&
7076 WordVT == VCI.VecVT.getScalarType())
7082 if (isa<BuildVectorSDNode>(Op1) &&
7085 if (
auto *
C = dyn_cast<ConstantSDNode>(SplatVal))
7088 FindReplicatedReg(SplatVal);
7090 if (
auto *
C = dyn_cast<ConstantSDNode>(Op1))
7093 FindReplicatedReg(Op1);
7098 "Bad type handling");
7103 SN->getBasePtr(), SN->getMemOperand());
7110SDValue SystemZTargetLowering::combineVECTOR_SHUFFLE(
7111 SDNode *
N, DAGCombinerInfo &DCI)
const {
7115 N->getOperand(0).hasOneUse() &&
7116 Subtarget.hasVectorEnhancements2()) {
7131 Ops,
LD->getMemoryVT(),
LD->getMemOperand());
7135 DCI.CombineTo(
N, ESLoad);
7139 DCI.CombineTo(
Load.getNode(), ESLoad, ESLoad.
getValue(1));
7149SDValue SystemZTargetLowering::combineEXTRACT_VECTOR_ELT(
7150 SDNode *
N, DAGCombinerInfo &DCI)
const {
7153 if (!Subtarget.hasVector())
7159 Op.getValueType().isVector() &&
7160 Op.getOperand(0).getValueType().isVector() &&
7161 Op.getValueType().getVectorNumElements() ==
7162 Op.getOperand(0).getValueType().getVectorNumElements())
7163 Op =
Op.getOperand(0);
7167 EVT VecVT =
Op.getValueType();
7170 Op.getOperand(0),
N->getOperand(1));
7171 DCI.AddToWorklist(
Op.getNode());
7173 if (EltVT !=
N->getValueType(0)) {
7174 DCI.AddToWorklist(
Op.getNode());
7181 if (
auto *IndexN = dyn_cast<ConstantSDNode>(
N->getOperand(1))) {
7184 return combineExtract(
SDLoc(
N),
N->getValueType(0), VecVT, Op0,
7185 IndexN->getZExtValue(), DCI,
false);
7190SDValue SystemZTargetLowering::combineJOIN_DWORDS(
7191 SDNode *
N, DAGCombinerInfo &DCI)
const {
7194 if (
N->getOperand(0) ==
N->getOperand(1))
7205 if (Chain1 == Chain2)
7213SDValue SystemZTargetLowering::combineFP_ROUND(
7214 SDNode *
N, DAGCombinerInfo &DCI)
const {
7216 if (!Subtarget.hasVector())
7225 unsigned OpNo =
N->isStrictFPOpcode() ? 1 : 0;
7228 if (
N->getValueType(0) == MVT::f32 && Op0.
hasOneUse() &&
7234 for (
auto *U : Vec->
uses()) {
7235 if (U != Op0.
getNode() &&
U->hasOneUse() &&
7237 U->getOperand(0) == Vec &&
7239 U->getConstantOperandVal(1) == 1) {
7241 if (OtherRound.
getOpcode() ==
N->getOpcode() &&
7245 if (
N->isStrictFPOpcode()) {
7250 {MVT::v4f32, MVT::Other}, {Chain, Vec});
7255 DCI.AddToWorklist(VRound.
getNode());
7259 DCI.AddToWorklist(Extract1.
getNode());
7268 N->getVTList(), Extract0, Chain);
7277SDValue SystemZTargetLowering::combineFP_EXTEND(
7278 SDNode *
N, DAGCombinerInfo &DCI)
const {
7280 if (!Subtarget.hasVector())
7289 unsigned OpNo =
N->isStrictFPOpcode() ? 1 : 0;
7292 if (
N->getValueType(0) == MVT::f64 && Op0.
hasOneUse() &&
7298 for (
auto *U : Vec->
uses()) {
7299 if (U != Op0.
getNode() &&
U->hasOneUse() &&
7301 U->getOperand(0) == Vec &&
7303 U->getConstantOperandVal(1) == 2) {
7305 if (OtherExtend.
getOpcode() ==
N->getOpcode() &&
7309 if (
N->isStrictFPOpcode()) {
7314 {MVT::v2f64, MVT::Other}, {Chain, Vec});
7319 DCI.AddToWorklist(VExtend.
getNode());
7323 DCI.AddToWorklist(Extract1.
getNode());
7332 N->getVTList(), Extract0, Chain);
7341SDValue SystemZTargetLowering::combineINT_TO_FP(
7342 SDNode *
N, DAGCombinerInfo &DCI)
const {
7347 unsigned Opcode =
N->getOpcode();
7348 EVT OutVT =
N->getValueType(0);
7352 unsigned InScalarBits =
Op->getValueType(0).getScalarSizeInBits();
7358 if (OutLLVMTy->
isVectorTy() && OutScalarBits > InScalarBits &&
7359 OutScalarBits <= 64) {
7360 unsigned NumElts = cast<FixedVectorType>(OutLLVMTy)->getNumElements();
7363 unsigned ExtOpcode =
7371SDValue SystemZTargetLowering::combineBSWAP(
7372 SDNode *
N, DAGCombinerInfo &DCI)
const {
7376 N->getOperand(0).hasOneUse() &&
7377 canLoadStoreByteSwapped(
N->getValueType(0))) {
7386 EVT LoadVT =
N->getValueType(0);
7387 if (LoadVT == MVT::i16)
7392 Ops,
LD->getMemoryVT(),
LD->getMemOperand());
7396 if (
N->getValueType(0) == MVT::i16)
7401 DCI.CombineTo(
N, ResVal);
7405 DCI.CombineTo(
Load.getNode(), ResVal, BSLoad.
getValue(1));
7414 Op.getValueType().isVector() &&
7415 Op.getOperand(0).getValueType().isVector() &&
7416 Op.getValueType().getVectorNumElements() ==
7417 Op.getOperand(0).getValueType().getVectorNumElements())
7418 Op =
Op.getOperand(0);
7430 (canLoadStoreByteSwapped(
N->getValueType(0)) &&
7432 EVT VecVT =
N->getValueType(0);
7433 EVT EltVT =
N->getValueType(0).getVectorElementType();
7436 DCI.AddToWorklist(Vec.
getNode());
7440 DCI.AddToWorklist(Elt.
getNode());
7443 DCI.AddToWorklist(Vec.
getNode());
7445 DCI.AddToWorklist(Elt.
getNode());
7453 if (SV &&
Op.hasOneUse()) {
7461 EVT VecVT =
N->getValueType(0);
7464 DCI.AddToWorklist(Op0.
getNode());
7468 DCI.AddToWorklist(Op1.
getNode());
7471 DCI.AddToWorklist(Op0.
getNode());
7473 DCI.AddToWorklist(Op1.
getNode());
7495 auto *CompareRHS = dyn_cast<ConstantSDNode>(ICmp->getOperand(1));
7502 bool Invert =
false;
7509 auto *TrueVal = dyn_cast<ConstantSDNode>(CompareLHS->getOperand(0));
7512 auto *FalseVal = dyn_cast<ConstantSDNode>(CompareLHS->getOperand(1));
7515 if (CompareRHS->getZExtValue() == FalseVal->getZExtValue())
7517 else if (CompareRHS->getZExtValue() != TrueVal->getZExtValue())
7521 auto *NewCCValid = dyn_cast<ConstantSDNode>(CompareLHS->getOperand(2));
7522 auto *NewCCMask = dyn_cast<ConstantSDNode>(CompareLHS->getOperand(3));
7523 if (!NewCCValid || !NewCCMask)
7525 CCValid = NewCCValid->getZExtValue();
7526 CCMask = NewCCMask->getZExtValue();
7536 if (CompareLHS->getOpcode() ==
ISD::SRA) {
7537 auto *SRACount = dyn_cast<ConstantSDNode>(CompareLHS->getOperand(1));
7538 if (!SRACount || SRACount->getZExtValue() != 30)
7540 auto *SHL = CompareLHS->getOperand(0).getNode();
7543 auto *SHLCount = dyn_cast<ConstantSDNode>(SHL->getOperand(1));
7546 auto *IPM = SHL->getOperand(0).getNode();
7551 if (!CompareLHS->hasOneUse())
7554 if (CompareRHS->getZExtValue() != 0)
7561 CCReg = IPM->getOperand(0);
7568SDValue SystemZTargetLowering::combineBR_CCMASK(
7569 SDNode *
N, DAGCombinerInfo &DCI)
const {
7573 auto *CCValid = dyn_cast<ConstantSDNode>(
N->getOperand(1));
7574 auto *CCMask = dyn_cast<ConstantSDNode>(
N->getOperand(2));
7575 if (!CCValid || !CCMask)
7578 int CCValidVal = CCValid->getZExtValue();
7579 int CCMaskVal = CCMask->getZExtValue();
7588 N->getOperand(3), CCReg);
7592SDValue SystemZTargetLowering::combineSELECT_CCMASK(
7593 SDNode *
N, DAGCombinerInfo &DCI)
const {
7597 auto *CCValid = dyn_cast<ConstantSDNode>(
N->getOperand(2));
7598 auto *CCMask = dyn_cast<ConstantSDNode>(
N->getOperand(3));
7599 if (!CCValid || !CCMask)
7602 int CCValidVal = CCValid->getZExtValue();
7603 int CCMaskVal = CCMask->getZExtValue();
7608 N->getOperand(0),
N->getOperand(1),
7616SDValue SystemZTargetLowering::combineGET_CCMASK(
7617 SDNode *
N, DAGCombinerInfo &DCI)
const {
7620 auto *CCValid = dyn_cast<ConstantSDNode>(
N->getOperand(1));
7621 auto *CCMask = dyn_cast<ConstantSDNode>(
N->getOperand(2));
7622 if (!CCValid || !CCMask)
7624 int CCValidVal = CCValid->getZExtValue();
7625 int CCMaskVal = CCMask->getZExtValue();
7633 auto *SelectCCValid = dyn_cast<ConstantSDNode>(
Select->getOperand(2));
7634 auto *SelectCCMask = dyn_cast<ConstantSDNode>(
Select->getOperand(3));
7635 if (!SelectCCValid || !SelectCCMask)
7637 int SelectCCValidVal = SelectCCValid->getZExtValue();
7638 int SelectCCMaskVal = SelectCCMask->getZExtValue();
7640 auto *
TrueVal = dyn_cast<ConstantSDNode>(
Select->getOperand(0));
7641 auto *
FalseVal = dyn_cast<ConstantSDNode>(
Select->getOperand(1));
7642 if (!TrueVal || !FalseVal)
7646 else if (
TrueVal->getZExtValue() == 0 &&
FalseVal->getZExtValue() == 1)
7647 SelectCCMaskVal ^= SelectCCValidVal;
7651 if (SelectCCValidVal & ~CCValidVal)
7653 if (SelectCCMaskVal != (CCMaskVal & SelectCCValidVal))
7656 return Select->getOperand(4);
7659SDValue SystemZTargetLowering::combineIntDIVREM(
7660 SDNode *
N, DAGCombinerInfo &DCI)
const {
7662 EVT VT =
N->getValueType(0);
7676SDValue SystemZTargetLowering::combineINTRINSIC(
7677 SDNode *
N, DAGCombinerInfo &DCI)
const {
7680 unsigned Id =
N->getConstantOperandVal(1);
7684 case Intrinsic::s390_vll:
7685 case Intrinsic::s390_vlrl:
7686 if (
auto *
C = dyn_cast<ConstantSDNode>(
N->getOperand(2)))
7687 if (
C->getZExtValue() >= 15)
7692 case Intrinsic::s390_vstl:
7693 case Intrinsic::s390_vstrl:
7694 if (
auto *
C = dyn_cast<ConstantSDNode>(
N->getOperand(3)))
7695 if (
C->getZExtValue() >= 15)
7706 return N->getOperand(0);
7712 switch(
N->getOpcode()) {
7737 case ISD::UREM:
return combineIntDIVREM(
N, DCI);
7749 EVT VT =
Op.getValueType();
7752 unsigned Opcode =
Op.getOpcode();
7754 unsigned Id =
Op.getConstantOperandVal(0);
7756 case Intrinsic::s390_vpksh:
7757 case Intrinsic::s390_vpksf:
7758 case Intrinsic::s390_vpksg:
7759 case Intrinsic::s390_vpkshs:
7760 case Intrinsic::s390_vpksfs:
7761 case Intrinsic::s390_vpksgs:
7762 case Intrinsic::s390_vpklsh:
7763 case Intrinsic::s390_vpklsf:
7764 case Intrinsic::s390_vpklsg:
7765 case Intrinsic::s390_vpklshs:
7766 case Intrinsic::s390_vpklsfs:
7767 case Intrinsic::s390_vpklsgs:
7769 SrcDemE = DemandedElts;
7772 SrcDemE = SrcDemE.
trunc(NumElts / 2);
7775 case Intrinsic::s390_vuphb:
7776 case Intrinsic::s390_vuphh:
7777 case Intrinsic::s390_vuphf:
7778 case Intrinsic::s390_vuplhb:
7779 case Intrinsic::s390_vuplhh:
7780 case Intrinsic::s390_vuplhf:
7781 SrcDemE =
APInt(NumElts * 2, 0);
7784 case Intrinsic::s390_vuplb:
7785 case Intrinsic::s390_vuplhw:
7786 case Intrinsic::s390_vuplf:
7787 case Intrinsic::s390_vupllb:
7788 case Intrinsic::s390_vupllh:
7789 case Intrinsic::s390_vupllf:
7790 SrcDemE =
APInt(NumElts * 2, 0);
7793 case Intrinsic::s390_vpdi: {
7795 SrcDemE =
APInt(NumElts, 0);
7796 if (!DemandedElts[OpNo - 1])
7798 unsigned Mask =
Op.getConstantOperandVal(3);
7799 unsigned MaskBit = ((OpNo - 1) ? 1 : 4);
7801 SrcDemE.
setBit((Mask & MaskBit)? 1 : 0);
7804 case Intrinsic::s390_vsldb: {
7806 assert(VT == MVT::v16i8 &&
"Unexpected type.");
7807 unsigned FirstIdx =
Op.getConstantOperandVal(3);
7808 assert (FirstIdx > 0 && FirstIdx < 16 &&
"Unused operand.");
7809 unsigned NumSrc0Els = 16 - FirstIdx;
7810 SrcDemE =
APInt(NumElts, 0);
7812 APInt DemEls = DemandedElts.
trunc(NumSrc0Els);
7815 APInt DemEls = DemandedElts.
lshr(NumSrc0Els);
7820 case Intrinsic::s390_vperm:
7821 SrcDemE =
APInt(NumElts, -1);
7831 SrcDemE =
APInt(1, 1);
7834 SrcDemE = DemandedElts;
7845 const APInt &DemandedElts,
7860 const APInt &DemandedElts,
7862 unsigned Depth)
const {
7866 unsigned tmp0, tmp1;
7871 EVT VT =
Op.getValueType();
7872 if (
Op.getResNo() != 0 || VT == MVT::Untyped)
7875 "KnownBits does not match VT in bitwidth");
7878 "DemandedElts does not match VT number of elements");
7880 unsigned Opcode =
Op.getOpcode();
7882 bool IsLogical =
false;
7883 unsigned Id =
Op.getConstantOperandVal(0);
7885 case Intrinsic::s390_vpksh:
7886 case Intrinsic::s390_vpksf:
7887 case Intrinsic::s390_vpksg:
7888 case Intrinsic::s390_vpkshs:
7889 case Intrinsic::s390_vpksfs:
7890 case Intrinsic::s390_vpksgs:
7891 case Intrinsic::s390_vpklsh:
7892 case Intrinsic::s390_vpklsf:
7893 case Intrinsic::s390_vpklsg:
7894 case Intrinsic::s390_vpklshs:
7895 case Intrinsic::s390_vpklsfs:
7896 case Intrinsic::s390_vpklsgs:
7897 case Intrinsic::s390_vpdi:
7898 case Intrinsic::s390_vsldb:
7899 case Intrinsic::s390_vperm:
7902 case Intrinsic::s390_vuplhb:
7903 case Intrinsic::s390_vuplhh:
7904 case Intrinsic::s390_vuplhf:
7905 case Intrinsic::s390_vupllb:
7906 case Intrinsic::s390_vupllh:
7907 case Intrinsic::s390_vupllf:
7910 case Intrinsic::s390_vuphb:
7911 case Intrinsic::s390_vuphh:
7912 case Intrinsic::s390_vuphf:
7913 case Intrinsic::s390_vuplb:
7914 case Intrinsic::s390_vuplhw:
7915 case Intrinsic::s390_vuplf: {
7957 if (
LHS == 1)
return 1;
7960 if (
RHS == 1)
return 1;
7961 unsigned Common = std::min(
LHS,
RHS);
7962 unsigned SrcBitWidth =
Op.getOperand(OpNo).getScalarValueSizeInBits();
7963 EVT VT =
Op.getValueType();
7965 if (SrcBitWidth > VTBits) {
7966 unsigned SrcExtraBits = SrcBitWidth - VTBits;
7967 if (Common > SrcExtraBits)
7968 return (Common - SrcExtraBits);
7971 assert (SrcBitWidth == VTBits &&
"Expected operands of same bitwidth.");
7978 unsigned Depth)
const {
7979 if (
Op.getResNo() != 0)
7981 unsigned Opcode =
Op.getOpcode();
7983 unsigned Id =
Op.getConstantOperandVal(0);
7985 case Intrinsic::s390_vpksh:
7986 case Intrinsic::s390_vpksf:
7987 case Intrinsic::s390_vpksg:
7988 case Intrinsic::s390_vpkshs:
7989 case Intrinsic::s390_vpksfs:
7990 case Intrinsic::s390_vpksgs:
7991 case Intrinsic::s390_vpklsh:
7992 case Intrinsic::s390_vpklsf:
7993 case Intrinsic::s390_vpklsg:
7994 case Intrinsic::s390_vpklshs:
7995 case Intrinsic::s390_vpklsfs:
7996 case Intrinsic::s390_vpklsgs:
7997 case Intrinsic::s390_vpdi:
7998 case Intrinsic::s390_vsldb:
7999 case Intrinsic::s390_vperm:
8001 case Intrinsic::s390_vuphb:
8002 case Intrinsic::s390_vuphh:
8003 case Intrinsic::s390_vuphf:
8004 case Intrinsic::s390_vuplb:
8005 case Intrinsic::s390_vuplhw:
8006 case Intrinsic::s390_vuplf: {
8010 EVT VT =
Op.getValueType();
8034 switch (
Op->getOpcode()) {
8047 "Unexpected stack alignment");
8050 unsigned StackProbeSize =
8053 StackProbeSize &= ~(StackAlign - 1);
8054 return StackProbeSize ? StackProbeSize : StackAlign;
8071 Register Reg =
MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
8077 Register Reg =
MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
8103 if (Succ->isLiveIn(SystemZ::CC))
8114 switch (
MI.getOpcode()) {
8115 case SystemZ::Select32:
8116 case SystemZ::Select64:
8117 case SystemZ::Select128:
8118 case SystemZ::SelectF32:
8119 case SystemZ::SelectF64:
8120 case SystemZ::SelectF128:
8121 case SystemZ::SelectVR32:
8122 case SystemZ::SelectVR64:
8123 case SystemZ::SelectVR128:
8155 for (
auto *
MI : Selects) {
8156 Register DestReg =
MI->getOperand(0).getReg();
8157 Register TrueReg =
MI->getOperand(1).getReg();
8158 Register FalseReg =
MI->getOperand(2).getReg();
8163 if (
MI->getOperand(4).getImm() == (CCValid ^ CCMask))
8166 if (RegRewriteTable.
contains(TrueReg))
8167 TrueReg = RegRewriteTable[TrueReg].first;
8169 if (RegRewriteTable.
contains(FalseReg))
8170 FalseReg = RegRewriteTable[FalseReg].second;
8173 BuildMI(*SinkMBB, SinkInsertionPoint,
DL,
TII->get(SystemZ::PHI), DestReg)
8178 RegRewriteTable[DestReg] = std::make_pair(TrueReg, FalseReg);
8190 assert(TFL->hasReservedCallFrame(MF) &&
8191 "ADJSTACKDOWN and ADJSTACKUP should be no-ops");
8196 uint32_t NumBytes =
MI.getOperand(0).getImm();
8201 MI.eraseFromParent();
8212 unsigned CCValid =
MI.getOperand(3).getImm();
8213 unsigned CCMask =
MI.getOperand(4).getImm();
8225 assert(NextMI.getOperand(3).getImm() == CCValid &&
8226 "Bad CCValid operands since CC was not redefined.");
8227 if (NextMI.getOperand(4).getImm() == CCMask ||
8228 NextMI.getOperand(4).getImm() == (CCValid ^ CCMask)) {
8234 if (NextMI.definesRegister(SystemZ::CC) || NextMI.usesCustomInsertionHook())
8237 for (
auto *SelMI : Selects)
8238 if (NextMI.readsVirtualRegister(SelMI->getOperand(0).getReg())) {
8242 if (NextMI.isDebugInstr()) {
8244 assert(NextMI.isDebugValue() &&
"Unhandled debug opcode.");
8247 }
else if (
User || ++Count > 20)
8284 for (
auto *SelMI : Selects)
8285 SelMI->eraseFromParent();
8288 for (
auto *DbgMI : DbgValues)
8289 MBB->
splice(InsertPos, StartMBB, DbgMI);
8300 unsigned StoreOpcode,
8301 unsigned STOCOpcode,
8302 bool Invert)
const {
8307 int64_t Disp =
MI.getOperand(2).getImm();
8308 Register IndexReg =
MI.getOperand(3).getReg();
8309 unsigned CCValid =
MI.getOperand(4).getImm();
8310 unsigned CCMask =
MI.getOperand(5).getImm();
8313 StoreOpcode =
TII->getOpcodeForOffset(StoreOpcode, Disp);
8318 for (
auto *
I :
MI.memoperands())
8327 if (STOCOpcode && !IndexReg && Subtarget.hasLoadStoreOnCond()) {
8339 MI.eraseFromParent();
8379 MI.eraseFromParent();
8415 int HiOpcode =
Unsigned? SystemZ::VECLG : SystemZ::VECG;
8434 Register Temp =
MRI.createVirtualRegister(&SystemZ::VR128BitRegClass);
8442 MI.eraseFromParent();
8453 bool Invert)
const {
8462 int64_t Disp =
MI.getOperand(2).getImm();
8464 Register BitShift =
MI.getOperand(4).getReg();
8465 Register NegBitShift =
MI.getOperand(5).getReg();
8466 unsigned BitSize =
MI.getOperand(6).getImm();
8470 unsigned LOpcode =
TII->getOpcodeForOffset(SystemZ::L, Disp);
8471 unsigned CSOpcode =
TII->getOpcodeForOffset(SystemZ::CS, Disp);
8472 assert(LOpcode && CSOpcode &&
"Displacement out of range");
8475 Register OrigVal =
MRI.createVirtualRegister(&SystemZ::GR32BitRegClass);
8476 Register OldVal =
MRI.createVirtualRegister(&SystemZ::GR32BitRegClass);
8477 Register NewVal =
MRI.createVirtualRegister(&SystemZ::GR32BitRegClass);
8478 Register RotatedOldVal =
MRI.createVirtualRegister(&SystemZ::GR32BitRegClass);
8479 Register RotatedNewVal =
MRI.createVirtualRegister(&SystemZ::GR32BitRegClass);
8510 Register Tmp =
MRI.createVirtualRegister(&SystemZ::GR32BitRegClass);
8515 }
else if (BinOpcode)
8538 MI.eraseFromParent();
8549 unsigned KeepOldMask)
const {
8557 int64_t Disp =
MI.getOperand(2).getImm();
8559 Register BitShift =
MI.getOperand(4).getReg();
8560 Register NegBitShift =
MI.getOperand(5).getReg();
8561 unsigned BitSize =
MI.getOperand(6).getImm();
8565 unsigned LOpcode =
TII->getOpcodeForOffset(SystemZ::L, Disp);
8566 unsigned CSOpcode =
TII->getOpcodeForOffset(SystemZ::CS, Disp);
8567 assert(LOpcode && CSOpcode &&
"Displacement out of range");
8570 Register OrigVal =
MRI.createVirtualRegister(&SystemZ::GR32BitRegClass);
8571 Register OldVal =
MRI.createVirtualRegister(&SystemZ::GR32BitRegClass);
8572 Register NewVal =
MRI.createVirtualRegister(&SystemZ::GR32BitRegClass);
8573 Register RotatedOldVal =
MRI.createVirtualRegister(&SystemZ::GR32BitRegClass);
8574 Register RotatedAltVal =
MRI.createVirtualRegister(&SystemZ::GR32BitRegClass);
8575 Register RotatedNewVal =
MRI.createVirtualRegister(&SystemZ::GR32BitRegClass);
8642 MI.eraseFromParent();
8658 int64_t Disp =
MI.getOperand(2).getImm();
8660 Register OrigSwapVal =
MI.getOperand(4).getReg();
8661 Register BitShift =
MI.getOperand(5).getReg();
8662 Register NegBitShift =
MI.getOperand(6).getReg();
8663 int64_t BitSize =
MI.getOperand(7).getImm();
8669 unsigned LOpcode =
TII->getOpcodeForOffset(SystemZ::L, Disp);
8670 unsigned CSOpcode =
TII->getOpcodeForOffset(SystemZ::CS, Disp);
8671 unsigned ZExtOpcode = BitSize == 8 ? SystemZ::LLCR : SystemZ::LLHR;
8672 assert(LOpcode && CSOpcode &&
"Displacement out of range");
8675 Register OrigOldVal =
MRI.createVirtualRegister(RC);
8678 Register StoreVal =
MRI.createVirtualRegister(RC);
8679 Register OldValRot =
MRI.createVirtualRegister(RC);
8680 Register RetryOldVal =
MRI.createVirtualRegister(RC);
8681 Register RetrySwapVal =
MRI.createVirtualRegister(RC);
8756 if (!
MI.registerDefIsDead(SystemZ::CC))
8759 MI.eraseFromParent();
8775 Register Tmp1 =
MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
8776 Register Tmp2 =
MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
8784 MI.eraseFromParent();
8793 bool ClearEven)
const {
8801 Register In128 =
MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
8805 Register NewIn128 =
MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
8806 Register Zero64 =
MRI.createVirtualRegister(&SystemZ::GR64BitRegClass);
8817 MI.eraseFromParent();
8824 unsigned Opcode,
bool IsMemset)
const {
8831 uint64_t DestDisp =
MI.getOperand(1).getImm();
8837 if (!isUInt<12>(Disp)) {
8838 Register Reg =
MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
8839 unsigned Opcode =
TII->getOpcodeForOffset(SystemZ::LA, Disp);
8849 SrcDisp =
MI.getOperand(3).getImm();
8852 SrcDisp = DestDisp++;
8853 foldDisplIfNeeded(DestBase, DestDisp);
8857 bool IsImmForm = LengthMO.
isImm();
8858 bool IsRegForm = !IsImmForm;
8865 unsigned Length) ->
void {
8884 bool NeedsLoop =
false;
8886 Register LenAdjReg = SystemZ::NoRegister;
8888 ImmLength = LengthMO.
getImm();
8889 ImmLength += IsMemset ? 2 : 1;
8890 if (ImmLength == 0) {
8891 MI.eraseFromParent();
8894 if (Opcode == SystemZ::CLC) {
8895 if (ImmLength > 3 * 256)
8905 }
else if (ImmLength > 6 * 256)
8913 LenAdjReg = LengthMO.
getReg();
8919 (Opcode == SystemZ::CLC && (ImmLength > 256 || NeedsLoop)
8925 MRI.createVirtualRegister(&SystemZ::GR64BitRegClass);
8927 TII->loadImmediate(*
MBB,
MI, StartCountReg, ImmLength / 256);
8938 Register Reg =
MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
8942 if (DestBase.
isReg() && DestBase.
getReg() == SystemZ::NoRegister)
8943 DestBase = loadZeroAddress();
8944 if (SrcBase.
isReg() && SrcBase.
getReg() == SystemZ::NoRegister)
8945 SrcBase = HaveSingleBase ? DestBase : loadZeroAddress();
8955 (HaveSingleBase ? StartSrcReg :
forceReg(
MI, DestBase,
TII));
8958 Register ThisSrcReg =
MRI.createVirtualRegister(RC);
8960 (HaveSingleBase ? ThisSrcReg :
MRI.createVirtualRegister(RC));
8961 Register NextSrcReg =
MRI.createVirtualRegister(RC);
8963 (HaveSingleBase ? NextSrcReg :
MRI.createVirtualRegister(RC));
8964 RC = &SystemZ::GR64BitRegClass;
8965 Register ThisCountReg =
MRI.createVirtualRegister(RC);
8966 Register NextCountReg =
MRI.createVirtualRegister(RC);
8992 MBB = MemsetOneCheckMBB;
9035 if (EndMBB && !ImmLength)
9057 if (!HaveSingleBase)
9064 if (Opcode == SystemZ::MVC)
9091 if (!HaveSingleBase)
9113 Register RemSrcReg =
MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
9114 Register RemDestReg = HaveSingleBase ? RemSrcReg
9115 :
MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
9119 if (!HaveSingleBase)
9135 if (Opcode != SystemZ::MVC) {
9145 while (ImmLength > 0) {
9149 foldDisplIfNeeded(DestBase, DestDisp);
9150 foldDisplIfNeeded(SrcBase, SrcDisp);
9151 insertMemMemOp(
MBB,
MI, DestBase, DestDisp, SrcBase, SrcDisp, ThisLength);
9152 DestDisp += ThisLength;
9153 SrcDisp += ThisLength;
9154 ImmLength -= ThisLength;
9157 if (EndMBB && ImmLength > 0) {
9173 MI.eraseFromParent();
9186 uint64_t End1Reg =
MI.getOperand(0).getReg();
9187 uint64_t Start1Reg =
MI.getOperand(1).getReg();
9188 uint64_t Start2Reg =
MI.getOperand(2).getReg();
9189 uint64_t CharReg =
MI.getOperand(3).getReg();
9192 uint64_t This1Reg =
MRI.createVirtualRegister(RC);
9193 uint64_t This2Reg =
MRI.createVirtualRegister(RC);
9232 MI.eraseFromParent();
9239 bool NoFloat)
const {
9245 MI.setDesc(
TII->get(Opcode));
9249 uint64_t Control =
MI.getOperand(2).getImm();
9250 static const unsigned GPRControlBit[16] = {
9251 0x8000, 0x8000, 0x4000, 0x4000, 0x2000, 0x2000, 0x1000, 0x1000,
9252 0x0800, 0x0800, 0x0400, 0x0400, 0x0200, 0x0200, 0x0100, 0x0100
9254 Control |= GPRControlBit[15];
9256 Control |= GPRControlBit[11];
9257 MI.getOperand(2).setImm(Control);
9260 for (
int I = 0;
I < 16;
I++) {
9261 if ((Control & GPRControlBit[
I]) == 0) {
9268 if (!NoFloat && (Control & 4) != 0) {
9269 if (Subtarget.hasVector()) {
9301 MI.eraseFromParent();
9314 Register SizeReg =
MI.getOperand(2).getReg();
9326 Register PHIReg =
MRI->createVirtualRegister(&SystemZ::ADDR64BitRegClass);
9327 Register IncReg =
MRI->createVirtualRegister(&SystemZ::ADDR64BitRegClass);
9392 MI.eraseFromParent();
9396SDValue SystemZTargetLowering::
9407 switch (
MI.getOpcode()) {
9408 case SystemZ::ADJCALLSTACKDOWN:
9409 case SystemZ::ADJCALLSTACKUP:
9410 return emitAdjCallStack(
MI,
MBB);
9412 case SystemZ::Select32:
9413 case SystemZ::Select64:
9414 case SystemZ::Select128:
9415 case SystemZ::SelectF32:
9416 case SystemZ::SelectF64:
9417 case SystemZ::SelectF128:
9418 case SystemZ::SelectVR32:
9419 case SystemZ::SelectVR64:
9420 case SystemZ::SelectVR128:
9421 return emitSelect(
MI,
MBB);
9423 case SystemZ::CondStore8Mux:
9424 return emitCondStore(
MI,
MBB, SystemZ::STCMux, 0,
false);
9425 case SystemZ::CondStore8MuxInv:
9426 return emitCondStore(
MI,
MBB, SystemZ::STCMux, 0,
true);
9427 case SystemZ::CondStore16Mux:
9428 return emitCondStore(
MI,
MBB, SystemZ::STHMux, 0,
false);
9429 case SystemZ::CondStore16MuxInv:
9430 return emitCondStore(
MI,
MBB, SystemZ::STHMux, 0,
true);
9431 case SystemZ::CondStore32Mux:
9432 return emitCondStore(
MI,
MBB, SystemZ::STMux, SystemZ::STOCMux,
false);
9433 case SystemZ::CondStore32MuxInv:
9434 return emitCondStore(
MI,
MBB, SystemZ::STMux, SystemZ::STOCMux,
true);
9435 case SystemZ::CondStore8:
9436 return emitCondStore(
MI,
MBB, SystemZ::STC, 0,
false);
9437 case SystemZ::CondStore8Inv:
9438 return emitCondStore(
MI,
MBB, SystemZ::STC, 0,
true);
9439 case SystemZ::CondStore16:
9440 return emitCondStore(
MI,
MBB, SystemZ::STH, 0,
false);
9441 case SystemZ::CondStore16Inv:
9442 return emitCondStore(
MI,
MBB, SystemZ::STH, 0,
true);
9443 case SystemZ::CondStore32:
9444 return emitCondStore(
MI,
MBB, SystemZ::ST, SystemZ::STOC,
false);
9445 case SystemZ::CondStore32Inv:
9446 return emitCondStore(
MI,
MBB, SystemZ::ST, SystemZ::STOC,
true);
9447 case SystemZ::CondStore64:
9448 return emitCondStore(
MI,
MBB, SystemZ::STG, SystemZ::STOCG,
false);
9449 case SystemZ::CondStore64Inv:
9450 return emitCondStore(
MI,
MBB, SystemZ::STG, SystemZ::STOCG,
true);
9451 case SystemZ::CondStoreF32:
9452 return emitCondStore(
MI,
MBB, SystemZ::STE, 0,
false);
9453 case SystemZ::CondStoreF32Inv:
9454 return emitCondStore(
MI,
MBB, SystemZ::STE, 0,
true);
9455 case SystemZ::CondStoreF64:
9456 return emitCondStore(
MI,
MBB, SystemZ::STD, 0,
false);
9457 case SystemZ::CondStoreF64Inv:
9458 return emitCondStore(
MI,
MBB, SystemZ::STD, 0,
true);
9460 case SystemZ::SCmp128Hi:
9461 return emitICmp128Hi(
MI,
MBB,
false);
9462 case SystemZ::UCmp128Hi:
9463 return emitICmp128Hi(
MI,
MBB,
true);
9465 case SystemZ::PAIR128:
9466 return emitPair128(
MI,
MBB);
9467 case SystemZ::AEXT128:
9468 return emitExt128(
MI,
MBB,
false);
9469 case SystemZ::ZEXT128:
9470 return emitExt128(
MI,
MBB,
true);
9472 case SystemZ::ATOMIC_SWAPW:
9473 return emitAtomicLoadBinary(
MI,
MBB, 0);
9475 case SystemZ::ATOMIC_LOADW_AR:
9476 return emitAtomicLoadBinary(
MI,
MBB, SystemZ::AR);
9477 case SystemZ::ATOMIC_LOADW_AFI:
9478 return emitAtomicLoadBinary(
MI,
MBB, SystemZ::AFI);
9480 case SystemZ::ATOMIC_LOADW_SR:
9481 return emitAtomicLoadBinary(
MI,
MBB, SystemZ::SR);
9483 case SystemZ::ATOMIC_LOADW_NR:
9484 return emitAtomicLoadBinary(
MI,
MBB, SystemZ::NR);
9485 case SystemZ::ATOMIC_LOADW_NILH:
9486 return emitAtomicLoadBinary(
MI,
MBB, SystemZ::NILH);
9488 case SystemZ::ATOMIC_LOADW_OR:
9489 return emitAtomicLoadBinary(
MI,
MBB, SystemZ::OR);
9490 case SystemZ::ATOMIC_LOADW_OILH:
9491 return emitAtomicLoadBinary(
MI,
MBB, SystemZ::OILH);
9493 case SystemZ::ATOMIC_LOADW_XR:
9494 return emitAtomicLoadBinary(
MI,
MBB, SystemZ::XR);
9495 case SystemZ::ATOMIC_LOADW_XILF:
9496 return emitAtomicLoadBinary(
MI,
MBB, SystemZ::XILF);
9498 case SystemZ::ATOMIC_LOADW_NRi:
9499 return emitAtomicLoadBinary(
MI,
MBB, SystemZ::NR,
true);
9500 case SystemZ::ATOMIC_LOADW_NILHi:
9501 return emitAtomicLoadBinary(
MI,
MBB, SystemZ::NILH,
true);
9503 case SystemZ::ATOMIC_LOADW_MIN:
9505 case SystemZ::ATOMIC_LOADW_MAX:
9507 case SystemZ::ATOMIC_LOADW_UMIN:
9509 case SystemZ::ATOMIC_LOADW_UMAX:
9512 case SystemZ::ATOMIC_CMP_SWAPW:
9513 return emitAtomicCmpSwapW(
MI,
MBB);
9514 case SystemZ::MVCImm:
9515 case SystemZ::MVCReg:
9516 return emitMemMemWrapper(
MI,
MBB, SystemZ::MVC);
9517 case SystemZ::NCImm:
9518 return emitMemMemWrapper(
MI,
MBB, SystemZ::NC);
9519 case SystemZ::OCImm:
9520 return emitMemMemWrapper(
MI,
MBB, SystemZ::OC);
9521 case SystemZ::XCImm:
9522 case SystemZ::XCReg:
9523 return emitMemMemWrapper(
MI,
MBB, SystemZ::XC);
9524 case SystemZ::CLCImm:
9525 case SystemZ::CLCReg:
9526 return emitMemMemWrapper(
MI,
MBB, SystemZ::CLC);
9527 case SystemZ::MemsetImmImm:
9528 case SystemZ::MemsetImmReg:
9529 case SystemZ::MemsetRegImm:
9530 case SystemZ::MemsetRegReg:
9531 return emitMemMemWrapper(
MI,
MBB, SystemZ::MVC,
true);
9532 case SystemZ::CLSTLoop:
9533 return emitStringWrapper(
MI,
MBB, SystemZ::CLST);
9534 case SystemZ::MVSTLoop:
9535 return emitStringWrapper(
MI,
MBB, SystemZ::MVST);
9536 case SystemZ::SRSTLoop:
9537 return emitStringWrapper(
MI,
MBB, SystemZ::SRST);
9538 case SystemZ::TBEGIN:
9539 return emitTransactionBegin(
MI,
MBB, SystemZ::TBEGIN,
false);
9540 case SystemZ::TBEGIN_nofloat:
9541 return emitTransactionBegin(
MI,
MBB, SystemZ::TBEGIN,
true);
9542 case SystemZ::TBEGINC:
9543 return emitTransactionBegin(
MI,
MBB, SystemZ::TBEGINC,
true);
9544 case SystemZ::LTEBRCompare_Pseudo:
9545 return emitLoadAndTestCmp0(
MI,
MBB, SystemZ::LTEBR);
9546 case SystemZ::LTDBRCompare_Pseudo:
9547 return emitLoadAndTestCmp0(
MI,
MBB, SystemZ::LTDBR);
9548 case SystemZ::LTXBRCompare_Pseudo:
9549 return emitLoadAndTestCmp0(
MI,
MBB, SystemZ::LTXBR);
9551 case SystemZ::PROBED_ALLOCA:
9552 return emitProbedAlloca(
MI,
MBB);
9554 case TargetOpcode::STACKMAP:
9555 case TargetOpcode::PATCHPOINT:
9566SystemZTargetLowering::getRepRegClassFor(
MVT VT)
const {
9567 if (VT == MVT::Untyped)
9568 return &SystemZ::ADDR128BitRegClass;
9594 DAG.
getMachineNode(SystemZ::EFPC, dl, {MVT::i32, MVT::Other}, Chain), 0);
9614 EVT VT =
Op.getValueType();
9615 Op =
Op.getOperand(0);
9616 EVT OpVT =
Op.getValueType();
9618 assert(OpVT.
isVector() &&
"Operand type for VECREDUCE_ADD is not a vector.");
unsigned const MachineRegisterInfo * MRI
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
amdgpu AMDGPU Register Bank Select
static bool isZeroVector(SDValue N)
Function Alias Analysis Results
BlockVerifier::State From
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static SDValue convertValVTToLocVT(SelectionDAG &DAG, SDValue Val, const CCValAssign &VA, const SDLoc &DL)
static SDValue convertLocVTToValVT(SelectionDAG &DAG, SDValue Val, const CCValAssign &VA, const SDLoc &DL)
#define LLVM_FALLTHROUGH
LLVM_FALLTHROUGH - Mark fallthrough cases in switch statements.
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
const HexagonInstrInfo * TII
static bool isUndef(ArrayRef< int > Mask)
iv Induction Variable Users
unsigned const TargetRegisterInfo * TRI
const char LLVMTargetMachineRef TM
static bool isSelectPseudo(MachineInstr &MI)
const SmallVectorImpl< MachineOperand > & Cond
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static void adjustForTestUnderMask(SelectionDAG &DAG, const SDLoc &DL, Comparison &C)
static void adjustForLTGFR(Comparison &C)
static void adjustSubwordCmp(SelectionDAG &DAG, const SDLoc &DL, Comparison &C)
static SDValue joinDwords(SelectionDAG &DAG, const SDLoc &DL, SDValue Op0, SDValue Op1)
static bool isOnlyUsedByStores(SDValue StoredVal, SelectionDAG &DAG)
static void lowerGR128Binary(SelectionDAG &DAG, const SDLoc &DL, EVT VT, unsigned Opcode, SDValue Op0, SDValue Op1, SDValue &Even, SDValue &Odd)
static void adjustForRedundantAnd(SelectionDAG &DAG, const SDLoc &DL, Comparison &C)
static SDValue buildScalarToVector(SelectionDAG &DAG, const SDLoc &DL, EVT VT, SDValue Value)
static SDValue lowerI128ToGR128(SelectionDAG &DAG, SDValue In)
static bool isSimpleShift(SDValue N, unsigned &ShiftVal)
static bool chooseShuffleOpNos(int *OpNos, unsigned &OpNo0, unsigned &OpNo1)
static uint32_t findZeroVectorIdx(SDValue *Ops, unsigned Num)
static bool isVectorElementSwap(ArrayRef< int > M, EVT VT)
static void getCSAddressAndShifts(SDValue Addr, SelectionDAG &DAG, SDLoc DL, SDValue &AlignedAddr, SDValue &BitShift, SDValue &NegBitShift)
static bool isShlDoublePermute(const SmallVectorImpl< int > &Bytes, unsigned &StartIndex, unsigned &OpNo0, unsigned &OpNo1)
static SDValue getPermuteNode(SelectionDAG &DAG, const SDLoc &DL, const Permute &P, SDValue Op0, SDValue Op1)
static SDNode * emitIntrinsicWithCCAndChain(SelectionDAG &DAG, SDValue Op, unsigned Opcode)
static SDValue getCCResult(SelectionDAG &DAG, SDValue CCReg)
static bool isIntrinsicWithCCAndChain(SDValue Op, unsigned &Opcode, unsigned &CCValid)
static void lowerMUL_LOHI32(SelectionDAG &DAG, const SDLoc &DL, unsigned Extend, SDValue Op0, SDValue Op1, SDValue &Hi, SDValue &Lo)
static void createPHIsForSelects(SmallVector< MachineInstr *, 8 > &Selects, MachineBasicBlock *TrueMBB, MachineBasicBlock *FalseMBB, MachineBasicBlock *SinkMBB)
static SDValue getGeneralPermuteNode(SelectionDAG &DAG, const SDLoc &DL, SDValue *Ops, const SmallVectorImpl< int > &Bytes)
static unsigned getVectorComparisonOrInvert(ISD::CondCode CC, CmpMode Mode, bool &Invert)
static unsigned CCMaskForCondCode(ISD::CondCode CC)
static void adjustICmpTruncate(SelectionDAG &DAG, const SDLoc &DL, Comparison &C)
static void adjustForFNeg(Comparison &C)
static bool isScalarToVector(SDValue Op)
static SDValue emitSETCC(SelectionDAG &DAG, const SDLoc &DL, SDValue CCReg, unsigned CCValid, unsigned CCMask)
static bool matchPermute(const SmallVectorImpl< int > &Bytes, const Permute &P, unsigned &OpNo0, unsigned &OpNo1)
static bool isAddCarryChain(SDValue Carry)
static SDValue emitCmp(SelectionDAG &DAG, const SDLoc &DL, Comparison &C)
static MachineOperand earlyUseOperand(MachineOperand Op)
static bool canUseSiblingCall(const CCState &ArgCCInfo, SmallVectorImpl< CCValAssign > &ArgLocs, SmallVectorImpl< ISD::OutputArg > &Outs)
static bool combineCCMask(SDValue &CCReg, int &CCValid, int &CCMask)
static bool getzOSCalleeAndADA(SelectionDAG &DAG, SDValue &Callee, SDValue &ADA, SDLoc &DL, SDValue &Chain)
static bool shouldSwapCmpOperands(const Comparison &C)
static bool isNaturalMemoryOperand(SDValue Op, unsigned ICmpType)
static SDValue getADAEntry(SelectionDAG &DAG, SDValue Val, SDLoc DL, unsigned Offset, bool LoadAdr=false)
static SDNode * emitIntrinsicWithCC(SelectionDAG &DAG, SDValue Op, unsigned Opcode)
static void adjustForSubtraction(SelectionDAG &DAG, const SDLoc &DL, Comparison &C)
static bool getVPermMask(SDValue ShuffleOp, SmallVectorImpl< int > &Bytes)
static const Permute PermuteForms[]
static bool isSubBorrowChain(SDValue Carry)
static void adjustICmp128(SelectionDAG &DAG, const SDLoc &DL, Comparison &C)
static APInt getDemandedSrcElements(SDValue Op, const APInt &DemandedElts, unsigned OpNo)
static SDValue getAbsolute(SelectionDAG &DAG, const SDLoc &DL, SDValue Op, bool IsNegative)
static unsigned computeNumSignBitsBinOp(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth, unsigned OpNo)
static SDValue tryBuildVectorShuffle(SelectionDAG &DAG, BuildVectorSDNode *BVN)
static bool isMovedFromParts(SDValue Val, SDValue &LoPart, SDValue &HiPart)
static unsigned getVectorComparison(ISD::CondCode CC, CmpMode Mode)
static SDValue lowerGR128ToI128(SelectionDAG &DAG, SDValue In)
static SDValue MergeInputChains(SDNode *N1, SDNode *N2)
static unsigned getTestUnderMaskCond(unsigned BitSize, unsigned CCMask, uint64_t Mask, uint64_t CmpVal, unsigned ICmpType)
static bool isIntrinsicWithCC(SDValue Op, unsigned &Opcode, unsigned &CCValid)
static SDValue expandV4F32ToV2F64(SelectionDAG &DAG, int Start, const SDLoc &DL, SDValue Op, SDValue Chain)
static Comparison getCmp(SelectionDAG &DAG, SDValue CmpOp0, SDValue CmpOp1, ISD::CondCode Cond, const SDLoc &DL, SDValue Chain=SDValue(), bool IsSignaling=false)
static bool checkCCKill(MachineInstr &MI, MachineBasicBlock *MBB)
static Register forceReg(MachineInstr &MI, MachineOperand &Base, const SystemZInstrInfo *TII)
static bool is32Bit(EVT VT)
static std::pair< unsigned, const TargetRegisterClass * > parseRegisterNumber(StringRef Constraint, const TargetRegisterClass *RC, const unsigned *Map, unsigned Size)
static bool matchDoublePermute(const SmallVectorImpl< int > &Bytes, const Permute &P, SmallVectorImpl< int > &Transform)
static Comparison getIntrinsicCmp(SelectionDAG &DAG, unsigned Opcode, SDValue Call, unsigned CCValid, uint64_t CC, ISD::CondCode Cond)
static bool isAbsolute(SDValue CmpOp, SDValue Pos, SDValue Neg)
static AddressingMode getLoadStoreAddrMode(bool HasVector, Type *Ty)
static SDValue buildMergeScalars(SelectionDAG &DAG, const SDLoc &DL, EVT VT, SDValue Op0, SDValue Op1)
static void computeKnownBitsBinOp(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth, unsigned OpNo)
static bool getShuffleInput(const SmallVectorImpl< int > &Bytes, unsigned Start, unsigned BytesPerElement, int &Base)
static AddressingMode supportedAddressingMode(Instruction *I, bool HasVector)
static void adjustZeroCmp(SelectionDAG &DAG, const SDLoc &DL, Comparison &C)
Class for arbitrary precision integers.
APInt zext(unsigned width) const
Zero extend to a new width.
uint64_t getZExtValue() const
Get zero extended value.
void setBitsFrom(unsigned loBit)
Set the top bits starting from loBit.
unsigned getActiveBits() const
Compute the number of active bits in the value.
APInt trunc(unsigned width) const
Truncate to new width.
void setBit(unsigned BitPosition)
Set the given bit to 1 whose position is given as "bitPosition".
static APInt getBitsSet(unsigned numBits, unsigned loBit, unsigned hiBit)
Get a value with a block of bits set.
unsigned getBitWidth() const
Return the number of bits in the APInt.
bool isSingleWord() const
Determine if this APInt just has one word to store value.
void insertBits(const APInt &SubBits, unsigned bitPosition)
Insert the bits from a smaller APInt starting at bitPosition.
bool isSubsetOf(const APInt &RHS) const
This operation checks that all bits set in this APInt are also set in RHS.
void lshrInPlace(unsigned ShiftAmt)
Logical right-shift this APInt by ShiftAmt in place.
APInt lshr(unsigned shiftAmt) const
Logical right-shift function.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
an instruction that atomically reads a memory location, combines it with another value,...
BinOp getOperation() const
StringRef getValueAsString() const
Return the attribute's value as a string.
The address of a basic block.
A "pseudo-class" with methods for operating on BUILD_VECTORs.
bool isConstantSplat(APInt &SplatValue, APInt &SplatUndef, unsigned &SplatBitSize, bool &HasAnyUndefs, unsigned MinSplatBits=0, bool isBigEndian=false) const
Check if this is a constant splat, and if so, find the smallest element size that splats the vector.
CCState - This class holds information needed while lowering arguments and return values.
void AnalyzeCallResult(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
AnalyzeCallResult - Analyze the return values of a call, incorporating info about the passed values i...
bool CheckReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
CheckReturn - Analyze the return values of a function, returning true if the return can be performed ...
void AnalyzeReturn(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
AnalyzeReturn - Analyze the returned values of a return, incorporating info about the result values i...
uint64_t getStackSize() const
Returns the size of the currently allocated portion of the stack.
CCValAssign - Represent assignment of one arg/retval to a location.
Register getLocReg() const
LocInfo getLocInfo() const
int64_t getLocMemOffset() const
This class represents a function call, abstracting a target machine's calling convention.
This is an important base class in LLVM.
This class represents an Operation in the Expression.
uint64_t getNumOperands() const
A parsed version of the target data layout string in and methods for querying it.
bool contains(const_arg_type_t< KeyT > Val) const
Return true if the specified key is in the map, false otherwise.
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
uint64_t getFnAttributeAsParsedInteger(StringRef Kind, uint64_t Default=0) const
For a string attribute Kind, parse attribute as an integer.
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
const GlobalObject * getAliaseeObject() const
bool hasPrivateLinkage() const
bool hasInternalLinkage() const
A wrapper class for inspecting calls to intrinsic functions.
This is an important class for using LLVM in a threaded context.
An instruction for reading from memory.
This class is used to represent ISD::LOAD nodes.
static auto integer_fixedlen_vector_valuetypes()
bool isVector() const
Return true if this is a vector value type.
static auto integer_valuetypes()
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
static auto fixedlen_vector_valuetypes()
static MVT getVectorVT(MVT VT, unsigned NumElements)
static MVT getIntegerVT(unsigned BitWidth)
static auto fp_valuetypes()
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
iterator getFirstNonPHI()
Returns a pointer to the first instruction in this block that is not a PHINode instruction.
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
iterator_range< succ_iterator > successors()
void splice(iterator Where, MachineBasicBlock *Other, iterator From)
Take an instruction from MBB 'Other' at the position From, and insert it into this MBB right before '...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
int CreateFixedObject(uint64_t Size, int64_t SPOffset, bool IsImmutable, bool isAliased=false)
Create a new object at a fixed location on the stack.
void setAdjustsStack(bool V)
void setFrameAddressIsTaken(bool T)
void setReturnAddressIsTaken(bool s)
unsigned getMaxCallFrameSize() const
Return the maximum size of a call frame that must be allocated for an outgoing function call.
void setMaxCallFrameSize(unsigned S)
MachineFunctionProperties & reset(Property P)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
reverse_iterator rbegin()
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
const DataLayout & getDataLayout() const
Return the DataLayout attached to the Module associated to this MF.
Function & getFunction()
Return the LLVM function that this machine code represents.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const MachineFunctionProperties & getProperties() const
Get the function properties.
Register addLiveIn(MCRegister PReg, const TargetRegisterClass *RC)
addLiveIn - Add the specified physical register as a live-in value and create a corresponding virtual...
const MachineInstrBuilder & setMemRefs(ArrayRef< MachineMemOperand * > MMOs) const
const MachineInstrBuilder & addImm(int64_t Val) const
Add a new immediate operand.
const MachineInstrBuilder & add(const MachineOperand &MO) const
const MachineInstrBuilder & addReg(Register RegNo, unsigned flags=0, unsigned SubReg=0) const
Add a new virtual register operand.
const MachineInstrBuilder & addMBB(MachineBasicBlock *MBB, unsigned TargetFlags=0) const
const MachineInstrBuilder & setMIFlags(unsigned Flags) const
const MachineInstrBuilder & addMemOperand(MachineMemOperand *MMO) const
Representation of each machine instruction.
bool killsRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr kills the specified register.
bool definesRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr fully defines the specified register.
bool readsRegister(Register Reg, const TargetRegisterInfo *TRI=nullptr) const
Return true if the MachineInstr reads the specified register.
const MachineOperand & getOperand(unsigned i) const
A description of a memory reference used in the backend.
Flags
Flags values. These may be or'd together.
@ MOVolatile
The memory access is volatile.
@ MODereferenceable
The memory access is dereferenceable (i.e., doesn't trap).
@ MOLoad
The memory access reads data.
@ MOInvariant
The memory access always returns the same value (or traps).
@ MOStore
The memory access writes data.
MachineOperand class - Representation of each machine instruction operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Register getReg() const
getReg - Returns the register number.
bool isIdenticalTo(const MachineOperand &Other) const
Returns true if this operand is identical to the specified operand except for liveness related flags ...
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Wrapper class representing virtual and physical registers.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
This class provides iterator support for SDUse operands that use a specific SDNode.
Represents one node in the SelectionDAG.
bool hasOneUse() const
Return true if there is exactly one use of this node.
iterator_range< use_iterator > uses()
SDNodeFlags getFlags() const
uint64_t getAsZExtVal() const
Helper method returns the zero-extended integer value of a ConstantSDNode.
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
const SDValue & getOperand(unsigned Num) const
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
bool hasNUsesOfValue(unsigned NUses, unsigned Value) const
Return true if there are exactly NUSES uses of the indicated value.
void setFlags(SDNodeFlags NewFlags)
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
SDNode * getNode() const
get the SDNode which holds the desired result
bool hasOneUse() const
Return true if there is exactly one node using value ResNo of Node.
SDValue getValue(unsigned R) const
EVT getValueType() const
Return the ValueType of the referenced return value.
TypeSize getValueSizeInBits() const
Returns the size of the value in bits.
const SDValue & getOperand(unsigned i) const
const APInt & getConstantOperandAPInt(unsigned i) const
uint64_t getScalarValueSizeInBits() const
unsigned getResNo() const
get the index which selects a specific result in the SDNode
uint64_t getConstantOperandVal(unsigned i) const
unsigned getOpcode() const
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned TargetFlags=0)
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s),...
SDValue getConstantPool(const Constant *C, EVT VT, MaybeAlign Align=std::nullopt, int Offs=0, bool isT=false, unsigned TargetFlags=0)
SDNode * isConstantIntBuildVectorOrConstantInt(SDValue N) const
Test whether the given value is a constant int or similar node.
SDValue UnrollVectorOp(SDNode *N, unsigned ResNE=0)
Utility function used by legalize and lowering to "unroll" a vector operation by splitting out the sc...
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
SDValue getGLOBAL_OFFSET_TABLE(EVT VT)
Return a GLOBAL_OFFSET_TABLE node. This does not have a useful SDLoc.
SDValue getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT, SDValue Chain, SDValue Ptr, SDValue Val, MachineMemOperand *MMO)
Gets a node for an atomic op, produces result (if relevant) and chain and takes 2 operands.
void addNoMergeSiteInfo(const SDNode *Node, bool NoMerge)
Set NoMergeSiteInfo to be associated with Node if NoMerge is true.
const TargetLowering & getTargetLoweringInfo() const
SDValue getTargetJumpTable(int JTI, EVT VT, unsigned TargetFlags=0)
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd).
SDValue getBuildVector(EVT VT, const SDLoc &DL, ArrayRef< SDValue > Ops)
Return an ISD::BUILD_VECTOR node.
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes(), AAResults *AA=nullptr)
bool isSplatValue(SDValue V, const APInt &DemandedElts, APInt &UndefElts, unsigned Depth=0) const
Test whether V has a splatted value for all the demanded elements.
SDValue getBitcast(EVT VT, SDValue V)
Return a bitcast using the SDLoc of the value operand, and casting to the provided type.
const DataLayout & getDataLayout() const
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
SDValue getMemBasePlusOffset(SDValue Base, TypeSize Offset, const SDLoc &DL, const SDNodeFlags Flags=SDNodeFlags())
Returns sum of the base pointer and offset.
SDValue getTruncStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, EVT SVT, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
SDValue getSplatVector(EVT VT, const SDLoc &DL, SDValue Op)
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
bool SignBitIsZero(SDValue Op, unsigned Depth=0) const
Return true if the sign bit of Op is known to be zero.
SDValue getRegister(unsigned Reg, EVT VT)
SDValue getTargetExtractSubreg(int SRIdx, const SDLoc &DL, EVT VT, SDValue Operand)
A convenience function for creating TargetInstrInfo::EXTRACT_SUBREG nodes.
SDValue getExternalSymbol(const char *Sym, EVT VT)
const TargetMachine & getTarget() const
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
SDValue getValueType(EVT)
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
unsigned ComputeNumSignBits(SDValue Op, unsigned Depth=0) const
Return the number of times the sign bit of the register is replicated into the other bits.
SDValue getTargetBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, unsigned TargetFlags=0)
void ReplaceAllUsesOfValueWith(SDValue From, SDValue To)
Replace any uses of From with To, leaving uses of other values produced by From.getNode() alone.
MachineFunction & getMachineFunction() const
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
SDValue getSplatBuildVector(EVT VT, const SDLoc &DL, SDValue Op)
Return a splat ISD::BUILD_VECTOR node, consisting of Op splatted to all elements.
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
KnownBits computeKnownBits(SDValue Op, unsigned Depth=0) const
Determine which bits of Op are known to be either zero or one and return them in Known.
SDValue getRegisterMask(const uint32_t *RegMask)
SDValue getZExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either zero-extending or trunca...
bool MaskedValueIsZero(SDValue Op, const APInt &Mask, unsigned Depth=0) const
Return true if 'Op & Mask' is known to be zero.
SDValue getObjectPtrOffset(const SDLoc &SL, SDValue Ptr, TypeSize Offset)
Create an add instruction with appropriate flags when used for addressing some offset of an object.
LLVMContext * getContext() const
SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef< SDValue > Ops, EVT MemVT, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags Flags=MachineMemOperand::MOLoad|MachineMemOperand::MOStore, LocationSize Size=0, const AAMDNodes &AAInfo=AAMDNodes())
Creates a MemIntrinsicNode that may produce a result and takes a list of operands.
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned TargetFlags=0)
SDValue CreateStackTemporary(TypeSize Bytes, Align Alignment)
Create a stack temporary based on the size in bytes and the alignment.
SDNode * UpdateNodeOperands(SDNode *N, SDValue Op)
Mutate the specified node in-place to have the specified operands.
SDValue getTargetConstantPool(const Constant *C, EVT VT, MaybeAlign Align=std::nullopt, int Offset=0, unsigned TargetFlags=0)
SDValue getTargetInsertSubreg(int SRIdx, const SDLoc &DL, EVT VT, SDValue Operand, SDValue Subreg)
A convenience function for creating TargetInstrInfo::INSERT_SUBREG nodes.
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
std::pair< SDValue, SDValue > SplitScalar(const SDValue &N, const SDLoc &DL, const EVT &LoVT, const EVT &HiVT)
Split the scalar node with EXTRACT_ELEMENT using the provided VTs and return the low/high part.
SDValue getVectorShuffle(EVT VT, const SDLoc &dl, SDValue N1, SDValue N2, ArrayRef< int > Mask)
Return an ISD::VECTOR_SHUFFLE node.
This SDNode is used to implement the code generator support for the llvm IR shufflevector instruction...
ArrayRef< int > getMask() const
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void reserve(size_type N)
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
An instruction for storing to memory.
This class is used to represent ISD::STORE nodes.
StringRef - Represent a constant reference to a string, i.e.
bool getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
bool starts_with(StringRef Prefix) const
Check if this string starts with the given Prefix.
StringRef slice(size_t Start, size_t End) const
Return a reference to the substring from [Start, End).
constexpr size_t size() const
size - Get the string size.
A switch()-like statement whose cases are string literals.
StringSwitch & Case(StringLiteral S, T Value)
void AnalyzeFormalArguments(const SmallVectorImpl< ISD::InputArg > &Ins, CCAssignFn Fn)
void AnalyzeCallOperands(const SmallVectorImpl< ISD::OutputArg > &Outs, CCAssignFn Fn)
A SystemZ-specific class detailing special use registers particular for calling conventions.
virtual int getStackPointerBias()=0
virtual int getCallFrameSize()=0
virtual int getStackPointerRegister()=0
A SystemZ-specific constant pool value.
static SystemZConstantPoolValue * Create(const GlobalValue *GV, SystemZCP::SystemZCPModifier Modifier)
unsigned getVarArgsFrameIndex() const
void setVarArgsFrameIndex(unsigned FI)
void setRegSaveFrameIndex(unsigned FI)
void incNumLocalDynamicTLSAccesses()
Register getVarArgsFirstGPR() const
void setADAVirtualRegister(Register Reg)
void setVarArgsFirstGPR(Register GPR)
Register getADAVirtualRegister() const
void setSizeOfFnParams(unsigned Size)
void setVarArgsFirstFPR(Register FPR)
unsigned getRegSaveFrameIndex() const
Register getVarArgsFirstFPR() const
const SystemZInstrInfo * getInstrInfo() const override
bool isPC32DBLSymbol(const GlobalValue *GV, CodeModel::Model CM) const
const TargetFrameLowering * getFrameLowering() const override
bool isTargetXPLINK64() const
SystemZCallingConventionRegisters * getSpecialRegisters() const
const SystemZRegisterInfo * getRegisterInfo() const override
Register getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const override
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override
This callback is invoked for operations that are unsupported by the target, which are registered to u...
EVT getOptimalMemOpType(const MemOp &Op, const AttributeList &FuncAttributes) const override
Returns the target specific optimal type for load and store operations as a result of memset,...
bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, LLVMContext &Context) const override
This hook should be implemented to check whether the return values described by the Outs array can fi...
bool hasInlineStackProbe(const MachineFunction &MF) const override
Returns true if stack probing through inline assembly is requested.
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const override
This method should be implemented by targets that mark instructions with the 'usesCustomInserter' fla...
AtomicExpansionKind shouldCastAtomicLoadInIR(LoadInst *LI) const override
Returns how the given (atomic) load should be cast by the IR-level AtomicExpand pass.
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &, EVT) const override
Return the ValueType of the result of SETCC operations.
bool allowTruncateForTailCall(Type *, Type *) const override
Return true if a truncation from FromTy to ToTy is permitted when deciding whether a call is in tail ...
SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl< ISD::OutputArg > &Outs, const SmallVectorImpl< SDValue > &OutVals, const SDLoc &DL, SelectionDAG &DAG) const override
This hook must be implemented to lower outgoing return values, described by the Outs array,...
bool findOptimalMemOpLowering(std::vector< EVT > &MemOps, unsigned Limit, const MemOp &Op, unsigned DstAS, unsigned SrcAS, const AttributeList &FuncAttributes) const override
Determines the optimal series of memory ops to replace the memset / memcpy.
bool useSoftFloat() const override
std::pair< SDValue, SDValue > makeExternalCall(SDValue Chain, SelectionDAG &DAG, const char *CalleeName, EVT RetVT, ArrayRef< SDValue > Ops, CallingConv::ID CallConv, bool IsSigned, SDLoc DL, bool DoesNotReturn, bool IsReturnValueUsed) const
bool mayBeEmittedAsTailCall(const CallInst *CI) const override
Return true if the target may be able emit the call instruction as a tail call.
bool splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, std::optional< CallingConv::ID > CC) const override
Target-specific splitting of values into parts that fit a register storing a legal type.
bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty, unsigned AS, Instruction *I=nullptr) const override
Return true if the addressing mode represented by AM is legal for this target, for a load/store of th...
SystemZTargetLowering(const TargetMachine &TM, const SystemZSubtarget &STI)
bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT VT) const override
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
bool isLegalICmpImmediate(int64_t Imm) const override
Return true if the specified immediate is legal icmp immediate, that is the target has icmp instructi...
std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override
Given a physical register constraint (e.g.
AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *RMW) const override
Returns how the IR-level AtomicExpand pass should expand the given AtomicRMW, if at all.
TargetLowering::ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override
Examine constraint string and operand type and determine a weight value.
bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, Align Alignment, MachineMemOperand::Flags Flags, unsigned *Fast) const override
Determine if the target supports unaligned memory accesses.
const MCPhysReg * getScratchRegisters(CallingConv::ID CC) const override
Returns a 0 terminated array of registers that can be safely used as scratch registers.
TargetLowering::ConstraintType getConstraintType(StringRef Constraint) const override
Given a constraint, return the type of constraint it is for this target.
bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override
Returns true if the target can instruction select the specified FP immediate natively.
Register getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
SDValue joinRegisterPartsIntoValue(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts, MVT PartVT, EVT ValueVT, std::optional< CallingConv::ID > CC) const override
Target-specific combining of register parts into its original value.
bool isTruncateFree(Type *, Type *) const override
Return true if it's free to truncate a value of type FromTy to type ToTy.
unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const override
Determine the number of bits in the operation that are sign bits.
void LowerOperationWrapper(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but leg...
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override
This method will be invoked for all target nodes and for any target-independent nodes that the target...
SDValue LowerCall(CallLoweringInfo &CLI, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower calls into the specified DAG.
bool isLegalAddImmediate(int64_t Imm) const override
Return true if the specified immediate is legal add immediate, that is the target has add instruction...
void ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override
This callback is invoked when a node result type is illegal for the target, and the operation was reg...
void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override
Lower the specified operand into the Ops vector.
const char * getTargetNodeName(unsigned Opcode) const override
This method returns the name of a target specific DAG node.
bool isGuaranteedNotToBeUndefOrPoisonForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, bool PoisonOnly, unsigned Depth) const override
Return true if this function can prove that Op is never poison and, if PoisonOnly is false,...
AtomicExpansionKind shouldCastAtomicStoreInIR(StoreInst *SI) const override
Returns how the given (atomic) store should be cast by the IR-level AtomicExpand pass into.
Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override
Return the register ID of the name passed in.
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl< ISD::InputArg > &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals) const override
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const override
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
unsigned getStackProbeSize(const MachineFunction &MF) const
XPLINK64 calling convention specific use registers Particular to z/OS when in 64 bit mode.
int getCallFrameSize() final
Information about stack frame layout on the target.
unsigned getStackAlignment() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
virtual bool hasFP(const MachineFunction &MF) const =0
hasFP - Return true if the specified function should have a dedicated frame pointer register.
TargetInstrInfo - Interface to description of machine instruction set.
void setBooleanVectorContents(BooleanContent Ty)
Specify how the target extends the result of a vector boolean value from a vector of i1 to a wider ty...
void setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)
Indicate that the specified operation does not work with the specified type and indicate what to do a...
virtual bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const
Returns true if arguments should be sign-extended in lib calls.
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
unsigned MaxStoresPerMemcpyOptSize
Likewise for functions with the OptSize attribute.
MachineBasicBlock * emitPatchPoint(MachineInstr &MI, MachineBasicBlock *MBB) const
Replace/modify any TargetFrameIndex operands with a targte-dependent sequence of memory operands that...
const TargetMachine & getTargetMachine() const
virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain targets require unusual breakdowns of certain types.
void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits)
Set the maximum atomic operation size supported by the backend.
void setAtomicLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Let target indicate that an extending atomic load of the specified type is legal.
Register getStackPointerRegisterToSaveRestore() const
If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save...
void setMinFunctionAlignment(Align Alignment)
Set the target's minimum function alignment.
unsigned MaxStoresPerMemsetOptSize
Likewise for functions with the OptSize attribute.
void setBooleanContents(BooleanContent Ty)
Specify how the target extends the result of integer and floating point boolean values from i1 to a w...
void computeRegisterProperties(const TargetRegisterInfo *TRI)
Once all of the register classes are added, this allows us to compute derived properties we expose.
void addRegisterClass(MVT VT, const TargetRegisterClass *RC)
Add the specified register class as an available regclass for the specified value type.
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
void setLibcallName(RTLIB::Libcall Call, const char *Name)
Rename the default libcall routine name for the specified libcall.
void setPrefFunctionAlignment(Align Alignment)
Set the target's preferred function alignment.
bool isOperationLegal(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target.
unsigned MaxStoresPerMemset
Specify maximum number of store instructions per memset call.
void setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified truncating store does not work with the specified type and indicate what ...
@ ZeroOrOneBooleanContent
@ ZeroOrNegativeOneBooleanContent
virtual const TargetRegisterClass * getRepRegClassFor(MVT VT) const
Return the 'representative' register class for the specified value type.
void setStackPointerRegisterToSaveRestore(Register R)
If set to a physical register, this specifies the register that llvm.savestack/llvm....
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
void setTargetDAGCombine(ArrayRef< ISD::NodeType > NTs)
Targets should invoke this method for each target independent node that they want to provide a custom...
void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, LegalizeAction Action)
Indicate that the specified load with extension does not work with the specified type and indicate wh...
std::vector< ArgListEntry > ArgListTy
unsigned MaxStoresPerMemcpy
Specify maximum number of store instructions per memcpy call.
virtual MVT getPointerMemTy(const DataLayout &DL, uint32_t AS=0) const
Return the in-memory pointer type for the given address space, defaults to the pointer type from the ...
void setSchedulingPreference(Sched::Preference Pref)
Specify the target scheduling preference.
LegalizeAction getOperationAction(unsigned Op, EVT VT) const
Return how this operation should be treated: either it is legal, needs to be promoted to a larger siz...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual bool findOptimalMemOpLowering(std::vector< EVT > &MemOps, unsigned Limit, const MemOp &Op, unsigned DstAS, unsigned SrcAS, const AttributeList &FuncAttributes) const
Determines the optimal series of memory ops to replace the memset / memcpy.
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
virtual SDValue LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA, SelectionDAG &DAG) const
Lower TLS global address SDNode for target independent emulated TLS model.
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
This function lowers an abstract call to a function into an actual call.
virtual ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const
Examine constraint string and operand type and determine a weight value.
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
bool verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const
virtual void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
Lower the specified operand into the Ops vector.
Primary interface to the complete machine description for the target machine.
TLSModel::Model getTLSModel(const GlobalValue *GV) const
Returns the TLS model which should be used for the given global variable.
bool useEmulatedTLS() const
Returns true if this target uses emulated TLS.
unsigned getPointerSize(unsigned AS) const
Get the pointer size for this target.
CodeModel::Model getCodeModel() const
Returns the code model.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetInstrInfo * getInstrInfo() const
static constexpr TypeSize getFixed(ScalarTy ExactSize)
The instances of the Type class are immutable: once they are created, they are never changed.
bool isVectorTy() const
True if this is an instance of VectorType.
bool isFP128Ty() const
Return true if this is 'fp128'.
unsigned getScalarSizeInBits() const LLVM_READONLY
If this is a vector type, return the getPrimitiveSizeInBits value for the element type.
bool isFloatingPointTy() const
Return true if this is one of the floating-point types.
bool isIntegerTy() const
True if this is an instance of IntegerType.
TypeSize getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
Value * getOperand(unsigned i) const
LLVM Value Representation.
Type * getType() const
All values are typed, get the type of this value.
bool hasOneUse() const
Return true if there is exactly one use of this value.
constexpr ScalarTy getFixedValue() const
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
@ GHC
Used by the Glasgow Haskell Compiler (GHC).
@ Fast
Attempts to make calls as fast as possible (e.g.
@ C
The default llvm calling convention, compatible with C.
bool isNON_EXTLoad(const SDNode *N)
Returns true if the specified node is a non-extending load.
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
@ MERGE_VALUES
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
@ STACKRESTORE
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain.
@ STACKSAVE
STACKSAVE - STACKSAVE has one operand, an input chain.
@ STRICT_FSETCC
STRICT_FSETCC/STRICT_FSETCCS - Constrained versions of SETCC, used for floating-point operands only.
@ SMUL_LOHI
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
@ BSWAP
Byte Swap and Counting operators.
@ VAEND
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE.
@ ATOMIC_STORE
OUTCHAIN = ATOMIC_STORE(INCHAIN, ptr, val) This corresponds to "store atomic" instruction.
@ ADD
Simple integer binary arithmetic operators.
@ LOAD
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
@ FMA
FMA - Perform a * b + c with no intermediate rounding step.
@ INTRINSIC_VOID
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
@ ATOMIC_CMP_SWAP_WITH_SUCCESS
Val, Success, OUTCHAIN = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) N.b.
@ SINT_TO_FP
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
@ FADD
Simple binary floating point operators.
@ ABS
ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth.
@ MEMBARRIER
MEMBARRIER - Compiler barrier only; generate a no-op.
@ ATOMIC_FENCE
OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) This corresponds to the fence instruction.
@ SIGN_EXTEND_VECTOR_INREG
SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register sign-extension of the low ...
@ SDIVREM
SDIVREM/UDIVREM - Divide two integers and produce both a quotient and remainder result.
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
@ BUILD_PAIR
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
@ STRICT_FSQRT
Constrained versions of libm-equivalent floating point intrinsics.
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
@ SIGN_EXTEND
Conversion operators.
@ SCALAR_TO_VECTOR
SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a scalar value into element 0 of the...
@ PREFETCH
PREFETCH - This corresponds to a prefetch intrinsic.
@ FSINCOS
FSINCOS - Compute both fsin and fcos as a single operation.
@ FNEG
Perform various unary floating-point operations inspired by libm.
@ BR_CC
BR_CC - Conditional branch.
@ SSUBO
Same for subtraction.
@ BR_JT
BR_JT - Jumptable branch.
@ IS_FPCLASS
Performs a check of floating point class property, defined by IEEE-754.
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
@ ATOMIC_LOAD
Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr) This corresponds to "load atomic" instruction.
@ UNDEF
UNDEF - An undefined node.
@ EXTRACT_ELEMENT
EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant,...
@ SPLAT_VECTOR
SPLAT_VECTOR(VAL) - Returns a vector with the scalar value VAL duplicated in all lanes.
@ VACOPY
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer,...
@ SADDO
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
@ VECREDUCE_ADD
Integer reductions may have a result type larger than the vector element type.
@ GET_ROUNDING
Returns current rounding mode: -1 Undefined 0 Round to 0 1 Round to nearest, ties to even 2 Round to ...
@ MULHU
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
@ SHL
Shift and rotation operations.
@ VECTOR_SHUFFLE
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
@ EXTRACT_VECTOR_ELT
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
@ FMINNUM
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
@ DYNAMIC_STACKALLOC
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary.
@ ANY_EXTEND_VECTOR_INREG
ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register any-extension of the low la...
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
@ FP_EXTEND
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
@ VSELECT
Select with a vector condition (op #0) and two vector operands (ops #1 and #2), returning a vector re...
@ UADDO_CARRY
Carry-using nodes for multiple precision addition and subtraction.
@ STRICT_SINT_TO_FP
STRICT_[US]INT_TO_FP - Convert a signed or unsigned integer to a floating point value.
@ FRAMEADDR
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG.
@ STRICT_FP_ROUND
X = STRICT_FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision ...
@ STRICT_FP_TO_SINT
STRICT_FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
@ FMINIMUM
FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0 as less than 0....
@ FP_TO_SINT
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
@ READCYCLECOUNTER
READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
@ STRICT_FP_EXTEND
X = STRICT_FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
@ AND
Bitwise operators - logical and, logical or, logical xor.
@ TRAP
TRAP - Trapping instruction.
@ INTRINSIC_WO_CHAIN
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
@ STRICT_FADD
Constrained versions of the binary floating point operators.
@ INSERT_VECTOR_ELT
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL.
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
@ ATOMIC_SWAP
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN,...
@ FP_ROUND
X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...
@ ZERO_EXTEND_VECTOR_INREG
ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register zero-extension of the low ...
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
@ BRCOND
BRCOND - Conditional branch.
@ SHL_PARTS
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.
@ AssertSext
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
@ FCOPYSIGN
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
@ GET_DYNAMIC_AREA_OFFSET
GET_DYNAMIC_AREA_OFFSET - get offset from native SP to the address of the most recent dynamic alloca.
@ INTRINSIC_W_CHAIN
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
@ BUILD_VECTOR
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a fixed-width vector with the specified,...
bool isNormalStore(const SDNode *N)
Returns true if the specified node is a non-truncating and unindexed store.
CondCode getSetCCInverse(CondCode Operation, EVT Type)
Return the operation corresponding to !(X op Y), where 'op' is a valid SetCC operation.
CondCode getSetCCSwappedOperands(CondCode Operation)
Return the operation corresponding to (Y op X) when given the operation for (X op Y).
bool isBuildVectorAllZeros(const SDNode *N)
Return true if the specified node is a BUILD_VECTOR where all of the elements are 0 or undef.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
bool isNormalLoad(const SDNode *N)
Returns true if the specified node is a non-extending and unindexed load.
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit.
@ Define
Register definition.
@ System
Synchronized with respect to all concurrently executing threads.
@ MO_ADA_DATA_SYMBOL_ADDR
@ MO_ADA_DIRECT_FUNC_DESC
@ MO_ADA_INDIRECT_FUNC_DESC
const unsigned GR64Regs[16]
const unsigned VR128Regs[32]
const unsigned GR128Regs[16]
const unsigned FP32Regs[16]
const unsigned GR32Regs[16]
const unsigned FP64Regs[16]
const int64_t ELFCallFrameSize
const unsigned VR64Regs[32]
const unsigned FP128Regs[16]
const unsigned VR32Regs[32]
unsigned odd128(bool Is32bit)
const unsigned CCMASK_CMP_GE
static bool isImmHH(uint64_t Val)
const unsigned CCMASK_TEND
const unsigned CCMASK_CS_EQ
const unsigned CCMASK_TBEGIN
const MCPhysReg ELFArgFPRs[ELFNumArgFPRs]
MachineBasicBlock * splitBlockBefore(MachineBasicBlock::iterator MI, MachineBasicBlock *MBB)
const unsigned CCMASK_TM_SOME_1
const unsigned CCMASK_LOGICAL_CARRY
const unsigned TDCMASK_NORMAL_MINUS
const unsigned CCMASK_TDC
const unsigned CCMASK_FCMP
const unsigned CCMASK_TM_SOME_0
static bool isImmHL(uint64_t Val)
const unsigned TDCMASK_SUBNORMAL_MINUS
const unsigned TDCMASK_NORMAL_PLUS
const unsigned CCMASK_CMP_GT
const unsigned TDCMASK_QNAN_MINUS
const unsigned CCMASK_ANY
const unsigned CCMASK_ARITH
const unsigned CCMASK_TM_MIXED_MSB_0
const unsigned TDCMASK_SUBNORMAL_PLUS
static bool isImmLL(uint64_t Val)
const unsigned VectorBits
static bool isImmLH(uint64_t Val)
MachineBasicBlock * emitBlockAfter(MachineBasicBlock *MBB)
const unsigned TDCMASK_INFINITY_PLUS
unsigned reverseCCMask(unsigned CCMask)
const unsigned CCMASK_TM_ALL_0
const unsigned CCMASK_CMP_LE
const unsigned CCMASK_CMP_O
const unsigned CCMASK_CMP_EQ
const unsigned VectorBytes
const unsigned TDCMASK_INFINITY_MINUS
const unsigned CCMASK_ICMP
const unsigned CCMASK_VCMP_ALL
MachineBasicBlock * splitBlockAfter(MachineBasicBlock::iterator MI, MachineBasicBlock *MBB)
const unsigned CCMASK_VCMP
const unsigned CCMASK_TM_MIXED_MSB_1
const unsigned CCMASK_TM_MSB_0
const unsigned CCMASK_ARITH_OVERFLOW
const unsigned CCMASK_CS_NE
const unsigned TDCMASK_SNAN_PLUS
const unsigned CCMASK_CMP_LT
const unsigned CCMASK_CMP_NE
const unsigned TDCMASK_ZERO_PLUS
const unsigned TDCMASK_QNAN_PLUS
const unsigned TDCMASK_ZERO_MINUS
unsigned even128(bool Is32bit)
const unsigned CCMASK_TM_ALL_1
const unsigned CCMASK_LOGICAL_BORROW
const unsigned ELFNumArgFPRs
const unsigned CCMASK_CMP_UO
const unsigned CCMASK_LOGICAL
const unsigned CCMASK_TM_MSB_1
const unsigned TDCMASK_SNAN_MINUS
Reg
All possible values of the reg field in the ModR/M byte.
support::ulittle32_t Word
NodeAddr< CodeNode * > Code
constexpr const char32_t SBase
This is an optimization pass for GlobalISel generic memory operations.
@ Low
Lower the current thread's priority such that it does not affect foreground tasks significantly.
unsigned Log2_32_Ceil(uint32_t Value)
Return the ceil log base 2 of the specified value, 32 if the value is zero.
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
testing::Matcher< const detail::ErrorHolder & > Failed()
iterator_range< T > make_range(T x, T y)
Convenience function for iterating over sub-ranges.
void dumpBytes(ArrayRef< uint8_t > Bytes, raw_ostream &OS)
Convert ‘Bytes’ to a hex string and output to ‘OS’.
T bit_ceil(T Value)
Returns the smallest integral power of two no smaller than Value if Value is nonzero.
int countr_zero(T Val)
Count number of 0's from the least significant bit to the most stopping at the first 1.
int countl_zero(T Val)
Count number of 0's from the most significant bit to the least stopping at the first 1.
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
AtomicOrdering
Atomic ordering for LLVM's memory model.
@ First
Helpers to iterate all locations in the MemoryEffectsBase class.
@ Mul
Product of integers.
DWARFExpression::Operation Op
constexpr unsigned BitWidth
constexpr int64_t SignExtend64(uint64_t x)
Sign-extend the number in the bottom B bits of X to a 64-bit integer.
T bit_floor(T Value)
Returns the largest integral power of two no greater than Value if Value is nonzero.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
AddressingMode(bool LongDispl, bool IdxReg)
This struct is a compact representation of a valid (non-zero power of two) alignment.
EVT changeVectorElementTypeToInteger() const
Return a vector with the same number of elements as this vector, but with the element type converted ...
TypeSize getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)
Returns the EVT that represents a vector NumElements in length, where each element is of type VT.
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
uint64_t getScalarSizeInBits() const
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
Returns the EVT that represents an integer with the given number of bits.
uint64_t getFixedSizeInBits() const
Return the size of the specified fixed width value type in bits.
bool isVector() const
Return true if this is a vector value type.
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
bool isRound() const
Return true if the size is a power-of-two number of bytes.
EVT getVectorElementType() const
Given a vector type, return the type of each element.
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
bool isInteger() const
Return true if this is an integer or a vector integer type.
KnownBits anyextOrTrunc(unsigned BitWidth) const
Return known bits for an "any" extension or truncation of the value we're tracking.
unsigned getBitWidth() const
Get the bit width of this value.
KnownBits zext(unsigned BitWidth) const
Return known bits for a zero extension of the value we're tracking.
void resetAll()
Resets the known state of all bits.
KnownBits intersectWith(const KnownBits &RHS) const
Returns KnownBits information that is known to be true for both this and RHS.
KnownBits sext(unsigned BitWidth) const
Return known bits for a sign extension of the value we're tracking.
APInt getMaxValue() const
Return the maximal unsigned value possible given these KnownBits.
This class contains a discriminated union of information about pointers in memory operands,...
static MachinePointerInfo getConstantPool(MachineFunction &MF)
Return a MachinePointerInfo record that refers to the constant pool.
static MachinePointerInfo getGOT(MachineFunction &MF)
Return a MachinePointerInfo record that refers to a GOT entry.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
These are IR-level optimization flags that may be propagated to SDNodes.
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
SystemZVectorConstantInfo(APInt IntImm)
SmallVector< unsigned, 2 > OpVals
bool isVectorConstantLegal(const SystemZSubtarget &Subtarget)
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg + ScalableOffset*...
This contains information for each constraint that we are lowering.
This structure contains all information that is necessary for lowering calls.
SmallVector< ISD::InputArg, 32 > Ins
CallLoweringInfo & setDiscardResult(bool Value=true)
CallLoweringInfo & setZExtResult(bool Value=true)
CallLoweringInfo & setDebugLoc(const SDLoc &dl)
CallLoweringInfo & setSExtResult(bool Value=true)
CallLoweringInfo & setNoReturn(bool Value=true)
SmallVector< ISD::OutputArg, 32 > Outs
SmallVector< SDValue, 32 > OutVals
CallLoweringInfo & setChain(SDValue InChain)
CallLoweringInfo & setCallee(CallingConv::ID CC, Type *ResultType, SDValue Target, ArgListTy &&ArgsList, AttributeSet ResultAttrs={})