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SystemZISelLowering.cpp
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00001 //===-- SystemZISelLowering.cpp - SystemZ DAG lowering implementation -----===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file implements the SystemZTargetLowering class.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #include "SystemZISelLowering.h"
00015 #include "SystemZCallingConv.h"
00016 #include "SystemZConstantPoolValue.h"
00017 #include "SystemZMachineFunctionInfo.h"
00018 #include "SystemZTargetMachine.h"
00019 #include "llvm/CodeGen/CallingConvLower.h"
00020 #include "llvm/CodeGen/MachineInstrBuilder.h"
00021 #include "llvm/CodeGen/MachineRegisterInfo.h"
00022 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
00023 #include <cctype>
00024 
00025 using namespace llvm;
00026 
00027 #define DEBUG_TYPE "systemz-lower"
00028 
00029 namespace {
00030 // Represents a sequence for extracting a 0/1 value from an IPM result:
00031 // (((X ^ XORValue) + AddValue) >> Bit)
00032 struct IPMConversion {
00033   IPMConversion(unsigned xorValue, int64_t addValue, unsigned bit)
00034     : XORValue(xorValue), AddValue(addValue), Bit(bit) {}
00035 
00036   int64_t XORValue;
00037   int64_t AddValue;
00038   unsigned Bit;
00039 };
00040 
00041 // Represents information about a comparison.
00042 struct Comparison {
00043   Comparison(SDValue Op0In, SDValue Op1In)
00044     : Op0(Op0In), Op1(Op1In), Opcode(0), ICmpType(0), CCValid(0), CCMask(0) {}
00045 
00046   // The operands to the comparison.
00047   SDValue Op0, Op1;
00048 
00049   // The opcode that should be used to compare Op0 and Op1.
00050   unsigned Opcode;
00051 
00052   // A SystemZICMP value.  Only used for integer comparisons.
00053   unsigned ICmpType;
00054 
00055   // The mask of CC values that Opcode can produce.
00056   unsigned CCValid;
00057 
00058   // The mask of CC values for which the original condition is true.
00059   unsigned CCMask;
00060 };
00061 } // end anonymous namespace
00062 
00063 // Classify VT as either 32 or 64 bit.
00064 static bool is32Bit(EVT VT) {
00065   switch (VT.getSimpleVT().SimpleTy) {
00066   case MVT::i32:
00067     return true;
00068   case MVT::i64:
00069     return false;
00070   default:
00071     llvm_unreachable("Unsupported type");
00072   }
00073 }
00074 
00075 // Return a version of MachineOperand that can be safely used before the
00076 // final use.
00077 static MachineOperand earlyUseOperand(MachineOperand Op) {
00078   if (Op.isReg())
00079     Op.setIsKill(false);
00080   return Op;
00081 }
00082 
00083 SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &tm)
00084     : TargetLowering(tm, new TargetLoweringObjectFileELF()),
00085       Subtarget(tm.getSubtarget<SystemZSubtarget>()) {
00086   MVT PtrVT = getPointerTy();
00087 
00088   // Set up the register classes.
00089   if (Subtarget.hasHighWord())
00090     addRegisterClass(MVT::i32, &SystemZ::GRX32BitRegClass);
00091   else
00092     addRegisterClass(MVT::i32, &SystemZ::GR32BitRegClass);
00093   addRegisterClass(MVT::i64,  &SystemZ::GR64BitRegClass);
00094   addRegisterClass(MVT::f32,  &SystemZ::FP32BitRegClass);
00095   addRegisterClass(MVT::f64,  &SystemZ::FP64BitRegClass);
00096   addRegisterClass(MVT::f128, &SystemZ::FP128BitRegClass);
00097 
00098   // Compute derived properties from the register classes
00099   computeRegisterProperties();
00100 
00101   // Set up special registers.
00102   setExceptionPointerRegister(SystemZ::R6D);
00103   setExceptionSelectorRegister(SystemZ::R7D);
00104   setStackPointerRegisterToSaveRestore(SystemZ::R15D);
00105 
00106   // TODO: It may be better to default to latency-oriented scheduling, however
00107   // LLVM's current latency-oriented scheduler can't handle physreg definitions
00108   // such as SystemZ has with CC, so set this to the register-pressure
00109   // scheduler, because it can.
00110   setSchedulingPreference(Sched::RegPressure);
00111 
00112   setBooleanContents(ZeroOrOneBooleanContent);
00113   setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
00114 
00115   // Instructions are strings of 2-byte aligned 2-byte values.
00116   setMinFunctionAlignment(2);
00117 
00118   // Handle operations that are handled in a similar way for all types.
00119   for (unsigned I = MVT::FIRST_INTEGER_VALUETYPE;
00120        I <= MVT::LAST_FP_VALUETYPE;
00121        ++I) {
00122     MVT VT = MVT::SimpleValueType(I);
00123     if (isTypeLegal(VT)) {
00124       // Lower SET_CC into an IPM-based sequence.
00125       setOperationAction(ISD::SETCC, VT, Custom);
00126 
00127       // Expand SELECT(C, A, B) into SELECT_CC(X, 0, A, B, NE).
00128       setOperationAction(ISD::SELECT, VT, Expand);
00129 
00130       // Lower SELECT_CC and BR_CC into separate comparisons and branches.
00131       setOperationAction(ISD::SELECT_CC, VT, Custom);
00132       setOperationAction(ISD::BR_CC,     VT, Custom);
00133     }
00134   }
00135 
00136   // Expand jump table branches as address arithmetic followed by an
00137   // indirect jump.
00138   setOperationAction(ISD::BR_JT, MVT::Other, Expand);
00139 
00140   // Expand BRCOND into a BR_CC (see above).
00141   setOperationAction(ISD::BRCOND, MVT::Other, Expand);
00142 
00143   // Handle integer types.
00144   for (unsigned I = MVT::FIRST_INTEGER_VALUETYPE;
00145        I <= MVT::LAST_INTEGER_VALUETYPE;
00146        ++I) {
00147     MVT VT = MVT::SimpleValueType(I);
00148     if (isTypeLegal(VT)) {
00149       // Expand individual DIV and REMs into DIVREMs.
00150       setOperationAction(ISD::SDIV, VT, Expand);
00151       setOperationAction(ISD::UDIV, VT, Expand);
00152       setOperationAction(ISD::SREM, VT, Expand);
00153       setOperationAction(ISD::UREM, VT, Expand);
00154       setOperationAction(ISD::SDIVREM, VT, Custom);
00155       setOperationAction(ISD::UDIVREM, VT, Custom);
00156 
00157       // Lower ATOMIC_LOAD and ATOMIC_STORE into normal volatile loads and
00158       // stores, putting a serialization instruction after the stores.
00159       setOperationAction(ISD::ATOMIC_LOAD,  VT, Custom);
00160       setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
00161 
00162       // Lower ATOMIC_LOAD_SUB into ATOMIC_LOAD_ADD if LAA and LAAG are
00163       // available, or if the operand is constant.
00164       setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
00165 
00166       // No special instructions for these.
00167       setOperationAction(ISD::CTPOP,           VT, Expand);
00168       setOperationAction(ISD::CTTZ,            VT, Expand);
00169       setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
00170       setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
00171       setOperationAction(ISD::ROTR,            VT, Expand);
00172 
00173       // Use *MUL_LOHI where possible instead of MULH*.
00174       setOperationAction(ISD::MULHS, VT, Expand);
00175       setOperationAction(ISD::MULHU, VT, Expand);
00176       setOperationAction(ISD::SMUL_LOHI, VT, Custom);
00177       setOperationAction(ISD::UMUL_LOHI, VT, Custom);
00178 
00179       // Only z196 and above have native support for conversions to unsigned.
00180       if (!Subtarget.hasFPExtension())
00181         setOperationAction(ISD::FP_TO_UINT, VT, Expand);
00182     }
00183   }
00184 
00185   // Type legalization will convert 8- and 16-bit atomic operations into
00186   // forms that operate on i32s (but still keeping the original memory VT).
00187   // Lower them into full i32 operations.
00188   setOperationAction(ISD::ATOMIC_SWAP,      MVT::i32, Custom);
00189   setOperationAction(ISD::ATOMIC_LOAD_ADD,  MVT::i32, Custom);
00190   setOperationAction(ISD::ATOMIC_LOAD_SUB,  MVT::i32, Custom);
00191   setOperationAction(ISD::ATOMIC_LOAD_AND,  MVT::i32, Custom);
00192   setOperationAction(ISD::ATOMIC_LOAD_OR,   MVT::i32, Custom);
00193   setOperationAction(ISD::ATOMIC_LOAD_XOR,  MVT::i32, Custom);
00194   setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Custom);
00195   setOperationAction(ISD::ATOMIC_LOAD_MIN,  MVT::i32, Custom);
00196   setOperationAction(ISD::ATOMIC_LOAD_MAX,  MVT::i32, Custom);
00197   setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Custom);
00198   setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Custom);
00199   setOperationAction(ISD::ATOMIC_CMP_SWAP,  MVT::i32, Custom);
00200 
00201   // z10 has instructions for signed but not unsigned FP conversion.
00202   // Handle unsigned 32-bit types as signed 64-bit types.
00203   if (!Subtarget.hasFPExtension()) {
00204     setOperationAction(ISD::UINT_TO_FP, MVT::i32, Promote);
00205     setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
00206   }
00207 
00208   // We have native support for a 64-bit CTLZ, via FLOGR.
00209   setOperationAction(ISD::CTLZ, MVT::i32, Promote);
00210   setOperationAction(ISD::CTLZ, MVT::i64, Legal);
00211 
00212   // Give LowerOperation the chance to replace 64-bit ORs with subregs.
00213   setOperationAction(ISD::OR, MVT::i64, Custom);
00214 
00215   // FIXME: Can we support these natively?
00216   setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
00217   setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
00218   setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
00219 
00220   // We have native instructions for i8, i16 and i32 extensions, but not i1.
00221   setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
00222   setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
00223   setLoadExtAction(ISD::EXTLOAD,  MVT::i1, Promote);
00224   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
00225 
00226   // Handle the various types of symbolic address.
00227   setOperationAction(ISD::ConstantPool,     PtrVT, Custom);
00228   setOperationAction(ISD::GlobalAddress,    PtrVT, Custom);
00229   setOperationAction(ISD::GlobalTLSAddress, PtrVT, Custom);
00230   setOperationAction(ISD::BlockAddress,     PtrVT, Custom);
00231   setOperationAction(ISD::JumpTable,        PtrVT, Custom);
00232 
00233   // We need to handle dynamic allocations specially because of the
00234   // 160-byte area at the bottom of the stack.
00235   setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom);
00236 
00237   // Use custom expanders so that we can force the function to use
00238   // a frame pointer.
00239   setOperationAction(ISD::STACKSAVE,    MVT::Other, Custom);
00240   setOperationAction(ISD::STACKRESTORE, MVT::Other, Custom);
00241 
00242   // Handle prefetches with PFD or PFDRL.
00243   setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
00244 
00245   // Handle floating-point types.
00246   for (unsigned I = MVT::FIRST_FP_VALUETYPE;
00247        I <= MVT::LAST_FP_VALUETYPE;
00248        ++I) {
00249     MVT VT = MVT::SimpleValueType(I);
00250     if (isTypeLegal(VT)) {
00251       // We can use FI for FRINT.
00252       setOperationAction(ISD::FRINT, VT, Legal);
00253 
00254       // We can use the extended form of FI for other rounding operations.
00255       if (Subtarget.hasFPExtension()) {
00256         setOperationAction(ISD::FNEARBYINT, VT, Legal);
00257         setOperationAction(ISD::FFLOOR, VT, Legal);
00258         setOperationAction(ISD::FCEIL, VT, Legal);
00259         setOperationAction(ISD::FTRUNC, VT, Legal);
00260         setOperationAction(ISD::FROUND, VT, Legal);
00261       }
00262 
00263       // No special instructions for these.
00264       setOperationAction(ISD::FSIN, VT, Expand);
00265       setOperationAction(ISD::FCOS, VT, Expand);
00266       setOperationAction(ISD::FREM, VT, Expand);
00267     }
00268   }
00269 
00270   // We have fused multiply-addition for f32 and f64 but not f128.
00271   setOperationAction(ISD::FMA, MVT::f32,  Legal);
00272   setOperationAction(ISD::FMA, MVT::f64,  Legal);
00273   setOperationAction(ISD::FMA, MVT::f128, Expand);
00274 
00275   // Needed so that we don't try to implement f128 constant loads using
00276   // a load-and-extend of a f80 constant (in cases where the constant
00277   // would fit in an f80).
00278   setLoadExtAction(ISD::EXTLOAD, MVT::f80, Expand);
00279 
00280   // Floating-point truncation and stores need to be done separately.
00281   setTruncStoreAction(MVT::f64,  MVT::f32, Expand);
00282   setTruncStoreAction(MVT::f128, MVT::f32, Expand);
00283   setTruncStoreAction(MVT::f128, MVT::f64, Expand);
00284 
00285   // We have 64-bit FPR<->GPR moves, but need special handling for
00286   // 32-bit forms.
00287   setOperationAction(ISD::BITCAST, MVT::i32, Custom);
00288   setOperationAction(ISD::BITCAST, MVT::f32, Custom);
00289 
00290   // VASTART and VACOPY need to deal with the SystemZ-specific varargs
00291   // structure, but VAEND is a no-op.
00292   setOperationAction(ISD::VASTART, MVT::Other, Custom);
00293   setOperationAction(ISD::VACOPY,  MVT::Other, Custom);
00294   setOperationAction(ISD::VAEND,   MVT::Other, Expand);
00295 
00296   // Codes for which we want to perform some z-specific combinations.
00297   setTargetDAGCombine(ISD::SIGN_EXTEND);
00298 
00299   // We want to use MVC in preference to even a single load/store pair.
00300   MaxStoresPerMemcpy = 0;
00301   MaxStoresPerMemcpyOptSize = 0;
00302 
00303   // The main memset sequence is a byte store followed by an MVC.
00304   // Two STC or MV..I stores win over that, but the kind of fused stores
00305   // generated by target-independent code don't when the byte value is
00306   // variable.  E.g.  "STC <reg>;MHI <reg>,257;STH <reg>" is not better
00307   // than "STC;MVC".  Handle the choice in target-specific code instead.
00308   MaxStoresPerMemset = 0;
00309   MaxStoresPerMemsetOptSize = 0;
00310 }
00311 
00312 EVT SystemZTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
00313   if (!VT.isVector())
00314     return MVT::i32;
00315   return VT.changeVectorElementTypeToInteger();
00316 }
00317 
00318 bool SystemZTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
00319   VT = VT.getScalarType();
00320 
00321   if (!VT.isSimple())
00322     return false;
00323 
00324   switch (VT.getSimpleVT().SimpleTy) {
00325   case MVT::f32:
00326   case MVT::f64:
00327     return true;
00328   case MVT::f128:
00329     return false;
00330   default:
00331     break;
00332   }
00333 
00334   return false;
00335 }
00336 
00337 bool SystemZTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
00338   // We can load zero using LZ?R and negative zero using LZ?R;LC?BR.
00339   return Imm.isZero() || Imm.isNegZero();
00340 }
00341 
00342 bool SystemZTargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
00343                                                           unsigned,
00344                                                           bool *Fast) const {
00345   // Unaligned accesses should never be slower than the expanded version.
00346   // We check specifically for aligned accesses in the few cases where
00347   // they are required.
00348   if (Fast)
00349     *Fast = true;
00350   return true;
00351 }
00352   
00353 bool SystemZTargetLowering::isLegalAddressingMode(const AddrMode &AM,
00354                                                   Type *Ty) const {
00355   // Punt on globals for now, although they can be used in limited
00356   // RELATIVE LONG cases.
00357   if (AM.BaseGV)
00358     return false;
00359 
00360   // Require a 20-bit signed offset.
00361   if (!isInt<20>(AM.BaseOffs))
00362     return false;
00363 
00364   // Indexing is OK but no scale factor can be applied.
00365   return AM.Scale == 0 || AM.Scale == 1;
00366 }
00367 
00368 bool SystemZTargetLowering::isTruncateFree(Type *FromType, Type *ToType) const {
00369   if (!FromType->isIntegerTy() || !ToType->isIntegerTy())
00370     return false;
00371   unsigned FromBits = FromType->getPrimitiveSizeInBits();
00372   unsigned ToBits = ToType->getPrimitiveSizeInBits();
00373   return FromBits > ToBits;
00374 }
00375 
00376 bool SystemZTargetLowering::isTruncateFree(EVT FromVT, EVT ToVT) const {
00377   if (!FromVT.isInteger() || !ToVT.isInteger())
00378     return false;
00379   unsigned FromBits = FromVT.getSizeInBits();
00380   unsigned ToBits = ToVT.getSizeInBits();
00381   return FromBits > ToBits;
00382 }
00383 
00384 //===----------------------------------------------------------------------===//
00385 // Inline asm support
00386 //===----------------------------------------------------------------------===//
00387 
00388 TargetLowering::ConstraintType
00389 SystemZTargetLowering::getConstraintType(const std::string &Constraint) const {
00390   if (Constraint.size() == 1) {
00391     switch (Constraint[0]) {
00392     case 'a': // Address register
00393     case 'd': // Data register (equivalent to 'r')
00394     case 'f': // Floating-point register
00395     case 'h': // High-part register
00396     case 'r': // General-purpose register
00397       return C_RegisterClass;
00398 
00399     case 'Q': // Memory with base and unsigned 12-bit displacement
00400     case 'R': // Likewise, plus an index
00401     case 'S': // Memory with base and signed 20-bit displacement
00402     case 'T': // Likewise, plus an index
00403     case 'm': // Equivalent to 'T'.
00404       return C_Memory;
00405 
00406     case 'I': // Unsigned 8-bit constant
00407     case 'J': // Unsigned 12-bit constant
00408     case 'K': // Signed 16-bit constant
00409     case 'L': // Signed 20-bit displacement (on all targets we support)
00410     case 'M': // 0x7fffffff
00411       return C_Other;
00412 
00413     default:
00414       break;
00415     }
00416   }
00417   return TargetLowering::getConstraintType(Constraint);
00418 }
00419 
00420 TargetLowering::ConstraintWeight SystemZTargetLowering::
00421 getSingleConstraintMatchWeight(AsmOperandInfo &info,
00422                                const char *constraint) const {
00423   ConstraintWeight weight = CW_Invalid;
00424   Value *CallOperandVal = info.CallOperandVal;
00425   // If we don't have a value, we can't do a match,
00426   // but allow it at the lowest weight.
00427   if (!CallOperandVal)
00428     return CW_Default;
00429   Type *type = CallOperandVal->getType();
00430   // Look at the constraint type.
00431   switch (*constraint) {
00432   default:
00433     weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
00434     break;
00435 
00436   case 'a': // Address register
00437   case 'd': // Data register (equivalent to 'r')
00438   case 'h': // High-part register
00439   case 'r': // General-purpose register
00440     if (CallOperandVal->getType()->isIntegerTy())
00441       weight = CW_Register;
00442     break;
00443 
00444   case 'f': // Floating-point register
00445     if (type->isFloatingPointTy())
00446       weight = CW_Register;
00447     break;
00448 
00449   case 'I': // Unsigned 8-bit constant
00450     if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
00451       if (isUInt<8>(C->getZExtValue()))
00452         weight = CW_Constant;
00453     break;
00454 
00455   case 'J': // Unsigned 12-bit constant
00456     if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
00457       if (isUInt<12>(C->getZExtValue()))
00458         weight = CW_Constant;
00459     break;
00460 
00461   case 'K': // Signed 16-bit constant
00462     if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
00463       if (isInt<16>(C->getSExtValue()))
00464         weight = CW_Constant;
00465     break;
00466 
00467   case 'L': // Signed 20-bit displacement (on all targets we support)
00468     if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
00469       if (isInt<20>(C->getSExtValue()))
00470         weight = CW_Constant;
00471     break;
00472 
00473   case 'M': // 0x7fffffff
00474     if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
00475       if (C->getZExtValue() == 0x7fffffff)
00476         weight = CW_Constant;
00477     break;
00478   }
00479   return weight;
00480 }
00481 
00482 // Parse a "{tNNN}" register constraint for which the register type "t"
00483 // has already been verified.  MC is the class associated with "t" and
00484 // Map maps 0-based register numbers to LLVM register numbers.
00485 static std::pair<unsigned, const TargetRegisterClass *>
00486 parseRegisterNumber(const std::string &Constraint,
00487                     const TargetRegisterClass *RC, const unsigned *Map) {
00488   assert(*(Constraint.end()-1) == '}' && "Missing '}'");
00489   if (isdigit(Constraint[2])) {
00490     std::string Suffix(Constraint.data() + 2, Constraint.size() - 2);
00491     unsigned Index = atoi(Suffix.c_str());
00492     if (Index < 16 && Map[Index])
00493       return std::make_pair(Map[Index], RC);
00494   }
00495   return std::make_pair(0U, nullptr);
00496 }
00497 
00498 std::pair<unsigned, const TargetRegisterClass *> SystemZTargetLowering::
00499 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const {
00500   if (Constraint.size() == 1) {
00501     // GCC Constraint Letters
00502     switch (Constraint[0]) {
00503     default: break;
00504     case 'd': // Data register (equivalent to 'r')
00505     case 'r': // General-purpose register
00506       if (VT == MVT::i64)
00507         return std::make_pair(0U, &SystemZ::GR64BitRegClass);
00508       else if (VT == MVT::i128)
00509         return std::make_pair(0U, &SystemZ::GR128BitRegClass);
00510       return std::make_pair(0U, &SystemZ::GR32BitRegClass);
00511 
00512     case 'a': // Address register
00513       if (VT == MVT::i64)
00514         return std::make_pair(0U, &SystemZ::ADDR64BitRegClass);
00515       else if (VT == MVT::i128)
00516         return std::make_pair(0U, &SystemZ::ADDR128BitRegClass);
00517       return std::make_pair(0U, &SystemZ::ADDR32BitRegClass);
00518 
00519     case 'h': // High-part register (an LLVM extension)
00520       return std::make_pair(0U, &SystemZ::GRH32BitRegClass);
00521 
00522     case 'f': // Floating-point register
00523       if (VT == MVT::f64)
00524         return std::make_pair(0U, &SystemZ::FP64BitRegClass);
00525       else if (VT == MVT::f128)
00526         return std::make_pair(0U, &SystemZ::FP128BitRegClass);
00527       return std::make_pair(0U, &SystemZ::FP32BitRegClass);
00528     }
00529   }
00530   if (Constraint[0] == '{') {
00531     // We need to override the default register parsing for GPRs and FPRs
00532     // because the interpretation depends on VT.  The internal names of
00533     // the registers are also different from the external names
00534     // (F0D and F0S instead of F0, etc.).
00535     if (Constraint[1] == 'r') {
00536       if (VT == MVT::i32)
00537         return parseRegisterNumber(Constraint, &SystemZ::GR32BitRegClass,
00538                                    SystemZMC::GR32Regs);
00539       if (VT == MVT::i128)
00540         return parseRegisterNumber(Constraint, &SystemZ::GR128BitRegClass,
00541                                    SystemZMC::GR128Regs);
00542       return parseRegisterNumber(Constraint, &SystemZ::GR64BitRegClass,
00543                                  SystemZMC::GR64Regs);
00544     }
00545     if (Constraint[1] == 'f') {
00546       if (VT == MVT::f32)
00547         return parseRegisterNumber(Constraint, &SystemZ::FP32BitRegClass,
00548                                    SystemZMC::FP32Regs);
00549       if (VT == MVT::f128)
00550         return parseRegisterNumber(Constraint, &SystemZ::FP128BitRegClass,
00551                                    SystemZMC::FP128Regs);
00552       return parseRegisterNumber(Constraint, &SystemZ::FP64BitRegClass,
00553                                  SystemZMC::FP64Regs);
00554     }
00555   }
00556   return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
00557 }
00558 
00559 void SystemZTargetLowering::
00560 LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
00561                              std::vector<SDValue> &Ops,
00562                              SelectionDAG &DAG) const {
00563   // Only support length 1 constraints for now.
00564   if (Constraint.length() == 1) {
00565     switch (Constraint[0]) {
00566     case 'I': // Unsigned 8-bit constant
00567       if (auto *C = dyn_cast<ConstantSDNode>(Op))
00568         if (isUInt<8>(C->getZExtValue()))
00569           Ops.push_back(DAG.getTargetConstant(C->getZExtValue(),
00570                                               Op.getValueType()));
00571       return;
00572 
00573     case 'J': // Unsigned 12-bit constant
00574       if (auto *C = dyn_cast<ConstantSDNode>(Op))
00575         if (isUInt<12>(C->getZExtValue()))
00576           Ops.push_back(DAG.getTargetConstant(C->getZExtValue(),
00577                                               Op.getValueType()));
00578       return;
00579 
00580     case 'K': // Signed 16-bit constant
00581       if (auto *C = dyn_cast<ConstantSDNode>(Op))
00582         if (isInt<16>(C->getSExtValue()))
00583           Ops.push_back(DAG.getTargetConstant(C->getSExtValue(),
00584                                               Op.getValueType()));
00585       return;
00586 
00587     case 'L': // Signed 20-bit displacement (on all targets we support)
00588       if (auto *C = dyn_cast<ConstantSDNode>(Op))
00589         if (isInt<20>(C->getSExtValue()))
00590           Ops.push_back(DAG.getTargetConstant(C->getSExtValue(),
00591                                               Op.getValueType()));
00592       return;
00593 
00594     case 'M': // 0x7fffffff
00595       if (auto *C = dyn_cast<ConstantSDNode>(Op))
00596         if (C->getZExtValue() == 0x7fffffff)
00597           Ops.push_back(DAG.getTargetConstant(C->getZExtValue(),
00598                                               Op.getValueType()));
00599       return;
00600     }
00601   }
00602   TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
00603 }
00604 
00605 //===----------------------------------------------------------------------===//
00606 // Calling conventions
00607 //===----------------------------------------------------------------------===//
00608 
00609 #include "SystemZGenCallingConv.inc"
00610 
00611 bool SystemZTargetLowering::allowTruncateForTailCall(Type *FromType,
00612                                                      Type *ToType) const {
00613   return isTruncateFree(FromType, ToType);
00614 }
00615 
00616 bool SystemZTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
00617   if (!CI->isTailCall())
00618     return false;
00619   return true;
00620 }
00621 
00622 // Value is a value that has been passed to us in the location described by VA
00623 // (and so has type VA.getLocVT()).  Convert Value to VA.getValVT(), chaining
00624 // any loads onto Chain.
00625 static SDValue convertLocVTToValVT(SelectionDAG &DAG, SDLoc DL,
00626                                    CCValAssign &VA, SDValue Chain,
00627                                    SDValue Value) {
00628   // If the argument has been promoted from a smaller type, insert an
00629   // assertion to capture this.
00630   if (VA.getLocInfo() == CCValAssign::SExt)
00631     Value = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Value,
00632                         DAG.getValueType(VA.getValVT()));
00633   else if (VA.getLocInfo() == CCValAssign::ZExt)
00634     Value = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Value,
00635                         DAG.getValueType(VA.getValVT()));
00636 
00637   if (VA.isExtInLoc())
00638     Value = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Value);
00639   else if (VA.getLocInfo() == CCValAssign::Indirect)
00640     Value = DAG.getLoad(VA.getValVT(), DL, Chain, Value,
00641                         MachinePointerInfo(), false, false, false, 0);
00642   else
00643     assert(VA.getLocInfo() == CCValAssign::Full && "Unsupported getLocInfo");
00644   return Value;
00645 }
00646 
00647 // Value is a value of type VA.getValVT() that we need to copy into
00648 // the location described by VA.  Return a copy of Value converted to
00649 // VA.getValVT().  The caller is responsible for handling indirect values.
00650 static SDValue convertValVTToLocVT(SelectionDAG &DAG, SDLoc DL,
00651                                    CCValAssign &VA, SDValue Value) {
00652   switch (VA.getLocInfo()) {
00653   case CCValAssign::SExt:
00654     return DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Value);
00655   case CCValAssign::ZExt:
00656     return DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Value);
00657   case CCValAssign::AExt:
00658     return DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Value);
00659   case CCValAssign::Full:
00660     return Value;
00661   default:
00662     llvm_unreachable("Unhandled getLocInfo()");
00663   }
00664 }
00665 
00666 SDValue SystemZTargetLowering::
00667 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
00668                      const SmallVectorImpl<ISD::InputArg> &Ins,
00669                      SDLoc DL, SelectionDAG &DAG,
00670                      SmallVectorImpl<SDValue> &InVals) const {
00671   MachineFunction &MF = DAG.getMachineFunction();
00672   MachineFrameInfo *MFI = MF.getFrameInfo();
00673   MachineRegisterInfo &MRI = MF.getRegInfo();
00674   SystemZMachineFunctionInfo *FuncInfo =
00675     MF.getInfo<SystemZMachineFunctionInfo>();
00676   auto *TFL = static_cast<const SystemZFrameLowering *>(
00677       DAG.getTarget().getFrameLowering());
00678 
00679   // Assign locations to all of the incoming arguments.
00680   SmallVector<CCValAssign, 16> ArgLocs;
00681   CCState CCInfo(CallConv, IsVarArg, MF, DAG.getTarget(), ArgLocs,
00682                  *DAG.getContext());
00683   CCInfo.AnalyzeFormalArguments(Ins, CC_SystemZ);
00684 
00685   unsigned NumFixedGPRs = 0;
00686   unsigned NumFixedFPRs = 0;
00687   for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
00688     SDValue ArgValue;
00689     CCValAssign &VA = ArgLocs[I];
00690     EVT LocVT = VA.getLocVT();
00691     if (VA.isRegLoc()) {
00692       // Arguments passed in registers
00693       const TargetRegisterClass *RC;
00694       switch (LocVT.getSimpleVT().SimpleTy) {
00695       default:
00696         // Integers smaller than i64 should be promoted to i64.
00697         llvm_unreachable("Unexpected argument type");
00698       case MVT::i32:
00699         NumFixedGPRs += 1;
00700         RC = &SystemZ::GR32BitRegClass;
00701         break;
00702       case MVT::i64:
00703         NumFixedGPRs += 1;
00704         RC = &SystemZ::GR64BitRegClass;
00705         break;
00706       case MVT::f32:
00707         NumFixedFPRs += 1;
00708         RC = &SystemZ::FP32BitRegClass;
00709         break;
00710       case MVT::f64:
00711         NumFixedFPRs += 1;
00712         RC = &SystemZ::FP64BitRegClass;
00713         break;
00714       }
00715 
00716       unsigned VReg = MRI.createVirtualRegister(RC);
00717       MRI.addLiveIn(VA.getLocReg(), VReg);
00718       ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, LocVT);
00719     } else {
00720       assert(VA.isMemLoc() && "Argument not register or memory");
00721 
00722       // Create the frame index object for this incoming parameter.
00723       int FI = MFI->CreateFixedObject(LocVT.getSizeInBits() / 8,
00724                                       VA.getLocMemOffset(), true);
00725 
00726       // Create the SelectionDAG nodes corresponding to a load
00727       // from this parameter.  Unpromoted ints and floats are
00728       // passed as right-justified 8-byte values.
00729       EVT PtrVT = getPointerTy();
00730       SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
00731       if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)
00732         FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4));
00733       ArgValue = DAG.getLoad(LocVT, DL, Chain, FIN,
00734                              MachinePointerInfo::getFixedStack(FI),
00735                              false, false, false, 0);
00736     }
00737 
00738     // Convert the value of the argument register into the value that's
00739     // being passed.
00740     InVals.push_back(convertLocVTToValVT(DAG, DL, VA, Chain, ArgValue));
00741   }
00742 
00743   if (IsVarArg) {
00744     // Save the number of non-varargs registers for later use by va_start, etc.
00745     FuncInfo->setVarArgsFirstGPR(NumFixedGPRs);
00746     FuncInfo->setVarArgsFirstFPR(NumFixedFPRs);
00747 
00748     // Likewise the address (in the form of a frame index) of where the
00749     // first stack vararg would be.  The 1-byte size here is arbitrary.
00750     int64_t StackSize = CCInfo.getNextStackOffset();
00751     FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize, true));
00752 
00753     // ...and a similar frame index for the caller-allocated save area
00754     // that will be used to store the incoming registers.
00755     int64_t RegSaveOffset = TFL->getOffsetOfLocalArea();
00756     unsigned RegSaveIndex = MFI->CreateFixedObject(1, RegSaveOffset, true);
00757     FuncInfo->setRegSaveFrameIndex(RegSaveIndex);
00758 
00759     // Store the FPR varargs in the reserved frame slots.  (We store the
00760     // GPRs as part of the prologue.)
00761     if (NumFixedFPRs < SystemZ::NumArgFPRs) {
00762       SDValue MemOps[SystemZ::NumArgFPRs];
00763       for (unsigned I = NumFixedFPRs; I < SystemZ::NumArgFPRs; ++I) {
00764         unsigned Offset = TFL->getRegSpillOffset(SystemZ::ArgFPRs[I]);
00765         int FI = MFI->CreateFixedObject(8, RegSaveOffset + Offset, true);
00766         SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
00767         unsigned VReg = MF.addLiveIn(SystemZ::ArgFPRs[I],
00768                                      &SystemZ::FP64BitRegClass);
00769         SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f64);
00770         MemOps[I] = DAG.getStore(ArgValue.getValue(1), DL, ArgValue, FIN,
00771                                  MachinePointerInfo::getFixedStack(FI),
00772                                  false, false, 0);
00773 
00774       }
00775       // Join the stores, which are independent of one another.
00776       Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
00777                           makeArrayRef(&MemOps[NumFixedFPRs],
00778                                        SystemZ::NumArgFPRs-NumFixedFPRs));
00779     }
00780   }
00781 
00782   return Chain;
00783 }
00784 
00785 static bool canUseSiblingCall(CCState ArgCCInfo,
00786                               SmallVectorImpl<CCValAssign> &ArgLocs) {
00787   // Punt if there are any indirect or stack arguments, or if the call
00788   // needs the call-saved argument register R6.
00789   for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
00790     CCValAssign &VA = ArgLocs[I];
00791     if (VA.getLocInfo() == CCValAssign::Indirect)
00792       return false;
00793     if (!VA.isRegLoc())
00794       return false;
00795     unsigned Reg = VA.getLocReg();
00796     if (Reg == SystemZ::R6H || Reg == SystemZ::R6L || Reg == SystemZ::R6D)
00797       return false;
00798   }
00799   return true;
00800 }
00801 
00802 SDValue
00803 SystemZTargetLowering::LowerCall(CallLoweringInfo &CLI,
00804                                  SmallVectorImpl<SDValue> &InVals) const {
00805   SelectionDAG &DAG = CLI.DAG;
00806   SDLoc &DL = CLI.DL;
00807   SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
00808   SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
00809   SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
00810   SDValue Chain = CLI.Chain;
00811   SDValue Callee = CLI.Callee;
00812   bool &IsTailCall = CLI.IsTailCall;
00813   CallingConv::ID CallConv = CLI.CallConv;
00814   bool IsVarArg = CLI.IsVarArg;
00815   MachineFunction &MF = DAG.getMachineFunction();
00816   EVT PtrVT = getPointerTy();
00817 
00818   // Analyze the operands of the call, assigning locations to each operand.
00819   SmallVector<CCValAssign, 16> ArgLocs;
00820   CCState ArgCCInfo(CallConv, IsVarArg, MF, DAG.getTarget(), ArgLocs,
00821                     *DAG.getContext());
00822   ArgCCInfo.AnalyzeCallOperands(Outs, CC_SystemZ);
00823 
00824   // We don't support GuaranteedTailCallOpt, only automatically-detected
00825   // sibling calls.
00826   if (IsTailCall && !canUseSiblingCall(ArgCCInfo, ArgLocs))
00827     IsTailCall = false;
00828 
00829   // Get a count of how many bytes are to be pushed on the stack.
00830   unsigned NumBytes = ArgCCInfo.getNextStackOffset();
00831 
00832   // Mark the start of the call.
00833   if (!IsTailCall)
00834     Chain = DAG.getCALLSEQ_START(Chain, DAG.getConstant(NumBytes, PtrVT, true),
00835                                  DL);
00836 
00837   // Copy argument values to their designated locations.
00838   SmallVector<std::pair<unsigned, SDValue>, 9> RegsToPass;
00839   SmallVector<SDValue, 8> MemOpChains;
00840   SDValue StackPtr;
00841   for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
00842     CCValAssign &VA = ArgLocs[I];
00843     SDValue ArgValue = OutVals[I];
00844 
00845     if (VA.getLocInfo() == CCValAssign::Indirect) {
00846       // Store the argument in a stack slot and pass its address.
00847       SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
00848       int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
00849       MemOpChains.push_back(DAG.getStore(Chain, DL, ArgValue, SpillSlot,
00850                                          MachinePointerInfo::getFixedStack(FI),
00851                                          false, false, 0));
00852       ArgValue = SpillSlot;
00853     } else
00854       ArgValue = convertValVTToLocVT(DAG, DL, VA, ArgValue);
00855 
00856     if (VA.isRegLoc())
00857       // Queue up the argument copies and emit them at the end.
00858       RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue));
00859     else {
00860       assert(VA.isMemLoc() && "Argument not register or memory");
00861 
00862       // Work out the address of the stack slot.  Unpromoted ints and
00863       // floats are passed as right-justified 8-byte values.
00864       if (!StackPtr.getNode())
00865         StackPtr = DAG.getCopyFromReg(Chain, DL, SystemZ::R15D, PtrVT);
00866       unsigned Offset = SystemZMC::CallFrameSize + VA.getLocMemOffset();
00867       if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)
00868         Offset += 4;
00869       SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr,
00870                                     DAG.getIntPtrConstant(Offset));
00871 
00872       // Emit the store.
00873       MemOpChains.push_back(DAG.getStore(Chain, DL, ArgValue, Address,
00874                                          MachinePointerInfo(),
00875                                          false, false, 0));
00876     }
00877   }
00878 
00879   // Join the stores, which are independent of one another.
00880   if (!MemOpChains.empty())
00881     Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
00882 
00883   // Accept direct calls by converting symbolic call addresses to the
00884   // associated Target* opcodes.  Force %r1 to be used for indirect
00885   // tail calls.
00886   SDValue Glue;
00887   if (auto *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
00888     Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, PtrVT);
00889     Callee = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Callee);
00890   } else if (auto *E = dyn_cast<ExternalSymbolSDNode>(Callee)) {
00891     Callee = DAG.getTargetExternalSymbol(E->getSymbol(), PtrVT);
00892     Callee = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Callee);
00893   } else if (IsTailCall) {
00894     Chain = DAG.getCopyToReg(Chain, DL, SystemZ::R1D, Callee, Glue);
00895     Glue = Chain.getValue(1);
00896     Callee = DAG.getRegister(SystemZ::R1D, Callee.getValueType());
00897   }
00898 
00899   // Build a sequence of copy-to-reg nodes, chained and glued together.
00900   for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I) {
00901     Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[I].first,
00902                              RegsToPass[I].second, Glue);
00903     Glue = Chain.getValue(1);
00904   }
00905 
00906   // The first call operand is the chain and the second is the target address.
00907   SmallVector<SDValue, 8> Ops;
00908   Ops.push_back(Chain);
00909   Ops.push_back(Callee);
00910 
00911   // Add argument registers to the end of the list so that they are
00912   // known live into the call.
00913   for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I)
00914     Ops.push_back(DAG.getRegister(RegsToPass[I].first,
00915                                   RegsToPass[I].second.getValueType()));
00916 
00917   // Add a register mask operand representing the call-preserved registers.
00918   const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
00919   const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
00920   assert(Mask && "Missing call preserved mask for calling convention");
00921   Ops.push_back(DAG.getRegisterMask(Mask));
00922 
00923   // Glue the call to the argument copies, if any.
00924   if (Glue.getNode())
00925     Ops.push_back(Glue);
00926 
00927   // Emit the call.
00928   SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
00929   if (IsTailCall)
00930     return DAG.getNode(SystemZISD::SIBCALL, DL, NodeTys, Ops);
00931   Chain = DAG.getNode(SystemZISD::CALL, DL, NodeTys, Ops);
00932   Glue = Chain.getValue(1);
00933 
00934   // Mark the end of the call, which is glued to the call itself.
00935   Chain = DAG.getCALLSEQ_END(Chain,
00936                              DAG.getConstant(NumBytes, PtrVT, true),
00937                              DAG.getConstant(0, PtrVT, true),
00938                              Glue, DL);
00939   Glue = Chain.getValue(1);
00940 
00941   // Assign locations to each value returned by this call.
00942   SmallVector<CCValAssign, 16> RetLocs;
00943   CCState RetCCInfo(CallConv, IsVarArg, MF, DAG.getTarget(), RetLocs,
00944                     *DAG.getContext());
00945   RetCCInfo.AnalyzeCallResult(Ins, RetCC_SystemZ);
00946 
00947   // Copy all of the result registers out of their specified physreg.
00948   for (unsigned I = 0, E = RetLocs.size(); I != E; ++I) {
00949     CCValAssign &VA = RetLocs[I];
00950 
00951     // Copy the value out, gluing the copy to the end of the call sequence.
00952     SDValue RetValue = DAG.getCopyFromReg(Chain, DL, VA.getLocReg(),
00953                                           VA.getLocVT(), Glue);
00954     Chain = RetValue.getValue(1);
00955     Glue = RetValue.getValue(2);
00956 
00957     // Convert the value of the return register into the value that's
00958     // being returned.
00959     InVals.push_back(convertLocVTToValVT(DAG, DL, VA, Chain, RetValue));
00960   }
00961 
00962   return Chain;
00963 }
00964 
00965 SDValue
00966 SystemZTargetLowering::LowerReturn(SDValue Chain,
00967                                    CallingConv::ID CallConv, bool IsVarArg,
00968                                    const SmallVectorImpl<ISD::OutputArg> &Outs,
00969                                    const SmallVectorImpl<SDValue> &OutVals,
00970                                    SDLoc DL, SelectionDAG &DAG) const {
00971   MachineFunction &MF = DAG.getMachineFunction();
00972 
00973   // Assign locations to each returned value.
00974   SmallVector<CCValAssign, 16> RetLocs;
00975   CCState RetCCInfo(CallConv, IsVarArg, MF, DAG.getTarget(), RetLocs,
00976                     *DAG.getContext());
00977   RetCCInfo.AnalyzeReturn(Outs, RetCC_SystemZ);
00978 
00979   // Quick exit for void returns
00980   if (RetLocs.empty())
00981     return DAG.getNode(SystemZISD::RET_FLAG, DL, MVT::Other, Chain);
00982 
00983   // Copy the result values into the output registers.
00984   SDValue Glue;
00985   SmallVector<SDValue, 4> RetOps;
00986   RetOps.push_back(Chain);
00987   for (unsigned I = 0, E = RetLocs.size(); I != E; ++I) {
00988     CCValAssign &VA = RetLocs[I];
00989     SDValue RetValue = OutVals[I];
00990 
00991     // Make the return register live on exit.
00992     assert(VA.isRegLoc() && "Can only return in registers!");
00993 
00994     // Promote the value as required.
00995     RetValue = convertValVTToLocVT(DAG, DL, VA, RetValue);
00996 
00997     // Chain and glue the copies together.
00998     unsigned Reg = VA.getLocReg();
00999     Chain = DAG.getCopyToReg(Chain, DL, Reg, RetValue, Glue);
01000     Glue = Chain.getValue(1);
01001     RetOps.push_back(DAG.getRegister(Reg, VA.getLocVT()));
01002   }
01003 
01004   // Update chain and glue.
01005   RetOps[0] = Chain;
01006   if (Glue.getNode())
01007     RetOps.push_back(Glue);
01008 
01009   return DAG.getNode(SystemZISD::RET_FLAG, DL, MVT::Other, RetOps);
01010 }
01011 
01012 SDValue SystemZTargetLowering::
01013 prepareVolatileOrAtomicLoad(SDValue Chain, SDLoc DL, SelectionDAG &DAG) const {
01014   return DAG.getNode(SystemZISD::SERIALIZE, DL, MVT::Other, Chain);
01015 }
01016 
01017 // CC is a comparison that will be implemented using an integer or
01018 // floating-point comparison.  Return the condition code mask for
01019 // a branch on true.  In the integer case, CCMASK_CMP_UO is set for
01020 // unsigned comparisons and clear for signed ones.  In the floating-point
01021 // case, CCMASK_CMP_UO has its normal mask meaning (unordered).
01022 static unsigned CCMaskForCondCode(ISD::CondCode CC) {
01023 #define CONV(X) \
01024   case ISD::SET##X: return SystemZ::CCMASK_CMP_##X; \
01025   case ISD::SETO##X: return SystemZ::CCMASK_CMP_##X; \
01026   case ISD::SETU##X: return SystemZ::CCMASK_CMP_UO | SystemZ::CCMASK_CMP_##X
01027 
01028   switch (CC) {
01029   default:
01030     llvm_unreachable("Invalid integer condition!");
01031 
01032   CONV(EQ);
01033   CONV(NE);
01034   CONV(GT);
01035   CONV(GE);
01036   CONV(LT);
01037   CONV(LE);
01038 
01039   case ISD::SETO:  return SystemZ::CCMASK_CMP_O;
01040   case ISD::SETUO: return SystemZ::CCMASK_CMP_UO;
01041   }
01042 #undef CONV
01043 }
01044 
01045 // Return a sequence for getting a 1 from an IPM result when CC has a
01046 // value in CCMask and a 0 when CC has a value in CCValid & ~CCMask.
01047 // The handling of CC values outside CCValid doesn't matter.
01048 static IPMConversion getIPMConversion(unsigned CCValid, unsigned CCMask) {
01049   // Deal with cases where the result can be taken directly from a bit
01050   // of the IPM result.
01051   if (CCMask == (CCValid & (SystemZ::CCMASK_1 | SystemZ::CCMASK_3)))
01052     return IPMConversion(0, 0, SystemZ::IPM_CC);
01053   if (CCMask == (CCValid & (SystemZ::CCMASK_2 | SystemZ::CCMASK_3)))
01054     return IPMConversion(0, 0, SystemZ::IPM_CC + 1);
01055 
01056   // Deal with cases where we can add a value to force the sign bit
01057   // to contain the right value.  Putting the bit in 31 means we can
01058   // use SRL rather than RISBG(L), and also makes it easier to get a
01059   // 0/-1 value, so it has priority over the other tests below.
01060   //
01061   // These sequences rely on the fact that the upper two bits of the
01062   // IPM result are zero.
01063   uint64_t TopBit = uint64_t(1) << 31;
01064   if (CCMask == (CCValid & SystemZ::CCMASK_0))
01065     return IPMConversion(0, -(1 << SystemZ::IPM_CC), 31);
01066   if (CCMask == (CCValid & (SystemZ::CCMASK_0 | SystemZ::CCMASK_1)))
01067     return IPMConversion(0, -(2 << SystemZ::IPM_CC), 31);
01068   if (CCMask == (CCValid & (SystemZ::CCMASK_0
01069                             | SystemZ::CCMASK_1
01070                             | SystemZ::CCMASK_2)))
01071     return IPMConversion(0, -(3 << SystemZ::IPM_CC), 31);
01072   if (CCMask == (CCValid & SystemZ::CCMASK_3))
01073     return IPMConversion(0, TopBit - (3 << SystemZ::IPM_CC), 31);
01074   if (CCMask == (CCValid & (SystemZ::CCMASK_1
01075                             | SystemZ::CCMASK_2
01076                             | SystemZ::CCMASK_3)))
01077     return IPMConversion(0, TopBit - (1 << SystemZ::IPM_CC), 31);
01078 
01079   // Next try inverting the value and testing a bit.  0/1 could be
01080   // handled this way too, but we dealt with that case above.
01081   if (CCMask == (CCValid & (SystemZ::CCMASK_0 | SystemZ::CCMASK_2)))
01082     return IPMConversion(-1, 0, SystemZ::IPM_CC);
01083 
01084   // Handle cases where adding a value forces a non-sign bit to contain
01085   // the right value.
01086   if (CCMask == (CCValid & (SystemZ::CCMASK_1 | SystemZ::CCMASK_2)))
01087     return IPMConversion(0, 1 << SystemZ::IPM_CC, SystemZ::IPM_CC + 1);
01088   if (CCMask == (CCValid & (SystemZ::CCMASK_0 | SystemZ::CCMASK_3)))
01089     return IPMConversion(0, -(1 << SystemZ::IPM_CC), SystemZ::IPM_CC + 1);
01090 
01091   // The remaining cases are 1, 2, 0/1/3 and 0/2/3.  All these are
01092   // can be done by inverting the low CC bit and applying one of the
01093   // sign-based extractions above.
01094   if (CCMask == (CCValid & SystemZ::CCMASK_1))
01095     return IPMConversion(1 << SystemZ::IPM_CC, -(1 << SystemZ::IPM_CC), 31);
01096   if (CCMask == (CCValid & SystemZ::CCMASK_2))
01097     return IPMConversion(1 << SystemZ::IPM_CC,
01098                          TopBit - (3 << SystemZ::IPM_CC), 31);
01099   if (CCMask == (CCValid & (SystemZ::CCMASK_0
01100                             | SystemZ::CCMASK_1
01101                             | SystemZ::CCMASK_3)))
01102     return IPMConversion(1 << SystemZ::IPM_CC, -(3 << SystemZ::IPM_CC), 31);
01103   if (CCMask == (CCValid & (SystemZ::CCMASK_0
01104                             | SystemZ::CCMASK_2
01105                             | SystemZ::CCMASK_3)))
01106     return IPMConversion(1 << SystemZ::IPM_CC,
01107                          TopBit - (1 << SystemZ::IPM_CC), 31);
01108 
01109   llvm_unreachable("Unexpected CC combination");
01110 }
01111 
01112 // If C can be converted to a comparison against zero, adjust the operands
01113 // as necessary.
01114 static void adjustZeroCmp(SelectionDAG &DAG, Comparison &C) {
01115   if (C.ICmpType == SystemZICMP::UnsignedOnly)
01116     return;
01117 
01118   auto *ConstOp1 = dyn_cast<ConstantSDNode>(C.Op1.getNode());
01119   if (!ConstOp1)
01120     return;
01121 
01122   int64_t Value = ConstOp1->getSExtValue();
01123   if ((Value == -1 && C.CCMask == SystemZ::CCMASK_CMP_GT) ||
01124       (Value == -1 && C.CCMask == SystemZ::CCMASK_CMP_LE) ||
01125       (Value == 1 && C.CCMask == SystemZ::CCMASK_CMP_LT) ||
01126       (Value == 1 && C.CCMask == SystemZ::CCMASK_CMP_GE)) {
01127     C.CCMask ^= SystemZ::CCMASK_CMP_EQ;
01128     C.Op1 = DAG.getConstant(0, C.Op1.getValueType());
01129   }
01130 }
01131 
01132 // If a comparison described by C is suitable for CLI(Y), CHHSI or CLHHSI,
01133 // adjust the operands as necessary.
01134 static void adjustSubwordCmp(SelectionDAG &DAG, Comparison &C) {
01135   // For us to make any changes, it must a comparison between a single-use
01136   // load and a constant.
01137   if (!C.Op0.hasOneUse() ||
01138       C.Op0.getOpcode() != ISD::LOAD ||
01139       C.Op1.getOpcode() != ISD::Constant)
01140     return;
01141 
01142   // We must have an 8- or 16-bit load.
01143   auto *Load = cast<LoadSDNode>(C.Op0);
01144   unsigned NumBits = Load->getMemoryVT().getStoreSizeInBits();
01145   if (NumBits != 8 && NumBits != 16)
01146     return;
01147 
01148   // The load must be an extending one and the constant must be within the
01149   // range of the unextended value.
01150   auto *ConstOp1 = cast<ConstantSDNode>(C.Op1);
01151   uint64_t Value = ConstOp1->getZExtValue();
01152   uint64_t Mask = (1 << NumBits) - 1;
01153   if (Load->getExtensionType() == ISD::SEXTLOAD) {
01154     // Make sure that ConstOp1 is in range of C.Op0.
01155     int64_t SignedValue = ConstOp1->getSExtValue();
01156     if (uint64_t(SignedValue) + (uint64_t(1) << (NumBits - 1)) > Mask)
01157       return;
01158     if (C.ICmpType != SystemZICMP::SignedOnly) {
01159       // Unsigned comparison between two sign-extended values is equivalent
01160       // to unsigned comparison between two zero-extended values.
01161       Value &= Mask;
01162     } else if (NumBits == 8) {
01163       // Try to treat the comparison as unsigned, so that we can use CLI.
01164       // Adjust CCMask and Value as necessary.
01165       if (Value == 0 && C.CCMask == SystemZ::CCMASK_CMP_LT)
01166         // Test whether the high bit of the byte is set.
01167         Value = 127, C.CCMask = SystemZ::CCMASK_CMP_GT;
01168       else if (Value == 0 && C.CCMask == SystemZ::CCMASK_CMP_GE)
01169         // Test whether the high bit of the byte is clear.
01170         Value = 128, C.CCMask = SystemZ::CCMASK_CMP_LT;
01171       else
01172         // No instruction exists for this combination.
01173         return;
01174       C.ICmpType = SystemZICMP::UnsignedOnly;
01175     }
01176   } else if (Load->getExtensionType() == ISD::ZEXTLOAD) {
01177     if (Value > Mask)
01178       return;
01179     assert(C.ICmpType == SystemZICMP::Any &&
01180            "Signedness shouldn't matter here.");
01181   } else
01182     return;
01183 
01184   // Make sure that the first operand is an i32 of the right extension type.
01185   ISD::LoadExtType ExtType = (C.ICmpType == SystemZICMP::SignedOnly ?
01186                               ISD::SEXTLOAD :
01187                               ISD::ZEXTLOAD);
01188   if (C.Op0.getValueType() != MVT::i32 ||
01189       Load->getExtensionType() != ExtType)
01190     C.Op0 = DAG.getExtLoad(ExtType, SDLoc(Load), MVT::i32,
01191                            Load->getChain(), Load->getBasePtr(),
01192                            Load->getPointerInfo(), Load->getMemoryVT(),
01193                            Load->isVolatile(), Load->isNonTemporal(),
01194                            Load->getAlignment());
01195 
01196   // Make sure that the second operand is an i32 with the right value.
01197   if (C.Op1.getValueType() != MVT::i32 ||
01198       Value != ConstOp1->getZExtValue())
01199     C.Op1 = DAG.getConstant(Value, MVT::i32);
01200 }
01201 
01202 // Return true if Op is either an unextended load, or a load suitable
01203 // for integer register-memory comparisons of type ICmpType.
01204 static bool isNaturalMemoryOperand(SDValue Op, unsigned ICmpType) {
01205   auto *Load = dyn_cast<LoadSDNode>(Op.getNode());
01206   if (Load) {
01207     // There are no instructions to compare a register with a memory byte.
01208     if (Load->getMemoryVT() == MVT::i8)
01209       return false;
01210     // Otherwise decide on extension type.
01211     switch (Load->getExtensionType()) {
01212     case ISD::NON_EXTLOAD:
01213       return true;
01214     case ISD::SEXTLOAD:
01215       return ICmpType != SystemZICMP::UnsignedOnly;
01216     case ISD::ZEXTLOAD:
01217       return ICmpType != SystemZICMP::SignedOnly;
01218     default:
01219       break;
01220     }
01221   }
01222   return false;
01223 }
01224 
01225 // Return true if it is better to swap the operands of C.
01226 static bool shouldSwapCmpOperands(const Comparison &C) {
01227   // Leave f128 comparisons alone, since they have no memory forms.
01228   if (C.Op0.getValueType() == MVT::f128)
01229     return false;
01230 
01231   // Always keep a floating-point constant second, since comparisons with
01232   // zero can use LOAD TEST and comparisons with other constants make a
01233   // natural memory operand.
01234   if (isa<ConstantFPSDNode>(C.Op1))
01235     return false;
01236 
01237   // Never swap comparisons with zero since there are many ways to optimize
01238   // those later.
01239   auto *ConstOp1 = dyn_cast<ConstantSDNode>(C.Op1);
01240   if (ConstOp1 && ConstOp1->getZExtValue() == 0)
01241     return false;
01242 
01243   // Also keep natural memory operands second if the loaded value is
01244   // only used here.  Several comparisons have memory forms.
01245   if (isNaturalMemoryOperand(C.Op1, C.ICmpType) && C.Op1.hasOneUse())
01246     return false;
01247 
01248   // Look for cases where Cmp0 is a single-use load and Cmp1 isn't.
01249   // In that case we generally prefer the memory to be second.
01250   if (isNaturalMemoryOperand(C.Op0, C.ICmpType) && C.Op0.hasOneUse()) {
01251     // The only exceptions are when the second operand is a constant and
01252     // we can use things like CHHSI.
01253     if (!ConstOp1)
01254       return true;
01255     // The unsigned memory-immediate instructions can handle 16-bit
01256     // unsigned integers.
01257     if (C.ICmpType != SystemZICMP::SignedOnly &&
01258         isUInt<16>(ConstOp1->getZExtValue()))
01259       return false;
01260     // The signed memory-immediate instructions can handle 16-bit
01261     // signed integers.
01262     if (C.ICmpType != SystemZICMP::UnsignedOnly &&
01263         isInt<16>(ConstOp1->getSExtValue()))
01264       return false;
01265     return true;
01266   }
01267 
01268   // Try to promote the use of CGFR and CLGFR.
01269   unsigned Opcode0 = C.Op0.getOpcode();
01270   if (C.ICmpType != SystemZICMP::UnsignedOnly && Opcode0 == ISD::SIGN_EXTEND)
01271     return true;
01272   if (C.ICmpType != SystemZICMP::SignedOnly && Opcode0 == ISD::ZERO_EXTEND)
01273     return true;
01274   if (C.ICmpType != SystemZICMP::SignedOnly &&
01275       Opcode0 == ISD::AND &&
01276       C.Op0.getOperand(1).getOpcode() == ISD::Constant &&
01277       cast<ConstantSDNode>(C.Op0.getOperand(1))->getZExtValue() == 0xffffffff)
01278     return true;
01279 
01280   return false;
01281 }
01282 
01283 // Return a version of comparison CC mask CCMask in which the LT and GT
01284 // actions are swapped.
01285 static unsigned reverseCCMask(unsigned CCMask) {
01286   return ((CCMask & SystemZ::CCMASK_CMP_EQ) |
01287           (CCMask & SystemZ::CCMASK_CMP_GT ? SystemZ::CCMASK_CMP_LT : 0) |
01288           (CCMask & SystemZ::CCMASK_CMP_LT ? SystemZ::CCMASK_CMP_GT : 0) |
01289           (CCMask & SystemZ::CCMASK_CMP_UO));
01290 }
01291 
01292 // Check whether C tests for equality between X and Y and whether X - Y
01293 // or Y - X is also computed.  In that case it's better to compare the
01294 // result of the subtraction against zero.
01295 static void adjustForSubtraction(SelectionDAG &DAG, Comparison &C) {
01296   if (C.CCMask == SystemZ::CCMASK_CMP_EQ ||
01297       C.CCMask == SystemZ::CCMASK_CMP_NE) {
01298     for (auto I = C.Op0->use_begin(), E = C.Op0->use_end(); I != E; ++I) {
01299       SDNode *N = *I;
01300       if (N->getOpcode() == ISD::SUB &&
01301           ((N->getOperand(0) == C.Op0 && N->getOperand(1) == C.Op1) ||
01302            (N->getOperand(0) == C.Op1 && N->getOperand(1) == C.Op0))) {
01303         C.Op0 = SDValue(N, 0);
01304         C.Op1 = DAG.getConstant(0, N->getValueType(0));
01305         return;
01306       }
01307     }
01308   }
01309 }
01310 
01311 // Check whether C compares a floating-point value with zero and if that
01312 // floating-point value is also negated.  In this case we can use the
01313 // negation to set CC, so avoiding separate LOAD AND TEST and
01314 // LOAD (NEGATIVE/COMPLEMENT) instructions.
01315 static void adjustForFNeg(Comparison &C) {
01316   auto *C1 = dyn_cast<ConstantFPSDNode>(C.Op1);
01317   if (C1 && C1->isZero()) {
01318     for (auto I = C.Op0->use_begin(), E = C.Op0->use_end(); I != E; ++I) {
01319       SDNode *N = *I;
01320       if (N->getOpcode() == ISD::FNEG) {
01321         C.Op0 = SDValue(N, 0);
01322         C.CCMask = reverseCCMask(C.CCMask);
01323         return;
01324       }
01325     }
01326   }
01327 }
01328 
01329 // Check whether C compares (shl X, 32) with 0 and whether X is
01330 // also sign-extended.  In that case it is better to test the result
01331 // of the sign extension using LTGFR.
01332 //
01333 // This case is important because InstCombine transforms a comparison
01334 // with (sext (trunc X)) into a comparison with (shl X, 32).
01335 static void adjustForLTGFR(Comparison &C) {
01336   // Check for a comparison between (shl X, 32) and 0.
01337   if (C.Op0.getOpcode() == ISD::SHL &&
01338       C.Op0.getValueType() == MVT::i64 &&
01339       C.Op1.getOpcode() == ISD::Constant &&
01340       cast<ConstantSDNode>(C.Op1)->getZExtValue() == 0) {
01341     auto *C1 = dyn_cast<ConstantSDNode>(C.Op0.getOperand(1));
01342     if (C1 && C1->getZExtValue() == 32) {
01343       SDValue ShlOp0 = C.Op0.getOperand(0);
01344       // See whether X has any SIGN_EXTEND_INREG uses.
01345       for (auto I = ShlOp0->use_begin(), E = ShlOp0->use_end(); I != E; ++I) {
01346         SDNode *N = *I;
01347         if (N->getOpcode() == ISD::SIGN_EXTEND_INREG &&
01348             cast<VTSDNode>(N->getOperand(1))->getVT() == MVT::i32) {
01349           C.Op0 = SDValue(N, 0);
01350           return;
01351         }
01352       }
01353     }
01354   }
01355 }
01356 
01357 // If C compares the truncation of an extending load, try to compare
01358 // the untruncated value instead.  This exposes more opportunities to
01359 // reuse CC.
01360 static void adjustICmpTruncate(SelectionDAG &DAG, Comparison &C) {
01361   if (C.Op0.getOpcode() == ISD::TRUNCATE &&
01362       C.Op0.getOperand(0).getOpcode() == ISD::LOAD &&
01363       C.Op1.getOpcode() == ISD::Constant &&
01364       cast<ConstantSDNode>(C.Op1)->getZExtValue() == 0) {
01365     auto *L = cast<LoadSDNode>(C.Op0.getOperand(0));
01366     if (L->getMemoryVT().getStoreSizeInBits()
01367         <= C.Op0.getValueType().getSizeInBits()) {
01368       unsigned Type = L->getExtensionType();
01369       if ((Type == ISD::ZEXTLOAD && C.ICmpType != SystemZICMP::SignedOnly) ||
01370           (Type == ISD::SEXTLOAD && C.ICmpType != SystemZICMP::UnsignedOnly)) {
01371         C.Op0 = C.Op0.getOperand(0);
01372         C.Op1 = DAG.getConstant(0, C.Op0.getValueType());
01373       }
01374     }
01375   }
01376 }
01377 
01378 // Return true if shift operation N has an in-range constant shift value.
01379 // Store it in ShiftVal if so.
01380 static bool isSimpleShift(SDValue N, unsigned &ShiftVal) {
01381   auto *Shift = dyn_cast<ConstantSDNode>(N.getOperand(1));
01382   if (!Shift)
01383     return false;
01384 
01385   uint64_t Amount = Shift->getZExtValue();
01386   if (Amount >= N.getValueType().getSizeInBits())
01387     return false;
01388 
01389   ShiftVal = Amount;
01390   return true;
01391 }
01392 
01393 // Check whether an AND with Mask is suitable for a TEST UNDER MASK
01394 // instruction and whether the CC value is descriptive enough to handle
01395 // a comparison of type Opcode between the AND result and CmpVal.
01396 // CCMask says which comparison result is being tested and BitSize is
01397 // the number of bits in the operands.  If TEST UNDER MASK can be used,
01398 // return the corresponding CC mask, otherwise return 0.
01399 static unsigned getTestUnderMaskCond(unsigned BitSize, unsigned CCMask,
01400                                      uint64_t Mask, uint64_t CmpVal,
01401                                      unsigned ICmpType) {
01402   assert(Mask != 0 && "ANDs with zero should have been removed by now");
01403 
01404   // Check whether the mask is suitable for TMHH, TMHL, TMLH or TMLL.
01405   if (!SystemZ::isImmLL(Mask) && !SystemZ::isImmLH(Mask) &&
01406       !SystemZ::isImmHL(Mask) && !SystemZ::isImmHH(Mask))
01407     return 0;
01408 
01409   // Work out the masks for the lowest and highest bits.
01410   unsigned HighShift = 63 - countLeadingZeros(Mask);
01411   uint64_t High = uint64_t(1) << HighShift;
01412   uint64_t Low = uint64_t(1) << countTrailingZeros(Mask);
01413 
01414   // Signed ordered comparisons are effectively unsigned if the sign
01415   // bit is dropped.
01416   bool EffectivelyUnsigned = (ICmpType != SystemZICMP::SignedOnly);
01417 
01418   // Check for equality comparisons with 0, or the equivalent.
01419   if (CmpVal == 0) {
01420     if (CCMask == SystemZ::CCMASK_CMP_EQ)
01421       return SystemZ::CCMASK_TM_ALL_0;
01422     if (CCMask == SystemZ::CCMASK_CMP_NE)
01423       return SystemZ::CCMASK_TM_SOME_1;
01424   }
01425   if (EffectivelyUnsigned && CmpVal <= Low) {
01426     if (CCMask == SystemZ::CCMASK_CMP_LT)
01427       return SystemZ::CCMASK_TM_ALL_0;
01428     if (CCMask == SystemZ::CCMASK_CMP_GE)
01429       return SystemZ::CCMASK_TM_SOME_1;
01430   }
01431   if (EffectivelyUnsigned && CmpVal < Low) {
01432     if (CCMask == SystemZ::CCMASK_CMP_LE)
01433       return SystemZ::CCMASK_TM_ALL_0;
01434     if (CCMask == SystemZ::CCMASK_CMP_GT)
01435       return SystemZ::CCMASK_TM_SOME_1;
01436   }
01437 
01438   // Check for equality comparisons with the mask, or the equivalent.
01439   if (CmpVal == Mask) {
01440     if (CCMask == SystemZ::CCMASK_CMP_EQ)
01441       return SystemZ::CCMASK_TM_ALL_1;
01442     if (CCMask == SystemZ::CCMASK_CMP_NE)
01443       return SystemZ::CCMASK_TM_SOME_0;
01444   }
01445   if (EffectivelyUnsigned && CmpVal >= Mask - Low && CmpVal < Mask) {
01446     if (CCMask == SystemZ::CCMASK_CMP_GT)
01447       return SystemZ::CCMASK_TM_ALL_1;
01448     if (CCMask == SystemZ::CCMASK_CMP_LE)
01449       return SystemZ::CCMASK_TM_SOME_0;
01450   }
01451   if (EffectivelyUnsigned && CmpVal > Mask - Low && CmpVal <= Mask) {
01452     if (CCMask == SystemZ::CCMASK_CMP_GE)
01453       return SystemZ::CCMASK_TM_ALL_1;
01454     if (CCMask == SystemZ::CCMASK_CMP_LT)
01455       return SystemZ::CCMASK_TM_SOME_0;
01456   }
01457 
01458   // Check for ordered comparisons with the top bit.
01459   if (EffectivelyUnsigned && CmpVal >= Mask - High && CmpVal < High) {
01460     if (CCMask == SystemZ::CCMASK_CMP_LE)
01461       return SystemZ::CCMASK_TM_MSB_0;
01462     if (CCMask == SystemZ::CCMASK_CMP_GT)
01463       return SystemZ::CCMASK_TM_MSB_1;
01464   }
01465   if (EffectivelyUnsigned && CmpVal > Mask - High && CmpVal <= High) {
01466     if (CCMask == SystemZ::CCMASK_CMP_LT)
01467       return SystemZ::CCMASK_TM_MSB_0;
01468     if (CCMask == SystemZ::CCMASK_CMP_GE)
01469       return SystemZ::CCMASK_TM_MSB_1;
01470   }
01471 
01472   // If there are just two bits, we can do equality checks for Low and High
01473   // as well.
01474   if (Mask == Low + High) {
01475     if (CCMask == SystemZ::CCMASK_CMP_EQ && CmpVal == Low)
01476       return SystemZ::CCMASK_TM_MIXED_MSB_0;
01477     if (CCMask == SystemZ::CCMASK_CMP_NE && CmpVal == Low)
01478       return SystemZ::CCMASK_TM_MIXED_MSB_0 ^ SystemZ::CCMASK_ANY;
01479     if (CCMask == SystemZ::CCMASK_CMP_EQ && CmpVal == High)
01480       return SystemZ::CCMASK_TM_MIXED_MSB_1;
01481     if (CCMask == SystemZ::CCMASK_CMP_NE && CmpVal == High)
01482       return SystemZ::CCMASK_TM_MIXED_MSB_1 ^ SystemZ::CCMASK_ANY;
01483   }
01484 
01485   // Looks like we've exhausted our options.
01486   return 0;
01487 }
01488 
01489 // See whether C can be implemented as a TEST UNDER MASK instruction.
01490 // Update the arguments with the TM version if so.
01491 static void adjustForTestUnderMask(SelectionDAG &DAG, Comparison &C) {
01492   // Check that we have a comparison with a constant.
01493   auto *ConstOp1 = dyn_cast<ConstantSDNode>(C.Op1);
01494   if (!ConstOp1)
01495     return;
01496   uint64_t CmpVal = ConstOp1->getZExtValue();
01497 
01498   // Check whether the nonconstant input is an AND with a constant mask.
01499   Comparison NewC(C);
01500   uint64_t MaskVal;
01501   ConstantSDNode *Mask = nullptr;
01502   if (C.Op0.getOpcode() == ISD::AND) {
01503     NewC.Op0 = C.Op0.getOperand(0);
01504     NewC.Op1 = C.Op0.getOperand(1);
01505     Mask = dyn_cast<ConstantSDNode>(NewC.Op1);
01506     if (!Mask)
01507       return;
01508     MaskVal = Mask->getZExtValue();
01509   } else {
01510     // There is no instruction to compare with a 64-bit immediate
01511     // so use TMHH instead if possible.  We need an unsigned ordered
01512     // comparison with an i64 immediate.
01513     if (NewC.Op0.getValueType() != MVT::i64 ||
01514         NewC.CCMask == SystemZ::CCMASK_CMP_EQ ||
01515         NewC.CCMask == SystemZ::CCMASK_CMP_NE ||
01516         NewC.ICmpType == SystemZICMP::SignedOnly)
01517       return;
01518     // Convert LE and GT comparisons into LT and GE.
01519     if (NewC.CCMask == SystemZ::CCMASK_CMP_LE ||
01520         NewC.CCMask == SystemZ::CCMASK_CMP_GT) {
01521       if (CmpVal == uint64_t(-1))
01522         return;
01523       CmpVal += 1;
01524       NewC.CCMask ^= SystemZ::CCMASK_CMP_EQ;
01525     }
01526     // If the low N bits of Op1 are zero than the low N bits of Op0 can
01527     // be masked off without changing the result.
01528     MaskVal = -(CmpVal & -CmpVal);
01529     NewC.ICmpType = SystemZICMP::UnsignedOnly;
01530   }
01531 
01532   // Check whether the combination of mask, comparison value and comparison
01533   // type are suitable.
01534   unsigned BitSize = NewC.Op0.getValueType().getSizeInBits();
01535   unsigned NewCCMask, ShiftVal;
01536   if (NewC.ICmpType != SystemZICMP::SignedOnly &&
01537       NewC.Op0.getOpcode() == ISD::SHL &&
01538       isSimpleShift(NewC.Op0, ShiftVal) &&
01539       (NewCCMask = getTestUnderMaskCond(BitSize, NewC.CCMask,
01540                                         MaskVal >> ShiftVal,
01541                                         CmpVal >> ShiftVal,
01542                                         SystemZICMP::Any))) {
01543     NewC.Op0 = NewC.Op0.getOperand(0);
01544     MaskVal >>= ShiftVal;
01545   } else if (NewC.ICmpType != SystemZICMP::SignedOnly &&
01546              NewC.Op0.getOpcode() == ISD::SRL &&
01547              isSimpleShift(NewC.Op0, ShiftVal) &&
01548              (NewCCMask = getTestUnderMaskCond(BitSize, NewC.CCMask,
01549                                                MaskVal << ShiftVal,
01550                                                CmpVal << ShiftVal,
01551                                                SystemZICMP::UnsignedOnly))) {
01552     NewC.Op0 = NewC.Op0.getOperand(0);
01553     MaskVal <<= ShiftVal;
01554   } else {
01555     NewCCMask = getTestUnderMaskCond(BitSize, NewC.CCMask, MaskVal, CmpVal,
01556                                      NewC.ICmpType);
01557     if (!NewCCMask)
01558       return;
01559   }
01560 
01561   // Go ahead and make the change.
01562   C.Opcode = SystemZISD::TM;
01563   C.Op0 = NewC.Op0;
01564   if (Mask && Mask->getZExtValue() == MaskVal)
01565     C.Op1 = SDValue(Mask, 0);
01566   else
01567     C.Op1 = DAG.getConstant(MaskVal, C.Op0.getValueType());
01568   C.CCValid = SystemZ::CCMASK_TM;
01569   C.CCMask = NewCCMask;
01570 }
01571 
01572 // Decide how to implement a comparison of type Cond between CmpOp0 with CmpOp1.
01573 static Comparison getCmp(SelectionDAG &DAG, SDValue CmpOp0, SDValue CmpOp1,
01574                          ISD::CondCode Cond) {
01575   Comparison C(CmpOp0, CmpOp1);
01576   C.CCMask = CCMaskForCondCode(Cond);
01577   if (C.Op0.getValueType().isFloatingPoint()) {
01578     C.CCValid = SystemZ::CCMASK_FCMP;
01579     C.Opcode = SystemZISD::FCMP;
01580     adjustForFNeg(C);
01581   } else {
01582     C.CCValid = SystemZ::CCMASK_ICMP;
01583     C.Opcode = SystemZISD::ICMP;
01584     // Choose the type of comparison.  Equality and inequality tests can
01585     // use either signed or unsigned comparisons.  The choice also doesn't
01586     // matter if both sign bits are known to be clear.  In those cases we
01587     // want to give the main isel code the freedom to choose whichever
01588     // form fits best.
01589     if (C.CCMask == SystemZ::CCMASK_CMP_EQ ||
01590         C.CCMask == SystemZ::CCMASK_CMP_NE ||
01591         (DAG.SignBitIsZero(C.Op0) && DAG.SignBitIsZero(C.Op1)))
01592       C.ICmpType = SystemZICMP::Any;
01593     else if (C.CCMask & SystemZ::CCMASK_CMP_UO)
01594       C.ICmpType = SystemZICMP::UnsignedOnly;
01595     else
01596       C.ICmpType = SystemZICMP::SignedOnly;
01597     C.CCMask &= ~SystemZ::CCMASK_CMP_UO;
01598     adjustZeroCmp(DAG, C);
01599     adjustSubwordCmp(DAG, C);
01600     adjustForSubtraction(DAG, C);
01601     adjustForLTGFR(C);
01602     adjustICmpTruncate(DAG, C);
01603   }
01604 
01605   if (shouldSwapCmpOperands(C)) {
01606     std::swap(C.Op0, C.Op1);
01607     C.CCMask = reverseCCMask(C.CCMask);
01608   }
01609 
01610   adjustForTestUnderMask(DAG, C);
01611   return C;
01612 }
01613 
01614 // Emit the comparison instruction described by C.
01615 static SDValue emitCmp(SelectionDAG &DAG, SDLoc DL, Comparison &C) {
01616   if (C.Opcode == SystemZISD::ICMP)
01617     return DAG.getNode(SystemZISD::ICMP, DL, MVT::Glue, C.Op0, C.Op1,
01618                        DAG.getConstant(C.ICmpType, MVT::i32));
01619   if (C.Opcode == SystemZISD::TM) {
01620     bool RegisterOnly = (bool(C.CCMask & SystemZ::CCMASK_TM_MIXED_MSB_0) !=
01621                          bool(C.CCMask & SystemZ::CCMASK_TM_MIXED_MSB_1));
01622     return DAG.getNode(SystemZISD::TM, DL, MVT::Glue, C.Op0, C.Op1,
01623                        DAG.getConstant(RegisterOnly, MVT::i32));
01624   }
01625   return DAG.getNode(C.Opcode, DL, MVT::Glue, C.Op0, C.Op1);
01626 }
01627 
01628 // Implement a 32-bit *MUL_LOHI operation by extending both operands to
01629 // 64 bits.  Extend is the extension type to use.  Store the high part
01630 // in Hi and the low part in Lo.
01631 static void lowerMUL_LOHI32(SelectionDAG &DAG, SDLoc DL,
01632                             unsigned Extend, SDValue Op0, SDValue Op1,
01633                             SDValue &Hi, SDValue &Lo) {
01634   Op0 = DAG.getNode(Extend, DL, MVT::i64, Op0);
01635   Op1 = DAG.getNode(Extend, DL, MVT::i64, Op1);
01636   SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, Op0, Op1);
01637   Hi = DAG.getNode(ISD::SRL, DL, MVT::i64, Mul, DAG.getConstant(32, MVT::i64));
01638   Hi = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Hi);
01639   Lo = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mul);
01640 }
01641 
01642 // Lower a binary operation that produces two VT results, one in each
01643 // half of a GR128 pair.  Op0 and Op1 are the VT operands to the operation,
01644 // Extend extends Op0 to a GR128, and Opcode performs the GR128 operation
01645 // on the extended Op0 and (unextended) Op1.  Store the even register result
01646 // in Even and the odd register result in Odd.
01647 static void lowerGR128Binary(SelectionDAG &DAG, SDLoc DL, EVT VT,
01648                              unsigned Extend, unsigned Opcode,
01649                              SDValue Op0, SDValue Op1,
01650                              SDValue &Even, SDValue &Odd) {
01651   SDNode *In128 = DAG.getMachineNode(Extend, DL, MVT::Untyped, Op0);
01652   SDValue Result = DAG.getNode(Opcode, DL, MVT::Untyped,
01653                                SDValue(In128, 0), Op1);
01654   bool Is32Bit = is32Bit(VT);
01655   Even = DAG.getTargetExtractSubreg(SystemZ::even128(Is32Bit), DL, VT, Result);
01656   Odd = DAG.getTargetExtractSubreg(SystemZ::odd128(Is32Bit), DL, VT, Result);
01657 }
01658 
01659 // Return an i32 value that is 1 if the CC value produced by Glue is
01660 // in the mask CCMask and 0 otherwise.  CC is known to have a value
01661 // in CCValid, so other values can be ignored.
01662 static SDValue emitSETCC(SelectionDAG &DAG, SDLoc DL, SDValue Glue,
01663                          unsigned CCValid, unsigned CCMask) {
01664   IPMConversion Conversion = getIPMConversion(CCValid, CCMask);
01665   SDValue Result = DAG.getNode(SystemZISD::IPM, DL, MVT::i32, Glue);
01666 
01667   if (Conversion.XORValue)
01668     Result = DAG.getNode(ISD::XOR, DL, MVT::i32, Result,
01669                          DAG.getConstant(Conversion.XORValue, MVT::i32));
01670 
01671   if (Conversion.AddValue)
01672     Result = DAG.getNode(ISD::ADD, DL, MVT::i32, Result,
01673                          DAG.getConstant(Conversion.AddValue, MVT::i32));
01674 
01675   // The SHR/AND sequence should get optimized to an RISBG.
01676   Result = DAG.getNode(ISD::SRL, DL, MVT::i32, Result,
01677                        DAG.getConstant(Conversion.Bit, MVT::i32));
01678   if (Conversion.Bit != 31)
01679     Result = DAG.getNode(ISD::AND, DL, MVT::i32, Result,
01680                          DAG.getConstant(1, MVT::i32));
01681   return Result;
01682 }
01683 
01684 SDValue SystemZTargetLowering::lowerSETCC(SDValue Op,
01685                                           SelectionDAG &DAG) const {
01686   SDValue CmpOp0   = Op.getOperand(0);
01687   SDValue CmpOp1   = Op.getOperand(1);
01688   ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
01689   SDLoc DL(Op);
01690 
01691   Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC));
01692   SDValue Glue = emitCmp(DAG, DL, C);
01693   return emitSETCC(DAG, DL, Glue, C.CCValid, C.CCMask);
01694 }
01695 
01696 SDValue SystemZTargetLowering::lowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
01697   SDValue Chain    = Op.getOperand(0);
01698   ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
01699   SDValue CmpOp0   = Op.getOperand(2);
01700   SDValue CmpOp1   = Op.getOperand(3);
01701   SDValue Dest     = Op.getOperand(4);
01702   SDLoc DL(Op);
01703 
01704   Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC));
01705   SDValue Glue = emitCmp(DAG, DL, C);
01706   return DAG.getNode(SystemZISD::BR_CCMASK, DL, Op.getValueType(),
01707                      Chain, DAG.getConstant(C.CCValid, MVT::i32),
01708                      DAG.getConstant(C.CCMask, MVT::i32), Dest, Glue);
01709 }
01710 
01711 // Return true if Pos is CmpOp and Neg is the negative of CmpOp,
01712 // allowing Pos and Neg to be wider than CmpOp.
01713 static bool isAbsolute(SDValue CmpOp, SDValue Pos, SDValue Neg) {
01714   return (Neg.getOpcode() == ISD::SUB &&
01715           Neg.getOperand(0).getOpcode() == ISD::Constant &&
01716           cast<ConstantSDNode>(Neg.getOperand(0))->getZExtValue() == 0 &&
01717           Neg.getOperand(1) == Pos &&
01718           (Pos == CmpOp ||
01719            (Pos.getOpcode() == ISD::SIGN_EXTEND &&
01720             Pos.getOperand(0) == CmpOp)));
01721 }
01722 
01723 // Return the absolute or negative absolute of Op; IsNegative decides which.
01724 static SDValue getAbsolute(SelectionDAG &DAG, SDLoc DL, SDValue Op,
01725                            bool IsNegative) {
01726   Op = DAG.getNode(SystemZISD::IABS, DL, Op.getValueType(), Op);
01727   if (IsNegative)
01728     Op = DAG.getNode(ISD::SUB, DL, Op.getValueType(),
01729                      DAG.getConstant(0, Op.getValueType()), Op);
01730   return Op;
01731 }
01732 
01733 SDValue SystemZTargetLowering::lowerSELECT_CC(SDValue Op,
01734                                               SelectionDAG &DAG) const {
01735   SDValue CmpOp0   = Op.getOperand(0);
01736   SDValue CmpOp1   = Op.getOperand(1);
01737   SDValue TrueOp   = Op.getOperand(2);
01738   SDValue FalseOp  = Op.getOperand(3);
01739   ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
01740   SDLoc DL(Op);
01741 
01742   Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC));
01743 
01744   // Check for absolute and negative-absolute selections, including those
01745   // where the comparison value is sign-extended (for LPGFR and LNGFR).
01746   // This check supplements the one in DAGCombiner.
01747   if (C.Opcode == SystemZISD::ICMP &&
01748       C.CCMask != SystemZ::CCMASK_CMP_EQ &&
01749       C.CCMask != SystemZ::CCMASK_CMP_NE &&
01750       C.Op1.getOpcode() == ISD::Constant &&
01751       cast<ConstantSDNode>(C.Op1)->getZExtValue() == 0) {
01752     if (isAbsolute(C.Op0, TrueOp, FalseOp))
01753       return getAbsolute(DAG, DL, TrueOp, C.CCMask & SystemZ::CCMASK_CMP_LT);
01754     if (isAbsolute(C.Op0, FalseOp, TrueOp))
01755       return getAbsolute(DAG, DL, FalseOp, C.CCMask & SystemZ::CCMASK_CMP_GT);
01756   }
01757 
01758   SDValue Glue = emitCmp(DAG, DL, C);
01759 
01760   // Special case for handling -1/0 results.  The shifts we use here
01761   // should get optimized with the IPM conversion sequence.
01762   auto *TrueC = dyn_cast<ConstantSDNode>(TrueOp);
01763   auto *FalseC = dyn_cast<ConstantSDNode>(FalseOp);
01764   if (TrueC && FalseC) {
01765     int64_t TrueVal = TrueC->getSExtValue();
01766     int64_t FalseVal = FalseC->getSExtValue();
01767     if ((TrueVal == -1 && FalseVal == 0) || (TrueVal == 0 && FalseVal == -1)) {
01768       // Invert the condition if we want -1 on false.
01769       if (TrueVal == 0)
01770         C.CCMask ^= C.CCValid;
01771       SDValue Result = emitSETCC(DAG, DL, Glue, C.CCValid, C.CCMask);
01772       EVT VT = Op.getValueType();
01773       // Extend the result to VT.  Upper bits are ignored.
01774       if (!is32Bit(VT))
01775         Result = DAG.getNode(ISD::ANY_EXTEND, DL, VT, Result);
01776       // Sign-extend from the low bit.
01777       SDValue ShAmt = DAG.getConstant(VT.getSizeInBits() - 1, MVT::i32);
01778       SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, Result, ShAmt);
01779       return DAG.getNode(ISD::SRA, DL, VT, Shl, ShAmt);
01780     }
01781   }
01782 
01783   SmallVector<SDValue, 5> Ops;
01784   Ops.push_back(TrueOp);
01785   Ops.push_back(FalseOp);
01786   Ops.push_back(DAG.getConstant(C.CCValid, MVT::i32));
01787   Ops.push_back(DAG.getConstant(C.CCMask, MVT::i32));
01788   Ops.push_back(Glue);
01789 
01790   SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
01791   return DAG.getNode(SystemZISD::SELECT_CCMASK, DL, VTs, Ops);
01792 }
01793 
01794 SDValue SystemZTargetLowering::lowerGlobalAddress(GlobalAddressSDNode *Node,
01795                                                   SelectionDAG &DAG) const {
01796   SDLoc DL(Node);
01797   const GlobalValue *GV = Node->getGlobal();
01798   int64_t Offset = Node->getOffset();
01799   EVT PtrVT = getPointerTy();
01800   Reloc::Model RM = DAG.getTarget().getRelocationModel();
01801   CodeModel::Model CM = DAG.getTarget().getCodeModel();
01802 
01803   SDValue Result;
01804   if (Subtarget.isPC32DBLSymbol(GV, RM, CM)) {
01805     // Assign anchors at 1<<12 byte boundaries.
01806     uint64_t Anchor = Offset & ~uint64_t(0xfff);
01807     Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, Anchor);
01808     Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
01809 
01810     // The offset can be folded into the address if it is aligned to a halfword.
01811     Offset -= Anchor;
01812     if (Offset != 0 && (Offset & 1) == 0) {
01813       SDValue Full = DAG.getTargetGlobalAddress(GV, DL, PtrVT, Anchor + Offset);
01814       Result = DAG.getNode(SystemZISD::PCREL_OFFSET, DL, PtrVT, Full, Result);
01815       Offset = 0;
01816     }
01817   } else {
01818     Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, SystemZII::MO_GOT);
01819     Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
01820     Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
01821                          MachinePointerInfo::getGOT(), false, false, false, 0);
01822   }
01823 
01824   // If there was a non-zero offset that we didn't fold, create an explicit
01825   // addition for it.
01826   if (Offset != 0)
01827     Result = DAG.getNode(ISD::ADD, DL, PtrVT, Result,
01828                          DAG.getConstant(Offset, PtrVT));
01829 
01830   return Result;
01831 }
01832 
01833 SDValue SystemZTargetLowering::lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
01834                  SelectionDAG &DAG) const {
01835   SDLoc DL(Node);
01836   const GlobalValue *GV = Node->getGlobal();
01837   EVT PtrVT = getPointerTy();
01838   TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
01839 
01840   if (model != TLSModel::LocalExec)
01841     llvm_unreachable("only local-exec TLS mode supported");
01842 
01843   // The high part of the thread pointer is in access register 0.
01844   SDValue TPHi = DAG.getNode(SystemZISD::EXTRACT_ACCESS, DL, MVT::i32,
01845                              DAG.getConstant(0, MVT::i32));
01846   TPHi = DAG.getNode(ISD::ANY_EXTEND, DL, PtrVT, TPHi);
01847 
01848   // The low part of the thread pointer is in access register 1.
01849   SDValue TPLo = DAG.getNode(SystemZISD::EXTRACT_ACCESS, DL, MVT::i32,
01850                              DAG.getConstant(1, MVT::i32));
01851   TPLo = DAG.getNode(ISD::ZERO_EXTEND, DL, PtrVT, TPLo);
01852 
01853   // Merge them into a single 64-bit address.
01854   SDValue TPHiShifted = DAG.getNode(ISD::SHL, DL, PtrVT, TPHi,
01855             DAG.getConstant(32, PtrVT));
01856   SDValue TP = DAG.getNode(ISD::OR, DL, PtrVT, TPHiShifted, TPLo);
01857 
01858   // Get the offset of GA from the thread pointer.
01859   SystemZConstantPoolValue *CPV =
01860     SystemZConstantPoolValue::Create(GV, SystemZCP::NTPOFF);
01861 
01862   // Force the offset into the constant pool and load it from there.
01863   SDValue CPAddr = DAG.getConstantPool(CPV, PtrVT, 8);
01864   SDValue Offset = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(),
01865              CPAddr, MachinePointerInfo::getConstantPool(),
01866              false, false, false, 0);
01867 
01868   // Add the base and offset together.
01869   return DAG.getNode(ISD::ADD, DL, PtrVT, TP, Offset);
01870 }
01871 
01872 SDValue SystemZTargetLowering::lowerBlockAddress(BlockAddressSDNode *Node,
01873                                                  SelectionDAG &DAG) const {
01874   SDLoc DL(Node);
01875   const BlockAddress *BA = Node->getBlockAddress();
01876   int64_t Offset = Node->getOffset();
01877   EVT PtrVT = getPointerTy();
01878 
01879   SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT, Offset);
01880   Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
01881   return Result;
01882 }
01883 
01884 SDValue SystemZTargetLowering::lowerJumpTable(JumpTableSDNode *JT,
01885                                               SelectionDAG &DAG) const {
01886   SDLoc DL(JT);
01887   EVT PtrVT = getPointerTy();
01888   SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
01889 
01890   // Use LARL to load the address of the table.
01891   return DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
01892 }
01893 
01894 SDValue SystemZTargetLowering::lowerConstantPool(ConstantPoolSDNode *CP,
01895                                                  SelectionDAG &DAG) const {
01896   SDLoc DL(CP);
01897   EVT PtrVT = getPointerTy();
01898 
01899   SDValue Result;
01900   if (CP->isMachineConstantPoolEntry())
01901     Result = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
01902                CP->getAlignment());
01903   else
01904     Result = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
01905                CP->getAlignment(), CP->getOffset());
01906 
01907   // Use LARL to load the address of the constant pool entry.
01908   return DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
01909 }
01910 
01911 SDValue SystemZTargetLowering::lowerBITCAST(SDValue Op,
01912                                             SelectionDAG &DAG) const {
01913   SDLoc DL(Op);
01914   SDValue In = Op.getOperand(0);
01915   EVT InVT = In.getValueType();
01916   EVT ResVT = Op.getValueType();
01917 
01918   if (InVT == MVT::i32 && ResVT == MVT::f32) {
01919     SDValue In64;
01920     if (Subtarget.hasHighWord()) {
01921       SDNode *U64 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL,
01922                                        MVT::i64);
01923       In64 = DAG.getTargetInsertSubreg(SystemZ::subreg_h32, DL,
01924                                        MVT::i64, SDValue(U64, 0), In);
01925     } else {
01926       In64 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, In);
01927       In64 = DAG.getNode(ISD::SHL, DL, MVT::i64, In64,
01928                          DAG.getConstant(32, MVT::i64));
01929     }
01930     SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::f64, In64);
01931     return DAG.getTargetExtractSubreg(SystemZ::subreg_h32,
01932                                       DL, MVT::f32, Out64);
01933   }
01934   if (InVT == MVT::f32 && ResVT == MVT::i32) {
01935     SDNode *U64 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, MVT::f64);
01936     SDValue In64 = DAG.getTargetInsertSubreg(SystemZ::subreg_h32, DL,
01937                                              MVT::f64, SDValue(U64, 0), In);
01938     SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::i64, In64);
01939     if (Subtarget.hasHighWord())
01940       return DAG.getTargetExtractSubreg(SystemZ::subreg_h32, DL,
01941                                         MVT::i32, Out64);
01942     SDValue Shift = DAG.getNode(ISD::SRL, DL, MVT::i64, Out64,
01943                                 DAG.getConstant(32, MVT::i64));
01944     return DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Shift);
01945   }
01946   llvm_unreachable("Unexpected bitcast combination");
01947 }
01948 
01949 SDValue SystemZTargetLowering::lowerVASTART(SDValue Op,
01950                                             SelectionDAG &DAG) const {
01951   MachineFunction &MF = DAG.getMachineFunction();
01952   SystemZMachineFunctionInfo *FuncInfo =
01953     MF.getInfo<SystemZMachineFunctionInfo>();
01954   EVT PtrVT = getPointerTy();
01955 
01956   SDValue Chain   = Op.getOperand(0);
01957   SDValue Addr    = Op.getOperand(1);
01958   const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
01959   SDLoc DL(Op);
01960 
01961   // The initial values of each field.
01962   const unsigned NumFields = 4;
01963   SDValue Fields[NumFields] = {
01964     DAG.getConstant(FuncInfo->getVarArgsFirstGPR(), PtrVT),
01965     DAG.getConstant(FuncInfo->getVarArgsFirstFPR(), PtrVT),
01966     DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT),
01967     DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), PtrVT)
01968   };
01969 
01970   // Store each field into its respective slot.
01971   SDValue MemOps[NumFields];
01972   unsigned Offset = 0;
01973   for (unsigned I = 0; I < NumFields; ++I) {
01974     SDValue FieldAddr = Addr;
01975     if (Offset != 0)
01976       FieldAddr = DAG.getNode(ISD::ADD, DL, PtrVT, FieldAddr,
01977                               DAG.getIntPtrConstant(Offset));
01978     MemOps[I] = DAG.getStore(Chain, DL, Fields[I], FieldAddr,
01979                              MachinePointerInfo(SV, Offset),
01980                              false, false, 0);
01981     Offset += 8;
01982   }
01983   return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
01984 }
01985 
01986 SDValue SystemZTargetLowering::lowerVACOPY(SDValue Op,
01987                                            SelectionDAG &DAG) const {
01988   SDValue Chain      = Op.getOperand(0);
01989   SDValue DstPtr     = Op.getOperand(1);
01990   SDValue SrcPtr     = Op.getOperand(2);
01991   const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
01992   const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
01993   SDLoc DL(Op);
01994 
01995   return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr, DAG.getIntPtrConstant(32),
01996                        /*Align*/8, /*isVolatile*/false, /*AlwaysInline*/false,
01997                        MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
01998 }
01999 
02000 SDValue SystemZTargetLowering::
02001 lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const {
02002   SDValue Chain = Op.getOperand(0);
02003   SDValue Size  = Op.getOperand(1);
02004   SDLoc DL(Op);
02005 
02006   unsigned SPReg = getStackPointerRegisterToSaveRestore();
02007 
02008   // Get a reference to the stack pointer.
02009   SDValue OldSP = DAG.getCopyFromReg(Chain, DL, SPReg, MVT::i64);
02010 
02011   // Get the new stack pointer value.
02012   SDValue NewSP = DAG.getNode(ISD::SUB, DL, MVT::i64, OldSP, Size);
02013 
02014   // Copy the new stack pointer back.
02015   Chain = DAG.getCopyToReg(Chain, DL, SPReg, NewSP);
02016 
02017   // The allocated data lives above the 160 bytes allocated for the standard
02018   // frame, plus any outgoing stack arguments.  We don't know how much that
02019   // amounts to yet, so emit a special ADJDYNALLOC placeholder.
02020   SDValue ArgAdjust = DAG.getNode(SystemZISD::ADJDYNALLOC, DL, MVT::i64);
02021   SDValue Result = DAG.getNode(ISD::ADD, DL, MVT::i64, NewSP, ArgAdjust);
02022 
02023   SDValue Ops[2] = { Result, Chain };
02024   return DAG.getMergeValues(Ops, DL);
02025 }
02026 
02027 SDValue SystemZTargetLowering::lowerSMUL_LOHI(SDValue Op,
02028                                               SelectionDAG &DAG) const {
02029   EVT VT = Op.getValueType();
02030   SDLoc DL(Op);
02031   SDValue Ops[2];
02032   if (is32Bit(VT))
02033     // Just do a normal 64-bit multiplication and extract the results.
02034     // We define this so that it can be used for constant division.
02035     lowerMUL_LOHI32(DAG, DL, ISD::SIGN_EXTEND, Op.getOperand(0),
02036                     Op.getOperand(1), Ops[1], Ops[0]);
02037   else {
02038     // Do a full 128-bit multiplication based on UMUL_LOHI64:
02039     //
02040     //   (ll * rl) + ((lh * rl) << 64) + ((ll * rh) << 64)
02041     //
02042     // but using the fact that the upper halves are either all zeros
02043     // or all ones:
02044     //
02045     //   (ll * rl) - ((lh & rl) << 64) - ((ll & rh) << 64)
02046     //
02047     // and grouping the right terms together since they are quicker than the
02048     // multiplication:
02049     //
02050     //   (ll * rl) - (((lh & rl) + (ll & rh)) << 64)
02051     SDValue C63 = DAG.getConstant(63, MVT::i64);
02052     SDValue LL = Op.getOperand(0);
02053     SDValue RL = Op.getOperand(1);
02054     SDValue LH = DAG.getNode(ISD::SRA, DL, VT, LL, C63);
02055     SDValue RH = DAG.getNode(ISD::SRA, DL, VT, RL, C63);
02056     // UMUL_LOHI64 returns the low result in the odd register and the high
02057     // result in the even register.  SMUL_LOHI is defined to return the
02058     // low half first, so the results are in reverse order.
02059     lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, SystemZISD::UMUL_LOHI64,
02060                      LL, RL, Ops[1], Ops[0]);
02061     SDValue NegLLTimesRH = DAG.getNode(ISD::AND, DL, VT, LL, RH);
02062     SDValue NegLHTimesRL = DAG.getNode(ISD::AND, DL, VT, LH, RL);
02063     SDValue NegSum = DAG.getNode(ISD::ADD, DL, VT, NegLLTimesRH, NegLHTimesRL);
02064     Ops[1] = DAG.getNode(ISD::SUB, DL, VT, Ops[1], NegSum);
02065   }
02066   return DAG.getMergeValues(Ops, DL);
02067 }
02068 
02069 SDValue SystemZTargetLowering::lowerUMUL_LOHI(SDValue Op,
02070                                               SelectionDAG &DAG) const {
02071   EVT VT = Op.getValueType();
02072   SDLoc DL(Op);
02073   SDValue Ops[2];
02074   if (is32Bit(VT))
02075     // Just do a normal 64-bit multiplication and extract the results.
02076     // We define this so that it can be used for constant division.
02077     lowerMUL_LOHI32(DAG, DL, ISD::ZERO_EXTEND, Op.getOperand(0),
02078                     Op.getOperand(1), Ops[1], Ops[0]);
02079   else
02080     // UMUL_LOHI64 returns the low result in the odd register and the high
02081     // result in the even register.  UMUL_LOHI is defined to return the
02082     // low half first, so the results are in reverse order.
02083     lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, SystemZISD::UMUL_LOHI64,
02084                      Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
02085   return DAG.getMergeValues(Ops, DL);
02086 }
02087 
02088 SDValue SystemZTargetLowering::lowerSDIVREM(SDValue Op,
02089                                             SelectionDAG &DAG) const {
02090   SDValue Op0 = Op.getOperand(0);
02091   SDValue Op1 = Op.getOperand(1);
02092   EVT VT = Op.getValueType();
02093   SDLoc DL(Op);
02094   unsigned Opcode;
02095 
02096   // We use DSGF for 32-bit division.
02097   if (is32Bit(VT)) {
02098     Op0 = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, Op0);
02099     Opcode = SystemZISD::SDIVREM32;
02100   } else if (DAG.ComputeNumSignBits(Op1) > 32) {
02101     Op1 = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Op1);
02102     Opcode = SystemZISD::SDIVREM32;
02103   } else    
02104     Opcode = SystemZISD::SDIVREM64;
02105 
02106   // DSG(F) takes a 64-bit dividend, so the even register in the GR128
02107   // input is "don't care".  The instruction returns the remainder in
02108   // the even register and the quotient in the odd register.
02109   SDValue Ops[2];
02110   lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, Opcode,
02111                    Op0, Op1, Ops[1], Ops[0]);
02112   return DAG.getMergeValues(Ops, DL);
02113 }
02114 
02115 SDValue SystemZTargetLowering::lowerUDIVREM(SDValue Op,
02116                                             SelectionDAG &DAG) const {
02117   EVT VT = Op.getValueType();
02118   SDLoc DL(Op);
02119 
02120   // DL(G) uses a double-width dividend, so we need to clear the even
02121   // register in the GR128 input.  The instruction returns the remainder
02122   // in the even register and the quotient in the odd register.
02123   SDValue Ops[2];
02124   if (is32Bit(VT))
02125     lowerGR128Binary(DAG, DL, VT, SystemZ::ZEXT128_32, SystemZISD::UDIVREM32,
02126                      Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
02127   else
02128     lowerGR128Binary(DAG, DL, VT, SystemZ::ZEXT128_64, SystemZISD::UDIVREM64,
02129                      Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
02130   return DAG.getMergeValues(Ops, DL);
02131 }
02132 
02133 SDValue SystemZTargetLowering::lowerOR(SDValue Op, SelectionDAG &DAG) const {
02134   assert(Op.getValueType() == MVT::i64 && "Should be 64-bit operation");
02135 
02136   // Get the known-zero masks for each operand.
02137   SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1) };
02138   APInt KnownZero[2], KnownOne[2];
02139   DAG.computeKnownBits(Ops[0], KnownZero[0], KnownOne[0]);
02140   DAG.computeKnownBits(Ops[1], KnownZero[1], KnownOne[1]);
02141 
02142   // See if the upper 32 bits of one operand and the lower 32 bits of the
02143   // other are known zero.  They are the low and high operands respectively.
02144   uint64_t Masks[] = { KnownZero[0].getZExtValue(),
02145                        KnownZero[1].getZExtValue() };
02146   unsigned High, Low;
02147   if ((Masks[0] >> 32) == 0xffffffff && uint32_t(Masks[1]) == 0xffffffff)
02148     High = 1, Low = 0;
02149   else if ((Masks[1] >> 32) == 0xffffffff && uint32_t(Masks[0]) == 0xffffffff)
02150     High = 0, Low = 1;
02151   else
02152     return Op;
02153 
02154   SDValue LowOp = Ops[Low];
02155   SDValue HighOp = Ops[High];
02156 
02157   // If the high part is a constant, we're better off using IILH.
02158   if (HighOp.getOpcode() == ISD::Constant)
02159     return Op;
02160 
02161   // If the low part is a constant that is outside the range of LHI,
02162   // then we're better off using IILF.
02163   if (LowOp.getOpcode() == ISD::Constant) {
02164     int64_t Value = int32_t(cast<ConstantSDNode>(LowOp)->getZExtValue());
02165     if (!isInt<16>(Value))
02166       return Op;
02167   }
02168 
02169   // Check whether the high part is an AND that doesn't change the
02170   // high 32 bits and just masks out low bits.  We can skip it if so.
02171   if (HighOp.getOpcode() == ISD::AND &&
02172       HighOp.getOperand(1).getOpcode() == ISD::Constant) {
02173     SDValue HighOp0 = HighOp.getOperand(0);
02174     uint64_t Mask = cast<ConstantSDNode>(HighOp.getOperand(1))->getZExtValue();
02175     if (DAG.MaskedValueIsZero(HighOp0, APInt(64, ~(Mask | 0xffffffff))))
02176       HighOp = HighOp0;
02177   }
02178 
02179   // Take advantage of the fact that all GR32 operations only change the
02180   // low 32 bits by truncating Low to an i32 and inserting it directly
02181   // using a subreg.  The interesting cases are those where the truncation
02182   // can be folded.
02183   SDLoc DL(Op);
02184   SDValue Low32 = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, LowOp);
02185   return DAG.getTargetInsertSubreg(SystemZ::subreg_l32, DL,
02186                                    MVT::i64, HighOp, Low32);
02187 }
02188 
02189 // Op is an atomic load.  Lower it into a normal volatile load.
02190 SDValue SystemZTargetLowering::lowerATOMIC_LOAD(SDValue Op,
02191                                                 SelectionDAG &DAG) const {
02192   auto *Node = cast<AtomicSDNode>(Op.getNode());
02193   return DAG.getExtLoad(ISD::EXTLOAD, SDLoc(Op), Op.getValueType(),
02194                         Node->getChain(), Node->getBasePtr(),
02195                         Node->getMemoryVT(), Node->getMemOperand());
02196 }
02197 
02198 // Op is an atomic store.  Lower it into a normal volatile store followed
02199 // by a serialization.
02200 SDValue SystemZTargetLowering::lowerATOMIC_STORE(SDValue Op,
02201                                                  SelectionDAG &DAG) const {
02202   auto *Node = cast<AtomicSDNode>(Op.getNode());
02203   SDValue Chain = DAG.getTruncStore(Node->getChain(), SDLoc(Op), Node->getVal(),
02204                                     Node->getBasePtr(), Node->getMemoryVT(),
02205                                     Node->getMemOperand());
02206   return SDValue(DAG.getMachineNode(SystemZ::Serialize, SDLoc(Op), MVT::Other,
02207                                     Chain), 0);
02208 }
02209 
02210 // Op is an 8-, 16-bit or 32-bit ATOMIC_LOAD_* operation.  Lower the first
02211 // two into the fullword ATOMIC_LOADW_* operation given by Opcode.
02212 SDValue SystemZTargetLowering::lowerATOMIC_LOAD_OP(SDValue Op,
02213                                                    SelectionDAG &DAG,
02214                                                    unsigned Opcode) const {
02215   auto *Node = cast<AtomicSDNode>(Op.getNode());
02216 
02217   // 32-bit operations need no code outside the main loop.
02218   EVT NarrowVT = Node->getMemoryVT();
02219   EVT WideVT = MVT::i32;
02220   if (NarrowVT == WideVT)
02221     return Op;
02222 
02223   int64_t BitSize = NarrowVT.getSizeInBits();
02224   SDValue ChainIn = Node->getChain();
02225   SDValue Addr = Node->getBasePtr();
02226   SDValue Src2 = Node->getVal();
02227   MachineMemOperand *MMO = Node->getMemOperand();
02228   SDLoc DL(Node);
02229   EVT PtrVT = Addr.getValueType();
02230 
02231   // Convert atomic subtracts of constants into additions.
02232   if (Opcode == SystemZISD::ATOMIC_LOADW_SUB)
02233     if (auto *Const = dyn_cast<ConstantSDNode>(Src2)) {
02234       Opcode = SystemZISD::ATOMIC_LOADW_ADD;
02235       Src2 = DAG.getConstant(-Const->getSExtValue(), Src2.getValueType());
02236     }
02237 
02238   // Get the address of the containing word.
02239   SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr,
02240                                     DAG.getConstant(-4, PtrVT));
02241 
02242   // Get the number of bits that the word must be rotated left in order
02243   // to bring the field to the top bits of a GR32.
02244   SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr,
02245                                  DAG.getConstant(3, PtrVT));
02246   BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift);
02247 
02248   // Get the complementing shift amount, for rotating a field in the top
02249   // bits back to its proper position.
02250   SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT,
02251                                     DAG.getConstant(0, WideVT), BitShift);
02252 
02253   // Extend the source operand to 32 bits and prepare it for the inner loop.
02254   // ATOMIC_SWAPW uses RISBG to rotate the field left, but all other
02255   // operations require the source to be shifted in advance.  (This shift
02256   // can be folded if the source is constant.)  For AND and NAND, the lower
02257   // bits must be set, while for other opcodes they should be left clear.
02258   if (Opcode != SystemZISD::ATOMIC_SWAPW)
02259     Src2 = DAG.getNode(ISD::SHL, DL, WideVT, Src2,
02260                        DAG.getConstant(32 - BitSize, WideVT));
02261   if (Opcode == SystemZISD::ATOMIC_LOADW_AND ||
02262       Opcode == SystemZISD::ATOMIC_LOADW_NAND)
02263     Src2 = DAG.getNode(ISD::OR, DL, WideVT, Src2,
02264                        DAG.getConstant(uint32_t(-1) >> BitSize, WideVT));
02265 
02266   // Construct the ATOMIC_LOADW_* node.
02267   SDVTList VTList = DAG.getVTList(WideVT, MVT::Other);
02268   SDValue Ops[] = { ChainIn, AlignedAddr, Src2, BitShift, NegBitShift,
02269                     DAG.getConstant(BitSize, WideVT) };
02270   SDValue AtomicOp = DAG.getMemIntrinsicNode(Opcode, DL, VTList, Ops,
02271                                              NarrowVT, MMO);
02272 
02273   // Rotate the result of the final CS so that the field is in the lower
02274   // bits of a GR32, then truncate it.
02275   SDValue ResultShift = DAG.getNode(ISD::ADD, DL, WideVT, BitShift,
02276                                     DAG.getConstant(BitSize, WideVT));
02277   SDValue Result = DAG.getNode(ISD::ROTL, DL, WideVT, AtomicOp, ResultShift);
02278 
02279   SDValue RetOps[2] = { Result, AtomicOp.getValue(1) };
02280   return DAG.getMergeValues(RetOps, DL);
02281 }
02282 
02283 // Op is an ATOMIC_LOAD_SUB operation.  Lower 8- and 16-bit operations
02284 // into ATOMIC_LOADW_SUBs and decide whether to convert 32- and 64-bit
02285 // operations into additions.
02286 SDValue SystemZTargetLowering::lowerATOMIC_LOAD_SUB(SDValue Op,
02287                                                     SelectionDAG &DAG) const {
02288   auto *Node = cast<AtomicSDNode>(Op.getNode());
02289   EVT MemVT = Node->getMemoryVT();
02290   if (MemVT == MVT::i32 || MemVT == MVT::i64) {
02291     // A full-width operation.
02292     assert(Op.getValueType() == MemVT && "Mismatched VTs");
02293     SDValue Src2 = Node->getVal();
02294     SDValue NegSrc2;
02295     SDLoc DL(Src2);
02296 
02297     if (auto *Op2 = dyn_cast<ConstantSDNode>(Src2)) {
02298       // Use an addition if the operand is constant and either LAA(G) is
02299       // available or the negative value is in the range of A(G)FHI.
02300       int64_t Value = (-Op2->getAPIntValue()).getSExtValue();
02301       if (isInt<32>(Value) || Subtarget.hasInterlockedAccess1())
02302         NegSrc2 = DAG.getConstant(Value, MemVT);
02303     } else if (Subtarget.hasInterlockedAccess1())
02304       // Use LAA(G) if available.
02305       NegSrc2 = DAG.getNode(ISD::SUB, DL, MemVT, DAG.getConstant(0, MemVT),
02306                             Src2);
02307 
02308     if (NegSrc2.getNode())
02309       return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, DL, MemVT,
02310                            Node->getChain(), Node->getBasePtr(), NegSrc2,
02311                            Node->getMemOperand(), Node->getOrdering(),
02312                            Node->getSynchScope());
02313 
02314     // Use the node as-is.
02315     return Op;
02316   }
02317 
02318   return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_SUB);
02319 }
02320 
02321 // Node is an 8- or 16-bit ATOMIC_CMP_SWAP operation.  Lower the first two
02322 // into a fullword ATOMIC_CMP_SWAPW operation.
02323 SDValue SystemZTargetLowering::lowerATOMIC_CMP_SWAP(SDValue Op,
02324                                                     SelectionDAG &DAG) const {
02325   auto *Node = cast<AtomicSDNode>(Op.getNode());
02326 
02327   // We have native support for 32-bit compare and swap.
02328   EVT NarrowVT = Node->getMemoryVT();
02329   EVT WideVT = MVT::i32;
02330   if (NarrowVT == WideVT)
02331     return Op;
02332 
02333   int64_t BitSize = NarrowVT.getSizeInBits();
02334   SDValue ChainIn = Node->getOperand(0);
02335   SDValue Addr = Node->getOperand(1);
02336   SDValue CmpVal = Node->getOperand(2);
02337   SDValue SwapVal = Node->getOperand(3);
02338   MachineMemOperand *MMO = Node->getMemOperand();
02339   SDLoc DL(Node);
02340   EVT PtrVT = Addr.getValueType();
02341 
02342   // Get the address of the containing word.
02343   SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr,
02344                                     DAG.getConstant(-4, PtrVT));
02345 
02346   // Get the number of bits that the word must be rotated left in order
02347   // to bring the field to the top bits of a GR32.
02348   SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr,
02349                                  DAG.getConstant(3, PtrVT));
02350   BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift);
02351 
02352   // Get the complementing shift amount, for rotating a field in the top
02353   // bits back to its proper position.
02354   SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT,
02355                                     DAG.getConstant(0, WideVT), BitShift);
02356 
02357   // Construct the ATOMIC_CMP_SWAPW node.
02358   SDVTList VTList = DAG.getVTList(WideVT, MVT::Other);
02359   SDValue Ops[] = { ChainIn, AlignedAddr, CmpVal, SwapVal, BitShift,
02360                     NegBitShift, DAG.getConstant(BitSize, WideVT) };
02361   SDValue AtomicOp = DAG.getMemIntrinsicNode(SystemZISD::ATOMIC_CMP_SWAPW, DL,
02362                                              VTList, Ops, NarrowVT, MMO);
02363   return AtomicOp;
02364 }
02365 
02366 SDValue SystemZTargetLowering::lowerSTACKSAVE(SDValue Op,
02367                                               SelectionDAG &DAG) const {
02368   MachineFunction &MF = DAG.getMachineFunction();
02369   MF.getInfo<SystemZMachineFunctionInfo>()->setManipulatesSP(true);
02370   return DAG.getCopyFromReg(Op.getOperand(0), SDLoc(Op),
02371                             SystemZ::R15D, Op.getValueType());
02372 }
02373 
02374 SDValue SystemZTargetLowering::lowerSTACKRESTORE(SDValue Op,
02375                                                  SelectionDAG &DAG) const {
02376   MachineFunction &MF = DAG.getMachineFunction();
02377   MF.getInfo<SystemZMachineFunctionInfo>()->setManipulatesSP(true);
02378   return DAG.getCopyToReg(Op.getOperand(0), SDLoc(Op),
02379                           SystemZ::R15D, Op.getOperand(1));
02380 }
02381 
02382 SDValue SystemZTargetLowering::lowerPREFETCH(SDValue Op,
02383                                              SelectionDAG &DAG) const {
02384   bool IsData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
02385   if (!IsData)
02386     // Just preserve the chain.
02387     return Op.getOperand(0);
02388 
02389   bool IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
02390   unsigned Code = IsWrite ? SystemZ::PFD_WRITE : SystemZ::PFD_READ;
02391   auto *Node = cast<MemIntrinsicSDNode>(Op.getNode());
02392   SDValue Ops[] = {
02393     Op.getOperand(0),
02394     DAG.getConstant(Code, MVT::i32),
02395     Op.getOperand(1)
02396   };
02397   return DAG.getMemIntrinsicNode(SystemZISD::PREFETCH, SDLoc(Op),
02398                                  Node->getVTList(), Ops,
02399                                  Node->getMemoryVT(), Node->getMemOperand());
02400 }
02401 
02402 SDValue SystemZTargetLowering::LowerOperation(SDValue Op,
02403                                               SelectionDAG &DAG) const {
02404   switch (Op.getOpcode()) {
02405   case ISD::BR_CC:
02406     return lowerBR_CC(Op, DAG);
02407   case ISD::SELECT_CC:
02408     return lowerSELECT_CC(Op, DAG);
02409   case ISD::SETCC:
02410     return lowerSETCC(Op, DAG);
02411   case ISD::GlobalAddress:
02412     return lowerGlobalAddress(cast<GlobalAddressSDNode>(Op), DAG);
02413   case ISD::GlobalTLSAddress:
02414     return lowerGlobalTLSAddress(cast<GlobalAddressSDNode>(Op), DAG);
02415   case ISD::BlockAddress:
02416     return lowerBlockAddress(cast<BlockAddressSDNode>(Op), DAG);
02417   case ISD::JumpTable:
02418     return lowerJumpTable(cast<JumpTableSDNode>(Op), DAG);
02419   case ISD::ConstantPool:
02420     return lowerConstantPool(cast<ConstantPoolSDNode>(Op), DAG);
02421   case ISD::BITCAST:
02422     return lowerBITCAST(Op, DAG);
02423   case ISD::VASTART:
02424     return lowerVASTART(Op, DAG);
02425   case ISD::VACOPY:
02426     return lowerVACOPY(Op, DAG);
02427   case ISD::DYNAMIC_STACKALLOC:
02428     return lowerDYNAMIC_STACKALLOC(Op, DAG);
02429   case ISD::SMUL_LOHI:
02430     return lowerSMUL_LOHI(Op, DAG);
02431   case ISD::UMUL_LOHI:
02432     return lowerUMUL_LOHI(Op, DAG);
02433   case ISD::SDIVREM:
02434     return lowerSDIVREM(Op, DAG);
02435   case ISD::UDIVREM:
02436     return lowerUDIVREM(Op, DAG);
02437   case ISD::OR:
02438     return lowerOR(Op, DAG);
02439   case ISD::ATOMIC_SWAP:
02440     return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_SWAPW);
02441   case ISD::ATOMIC_STORE:
02442     return lowerATOMIC_STORE(Op, DAG);
02443   case ISD::ATOMIC_LOAD:
02444     return lowerATOMIC_LOAD(Op, DAG);
02445   case ISD::ATOMIC_LOAD_ADD:
02446     return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_ADD);
02447   case ISD::ATOMIC_LOAD_SUB:
02448     return lowerATOMIC_LOAD_SUB(Op, DAG);
02449   case ISD::ATOMIC_LOAD_AND:
02450     return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_AND);
02451   case ISD::ATOMIC_LOAD_OR:
02452     return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_OR);
02453   case ISD::ATOMIC_LOAD_XOR:
02454     return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_XOR);
02455   case ISD::ATOMIC_LOAD_NAND:
02456     return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_NAND);
02457   case ISD::ATOMIC_LOAD_MIN:
02458     return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_MIN);
02459   case ISD::ATOMIC_LOAD_MAX:
02460     return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_MAX);
02461   case ISD::ATOMIC_LOAD_UMIN:
02462     return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_UMIN);
02463   case ISD::ATOMIC_LOAD_UMAX:
02464     return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_UMAX);
02465   case ISD::ATOMIC_CMP_SWAP:
02466     return lowerATOMIC_CMP_SWAP(Op, DAG);
02467   case ISD::STACKSAVE:
02468     return lowerSTACKSAVE(Op, DAG);
02469   case ISD::STACKRESTORE:
02470     return lowerSTACKRESTORE(Op, DAG);
02471   case ISD::PREFETCH:
02472     return lowerPREFETCH(Op, DAG);
02473   default:
02474     llvm_unreachable("Unexpected node to lower");
02475   }
02476 }
02477 
02478 const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const {
02479 #define OPCODE(NAME) case SystemZISD::NAME: return "SystemZISD::" #NAME
02480   switch (Opcode) {
02481     OPCODE(RET_FLAG);
02482     OPCODE(CALL);
02483     OPCODE(SIBCALL);
02484     OPCODE(PCREL_WRAPPER);
02485     OPCODE(PCREL_OFFSET);
02486     OPCODE(IABS);
02487     OPCODE(ICMP);
02488     OPCODE(FCMP);
02489     OPCODE(TM);
02490     OPCODE(BR_CCMASK);
02491     OPCODE(SELECT_CCMASK);
02492     OPCODE(ADJDYNALLOC);
02493     OPCODE(EXTRACT_ACCESS);
02494     OPCODE(UMUL_LOHI64);
02495     OPCODE(SDIVREM64);
02496     OPCODE(UDIVREM32);
02497     OPCODE(UDIVREM64);
02498     OPCODE(MVC);
02499     OPCODE(MVC_LOOP);
02500     OPCODE(NC);
02501     OPCODE(NC_LOOP);
02502     OPCODE(OC);
02503     OPCODE(OC_LOOP);
02504     OPCODE(XC);
02505     OPCODE(XC_LOOP);
02506     OPCODE(CLC);
02507     OPCODE(CLC_LOOP);
02508     OPCODE(STRCMP);
02509     OPCODE(STPCPY);
02510     OPCODE(SEARCH_STRING);
02511     OPCODE(IPM);
02512     OPCODE(SERIALIZE);
02513     OPCODE(ATOMIC_SWAPW);
02514     OPCODE(ATOMIC_LOADW_ADD);
02515     OPCODE(ATOMIC_LOADW_SUB);
02516     OPCODE(ATOMIC_LOADW_AND);
02517     OPCODE(ATOMIC_LOADW_OR);
02518     OPCODE(ATOMIC_LOADW_XOR);
02519     OPCODE(ATOMIC_LOADW_NAND);
02520     OPCODE(ATOMIC_LOADW_MIN);
02521     OPCODE(ATOMIC_LOADW_MAX);
02522     OPCODE(ATOMIC_LOADW_UMIN);
02523     OPCODE(ATOMIC_LOADW_UMAX);
02524     OPCODE(ATOMIC_CMP_SWAPW);
02525     OPCODE(PREFETCH);
02526   }
02527   return nullptr;
02528 #undef OPCODE
02529 }
02530 
02531 SDValue SystemZTargetLowering::PerformDAGCombine(SDNode *N,
02532                                                  DAGCombinerInfo &DCI) const {
02533   SelectionDAG &DAG = DCI.DAG;
02534   unsigned Opcode = N->getOpcode();
02535   if (Opcode == ISD::SIGN_EXTEND) {
02536     // Convert (sext (ashr (shl X, C1), C2)) to
02537     // (ashr (shl (anyext X), C1'), C2')), since wider shifts are as
02538     // cheap as narrower ones.
02539     SDValue N0 = N->getOperand(0);
02540     EVT VT = N->getValueType(0);
02541     if (N0.hasOneUse() && N0.getOpcode() == ISD::SRA) {
02542       auto *SraAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1));
02543       SDValue Inner = N0.getOperand(0);
02544       if (SraAmt && Inner.hasOneUse() && Inner.getOpcode() == ISD::SHL) {
02545         if (auto *ShlAmt = dyn_cast<ConstantSDNode>(Inner.getOperand(1))) {
02546           unsigned Extra = (VT.getSizeInBits() -
02547                             N0.getValueType().getSizeInBits());
02548           unsigned NewShlAmt = ShlAmt->getZExtValue() + Extra;
02549           unsigned NewSraAmt = SraAmt->getZExtValue() + Extra;
02550           EVT ShiftVT = N0.getOperand(1).getValueType();
02551           SDValue Ext = DAG.getNode(ISD::ANY_EXTEND, SDLoc(Inner), VT,
02552                                     Inner.getOperand(0));
02553           SDValue Shl = DAG.getNode(ISD::SHL, SDLoc(Inner), VT, Ext,
02554                                     DAG.getConstant(NewShlAmt, ShiftVT));
02555           return DAG.getNode(ISD::SRA, SDLoc(N0), VT, Shl,
02556                              DAG.getConstant(NewSraAmt, ShiftVT));
02557         }
02558       }
02559     }
02560   }
02561   return SDValue();
02562 }
02563 
02564 //===----------------------------------------------------------------------===//
02565 // Custom insertion
02566 //===----------------------------------------------------------------------===//
02567 
02568 // Create a new basic block after MBB.
02569 static MachineBasicBlock *emitBlockAfter(MachineBasicBlock *MBB) {
02570   MachineFunction &MF = *MBB->getParent();
02571   MachineBasicBlock *NewMBB = MF.CreateMachineBasicBlock(MBB->getBasicBlock());
02572   MF.insert(std::next(MachineFunction::iterator(MBB)), NewMBB);
02573   return NewMBB;
02574 }
02575 
02576 // Split MBB after MI and return the new block (the one that contains
02577 // instructions after MI).
02578 static MachineBasicBlock *splitBlockAfter(MachineInstr *MI,
02579                                           MachineBasicBlock *MBB) {
02580   MachineBasicBlock *NewMBB = emitBlockAfter(MBB);
02581   NewMBB->splice(NewMBB->begin(), MBB,
02582                  std::next(MachineBasicBlock::iterator(MI)), MBB->end());
02583   NewMBB->transferSuccessorsAndUpdatePHIs(MBB);
02584   return NewMBB;
02585 }
02586 
02587 // Split MBB before MI and return the new block (the one that contains MI).
02588 static MachineBasicBlock *splitBlockBefore(MachineInstr *MI,
02589                                            MachineBasicBlock *MBB) {
02590   MachineBasicBlock *NewMBB = emitBlockAfter(MBB);
02591   NewMBB->splice(NewMBB->begin(), MBB, MI, MBB->end());
02592   NewMBB->transferSuccessorsAndUpdatePHIs(MBB);
02593   return NewMBB;
02594 }
02595 
02596 // Force base value Base into a register before MI.  Return the register.
02597 static unsigned forceReg(MachineInstr *MI, MachineOperand &Base,
02598                          const SystemZInstrInfo *TII) {
02599   if (Base.isReg())
02600     return Base.getReg();
02601 
02602   MachineBasicBlock *MBB = MI->getParent();
02603   MachineFunction &MF = *MBB->getParent();
02604   MachineRegisterInfo &MRI = MF.getRegInfo();
02605 
02606   unsigned Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
02607   BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(SystemZ::LA), Reg)
02608     .addOperand(Base).addImm(0).addReg(0);
02609   return Reg;
02610 }
02611 
02612 // Implement EmitInstrWithCustomInserter for pseudo Select* instruction MI.
02613 MachineBasicBlock *
02614 SystemZTargetLowering::emitSelect(MachineInstr *MI,
02615                                   MachineBasicBlock *MBB) const {
02616   const SystemZInstrInfo *TII = static_cast<const SystemZInstrInfo *>(
02617       MBB->getParent()->getTarget().getInstrInfo());
02618 
02619   unsigned DestReg  = MI->getOperand(0).getReg();
02620   unsigned TrueReg  = MI->getOperand(1).getReg();
02621   unsigned FalseReg = MI->getOperand(2).getReg();
02622   unsigned CCValid  = MI->getOperand(3).getImm();
02623   unsigned CCMask   = MI->getOperand(4).getImm();
02624   DebugLoc DL       = MI->getDebugLoc();
02625 
02626   MachineBasicBlock *StartMBB = MBB;
02627   MachineBasicBlock *JoinMBB  = splitBlockBefore(MI, MBB);
02628   MachineBasicBlock *FalseMBB = emitBlockAfter(StartMBB);
02629 
02630   //  StartMBB:
02631   //   BRC CCMask, JoinMBB
02632   //   # fallthrough to FalseMBB
02633   MBB = StartMBB;
02634   BuildMI(MBB, DL, TII->get(SystemZ::BRC))
02635     .addImm(CCValid).addImm(CCMask).addMBB(JoinMBB);
02636   MBB->addSuccessor(JoinMBB);
02637   MBB->addSuccessor(FalseMBB);
02638 
02639   //  FalseMBB:
02640   //   # fallthrough to JoinMBB
02641   MBB = FalseMBB;
02642   MBB->addSuccessor(JoinMBB);
02643 
02644   //  JoinMBB:
02645   //   %Result = phi [ %FalseReg, FalseMBB ], [ %TrueReg, StartMBB ]
02646   //  ...
02647   MBB = JoinMBB;
02648   BuildMI(*MBB, MI, DL, TII->get(SystemZ::PHI), DestReg)
02649     .addReg(TrueReg).addMBB(StartMBB)
02650     .addReg(FalseReg).addMBB(FalseMBB);
02651 
02652   MI->eraseFromParent();
02653   return JoinMBB;
02654 }
02655 
02656 // Implement EmitInstrWithCustomInserter for pseudo CondStore* instruction MI.
02657 // StoreOpcode is the store to use and Invert says whether the store should
02658 // happen when the condition is false rather than true.  If a STORE ON
02659 // CONDITION is available, STOCOpcode is its opcode, otherwise it is 0.
02660 MachineBasicBlock *
02661 SystemZTargetLowering::emitCondStore(MachineInstr *MI,
02662                                      MachineBasicBlock *MBB,
02663                                      unsigned StoreOpcode, unsigned STOCOpcode,
02664                                      bool Invert) const {
02665   const SystemZInstrInfo *TII = static_cast<const SystemZInstrInfo *>(
02666       MBB->getParent()->getTarget().getInstrInfo());
02667 
02668   unsigned SrcReg     = MI->getOperand(0).getReg();
02669   MachineOperand Base = MI->getOperand(1);
02670   int64_t Disp        = MI->getOperand(2).getImm();
02671   unsigned IndexReg   = MI->getOperand(3).getReg();
02672   unsigned CCValid    = MI->getOperand(4).getImm();
02673   unsigned CCMask     = MI->getOperand(5).getImm();
02674   DebugLoc DL         = MI->getDebugLoc();
02675 
02676   StoreOpcode = TII->getOpcodeForOffset(StoreOpcode, Disp);
02677 
02678   // Use STOCOpcode if possible.  We could use different store patterns in
02679   // order to avoid matching the index register, but the performance trade-offs
02680   // might be more complicated in that case.
02681   if (STOCOpcode && !IndexReg && Subtarget.hasLoadStoreOnCond()) {
02682     if (Invert)
02683       CCMask ^= CCValid;
02684     BuildMI(*MBB, MI, DL, TII->get(STOCOpcode))
02685       .addReg(SrcReg).addOperand(Base).addImm(Disp)
02686       .addImm(CCValid).addImm(CCMask);
02687     MI->eraseFromParent();
02688     return MBB;
02689   }
02690 
02691   // Get the condition needed to branch around the store.
02692   if (!Invert)
02693     CCMask ^= CCValid;
02694 
02695   MachineBasicBlock *StartMBB = MBB;
02696   MachineBasicBlock *JoinMBB  = splitBlockBefore(MI, MBB);
02697   MachineBasicBlock *FalseMBB = emitBlockAfter(StartMBB);
02698 
02699   //  StartMBB:
02700   //   BRC CCMask, JoinMBB
02701   //   # fallthrough to FalseMBB
02702   MBB = StartMBB;
02703   BuildMI(MBB, DL, TII->get(SystemZ::BRC))
02704     .addImm(CCValid).addImm(CCMask).addMBB(JoinMBB);
02705   MBB->addSuccessor(JoinMBB);
02706   MBB->addSuccessor(FalseMBB);
02707 
02708   //  FalseMBB:
02709   //   store %SrcReg, %Disp(%Index,%Base)
02710   //   # fallthrough to JoinMBB
02711   MBB = FalseMBB;
02712   BuildMI(MBB, DL, TII->get(StoreOpcode))
02713     .addReg(SrcReg).addOperand(Base).addImm(Disp).addReg(IndexReg);
02714   MBB->addSuccessor(JoinMBB);
02715 
02716   MI->eraseFromParent();
02717   return JoinMBB;
02718 }
02719 
02720 // Implement EmitInstrWithCustomInserter for pseudo ATOMIC_LOAD{,W}_*
02721 // or ATOMIC_SWAP{,W} instruction MI.  BinOpcode is the instruction that
02722 // performs the binary operation elided by "*", or 0 for ATOMIC_SWAP{,W}.
02723 // BitSize is the width of the field in bits, or 0 if this is a partword
02724 // ATOMIC_LOADW_* or ATOMIC_SWAPW instruction, in which case the bitsize
02725 // is one of the operands.  Invert says whether the field should be
02726 // inverted after performing BinOpcode (e.g. for NAND).
02727 MachineBasicBlock *
02728 SystemZTargetLowering::emitAtomicLoadBinary(MachineInstr *MI,
02729                                             MachineBasicBlock *MBB,
02730                                             unsigned BinOpcode,
02731                                             unsigned BitSize,
02732                                             bool Invert) const {
02733   MachineFunction &MF = *MBB->getParent();
02734   const SystemZInstrInfo *TII =
02735       static_cast<const SystemZInstrInfo *>(MF.getTarget().getInstrInfo());
02736   MachineRegisterInfo &MRI = MF.getRegInfo();
02737   bool IsSubWord = (BitSize < 32);
02738 
02739   // Extract the operands.  Base can be a register or a frame index.
02740   // Src2 can be a register or immediate.
02741   unsigned Dest        = MI->getOperand(0).getReg();
02742   MachineOperand Base  = earlyUseOperand(MI->getOperand(1));
02743   int64_t Disp         = MI->getOperand(2).getImm();
02744   MachineOperand Src2  = earlyUseOperand(MI->getOperand(3));
02745   unsigned BitShift    = (IsSubWord ? MI->getOperand(4).getReg() : 0);
02746   unsigned NegBitShift = (IsSubWord ? MI->getOperand(5).getReg() : 0);
02747   DebugLoc DL          = MI->getDebugLoc();
02748   if (IsSubWord)
02749     BitSize = MI->getOperand(6).getImm();
02750 
02751   // Subword operations use 32-bit registers.
02752   const TargetRegisterClass *RC = (BitSize <= 32 ?
02753                                    &SystemZ::GR32BitRegClass :
02754                                    &SystemZ::GR64BitRegClass);
02755   unsigned LOpcode  = BitSize <= 32 ? SystemZ::L  : SystemZ::LG;
02756   unsigned CSOpcode = BitSize <= 32 ? SystemZ::CS : SystemZ::CSG;
02757 
02758   // Get the right opcodes for the displacement.
02759   LOpcode  = TII->getOpcodeForOffset(LOpcode,  Disp);
02760   CSOpcode = TII->getOpcodeForOffset(CSOpcode, Disp);
02761   assert(LOpcode && CSOpcode && "Displacement out of range");
02762 
02763   // Create virtual registers for temporary results.
02764   unsigned OrigVal       = MRI.createVirtualRegister(RC);
02765   unsigned OldVal        = MRI.createVirtualRegister(RC);
02766   unsigned NewVal        = (BinOpcode || IsSubWord ?
02767                             MRI.createVirtualRegister(RC) : Src2.getReg());
02768   unsigned RotatedOldVal = (IsSubWord ? MRI.createVirtualRegister(RC) : OldVal);
02769   unsigned RotatedNewVal = (IsSubWord ? MRI.createVirtualRegister(RC) : NewVal);
02770 
02771   // Insert a basic block for the main loop.
02772   MachineBasicBlock *StartMBB = MBB;
02773   MachineBasicBlock *DoneMBB  = splitBlockBefore(MI, MBB);
02774   MachineBasicBlock *LoopMBB  = emitBlockAfter(StartMBB);
02775 
02776   //  StartMBB:
02777   //   ...
02778   //   %OrigVal = L Disp(%Base)
02779   //   # fall through to LoopMMB
02780   MBB = StartMBB;
02781   BuildMI(MBB, DL, TII->get(LOpcode), OrigVal)
02782     .addOperand(Base).addImm(Disp).addReg(0);
02783   MBB->addSuccessor(LoopMBB);
02784 
02785   //  LoopMBB:
02786   //   %OldVal        = phi [ %OrigVal, StartMBB ], [ %Dest, LoopMBB ]
02787   //   %RotatedOldVal = RLL %OldVal, 0(%BitShift)
02788   //   %RotatedNewVal = OP %RotatedOldVal, %Src2
02789   //   %NewVal        = RLL %RotatedNewVal, 0(%NegBitShift)
02790   //   %Dest          = CS %OldVal, %NewVal, Disp(%Base)
02791   //   JNE LoopMBB
02792   //   # fall through to DoneMMB
02793   MBB = LoopMBB;
02794   BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
02795     .addReg(OrigVal).addMBB(StartMBB)
02796     .addReg(Dest).addMBB(LoopMBB);
02797   if (IsSubWord)
02798     BuildMI(MBB, DL, TII->get(SystemZ::RLL), RotatedOldVal)
02799       .addReg(OldVal).addReg(BitShift).addImm(0);
02800   if (Invert) {
02801     // Perform the operation normally and then invert every bit of the field.
02802     unsigned Tmp = MRI.createVirtualRegister(RC);
02803     BuildMI(MBB, DL, TII->get(BinOpcode), Tmp)
02804       .addReg(RotatedOldVal).addOperand(Src2);
02805     if (BitSize < 32)
02806       // XILF with the upper BitSize bits set.
02807       BuildMI(MBB, DL, TII->get(SystemZ::XILF), RotatedNewVal)
02808         .addReg(Tmp).addImm(uint32_t(~0 << (32 - BitSize)));
02809     else if (BitSize == 32)
02810       // XILF with every bit set.
02811       BuildMI(MBB, DL, TII->get(SystemZ::XILF), RotatedNewVal)
02812         .addReg(Tmp).addImm(~uint32_t(0));
02813     else {
02814       // Use LCGR and add -1 to the result, which is more compact than
02815       // an XILF, XILH pair.
02816       unsigned Tmp2 = MRI.createVirtualRegister(RC);
02817       BuildMI(MBB, DL, TII->get(SystemZ::LCGR), Tmp2).addReg(Tmp);
02818       BuildMI(MBB, DL, TII->get(SystemZ::AGHI), RotatedNewVal)
02819         .addReg(Tmp2).addImm(-1);
02820     }
02821   } else if (BinOpcode)
02822     // A simply binary operation.
02823     BuildMI(MBB, DL, TII->get(BinOpcode), RotatedNewVal)
02824       .addReg(RotatedOldVal).addOperand(Src2);
02825   else if (IsSubWord)
02826     // Use RISBG to rotate Src2 into position and use it to replace the
02827     // field in RotatedOldVal.
02828     BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RotatedNewVal)
02829       .addReg(RotatedOldVal).addReg(Src2.getReg())
02830       .addImm(32).addImm(31 + BitSize).addImm(32 - BitSize);
02831   if (IsSubWord)
02832     BuildMI(MBB, DL, TII->get(SystemZ::RLL), NewVal)
02833       .addReg(RotatedNewVal).addReg(NegBitShift).addImm(0);
02834   BuildMI(MBB, DL, TII->get(CSOpcode), Dest)
02835     .addReg(OldVal).addReg(NewVal).addOperand(Base).addImm(Disp);
02836   BuildMI(MBB, DL, TII->get(SystemZ::BRC))
02837     .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
02838   MBB->addSuccessor(LoopMBB);
02839   MBB->addSuccessor(DoneMBB);
02840 
02841   MI->eraseFromParent();
02842   return DoneMBB;
02843 }
02844 
02845 // Implement EmitInstrWithCustomInserter for pseudo
02846 // ATOMIC_LOAD{,W}_{,U}{MIN,MAX} instruction MI.  CompareOpcode is the
02847 // instruction that should be used to compare the current field with the
02848 // minimum or maximum value.  KeepOldMask is the BRC condition-code mask
02849 // for when the current field should be kept.  BitSize is the width of
02850 // the field in bits, or 0 if this is a partword ATOMIC_LOADW_* instruction.
02851 MachineBasicBlock *
02852 SystemZTargetLowering::emitAtomicLoadMinMax(MachineInstr *MI,
02853                                             MachineBasicBlock *MBB,
02854                                             unsigned CompareOpcode,
02855                                             unsigned KeepOldMask,
02856                                             unsigned BitSize) const {
02857   MachineFunction &MF = *MBB->getParent();
02858   const SystemZInstrInfo *TII =
02859       static_cast<const SystemZInstrInfo *>(MF.getTarget().getInstrInfo());
02860   MachineRegisterInfo &MRI = MF.getRegInfo();
02861   bool IsSubWord = (BitSize < 32);
02862 
02863   // Extract the operands.  Base can be a register or a frame index.
02864   unsigned Dest        = MI->getOperand(0).getReg();
02865   MachineOperand Base  = earlyUseOperand(MI->getOperand(1));
02866   int64_t  Disp        = MI->getOperand(2).getImm();
02867   unsigned Src2        = MI->getOperand(3).getReg();
02868   unsigned BitShift    = (IsSubWord ? MI->getOperand(4).getReg() : 0);
02869   unsigned NegBitShift = (IsSubWord ? MI->getOperand(5).getReg() : 0);
02870   DebugLoc DL          = MI->getDebugLoc();
02871   if (IsSubWord)
02872     BitSize = MI->getOperand(6).getImm();
02873 
02874   // Subword operations use 32-bit registers.
02875   const TargetRegisterClass *RC = (BitSize <= 32 ?
02876                                    &SystemZ::GR32BitRegClass :
02877                                    &SystemZ::GR64BitRegClass);
02878   unsigned LOpcode  = BitSize <= 32 ? SystemZ::L  : SystemZ::LG;
02879   unsigned CSOpcode = BitSize <= 32 ? SystemZ::CS : SystemZ::CSG;
02880 
02881   // Get the right opcodes for the displacement.
02882   LOpcode  = TII->getOpcodeForOffset(LOpcode,  Disp);
02883   CSOpcode = TII->getOpcodeForOffset(CSOpcode, Disp);
02884   assert(LOpcode && CSOpcode && "Displacement out of range");
02885 
02886   // Create virtual registers for temporary results.
02887   unsigned OrigVal       = MRI.createVirtualRegister(RC);
02888   unsigned OldVal        = MRI.createVirtualRegister(RC);
02889   unsigned NewVal        = MRI.createVirtualRegister(RC);
02890   unsigned RotatedOldVal = (IsSubWord ? MRI.createVirtualRegister(RC) : OldVal);
02891   unsigned RotatedAltVal = (IsSubWord ? MRI.createVirtualRegister(RC) : Src2);
02892   unsigned RotatedNewVal = (IsSubWord ? MRI.createVirtualRegister(RC) : NewVal);
02893 
02894   // Insert 3 basic blocks for the loop.
02895   MachineBasicBlock *StartMBB  = MBB;
02896   MachineBasicBlock *DoneMBB   = splitBlockBefore(MI, MBB);
02897   MachineBasicBlock *LoopMBB   = emitBlockAfter(StartMBB);
02898   MachineBasicBlock *UseAltMBB = emitBlockAfter(LoopMBB);
02899   MachineBasicBlock *UpdateMBB = emitBlockAfter(UseAltMBB);
02900 
02901   //  StartMBB:
02902   //   ...
02903   //   %OrigVal     = L Disp(%Base)
02904   //   # fall through to LoopMMB
02905   MBB = StartMBB;
02906   BuildMI(MBB, DL, TII->get(LOpcode), OrigVal)
02907     .addOperand(Base).addImm(Disp).addReg(0);
02908   MBB->addSuccessor(LoopMBB);
02909 
02910   //  LoopMBB:
02911   //   %OldVal        = phi [ %OrigVal, StartMBB ], [ %Dest, UpdateMBB ]
02912   //   %RotatedOldVal = RLL %OldVal, 0(%BitShift)
02913   //   CompareOpcode %RotatedOldVal, %Src2
02914   //   BRC KeepOldMask, UpdateMBB
02915   MBB = LoopMBB;
02916   BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
02917     .addReg(OrigVal).addMBB(StartMBB)
02918     .addReg(Dest).addMBB(UpdateMBB);
02919   if (IsSubWord)
02920     BuildMI(MBB, DL, TII->get(SystemZ::RLL), RotatedOldVal)
02921       .addReg(OldVal).addReg(BitShift).addImm(0);
02922   BuildMI(MBB, DL, TII->get(CompareOpcode))
02923     .addReg(RotatedOldVal).addReg(Src2);
02924   BuildMI(MBB, DL, TII->get(SystemZ::BRC))
02925     .addImm(SystemZ::CCMASK_ICMP).addImm(KeepOldMask).addMBB(UpdateMBB);
02926   MBB->addSuccessor(UpdateMBB);
02927   MBB->addSuccessor(UseAltMBB);
02928 
02929   //  UseAltMBB:
02930   //   %RotatedAltVal = RISBG %RotatedOldVal, %Src2, 32, 31 + BitSize, 0
02931   //   # fall through to UpdateMMB
02932   MBB = UseAltMBB;
02933   if (IsSubWord)
02934     BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RotatedAltVal)
02935       .addReg(RotatedOldVal).addReg(Src2)
02936       .addImm(32).addImm(31 + BitSize).addImm(0);
02937   MBB->addSuccessor(UpdateMBB);
02938 
02939   //  UpdateMBB:
02940   //   %RotatedNewVal = PHI [ %RotatedOldVal, LoopMBB ],
02941   //                        [ %RotatedAltVal, UseAltMBB ]
02942   //   %NewVal        = RLL %RotatedNewVal, 0(%NegBitShift)
02943   //   %Dest          = CS %OldVal, %NewVal, Disp(%Base)
02944   //   JNE LoopMBB
02945   //   # fall through to DoneMMB
02946   MBB = UpdateMBB;
02947   BuildMI(MBB, DL, TII->get(SystemZ::PHI), RotatedNewVal)
02948     .addReg(RotatedOldVal).addMBB(LoopMBB)
02949     .addReg(RotatedAltVal).addMBB(UseAltMBB);
02950   if (IsSubWord)
02951     BuildMI(MBB, DL, TII->get(SystemZ::RLL), NewVal)
02952       .addReg(RotatedNewVal).addReg(NegBitShift).addImm(0);
02953   BuildMI(MBB, DL, TII->get(CSOpcode), Dest)
02954     .addReg(OldVal).addReg(NewVal).addOperand(Base).addImm(Disp);
02955   BuildMI(MBB, DL, TII->get(SystemZ::BRC))
02956     .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
02957   MBB->addSuccessor(LoopMBB);
02958   MBB->addSuccessor(DoneMBB);
02959 
02960   MI->eraseFromParent();
02961   return DoneMBB;
02962 }
02963 
02964 // Implement EmitInstrWithCustomInserter for pseudo ATOMIC_CMP_SWAPW
02965 // instruction MI.
02966 MachineBasicBlock *
02967 SystemZTargetLowering::emitAtomicCmpSwapW(MachineInstr *MI,
02968                                           MachineBasicBlock *MBB) const {
02969   MachineFunction &MF = *MBB->getParent();
02970   const SystemZInstrInfo *TII =
02971       static_cast<const SystemZInstrInfo *>(MF.getTarget().getInstrInfo());
02972   MachineRegisterInfo &MRI = MF.getRegInfo();
02973 
02974   // Extract the operands.  Base can be a register or a frame index.
02975   unsigned Dest        = MI->getOperand(0).getReg();
02976   MachineOperand Base  = earlyUseOperand(MI->getOperand(1));
02977   int64_t  Disp        = MI->getOperand(2).getImm();
02978   unsigned OrigCmpVal  = MI->getOperand(3).getReg();
02979   unsigned OrigSwapVal = MI->getOperand(4).getReg();
02980   unsigned BitShift    = MI->getOperand(5).getReg();
02981   unsigned NegBitShift = MI->getOperand(6).getReg();
02982   int64_t  BitSize     = MI->getOperand(7).getImm();
02983   DebugLoc DL          = MI->getDebugLoc();
02984 
02985   const TargetRegisterClass *RC = &SystemZ::GR32BitRegClass;
02986 
02987   // Get the right opcodes for the displacement.
02988   unsigned LOpcode  = TII->getOpcodeForOffset(SystemZ::L,  Disp);
02989   unsigned CSOpcode = TII->getOpcodeForOffset(SystemZ::CS, Disp);
02990   assert(LOpcode && CSOpcode && "Displacement out of range");
02991 
02992   // Create virtual registers for temporary results.
02993   unsigned OrigOldVal   = MRI.createVirtualRegister(RC);
02994   unsigned OldVal       = MRI.createVirtualRegister(RC);
02995   unsigned CmpVal       = MRI.createVirtualRegister(RC);
02996   unsigned SwapVal      = MRI.createVirtualRegister(RC);
02997   unsigned StoreVal     = MRI.createVirtualRegister(RC);
02998   unsigned RetryOldVal  = MRI.createVirtualRegister(RC);
02999   unsigned RetryCmpVal  = MRI.createVirtualRegister(RC);
03000   unsigned RetrySwapVal = MRI.createVirtualRegister(RC);
03001 
03002   // Insert 2 basic blocks for the loop.
03003   MachineBasicBlock *StartMBB = MBB;
03004   MachineBasicBlock *DoneMBB  = splitBlockBefore(MI, MBB);
03005   MachineBasicBlock *LoopMBB  = emitBlockAfter(StartMBB);
03006   MachineBasicBlock *SetMBB   = emitBlockAfter(LoopMBB);
03007 
03008   //  StartMBB:
03009   //   ...
03010   //   %OrigOldVal     = L Disp(%Base)
03011   //   # fall through to LoopMMB
03012   MBB = StartMBB;
03013   BuildMI(MBB, DL, TII->get(LOpcode), OrigOldVal)
03014     .addOperand(Base).addImm(Disp).addReg(0);
03015   MBB->addSuccessor(LoopMBB);
03016 
03017   //  LoopMBB:
03018   //   %OldVal        = phi [ %OrigOldVal, EntryBB ], [ %RetryOldVal, SetMBB ]
03019   //   %CmpVal        = phi [ %OrigCmpVal, EntryBB ], [ %RetryCmpVal, SetMBB ]
03020   //   %SwapVal       = phi [ %OrigSwapVal, EntryBB ], [ %RetrySwapVal, SetMBB ]
03021   //   %Dest          = RLL %OldVal, BitSize(%BitShift)
03022   //                      ^^ The low BitSize bits contain the field
03023   //                         of interest.
03024   //   %RetryCmpVal   = RISBG32 %CmpVal, %Dest, 32, 63-BitSize, 0
03025   //                      ^^ Replace the upper 32-BitSize bits of the
03026   //                         comparison value with those that we loaded,
03027   //                         so that we can use a full word comparison.
03028   //   CR %Dest, %RetryCmpVal
03029   //   JNE DoneMBB
03030   //   # Fall through to SetMBB
03031   MBB = LoopMBB;
03032   BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
03033     .addReg(OrigOldVal).addMBB(StartMBB)
03034     .addReg(RetryOldVal).addMBB(SetMBB);
03035   BuildMI(MBB, DL, TII->get(SystemZ::PHI), CmpVal)
03036     .addReg(OrigCmpVal).addMBB(StartMBB)
03037     .addReg(RetryCmpVal).addMBB(SetMBB);
03038   BuildMI(MBB, DL, TII->get(SystemZ::PHI), SwapVal)
03039     .addReg(OrigSwapVal).addMBB(StartMBB)
03040     .addReg(RetrySwapVal).addMBB(SetMBB);
03041   BuildMI(MBB, DL, TII->get(SystemZ::RLL), Dest)
03042     .addReg(OldVal).addReg(BitShift).addImm(BitSize);
03043   BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RetryCmpVal)
03044     .addReg(CmpVal).addReg(Dest).addImm(32).addImm(63 - BitSize).addImm(0);
03045   BuildMI(MBB, DL, TII->get(SystemZ::CR))
03046     .addReg(Dest).addReg(RetryCmpVal);
03047   BuildMI(MBB, DL, TII->get(SystemZ::BRC))
03048     .addImm(SystemZ::CCMASK_ICMP)
03049     .addImm(SystemZ::CCMASK_CMP_NE).addMBB(DoneMBB);
03050   MBB->addSuccessor(DoneMBB);
03051   MBB->addSuccessor(SetMBB);
03052 
03053   //  SetMBB:
03054   //   %RetrySwapVal = RISBG32 %SwapVal, %Dest, 32, 63-BitSize, 0
03055   //                      ^^ Replace the upper 32-BitSize bits of the new
03056   //                         value with those that we loaded.
03057   //   %StoreVal    = RLL %RetrySwapVal, -BitSize(%NegBitShift)
03058   //                      ^^ Rotate the new field to its proper position.
03059   //   %RetryOldVal = CS %Dest, %StoreVal, Disp(%Base)
03060   //   JNE LoopMBB
03061   //   # fall through to ExitMMB
03062   MBB = SetMBB;
03063   BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RetrySwapVal)
03064     .addReg(SwapVal).addReg(Dest).addImm(32).addImm(63 - BitSize).addImm(0);
03065   BuildMI(MBB, DL, TII->get(SystemZ::RLL), StoreVal)
03066     .addReg(RetrySwapVal).addReg(NegBitShift).addImm(-BitSize);
03067   BuildMI(MBB, DL, TII->get(CSOpcode), RetryOldVal)
03068     .addReg(OldVal).addReg(StoreVal).addOperand(Base).addImm(Disp);
03069   BuildMI(MBB, DL, TII->get(SystemZ::BRC))
03070     .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
03071   MBB->addSuccessor(LoopMBB);
03072   MBB->addSuccessor(DoneMBB);
03073 
03074   MI->eraseFromParent();
03075   return DoneMBB;
03076 }
03077 
03078 // Emit an extension from a GR32 or GR64 to a GR128.  ClearEven is true
03079 // if the high register of the GR128 value must be cleared or false if
03080 // it's "don't care".  SubReg is subreg_l32 when extending a GR32
03081 // and subreg_l64 when extending a GR64.
03082 MachineBasicBlock *
03083 SystemZTargetLowering::emitExt128(MachineInstr *MI,
03084                                   MachineBasicBlock *MBB,
03085                                   bool ClearEven, unsigned SubReg) const {
03086   MachineFunction &MF = *MBB->getParent();
03087   const SystemZInstrInfo *TII =
03088       static_cast<const SystemZInstrInfo *>(MF.getTarget().getInstrInfo());
03089   MachineRegisterInfo &MRI = MF.getRegInfo();
03090   DebugLoc DL = MI->getDebugLoc();
03091 
03092   unsigned Dest  = MI->getOperand(0).getReg();
03093   unsigned Src   = MI->getOperand(1).getReg();
03094   unsigned In128 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
03095 
03096   BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::IMPLICIT_DEF), In128);
03097   if (ClearEven) {
03098     unsigned NewIn128 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
03099     unsigned Zero64   = MRI.createVirtualRegister(&SystemZ::GR64BitRegClass);
03100 
03101     BuildMI(*MBB, MI, DL, TII->get(SystemZ::LLILL), Zero64)
03102       .addImm(0);
03103     BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), NewIn128)
03104       .addReg(In128).addReg(Zero64).addImm(SystemZ::subreg_h64);
03105     In128 = NewIn128;
03106   }
03107   BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), Dest)
03108     .addReg(In128).addReg(Src).addImm(SubReg);
03109 
03110   MI->eraseFromParent();
03111   return MBB;
03112 }
03113 
03114 MachineBasicBlock *
03115 SystemZTargetLowering::emitMemMemWrapper(MachineInstr *MI,
03116                                          MachineBasicBlock *MBB,
03117                                          unsigned Opcode) const {
03118   MachineFunction &MF = *MBB->getParent();
03119   const SystemZInstrInfo *TII =
03120       static_cast<const SystemZInstrInfo *>(MF.getTarget().getInstrInfo());
03121   MachineRegisterInfo &MRI = MF.getRegInfo();
03122   DebugLoc DL = MI->getDebugLoc();
03123 
03124   MachineOperand DestBase = earlyUseOperand(MI->getOperand(0));
03125   uint64_t       DestDisp = MI->getOperand(1).getImm();
03126   MachineOperand SrcBase  = earlyUseOperand(MI->getOperand(2));
03127   uint64_t       SrcDisp  = MI->getOperand(3).getImm();
03128   uint64_t       Length   = MI->getOperand(4).getImm();
03129 
03130   // When generating more than one CLC, all but the last will need to
03131   // branch to the end when a difference is found.
03132   MachineBasicBlock *EndMBB = (Length > 256 && Opcode == SystemZ::CLC ?
03133                                splitBlockAfter(MI, MBB) : nullptr);
03134 
03135   // Check for the loop form, in which operand 5 is the trip count.
03136   if (MI->getNumExplicitOperands() > 5) {
03137     bool HaveSingleBase = DestBase.isIdenticalTo(SrcBase);
03138 
03139     uint64_t StartCountReg = MI->getOperand(5).getReg();
03140     uint64_t StartSrcReg   = forceReg(MI, SrcBase, TII);
03141     uint64_t StartDestReg  = (HaveSingleBase ? StartSrcReg :
03142                               forceReg(MI, DestBase, TII));
03143 
03144     const TargetRegisterClass *RC = &SystemZ::ADDR64BitRegClass;
03145     uint64_t ThisSrcReg  = MRI.createVirtualRegister(RC);
03146     uint64_t ThisDestReg = (HaveSingleBase ? ThisSrcReg :
03147                             MRI.createVirtualRegister(RC));
03148     uint64_t NextSrcReg  = MRI.createVirtualRegister(RC);
03149     uint64_t NextDestReg = (HaveSingleBase ? NextSrcReg :
03150                             MRI.createVirtualRegister(RC));
03151 
03152     RC = &SystemZ::GR64BitRegClass;
03153     uint64_t ThisCountReg = MRI.createVirtualRegister(RC);
03154     uint64_t NextCountReg = MRI.createVirtualRegister(RC);
03155 
03156     MachineBasicBlock *StartMBB = MBB;
03157     MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
03158     MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
03159     MachineBasicBlock *NextMBB = (EndMBB ? emitBlockAfter(LoopMBB) : LoopMBB);
03160 
03161     //  StartMBB:
03162     //   # fall through to LoopMMB
03163     MBB->addSuccessor(LoopMBB);
03164 
03165     //  LoopMBB:
03166     //   %ThisDestReg = phi [ %StartDestReg, StartMBB ],
03167     //                      [ %NextDestReg, NextMBB ]
03168     //   %ThisSrcReg = phi [ %StartSrcReg, StartMBB ],
03169     //                     [ %NextSrcReg, NextMBB ]
03170     //   %ThisCountReg = phi [ %StartCountReg, StartMBB ],
03171     //                       [ %NextCountReg, NextMBB ]
03172     //   ( PFD 2, 768+DestDisp(%ThisDestReg) )
03173     //   Opcode DestDisp(256,%ThisDestReg), SrcDisp(%ThisSrcReg)
03174     //   ( JLH EndMBB )
03175     //
03176     // The prefetch is used only for MVC.  The JLH is used only for CLC.
03177     MBB = LoopMBB;
03178 
03179     BuildMI(MBB, DL, TII->get(SystemZ::PHI), ThisDestReg)
03180       .addReg(StartDestReg).addMBB(StartMBB)
03181       .addReg(NextDestReg).addMBB(NextMBB);
03182     if (!HaveSingleBase)
03183       BuildMI(MBB, DL, TII->get(SystemZ::PHI), ThisSrcReg)
03184         .addReg(StartSrcReg).addMBB(StartMBB)
03185         .addReg(NextSrcReg).addMBB(NextMBB);
03186     BuildMI(MBB, DL, TII->get(SystemZ::PHI), ThisCountReg)
03187       .addReg(StartCountReg).addMBB(StartMBB)
03188       .addReg(NextCountReg).addMBB(NextMBB);
03189     if (Opcode == SystemZ::MVC)
03190       BuildMI(MBB, DL, TII->get(SystemZ::PFD))
03191         .addImm(SystemZ::PFD_WRITE)
03192         .addReg(ThisDestReg).addImm(DestDisp + 768).addReg(0);
03193     BuildMI(MBB, DL, TII->get(Opcode))
03194       .addReg(ThisDestReg).addImm(DestDisp).addImm(256)
03195       .addReg(ThisSrcReg).addImm(SrcDisp);
03196     if (EndMBB) {
03197       BuildMI(MBB, DL, TII->get(SystemZ::BRC))
03198         .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_NE)
03199         .addMBB(EndMBB);
03200       MBB->addSuccessor(EndMBB);
03201       MBB->addSuccessor(NextMBB);
03202     }
03203 
03204     // NextMBB:
03205     //   %NextDestReg = LA 256(%ThisDestReg)
03206     //   %NextSrcReg = LA 256(%ThisSrcReg)
03207     //   %NextCountReg = AGHI %ThisCountReg, -1
03208     //   CGHI %NextCountReg, 0
03209     //   JLH LoopMBB
03210     //   # fall through to DoneMMB
03211     //
03212     // The AGHI, CGHI and JLH should be converted to BRCTG by later passes.
03213     MBB = NextMBB;
03214 
03215     BuildMI(MBB, DL, TII->get(SystemZ::LA), NextDestReg)
03216       .addReg(ThisDestReg).addImm(256).addReg(0);
03217     if (!HaveSingleBase)
03218       BuildMI(MBB, DL, TII->get(SystemZ::LA), NextSrcReg)
03219         .addReg(ThisSrcReg).addImm(256).addReg(0);
03220     BuildMI(MBB, DL, TII->get(SystemZ::AGHI), NextCountReg)
03221       .addReg(ThisCountReg).addImm(-1);
03222     BuildMI(MBB, DL, TII->get(SystemZ::CGHI))
03223       .addReg(NextCountReg).addImm(0);
03224     BuildMI(MBB, DL, TII->get(SystemZ::BRC))
03225       .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_NE)
03226       .addMBB(LoopMBB);
03227     MBB->addSuccessor(LoopMBB);
03228     MBB->addSuccessor(DoneMBB);
03229 
03230     DestBase = MachineOperand::CreateReg(NextDestReg, false);
03231     SrcBase = MachineOperand::CreateReg(NextSrcReg, false);
03232     Length &= 255;
03233     MBB = DoneMBB;
03234   }
03235   // Handle any remaining bytes with straight-line code.
03236   while (Length > 0) {
03237     uint64_t ThisLength = std::min(Length, uint64_t(256));
03238     // The previous iteration might have created out-of-range displacements.
03239     // Apply them using LAY if so.
03240     if (!isUInt<12>(DestDisp)) {
03241       unsigned Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
03242       BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(SystemZ::LAY), Reg)
03243         .addOperand(DestBase).addImm(DestDisp).addReg(0);
03244       DestBase = MachineOperand::CreateReg(Reg, false);
03245       DestDisp = 0;
03246     }
03247     if (!isUInt<12>(SrcDisp)) {
03248       unsigned Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
03249       BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(SystemZ::LAY), Reg)
03250         .addOperand(SrcBase).addImm(SrcDisp).addReg(0);
03251       SrcBase = MachineOperand::CreateReg(Reg, false);
03252       SrcDisp = 0;
03253     }
03254     BuildMI(*MBB, MI, DL, TII->get(Opcode))
03255       .addOperand(DestBase).addImm(DestDisp).addImm(ThisLength)
03256       .addOperand(SrcBase).addImm(SrcDisp);
03257     DestDisp += ThisLength;
03258     SrcDisp += ThisLength;
03259     Length -= ThisLength;
03260     // If there's another CLC to go, branch to the end if a difference
03261     // was found.
03262     if (EndMBB && Length > 0) {
03263       MachineBasicBlock *NextMBB = splitBlockBefore(MI, MBB);
03264       BuildMI(MBB, DL, TII->get(SystemZ::BRC))
03265         .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_NE)
03266         .addMBB(EndMBB);
03267       MBB->addSuccessor(EndMBB);
03268       MBB->addSuccessor(NextMBB);
03269       MBB = NextMBB;
03270     }
03271   }
03272   if (EndMBB) {
03273     MBB->addSuccessor(EndMBB);
03274     MBB = EndMBB;
03275     MBB->addLiveIn(SystemZ::CC);
03276   }
03277 
03278   MI->eraseFromParent();
03279   return MBB;
03280 }
03281 
03282 // Decompose string pseudo-instruction MI into a loop that continually performs
03283 // Opcode until CC != 3.
03284 MachineBasicBlock *
03285 SystemZTargetLowering::emitStringWrapper(MachineInstr *MI,
03286                                          MachineBasicBlock *MBB,
03287                                          unsigned Opcode) const {
03288   MachineFunction &MF = *MBB->getParent();
03289   const SystemZInstrInfo *TII =
03290       static_cast<const SystemZInstrInfo *>(MF.getTarget().getInstrInfo());
03291   MachineRegisterInfo &MRI = MF.getRegInfo();
03292   DebugLoc DL = MI->getDebugLoc();
03293 
03294   uint64_t End1Reg   = MI->getOperand(0).getReg();
03295   uint64_t Start1Reg = MI->getOperand(1).getReg();
03296   uint64_t Start2Reg = MI->getOperand(2).getReg();
03297   uint64_t CharReg   = MI->getOperand(3).getReg();
03298 
03299   const TargetRegisterClass *RC = &SystemZ::GR64BitRegClass;
03300   uint64_t This1Reg = MRI.createVirtualRegister(RC);
03301   uint64_t This2Reg = MRI.createVirtualRegister(RC);
03302   uint64_t End2Reg  = MRI.createVirtualRegister(RC);
03303 
03304   MachineBasicBlock *StartMBB = MBB;
03305   MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
03306   MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
03307 
03308   //  StartMBB:
03309   //   # fall through to LoopMMB
03310   MBB->addSuccessor(LoopMBB);
03311 
03312   //  LoopMBB:
03313   //   %This1Reg = phi [ %Start1Reg, StartMBB ], [ %End1Reg, LoopMBB ]
03314   //   %This2Reg = phi [ %Start2Reg, StartMBB ], [ %End2Reg, LoopMBB ]
03315   //   R0L = %CharReg
03316   //   %End1Reg, %End2Reg = CLST %This1Reg, %This2Reg -- uses R0L
03317   //   JO LoopMBB
03318   //   # fall through to DoneMMB
03319   //
03320   // The load of R0L can be hoisted by post-RA LICM.
03321   MBB = LoopMBB;
03322 
03323   BuildMI(MBB, DL, TII->get(SystemZ::PHI), This1Reg)
03324     .addReg(Start1Reg).addMBB(StartMBB)
03325     .addReg(End1Reg).addMBB(LoopMBB);
03326   BuildMI(MBB, DL, TII->get(SystemZ::PHI), This2Reg)
03327     .addReg(Start2Reg).addMBB(StartMBB)
03328     .addReg(End2Reg).addMBB(LoopMBB);
03329   BuildMI(MBB, DL, TII->get(TargetOpcode::COPY), SystemZ::R0L).addReg(CharReg);
03330   BuildMI(MBB, DL, TII->get(Opcode))
03331     .addReg(End1Reg, RegState::Define).addReg(End2Reg, RegState::Define)
03332     .addReg(This1Reg).addReg(This2Reg);
03333   BuildMI(MBB, DL, TII->get(SystemZ::BRC))
03334     .addImm(SystemZ::CCMASK_ANY).addImm(SystemZ::CCMASK_3).addMBB(LoopMBB);
03335   MBB->addSuccessor(LoopMBB);
03336   MBB->addSuccessor(DoneMBB);
03337 
03338   DoneMBB->addLiveIn(SystemZ::CC);
03339 
03340   MI->eraseFromParent();
03341   return DoneMBB;
03342 }
03343 
03344 MachineBasicBlock *SystemZTargetLowering::
03345 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const {
03346   switch (MI->getOpcode()) {
03347   case SystemZ::Select32Mux:
03348   case SystemZ::Select32:
03349   case SystemZ::SelectF32:
03350   case SystemZ::Select64:
03351   case SystemZ::SelectF64:
03352   case SystemZ::SelectF128:
03353     return emitSelect(MI, MBB);
03354 
03355   case SystemZ::CondStore8Mux:
03356     return emitCondStore(MI, MBB, SystemZ::STCMux, 0, false);
03357   case SystemZ::CondStore8MuxInv:
03358     return emitCondStore(MI, MBB, SystemZ::STCMux, 0, true);
03359   case SystemZ::CondStore16Mux:
03360     return emitCondStore(MI, MBB, SystemZ::STHMux, 0, false);
03361   case SystemZ::CondStore16MuxInv:
03362     return emitCondStore(MI, MBB, SystemZ::STHMux, 0, true);
03363   case SystemZ::CondStore8:
03364     return emitCondStore(MI, MBB, SystemZ::STC, 0, false);
03365   case SystemZ::CondStore8Inv:
03366     return emitCondStore(MI, MBB, SystemZ::STC, 0, true);
03367   case SystemZ::CondStore16:
03368     return emitCondStore(MI, MBB, SystemZ::STH, 0, false);
03369   case SystemZ::CondStore16Inv:
03370     return emitCondStore(MI, MBB, SystemZ::STH, 0, true);
03371   case SystemZ::CondStore32:
03372     return emitCondStore(MI, MBB, SystemZ::ST, SystemZ::STOC, false);
03373   case SystemZ::CondStore32Inv:
03374     return emitCondStore(MI, MBB, SystemZ::ST, SystemZ::STOC, true);
03375   case SystemZ::CondStore64:
03376     return emitCondStore(MI, MBB, SystemZ::STG, SystemZ::STOCG, false);
03377   case SystemZ::CondStore64Inv:
03378     return emitCondStore(MI, MBB, SystemZ::STG, SystemZ::STOCG, true);
03379   case SystemZ::CondStoreF32:
03380     return emitCondStore(MI, MBB, SystemZ::STE, 0, false);
03381   case SystemZ::CondStoreF32Inv:
03382     return emitCondStore(MI, MBB, SystemZ::STE, 0, true);
03383   case SystemZ::CondStoreF64:
03384     return emitCondStore(MI, MBB, SystemZ::STD, 0, false);
03385   case SystemZ::CondStoreF64Inv:
03386     return emitCondStore(MI, MBB, SystemZ::STD, 0, true);
03387 
03388   case SystemZ::AEXT128_64:
03389     return emitExt128(MI, MBB, false, SystemZ::subreg_l64);
03390   case SystemZ::ZEXT128_32:
03391     return emitExt128(MI, MBB, true, SystemZ::subreg_l32);
03392   case SystemZ::ZEXT128_64:
03393     return emitExt128(MI, MBB, true, SystemZ::subreg_l64);
03394 
03395   case SystemZ::ATOMIC_SWAPW:
03396     return emitAtomicLoadBinary(MI, MBB, 0, 0);
03397   case SystemZ::ATOMIC_SWAP_32:
03398     return emitAtomicLoadBinary(MI, MBB, 0, 32);
03399   case SystemZ::ATOMIC_SWAP_64:
03400     return emitAtomicLoadBinary(MI, MBB, 0, 64);
03401 
03402   case SystemZ::ATOMIC_LOADW_AR:
03403     return emitAtomicLoadBinary(MI, MBB, SystemZ::AR, 0);
03404   case SystemZ::ATOMIC_LOADW_AFI:
03405     return emitAtomicLoadBinary(MI, MBB, SystemZ::AFI, 0);
03406   case SystemZ::ATOMIC_LOAD_AR:
03407     return emitAtomicLoadBinary(MI, MBB, SystemZ::AR, 32);
03408   case SystemZ::ATOMIC_LOAD_AHI:
03409     return emitAtomicLoadBinary(MI, MBB, SystemZ::AHI, 32);
03410   case SystemZ::ATOMIC_LOAD_AFI:
03411     return emitAtomicLoadBinary(MI, MBB, SystemZ::AFI, 32);
03412   case SystemZ::ATOMIC_LOAD_AGR:
03413     return emitAtomicLoadBinary(MI, MBB, SystemZ::AGR, 64);
03414   case SystemZ::ATOMIC_LOAD_AGHI:
03415     return emitAtomicLoadBinary(MI, MBB, SystemZ::AGHI, 64);
03416   case SystemZ::ATOMIC_LOAD_AGFI:
03417     return emitAtomicLoadBinary(MI, MBB, SystemZ::AGFI, 64);
03418 
03419   case SystemZ::ATOMIC_LOADW_SR:
03420     return emitAtomicLoadBinary(MI, MBB, SystemZ::SR, 0);
03421   case SystemZ::ATOMIC_LOAD_SR:
03422     return emitAtomicLoadBinary(MI, MBB, SystemZ::SR, 32);
03423   case SystemZ::ATOMIC_LOAD_SGR:
03424     return emitAtomicLoadBinary(MI, MBB, SystemZ::SGR, 64);
03425 
03426   case SystemZ::ATOMIC_LOADW_NR:
03427     return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 0);
03428   case SystemZ::ATOMIC_LOADW_NILH:
03429     return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 0);
03430   case SystemZ::ATOMIC_LOAD_NR:
03431     return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 32);
03432   case SystemZ::ATOMIC_LOAD_NILL:
03433     return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL, 32);
03434   case SystemZ::ATOMIC_LOAD_NILH:
03435     return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 32);
03436   case SystemZ::ATOMIC_LOAD_NILF:
03437     return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF, 32);
03438   case SystemZ::ATOMIC_LOAD_NGR:
03439     return emitAtomicLoadBinary(MI, MBB, SystemZ::NGR, 64);
03440   case SystemZ::ATOMIC_LOAD_NILL64:
03441     return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL64, 64);
03442   case SystemZ::ATOMIC_LOAD_NILH64:
03443     return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH64, 64);
03444   case SystemZ::ATOMIC_LOAD_NIHL64:
03445     return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHL64, 64);
03446   case SystemZ::ATOMIC_LOAD_NIHH64:
03447     return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHH64, 64);
03448   case SystemZ::ATOMIC_LOAD_NILF64:
03449     return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF64, 64);
03450   case SystemZ::ATOMIC_LOAD_NIHF64:
03451     return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHF64, 64);
03452 
03453   case SystemZ::ATOMIC_LOADW_OR:
03454     return emitAtomicLoadBinary(MI, MBB, SystemZ::OR, 0);
03455   case SystemZ::ATOMIC_LOADW_OILH:
03456     return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH, 0);
03457   case SystemZ::ATOMIC_LOAD_OR:
03458     return emitAtomicLoadBinary(MI, MBB, SystemZ::OR, 32);
03459   case SystemZ::ATOMIC_LOAD_OILL:
03460     return emitAtomicLoadBinary(MI, MBB, SystemZ::OILL, 32);
03461   case SystemZ::ATOMIC_LOAD_OILH:
03462     return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH, 32);
03463   case SystemZ::ATOMIC_LOAD_OILF:
03464     return emitAtomicLoadBinary(MI, MBB, SystemZ::OILF, 32);
03465   case SystemZ::ATOMIC_LOAD_OGR:
03466     return emitAtomicLoadBinary(MI, MBB, SystemZ::OGR, 64);
03467   case SystemZ::ATOMIC_LOAD_OILL64:
03468     return emitAtomicLoadBinary(MI, MBB, SystemZ::OILL64, 64);
03469   case SystemZ::ATOMIC_LOAD_OILH64:
03470     return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH64, 64);
03471   case SystemZ::ATOMIC_LOAD_OIHL64:
03472     return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHL64, 64);
03473   case SystemZ::ATOMIC_LOAD_OIHH64:
03474     return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHH64, 64);
03475   case SystemZ::ATOMIC_LOAD_OILF64:
03476     return emitAtomicLoadBinary(MI, MBB, SystemZ::OILF64, 64);
03477   case SystemZ::ATOMIC_LOAD_OIHF64:
03478     return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHF64, 64);
03479 
03480   case SystemZ::ATOMIC_LOADW_XR:
03481     return emitAtomicLoadBinary(MI, MBB, SystemZ::XR, 0);
03482   case SystemZ::ATOMIC_LOADW_XILF:
03483     return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF, 0);
03484   case SystemZ::ATOMIC_LOAD_XR:
03485     return emitAtomicLoadBinary(MI, MBB, SystemZ::XR, 32);
03486   case SystemZ::ATOMIC_LOAD_XILF:
03487     return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF, 32);
03488   case SystemZ::ATOMIC_LOAD_XGR:
03489     return emitAtomicLoadBinary(MI, MBB, SystemZ::XGR, 64);
03490   case SystemZ::ATOMIC_LOAD_XILF64:
03491     return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF64, 64);
03492   case SystemZ::ATOMIC_LOAD_XIHF64:
03493     return emitAtomicLoadBinary(MI, MBB, SystemZ::XIHF64, 64);
03494 
03495   case SystemZ::ATOMIC_LOADW_NRi:
03496     return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 0, true);
03497   case SystemZ::ATOMIC_LOADW_NILHi:
03498     return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 0, true);
03499   case SystemZ::ATOMIC_LOAD_NRi:
03500     return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 32, true);
03501   case SystemZ::ATOMIC_LOAD_NILLi:
03502     return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL, 32, true);
03503   case SystemZ::ATOMIC_LOAD_NILHi:
03504     return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 32, true);
03505   case SystemZ::ATOMIC_LOAD_NILFi:
03506     return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF, 32, true);
03507   case SystemZ::ATOMIC_LOAD_NGRi:
03508     return emitAtomicLoadBinary(MI, MBB, SystemZ::NGR, 64, true);
03509   case SystemZ::ATOMIC_LOAD_NILL64i:
03510     return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL64, 64, true);
03511   case SystemZ::ATOMIC_LOAD_NILH64i:
03512     return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH64, 64, true);
03513   case SystemZ::ATOMIC_LOAD_NIHL64i:
03514     return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHL64, 64, true);
03515   case SystemZ::ATOMIC_LOAD_NIHH64i:
03516     return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHH64, 64, true);
03517   case SystemZ::ATOMIC_LOAD_NILF64i:
03518     return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF64, 64, true);
03519   case SystemZ::ATOMIC_LOAD_NIHF64i:
03520     return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHF64, 64, true);
03521 
03522   case SystemZ::ATOMIC_LOADW_MIN:
03523     return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
03524                                 SystemZ::CCMASK_CMP_LE, 0);
03525   case SystemZ::ATOMIC_LOAD_MIN_32:
03526     return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
03527                                 SystemZ::CCMASK_CMP_LE, 32);
03528   case SystemZ::ATOMIC_LOAD_MIN_64:
03529     return emitAtomicLoadMinMax(MI, MBB, SystemZ::CGR,
03530                                 SystemZ::CCMASK_CMP_LE, 64);
03531 
03532   case SystemZ::ATOMIC_LOADW_MAX:
03533     return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
03534                                 SystemZ::CCMASK_CMP_GE, 0);
03535   case SystemZ::ATOMIC_LOAD_MAX_32:
03536     return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
03537                                 SystemZ::CCMASK_CMP_GE, 32);
03538   case SystemZ::ATOMIC_LOAD_MAX_64:
03539     return emitAtomicLoadMinMax(MI, MBB, SystemZ::CGR,
03540                                 SystemZ::CCMASK_CMP_GE, 64);
03541 
03542   case SystemZ::ATOMIC_LOADW_UMIN:
03543     return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
03544                                 SystemZ::CCMASK_CMP_LE, 0);
03545   case SystemZ::ATOMIC_LOAD_UMIN_32:
03546     return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
03547                                 SystemZ::CCMASK_CMP_LE, 32);
03548   case SystemZ::ATOMIC_LOAD_UMIN_64:
03549     return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLGR,
03550                                 SystemZ::CCMASK_CMP_LE, 64);
03551 
03552   case SystemZ::ATOMIC_LOADW_UMAX:
03553     return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
03554                                 SystemZ::CCMASK_CMP_GE, 0);
03555   case SystemZ::ATOMIC_LOAD_UMAX_32:
03556     return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
03557                                 SystemZ::CCMASK_CMP_GE, 32);
03558   case SystemZ::ATOMIC_LOAD_UMAX_64:
03559     return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLGR,
03560                                 SystemZ::CCMASK_CMP_GE, 64);
03561 
03562   case SystemZ::ATOMIC_CMP_SWAPW:
03563     return emitAtomicCmpSwapW(MI, MBB);
03564   case SystemZ::MVCSequence:
03565   case SystemZ::MVCLoop:
03566     return emitMemMemWrapper(MI, MBB, SystemZ::MVC);
03567   case SystemZ::NCSequence:
03568   case SystemZ::NCLoop:
03569     return emitMemMemWrapper(MI, MBB, SystemZ::NC);
03570   case SystemZ::OCSequence:
03571   case SystemZ::OCLoop:
03572     return emitMemMemWrapper(MI, MBB, SystemZ::OC);
03573   case SystemZ::XCSequence:
03574   case SystemZ::XCLoop:
03575     return emitMemMemWrapper(MI, MBB, SystemZ::XC);
03576   case SystemZ::CLCSequence:
03577   case SystemZ::CLCLoop:
03578     return emitMemMemWrapper(MI, MBB, SystemZ::CLC);
03579   case SystemZ::CLSTLoop:
03580     return emitStringWrapper(MI, MBB, SystemZ::CLST);
03581   case SystemZ::MVSTLoop:
03582     return emitStringWrapper(MI, MBB, SystemZ::MVST);
03583   case SystemZ::SRSTLoop:
03584     return emitStringWrapper(MI, MBB, SystemZ::SRST);
03585   default:
03586     llvm_unreachable("Unexpected instr type to insert");
03587   }
03588 }