LLVM 19.0.0git
TargetTransformInfoImpl.h
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1//===- TargetTransformInfoImpl.h --------------------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This file provides helpers for the implementation of
10/// a TargetTransformInfo-conforming class.
11///
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_ANALYSIS_TARGETTRANSFORMINFOIMPL_H
15#define LLVM_ANALYSIS_TARGETTRANSFORMINFOIMPL_H
16
20#include "llvm/IR/DataLayout.h"
23#include "llvm/IR/Operator.h"
25#include <optional>
26#include <utility>
27
28namespace llvm {
29
30class Function;
31
32/// Base class for use as a mix-in that aids implementing
33/// a TargetTransformInfo-compatible class.
35protected:
37
38 const DataLayout &DL;
39
41
42public:
43 // Provide value semantics. MSVC requires that we spell all of these out.
46
47 const DataLayout &getDataLayout() const { return DL; }
48
49 InstructionCost getGEPCost(Type *PointeeType, const Value *Ptr,
52 // In the basic model, we just assume that all-constant GEPs will be folded
53 // into their uses via addressing modes.
54 for (const Value *Operand : Operands)
55 if (!isa<Constant>(Operand))
56 return TTI::TCC_Basic;
57
58 return TTI::TCC_Free;
59 }
60
62 unsigned &JTSize,
64 BlockFrequencyInfo *BFI) const {
65 (void)PSI;
66 (void)BFI;
67 JTSize = 0;
68 return SI.getNumCases();
69 }
70
71 unsigned getInliningThresholdMultiplier() const { return 1; }
74 return 8;
75 }
76 unsigned adjustInliningThreshold(const CallBase *CB) const { return 0; }
77 unsigned getCallerAllocaCost(const CallBase *CB, const AllocaInst *AI) const {
78 return 0;
79 };
80
81 int getInlinerVectorBonusPercent() const { return 150; }
82
84 return TTI::TCC_Expensive;
85 }
86
88 return 64;
89 }
90
91 // Although this default value is arbitrary, it is not random. It is assumed
92 // that a condition that evaluates the same way by a higher percentage than
93 // this is best represented as control flow. Therefore, the default value N
94 // should be set such that the win from N% correct executions is greater than
95 // the loss from (100 - N)% mispredicted executions for the majority of
96 // intended targets.
98 return BranchProbability(99, 100);
99 }
100
101 bool hasBranchDivergence(const Function *F = nullptr) const { return false; }
102
103 bool isSourceOfDivergence(const Value *V) const { return false; }
104
105 bool isAlwaysUniform(const Value *V) const { return false; }
106
107 bool isValidAddrSpaceCast(unsigned FromAS, unsigned ToAS) const {
108 return false;
109 }
110
111 bool addrspacesMayAlias(unsigned AS0, unsigned AS1) const {
112 return true;
113 }
114
115 unsigned getFlatAddressSpace() const { return -1; }
116
118 Intrinsic::ID IID) const {
119 return false;
120 }
121
122 bool isNoopAddrSpaceCast(unsigned, unsigned) const { return false; }
124 return AS == 0;
125 };
126
127 unsigned getAssumedAddrSpace(const Value *V) const { return -1; }
128
129 bool isSingleThreaded() const { return false; }
130
131 std::pair<const Value *, unsigned>
133 return std::make_pair(nullptr, -1);
134 }
135
137 Value *NewV) const {
138 return nullptr;
139 }
140
141 bool isLoweredToCall(const Function *F) const {
142 assert(F && "A concrete function must be provided to this routine.");
143
144 // FIXME: These should almost certainly not be handled here, and instead
145 // handled with the help of TLI or the target itself. This was largely
146 // ported from existing analysis heuristics here so that such refactorings
147 // can take place in the future.
148
149 if (F->isIntrinsic())
150 return false;
151
152 if (F->hasLocalLinkage() || !F->hasName())
153 return true;
154
155 StringRef Name = F->getName();
156
157 // These will all likely lower to a single selection DAG node.
158 if (Name == "copysign" || Name == "copysignf" || Name == "copysignl" ||
159 Name == "fabs" || Name == "fabsf" || Name == "fabsl" || Name == "sin" ||
160 Name == "fmin" || Name == "fminf" || Name == "fminl" ||
161 Name == "fmax" || Name == "fmaxf" || Name == "fmaxl" ||
162 Name == "sinf" || Name == "sinl" || Name == "cos" || Name == "cosf" ||
163 Name == "cosl" || Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl")
164 return false;
165
166 // These are all likely to be optimized into something smaller.
167 if (Name == "pow" || Name == "powf" || Name == "powl" || Name == "exp2" ||
168 Name == "exp2l" || Name == "exp2f" || Name == "floor" ||
169 Name == "floorf" || Name == "ceil" || Name == "round" ||
170 Name == "ffs" || Name == "ffsl" || Name == "abs" || Name == "labs" ||
171 Name == "llabs")
172 return false;
173
174 return true;
175 }
176
179 HardwareLoopInfo &HWLoopInfo) const {
180 return false;
181 }
182
183 bool preferPredicateOverEpilogue(TailFoldingInfo *TFI) const { return false; }
184
186 getPreferredTailFoldingStyle(bool IVUpdateMayOverflow = true) const {
188 }
189
190 std::optional<Instruction *> instCombineIntrinsic(InstCombiner &IC,
191 IntrinsicInst &II) const {
192 return std::nullopt;
193 }
194
195 std::optional<Value *>
197 APInt DemandedMask, KnownBits &Known,
198 bool &KnownBitsComputed) const {
199 return std::nullopt;
200 }
201
203 InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
204 APInt &UndefElts2, APInt &UndefElts3,
205 std::function<void(Instruction *, unsigned, APInt, APInt &)>
206 SimplifyAndSetOp) const {
207 return std::nullopt;
208 }
209
212 OptimizationRemarkEmitter *) const {}
213
215 TTI::PeelingPreferences &) const {}
216
217 bool isLegalAddImmediate(int64_t Imm) const { return false; }
218
219 bool isLegalAddScalableImmediate(int64_t Imm) const { return false; }
220
221 bool isLegalICmpImmediate(int64_t Imm) const { return false; }
222
223 bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset,
224 bool HasBaseReg, int64_t Scale, unsigned AddrSpace,
225 Instruction *I = nullptr,
226 int64_t ScalableOffset = 0) const {
227 // Guess that only reg and reg+reg addressing is allowed. This heuristic is
228 // taken from the implementation of LSR.
229 return !BaseGV && BaseOffset == 0 && (Scale == 0 || Scale == 1);
230 }
231
232 bool isLSRCostLess(const TTI::LSRCost &C1, const TTI::LSRCost &C2) const {
233 return std::tie(C1.NumRegs, C1.AddRecCost, C1.NumIVMuls, C1.NumBaseAdds,
234 C1.ScaleCost, C1.ImmCost, C1.SetupCost) <
235 std::tie(C2.NumRegs, C2.AddRecCost, C2.NumIVMuls, C2.NumBaseAdds,
236 C2.ScaleCost, C2.ImmCost, C2.SetupCost);
237 }
238
239 bool isNumRegsMajorCostOfLSR() const { return true; }
240
241 bool shouldFoldTerminatingConditionAfterLSR() const { return false; }
242
243 bool isProfitableLSRChainElement(Instruction *I) const { return false; }
244
245 bool canMacroFuseCmp() const { return false; }
246
249 TargetLibraryInfo *LibInfo) const {
250 return false;
251 }
252
255 return TTI::AMK_None;
256 }
257
258 bool isLegalMaskedStore(Type *DataType, Align Alignment) const {
259 return false;
260 }
261
262 bool isLegalMaskedLoad(Type *DataType, Align Alignment) const {
263 return false;
264 }
265
266 bool isLegalNTStore(Type *DataType, Align Alignment) const {
267 // By default, assume nontemporal memory stores are available for stores
268 // that are aligned and have a size that is a power of 2.
269 unsigned DataSize = DL.getTypeStoreSize(DataType);
270 return Alignment >= DataSize && isPowerOf2_32(DataSize);
271 }
272
273 bool isLegalNTLoad(Type *DataType, Align Alignment) const {
274 // By default, assume nontemporal memory loads are available for loads that
275 // are aligned and have a size that is a power of 2.
276 unsigned DataSize = DL.getTypeStoreSize(DataType);
277 return Alignment >= DataSize && isPowerOf2_32(DataSize);
278 }
279
280 bool isLegalBroadcastLoad(Type *ElementTy, ElementCount NumElements) const {
281 return false;
282 }
283
284 bool isLegalMaskedScatter(Type *DataType, Align Alignment) const {
285 return false;
286 }
287
288 bool isLegalMaskedGather(Type *DataType, Align Alignment) const {
289 return false;
290 }
291
292 bool forceScalarizeMaskedGather(VectorType *DataType, Align Alignment) const {
293 return false;
294 }
295
297 Align Alignment) const {
298 return false;
299 }
300
301 bool isLegalMaskedCompressStore(Type *DataType, Align Alignment) const {
302 return false;
303 }
304
305 bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
306 const SmallBitVector &OpcodeMask) const {
307 return false;
308 }
309
310 bool isLegalMaskedExpandLoad(Type *DataType, Align Alignment) const {
311 return false;
312 }
313
314 bool isLegalStridedLoadStore(Type *DataType, Align Alignment) const {
315 return false;
316 }
317
318 bool enableOrderedReductions() const { return false; }
319
320 bool hasDivRemOp(Type *DataType, bool IsSigned) const { return false; }
321
322 bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) const {
323 return false;
324 }
325
326 bool prefersVectorizedAddressing() const { return true; }
327
329 int64_t BaseOffset, bool HasBaseReg,
330 int64_t Scale,
331 unsigned AddrSpace) const {
332 // Guess that all legal addressing mode are free.
333 if (isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg, Scale,
334 AddrSpace))
335 return 0;
336 return -1;
337 }
338
339 bool LSRWithInstrQueries() const { return false; }
340
341 bool isTruncateFree(Type *Ty1, Type *Ty2) const { return false; }
342
343 bool isProfitableToHoist(Instruction *I) const { return true; }
344
345 bool useAA() const { return false; }
346
347 bool isTypeLegal(Type *Ty) const { return false; }
348
349 unsigned getRegUsageForType(Type *Ty) const { return 1; }
350
351 bool shouldBuildLookupTables() const { return true; }
352
353 bool shouldBuildLookupTablesForConstant(Constant *C) const { return true; }
354
355 bool shouldBuildRelLookupTables() const { return false; }
356
357 bool useColdCCForColdCall(Function &F) const { return false; }
358
360 const APInt &DemandedElts,
361 bool Insert, bool Extract,
363 return 0;
364 }
365
370 return 0;
371 }
372
373 bool supportsEfficientVectorElementLoadStore() const { return false; }
374
375 bool supportsTailCalls() const { return true; }
376
377 bool enableAggressiveInterleaving(bool LoopHasReductions) const {
378 return false;
379 }
380
382 bool IsZeroCmp) const {
383 return {};
384 }
385
386 bool enableSelectOptimize() const { return true; }
387
389 // If the select is a logical-and/logical-or then it is better treated as a
390 // and/or by the backend.
391 using namespace llvm::PatternMatch;
392 return isa<SelectInst>(I) &&
395 }
396
397 bool enableInterleavedAccessVectorization() const { return false; }
398
399 bool enableMaskedInterleavedAccessVectorization() const { return false; }
400
401 bool isFPVectorizationPotentiallyUnsafe() const { return false; }
402
404 unsigned AddressSpace, Align Alignment,
405 unsigned *Fast) const {
406 return false;
407 }
408
409 TTI::PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const {
410 return TTI::PSK_Software;
411 }
412
413 bool haveFastSqrt(Type *Ty) const { return false; }
414
415 bool isExpensiveToSpeculativelyExecute(const Instruction *I) { return true; }
416
417 bool isFCmpOrdCheaperThanFCmpZero(Type *Ty) const { return true; }
418
421 }
422
423 InstructionCost getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx,
424 const APInt &Imm, Type *Ty) const {
425 return 0;
426 }
427
430 return TTI::TCC_Basic;
431 }
432
433 InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx,
434 const APInt &Imm, Type *Ty,
436 Instruction *Inst = nullptr) const {
437 return TTI::TCC_Free;
438 }
439
441 const APInt &Imm, Type *Ty,
443 return TTI::TCC_Free;
444 }
445
447 const Function &Fn) const {
448 return false;
449 }
450
451 unsigned getNumberOfRegisters(unsigned ClassID) const { return 8; }
452
453 unsigned getRegisterClassForType(bool Vector, Type *Ty = nullptr) const {
454 return Vector ? 1 : 0;
455 };
456
457 const char *getRegisterClassName(unsigned ClassID) const {
458 switch (ClassID) {
459 default:
460 return "Generic::Unknown Register Class";
461 case 0:
462 return "Generic::ScalarRC";
463 case 1:
464 return "Generic::VectorRC";
465 }
466 }
467
469 return TypeSize::getFixed(32);
470 }
471
472 unsigned getMinVectorRegisterBitWidth() const { return 128; }
473
474 std::optional<unsigned> getMaxVScale() const { return std::nullopt; }
475 std::optional<unsigned> getVScaleForTuning() const { return std::nullopt; }
476 bool isVScaleKnownToBeAPowerOfTwo() const { return false; }
477
478 bool
480 return false;
481 }
482
483 ElementCount getMinimumVF(unsigned ElemWidth, bool IsScalable) const {
484 return ElementCount::get(0, IsScalable);
485 }
486
487 unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const { return 0; }
488 unsigned getStoreMinimumVF(unsigned VF, Type *, Type *) const { return VF; }
489
491 const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const {
492 AllowPromotionWithoutCommonHeader = false;
493 return false;
494 }
495
496 unsigned getCacheLineSize() const { return 0; }
497 std::optional<unsigned>
499 switch (Level) {
501 [[fallthrough]];
503 return std::nullopt;
504 }
505 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel");
506 }
507
508 std::optional<unsigned>
510 switch (Level) {
512 [[fallthrough]];
514 return std::nullopt;
515 }
516
517 llvm_unreachable("Unknown TargetTransformInfo::CacheLevel");
518 }
519
520 std::optional<unsigned> getMinPageSize() const { return {}; }
521
522 unsigned getPrefetchDistance() const { return 0; }
523 unsigned getMinPrefetchStride(unsigned NumMemAccesses,
524 unsigned NumStridedMemAccesses,
525 unsigned NumPrefetches, bool HasCall) const {
526 return 1;
527 }
528 unsigned getMaxPrefetchIterationsAhead() const { return UINT_MAX; }
529 bool enableWritePrefetching() const { return false; }
530 bool shouldPrefetchAddressSpace(unsigned AS) const { return !AS; }
531
532 unsigned getMaxInterleaveFactor(ElementCount VF) const { return 1; }
533
535 unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
538 const Instruction *CxtI = nullptr) const {
539 // Widenable conditions will eventually lower into constants, so some
540 // operations with them will be trivially optimized away.
541 auto IsWidenableCondition = [](const Value *V) {
542 if (auto *II = dyn_cast<IntrinsicInst>(V))
543 if (II->getIntrinsicID() == Intrinsic::experimental_widenable_condition)
544 return true;
545 return false;
546 };
547 // FIXME: A number of transformation tests seem to require these values
548 // which seems a little odd for how arbitary there are.
549 switch (Opcode) {
550 default:
551 break;
552 case Instruction::FDiv:
553 case Instruction::FRem:
554 case Instruction::SDiv:
555 case Instruction::SRem:
556 case Instruction::UDiv:
557 case Instruction::URem:
558 // FIXME: Unlikely to be true for CodeSize.
559 return TTI::TCC_Expensive;
560 case Instruction::And:
561 case Instruction::Or:
562 if (any_of(Args, IsWidenableCondition))
563 return TTI::TCC_Free;
564 break;
565 }
566
567 // Assume a 3cy latency for fp arithmetic ops.
569 if (Ty->getScalarType()->isFloatingPointTy())
570 return 3;
571
572 return 1;
573 }
574
576 unsigned Opcode1,
577 const SmallBitVector &OpcodeMask,
580 }
581
585 ArrayRef<const Value *> Args = std::nullopt) const {
586 return 1;
587 }
588
589 InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
592 const Instruction *I) const {
593 switch (Opcode) {
594 default:
595 break;
596 case Instruction::IntToPtr: {
597 unsigned SrcSize = Src->getScalarSizeInBits();
598 if (DL.isLegalInteger(SrcSize) &&
599 SrcSize <= DL.getPointerTypeSizeInBits(Dst))
600 return 0;
601 break;
602 }
603 case Instruction::PtrToInt: {
604 unsigned DstSize = Dst->getScalarSizeInBits();
605 if (DL.isLegalInteger(DstSize) &&
606 DstSize >= DL.getPointerTypeSizeInBits(Src))
607 return 0;
608 break;
609 }
610 case Instruction::BitCast:
611 if (Dst == Src || (Dst->isPointerTy() && Src->isPointerTy()))
612 // Identity and pointer-to-pointer casts are free.
613 return 0;
614 break;
615 case Instruction::Trunc: {
616 // trunc to a native type is free (assuming the target has compare and
617 // shift-right of the same width).
618 TypeSize DstSize = DL.getTypeSizeInBits(Dst);
619 if (!DstSize.isScalable() && DL.isLegalInteger(DstSize.getFixedValue()))
620 return 0;
621 break;
622 }
623 }
624 return 1;
625 }
626
628 VectorType *VecTy,
629 unsigned Index) const {
630 return 1;
631 }
632
634 const Instruction *I = nullptr) const {
635 // A phi would be free, unless we're costing the throughput because it
636 // will require a register.
637 if (Opcode == Instruction::PHI && CostKind != TTI::TCK_RecipThroughput)
638 return 0;
639 return 1;
640 }
641
642 InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
643 CmpInst::Predicate VecPred,
645 const Instruction *I) const {
646 return 1;
647 }
648
651 unsigned Index, Value *Op0,
652 Value *Op1) const {
653 return 1;
654 }
655
658 unsigned Index) const {
659 return 1;
660 }
661
662 unsigned getReplicationShuffleCost(Type *EltTy, int ReplicationFactor, int VF,
663 const APInt &DemandedDstElts,
665 return 1;
666 }
667
668 InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment,
669 unsigned AddressSpace,
672 const Instruction *I) const {
673 return 1;
674 }
675
676 InstructionCost getVPMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment,
677 unsigned AddressSpace,
679 const Instruction *I) const {
680 return 1;
681 }
682
684 Align Alignment, unsigned AddressSpace,
686 return 1;
687 }
688
690 const Value *Ptr, bool VariableMask,
691 Align Alignment,
693 const Instruction *I = nullptr) const {
694 return 1;
695 }
696
698 const Value *Ptr, bool VariableMask,
699 Align Alignment,
701 const Instruction *I = nullptr) const {
703 }
704
706 unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
707 Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
708 bool UseMaskForCond, bool UseMaskForGaps) const {
709 return 1;
710 }
711
714 switch (ICA.getID()) {
715 default:
716 break;
717 case Intrinsic::annotation:
718 case Intrinsic::assume:
719 case Intrinsic::sideeffect:
720 case Intrinsic::pseudoprobe:
721 case Intrinsic::arithmetic_fence:
722 case Intrinsic::dbg_assign:
723 case Intrinsic::dbg_declare:
724 case Intrinsic::dbg_value:
725 case Intrinsic::dbg_label:
726 case Intrinsic::invariant_start:
727 case Intrinsic::invariant_end:
728 case Intrinsic::launder_invariant_group:
729 case Intrinsic::strip_invariant_group:
730 case Intrinsic::is_constant:
731 case Intrinsic::lifetime_start:
732 case Intrinsic::lifetime_end:
733 case Intrinsic::experimental_noalias_scope_decl:
734 case Intrinsic::objectsize:
735 case Intrinsic::ptr_annotation:
736 case Intrinsic::var_annotation:
737 case Intrinsic::experimental_gc_result:
738 case Intrinsic::experimental_gc_relocate:
739 case Intrinsic::coro_alloc:
740 case Intrinsic::coro_begin:
741 case Intrinsic::coro_free:
742 case Intrinsic::coro_end:
743 case Intrinsic::coro_frame:
744 case Intrinsic::coro_size:
745 case Intrinsic::coro_align:
746 case Intrinsic::coro_suspend:
747 case Intrinsic::coro_subfn_addr:
748 case Intrinsic::threadlocal_address:
749 case Intrinsic::experimental_widenable_condition:
750 case Intrinsic::ssa_copy:
751 // These intrinsics don't actually represent code after lowering.
752 return 0;
753 }
754 return 1;
755 }
756
760 return 1;
761 }
762
763 // Assume that we have a register of the right size for the type.
764 unsigned getNumberOfParts(Type *Tp) const { return 1; }
765
767 const SCEV *) const {
768 return 0;
769 }
770
772 std::optional<FastMathFlags> FMF,
773 TTI::TargetCostKind) const {
774 return 1;
775 }
776
779 TTI::TargetCostKind) const {
780 return 1;
781 }
782
783 InstructionCost getExtendedReductionCost(unsigned Opcode, bool IsUnsigned,
784 Type *ResTy, VectorType *Ty,
785 FastMathFlags FMF,
787 return 1;
788 }
789
791 VectorType *Ty,
793 return 1;
794 }
795
797 return 0;
798 }
799
801 return false;
802 }
803
805 // Note for overrides: You must ensure for all element unordered-atomic
806 // memory intrinsics that all power-of-2 element sizes up to, and
807 // including, the return value of this method have a corresponding
808 // runtime lib call. These runtime lib call definitions can be found
809 // in RuntimeLibcalls.h
810 return 0;
811 }
812
814 Type *ExpectedType) const {
815 return nullptr;
816 }
817
818 Type *
820 unsigned SrcAddrSpace, unsigned DestAddrSpace,
821 unsigned SrcAlign, unsigned DestAlign,
822 std::optional<uint32_t> AtomicElementSize) const {
823 return AtomicElementSize ? Type::getIntNTy(Context, *AtomicElementSize * 8)
825 }
826
828 SmallVectorImpl<Type *> &OpsOut, LLVMContext &Context,
829 unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace,
830 unsigned SrcAlign, unsigned DestAlign,
831 std::optional<uint32_t> AtomicCpySize) const {
832 unsigned OpSizeInBytes = AtomicCpySize ? *AtomicCpySize : 1;
833 Type *OpType = Type::getIntNTy(Context, OpSizeInBytes * 8);
834 for (unsigned i = 0; i != RemainingBytes; i += OpSizeInBytes)
835 OpsOut.push_back(OpType);
836 }
837
838 bool areInlineCompatible(const Function *Caller,
839 const Function *Callee) const {
840 return (Caller->getFnAttribute("target-cpu") ==
841 Callee->getFnAttribute("target-cpu")) &&
842 (Caller->getFnAttribute("target-features") ==
843 Callee->getFnAttribute("target-features"));
844 }
845
846 unsigned getInlineCallPenalty(const Function *F, const CallBase &Call,
847 unsigned DefaultCallPenalty) const {
848 return DefaultCallPenalty;
849 }
850
851 bool areTypesABICompatible(const Function *Caller, const Function *Callee,
852 const ArrayRef<Type *> &Types) const {
853 return (Caller->getFnAttribute("target-cpu") ==
854 Callee->getFnAttribute("target-cpu")) &&
855 (Caller->getFnAttribute("target-features") ==
856 Callee->getFnAttribute("target-features"));
857 }
858
860 const DataLayout &DL) const {
861 return false;
862 }
863
865 const DataLayout &DL) const {
866 return false;
867 }
868
869 unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const { return 128; }
870
871 bool isLegalToVectorizeLoad(LoadInst *LI) const { return true; }
872
873 bool isLegalToVectorizeStore(StoreInst *SI) const { return true; }
874
875 bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment,
876 unsigned AddrSpace) const {
877 return true;
878 }
879
880 bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment,
881 unsigned AddrSpace) const {
882 return true;
883 }
884
886 ElementCount VF) const {
887 return true;
888 }
889
890 bool isElementTypeLegalForScalableVector(Type *Ty) const { return true; }
891
892 unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize,
893 unsigned ChainSizeInBytes,
894 VectorType *VecTy) const {
895 return VF;
896 }
897
898 unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize,
899 unsigned ChainSizeInBytes,
900 VectorType *VecTy) const {
901 return VF;
902 }
903
904 bool preferInLoopReduction(unsigned Opcode, Type *Ty,
905 TTI::ReductionFlags Flags) const {
906 return false;
907 }
908
909 bool preferPredicatedReductionSelect(unsigned Opcode, Type *Ty,
910 TTI::ReductionFlags Flags) const {
911 return false;
912 }
913
915 return true;
916 }
917
918 bool shouldExpandReduction(const IntrinsicInst *II) const { return true; }
919
920 unsigned getGISelRematGlobalCost() const { return 1; }
921
922 unsigned getMinTripCountTailFoldingThreshold() const { return 0; }
923
924 bool supportsScalableVectors() const { return false; }
925
926 bool enableScalableVectorization() const { return false; }
927
928 bool hasActiveVectorLength(unsigned Opcode, Type *DataType,
929 Align Alignment) const {
930 return false;
931 }
932
937 /* OperatorStrategy */ TargetTransformInfo::VPLegalization::Convert);
938 }
939
940 bool hasArmWideBranch(bool) const { return false; }
941
942 unsigned getMaxNumArgs() const { return UINT_MAX; }
943
944protected:
945 // Obtain the minimum required size to hold the value (without the sign)
946 // In case of a vector it returns the min required size for one element.
947 unsigned minRequiredElementSize(const Value *Val, bool &isSigned) const {
948 if (isa<ConstantDataVector>(Val) || isa<ConstantVector>(Val)) {
949 const auto *VectorValue = cast<Constant>(Val);
950
951 // In case of a vector need to pick the max between the min
952 // required size for each element
953 auto *VT = cast<FixedVectorType>(Val->getType());
954
955 // Assume unsigned elements
956 isSigned = false;
957
958 // The max required size is the size of the vector element type
959 unsigned MaxRequiredSize =
960 VT->getElementType()->getPrimitiveSizeInBits().getFixedValue();
961
962 unsigned MinRequiredSize = 0;
963 for (unsigned i = 0, e = VT->getNumElements(); i < e; ++i) {
964 if (auto *IntElement =
965 dyn_cast<ConstantInt>(VectorValue->getAggregateElement(i))) {
966 bool signedElement = IntElement->getValue().isNegative();
967 // Get the element min required size.
968 unsigned ElementMinRequiredSize =
969 IntElement->getValue().getSignificantBits() - 1;
970 // In case one element is signed then all the vector is signed.
971 isSigned |= signedElement;
972 // Save the max required bit size between all the elements.
973 MinRequiredSize = std::max(MinRequiredSize, ElementMinRequiredSize);
974 } else {
975 // not an int constant element
976 return MaxRequiredSize;
977 }
978 }
979 return MinRequiredSize;
980 }
981
982 if (const auto *CI = dyn_cast<ConstantInt>(Val)) {
983 isSigned = CI->getValue().isNegative();
984 return CI->getValue().getSignificantBits() - 1;
985 }
986
987 if (const auto *Cast = dyn_cast<SExtInst>(Val)) {
988 isSigned = true;
989 return Cast->getSrcTy()->getScalarSizeInBits() - 1;
990 }
991
992 if (const auto *Cast = dyn_cast<ZExtInst>(Val)) {
993 isSigned = false;
994 return Cast->getSrcTy()->getScalarSizeInBits();
995 }
996
997 isSigned = false;
998 return Val->getType()->getScalarSizeInBits();
999 }
1000
1001 bool isStridedAccess(const SCEV *Ptr) const {
1002 return Ptr && isa<SCEVAddRecExpr>(Ptr);
1003 }
1004
1006 const SCEV *Ptr) const {
1007 if (!isStridedAccess(Ptr))
1008 return nullptr;
1009 const SCEVAddRecExpr *AddRec = cast<SCEVAddRecExpr>(Ptr);
1010 return dyn_cast<SCEVConstant>(AddRec->getStepRecurrence(*SE));
1011 }
1012
1014 int64_t MergeDistance) const {
1015 const SCEVConstant *Step = getConstantStrideStep(SE, Ptr);
1016 if (!Step)
1017 return false;
1018 APInt StrideVal = Step->getAPInt();
1019 if (StrideVal.getBitWidth() > 64)
1020 return false;
1021 // FIXME: Need to take absolute value for negative stride case.
1022 return StrideVal.getSExtValue() < MergeDistance;
1023 }
1024};
1025
1026/// CRTP base class for use as a mix-in that aids implementing
1027/// a TargetTransformInfo-compatible class.
1028template <typename T>
1030private:
1032
1033protected:
1035
1036public:
1038
1042 assert(PointeeType && Ptr && "can't get GEPCost of nullptr");
1043 auto *BaseGV = dyn_cast<GlobalValue>(Ptr->stripPointerCasts());
1044 bool HasBaseReg = (BaseGV == nullptr);
1045
1046 auto PtrSizeBits = DL.getPointerTypeSizeInBits(Ptr->getType());
1047 APInt BaseOffset(PtrSizeBits, 0);
1048 int64_t Scale = 0;
1049
1050 auto GTI = gep_type_begin(PointeeType, Operands);
1051 Type *TargetType = nullptr;
1052
1053 // Handle the case where the GEP instruction has a single operand,
1054 // the basis, therefore TargetType is a nullptr.
1055 if (Operands.empty())
1056 return !BaseGV ? TTI::TCC_Free : TTI::TCC_Basic;
1057
1058 for (auto I = Operands.begin(); I != Operands.end(); ++I, ++GTI) {
1059 TargetType = GTI.getIndexedType();
1060 // We assume that the cost of Scalar GEP with constant index and the
1061 // cost of Vector GEP with splat constant index are the same.
1062 const ConstantInt *ConstIdx = dyn_cast<ConstantInt>(*I);
1063 if (!ConstIdx)
1064 if (auto Splat = getSplatValue(*I))
1065 ConstIdx = dyn_cast<ConstantInt>(Splat);
1066 if (StructType *STy = GTI.getStructTypeOrNull()) {
1067 // For structures the index is always splat or scalar constant
1068 assert(ConstIdx && "Unexpected GEP index");
1069 uint64_t Field = ConstIdx->getZExtValue();
1070 BaseOffset += DL.getStructLayout(STy)->getElementOffset(Field);
1071 } else {
1072 // If this operand is a scalable type, bail out early.
1073 // TODO: Make isLegalAddressingMode TypeSize aware.
1074 if (TargetType->isScalableTy())
1075 return TTI::TCC_Basic;
1076 int64_t ElementSize =
1077 GTI.getSequentialElementStride(DL).getFixedValue();
1078 if (ConstIdx) {
1079 BaseOffset +=
1080 ConstIdx->getValue().sextOrTrunc(PtrSizeBits) * ElementSize;
1081 } else {
1082 // Needs scale register.
1083 if (Scale != 0)
1084 // No addressing mode takes two scale registers.
1085 return TTI::TCC_Basic;
1086 Scale = ElementSize;
1087 }
1088 }
1089 }
1090
1091 // If we haven't been provided a hint, use the target type for now.
1092 //
1093 // TODO: Take a look at potentially removing this: This is *slightly* wrong
1094 // as it's possible to have a GEP with a foldable target type but a memory
1095 // access that isn't foldable. For example, this load isn't foldable on
1096 // RISC-V:
1097 //
1098 // %p = getelementptr i32, ptr %base, i32 42
1099 // %x = load <2 x i32>, ptr %p
1100 if (!AccessType)
1101 AccessType = TargetType;
1102
1103 // If the final address of the GEP is a legal addressing mode for the given
1104 // access type, then we can fold it into its users.
1105 if (static_cast<T *>(this)->isLegalAddressingMode(
1106 AccessType, const_cast<GlobalValue *>(BaseGV),
1107 BaseOffset.sextOrTrunc(64).getSExtValue(), HasBaseReg, Scale,
1108 Ptr->getType()->getPointerAddressSpace()))
1109 return TTI::TCC_Free;
1110
1111 // TODO: Instead of returning TCC_Basic here, we should use
1112 // getArithmeticInstrCost. Or better yet, provide a hook to let the target
1113 // model it.
1114 return TTI::TCC_Basic;
1115 }
1116
1118 const Value *Base,
1120 Type *AccessTy,
1123 // In the basic model we take into account GEP instructions only
1124 // (although here can come alloca instruction, a value, constants and/or
1125 // constant expressions, PHIs, bitcasts ... whatever allowed to be used as a
1126 // pointer). Typically, if Base is a not a GEP-instruction and all the
1127 // pointers are relative to the same base address, all the rest are
1128 // either GEP instructions, PHIs, bitcasts or constants. When we have same
1129 // base, we just calculate cost of each non-Base GEP as an ADD operation if
1130 // any their index is a non-const.
1131 // If no known dependecies between the pointers cost is calculated as a sum
1132 // of costs of GEP instructions.
1133 for (const Value *V : Ptrs) {
1134 const auto *GEP = dyn_cast<GetElementPtrInst>(V);
1135 if (!GEP)
1136 continue;
1137 if (Info.isSameBase() && V != Base) {
1138 if (GEP->hasAllConstantIndices())
1139 continue;
1140 Cost += static_cast<T *>(this)->getArithmeticInstrCost(
1141 Instruction::Add, GEP->getType(), CostKind,
1143 std::nullopt);
1144 } else {
1145 SmallVector<const Value *> Indices(GEP->indices());
1146 Cost += static_cast<T *>(this)->getGEPCost(GEP->getSourceElementType(),
1147 GEP->getPointerOperand(),
1148 Indices, AccessTy, CostKind);
1149 }
1150 }
1151 return Cost;
1152 }
1153
1157 using namespace llvm::PatternMatch;
1158
1159 auto *TargetTTI = static_cast<T *>(this);
1160 // Handle non-intrinsic calls, invokes, and callbr.
1161 // FIXME: Unlikely to be true for anything but CodeSize.
1162 auto *CB = dyn_cast<CallBase>(U);
1163 if (CB && !isa<IntrinsicInst>(U)) {
1164 if (const Function *F = CB->getCalledFunction()) {
1165 if (!TargetTTI->isLoweredToCall(F))
1166 return TTI::TCC_Basic; // Give a basic cost if it will be lowered
1167
1168 return TTI::TCC_Basic * (F->getFunctionType()->getNumParams() + 1);
1169 }
1170 // For indirect or other calls, scale cost by number of arguments.
1171 return TTI::TCC_Basic * (CB->arg_size() + 1);
1172 }
1173
1174 Type *Ty = U->getType();
1175 unsigned Opcode = Operator::getOpcode(U);
1176 auto *I = dyn_cast<Instruction>(U);
1177 switch (Opcode) {
1178 default:
1179 break;
1180 case Instruction::Call: {
1181 assert(isa<IntrinsicInst>(U) && "Unexpected non-intrinsic call");
1182 auto *Intrinsic = cast<IntrinsicInst>(U);
1183 IntrinsicCostAttributes CostAttrs(Intrinsic->getIntrinsicID(), *CB);
1184 return TargetTTI->getIntrinsicInstrCost(CostAttrs, CostKind);
1185 }
1186 case Instruction::Br:
1187 case Instruction::Ret:
1188 case Instruction::PHI:
1189 case Instruction::Switch:
1190 return TargetTTI->getCFInstrCost(Opcode, CostKind, I);
1191 case Instruction::ExtractValue:
1192 case Instruction::Freeze:
1193 return TTI::TCC_Free;
1194 case Instruction::Alloca:
1195 if (cast<AllocaInst>(U)->isStaticAlloca())
1196 return TTI::TCC_Free;
1197 break;
1198 case Instruction::GetElementPtr: {
1199 const auto *GEP = cast<GEPOperator>(U);
1200 Type *AccessType = nullptr;
1201 // For now, only provide the AccessType in the simple case where the GEP
1202 // only has one user.
1203 if (GEP->hasOneUser() && I)
1204 AccessType = I->user_back()->getAccessType();
1205
1206 return TargetTTI->getGEPCost(GEP->getSourceElementType(),
1207 Operands.front(), Operands.drop_front(),
1208 AccessType, CostKind);
1209 }
1210 case Instruction::Add:
1211 case Instruction::FAdd:
1212 case Instruction::Sub:
1213 case Instruction::FSub:
1214 case Instruction::Mul:
1215 case Instruction::FMul:
1216 case Instruction::UDiv:
1217 case Instruction::SDiv:
1218 case Instruction::FDiv:
1219 case Instruction::URem:
1220 case Instruction::SRem:
1221 case Instruction::FRem:
1222 case Instruction::Shl:
1223 case Instruction::LShr:
1224 case Instruction::AShr:
1225 case Instruction::And:
1226 case Instruction::Or:
1227 case Instruction::Xor:
1228 case Instruction::FNeg: {
1230 TTI::OperandValueInfo Op2Info;
1231 if (Opcode != Instruction::FNeg)
1232 Op2Info = TTI::getOperandInfo(Operands[1]);
1233 return TargetTTI->getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info,
1234 Op2Info, Operands, I);
1235 }
1236 case Instruction::IntToPtr:
1237 case Instruction::PtrToInt:
1238 case Instruction::SIToFP:
1239 case Instruction::UIToFP:
1240 case Instruction::FPToUI:
1241 case Instruction::FPToSI:
1242 case Instruction::Trunc:
1243 case Instruction::FPTrunc:
1244 case Instruction::BitCast:
1245 case Instruction::FPExt:
1246 case Instruction::SExt:
1247 case Instruction::ZExt:
1248 case Instruction::AddrSpaceCast: {
1249 Type *OpTy = Operands[0]->getType();
1250 return TargetTTI->getCastInstrCost(
1251 Opcode, Ty, OpTy, TTI::getCastContextHint(I), CostKind, I);
1252 }
1253 case Instruction::Store: {
1254 auto *SI = cast<StoreInst>(U);
1255 Type *ValTy = Operands[0]->getType();
1257 return TargetTTI->getMemoryOpCost(Opcode, ValTy, SI->getAlign(),
1258 SI->getPointerAddressSpace(), CostKind,
1259 OpInfo, I);
1260 }
1261 case Instruction::Load: {
1262 // FIXME: Arbitary cost which could come from the backend.
1264 return 4;
1265 auto *LI = cast<LoadInst>(U);
1266 Type *LoadType = U->getType();
1267 // If there is a non-register sized type, the cost estimation may expand
1268 // it to be several instructions to load into multiple registers on the
1269 // target. But, if the only use of the load is a trunc instruction to a
1270 // register sized type, the instruction selector can combine these
1271 // instructions to be a single load. So, in this case, we use the
1272 // destination type of the trunc instruction rather than the load to
1273 // accurately estimate the cost of this load instruction.
1274 if (CostKind == TTI::TCK_CodeSize && LI->hasOneUse() &&
1275 !LoadType->isVectorTy()) {
1276 if (const TruncInst *TI = dyn_cast<TruncInst>(*LI->user_begin()))
1277 LoadType = TI->getDestTy();
1278 }
1279 return TargetTTI->getMemoryOpCost(Opcode, LoadType, LI->getAlign(),
1281 {TTI::OK_AnyValue, TTI::OP_None}, I);
1282 }
1283 case Instruction::Select: {
1284 const Value *Op0, *Op1;
1285 if (match(U, m_LogicalAnd(m_Value(Op0), m_Value(Op1))) ||
1286 match(U, m_LogicalOr(m_Value(Op0), m_Value(Op1)))) {
1287 // select x, y, false --> x & y
1288 // select x, true, y --> x | y
1289 const auto Op1Info = TTI::getOperandInfo(Op0);
1290 const auto Op2Info = TTI::getOperandInfo(Op1);
1291 assert(Op0->getType()->getScalarSizeInBits() == 1 &&
1292 Op1->getType()->getScalarSizeInBits() == 1);
1293
1295 return TargetTTI->getArithmeticInstrCost(
1296 match(U, m_LogicalOr()) ? Instruction::Or : Instruction::And, Ty,
1297 CostKind, Op1Info, Op2Info, Operands, I);
1298 }
1299 Type *CondTy = Operands[0]->getType();
1300 return TargetTTI->getCmpSelInstrCost(Opcode, U->getType(), CondTy,
1302 CostKind, I);
1303 }
1304 case Instruction::ICmp:
1305 case Instruction::FCmp: {
1306 Type *ValTy = Operands[0]->getType();
1307 // TODO: Also handle ICmp/FCmp constant expressions.
1308 return TargetTTI->getCmpSelInstrCost(Opcode, ValTy, U->getType(),
1309 I ? cast<CmpInst>(I)->getPredicate()
1311 CostKind, I);
1312 }
1313 case Instruction::InsertElement: {
1314 auto *IE = dyn_cast<InsertElementInst>(U);
1315 if (!IE)
1316 return TTI::TCC_Basic; // FIXME
1317 unsigned Idx = -1;
1318 if (auto *CI = dyn_cast<ConstantInt>(Operands[2]))
1319 if (CI->getValue().getActiveBits() <= 32)
1320 Idx = CI->getZExtValue();
1321 return TargetTTI->getVectorInstrCost(*IE, Ty, CostKind, Idx);
1322 }
1323 case Instruction::ShuffleVector: {
1324 auto *Shuffle = dyn_cast<ShuffleVectorInst>(U);
1325 if (!Shuffle)
1326 return TTI::TCC_Basic; // FIXME
1327
1328 auto *VecTy = cast<VectorType>(U->getType());
1329 auto *VecSrcTy = cast<VectorType>(Operands[0]->getType());
1330 ArrayRef<int> Mask = Shuffle->getShuffleMask();
1331 int NumSubElts, SubIndex;
1332
1333 // TODO: move more of this inside improveShuffleKindFromMask.
1334 if (Shuffle->changesLength()) {
1335 // Treat a 'subvector widening' as a free shuffle.
1336 if (Shuffle->increasesLength() && Shuffle->isIdentityWithPadding())
1337 return 0;
1338
1339 if (Shuffle->isExtractSubvectorMask(SubIndex))
1340 return TargetTTI->getShuffleCost(TTI::SK_ExtractSubvector, VecSrcTy,
1341 Mask, CostKind, SubIndex, VecTy,
1342 Operands);
1343
1344 if (Shuffle->isInsertSubvectorMask(NumSubElts, SubIndex))
1345 return TargetTTI->getShuffleCost(
1346 TTI::SK_InsertSubvector, VecTy, Mask, CostKind, SubIndex,
1347 FixedVectorType::get(VecTy->getScalarType(), NumSubElts),
1348 Operands);
1349
1350 int ReplicationFactor, VF;
1351 if (Shuffle->isReplicationMask(ReplicationFactor, VF)) {
1352 APInt DemandedDstElts = APInt::getZero(Mask.size());
1353 for (auto I : enumerate(Mask)) {
1354 if (I.value() != PoisonMaskElem)
1355 DemandedDstElts.setBit(I.index());
1356 }
1357 return TargetTTI->getReplicationShuffleCost(
1358 VecSrcTy->getElementType(), ReplicationFactor, VF,
1359 DemandedDstElts, CostKind);
1360 }
1361
1362 bool IsUnary = isa<UndefValue>(Operands[1]);
1363 NumSubElts = VecSrcTy->getElementCount().getKnownMinValue();
1364 SmallVector<int, 16> AdjustMask(Mask.begin(), Mask.end());
1365
1366 // Widening shuffle - widening the source(s) to the new length
1367 // (treated as free - see above), and then perform the adjusted
1368 // shuffle at that width.
1369 if (Shuffle->increasesLength()) {
1370 for (int &M : AdjustMask)
1371 M = M >= NumSubElts ? (M + (Mask.size() - NumSubElts)) : M;
1372
1373 return TargetTTI->getShuffleCost(
1375 AdjustMask, CostKind, 0, nullptr);
1376 }
1377
1378 // Narrowing shuffle - perform shuffle at original wider width and
1379 // then extract the lower elements.
1380 AdjustMask.append(NumSubElts - Mask.size(), PoisonMaskElem);
1381
1382 InstructionCost ShuffleCost = TargetTTI->getShuffleCost(
1384 VecSrcTy, AdjustMask, CostKind, 0, nullptr);
1385
1386 SmallVector<int, 16> ExtractMask(Mask.size());
1387 std::iota(ExtractMask.begin(), ExtractMask.end(), 0);
1388 return ShuffleCost + TargetTTI->getShuffleCost(TTI::SK_ExtractSubvector,
1389 VecSrcTy, ExtractMask,
1390 CostKind, 0, VecTy);
1391 }
1392
1393 if (Shuffle->isIdentity())
1394 return 0;
1395
1396 if (Shuffle->isReverse())
1397 return TargetTTI->getShuffleCost(TTI::SK_Reverse, VecTy, Mask, CostKind,
1398 0, nullptr, Operands);
1399
1400 if (Shuffle->isSelect())
1401 return TargetTTI->getShuffleCost(TTI::SK_Select, VecTy, Mask, CostKind,
1402 0, nullptr, Operands);
1403
1404 if (Shuffle->isTranspose())
1405 return TargetTTI->getShuffleCost(TTI::SK_Transpose, VecTy, Mask,
1406 CostKind, 0, nullptr, Operands);
1407
1408 if (Shuffle->isZeroEltSplat())
1409 return TargetTTI->getShuffleCost(TTI::SK_Broadcast, VecTy, Mask,
1410 CostKind, 0, nullptr, Operands);
1411
1412 if (Shuffle->isSingleSource())
1413 return TargetTTI->getShuffleCost(TTI::SK_PermuteSingleSrc, VecTy, Mask,
1414 CostKind, 0, nullptr, Operands);
1415
1416 if (Shuffle->isInsertSubvectorMask(NumSubElts, SubIndex))
1417 return TargetTTI->getShuffleCost(
1418 TTI::SK_InsertSubvector, VecTy, Mask, CostKind, SubIndex,
1419 FixedVectorType::get(VecTy->getScalarType(), NumSubElts), Operands);
1420
1421 if (Shuffle->isSplice(SubIndex))
1422 return TargetTTI->getShuffleCost(TTI::SK_Splice, VecTy, Mask, CostKind,
1423 SubIndex, nullptr, Operands);
1424
1425 return TargetTTI->getShuffleCost(TTI::SK_PermuteTwoSrc, VecTy, Mask,
1426 CostKind, 0, nullptr, Operands);
1427 }
1428 case Instruction::ExtractElement: {
1429 auto *EEI = dyn_cast<ExtractElementInst>(U);
1430 if (!EEI)
1431 return TTI::TCC_Basic; // FIXME
1432 unsigned Idx = -1;
1433 if (auto *CI = dyn_cast<ConstantInt>(Operands[1]))
1434 if (CI->getValue().getActiveBits() <= 32)
1435 Idx = CI->getZExtValue();
1436 Type *DstTy = Operands[0]->getType();
1437 return TargetTTI->getVectorInstrCost(*EEI, DstTy, CostKind, Idx);
1438 }
1439 }
1440
1441 // By default, just classify everything as 'basic' or -1 to represent that
1442 // don't know the throughput cost.
1444 }
1445
1447 auto *TargetTTI = static_cast<T *>(this);
1448 SmallVector<const Value *, 4> Ops(I->operand_values());
1449 InstructionCost Cost = TargetTTI->getInstructionCost(
1452 }
1453
1454 bool supportsTailCallFor(const CallBase *CB) const {
1455 return static_cast<const T *>(this)->supportsTailCalls();
1456 }
1457};
1458} // namespace llvm
1459
1460#endif
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
static cl::opt< TargetTransformInfo::TargetCostKind > CostKind("cost-kind", cl::desc("Target cost kind"), cl::init(TargetTransformInfo::TCK_RecipThroughput), cl::values(clEnumValN(TargetTransformInfo::TCK_RecipThroughput, "throughput", "Reciprocal throughput"), clEnumValN(TargetTransformInfo::TCK_Latency, "latency", "Instruction latency"), clEnumValN(TargetTransformInfo::TCK_CodeSize, "code-size", "Code size"), clEnumValN(TargetTransformInfo::TCK_SizeAndLatency, "size-latency", "Code size and latency")))
return RetTy
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
std::string Name
static bool isSigned(unsigned int Opcode)
Hexagon Common GEP
#define F(x, y, z)
Definition: MD5.cpp:55
#define I(x, y, z)
Definition: MD5.cpp:58
mir Rename Register Operands
LLVMContext & Context
static cl::opt< RegAllocEvictionAdvisorAnalysis::AdvisorMode > Mode("regalloc-enable-advisor", cl::Hidden, cl::init(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default), cl::desc("Enable regalloc advisor mode"), cl::values(clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default, "default", "Default"), clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Release, "release", "precompiled"), clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Development, "development", "for training")))
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static SymbolRef::Type getType(const Symbol *Sym)
Definition: TapiFile.cpp:40
This pass exposes codegen information to IR-level passes.
Class for arbitrary precision integers.
Definition: APInt.h:76
void setBit(unsigned BitPosition)
Set the given bit to 1 whose position is given as "bitPosition".
Definition: APInt.h:1308
unsigned getBitWidth() const
Return the number of bits in the APInt.
Definition: APInt.h:1439
APInt sextOrTrunc(unsigned width) const
Sign extend or truncate to width.
Definition: APInt.cpp:1010
static APInt getZero(unsigned numBits)
Get the '0' value for the specified bit-width.
Definition: APInt.h:178
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1513
an instruction to allocate memory on the stack
Definition: Instructions.h:59
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Definition: ArrayRef.h:41
A cache of @llvm.assume calls within a function.
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Conditional or Unconditional Branch instruction.
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
Definition: InstrTypes.h:1461
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
Definition: InstrTypes.h:960
This is the shared class of boolean and integer constants.
Definition: Constants.h:80
uint64_t getZExtValue() const
Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...
Definition: Constants.h:154
const APInt & getValue() const
Return the constant as an APInt value reference.
Definition: Constants.h:145
This is an important base class in LLVM.
Definition: Constant.h:41
A parsed version of the target data layout string in and methods for querying it.
Definition: DataLayout.h:110
bool isLegalInteger(uint64_t Width) const
Returns true if the specified type is known to be a native integer type supported by the CPU.
Definition: DataLayout.h:260
const StructLayout * getStructLayout(StructType *Ty) const
Returns a StructLayout object, indicating the alignment of the struct, its size, and the offsets of i...
Definition: DataLayout.cpp:720
unsigned getPointerTypeSizeInBits(Type *) const
Layout pointer size, in bits, based on the type.
Definition: DataLayout.cpp:763
TypeSize getTypeSizeInBits(Type *Ty) const
Size examples:
Definition: DataLayout.h:672
TypeSize getTypeStoreSize(Type *Ty) const
Returns the maximum number of bytes that may be overwritten by storing the specified type.
Definition: DataLayout.h:472
Concrete subclass of DominatorTreeBase that is used to compute a normal dominator tree.
Definition: Dominators.h:162
static constexpr ElementCount get(ScalarTy MinVal, bool Scalable)
Definition: TypeSize.h:302
Convenience struct for specifying and reasoning about fast-math flags.
Definition: FMF.h:20
static FixedVectorType * get(Type *ElementType, unsigned NumElts)
Definition: Type.cpp:692
The core instruction combiner logic.
Definition: InstCombiner.h:47
static InstructionCost getInvalid(CostType Val=0)
A wrapper class for inspecting calls to intrinsic functions.
Definition: IntrinsicInst.h:47
Intrinsic::ID getIntrinsicID() const
Return the intrinsic ID of this intrinsic.
Definition: IntrinsicInst.h:54
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
An instruction for reading from memory.
Definition: Instructions.h:184
Represents a single loop in the control flow graph.
Definition: LoopInfo.h:44
unsigned getOpcode() const
Return the opcode for this Instruction or ConstantExpr.
Definition: Operator.h:41
The optimization diagnostic interface.
Analysis providing profile information.
The RecurrenceDescriptor is used to identify recurrences variables in a loop.
Definition: IVDescriptors.h:71
This node represents a polynomial recurrence on the trip count of the specified loop.
const SCEV * getStepRecurrence(ScalarEvolution &SE) const
Constructs and returns the recurrence indicating how much this expression steps by.
This class represents a constant integer value.
const APInt & getAPInt() const
This class represents an analyzed expression in the program.
The main scalar evolution driver.
This is a 'bitvector' (really, a variable-sized bit array), optimized for the case when the array is ...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: SmallVector.h:586
void append(ItTy in_start, ItTy in_end)
Add the specified range to the end of the SmallVector.
Definition: SmallVector.h:696
void push_back(const T &Elt)
Definition: SmallVector.h:426
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
An instruction for storing to memory.
Definition: Instructions.h:317
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
TypeSize getElementOffset(unsigned Idx) const
Definition: DataLayout.h:651
Class to represent struct types.
Definition: DerivedTypes.h:216
Multiway switch.
Provides information about what library functions are available for the current target.
Base class for use as a mix-in that aids implementing a TargetTransformInfo-compatible class.
const DataLayout & getDataLayout() const
void getMemcpyLoopResidualLoweringType(SmallVectorImpl< Type * > &OpsOut, LLVMContext &Context, unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign, std::optional< uint32_t > AtomicCpySize) const
bool isLegalToVectorizeStore(StoreInst *SI) const
bool addrspacesMayAlias(unsigned AS0, unsigned AS1) const
bool shouldTreatInstructionLikeSelect(const Instruction *I)
bool isLegalToVectorizeLoad(LoadInst *LI) const
bool isLegalBroadcastLoad(Type *ElementTy, ElementCount NumElements) const
std::optional< unsigned > getVScaleForTuning() const
bool shouldMaximizeVectorBandwidth(TargetTransformInfo::RegisterKind K) const
bool canSaveCmp(Loop *L, BranchInst **BI, ScalarEvolution *SE, LoopInfo *LI, DominatorTree *DT, AssumptionCache *AC, TargetLibraryInfo *LibInfo) const
bool isLegalStridedLoadStore(Type *DataType, Align Alignment) const
std::optional< Value * > simplifyDemandedVectorEltsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, std::function< void(Instruction *, unsigned, APInt, APInt &)> SimplifyAndSetOp) const
bool isLegalICmpImmediate(int64_t Imm) const
unsigned getRegUsageForType(Type *Ty) const
unsigned getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef< unsigned > Indices, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, bool UseMaskForCond, bool UseMaskForGaps) const
bool areTypesABICompatible(const Function *Caller, const Function *Callee, const ArrayRef< Type * > &Types) const
void getPeelingPreferences(Loop *, ScalarEvolution &, TTI::PeelingPreferences &) const
bool isAlwaysUniform(const Value *V) const
bool isProfitableToHoist(Instruction *I) const
unsigned getEstimatedNumberOfCaseClusters(const SwitchInst &SI, unsigned &JTSize, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) const
InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind, Instruction *Inst=nullptr) const
bool isLSRCostLess(const TTI::LSRCost &C1, const TTI::LSRCost &C2) const
bool isExpensiveToSpeculativelyExecute(const Instruction *I)
bool isTruncateFree(Type *Ty1, Type *Ty2) const
bool isStridedAccess(const SCEV *Ptr) const
InstructionCost getCallInstrCost(Function *F, Type *RetTy, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind) const
InstructionCost getArithmeticReductionCost(unsigned, VectorType *, std::optional< FastMathFlags > FMF, TTI::TargetCostKind) const
InstructionCost getFPOpCost(Type *Ty) const
bool shouldConsiderAddressTypePromotion(const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const
bool areInlineCompatible(const Function *Caller, const Function *Callee) const
std::pair< const Value *, unsigned > getPredicatedAddrSpace(const Value *V) const
InstructionCost getMemcpyCost(const Instruction *I) const
unsigned getInliningCostBenefitAnalysisProfitableMultiplier() const
unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
std::optional< unsigned > getMaxVScale() const
TTI::PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const
unsigned getCallerAllocaCost(const CallBase *CB, const AllocaInst *AI) const
bool isProfitableLSRChainElement(Instruction *I) const
InstructionCost getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty) const
bool preferToKeepConstantsAttached(const Instruction &Inst, const Function &Fn) const
Value * getOrCreateResultFromMemIntrinsic(IntrinsicInst *Inst, Type *ExpectedType) const
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, TTI::TargetCostKind CostKind) const
bool isLegalMaskedStore(Type *DataType, Align Alignment) const
InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I=nullptr) const
unsigned getInlineCallPenalty(const Function *F, const CallBase &Call, unsigned DefaultCallPenalty) const
InstructionCost getVPMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, const Instruction *I) const
InstructionCost getStridedMemoryOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I=nullptr) const
bool isNoopAddrSpaceCast(unsigned, unsigned) const
unsigned getStoreMinimumVF(unsigned VF, Type *, Type *) const
InstructionCost getVectorInstrCost(const Instruction &I, Type *Val, TTI::TargetCostKind CostKind, unsigned Index) const
bool preferPredicatedReductionSelect(unsigned Opcode, Type *Ty, TTI::ReductionFlags Flags) const
TargetTransformInfoImplBase(TargetTransformInfoImplBase &&Arg)
TargetTransformInfo::VPLegalization getVPLegalizationStrategy(const VPIntrinsic &PI) const
void getUnrollingPreferences(Loop *, ScalarEvolution &, TTI::UnrollingPreferences &, OptimizationRemarkEmitter *) const
bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace, Instruction *I=nullptr, int64_t ScalableOffset=0) const
bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const
unsigned minRequiredElementSize(const Value *Val, bool &isSigned) const
Type * getMemcpyLoopLoweringType(LLVMContext &Context, Value *Length, unsigned SrcAddrSpace, unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign, std::optional< uint32_t > AtomicElementSize) const
std::optional< unsigned > getCacheSize(TargetTransformInfo::CacheLevel Level) const
unsigned getAssumedAddrSpace(const Value *V) const
bool isLegalMaskedExpandLoad(Type *DataType, Align Alignment) const
bool isLegalNTStore(Type *DataType, Align Alignment) const
unsigned getRegisterClassForType(bool Vector, Type *Ty=nullptr) const
bool isLegalMaskedGather(Type *DataType, Align Alignment) const
unsigned adjustInliningThreshold(const CallBase *CB) const
BranchProbability getPredictableBranchThreshold() const
std::optional< unsigned > getMinPageSize() const
bool collectFlatAddressOperands(SmallVectorImpl< int > &OpIndexes, Intrinsic::ID IID) const
InstructionCost getExtendedReductionCost(unsigned Opcode, bool IsUnsigned, Type *ResTy, VectorType *Ty, FastMathFlags FMF, TTI::TargetCostKind CostKind) const
bool allowsMisalignedMemoryAccesses(LLVMContext &Context, unsigned BitWidth, unsigned AddressSpace, Align Alignment, unsigned *Fast) const
const SCEVConstant * getConstantStrideStep(ScalarEvolution *SE, const SCEV *Ptr) const
unsigned getMinPrefetchStride(unsigned NumMemAccesses, unsigned NumStridedMemAccesses, unsigned NumPrefetches, bool HasCall) const
InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) const
unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize, unsigned ChainSizeInBytes, VectorType *VecTy) const
bool isIndexedLoadLegal(TTI::MemIndexedMode Mode, Type *Ty, const DataLayout &DL) const
bool shouldPrefetchAddressSpace(unsigned AS) const
InstructionCost getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind) const
unsigned getReplicationShuffleCost(Type *EltTy, int ReplicationFactor, int VF, const APInt &DemandedDstElts, TTI::TargetCostKind CostKind)
bool isSourceOfDivergence(const Value *V) const
bool enableAggressiveInterleaving(bool LoopHasReductions) const
unsigned getMaxInterleaveFactor(ElementCount VF) const
InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, TTI::TargetCostKind CostKind, const Instruction *I) const
std::optional< unsigned > getCacheAssociativity(TargetTransformInfo::CacheLevel Level) const
bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) const
InstructionCost getArithmeticInstrCost(unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Opd1Info, TTI::OperandValueInfo Opd2Info, ArrayRef< const Value * > Args, const Instruction *CxtI=nullptr) const
TTI::AddressingModeKind getPreferredAddressingMode(const Loop *L, ScalarEvolution *SE) const
bool forceScalarizeMaskedGather(VectorType *DataType, Align Alignment) const
bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info) const
unsigned getInliningCostBenefitAnalysisSavingsMultiplier() const
bool canHaveNonUndefGlobalInitializerInAddressSpace(unsigned AS) const
InstructionCost getMulAccReductionCost(bool IsUnsigned, Type *ResTy, VectorType *Ty, TTI::TargetCostKind CostKind) const
bool isIndexedStoreLegal(TTI::MemIndexedMode Mode, Type *Ty, const DataLayout &DL) const
bool hasDivRemOp(Type *DataType, bool IsSigned) const
InstructionCost getAddressComputationCost(Type *Tp, ScalarEvolution *, const SCEV *) const
InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, CmpInst::Predicate VecPred, TTI::TargetCostKind CostKind, const Instruction *I) const
TTI::MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const
InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Ty, ArrayRef< int > Mask, TTI::TargetCostKind CostKind, int Index, VectorType *SubTp, ArrayRef< const Value * > Args=std::nullopt) const
bool preferInLoopReduction(unsigned Opcode, Type *Ty, TTI::ReductionFlags Flags) const
InstructionCost getOperandsScalarizationOverhead(ArrayRef< const Value * > Args, ArrayRef< Type * > Tys, TTI::TargetCostKind CostKind) const
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const
bool isConstantStridedAccessLessThan(ScalarEvolution *SE, const SCEV *Ptr, int64_t MergeDistance) const
InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind) const
bool isLoweredToCall(const Function *F) const
bool hasBranchDivergence(const Function *F=nullptr) const
TargetTransformInfoImplBase(const DataLayout &DL)
const char * getRegisterClassName(unsigned ClassID) const
bool isElementTypeLegalForScalableVector(Type *Ty) const
bool preferPredicateOverEpilogue(TailFoldingInfo *TFI) const
bool isLegalToVectorizeReduction(const RecurrenceDescriptor &RdxDesc, ElementCount VF) const
InstructionCost getScalarizationOverhead(VectorType *Ty, const APInt &DemandedElts, bool Insert, bool Extract, TTI::TargetCostKind CostKind) const
unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const
TailFoldingStyle getPreferredTailFoldingStyle(bool IVUpdateMayOverflow=true) const
InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, const Instruction *I=nullptr) const
InstructionCost getCostOfKeepingLiveOverCall(ArrayRef< Type * > Tys) const
InstructionCost getMinMaxReductionCost(Intrinsic::ID IID, VectorType *, FastMathFlags, TTI::TargetCostKind) const
InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, TTI::TargetCostKind CostKind, unsigned Index, Value *Op0, Value *Op1) const
unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const
InstructionCost getMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind, TTI::OperandValueInfo OpInfo, const Instruction *I) const
bool useColdCCForColdCall(Function &F) const
bool shouldExpandReduction(const IntrinsicInst *II) const
bool isLegalMaskedScatter(Type *DataType, Align Alignment) const
unsigned getNumberOfRegisters(unsigned ClassID) const
InstructionCost getExtractWithExtendCost(unsigned Opcode, Type *Dst, VectorType *VecTy, unsigned Index) const
InstructionCost getGEPCost(Type *PointeeType, const Value *Ptr, ArrayRef< const Value * > Operands, Type *AccessType, TTI::TargetCostKind CostKind) const
bool isLegalNTLoad(Type *DataType, Align Alignment) const
std::optional< Value * > simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known, bool &KnownBitsComputed) const
bool forceScalarizeMaskedScatter(VectorType *DataType, Align Alignment) const
bool hasActiveVectorLength(unsigned Opcode, Type *DataType, Align Alignment) const
bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, const SmallBitVector &OpcodeMask) const
bool isLegalMaskedLoad(Type *DataType, Align Alignment) const
bool isValidAddrSpaceCast(unsigned FromAS, unsigned ToAS) const
std::optional< Instruction * > instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const
InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace) const
bool isLegalAddScalableImmediate(int64_t Imm) const
bool isLegalMaskedCompressStore(Type *DataType, Align Alignment) const
InstructionCost getAltInstrCost(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, const SmallBitVector &OpcodeMask, TTI::TargetCostKind CostKind) const
TargetTransformInfoImplBase(const TargetTransformInfoImplBase &Arg)=default
bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const
ElementCount getMinimumVF(unsigned ElemWidth, bool IsScalable) const
bool shouldBuildLookupTablesForConstant(Constant *C) const
Value * rewriteIntrinsicWithAddressSpace(IntrinsicInst *II, Value *OldV, Value *NewV) const
CRTP base class for use as a mix-in that aids implementing a TargetTransformInfo-compatible class.
bool supportsTailCallFor(const CallBase *CB) const
InstructionCost getGEPCost(Type *PointeeType, const Value *Ptr, ArrayRef< const Value * > Operands, Type *AccessType, TTI::TargetCostKind CostKind)
InstructionCost getPointersChainCost(ArrayRef< const Value * > Ptrs, const Value *Base, const TTI::PointersChainInfo &Info, Type *AccessTy, TTI::TargetCostKind CostKind)
InstructionCost getInstructionCost(const User *U, ArrayRef< const Value * > Operands, TTI::TargetCostKind CostKind)
bool isExpensiveToSpeculativelyExecute(const Instruction *I)
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
static CastContextHint getCastContextHint(const Instruction *I)
Calculates a CastContextHint from I.
static OperandValueInfo getOperandInfo(const Value *V)
Collect properties of V used in cost analysis, e.g. OP_PowerOf2.
TargetCostKind
The kind of cost model.
@ TCK_RecipThroughput
Reciprocal throughput.
@ TCK_CodeSize
Instruction code size.
@ TCK_SizeAndLatency
The weighted sum of size and latency.
@ TCK_Latency
The latency of instruction.
PopcntSupportKind
Flags indicating the kind of support for population count.
@ TCC_Expensive
The cost of a 'div' instruction on x86.
@ TCC_Free
Expected to fold away in lowering.
@ TCC_Basic
The cost of a typical 'add' instruction.
MemIndexedMode
The type of load/store indexing.
ShuffleKind
The various kinds of shuffle patterns for vector queries.
@ SK_InsertSubvector
InsertSubvector. Index indicates start offset.
@ SK_Select
Selects elements from the corresponding lane of either source operand.
@ SK_PermuteSingleSrc
Shuffle elements of single source vector with any shuffle mask.
@ SK_Transpose
Transpose two vectors.
@ SK_Splice
Concatenates elements from the first input vector with elements of the second input vector.
@ SK_Broadcast
Broadcast element 0 to all other elements.
@ SK_PermuteTwoSrc
Merge elements from two source vectors into one with any shuffle mask.
@ SK_Reverse
Reverse the order of the vector.
@ SK_ExtractSubvector
ExtractSubvector Index indicates start offset.
CastContextHint
Represents a hint about the context in which a cast is used.
CacheLevel
The possible cache levels.
This class represents a truncation of integer types.
static constexpr TypeSize getFixed(ScalarTy ExactSize)
Definition: TypeSize.h:330
The instances of the Type class are immutable: once they are created, they are never changed.
Definition: Type.h:45
bool isVectorTy() const
True if this is an instance of VectorType.
Definition: Type.h:265
unsigned getPointerAddressSpace() const
Get the address space of this pointer or pointer vector type.
static IntegerType * getIntNTy(LLVMContext &C, unsigned N)
unsigned getScalarSizeInBits() const LLVM_READONLY
If this is a vector type, return the getPrimitiveSizeInBits value for the element type.
static IntegerType * getInt8Ty(LLVMContext &C)
bool isFloatingPointTy() const
Return true if this is one of the floating-point types.
Definition: Type.h:185
bool isScalableTy() const
Return true if this is a type whose size is a known multiple of vscale.
Type * getScalarType() const
If this is a vector type, return the element type, otherwise return 'this'.
Definition: Type.h:348
This is the common base class for vector predication intrinsics.
LLVM Value Representation.
Definition: Value.h:74
Type * getType() const
All values are typed, get the type of this value.
Definition: Value.h:255
Base class of all SIMD vector types.
Definition: DerivedTypes.h:403
constexpr ScalarTy getFixedValue() const
Definition: TypeSize.h:187
constexpr bool isScalable() const
Returns whether the quantity is scaled by a runtime quantity (vscale).
Definition: TypeSize.h:171
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ Fast
Attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:41
@ C
The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
bool match(Val *V, const Pattern &P)
Definition: PatternMatch.h:49
auto m_LogicalOr()
Matches L || R where L and R are arbitrary values.
class_match< Value > m_Value()
Match an arbitrary value and ignore it.
Definition: PatternMatch.h:92
auto m_LogicalAnd()
Matches L && R where L and R are arbitrary values.
match_combine_or< LTy, RTy > m_CombineOr(const LTy &L, const RTy &R)
Combine two pattern matchers matching L || R.
Definition: PatternMatch.h:234
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
@ Length
Definition: DWP.cpp:456
auto enumerate(FirstRange &&First, RestRanges &&...Rest)
Given two or more input ranges, returns a new range whose values are are tuples (A,...
Definition: STLExtras.h:2415
AddressSpace
Definition: NVPTXBaseInfo.h:21
Value * getSplatValue(const Value *V)
Get splat value if the input is a splat vector or return nullptr.
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
Definition: STLExtras.h:1738
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
Definition: MathExtras.h:264
constexpr int PoisonMaskElem
constexpr unsigned BitWidth
Definition: BitmaskEnum.h:191
gep_type_iterator gep_type_begin(const User *GEP)
InstructionCost Cost
@ DataWithoutLaneMask
Same as Data, but avoids using the get.active.lane.mask intrinsic to calculate the mask and instead i...
This struct is a compact representation of a valid (non-zero power of two) alignment.
Definition: Alignment.h:39
Attributes of a target dependent hardware loop.
Information about a load/store intrinsic defined by the target.
Returns options for expansion of memcmp. IsZeroCmp is.
Describe known properties for a set of pointers.
Flags describing the kind of vector reduction.
Parameters that control the generic loop unrolling transformation.