LLVM API Documentation
00001 //===-- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information -------------===// 00002 // 00003 // The LLVM Compiler Infrastructure 00004 // 00005 // This file is distributed under the University of Illinois Open Source 00006 // License. See LICENSE.TXT for details. 00007 // 00008 //===----------------------------------------------------------------------===// 00009 // 00010 // This file contains the Thumb-1 implementation of the TargetInstrInfo class. 00011 // 00012 //===----------------------------------------------------------------------===// 00013 00014 #include "Thumb1InstrInfo.h" 00015 #include "ARM.h" 00016 #include "llvm/CodeGen/MachineFrameInfo.h" 00017 #include "llvm/CodeGen/MachineInstrBuilder.h" 00018 #include "llvm/CodeGen/MachineMemOperand.h" 00019 #include "llvm/CodeGen/MachineRegisterInfo.h" 00020 #include "llvm/MC/MCInst.h" 00021 00022 using namespace llvm; 00023 00024 Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI) 00025 : ARMBaseInstrInfo(STI), RI(*this, STI) { 00026 } 00027 00028 /// getNoopForMachoTarget - Return the noop instruction to use for a noop. 00029 void Thumb1InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const { 00030 NopInst.setOpcode(ARM::tMOVr); 00031 NopInst.addOperand(MCOperand::CreateReg(ARM::R8)); 00032 NopInst.addOperand(MCOperand::CreateReg(ARM::R8)); 00033 NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); 00034 NopInst.addOperand(MCOperand::CreateReg(0)); 00035 } 00036 00037 unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const { 00038 return 0; 00039 } 00040 00041 void Thumb1InstrInfo::copyPhysReg(MachineBasicBlock &MBB, 00042 MachineBasicBlock::iterator I, DebugLoc DL, 00043 unsigned DestReg, unsigned SrcReg, 00044 bool KillSrc) const { 00045 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) 00046 .addReg(SrcReg, getKillRegState(KillSrc))); 00047 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) && 00048 "Thumb1 can only copy GPR registers"); 00049 } 00050 00051 void Thumb1InstrInfo:: 00052 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 00053 unsigned SrcReg, bool isKill, int FI, 00054 const TargetRegisterClass *RC, 00055 const TargetRegisterInfo *TRI) const { 00056 assert((RC == &ARM::tGPRRegClass || 00057 (TargetRegisterInfo::isPhysicalRegister(SrcReg) && 00058 isARMLowRegister(SrcReg))) && "Unknown regclass!"); 00059 00060 if (RC == &ARM::tGPRRegClass || 00061 (TargetRegisterInfo::isPhysicalRegister(SrcReg) && 00062 isARMLowRegister(SrcReg))) { 00063 DebugLoc DL; 00064 if (I != MBB.end()) DL = I->getDebugLoc(); 00065 00066 MachineFunction &MF = *MBB.getParent(); 00067 MachineFrameInfo &MFI = *MF.getFrameInfo(); 00068 MachineMemOperand *MMO = 00069 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI), 00070 MachineMemOperand::MOStore, 00071 MFI.getObjectSize(FI), 00072 MFI.getObjectAlignment(FI)); 00073 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSTRspi)) 00074 .addReg(SrcReg, getKillRegState(isKill)) 00075 .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 00076 } 00077 } 00078 00079 void Thumb1InstrInfo:: 00080 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 00081 unsigned DestReg, int FI, 00082 const TargetRegisterClass *RC, 00083 const TargetRegisterInfo *TRI) const { 00084 assert((RC == &ARM::tGPRRegClass || 00085 (TargetRegisterInfo::isPhysicalRegister(DestReg) && 00086 isARMLowRegister(DestReg))) && "Unknown regclass!"); 00087 00088 if (RC == &ARM::tGPRRegClass || 00089 (TargetRegisterInfo::isPhysicalRegister(DestReg) && 00090 isARMLowRegister(DestReg))) { 00091 DebugLoc DL; 00092 if (I != MBB.end()) DL = I->getDebugLoc(); 00093 00094 MachineFunction &MF = *MBB.getParent(); 00095 MachineFrameInfo &MFI = *MF.getFrameInfo(); 00096 MachineMemOperand *MMO = 00097 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI), 00098 MachineMemOperand::MOLoad, 00099 MFI.getObjectSize(FI), 00100 MFI.getObjectAlignment(FI)); 00101 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tLDRspi), DestReg) 00102 .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 00103 } 00104 }