LLVM API Documentation

Classes | Defines | Enumerations | Functions | Variables
X86InstrInfo.cpp File Reference
#include "X86InstrInfo.h"
#include "X86.h"
#include "X86InstrBuilder.h"
#include "X86MachineFunctionInfo.h"
#include "X86Subtarget.h"
#include "X86TargetMachine.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/CodeGen/LiveVariables.h"
#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/StackMaps.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/LLVMContext.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInst.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetOptions.h"
#include <limits>
#include "X86GenInstrInfo.inc"
Include dependency graph for X86InstrInfo.cpp:

Go to the source code of this file.

Classes

struct  X86OpTblEntry

Defines

#define DEBUG_TYPE   "x86-instr-info"
#define GET_INSTRINFO_CTOR_DTOR

Enumerations

enum  {
  TB_INDEX_0 = 0, TB_INDEX_1 = 1, TB_INDEX_2 = 2, TB_INDEX_3 = 3,
  TB_INDEX_MASK = 0xf, TB_NO_REVERSE = 1 << 4, TB_NO_FORWARD = 1 << 5, TB_FOLDED_LOAD = 1 << 6,
  TB_FOLDED_STORE = 1 << 7, TB_ALIGN_SHIFT = 8, TB_ALIGN_NONE = 0 << TB_ALIGN_SHIFT, TB_ALIGN_16 = 16 << TB_ALIGN_SHIFT,
  TB_ALIGN_32 = 32 << TB_ALIGN_SHIFT, TB_ALIGN_64 = 64 << TB_ALIGN_SHIFT, TB_ALIGN_MASK = 0xff << TB_ALIGN_SHIFT
}

Functions

static bool isFrameLoadOpcode (int Opcode)
static bool isFrameStoreOpcode (int Opcode)
static bool regIsPICBase (unsigned BaseReg, const MachineRegisterInfo &MRI)
static bool hasLiveCondCodeDef (MachineInstr *MI)
static unsigned getTruncatedShiftCount (MachineInstr *MI, unsigned ShiftAmtOperandIdx)
static bool isTruncatedShiftCountForLEA (unsigned ShAmt)
static X86::CondCode getCondFromBranchOpc (unsigned BrOpc)
static X86::CondCode getCondFromSETOpc (unsigned Opc)
 getCondFromSETOpc - return condition code of a SET opcode.
static X86::CondCode getSwappedCondition (X86::CondCode CC)
static bool isHReg (unsigned Reg)
 isHReg - Test if the given register is a physical h register.
static unsigned CopyToFromAsymmetricReg (unsigned DestReg, unsigned SrcReg, const X86Subtarget &Subtarget)
static bool MaskRegClassContains (unsigned Reg)
static unsigned copyPhysRegOpcode_AVX512 (unsigned &DestReg, unsigned &SrcReg)
static unsigned getLoadStoreRegOpcode (unsigned Reg, const TargetRegisterClass *RC, bool isStackAligned, const X86Subtarget &STI, bool load)
static unsigned getStoreRegOpcode (unsigned SrcReg, const TargetRegisterClass *RC, bool isStackAligned, const X86Subtarget &STI)
static unsigned getLoadRegOpcode (unsigned DestReg, const TargetRegisterClass *RC, bool isStackAligned, const X86Subtarget &STI)
static bool isRedundantFlagInstr (MachineInstr *FlagI, unsigned SrcReg, unsigned SrcReg2, int ImmValue, MachineInstr *OI)
static bool isDefConvertible (MachineInstr *MI)
static X86::CondCode isUseDefConvertible (MachineInstr *MI)
static bool Expand2AddrUndef (MachineInstrBuilder &MIB, const MCInstrDesc &Desc)
static MachineInstrFuseTwoAddrInst (MachineFunction &MF, unsigned Opcode, const SmallVectorImpl< MachineOperand > &MOs, MachineInstr *MI, const TargetInstrInfo &TII)
static MachineInstrFuseInst (MachineFunction &MF, unsigned Opcode, unsigned OpNo, const SmallVectorImpl< MachineOperand > &MOs, MachineInstr *MI, const TargetInstrInfo &TII)
static MachineInstrMakeM0Inst (const TargetInstrInfo &TII, unsigned Opcode, const SmallVectorImpl< MachineOperand > &MOs, MachineInstr *MI)
static bool hasPartialRegUpdate (unsigned Opcode)
static bool hasUndefRegUpdate (unsigned Opcode)
static const uint16_t * lookup (unsigned opcode, unsigned domain)
static const uint16_t * lookupAVX2 (unsigned opcode, unsigned domain)

Variables

static cl::opt< boolNoFusing ("disable-spill-fusing", cl::desc("Disable fusing of spill code into instructions"))
static cl::opt< boolPrintFailedFusing ("print-failed-fuse-candidates", cl::desc("Print instructions that the allocator wants to"" fuse, but the X86 backend currently can't"), cl::Hidden)
static cl::opt< boolReMatPICStubLoad ("remat-pic-stub-load", cl::desc("Re-materialize load from stub in PIC mode"), cl::init(false), cl::Hidden)
static const uint16_t ReplaceableInstrs [][3]
static const uint16_t ReplaceableInstrsAVX2 [][3]

Define Documentation

#define DEBUG_TYPE   "x86-instr-info"

Definition at line 42 of file X86InstrInfo.cpp.

Definition at line 44 of file X86InstrInfo.cpp.


Enumeration Type Documentation

anonymous enum
Enumerator:
TB_INDEX_0 
TB_INDEX_1 
TB_INDEX_2 
TB_INDEX_3 
TB_INDEX_MASK 
TB_NO_REVERSE 
TB_NO_FORWARD 
TB_FOLDED_LOAD 
TB_FOLDED_STORE 
TB_ALIGN_SHIFT 
TB_ALIGN_NONE 
TB_ALIGN_16 
TB_ALIGN_32 
TB_ALIGN_64 
TB_ALIGN_MASK 

Definition at line 60 of file X86InstrInfo.cpp.


Function Documentation

static unsigned copyPhysRegOpcode_AVX512 ( unsigned DestReg,
unsigned SrcReg 
) [static]
static unsigned CopyToFromAsymmetricReg ( unsigned  DestReg,
unsigned  SrcReg,
const X86Subtarget &  Subtarget 
) [static]

Definition at line 3026 of file X86InstrInfo.cpp.

References contains().

static bool Expand2AddrUndef ( MachineInstrBuilder MIB,
const MCInstrDesc Desc 
) [static]

Expand2AddrUndef - Expand a single-def pseudo instruction to a two-addr instruction with two undef reads of the register being defined. This is used for mapping: xmm4 = V_SET0 to: xmm4 = PXORrr xmm4<undef>, xmm4<undef>

Definition at line 3951 of file X86InstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineInstr::setDesc(), and llvm::RegState::Undef.

static MachineInstr* FuseInst ( MachineFunction MF,
unsigned  Opcode,
unsigned  OpNo,
const SmallVectorImpl< MachineOperand > &  MOs,
MachineInstr MI,
const TargetInstrInfo TII 
) [static]
static MachineInstr* FuseTwoAddrInst ( MachineFunction MF,
unsigned  Opcode,
const SmallVectorImpl< MachineOperand > &  MOs,
MachineInstr MI,
const TargetInstrInfo TII 
) [static]
static X86::CondCode getCondFromBranchOpc ( unsigned  BrOpc) [static]
static X86::CondCode getCondFromSETOpc ( unsigned  Opc) [static]
static unsigned getLoadRegOpcode ( unsigned  DestReg,
const TargetRegisterClass RC,
bool  isStackAligned,
const X86Subtarget &  STI 
) [static]

Definition at line 3276 of file X86InstrInfo.cpp.

References getLoadStoreRegOpcode().

static unsigned getLoadStoreRegOpcode ( unsigned  Reg,
const TargetRegisterClass RC,
bool  isStackAligned,
const X86Subtarget &  STI,
bool  load 
) [static]
static unsigned getStoreRegOpcode ( unsigned  SrcReg,
const TargetRegisterClass RC,
bool  isStackAligned,
const X86Subtarget &  STI 
) [static]

Definition at line 3268 of file X86InstrInfo.cpp.

References getLoadStoreRegOpcode().

getSwappedCondition - assume the flags are set by MI(a,b), return the condition code if we modify the instructions such that flags are set by MI(b,a).

Definition at line 2655 of file X86InstrInfo.cpp.

References llvm::X86::COND_A, llvm::X86::COND_AE, llvm::X86::COND_B, llvm::X86::COND_BE, MSP430CC::COND_E, llvm::X86::COND_G, MSP430CC::COND_GE, MSP430CC::COND_INVALID, MSP430CC::COND_L, llvm::X86::COND_LE, and MSP430CC::COND_NE.

static unsigned getTruncatedShiftCount ( MachineInstr MI,
unsigned  ShiftAmtOperandIdx 
) [inline, static]

getTruncatedShiftCount - check whether the shift count for a machine operand is non-zero.

Definition at line 1843 of file X86InstrInfo.cpp.

References llvm::MachineInstr::getDesc(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOperand(), llvm::X86II::REX_W, and llvm::MCInstrDesc::TSFlags.

Referenced by isDefConvertible().

static bool hasLiveCondCodeDef ( MachineInstr MI) [static]

hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.

Definition at line 1830 of file X86InstrInfo.cpp.

References llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isDead(), llvm::MachineOperand::isDef(), and llvm::MachineOperand::isReg().

static bool hasPartialRegUpdate ( unsigned  Opcode) [static]

hasPartialRegUpdate - Return true for all instructions that only update the first 32 or 64-bits of the destination register and leave the rest unmodified. This can be used to avoid folding loads if the instructions only update part of the destination register, and the non-updated part is not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these instructions breaks the partial register dependency and it can improve performance. e.g.:

movss (rdi), xmm0 cvtss2sd xmm0, xmm0

Instead of cvtss2sd (rdi), xmm0

FIXME: This should be turned into a TSFlags.

Definition at line 4194 of file X86InstrInfo.cpp.

static bool hasUndefRegUpdate ( unsigned  Opcode) [static]

Definition at line 4247 of file X86InstrInfo.cpp.

static bool isDefConvertible ( MachineInstr MI) [inline, static]

isDefConvertible - check whether the definition can be converted to remove a comparison against zero.

Definition at line 3472 of file X86InstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), getTruncatedShiftCount(), and isTruncatedShiftCountForLEA().

static bool isFrameLoadOpcode ( int  Opcode) [static]

Definition at line 1527 of file X86InstrInfo.cpp.

static bool isFrameStoreOpcode ( int  Opcode) [static]

Definition at line 1557 of file X86InstrInfo.cpp.

static bool isHReg ( unsigned  Reg) [static]

isHReg - Test if the given register is a physical h register.

Definition at line 3021 of file X86InstrInfo.cpp.

Referenced by getLoadStoreRegOpcode().

static bool isRedundantFlagInstr ( MachineInstr FlagI,
unsigned  SrcReg,
unsigned  SrcReg2,
int  ImmValue,
MachineInstr OI 
) [inline, static]

isRedundantFlagInstr - check whether the first instruction, whose only purpose is to update flags, can be made redundant. CMPrr can be made redundant by SUBrr if the operands are the same. This function can be extended later on. SrcReg, SrcRegs: register operands for FlagI. ImmValue: immediate for FlagI if it takes an immediate.

Definition at line 3433 of file X86InstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::MachineOperand::getReg().

static bool isTruncatedShiftCountForLEA ( unsigned  ShAmt) [inline, static]

isTruncatedShiftCountForLEA - check whether the given shift count is appropriate can be represented by a LEA instruction.

Definition at line 1853 of file X86InstrInfo.cpp.

Referenced by isDefConvertible().

static X86::CondCode isUseDefConvertible ( MachineInstr MI) [static]

isUseDefConvertible - check whether the use can be converted to remove a comparison against zero.

Definition at line 3560 of file X86InstrInfo.cpp.

References llvm::X86::COND_B, MSP430CC::COND_E, MSP430CC::COND_INVALID, and llvm::MachineInstr::getOpcode().

static const uint16_t* lookup ( unsigned  opcode,
unsigned  domain 
) [static]

Definition at line 5259 of file X86InstrInfo.cpp.

References llvm::array_lengthof(), and ReplaceableInstrs.

Referenced by llvm::Module::getNamedMetadata().

static const uint16_t* lookupAVX2 ( unsigned  opcode,
unsigned  domain 
) [static]

Definition at line 5266 of file X86InstrInfo.cpp.

References llvm::array_lengthof(), and ReplaceableInstrsAVX2.

static MachineInstr* MakeM0Inst ( const TargetInstrInfo TII,
unsigned  Opcode,
const SmallVectorImpl< MachineOperand > &  MOs,
MachineInstr MI 
) [static]
static bool MaskRegClassContains ( unsigned  Reg) [inline, static]

Definition at line 3067 of file X86InstrInfo.cpp.

Referenced by copyPhysRegOpcode_AVX512().

static bool regIsPICBase ( unsigned  BaseReg,
const MachineRegisterInfo MRI 
) [static]

regIsPICBase - Return true if register is PIC base (i.e.g defined by X86::MOVPC32r.

Definition at line 1633 of file X86InstrInfo.cpp.

References llvm::MachineRegisterInfo::def_instr_begin(), llvm::MachineRegisterInfo::def_instr_end(), llvm::MachineInstr::getOpcode(), and I.


Variable Documentation

cl::opt<bool> NoFusing("disable-spill-fusing", cl::desc("Disable fusing of spill code into instructions")) [static]
cl::opt<bool> PrintFailedFusing("print-failed-fuse-candidates", cl::desc("Print instructions that the allocator wants to"" fuse, but the X86 backend currently can't"), cl::Hidden) [static]
cl::opt<bool> ReMatPICStubLoad("remat-pic-stub-load", cl::desc("Re-materialize load from stub in PIC mode"), cl::init(false), cl::Hidden) [static]
const uint16_t ReplaceableInstrs[][3] [static]

Definition at line 5192 of file X86InstrInfo.cpp.

Referenced by lookup().

const uint16_t ReplaceableInstrsAVX2[][3] [static]
Initial value:
 {
  
  { X86::VANDNPSYrm,   X86::VANDNPDYrm,   X86::VPANDNYrm   },
  { X86::VANDNPSYrr,   X86::VANDNPDYrr,   X86::VPANDNYrr   },
  { X86::VANDPSYrm,    X86::VANDPDYrm,    X86::VPANDYrm    },
  { X86::VANDPSYrr,    X86::VANDPDYrr,    X86::VPANDYrr    },
  { X86::VORPSYrm,     X86::VORPDYrm,     X86::VPORYrm     },
  { X86::VORPSYrr,     X86::VORPDYrr,     X86::VPORYrr     },
  { X86::VXORPSYrm,    X86::VXORPDYrm,    X86::VPXORYrm    },
  { X86::VXORPSYrr,    X86::VXORPDYrr,    X86::VPXORYrr    },
  { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
  { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
  { X86::VINSERTF128rm,  X86::VINSERTF128rm,  X86::VINSERTI128rm },
  { X86::VINSERTF128rr,  X86::VINSERTF128rr,  X86::VINSERTI128rr },
  { X86::VPERM2F128rm,   X86::VPERM2F128rm,   X86::VPERM2I128rm },
  { X86::VPERM2F128rr,   X86::VPERM2F128rr,   X86::VPERM2I128rr },
  { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm},
  { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr},
  { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr},
  { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm},
  { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr},
  { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm}
}

Definition at line 5232 of file X86InstrInfo.cpp.

Referenced by lookupAVX2().