LLVM API Documentation

Classes | Defines | Enumerations | Functions | Variables
X86InstrInfo.cpp File Reference
#include "X86InstrInfo.h"
#include "X86.h"
#include "X86InstrBuilder.h"
#include "X86MachineFunctionInfo.h"
#include "X86Subtarget.h"
#include "X86TargetMachine.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/CodeGen/LiveVariables.h"
#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/LLVMContext.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCInst.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetOptions.h"
#include <limits>
#include "X86GenInstrInfo.inc"
Include dependency graph for X86InstrInfo.cpp:

Go to the source code of this file.

Classes

struct  X86OpTblEntry

Defines

#define GET_INSTRINFO_CTOR

Enumerations

enum  {
  TB_INDEX_0 = 0, TB_INDEX_1 = 1, TB_INDEX_2 = 2, TB_INDEX_3 = 3,
  TB_INDEX_MASK = 0xf, TB_NO_REVERSE = 1 << 4, TB_NO_FORWARD = 1 << 5, TB_FOLDED_LOAD = 1 << 6,
  TB_FOLDED_STORE = 1 << 7, TB_ALIGN_SHIFT = 8, TB_ALIGN_NONE = 0 << TB_ALIGN_SHIFT, TB_ALIGN_16 = 16 << TB_ALIGN_SHIFT,
  TB_ALIGN_32 = 32 << TB_ALIGN_SHIFT, TB_ALIGN_MASK = 0xff << TB_ALIGN_SHIFT
}

Functions

static bool isFrameLoadOpcode (int Opcode)
static bool isFrameStoreOpcode (int Opcode)
static bool regIsPICBase (unsigned BaseReg, const MachineRegisterInfo &MRI)
static bool isSafeToClobberEFLAGS (MachineBasicBlock &MBB, MachineBasicBlock::iterator I)
static bool hasLiveCondCodeDef (MachineInstr *MI)
static X86::CondCode getCondFromBranchOpc (unsigned BrOpc)
static X86::CondCode getCondFromSETOpc (unsigned Opc)
 getCondFromSETOpc - return condition code of a SET opcode.
static X86::CondCode getSwappedCondition (X86::CondCode CC)
static unsigned getSETFromCond (X86::CondCode CC, bool HasMemoryOperand)
static unsigned getCMovFromCond (X86::CondCode CC, unsigned RegBytes, bool HasMemoryOperand)
static bool isHReg (unsigned Reg)
 isHReg - Test if the given register is a physical h register.
static unsigned CopyToFromAsymmetricReg (unsigned DestReg, unsigned SrcReg, bool HasAVX)
static unsigned getLoadStoreRegOpcode (unsigned Reg, const TargetRegisterClass *RC, bool isStackAligned, const TargetMachine &TM, bool load)
static unsigned getStoreRegOpcode (unsigned SrcReg, const TargetRegisterClass *RC, bool isStackAligned, TargetMachine &TM)
static unsigned getLoadRegOpcode (unsigned DestReg, const TargetRegisterClass *RC, bool isStackAligned, const TargetMachine &TM)
static bool isRedundantFlagInstr (MachineInstr *FlagI, unsigned SrcReg, unsigned SrcReg2, int ImmValue, MachineInstr *OI)
static bool isDefConvertible (MachineInstr *MI)
static bool Expand2AddrUndef (MachineInstrBuilder &MIB, const MCInstrDesc &Desc)
static MachineInstr * FuseTwoAddrInst (MachineFunction &MF, unsigned Opcode, const SmallVectorImpl< MachineOperand > &MOs, MachineInstr *MI, const TargetInstrInfo &TII)
static MachineInstr * FuseInst (MachineFunction &MF, unsigned Opcode, unsigned OpNo, const SmallVectorImpl< MachineOperand > &MOs, MachineInstr *MI, const TargetInstrInfo &TII)
static MachineInstr * MakeM0Inst (const TargetInstrInfo &TII, unsigned Opcode, const SmallVectorImpl< MachineOperand > &MOs, MachineInstr *MI)
static bool hasPartialRegUpdate (unsigned Opcode)
static const uint16_t * lookup (unsigned opcode, unsigned domain)
static const uint16_t * lookupAVX2 (unsigned opcode, unsigned domain)

Variables

static cl::opt< bool > NoFusing ("disable-spill-fusing", cl::desc("Disable fusing of spill code into instructions"))
static cl::opt< bool > PrintFailedFusing ("print-failed-fuse-candidates", cl::desc("Print instructions that the allocator wants to"" fuse, but the X86 backend currently can't"), cl::Hidden)
static cl::opt< bool > ReMatPICStubLoad ("remat-pic-stub-load", cl::desc("Re-materialize load from stub in PIC mode"), cl::init(false), cl::Hidden)
static const uint16_t ReplaceableInstrs [][3]
static const uint16_t ReplaceableInstrsAVX2 [][3]

Define Documentation

#define GET_INSTRINFO_CTOR

Definition at line 38 of file X86InstrInfo.cpp.

Enumeration Type Documentation

anonymous enum
Enumerator:
TB_INDEX_0 
TB_INDEX_1 
TB_INDEX_2 
TB_INDEX_3 
TB_INDEX_MASK 
TB_NO_REVERSE 
TB_NO_FORWARD 
TB_FOLDED_LOAD 
TB_FOLDED_STORE 
TB_ALIGN_SHIFT 
TB_ALIGN_NONE 
TB_ALIGN_16 
TB_ALIGN_32 
TB_ALIGN_MASK 

Definition at line 56 of file X86InstrInfo.cpp.

Function Documentation

static unsigned CopyToFromAsymmetricReg ( unsigned  DestReg,
unsigned  SrcReg,
bool  HasAVX 
) [static]

Definition at line 2791 of file X86InstrInfo.cpp.

Referenced by llvm::X86InstrInfo::copyPhysReg().

static bool Expand2AddrUndef ( MachineInstrBuilder &  MIB,
const MCInstrDesc &  Desc 
) [static]

Expand2AddrUndef - Expand a single-def pseudo instruction to a two-addr instruction with two undef reads of the register being defined. This is used for mapping: xmm4 = V_SET0 to: xmm4 = PXORrr xmm4<undef>, xmm4<undef>

Definition at line 3574 of file X86InstrInfo.cpp.

References llvm::MachineInstrBuilder::addReg(), llvm::MCInstrDesc::getNumOperands(), and llvm::RegState::Undef.

Referenced by llvm::X86InstrInfo::expandPostRAPseudo().

static MachineInstr* FuseInst ( MachineFunction &  MF,
unsigned  Opcode,
unsigned  OpNo,
const SmallVectorImpl< MachineOperand > &  MOs,
MachineInstr *  MI,
const TargetInstrInfo &  TII 
) [static]

Definition at line 3660 of file X86InstrInfo.cpp.

References llvm::addOffset(), llvm::MachineInstrBuilder::addOperand(), llvm::MachineFunction::CreateMachineInstr(), llvm::MCInstrInfo::get(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::isReg(), and llvm::SmallVectorTemplateCommon< T >::size().

Referenced by llvm::X86InstrInfo::foldMemoryOperandImpl().

static MachineInstr* FuseTwoAddrInst ( MachineFunction &  MF,
unsigned  Opcode,
const SmallVectorImpl< MachineOperand > &  MOs,
MachineInstr *  MI,
const TargetInstrInfo &  TII 
) [static]

Definition at line 3632 of file X86InstrInfo.cpp.

References llvm::addOffset(), llvm::MachineInstrBuilder::addOperand(), llvm::MachineFunction::CreateMachineInstr(), llvm::MCInstrInfo::get(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::getNumOperands(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), and llvm::SmallVectorTemplateCommon< T >::size().

Referenced by llvm::X86InstrInfo::foldMemoryOperandImpl().

static unsigned getCMovFromCond ( X86::CondCode  CC,
unsigned  RegBytes,
bool  HasMemoryOperand 
) [static]

getCMovFromCond - Return a cmov opcode for the given condition, register size in bytes, and operand type.

Definition at line 2464 of file X86InstrInfo.cpp.

References llvm_unreachable.

Referenced by llvm::X86InstrInfo::insertSelect(), and llvm::X86InstrInfo::optimizeCompareInstr().

static X86::CondCode getCondFromBranchOpc ( unsigned  BrOpc) [static]

Definition at line 2270 of file X86InstrInfo.cpp.

References llvm::X86::COND_A, llvm::X86::COND_AE, llvm::X86::COND_B, llvm::X86::COND_BE, llvm::X86::COND_E, llvm::X86::COND_G, llvm::X86::COND_GE, llvm::X86::COND_INVALID, llvm::X86::COND_L, llvm::X86::COND_LE, llvm::X86::COND_NE, llvm::X86::COND_NO, llvm::X86::COND_NP, llvm::X86::COND_NS, llvm::X86::COND_O, llvm::X86::COND_P, and llvm::X86::COND_S.

Referenced by llvm::X86InstrInfo::AnalyzeBranch(), llvm::X86InstrInfo::optimizeCompareInstr(), and llvm::X86InstrInfo::RemoveBranch().

static X86::CondCode getCondFromSETOpc ( unsigned  Opc) [static]

getCondFromSETOpc - return condition code of a SET opcode.

Definition at line 2293 of file X86InstrInfo.cpp.

References llvm::X86::COND_A, llvm::X86::COND_AE, llvm::X86::COND_B, llvm::X86::COND_BE, llvm::X86::COND_E, llvm::X86::COND_G, llvm::X86::COND_GE, llvm::X86::COND_INVALID, llvm::X86::COND_L, llvm::X86::COND_LE, llvm::X86::COND_NE, llvm::X86::COND_NO, llvm::X86::COND_NP, llvm::X86::COND_NS, llvm::X86::COND_O, llvm::X86::COND_P, and llvm::X86::COND_S.

Referenced by llvm::X86InstrInfo::optimizeCompareInstr().

static unsigned getLoadRegOpcode ( unsigned  DestReg,
const TargetRegisterClass *  RC,
bool  isStackAligned,
const TargetMachine &  TM 
) [static]

Definition at line 2977 of file X86InstrInfo.cpp.

References getLoadStoreRegOpcode().

Referenced by llvm::X86InstrInfo::loadRegFromAddr(), llvm::X86InstrInfo::loadRegFromStackSlot(), and llvm::X86InstrInfo::unfoldMemoryOperand().

static unsigned getLoadStoreRegOpcode ( unsigned  Reg,
const TargetRegisterClass *  RC,
bool  isStackAligned,
const TargetMachine &  TM,
bool  load 
) [static]

Definition at line 2902 of file X86InstrInfo.cpp.

References llvm::TargetRegisterClass::getSize(), llvm::TargetMachine::getSubtarget(), llvm::X86Subtarget::is64Bit(), isHReg(), and llvm_unreachable.

Referenced by getLoadRegOpcode(), and getStoreRegOpcode().

static unsigned getSETFromCond ( X86::CondCode  CC,
bool  HasMemoryOperand 
) [static]

getSETFromCond - Return a set opcode for the given condition and whether it has memory operand.

Definition at line 2437 of file X86InstrInfo.cpp.

Referenced by llvm::X86InstrInfo::optimizeCompareInstr().

static unsigned getStoreRegOpcode ( unsigned  SrcReg,
const TargetRegisterClass *  RC,
bool  isStackAligned,
TargetMachine &  TM 
) [static]

Definition at line 2969 of file X86InstrInfo.cpp.

References getLoadStoreRegOpcode().

Referenced by llvm::X86InstrInfo::storeRegToAddr(), llvm::X86InstrInfo::storeRegToStackSlot(), and llvm::X86InstrInfo::unfoldMemoryOperand().

static X86::CondCode getSwappedCondition ( X86::CondCode  CC) [static]

getSwappedCondition - assume the flags are set by MI(a,b), return the condition code if we modify the instructions such that flags are set by MI(b,a).

Definition at line 2419 of file X86InstrInfo.cpp.

References llvm::X86::COND_A, llvm::X86::COND_AE, llvm::X86::COND_B, llvm::X86::COND_BE, llvm::X86::COND_E, llvm::X86::COND_G, llvm::X86::COND_GE, llvm::X86::COND_INVALID, llvm::X86::COND_L, llvm::X86::COND_LE, and llvm::X86::COND_NE.

Referenced by llvm::X86InstrInfo::optimizeCompareInstr().

static bool hasLiveCondCodeDef ( MachineInstr *  MI) [static]

hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.

Definition at line 1764 of file X86InstrInfo.cpp.

References llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isDead(), llvm::MachineOperand::isDef(), and llvm::MachineOperand::isReg().

Referenced by llvm::X86InstrInfo::convertToThreeAddress().

static bool hasPartialRegUpdate ( unsigned  Opcode) [static]

hasPartialRegUpdate - Return true for all instructions that only update the first 32 or 64-bits of the destination register and leave the rest unmodified. This can be used to avoid folding loads if the instructions only update part of the destination register, and the non-updated part is not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these instructions breaks the partial register dependency and it can improve performance. e.g.:

movss (rdi), xmm0 cvtss2sd xmm0, xmm0

Instead of cvtss2sd (rdi), xmm0

FIXME: This should be turned into a TSFlags.

Definition at line 3828 of file X86InstrInfo.cpp.

Referenced by llvm::X86InstrInfo::foldMemoryOperandImpl(), and llvm::X86InstrInfo::getPartialRegUpdateClearance().

static bool isDefConvertible ( MachineInstr *  MI) [inline, static]

isDefConvertible - check whether the definition can be converted to remove a comparison against zero.

Definition at line 3171 of file X86InstrInfo.cpp.

References llvm::MachineInstr::getOpcode().

Referenced by llvm::X86InstrInfo::optimizeCompareInstr().

static bool isFrameLoadOpcode ( int  Opcode) [static]

Definition at line 1442 of file X86InstrInfo.cpp.

Referenced by llvm::X86InstrInfo::isLoadFromStackSlot(), and llvm::X86InstrInfo::isLoadFromStackSlotPostFE().

static bool isFrameStoreOpcode ( int  Opcode) [static]

Definition at line 1470 of file X86InstrInfo.cpp.

Referenced by llvm::X86InstrInfo::isStoreToStackSlot(), and llvm::X86InstrInfo::isStoreToStackSlotPostFE().

static bool isHReg ( unsigned  Reg) [static]

isHReg - Test if the given register is a physical h register.

Definition at line 2786 of file X86InstrInfo.cpp.

Referenced by llvm::X86InstrInfo::copyPhysReg(), and getLoadStoreRegOpcode().

static bool isRedundantFlagInstr ( MachineInstr *  FlagI,
unsigned  SrcReg,
unsigned  SrcReg2,
int  ImmValue,
MachineInstr *  OI 
) [inline, static]

isRedundantFlagInstr - check whether the first instruction, whose only purpose is to update flags, can be made redundant. CMPrr can be made redundant by SUBrr if the operands are the same. This function can be extended later on. SrcReg, SrcRegs: register operands for FlagI. ImmValue: immediate for FlagI if it takes an immediate.

Definition at line 3132 of file X86InstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::MachineOperand::getReg().

Referenced by llvm::X86InstrInfo::optimizeCompareInstr().

static bool isSafeToClobberEFLAGS ( MachineBasicBlock &  MBB,
MachineBasicBlock::iterator  I 
) [static]

isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that would clobber the EFLAGS condition register. Note the result may be conservative. If it cannot definitely determine the safety after visiting a few instructions in each direction it assumes it's not safe.

Definition at line 1642 of file X86InstrInfo.cpp.

References llvm::MachineBasicBlock::begin(), llvm::MachineOperand::clobbersPhysReg(), llvm::MachineBasicBlock::end(), llvm::MachineOperand::getReg(), I, llvm::MachineOperand::isDead(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isKill(), llvm::MachineBasicBlock::isLiveIn(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isRegMask(), llvm::MachineOperand::isUse(), llvm::MachineBasicBlock::succ_begin(), and llvm::MachineBasicBlock::succ_end().

Referenced by llvm::X86InstrInfo::reMaterialize().

static const uint16_t* lookup ( unsigned  opcode,
unsigned  domain 
) [static]

Definition at line 4663 of file X86InstrInfo.cpp.

References llvm::array_lengthof(), and ReplaceableInstrs.

Referenced by llvm::X86InstrInfo::getExecutionDomain(), llvm::Module::getNamedMetadata(), and llvm::X86InstrInfo::setExecutionDomain().

static const uint16_t* lookupAVX2 ( unsigned  opcode,
unsigned  domain 
) [static]

Definition at line 4670 of file X86InstrInfo.cpp.

References llvm::array_lengthof(), and ReplaceableInstrsAVX2.

Referenced by llvm::X86InstrInfo::getExecutionDomain(), and llvm::X86InstrInfo::setExecutionDomain().

static MachineInstr* MakeM0Inst ( const TargetInstrInfo &  TII,
unsigned  Opcode,
const SmallVectorImpl< MachineOperand > &  MOs,
MachineInstr *  MI 
) [static]

Definition at line 3685 of file X86InstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::addOffset(), llvm::MachineInstrBuilder::addOperand(), llvm::BuildMI(), llvm::MCInstrInfo::get(), llvm::MachineInstr::getDebugLoc(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), and llvm::SmallVectorTemplateCommon< T >::size().

Referenced by llvm::X86InstrInfo::foldMemoryOperandImpl().

static bool regIsPICBase ( unsigned  BaseReg,
const MachineRegisterInfo &  MRI 
) [static]

regIsPICBase - Return true if register is PIC base (i.e.g defined by X86::MOVPC32r.

Definition at line 1544 of file X86InstrInfo.cpp.

References llvm::MachineRegisterInfo::def_begin(), llvm::MachineRegisterInfo::def_end(), llvm::MachineInstr::getOpcode(), I, and llvm::TargetRegisterInfo::isVirtualRegister().

Referenced by llvm::X86InstrInfo::isReallyTriviallyReMaterializable().

Variable Documentation

cl::opt<bool> NoFusing("disable-spill-fusing", cl::desc("Disable fusing of spill code into instructions")) [static]

Referenced by llvm::X86InstrInfo::canFoldMemoryOperand(), and llvm::X86InstrInfo::foldMemoryOperandImpl().

cl::opt<bool> PrintFailedFusing("print-failed-fuse-candidates", cl::desc("Print instructions that the allocator wants to"" fuse, but the X86 backend currently can't"), cl::Hidden) [static]

Referenced by llvm::X86InstrInfo::foldMemoryOperandImpl().

cl::opt<bool> ReMatPICStubLoad("remat-pic-stub-load", cl::desc("Re-materialize load from stub in PIC mode"), cl::init(false), cl::Hidden) [static]

Referenced by llvm::X86InstrInfo::isReallyTriviallyReMaterializable().

const uint16_t ReplaceableInstrs[][3] [static]

Definition at line 4602 of file X86InstrInfo.cpp.

Referenced by lookup().

const uint16_t ReplaceableInstrsAVX2[][3] [static]
Initial value:
 {
  
  { X86::VANDNPSYrm,   X86::VANDNPDYrm,   X86::VPANDNYrm   },
  { X86::VANDNPSYrr,   X86::VANDNPDYrr,   X86::VPANDNYrr   },
  { X86::VANDPSYrm,    X86::VANDPDYrm,    X86::VPANDYrm    },
  { X86::VANDPSYrr,    X86::VANDPDYrr,    X86::VPANDYrr    },
  { X86::VORPSYrm,     X86::VORPDYrm,     X86::VPORYrm     },
  { X86::VORPSYrr,     X86::VORPDYrr,     X86::VPORYrr     },
  { X86::VXORPSYrm,    X86::VXORPDYrm,    X86::VPXORYrm    },
  { X86::VXORPSYrr,    X86::VXORPDYrr,    X86::VPXORYrr    },
  { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
  { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
  { X86::VINSERTF128rm,  X86::VINSERTF128rm,  X86::VINSERTI128rm },
  { X86::VINSERTF128rr,  X86::VINSERTF128rr,  X86::VINSERTI128rr },
  { X86::VPERM2F128rm,   X86::VPERM2F128rm,   X86::VPERM2I128rm },
  { X86::VPERM2F128rr,   X86::VPERM2F128rr,   X86::VPERM2I128rr }
}

Definition at line 4642 of file X86InstrInfo.cpp.

Referenced by lookupAVX2().

Generated on Tue May 21 2013 02:46:15 for LLVM by Doxygen1.7.5.1
Copyright © 2003-2013 University of Illinois at Urbana-Champaign. All Rights Reserved.