LLVM API Documentation

X86InstrInfo.cpp
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00001 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file contains the X86 implementation of the TargetInstrInfo class.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #include "X86InstrInfo.h"
00015 #include "X86.h"
00016 #include "X86InstrBuilder.h"
00017 #include "X86MachineFunctionInfo.h"
00018 #include "X86Subtarget.h"
00019 #include "X86TargetMachine.h"
00020 #include "llvm/ADT/STLExtras.h"
00021 #include "llvm/CodeGen/LiveVariables.h"
00022 #include "llvm/CodeGen/MachineConstantPool.h"
00023 #include "llvm/CodeGen/MachineDominators.h"
00024 #include "llvm/CodeGen/MachineFrameInfo.h"
00025 #include "llvm/CodeGen/MachineInstrBuilder.h"
00026 #include "llvm/CodeGen/MachineRegisterInfo.h"
00027 #include "llvm/IR/DerivedTypes.h"
00028 #include "llvm/IR/LLVMContext.h"
00029 #include "llvm/MC/MCAsmInfo.h"
00030 #include "llvm/MC/MCInst.h"
00031 #include "llvm/Support/CommandLine.h"
00032 #include "llvm/Support/Debug.h"
00033 #include "llvm/Support/ErrorHandling.h"
00034 #include "llvm/Support/raw_ostream.h"
00035 #include "llvm/Target/TargetOptions.h"
00036 #include <limits>
00037 
00038 #define GET_INSTRINFO_CTOR
00039 #include "X86GenInstrInfo.inc"
00040 
00041 using namespace llvm;
00042 
00043 static cl::opt<bool>
00044 NoFusing("disable-spill-fusing",
00045          cl::desc("Disable fusing of spill code into instructions"));
00046 static cl::opt<bool>
00047 PrintFailedFusing("print-failed-fuse-candidates",
00048                   cl::desc("Print instructions that the allocator wants to"
00049                            " fuse, but the X86 backend currently can't"),
00050                   cl::Hidden);
00051 static cl::opt<bool>
00052 ReMatPICStubLoad("remat-pic-stub-load",
00053                  cl::desc("Re-materialize load from stub in PIC mode"),
00054                  cl::init(false), cl::Hidden);
00055 
00056 enum {
00057   // Select which memory operand is being unfolded.
00058   // (stored in bits 0 - 3)
00059   TB_INDEX_0    = 0,
00060   TB_INDEX_1    = 1,
00061   TB_INDEX_2    = 2,
00062   TB_INDEX_3    = 3,
00063   TB_INDEX_MASK = 0xf,
00064 
00065   // Do not insert the reverse map (MemOp -> RegOp) into the table.
00066   // This may be needed because there is a many -> one mapping.
00067   TB_NO_REVERSE   = 1 << 4,
00068 
00069   // Do not insert the forward map (RegOp -> MemOp) into the table.
00070   // This is needed for Native Client, which prohibits branch
00071   // instructions from using a memory operand.
00072   TB_NO_FORWARD   = 1 << 5,
00073 
00074   TB_FOLDED_LOAD  = 1 << 6,
00075   TB_FOLDED_STORE = 1 << 7,
00076 
00077   // Minimum alignment required for load/store.
00078   // Used for RegOp->MemOp conversion.
00079   // (stored in bits 8 - 15)
00080   TB_ALIGN_SHIFT = 8,
00081   TB_ALIGN_NONE  =    0 << TB_ALIGN_SHIFT,
00082   TB_ALIGN_16    =   16 << TB_ALIGN_SHIFT,
00083   TB_ALIGN_32    =   32 << TB_ALIGN_SHIFT,
00084   TB_ALIGN_MASK  = 0xff << TB_ALIGN_SHIFT
00085 };
00086 
00087 struct X86OpTblEntry {
00088   uint16_t RegOp;
00089   uint16_t MemOp;
00090   uint16_t Flags;
00091 };
00092 
00093 X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
00094   : X86GenInstrInfo((tm.getSubtarget<X86Subtarget>().is64Bit()
00095                      ? X86::ADJCALLSTACKDOWN64
00096                      : X86::ADJCALLSTACKDOWN32),
00097                     (tm.getSubtarget<X86Subtarget>().is64Bit()
00098                      ? X86::ADJCALLSTACKUP64
00099                      : X86::ADJCALLSTACKUP32)),
00100     TM(tm), RI(tm, *this) {
00101 
00102   static const X86OpTblEntry OpTbl2Addr[] = {
00103     { X86::ADC32ri,     X86::ADC32mi,    0 },
00104     { X86::ADC32ri8,    X86::ADC32mi8,   0 },
00105     { X86::ADC32rr,     X86::ADC32mr,    0 },
00106     { X86::ADC64ri32,   X86::ADC64mi32,  0 },
00107     { X86::ADC64ri8,    X86::ADC64mi8,   0 },
00108     { X86::ADC64rr,     X86::ADC64mr,    0 },
00109     { X86::ADD16ri,     X86::ADD16mi,    0 },
00110     { X86::ADD16ri8,    X86::ADD16mi8,   0 },
00111     { X86::ADD16ri_DB,  X86::ADD16mi,    TB_NO_REVERSE },
00112     { X86::ADD16ri8_DB, X86::ADD16mi8,   TB_NO_REVERSE },
00113     { X86::ADD16rr,     X86::ADD16mr,    0 },
00114     { X86::ADD16rr_DB,  X86::ADD16mr,    TB_NO_REVERSE },
00115     { X86::ADD32ri,     X86::ADD32mi,    0 },
00116     { X86::ADD32ri8,    X86::ADD32mi8,   0 },
00117     { X86::ADD32ri_DB,  X86::ADD32mi,    TB_NO_REVERSE },
00118     { X86::ADD32ri8_DB, X86::ADD32mi8,   TB_NO_REVERSE },
00119     { X86::ADD32rr,     X86::ADD32mr,    0 },
00120     { X86::ADD32rr_DB,  X86::ADD32mr,    TB_NO_REVERSE },
00121     { X86::ADD64ri32,   X86::ADD64mi32,  0 },
00122     { X86::ADD64ri8,    X86::ADD64mi8,   0 },
00123     { X86::ADD64ri32_DB,X86::ADD64mi32,  TB_NO_REVERSE },
00124     { X86::ADD64ri8_DB, X86::ADD64mi8,   TB_NO_REVERSE },
00125     { X86::ADD64rr,     X86::ADD64mr,    0 },
00126     { X86::ADD64rr_DB,  X86::ADD64mr,    TB_NO_REVERSE },
00127     { X86::ADD8ri,      X86::ADD8mi,     0 },
00128     { X86::ADD8rr,      X86::ADD8mr,     0 },
00129     { X86::AND16ri,     X86::AND16mi,    0 },
00130     { X86::AND16ri8,    X86::AND16mi8,   0 },
00131     { X86::AND16rr,     X86::AND16mr,    0 },
00132     { X86::AND32ri,     X86::AND32mi,    0 },
00133     { X86::AND32ri8,    X86::AND32mi8,   0 },
00134     { X86::AND32rr,     X86::AND32mr,    0 },
00135     { X86::AND64ri32,   X86::AND64mi32,  0 },
00136     { X86::AND64ri8,    X86::AND64mi8,   0 },
00137     { X86::AND64rr,     X86::AND64mr,    0 },
00138     { X86::AND8ri,      X86::AND8mi,     0 },
00139     { X86::AND8rr,      X86::AND8mr,     0 },
00140     { X86::DEC16r,      X86::DEC16m,     0 },
00141     { X86::DEC32r,      X86::DEC32m,     0 },
00142     { X86::DEC64_16r,   X86::DEC64_16m,  0 },
00143     { X86::DEC64_32r,   X86::DEC64_32m,  0 },
00144     { X86::DEC64r,      X86::DEC64m,     0 },
00145     { X86::DEC8r,       X86::DEC8m,      0 },
00146     { X86::INC16r,      X86::INC16m,     0 },
00147     { X86::INC32r,      X86::INC32m,     0 },
00148     { X86::INC64_16r,   X86::INC64_16m,  0 },
00149     { X86::INC64_32r,   X86::INC64_32m,  0 },
00150     { X86::INC64r,      X86::INC64m,     0 },
00151     { X86::INC8r,       X86::INC8m,      0 },
00152     { X86::NEG16r,      X86::NEG16m,     0 },
00153     { X86::NEG32r,      X86::NEG32m,     0 },
00154     { X86::NEG64r,      X86::NEG64m,     0 },
00155     { X86::NEG8r,       X86::NEG8m,      0 },
00156     { X86::NOT16r,      X86::NOT16m,     0 },
00157     { X86::NOT32r,      X86::NOT32m,     0 },
00158     { X86::NOT64r,      X86::NOT64m,     0 },
00159     { X86::NOT8r,       X86::NOT8m,      0 },
00160     { X86::OR16ri,      X86::OR16mi,     0 },
00161     { X86::OR16ri8,     X86::OR16mi8,    0 },
00162     { X86::OR16rr,      X86::OR16mr,     0 },
00163     { X86::OR32ri,      X86::OR32mi,     0 },
00164     { X86::OR32ri8,     X86::OR32mi8,    0 },
00165     { X86::OR32rr,      X86::OR32mr,     0 },
00166     { X86::OR64ri32,    X86::OR64mi32,   0 },
00167     { X86::OR64ri8,     X86::OR64mi8,    0 },
00168     { X86::OR64rr,      X86::OR64mr,     0 },
00169     { X86::OR8ri,       X86::OR8mi,      0 },
00170     { X86::OR8rr,       X86::OR8mr,      0 },
00171     { X86::ROL16r1,     X86::ROL16m1,    0 },
00172     { X86::ROL16rCL,    X86::ROL16mCL,   0 },
00173     { X86::ROL16ri,     X86::ROL16mi,    0 },
00174     { X86::ROL32r1,     X86::ROL32m1,    0 },
00175     { X86::ROL32rCL,    X86::ROL32mCL,   0 },
00176     { X86::ROL32ri,     X86::ROL32mi,    0 },
00177     { X86::ROL64r1,     X86::ROL64m1,    0 },
00178     { X86::ROL64rCL,    X86::ROL64mCL,   0 },
00179     { X86::ROL64ri,     X86::ROL64mi,    0 },
00180     { X86::ROL8r1,      X86::ROL8m1,     0 },
00181     { X86::ROL8rCL,     X86::ROL8mCL,    0 },
00182     { X86::ROL8ri,      X86::ROL8mi,     0 },
00183     { X86::ROR16r1,     X86::ROR16m1,    0 },
00184     { X86::ROR16rCL,    X86::ROR16mCL,   0 },
00185     { X86::ROR16ri,     X86::ROR16mi,    0 },
00186     { X86::ROR32r1,     X86::ROR32m1,    0 },
00187     { X86::ROR32rCL,    X86::ROR32mCL,   0 },
00188     { X86::ROR32ri,     X86::ROR32mi,    0 },
00189     { X86::ROR64r1,     X86::ROR64m1,    0 },
00190     { X86::ROR64rCL,    X86::ROR64mCL,   0 },
00191     { X86::ROR64ri,     X86::ROR64mi,    0 },
00192     { X86::ROR8r1,      X86::ROR8m1,     0 },
00193     { X86::ROR8rCL,     X86::ROR8mCL,    0 },
00194     { X86::ROR8ri,      X86::ROR8mi,     0 },
00195     { X86::SAR16r1,     X86::SAR16m1,    0 },
00196     { X86::SAR16rCL,    X86::SAR16mCL,   0 },
00197     { X86::SAR16ri,     X86::SAR16mi,    0 },
00198     { X86::SAR32r1,     X86::SAR32m1,    0 },
00199     { X86::SAR32rCL,    X86::SAR32mCL,   0 },
00200     { X86::SAR32ri,     X86::SAR32mi,    0 },
00201     { X86::SAR64r1,     X86::SAR64m1,    0 },
00202     { X86::SAR64rCL,    X86::SAR64mCL,   0 },
00203     { X86::SAR64ri,     X86::SAR64mi,    0 },
00204     { X86::SAR8r1,      X86::SAR8m1,     0 },
00205     { X86::SAR8rCL,     X86::SAR8mCL,    0 },
00206     { X86::SAR8ri,      X86::SAR8mi,     0 },
00207     { X86::SBB32ri,     X86::SBB32mi,    0 },
00208     { X86::SBB32ri8,    X86::SBB32mi8,   0 },
00209     { X86::SBB32rr,     X86::SBB32mr,    0 },
00210     { X86::SBB64ri32,   X86::SBB64mi32,  0 },
00211     { X86::SBB64ri8,    X86::SBB64mi8,   0 },
00212     { X86::SBB64rr,     X86::SBB64mr,    0 },
00213     { X86::SHL16rCL,    X86::SHL16mCL,   0 },
00214     { X86::SHL16ri,     X86::SHL16mi,    0 },
00215     { X86::SHL32rCL,    X86::SHL32mCL,   0 },
00216     { X86::SHL32ri,     X86::SHL32mi,    0 },
00217     { X86::SHL64rCL,    X86::SHL64mCL,   0 },
00218     { X86::SHL64ri,     X86::SHL64mi,    0 },
00219     { X86::SHL8rCL,     X86::SHL8mCL,    0 },
00220     { X86::SHL8ri,      X86::SHL8mi,     0 },
00221     { X86::SHLD16rrCL,  X86::SHLD16mrCL, 0 },
00222     { X86::SHLD16rri8,  X86::SHLD16mri8, 0 },
00223     { X86::SHLD32rrCL,  X86::SHLD32mrCL, 0 },
00224     { X86::SHLD32rri8,  X86::SHLD32mri8, 0 },
00225     { X86::SHLD64rrCL,  X86::SHLD64mrCL, 0 },
00226     { X86::SHLD64rri8,  X86::SHLD64mri8, 0 },
00227     { X86::SHR16r1,     X86::SHR16m1,    0 },
00228     { X86::SHR16rCL,    X86::SHR16mCL,   0 },
00229     { X86::SHR16ri,     X86::SHR16mi,    0 },
00230     { X86::SHR32r1,     X86::SHR32m1,    0 },
00231     { X86::SHR32rCL,    X86::SHR32mCL,   0 },
00232     { X86::SHR32ri,     X86::SHR32mi,    0 },
00233     { X86::SHR64r1,     X86::SHR64m1,    0 },
00234     { X86::SHR64rCL,    X86::SHR64mCL,   0 },
00235     { X86::SHR64ri,     X86::SHR64mi,    0 },
00236     { X86::SHR8r1,      X86::SHR8m1,     0 },
00237     { X86::SHR8rCL,     X86::SHR8mCL,    0 },
00238     { X86::SHR8ri,      X86::SHR8mi,     0 },
00239     { X86::SHRD16rrCL,  X86::SHRD16mrCL, 0 },
00240     { X86::SHRD16rri8,  X86::SHRD16mri8, 0 },
00241     { X86::SHRD32rrCL,  X86::SHRD32mrCL, 0 },
00242     { X86::SHRD32rri8,  X86::SHRD32mri8, 0 },
00243     { X86::SHRD64rrCL,  X86::SHRD64mrCL, 0 },
00244     { X86::SHRD64rri8,  X86::SHRD64mri8, 0 },
00245     { X86::SUB16ri,     X86::SUB16mi,    0 },
00246     { X86::SUB16ri8,    X86::SUB16mi8,   0 },
00247     { X86::SUB16rr,     X86::SUB16mr,    0 },
00248     { X86::SUB32ri,     X86::SUB32mi,    0 },
00249     { X86::SUB32ri8,    X86::SUB32mi8,   0 },
00250     { X86::SUB32rr,     X86::SUB32mr,    0 },
00251     { X86::SUB64ri32,   X86::SUB64mi32,  0 },
00252     { X86::SUB64ri8,    X86::SUB64mi8,   0 },
00253     { X86::SUB64rr,     X86::SUB64mr,    0 },
00254     { X86::SUB8ri,      X86::SUB8mi,     0 },
00255     { X86::SUB8rr,      X86::SUB8mr,     0 },
00256     { X86::XOR16ri,     X86::XOR16mi,    0 },
00257     { X86::XOR16ri8,    X86::XOR16mi8,   0 },
00258     { X86::XOR16rr,     X86::XOR16mr,    0 },
00259     { X86::XOR32ri,     X86::XOR32mi,    0 },
00260     { X86::XOR32ri8,    X86::XOR32mi8,   0 },
00261     { X86::XOR32rr,     X86::XOR32mr,    0 },
00262     { X86::XOR64ri32,   X86::XOR64mi32,  0 },
00263     { X86::XOR64ri8,    X86::XOR64mi8,   0 },
00264     { X86::XOR64rr,     X86::XOR64mr,    0 },
00265     { X86::XOR8ri,      X86::XOR8mi,     0 },
00266     { X86::XOR8rr,      X86::XOR8mr,     0 }
00267   };
00268 
00269   for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
00270     unsigned RegOp = OpTbl2Addr[i].RegOp;
00271     unsigned MemOp = OpTbl2Addr[i].MemOp;
00272     unsigned Flags = OpTbl2Addr[i].Flags;
00273     AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
00274                   RegOp, MemOp,
00275                   // Index 0, folded load and store, no alignment requirement.
00276                   Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
00277   }
00278 
00279   static const X86OpTblEntry OpTbl0[] = {
00280     { X86::BT16ri8,     X86::BT16mi8,       TB_FOLDED_LOAD },
00281     { X86::BT32ri8,     X86::BT32mi8,       TB_FOLDED_LOAD },
00282     { X86::BT64ri8,     X86::BT64mi8,       TB_FOLDED_LOAD },
00283     { X86::CALL32r,     X86::CALL32m,       TB_FOLDED_LOAD },
00284     { X86::CALL64r,     X86::CALL64m,       TB_FOLDED_LOAD },
00285     { X86::CMP16ri,     X86::CMP16mi,       TB_FOLDED_LOAD },
00286     { X86::CMP16ri8,    X86::CMP16mi8,      TB_FOLDED_LOAD },
00287     { X86::CMP16rr,     X86::CMP16mr,       TB_FOLDED_LOAD },
00288     { X86::CMP32ri,     X86::CMP32mi,       TB_FOLDED_LOAD },
00289     { X86::CMP32ri8,    X86::CMP32mi8,      TB_FOLDED_LOAD },
00290     { X86::CMP32rr,     X86::CMP32mr,       TB_FOLDED_LOAD },
00291     { X86::CMP64ri32,   X86::CMP64mi32,     TB_FOLDED_LOAD },
00292     { X86::CMP64ri8,    X86::CMP64mi8,      TB_FOLDED_LOAD },
00293     { X86::CMP64rr,     X86::CMP64mr,       TB_FOLDED_LOAD },
00294     { X86::CMP8ri,      X86::CMP8mi,        TB_FOLDED_LOAD },
00295     { X86::CMP8rr,      X86::CMP8mr,        TB_FOLDED_LOAD },
00296     { X86::DIV16r,      X86::DIV16m,        TB_FOLDED_LOAD },
00297     { X86::DIV32r,      X86::DIV32m,        TB_FOLDED_LOAD },
00298     { X86::DIV64r,      X86::DIV64m,        TB_FOLDED_LOAD },
00299     { X86::DIV8r,       X86::DIV8m,         TB_FOLDED_LOAD },
00300     { X86::EXTRACTPSrr, X86::EXTRACTPSmr,   TB_FOLDED_STORE },
00301     { X86::FsMOVAPDrr,  X86::MOVSDmr,       TB_FOLDED_STORE | TB_NO_REVERSE },
00302     { X86::FsMOVAPSrr,  X86::MOVSSmr,       TB_FOLDED_STORE | TB_NO_REVERSE },
00303     { X86::IDIV16r,     X86::IDIV16m,       TB_FOLDED_LOAD },
00304     { X86::IDIV32r,     X86::IDIV32m,       TB_FOLDED_LOAD },
00305     { X86::IDIV64r,     X86::IDIV64m,       TB_FOLDED_LOAD },
00306     { X86::IDIV8r,      X86::IDIV8m,        TB_FOLDED_LOAD },
00307     { X86::IMUL16r,     X86::IMUL16m,       TB_FOLDED_LOAD },
00308     { X86::IMUL32r,     X86::IMUL32m,       TB_FOLDED_LOAD },
00309     { X86::IMUL64r,     X86::IMUL64m,       TB_FOLDED_LOAD },
00310     { X86::IMUL8r,      X86::IMUL8m,        TB_FOLDED_LOAD },
00311     { X86::JMP32r,      X86::JMP32m,        TB_FOLDED_LOAD },
00312     { X86::JMP64r,      X86::JMP64m,        TB_FOLDED_LOAD },
00313     { X86::MOV16ri,     X86::MOV16mi,       TB_FOLDED_STORE },
00314     { X86::MOV16rr,     X86::MOV16mr,       TB_FOLDED_STORE },
00315     { X86::MOV32ri,     X86::MOV32mi,       TB_FOLDED_STORE },
00316     { X86::MOV32rr,     X86::MOV32mr,       TB_FOLDED_STORE },
00317     { X86::MOV64ri32,   X86::MOV64mi32,     TB_FOLDED_STORE },
00318     { X86::MOV64rr,     X86::MOV64mr,       TB_FOLDED_STORE },
00319     { X86::MOV8ri,      X86::MOV8mi,        TB_FOLDED_STORE },
00320     { X86::MOV8rr,      X86::MOV8mr,        TB_FOLDED_STORE },
00321     { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
00322     { X86::MOVAPDrr,    X86::MOVAPDmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
00323     { X86::MOVAPSrr,    X86::MOVAPSmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
00324     { X86::MOVDQArr,    X86::MOVDQAmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
00325     { X86::MOVPDI2DIrr, X86::MOVPDI2DImr,   TB_FOLDED_STORE },
00326     { X86::MOVPQIto64rr,X86::MOVPQI2QImr,   TB_FOLDED_STORE },
00327     { X86::MOVSDto64rr, X86::MOVSDto64mr,   TB_FOLDED_STORE },
00328     { X86::MOVSS2DIrr,  X86::MOVSS2DImr,    TB_FOLDED_STORE },
00329     { X86::MOVUPDrr,    X86::MOVUPDmr,      TB_FOLDED_STORE },
00330     { X86::MOVUPSrr,    X86::MOVUPSmr,      TB_FOLDED_STORE },
00331     { X86::MUL16r,      X86::MUL16m,        TB_FOLDED_LOAD },
00332     { X86::MUL32r,      X86::MUL32m,        TB_FOLDED_LOAD },
00333     { X86::MUL64r,      X86::MUL64m,        TB_FOLDED_LOAD },
00334     { X86::MUL8r,       X86::MUL8m,         TB_FOLDED_LOAD },
00335     { X86::SETAEr,      X86::SETAEm,        TB_FOLDED_STORE },
00336     { X86::SETAr,       X86::SETAm,         TB_FOLDED_STORE },
00337     { X86::SETBEr,      X86::SETBEm,        TB_FOLDED_STORE },
00338     { X86::SETBr,       X86::SETBm,         TB_FOLDED_STORE },
00339     { X86::SETEr,       X86::SETEm,         TB_FOLDED_STORE },
00340     { X86::SETGEr,      X86::SETGEm,        TB_FOLDED_STORE },
00341     { X86::SETGr,       X86::SETGm,         TB_FOLDED_STORE },
00342     { X86::SETLEr,      X86::SETLEm,        TB_FOLDED_STORE },
00343     { X86::SETLr,       X86::SETLm,         TB_FOLDED_STORE },
00344     { X86::SETNEr,      X86::SETNEm,        TB_FOLDED_STORE },
00345     { X86::SETNOr,      X86::SETNOm,        TB_FOLDED_STORE },
00346     { X86::SETNPr,      X86::SETNPm,        TB_FOLDED_STORE },
00347     { X86::SETNSr,      X86::SETNSm,        TB_FOLDED_STORE },
00348     { X86::SETOr,       X86::SETOm,         TB_FOLDED_STORE },
00349     { X86::SETPr,       X86::SETPm,         TB_FOLDED_STORE },
00350     { X86::SETSr,       X86::SETSm,         TB_FOLDED_STORE },
00351     { X86::TAILJMPr,    X86::TAILJMPm,      TB_FOLDED_LOAD },
00352     { X86::TAILJMPr64,  X86::TAILJMPm64,    TB_FOLDED_LOAD },
00353     { X86::TEST16ri,    X86::TEST16mi,      TB_FOLDED_LOAD },
00354     { X86::TEST32ri,    X86::TEST32mi,      TB_FOLDED_LOAD },
00355     { X86::TEST64ri32,  X86::TEST64mi32,    TB_FOLDED_LOAD },
00356     { X86::TEST8ri,     X86::TEST8mi,       TB_FOLDED_LOAD },
00357     // AVX 128-bit versions of foldable instructions
00358     { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr,  TB_FOLDED_STORE  },
00359     { X86::FsVMOVAPDrr, X86::VMOVSDmr,      TB_FOLDED_STORE | TB_NO_REVERSE },
00360     { X86::FsVMOVAPSrr, X86::VMOVSSmr,      TB_FOLDED_STORE | TB_NO_REVERSE },
00361     { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
00362     { X86::VMOVAPDrr,   X86::VMOVAPDmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
00363     { X86::VMOVAPSrr,   X86::VMOVAPSmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
00364     { X86::VMOVDQArr,   X86::VMOVDQAmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
00365     { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr,  TB_FOLDED_STORE },
00366     { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
00367     { X86::VMOVSDto64rr,X86::VMOVSDto64mr,  TB_FOLDED_STORE },
00368     { X86::VMOVSS2DIrr, X86::VMOVSS2DImr,   TB_FOLDED_STORE },
00369     { X86::VMOVUPDrr,   X86::VMOVUPDmr,     TB_FOLDED_STORE },
00370     { X86::VMOVUPSrr,   X86::VMOVUPSmr,     TB_FOLDED_STORE },
00371     // AVX 256-bit foldable instructions
00372     { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
00373     { X86::VMOVAPDYrr,  X86::VMOVAPDYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
00374     { X86::VMOVAPSYrr,  X86::VMOVAPSYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
00375     { X86::VMOVDQAYrr,  X86::VMOVDQAYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
00376     { X86::VMOVUPDYrr,  X86::VMOVUPDYmr,    TB_FOLDED_STORE },
00377     { X86::VMOVUPSYrr,  X86::VMOVUPSYmr,    TB_FOLDED_STORE }
00378   };
00379 
00380   for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
00381     unsigned RegOp      = OpTbl0[i].RegOp;
00382     unsigned MemOp      = OpTbl0[i].MemOp;
00383     unsigned Flags      = OpTbl0[i].Flags;
00384     AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
00385                   RegOp, MemOp, TB_INDEX_0 | Flags);
00386   }
00387 
00388   static const X86OpTblEntry OpTbl1[] = {
00389     { X86::CMP16rr,         X86::CMP16rm,             0 },
00390     { X86::CMP32rr,         X86::CMP32rm,             0 },
00391     { X86::CMP64rr,         X86::CMP64rm,             0 },
00392     { X86::CMP8rr,          X86::CMP8rm,              0 },
00393     { X86::CVTSD2SSrr,      X86::CVTSD2SSrm,          0 },
00394     { X86::CVTSI2SD64rr,    X86::CVTSI2SD64rm,        0 },
00395     { X86::CVTSI2SDrr,      X86::CVTSI2SDrm,          0 },
00396     { X86::CVTSI2SS64rr,    X86::CVTSI2SS64rm,        0 },
00397     { X86::CVTSI2SSrr,      X86::CVTSI2SSrm,          0 },
00398     { X86::CVTSS2SDrr,      X86::CVTSS2SDrm,          0 },
00399     { X86::CVTTSD2SI64rr,   X86::CVTTSD2SI64rm,       0 },
00400     { X86::CVTTSD2SIrr,     X86::CVTTSD2SIrm,         0 },
00401     { X86::CVTTSS2SI64rr,   X86::CVTTSS2SI64rm,       0 },
00402     { X86::CVTTSS2SIrr,     X86::CVTTSS2SIrm,         0 },
00403     { X86::FsMOVAPDrr,      X86::MOVSDrm,             TB_NO_REVERSE },
00404     { X86::FsMOVAPSrr,      X86::MOVSSrm,             TB_NO_REVERSE },
00405     { X86::IMUL16rri,       X86::IMUL16rmi,           0 },
00406     { X86::IMUL16rri8,      X86::IMUL16rmi8,          0 },
00407     { X86::IMUL32rri,       X86::IMUL32rmi,           0 },
00408     { X86::IMUL32rri8,      X86::IMUL32rmi8,          0 },
00409     { X86::IMUL64rri32,     X86::IMUL64rmi32,         0 },
00410     { X86::IMUL64rri8,      X86::IMUL64rmi8,          0 },
00411     { X86::Int_COMISDrr,    X86::Int_COMISDrm,        0 },
00412     { X86::Int_COMISSrr,    X86::Int_COMISSrm,        0 },
00413     { X86::CVTSD2SI64rr,    X86::CVTSD2SI64rm,        0 },
00414     { X86::CVTSD2SIrr,      X86::CVTSD2SIrm,          0 },
00415     { X86::CVTSS2SI64rr,    X86::CVTSS2SI64rm,        0 },
00416     { X86::CVTSS2SIrr,      X86::CVTSS2SIrm,          0 },
00417     { X86::CVTTPD2DQrr,     X86::CVTTPD2DQrm,         TB_ALIGN_16 },
00418     { X86::CVTTPS2DQrr,     X86::CVTTPS2DQrm,         TB_ALIGN_16 },
00419     { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm,  0 },
00420     { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm,     0 },
00421     { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm,  0 },
00422     { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm,     0 },
00423     { X86::Int_UCOMISDrr,   X86::Int_UCOMISDrm,       0 },
00424     { X86::Int_UCOMISSrr,   X86::Int_UCOMISSrm,       0 },
00425     { X86::MOV16rr,         X86::MOV16rm,             0 },
00426     { X86::MOV32rr,         X86::MOV32rm,             0 },
00427     { X86::MOV64rr,         X86::MOV64rm,             0 },
00428     { X86::MOV64toPQIrr,    X86::MOVQI2PQIrm,         0 },
00429     { X86::MOV64toSDrr,     X86::MOV64toSDrm,         0 },
00430     { X86::MOV8rr,          X86::MOV8rm,              0 },
00431     { X86::MOVAPDrr,        X86::MOVAPDrm,            TB_ALIGN_16 },
00432     { X86::MOVAPSrr,        X86::MOVAPSrm,            TB_ALIGN_16 },
00433     { X86::MOVDDUPrr,       X86::MOVDDUPrm,           0 },
00434     { X86::MOVDI2PDIrr,     X86::MOVDI2PDIrm,         0 },
00435     { X86::MOVDI2SSrr,      X86::MOVDI2SSrm,          0 },
00436     { X86::MOVDQArr,        X86::MOVDQArm,            TB_ALIGN_16 },
00437     { X86::MOVSHDUPrr,      X86::MOVSHDUPrm,          TB_ALIGN_16 },
00438     { X86::MOVSLDUPrr,      X86::MOVSLDUPrm,          TB_ALIGN_16 },
00439     { X86::MOVSX16rr8,      X86::MOVSX16rm8,          0 },
00440     { X86::MOVSX32rr16,     X86::MOVSX32rm16,         0 },
00441     { X86::MOVSX32rr8,      X86::MOVSX32rm8,          0 },
00442     { X86::MOVSX64rr16,     X86::MOVSX64rm16,         0 },
00443     { X86::MOVSX64rr32,     X86::MOVSX64rm32,         0 },
00444     { X86::MOVSX64rr8,      X86::MOVSX64rm8,          0 },
00445     { X86::MOVUPDrr,        X86::MOVUPDrm,            TB_ALIGN_16 },
00446     { X86::MOVUPSrr,        X86::MOVUPSrm,            0 },
00447     { X86::MOVZDI2PDIrr,    X86::MOVZDI2PDIrm,        0 },
00448     { X86::MOVZQI2PQIrr,    X86::MOVZQI2PQIrm,        0 },
00449     { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm,     TB_ALIGN_16 },
00450     { X86::MOVZX16rr8,      X86::MOVZX16rm8,          0 },
00451     { X86::MOVZX32rr16,     X86::MOVZX32rm16,         0 },
00452     { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8,   0 },
00453     { X86::MOVZX32rr8,      X86::MOVZX32rm8,          0 },
00454     { X86::MOVZX64rr16,     X86::MOVZX64rm16,         0 },
00455     { X86::MOVZX64rr32,     X86::MOVZX64rm32,         0 },
00456     { X86::MOVZX64rr8,      X86::MOVZX64rm8,          0 },
00457     { X86::PABSBrr128,      X86::PABSBrm128,          TB_ALIGN_16 },
00458     { X86::PABSDrr128,      X86::PABSDrm128,          TB_ALIGN_16 },
00459     { X86::PABSWrr128,      X86::PABSWrm128,          TB_ALIGN_16 },
00460     { X86::PSHUFDri,        X86::PSHUFDmi,            TB_ALIGN_16 },
00461     { X86::PSHUFHWri,       X86::PSHUFHWmi,           TB_ALIGN_16 },
00462     { X86::PSHUFLWri,       X86::PSHUFLWmi,           TB_ALIGN_16 },
00463     { X86::RCPPSr,          X86::RCPPSm,              TB_ALIGN_16 },
00464     { X86::RCPPSr_Int,      X86::RCPPSm_Int,          TB_ALIGN_16 },
00465     { X86::RSQRTPSr,        X86::RSQRTPSm,            TB_ALIGN_16 },
00466     { X86::RSQRTPSr_Int,    X86::RSQRTPSm_Int,        TB_ALIGN_16 },
00467     { X86::RSQRTSSr,        X86::RSQRTSSm,            0 },
00468     { X86::RSQRTSSr_Int,    X86::RSQRTSSm_Int,        0 },
00469     { X86::SQRTPDr,         X86::SQRTPDm,             TB_ALIGN_16 },
00470     { X86::SQRTPSr,         X86::SQRTPSm,             TB_ALIGN_16 },
00471     { X86::SQRTSDr,         X86::SQRTSDm,             0 },
00472     { X86::SQRTSDr_Int,     X86::SQRTSDm_Int,         0 },
00473     { X86::SQRTSSr,         X86::SQRTSSm,             0 },
00474     { X86::SQRTSSr_Int,     X86::SQRTSSm_Int,         0 },
00475     { X86::TEST16rr,        X86::TEST16rm,            0 },
00476     { X86::TEST32rr,        X86::TEST32rm,            0 },
00477     { X86::TEST64rr,        X86::TEST64rm,            0 },
00478     { X86::TEST8rr,         X86::TEST8rm,             0 },
00479     // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
00480     { X86::UCOMISDrr,       X86::UCOMISDrm,           0 },
00481     { X86::UCOMISSrr,       X86::UCOMISSrm,           0 },
00482     // AVX 128-bit versions of foldable instructions
00483     { X86::Int_VCOMISDrr,   X86::Int_VCOMISDrm,       0 },
00484     { X86::Int_VCOMISSrr,   X86::Int_VCOMISSrm,       0 },
00485     { X86::Int_VUCOMISDrr,  X86::Int_VUCOMISDrm,      0 },
00486     { X86::Int_VUCOMISSrr,  X86::Int_VUCOMISSrm,      0 },
00487     { X86::VCVTTSD2SI64rr,  X86::VCVTTSD2SI64rm,      0 },
00488     { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,0 },
00489     { X86::VCVTTSD2SIrr,    X86::VCVTTSD2SIrm,        0 },
00490     { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm,    0 },
00491     { X86::VCVTTSS2SI64rr,  X86::VCVTTSS2SI64rm,      0 },
00492     { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,0 },
00493     { X86::VCVTTSS2SIrr,    X86::VCVTTSS2SIrm,        0 },
00494     { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm,    0 },
00495     { X86::VCVTSD2SI64rr,   X86::VCVTSD2SI64rm,       0 },
00496     { X86::VCVTSD2SIrr,     X86::VCVTSD2SIrm,         0 },
00497     { X86::VCVTSS2SI64rr,   X86::VCVTSS2SI64rm,       0 },
00498     { X86::VCVTSS2SIrr,     X86::VCVTSS2SIrm,         0 },
00499     { X86::FsVMOVAPDrr,     X86::VMOVSDrm,            TB_NO_REVERSE },
00500     { X86::FsVMOVAPSrr,     X86::VMOVSSrm,            TB_NO_REVERSE },
00501     { X86::VMOV64toPQIrr,   X86::VMOVQI2PQIrm,        0 },
00502     { X86::VMOV64toSDrr,    X86::VMOV64toSDrm,        0 },
00503     { X86::VMOVAPDrr,       X86::VMOVAPDrm,           TB_ALIGN_16 },
00504     { X86::VMOVAPSrr,       X86::VMOVAPSrm,           TB_ALIGN_16 },
00505     { X86::VMOVDDUPrr,      X86::VMOVDDUPrm,          0 },
00506     { X86::VMOVDI2PDIrr,    X86::VMOVDI2PDIrm,        0 },
00507     { X86::VMOVDI2SSrr,     X86::VMOVDI2SSrm,         0 },
00508     { X86::VMOVDQArr,       X86::VMOVDQArm,           TB_ALIGN_16 },
00509     { X86::VMOVSLDUPrr,     X86::VMOVSLDUPrm,         TB_ALIGN_16 },
00510     { X86::VMOVSHDUPrr,     X86::VMOVSHDUPrm,         TB_ALIGN_16 },
00511     { X86::VMOVUPDrr,       X86::VMOVUPDrm,           0 },
00512     { X86::VMOVUPSrr,       X86::VMOVUPSrm,           0 },
00513     { X86::VMOVZDI2PDIrr,   X86::VMOVZDI2PDIrm,       0 },
00514     { X86::VMOVZQI2PQIrr,   X86::VMOVZQI2PQIrm,       0 },
00515     { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm,    TB_ALIGN_16 },
00516     { X86::VPABSBrr128,     X86::VPABSBrm128,         0 },
00517     { X86::VPABSDrr128,     X86::VPABSDrm128,         0 },
00518     { X86::VPABSWrr128,     X86::VPABSWrm128,         0 },
00519     { X86::VPERMILPDri,     X86::VPERMILPDmi,         0 },
00520     { X86::VPERMILPSri,     X86::VPERMILPSmi,         0 },
00521     { X86::VPSHUFDri,       X86::VPSHUFDmi,           0 },
00522     { X86::VPSHUFHWri,      X86::VPSHUFHWmi,          0 },
00523     { X86::VPSHUFLWri,      X86::VPSHUFLWmi,          0 },
00524     { X86::VRCPPSr,         X86::VRCPPSm,             0 },
00525     { X86::VRCPPSr_Int,     X86::VRCPPSm_Int,         0 },
00526     { X86::VRSQRTPSr,       X86::VRSQRTPSm,           0 },
00527     { X86::VRSQRTPSr_Int,   X86::VRSQRTPSm_Int,       0 },
00528     { X86::VSQRTPDr,        X86::VSQRTPDm,            0 },
00529     { X86::VSQRTPSr,        X86::VSQRTPSm,            0 },
00530     { X86::VUCOMISDrr,      X86::VUCOMISDrm,          0 },
00531     { X86::VUCOMISSrr,      X86::VUCOMISSrm,          0 },
00532     { X86::VBROADCASTSSrr,  X86::VBROADCASTSSrm,      TB_NO_REVERSE },
00533 
00534     // AVX 256-bit foldable instructions
00535     { X86::VMOVAPDYrr,      X86::VMOVAPDYrm,          TB_ALIGN_32 },
00536     { X86::VMOVAPSYrr,      X86::VMOVAPSYrm,          TB_ALIGN_32 },
00537     { X86::VMOVDQAYrr,      X86::VMOVDQAYrm,          TB_ALIGN_32 },
00538     { X86::VMOVUPDYrr,      X86::VMOVUPDYrm,          0 },
00539     { X86::VMOVUPSYrr,      X86::VMOVUPSYrm,          0 },
00540     { X86::VPERMILPDYri,    X86::VPERMILPDYmi,        0 },
00541     { X86::VPERMILPSYri,    X86::VPERMILPSYmi,        0 },
00542 
00543     // AVX2 foldable instructions
00544     { X86::VPABSBrr256,     X86::VPABSBrm256,         0 },
00545     { X86::VPABSDrr256,     X86::VPABSDrm256,         0 },
00546     { X86::VPABSWrr256,     X86::VPABSWrm256,         0 },
00547     { X86::VPSHUFDYri,      X86::VPSHUFDYmi,          0 },
00548     { X86::VPSHUFHWYri,     X86::VPSHUFHWYmi,         0 },
00549     { X86::VPSHUFLWYri,     X86::VPSHUFLWYmi,         0 },
00550     { X86::VRCPPSYr,        X86::VRCPPSYm,            0 },
00551     { X86::VRCPPSYr_Int,    X86::VRCPPSYm_Int,        0 },
00552     { X86::VRSQRTPSYr,      X86::VRSQRTPSYm,          0 },
00553     { X86::VSQRTPDYr,       X86::VSQRTPDYm,           0 },
00554     { X86::VSQRTPSYr,       X86::VSQRTPSYm,           0 },
00555     { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm,     TB_NO_REVERSE },
00556     { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm,     TB_NO_REVERSE },
00557 
00558     // BMI/BMI2/LZCNT/POPCNT foldable instructions
00559     { X86::BEXTR32rr,       X86::BEXTR32rm,           0 },
00560     { X86::BEXTR64rr,       X86::BEXTR64rm,           0 },
00561     { X86::BLSI32rr,        X86::BLSI32rm,            0 },
00562     { X86::BLSI64rr,        X86::BLSI64rm,            0 },
00563     { X86::BLSMSK32rr,      X86::BLSMSK32rm,          0 },
00564     { X86::BLSMSK64rr,      X86::BLSMSK64rm,          0 },
00565     { X86::BLSR32rr,        X86::BLSR32rm,            0 },
00566     { X86::BLSR64rr,        X86::BLSR64rm,            0 },
00567     { X86::BZHI32rr,        X86::BZHI32rm,            0 },
00568     { X86::BZHI64rr,        X86::BZHI64rm,            0 },
00569     { X86::LZCNT16rr,       X86::LZCNT16rm,           0 },
00570     { X86::LZCNT32rr,       X86::LZCNT32rm,           0 },
00571     { X86::LZCNT64rr,       X86::LZCNT64rm,           0 },
00572     { X86::POPCNT16rr,      X86::POPCNT16rm,          0 },
00573     { X86::POPCNT32rr,      X86::POPCNT32rm,          0 },
00574     { X86::POPCNT64rr,      X86::POPCNT64rm,          0 },
00575     { X86::RORX32ri,        X86::RORX32mi,            0 },
00576     { X86::RORX64ri,        X86::RORX64mi,            0 },
00577     { X86::SARX32rr,        X86::SARX32rm,            0 },
00578     { X86::SARX64rr,        X86::SARX64rm,            0 },
00579     { X86::SHRX32rr,        X86::SHRX32rm,            0 },
00580     { X86::SHRX64rr,        X86::SHRX64rm,            0 },
00581     { X86::SHLX32rr,        X86::SHLX32rm,            0 },
00582     { X86::SHLX64rr,        X86::SHLX64rm,            0 },
00583     { X86::TZCNT16rr,       X86::TZCNT16rm,           0 },
00584     { X86::TZCNT32rr,       X86::TZCNT32rm,           0 },
00585     { X86::TZCNT64rr,       X86::TZCNT64rm,           0 },
00586   };
00587 
00588   for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
00589     unsigned RegOp = OpTbl1[i].RegOp;
00590     unsigned MemOp = OpTbl1[i].MemOp;
00591     unsigned Flags = OpTbl1[i].Flags;
00592     AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
00593                   RegOp, MemOp,
00594                   // Index 1, folded load
00595                   Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
00596   }
00597 
00598   static const X86OpTblEntry OpTbl2[] = {
00599     { X86::ADC32rr,         X86::ADC32rm,       0 },
00600     { X86::ADC64rr,         X86::ADC64rm,       0 },
00601     { X86::ADD16rr,         X86::ADD16rm,       0 },
00602     { X86::ADD16rr_DB,      X86::ADD16rm,       TB_NO_REVERSE },
00603     { X86::ADD32rr,         X86::ADD32rm,       0 },
00604     { X86::ADD32rr_DB,      X86::ADD32rm,       TB_NO_REVERSE },
00605     { X86::ADD64rr,         X86::ADD64rm,       0 },
00606     { X86::ADD64rr_DB,      X86::ADD64rm,       TB_NO_REVERSE },
00607     { X86::ADD8rr,          X86::ADD8rm,        0 },
00608     { X86::ADDPDrr,         X86::ADDPDrm,       TB_ALIGN_16 },
00609     { X86::ADDPSrr,         X86::ADDPSrm,       TB_ALIGN_16 },
00610     { X86::ADDSDrr,         X86::ADDSDrm,       0 },
00611     { X86::ADDSSrr,         X86::ADDSSrm,       0 },
00612     { X86::ADDSUBPDrr,      X86::ADDSUBPDrm,    TB_ALIGN_16 },
00613     { X86::ADDSUBPSrr,      X86::ADDSUBPSrm,    TB_ALIGN_16 },
00614     { X86::AND16rr,         X86::AND16rm,       0 },
00615     { X86::AND32rr,         X86::AND32rm,       0 },
00616     { X86::AND64rr,         X86::AND64rm,       0 },
00617     { X86::AND8rr,          X86::AND8rm,        0 },
00618     { X86::ANDNPDrr,        X86::ANDNPDrm,      TB_ALIGN_16 },
00619     { X86::ANDNPSrr,        X86::ANDNPSrm,      TB_ALIGN_16 },
00620     { X86::ANDPDrr,         X86::ANDPDrm,       TB_ALIGN_16 },
00621     { X86::ANDPSrr,         X86::ANDPSrm,       TB_ALIGN_16 },
00622     { X86::BLENDPDrri,      X86::BLENDPDrmi,    TB_ALIGN_16 },
00623     { X86::BLENDPSrri,      X86::BLENDPSrmi,    TB_ALIGN_16 },
00624     { X86::BLENDVPDrr0,     X86::BLENDVPDrm0,   TB_ALIGN_16 },
00625     { X86::BLENDVPSrr0,     X86::BLENDVPSrm0,   TB_ALIGN_16 },
00626     { X86::CMOVA16rr,       X86::CMOVA16rm,     0 },
00627     { X86::CMOVA32rr,       X86::CMOVA32rm,     0 },
00628     { X86::CMOVA64rr,       X86::CMOVA64rm,     0 },
00629     { X86::CMOVAE16rr,      X86::CMOVAE16rm,    0 },
00630     { X86::CMOVAE32rr,      X86::CMOVAE32rm,    0 },
00631     { X86::CMOVAE64rr,      X86::CMOVAE64rm,    0 },
00632     { X86::CMOVB16rr,       X86::CMOVB16rm,     0 },
00633     { X86::CMOVB32rr,       X86::CMOVB32rm,     0 },
00634     { X86::CMOVB64rr,       X86::CMOVB64rm,     0 },
00635     { X86::CMOVBE16rr,      X86::CMOVBE16rm,    0 },
00636     { X86::CMOVBE32rr,      X86::CMOVBE32rm,    0 },
00637     { X86::CMOVBE64rr,      X86::CMOVBE64rm,    0 },
00638     { X86::CMOVE16rr,       X86::CMOVE16rm,     0 },
00639     { X86::CMOVE32rr,       X86::CMOVE32rm,     0 },
00640     { X86::CMOVE64rr,       X86::CMOVE64rm,     0 },
00641     { X86::CMOVG16rr,       X86::CMOVG16rm,     0 },
00642     { X86::CMOVG32rr,       X86::CMOVG32rm,     0 },
00643     { X86::CMOVG64rr,       X86::CMOVG64rm,     0 },
00644     { X86::CMOVGE16rr,      X86::CMOVGE16rm,    0 },
00645     { X86::CMOVGE32rr,      X86::CMOVGE32rm,    0 },
00646     { X86::CMOVGE64rr,      X86::CMOVGE64rm,    0 },
00647     { X86::CMOVL16rr,       X86::CMOVL16rm,     0 },
00648     { X86::CMOVL32rr,       X86::CMOVL32rm,     0 },
00649     { X86::CMOVL64rr,       X86::CMOVL64rm,     0 },
00650     { X86::CMOVLE16rr,      X86::CMOVLE16rm,    0 },
00651     { X86::CMOVLE32rr,      X86::CMOVLE32rm,    0 },
00652     { X86::CMOVLE64rr,      X86::CMOVLE64rm,    0 },
00653     { X86::CMOVNE16rr,      X86::CMOVNE16rm,    0 },
00654     { X86::CMOVNE32rr,      X86::CMOVNE32rm,    0 },
00655     { X86::CMOVNE64rr,      X86::CMOVNE64rm,    0 },
00656     { X86::CMOVNO16rr,      X86::CMOVNO16rm,    0 },
00657     { X86::CMOVNO32rr,      X86::CMOVNO32rm,    0 },
00658     { X86::CMOVNO64rr,      X86::CMOVNO64rm,    0 },
00659     { X86::CMOVNP16rr,      X86::CMOVNP16rm,    0 },
00660     { X86::CMOVNP32rr,      X86::CMOVNP32rm,    0 },
00661     { X86::CMOVNP64rr,      X86::CMOVNP64rm,    0 },
00662     { X86::CMOVNS16rr,      X86::CMOVNS16rm,    0 },
00663     { X86::CMOVNS32rr,      X86::CMOVNS32rm,    0 },
00664     { X86::CMOVNS64rr,      X86::CMOVNS64rm,    0 },
00665     { X86::CMOVO16rr,       X86::CMOVO16rm,     0 },
00666     { X86::CMOVO32rr,       X86::CMOVO32rm,     0 },
00667     { X86::CMOVO64rr,       X86::CMOVO64rm,     0 },
00668     { X86::CMOVP16rr,       X86::CMOVP16rm,     0 },
00669     { X86::CMOVP32rr,       X86::CMOVP32rm,     0 },
00670     { X86::CMOVP64rr,       X86::CMOVP64rm,     0 },
00671     { X86::CMOVS16rr,       X86::CMOVS16rm,     0 },
00672     { X86::CMOVS32rr,       X86::CMOVS32rm,     0 },
00673     { X86::CMOVS64rr,       X86::CMOVS64rm,     0 },
00674     { X86::CMPPDrri,        X86::CMPPDrmi,      TB_ALIGN_16 },
00675     { X86::CMPPSrri,        X86::CMPPSrmi,      TB_ALIGN_16 },
00676     { X86::CMPSDrr,         X86::CMPSDrm,       0 },
00677     { X86::CMPSSrr,         X86::CMPSSrm,       0 },
00678     { X86::DIVPDrr,         X86::DIVPDrm,       TB_ALIGN_16 },
00679     { X86::DIVPSrr,         X86::DIVPSrm,       TB_ALIGN_16 },
00680     { X86::DIVSDrr,         X86::DIVSDrm,       0 },
00681     { X86::DIVSSrr,         X86::DIVSSrm,       0 },
00682     { X86::FsANDNPDrr,      X86::FsANDNPDrm,    TB_ALIGN_16 },
00683     { X86::FsANDNPSrr,      X86::FsANDNPSrm,    TB_ALIGN_16 },
00684     { X86::FsANDPDrr,       X86::FsANDPDrm,     TB_ALIGN_16 },
00685     { X86::FsANDPSrr,       X86::FsANDPSrm,     TB_ALIGN_16 },
00686     { X86::FsORPDrr,        X86::FsORPDrm,      TB_ALIGN_16 },
00687     { X86::FsORPSrr,        X86::FsORPSrm,      TB_ALIGN_16 },
00688     { X86::FsXORPDrr,       X86::FsXORPDrm,     TB_ALIGN_16 },
00689     { X86::FsXORPSrr,       X86::FsXORPSrm,     TB_ALIGN_16 },
00690     { X86::HADDPDrr,        X86::HADDPDrm,      TB_ALIGN_16 },
00691     { X86::HADDPSrr,        X86::HADDPSrm,      TB_ALIGN_16 },
00692     { X86::HSUBPDrr,        X86::HSUBPDrm,      TB_ALIGN_16 },
00693     { X86::HSUBPSrr,        X86::HSUBPSrm,      TB_ALIGN_16 },
00694     { X86::IMUL16rr,        X86::IMUL16rm,      0 },
00695     { X86::IMUL32rr,        X86::IMUL32rm,      0 },
00696     { X86::IMUL64rr,        X86::IMUL64rm,      0 },
00697     { X86::Int_CMPSDrr,     X86::Int_CMPSDrm,   0 },
00698     { X86::Int_CMPSSrr,     X86::Int_CMPSSrm,   0 },
00699     { X86::Int_CVTSD2SSrr,  X86::Int_CVTSD2SSrm,      0 },
00700     { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm,    0 },
00701     { X86::Int_CVTSI2SDrr,  X86::Int_CVTSI2SDrm,      0 },
00702     { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm,    0 },
00703     { X86::Int_CVTSI2SSrr,  X86::Int_CVTSI2SSrm,      0 },
00704     { X86::Int_CVTSS2SDrr,  X86::Int_CVTSS2SDrm,      0 },
00705     { X86::MAXPDrr,         X86::MAXPDrm,       TB_ALIGN_16 },
00706     { X86::MAXPSrr,         X86::MAXPSrm,       TB_ALIGN_16 },
00707     { X86::MAXSDrr,         X86::MAXSDrm,       0 },
00708     { X86::MAXSSrr,         X86::MAXSSrm,       0 },
00709     { X86::MINPDrr,         X86::MINPDrm,       TB_ALIGN_16 },
00710     { X86::MINPSrr,         X86::MINPSrm,       TB_ALIGN_16 },
00711     { X86::MINSDrr,         X86::MINSDrm,       0 },
00712     { X86::MINSSrr,         X86::MINSSrm,       0 },
00713     { X86::MPSADBWrri,      X86::MPSADBWrmi,    TB_ALIGN_16 },
00714     { X86::MULPDrr,         X86::MULPDrm,       TB_ALIGN_16 },
00715     { X86::MULPSrr,         X86::MULPSrm,       TB_ALIGN_16 },
00716     { X86::MULSDrr,         X86::MULSDrm,       0 },
00717     { X86::MULSSrr,         X86::MULSSrm,       0 },
00718     { X86::OR16rr,          X86::OR16rm,        0 },
00719     { X86::OR32rr,          X86::OR32rm,        0 },
00720     { X86::OR64rr,          X86::OR64rm,        0 },
00721     { X86::OR8rr,           X86::OR8rm,         0 },
00722     { X86::ORPDrr,          X86::ORPDrm,        TB_ALIGN_16 },
00723     { X86::ORPSrr,          X86::ORPSrm,        TB_ALIGN_16 },
00724     { X86::PACKSSDWrr,      X86::PACKSSDWrm,    TB_ALIGN_16 },
00725     { X86::PACKSSWBrr,      X86::PACKSSWBrm,    TB_ALIGN_16 },
00726     { X86::PACKUSDWrr,      X86::PACKUSDWrm,    TB_ALIGN_16 },
00727     { X86::PACKUSWBrr,      X86::PACKUSWBrm,    TB_ALIGN_16 },
00728     { X86::PADDBrr,         X86::PADDBrm,       TB_ALIGN_16 },
00729     { X86::PADDDrr,         X86::PADDDrm,       TB_ALIGN_16 },
00730     { X86::PADDQrr,         X86::PADDQrm,       TB_ALIGN_16 },
00731     { X86::PADDSBrr,        X86::PADDSBrm,      TB_ALIGN_16 },
00732     { X86::PADDSWrr,        X86::PADDSWrm,      TB_ALIGN_16 },
00733     { X86::PADDUSBrr,       X86::PADDUSBrm,     TB_ALIGN_16 },
00734     { X86::PADDUSWrr,       X86::PADDUSWrm,     TB_ALIGN_16 },
00735     { X86::PADDWrr,         X86::PADDWrm,       TB_ALIGN_16 },
00736     { X86::PALIGNR128rr,    X86::PALIGNR128rm,  TB_ALIGN_16 },
00737     { X86::PANDNrr,         X86::PANDNrm,       TB_ALIGN_16 },
00738     { X86::PANDrr,          X86::PANDrm,        TB_ALIGN_16 },
00739     { X86::PAVGBrr,         X86::PAVGBrm,       TB_ALIGN_16 },
00740     { X86::PAVGWrr,         X86::PAVGWrm,       TB_ALIGN_16 },
00741     { X86::PBLENDWrri,      X86::PBLENDWrmi,    TB_ALIGN_16 },
00742     { X86::PCMPEQBrr,       X86::PCMPEQBrm,     TB_ALIGN_16 },
00743     { X86::PCMPEQDrr,       X86::PCMPEQDrm,     TB_ALIGN_16 },
00744     { X86::PCMPEQQrr,       X86::PCMPEQQrm,     TB_ALIGN_16 },
00745     { X86::PCMPEQWrr,       X86::PCMPEQWrm,     TB_ALIGN_16 },
00746     { X86::PCMPGTBrr,       X86::PCMPGTBrm,     TB_ALIGN_16 },
00747     { X86::PCMPGTDrr,       X86::PCMPGTDrm,     TB_ALIGN_16 },
00748     { X86::PCMPGTQrr,       X86::PCMPGTQrm,     TB_ALIGN_16 },
00749     { X86::PCMPGTWrr,       X86::PCMPGTWrm,     TB_ALIGN_16 },
00750     { X86::PHADDDrr,        X86::PHADDDrm,      TB_ALIGN_16 },
00751     { X86::PHADDWrr,        X86::PHADDWrm,      TB_ALIGN_16 },
00752     { X86::PHADDSWrr128,    X86::PHADDSWrm128,  TB_ALIGN_16 },
00753     { X86::PHSUBDrr,        X86::PHSUBDrm,      TB_ALIGN_16 },
00754     { X86::PHSUBSWrr128,    X86::PHSUBSWrm128,  TB_ALIGN_16 },
00755     { X86::PHSUBWrr,        X86::PHSUBWrm,      TB_ALIGN_16 },
00756     { X86::PINSRWrri,       X86::PINSRWrmi,     TB_ALIGN_16 },
00757     { X86::PMADDUBSWrr128,  X86::PMADDUBSWrm128, TB_ALIGN_16 },
00758     { X86::PMADDWDrr,       X86::PMADDWDrm,     TB_ALIGN_16 },
00759     { X86::PMAXSWrr,        X86::PMAXSWrm,      TB_ALIGN_16 },
00760     { X86::PMAXUBrr,        X86::PMAXUBrm,      TB_ALIGN_16 },
00761     { X86::PMINSWrr,        X86::PMINSWrm,      TB_ALIGN_16 },
00762     { X86::PMINUBrr,        X86::PMINUBrm,      TB_ALIGN_16 },
00763     { X86::PMINSBrr,        X86::PMINSBrm,      TB_ALIGN_16 },
00764     { X86::PMINSDrr,        X86::PMINSDrm,      TB_ALIGN_16 },
00765     { X86::PMINUDrr,        X86::PMINUDrm,      TB_ALIGN_16 },
00766     { X86::PMINUWrr,        X86::PMINUWrm,      TB_ALIGN_16 },
00767     { X86::PMAXSBrr,        X86::PMAXSBrm,      TB_ALIGN_16 },
00768     { X86::PMAXSDrr,        X86::PMAXSDrm,      TB_ALIGN_16 },
00769     { X86::PMAXUDrr,        X86::PMAXUDrm,      TB_ALIGN_16 },
00770     { X86::PMAXUWrr,        X86::PMAXUWrm,      TB_ALIGN_16 },
00771     { X86::PMULDQrr,        X86::PMULDQrm,      TB_ALIGN_16 },
00772     { X86::PMULHRSWrr128,   X86::PMULHRSWrm128, TB_ALIGN_16 },
00773     { X86::PMULHUWrr,       X86::PMULHUWrm,     TB_ALIGN_16 },
00774     { X86::PMULHWrr,        X86::PMULHWrm,      TB_ALIGN_16 },
00775     { X86::PMULLDrr,        X86::PMULLDrm,      TB_ALIGN_16 },
00776     { X86::PMULLWrr,        X86::PMULLWrm,      TB_ALIGN_16 },
00777     { X86::PMULUDQrr,       X86::PMULUDQrm,     TB_ALIGN_16 },
00778     { X86::PORrr,           X86::PORrm,         TB_ALIGN_16 },
00779     { X86::PSADBWrr,        X86::PSADBWrm,      TB_ALIGN_16 },
00780     { X86::PSHUFBrr,        X86::PSHUFBrm,      TB_ALIGN_16 },
00781     { X86::PSIGNBrr,        X86::PSIGNBrm,      TB_ALIGN_16 },
00782     { X86::PSIGNWrr,        X86::PSIGNWrm,      TB_ALIGN_16 },
00783     { X86::PSIGNDrr,        X86::PSIGNDrm,      TB_ALIGN_16 },
00784     { X86::PSLLDrr,         X86::PSLLDrm,       TB_ALIGN_16 },
00785     { X86::PSLLQrr,         X86::PSLLQrm,       TB_ALIGN_16 },
00786     { X86::PSLLWrr,         X86::PSLLWrm,       TB_ALIGN_16 },
00787     { X86::PSRADrr,         X86::PSRADrm,       TB_ALIGN_16 },
00788     { X86::PSRAWrr,         X86::PSRAWrm,       TB_ALIGN_16 },
00789     { X86::PSRLDrr,         X86::PSRLDrm,       TB_ALIGN_16 },
00790     { X86::PSRLQrr,         X86::PSRLQrm,       TB_ALIGN_16 },
00791     { X86::PSRLWrr,         X86::PSRLWrm,       TB_ALIGN_16 },
00792     { X86::PSUBBrr,         X86::PSUBBrm,       TB_ALIGN_16 },
00793     { X86::PSUBDrr,         X86::PSUBDrm,       TB_ALIGN_16 },
00794     { X86::PSUBSBrr,        X86::PSUBSBrm,      TB_ALIGN_16 },
00795     { X86::PSUBSWrr,        X86::PSUBSWrm,      TB_ALIGN_16 },
00796     { X86::PSUBWrr,         X86::PSUBWrm,       TB_ALIGN_16 },
00797     { X86::PUNPCKHBWrr,     X86::PUNPCKHBWrm,   TB_ALIGN_16 },
00798     { X86::PUNPCKHDQrr,     X86::PUNPCKHDQrm,   TB_ALIGN_16 },
00799     { X86::PUNPCKHQDQrr,    X86::PUNPCKHQDQrm,  TB_ALIGN_16 },
00800     { X86::PUNPCKHWDrr,     X86::PUNPCKHWDrm,   TB_ALIGN_16 },
00801     { X86::PUNPCKLBWrr,     X86::PUNPCKLBWrm,   TB_ALIGN_16 },
00802     { X86::PUNPCKLDQrr,     X86::PUNPCKLDQrm,   TB_ALIGN_16 },
00803     { X86::PUNPCKLQDQrr,    X86::PUNPCKLQDQrm,  TB_ALIGN_16 },
00804     { X86::PUNPCKLWDrr,     X86::PUNPCKLWDrm,   TB_ALIGN_16 },
00805     { X86::PXORrr,          X86::PXORrm,        TB_ALIGN_16 },
00806     { X86::SBB32rr,         X86::SBB32rm,       0 },
00807     { X86::SBB64rr,         X86::SBB64rm,       0 },
00808     { X86::SHUFPDrri,       X86::SHUFPDrmi,     TB_ALIGN_16 },
00809     { X86::SHUFPSrri,       X86::SHUFPSrmi,     TB_ALIGN_16 },
00810     { X86::SUB16rr,         X86::SUB16rm,       0 },
00811     { X86::SUB32rr,         X86::SUB32rm,       0 },
00812     { X86::SUB64rr,         X86::SUB64rm,       0 },
00813     { X86::SUB8rr,          X86::SUB8rm,        0 },
00814     { X86::SUBPDrr,         X86::SUBPDrm,       TB_ALIGN_16 },
00815     { X86::SUBPSrr,         X86::SUBPSrm,       TB_ALIGN_16 },
00816     { X86::SUBSDrr,         X86::SUBSDrm,       0 },
00817     { X86::SUBSSrr,         X86::SUBSSrm,       0 },
00818     // FIXME: TEST*rr -> swapped operand of TEST*mr.
00819     { X86::UNPCKHPDrr,      X86::UNPCKHPDrm,    TB_ALIGN_16 },
00820     { X86::UNPCKHPSrr,      X86::UNPCKHPSrm,    TB_ALIGN_16 },
00821     { X86::UNPCKLPDrr,      X86::UNPCKLPDrm,    TB_ALIGN_16 },
00822     { X86::UNPCKLPSrr,      X86::UNPCKLPSrm,    TB_ALIGN_16 },
00823     { X86::XOR16rr,         X86::XOR16rm,       0 },
00824     { X86::XOR32rr,         X86::XOR32rm,       0 },
00825     { X86::XOR64rr,         X86::XOR64rm,       0 },
00826     { X86::XOR8rr,          X86::XOR8rm,        0 },
00827     { X86::XORPDrr,         X86::XORPDrm,       TB_ALIGN_16 },
00828     { X86::XORPSrr,         X86::XORPSrm,       TB_ALIGN_16 },
00829     // AVX 128-bit versions of foldable instructions
00830     { X86::VCVTSD2SSrr,       X86::VCVTSD2SSrm,        0 },
00831     { X86::Int_VCVTSD2SSrr,   X86::Int_VCVTSD2SSrm,    0 },
00832     { X86::VCVTSI2SD64rr,     X86::VCVTSI2SD64rm,      0 },
00833     { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm,  0 },
00834     { X86::VCVTSI2SDrr,       X86::VCVTSI2SDrm,        0 },
00835     { X86::Int_VCVTSI2SDrr,   X86::Int_VCVTSI2SDrm,    0 },
00836     { X86::VCVTSI2SS64rr,     X86::VCVTSI2SS64rm,      0 },
00837     { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm,  0 },
00838     { X86::VCVTSI2SSrr,       X86::VCVTSI2SSrm,        0 },
00839     { X86::Int_VCVTSI2SSrr,   X86::Int_VCVTSI2SSrm,    0 },
00840     { X86::VCVTSS2SDrr,       X86::VCVTSS2SDrm,        0 },
00841     { X86::Int_VCVTSS2SDrr,   X86::Int_VCVTSS2SDrm,    0 },
00842     { X86::VCVTTPD2DQrr,      X86::VCVTTPD2DQXrm,      0 },
00843     { X86::VCVTTPS2DQrr,      X86::VCVTTPS2DQrm,       0 },
00844     { X86::VRSQRTSSr,         X86::VRSQRTSSm,          0 },
00845     { X86::VSQRTSDr,          X86::VSQRTSDm,           0 },
00846     { X86::VSQRTSSr,          X86::VSQRTSSm,           0 },
00847     { X86::VADDPDrr,          X86::VADDPDrm,           0 },
00848     { X86::VADDPSrr,          X86::VADDPSrm,           0 },
00849     { X86::VADDSDrr,          X86::VADDSDrm,           0 },
00850     { X86::VADDSSrr,          X86::VADDSSrm,           0 },
00851     { X86::VADDSUBPDrr,       X86::VADDSUBPDrm,        0 },
00852     { X86::VADDSUBPSrr,       X86::VADDSUBPSrm,        0 },
00853     { X86::VANDNPDrr,         X86::VANDNPDrm,          0 },
00854     { X86::VANDNPSrr,         X86::VANDNPSrm,          0 },
00855     { X86::VANDPDrr,          X86::VANDPDrm,           0 },
00856     { X86::VANDPSrr,          X86::VANDPSrm,           0 },
00857     { X86::VBLENDPDrri,       X86::VBLENDPDrmi,        0 },
00858     { X86::VBLENDPSrri,       X86::VBLENDPSrmi,        0 },
00859     { X86::VBLENDVPDrr,       X86::VBLENDVPDrm,        0 },
00860     { X86::VBLENDVPSrr,       X86::VBLENDVPSrm,        0 },
00861     { X86::VCMPPDrri,         X86::VCMPPDrmi,          0 },
00862     { X86::VCMPPSrri,         X86::VCMPPSrmi,          0 },
00863     { X86::VCMPSDrr,          X86::VCMPSDrm,           0 },
00864     { X86::VCMPSSrr,          X86::VCMPSSrm,           0 },
00865     { X86::VDIVPDrr,          X86::VDIVPDrm,           0 },
00866     { X86::VDIVPSrr,          X86::VDIVPSrm,           0 },
00867     { X86::VDIVSDrr,          X86::VDIVSDrm,           0 },
00868     { X86::VDIVSSrr,          X86::VDIVSSrm,           0 },
00869     { X86::VFsANDNPDrr,       X86::VFsANDNPDrm,        TB_ALIGN_16 },
00870     { X86::VFsANDNPSrr,       X86::VFsANDNPSrm,        TB_ALIGN_16 },
00871     { X86::VFsANDPDrr,        X86::VFsANDPDrm,         TB_ALIGN_16 },
00872     { X86::VFsANDPSrr,        X86::VFsANDPSrm,         TB_ALIGN_16 },
00873     { X86::VFsORPDrr,         X86::VFsORPDrm,          TB_ALIGN_16 },
00874     { X86::VFsORPSrr,         X86::VFsORPSrm,          TB_ALIGN_16 },
00875     { X86::VFsXORPDrr,        X86::VFsXORPDrm,         TB_ALIGN_16 },
00876     { X86::VFsXORPSrr,        X86::VFsXORPSrm,         TB_ALIGN_16 },
00877     { X86::VHADDPDrr,         X86::VHADDPDrm,          0 },
00878     { X86::VHADDPSrr,         X86::VHADDPSrm,          0 },
00879     { X86::VHSUBPDrr,         X86::VHSUBPDrm,          0 },
00880     { X86::VHSUBPSrr,         X86::VHSUBPSrm,          0 },
00881     { X86::Int_VCMPSDrr,      X86::Int_VCMPSDrm,       0 },
00882     { X86::Int_VCMPSSrr,      X86::Int_VCMPSSrm,       0 },
00883     { X86::VMAXPDrr,          X86::VMAXPDrm,           0 },
00884     { X86::VMAXPSrr,          X86::VMAXPSrm,           0 },
00885     { X86::VMAXSDrr,          X86::VMAXSDrm,           0 },
00886     { X86::VMAXSSrr,          X86::VMAXSSrm,           0 },
00887     { X86::VMINPDrr,          X86::VMINPDrm,           0 },
00888     { X86::VMINPSrr,          X86::VMINPSrm,           0 },
00889     { X86::VMINSDrr,          X86::VMINSDrm,           0 },
00890     { X86::VMINSSrr,          X86::VMINSSrm,           0 },
00891     { X86::VMPSADBWrri,       X86::VMPSADBWrmi,        0 },
00892     { X86::VMULPDrr,          X86::VMULPDrm,           0 },
00893     { X86::VMULPSrr,          X86::VMULPSrm,           0 },
00894     { X86::VMULSDrr,          X86::VMULSDrm,           0 },
00895     { X86::VMULSSrr,          X86::VMULSSrm,           0 },
00896     { X86::VORPDrr,           X86::VORPDrm,            0 },
00897     { X86::VORPSrr,           X86::VORPSrm,            0 },
00898     { X86::VPACKSSDWrr,       X86::VPACKSSDWrm,        0 },
00899     { X86::VPACKSSWBrr,       X86::VPACKSSWBrm,        0 },
00900     { X86::VPACKUSDWrr,       X86::VPACKUSDWrm,        0 },
00901     { X86::VPACKUSWBrr,       X86::VPACKUSWBrm,        0 },
00902     { X86::VPADDBrr,          X86::VPADDBrm,           0 },
00903     { X86::VPADDDrr,          X86::VPADDDrm,           0 },
00904     { X86::VPADDQrr,          X86::VPADDQrm,           0 },
00905     { X86::VPADDSBrr,         X86::VPADDSBrm,          0 },
00906     { X86::VPADDSWrr,         X86::VPADDSWrm,          0 },
00907     { X86::VPADDUSBrr,        X86::VPADDUSBrm,         0 },
00908     { X86::VPADDUSWrr,        X86::VPADDUSWrm,         0 },
00909     { X86::VPADDWrr,          X86::VPADDWrm,           0 },
00910     { X86::VPALIGNR128rr,     X86::VPALIGNR128rm,      0 },
00911     { X86::VPANDNrr,          X86::VPANDNrm,           0 },
00912     { X86::VPANDrr,           X86::VPANDrm,            0 },
00913     { X86::VPAVGBrr,          X86::VPAVGBrm,           0 },
00914     { X86::VPAVGWrr,          X86::VPAVGWrm,           0 },
00915     { X86::VPBLENDWrri,       X86::VPBLENDWrmi,        0 },
00916     { X86::VPCMPEQBrr,        X86::VPCMPEQBrm,         0 },
00917     { X86::VPCMPEQDrr,        X86::VPCMPEQDrm,         0 },
00918     { X86::VPCMPEQQrr,        X86::VPCMPEQQrm,         0 },
00919     { X86::VPCMPEQWrr,        X86::VPCMPEQWrm,         0 },
00920     { X86::VPCMPGTBrr,        X86::VPCMPGTBrm,         0 },
00921     { X86::VPCMPGTDrr,        X86::VPCMPGTDrm,         0 },
00922     { X86::VPCMPGTQrr,        X86::VPCMPGTQrm,         0 },
00923     { X86::VPCMPGTWrr,        X86::VPCMPGTWrm,         0 },
00924     { X86::VPHADDDrr,         X86::VPHADDDrm,          0 },
00925     { X86::VPHADDSWrr128,     X86::VPHADDSWrm128,      0 },
00926     { X86::VPHADDWrr,         X86::VPHADDWrm,          0 },
00927     { X86::VPHSUBDrr,         X86::VPHSUBDrm,          0 },
00928     { X86::VPHSUBSWrr128,     X86::VPHSUBSWrm128,      0 },
00929     { X86::VPHSUBWrr,         X86::VPHSUBWrm,          0 },
00930     { X86::VPERMILPDrr,       X86::VPERMILPDrm,        0 },
00931     { X86::VPERMILPSrr,       X86::VPERMILPSrm,        0 },
00932     { X86::VPINSRWrri,        X86::VPINSRWrmi,         0 },
00933     { X86::VPMADDUBSWrr128,   X86::VPMADDUBSWrm128,    0 },
00934     { X86::VPMADDWDrr,        X86::VPMADDWDrm,         0 },
00935     { X86::VPMAXSWrr,         X86::VPMAXSWrm,          0 },
00936     { X86::VPMAXUBrr,         X86::VPMAXUBrm,          0 },
00937     { X86::VPMINSWrr,         X86::VPMINSWrm,          0 },
00938     { X86::VPMINUBrr,         X86::VPMINUBrm,          0 },
00939     { X86::VPMINSBrr,         X86::VPMINSBrm,          0 },
00940     { X86::VPMINSDrr,         X86::VPMINSDrm,          0 },
00941     { X86::VPMINUDrr,         X86::VPMINUDrm,          0 },
00942     { X86::VPMINUWrr,         X86::VPMINUWrm,          0 },
00943     { X86::VPMAXSBrr,         X86::VPMAXSBrm,          0 },
00944     { X86::VPMAXSDrr,         X86::VPMAXSDrm,          0 },
00945     { X86::VPMAXUDrr,         X86::VPMAXUDrm,          0 },
00946     { X86::VPMAXUWrr,         X86::VPMAXUWrm,          0 },
00947     { X86::VPMULDQrr,         X86::VPMULDQrm,          0 },
00948     { X86::VPMULHRSWrr128,    X86::VPMULHRSWrm128,     0 },
00949     { X86::VPMULHUWrr,        X86::VPMULHUWrm,         0 },
00950     { X86::VPMULHWrr,         X86::VPMULHWrm,          0 },
00951     { X86::VPMULLDrr,         X86::VPMULLDrm,          0 },
00952     { X86::VPMULLWrr,         X86::VPMULLWrm,          0 },
00953     { X86::VPMULUDQrr,        X86::VPMULUDQrm,         0 },
00954     { X86::VPORrr,            X86::VPORrm,             0 },
00955     { X86::VPSADBWrr,         X86::VPSADBWrm,          0 },
00956     { X86::VPSHUFBrr,         X86::VPSHUFBrm,          0 },
00957     { X86::VPSIGNBrr,         X86::VPSIGNBrm,          0 },
00958     { X86::VPSIGNWrr,         X86::VPSIGNWrm,          0 },
00959     { X86::VPSIGNDrr,         X86::VPSIGNDrm,          0 },
00960     { X86::VPSLLDrr,          X86::VPSLLDrm,           0 },
00961     { X86::VPSLLQrr,          X86::VPSLLQrm,           0 },
00962     { X86::VPSLLWrr,          X86::VPSLLWrm,           0 },
00963     { X86::VPSRADrr,          X86::VPSRADrm,           0 },
00964     { X86::VPSRAWrr,          X86::VPSRAWrm,           0 },
00965     { X86::VPSRLDrr,          X86::VPSRLDrm,           0 },
00966     { X86::VPSRLQrr,          X86::VPSRLQrm,           0 },
00967     { X86::VPSRLWrr,          X86::VPSRLWrm,           0 },
00968     { X86::VPSUBBrr,          X86::VPSUBBrm,           0 },
00969     { X86::VPSUBDrr,          X86::VPSUBDrm,           0 },
00970     { X86::VPSUBSBrr,         X86::VPSUBSBrm,          0 },
00971     { X86::VPSUBSWrr,         X86::VPSUBSWrm,          0 },
00972     { X86::VPSUBWrr,          X86::VPSUBWrm,           0 },
00973     { X86::VPUNPCKHBWrr,      X86::VPUNPCKHBWrm,       0 },
00974     { X86::VPUNPCKHDQrr,      X86::VPUNPCKHDQrm,       0 },
00975     { X86::VPUNPCKHQDQrr,     X86::VPUNPCKHQDQrm,      0 },
00976     { X86::VPUNPCKHWDrr,      X86::VPUNPCKHWDrm,       0 },
00977     { X86::VPUNPCKLBWrr,      X86::VPUNPCKLBWrm,       0 },
00978     { X86::VPUNPCKLDQrr,      X86::VPUNPCKLDQrm,       0 },
00979     { X86::VPUNPCKLQDQrr,     X86::VPUNPCKLQDQrm,      0 },
00980     { X86::VPUNPCKLWDrr,      X86::VPUNPCKLWDrm,       0 },
00981     { X86::VPXORrr,           X86::VPXORrm,            0 },
00982     { X86::VSHUFPDrri,        X86::VSHUFPDrmi,         0 },
00983     { X86::VSHUFPSrri,        X86::VSHUFPSrmi,         0 },
00984     { X86::VSUBPDrr,          X86::VSUBPDrm,           0 },
00985     { X86::VSUBPSrr,          X86::VSUBPSrm,           0 },
00986     { X86::VSUBSDrr,          X86::VSUBSDrm,           0 },
00987     { X86::VSUBSSrr,          X86::VSUBSSrm,           0 },
00988     { X86::VUNPCKHPDrr,       X86::VUNPCKHPDrm,        0 },
00989     { X86::VUNPCKHPSrr,       X86::VUNPCKHPSrm,        0 },
00990     { X86::VUNPCKLPDrr,       X86::VUNPCKLPDrm,        0 },
00991     { X86::VUNPCKLPSrr,       X86::VUNPCKLPSrm,        0 },
00992     { X86::VXORPDrr,          X86::VXORPDrm,           0 },
00993     { X86::VXORPSrr,          X86::VXORPSrm,           0 },
00994     // AVX 256-bit foldable instructions
00995     { X86::VADDPDYrr,         X86::VADDPDYrm,          0 },
00996     { X86::VADDPSYrr,         X86::VADDPSYrm,          0 },
00997     { X86::VADDSUBPDYrr,      X86::VADDSUBPDYrm,       0 },
00998     { X86::VADDSUBPSYrr,      X86::VADDSUBPSYrm,       0 },
00999     { X86::VANDNPDYrr,        X86::VANDNPDYrm,         0 },
01000     { X86::VANDNPSYrr,        X86::VANDNPSYrm,         0 },
01001     { X86::VANDPDYrr,         X86::VANDPDYrm,          0 },
01002     { X86::VANDPSYrr,         X86::VANDPSYrm,          0 },
01003     { X86::VBLENDPDYrri,      X86::VBLENDPDYrmi,       0 },
01004     { X86::VBLENDPSYrri,      X86::VBLENDPSYrmi,       0 },
01005     { X86::VBLENDVPDYrr,      X86::VBLENDVPDYrm,       0 },
01006     { X86::VBLENDVPSYrr,      X86::VBLENDVPSYrm,       0 },
01007     { X86::VCMPPDYrri,        X86::VCMPPDYrmi,         0 },
01008     { X86::VCMPPSYrri,        X86::VCMPPSYrmi,         0 },
01009     { X86::VDIVPDYrr,         X86::VDIVPDYrm,          0 },
01010     { X86::VDIVPSYrr,         X86::VDIVPSYrm,          0 },
01011     { X86::VHADDPDYrr,        X86::VHADDPDYrm,         0 },
01012     { X86::VHADDPSYrr,        X86::VHADDPSYrm,         0 },
01013     { X86::VHSUBPDYrr,        X86::VHSUBPDYrm,         0 },
01014     { X86::VHSUBPSYrr,        X86::VHSUBPSYrm,         0 },
01015     { X86::VINSERTF128rr,     X86::VINSERTF128rm,      0 },
01016     { X86::VMAXPDYrr,         X86::VMAXPDYrm,          0 },
01017     { X86::VMAXPSYrr,         X86::VMAXPSYrm,          0 },
01018     { X86::VMINPDYrr,         X86::VMINPDYrm,          0 },
01019     { X86::VMINPSYrr,         X86::VMINPSYrm,          0 },
01020     { X86::VMULPDYrr,         X86::VMULPDYrm,          0 },
01021     { X86::VMULPSYrr,         X86::VMULPSYrm,          0 },
01022     { X86::VORPDYrr,          X86::VORPDYrm,           0 },
01023     { X86::VORPSYrr,          X86::VORPSYrm,           0 },
01024     { X86::VPERM2F128rr,      X86::VPERM2F128rm,       0 },
01025     { X86::VPERMILPDYrr,      X86::VPERMILPDYrm,       0 },
01026     { X86::VPERMILPSYrr,      X86::VPERMILPSYrm,       0 },
01027     { X86::VSHUFPDYrri,       X86::VSHUFPDYrmi,        0 },
01028     { X86::VSHUFPSYrri,       X86::VSHUFPSYrmi,        0 },
01029     { X86::VSUBPDYrr,         X86::VSUBPDYrm,          0 },
01030     { X86::VSUBPSYrr,         X86::VSUBPSYrm,          0 },
01031     { X86::VUNPCKHPDYrr,      X86::VUNPCKHPDYrm,       0 },
01032     { X86::VUNPCKHPSYrr,      X86::VUNPCKHPSYrm,       0 },
01033     { X86::VUNPCKLPDYrr,      X86::VUNPCKLPDYrm,       0 },
01034     { X86::VUNPCKLPSYrr,      X86::VUNPCKLPSYrm,       0 },
01035     { X86::VXORPDYrr,         X86::VXORPDYrm,          0 },
01036     { X86::VXORPSYrr,         X86::VXORPSYrm,          0 },
01037     // AVX2 foldable instructions
01038     { X86::VINSERTI128rr,     X86::VINSERTI128rm,      0 },
01039     { X86::VPACKSSDWYrr,      X86::VPACKSSDWYrm,       0 },
01040     { X86::VPACKSSWBYrr,      X86::VPACKSSWBYrm,       0 },
01041     { X86::VPACKUSDWYrr,      X86::VPACKUSDWYrm,       0 },
01042     { X86::VPACKUSWBYrr,      X86::VPACKUSWBYrm,       0 },
01043     { X86::VPADDBYrr,         X86::VPADDBYrm,          0 },
01044     { X86::VPADDDYrr,         X86::VPADDDYrm,          0 },
01045     { X86::VPADDQYrr,         X86::VPADDQYrm,          0 },
01046     { X86::VPADDSBYrr,        X86::VPADDSBYrm,         0 },
01047     { X86::VPADDSWYrr,        X86::VPADDSWYrm,         0 },
01048     { X86::VPADDUSBYrr,       X86::VPADDUSBYrm,        0 },
01049     { X86::VPADDUSWYrr,       X86::VPADDUSWYrm,        0 },
01050     { X86::VPADDWYrr,         X86::VPADDWYrm,          0 },
01051     { X86::VPALIGNR256rr,     X86::VPALIGNR256rm,      0 },
01052     { X86::VPANDNYrr,         X86::VPANDNYrm,          0 },
01053     { X86::VPANDYrr,          X86::VPANDYrm,           0 },
01054     { X86::VPAVGBYrr,         X86::VPAVGBYrm,          0 },
01055     { X86::VPAVGWYrr,         X86::VPAVGWYrm,          0 },
01056     { X86::VPBLENDDrri,       X86::VPBLENDDrmi,        0 },
01057     { X86::VPBLENDDYrri,      X86::VPBLENDDYrmi,       0 },
01058     { X86::VPBLENDWYrri,      X86::VPBLENDWYrmi,       0 },
01059     { X86::VPCMPEQBYrr,       X86::VPCMPEQBYrm,        0 },
01060     { X86::VPCMPEQDYrr,       X86::VPCMPEQDYrm,        0 },
01061     { X86::VPCMPEQQYrr,       X86::VPCMPEQQYrm,        0 },
01062     { X86::VPCMPEQWYrr,       X86::VPCMPEQWYrm,        0 },
01063     { X86::VPCMPGTBYrr,       X86::VPCMPGTBYrm,        0 },
01064     { X86::VPCMPGTDYrr,       X86::VPCMPGTDYrm,        0 },
01065     { X86::VPCMPGTQYrr,       X86::VPCMPGTQYrm,        0 },
01066     { X86::VPCMPGTWYrr,       X86::VPCMPGTWYrm,        0 },
01067     { X86::VPERM2I128rr,      X86::VPERM2I128rm,       0 },
01068     { X86::VPERMDYrr,         X86::VPERMDYrm,          0 },
01069     { X86::VPERMPDYri,        X86::VPERMPDYmi,         0 },
01070     { X86::VPERMPSYrr,        X86::VPERMPSYrm,         0 },
01071     { X86::VPERMQYri,         X86::VPERMQYmi,          0 },
01072     { X86::VPHADDDYrr,        X86::VPHADDDYrm,         0 },
01073     { X86::VPHADDSWrr256,     X86::VPHADDSWrm256,      0 },
01074     { X86::VPHADDWYrr,        X86::VPHADDWYrm,         0 },
01075     { X86::VPHSUBDYrr,        X86::VPHSUBDYrm,         0 },
01076     { X86::VPHSUBSWrr256,     X86::VPHSUBSWrm256,      0 },
01077     { X86::VPHSUBWYrr,        X86::VPHSUBWYrm,         0 },
01078     { X86::VPMADDUBSWrr256,   X86::VPMADDUBSWrm256,    0 },
01079     { X86::VPMADDWDYrr,       X86::VPMADDWDYrm,        0 },
01080     { X86::VPMAXSWYrr,        X86::VPMAXSWYrm,         0 },
01081     { X86::VPMAXUBYrr,        X86::VPMAXUBYrm,         0 },
01082     { X86::VPMINSWYrr,        X86::VPMINSWYrm,         0 },
01083     { X86::VPMINUBYrr,        X86::VPMINUBYrm,         0 },
01084     { X86::VPMINSBYrr,        X86::VPMINSBYrm,         0 },
01085     { X86::VPMINSDYrr,        X86::VPMINSDYrm,         0 },
01086     { X86::VPMINUDYrr,        X86::VPMINUDYrm,         0 },
01087     { X86::VPMINUWYrr,        X86::VPMINUWYrm,         0 },
01088     { X86::VPMAXSBYrr,        X86::VPMAXSBYrm,         0 },
01089     { X86::VPMAXSDYrr,        X86::VPMAXSDYrm,         0 },
01090     { X86::VPMAXUDYrr,        X86::VPMAXUDYrm,         0 },
01091     { X86::VPMAXUWYrr,        X86::VPMAXUWYrm,         0 },
01092     { X86::VMPSADBWYrri,      X86::VMPSADBWYrmi,       0 },
01093     { X86::VPMULDQYrr,        X86::VPMULDQYrm,         0 },
01094     { X86::VPMULHRSWrr256,    X86::VPMULHRSWrm256,     0 },
01095     { X86::VPMULHUWYrr,       X86::VPMULHUWYrm,        0 },
01096     { X86::VPMULHWYrr,        X86::VPMULHWYrm,         0 },
01097     { X86::VPMULLDYrr,        X86::VPMULLDYrm,         0 },
01098     { X86::VPMULLWYrr,        X86::VPMULLWYrm,         0 },
01099     { X86::VPMULUDQYrr,       X86::VPMULUDQYrm,        0 },
01100     { X86::VPORYrr,           X86::VPORYrm,            0 },
01101     { X86::VPSADBWYrr,        X86::VPSADBWYrm,         0 },
01102     { X86::VPSHUFBYrr,        X86::VPSHUFBYrm,         0 },
01103     { X86::VPSIGNBYrr,        X86::VPSIGNBYrm,         0 },
01104     { X86::VPSIGNWYrr,        X86::VPSIGNWYrm,         0 },
01105     { X86::VPSIGNDYrr,        X86::VPSIGNDYrm,         0 },
01106     { X86::VPSLLDYrr,         X86::VPSLLDYrm,          0 },
01107     { X86::VPSLLQYrr,         X86::VPSLLQYrm,          0 },
01108     { X86::VPSLLWYrr,         X86::VPSLLWYrm,          0 },
01109     { X86::VPSLLVDrr,         X86::VPSLLVDrm,          0 },
01110     { X86::VPSLLVDYrr,        X86::VPSLLVDYrm,         0 },
01111     { X86::VPSLLVQrr,         X86::VPSLLVQrm,          0 },
01112     { X86::VPSLLVQYrr,        X86::VPSLLVQYrm,         0 },
01113     { X86::VPSRADYrr,         X86::VPSRADYrm,          0 },
01114     { X86::VPSRAWYrr,         X86::VPSRAWYrm,          0 },
01115     { X86::VPSRAVDrr,         X86::VPSRAVDrm,          0 },
01116     { X86::VPSRAVDYrr,        X86::VPSRAVDYrm,         0 },
01117     { X86::VPSRLDYrr,         X86::VPSRLDYrm,          0 },
01118     { X86::VPSRLQYrr,         X86::VPSRLQYrm,          0 },
01119     { X86::VPSRLWYrr,         X86::VPSRLWYrm,          0 },
01120     { X86::VPSRLVDrr,         X86::VPSRLVDrm,          0 },
01121     { X86::VPSRLVDYrr,        X86::VPSRLVDYrm,         0 },
01122     { X86::VPSRLVQrr,         X86::VPSRLVQrm,          0 },
01123     { X86::VPSRLVQYrr,        X86::VPSRLVQYrm,         0 },
01124     { X86::VPSUBBYrr,         X86::VPSUBBYrm,          0 },
01125     { X86::VPSUBDYrr,         X86::VPSUBDYrm,          0 },
01126     { X86::VPSUBSBYrr,        X86::VPSUBSBYrm,         0 },
01127     { X86::VPSUBSWYrr,        X86::VPSUBSWYrm,         0 },
01128     { X86::VPSUBWYrr,         X86::VPSUBWYrm,          0 },
01129     { X86::VPUNPCKHBWYrr,     X86::VPUNPCKHBWYrm,      0 },
01130     { X86::VPUNPCKHDQYrr,     X86::VPUNPCKHDQYrm,      0 },
01131     { X86::VPUNPCKHQDQYrr,    X86::VPUNPCKHQDQYrm,     0 },
01132     { X86::VPUNPCKHWDYrr,     X86::VPUNPCKHWDYrm,      0 },
01133     { X86::VPUNPCKLBWYrr,     X86::VPUNPCKLBWYrm,      0 },
01134     { X86::VPUNPCKLDQYrr,     X86::VPUNPCKLDQYrm,      0 },
01135     { X86::VPUNPCKLQDQYrr,    X86::VPUNPCKLQDQYrm,     0 },
01136     { X86::VPUNPCKLWDYrr,     X86::VPUNPCKLWDYrm,      0 },
01137     { X86::VPXORYrr,          X86::VPXORYrm,           0 },
01138     // FIXME: add AVX 256-bit foldable instructions
01139 
01140     // FMA4 foldable patterns
01141     { X86::VFMADDSS4rr,       X86::VFMADDSS4mr,        0           },
01142     { X86::VFMADDSD4rr,       X86::VFMADDSD4mr,        0           },
01143     { X86::VFMADDPS4rr,       X86::VFMADDPS4mr,        TB_ALIGN_16 },
01144     { X86::VFMADDPD4rr,       X86::VFMADDPD4mr,        TB_ALIGN_16 },
01145     { X86::VFMADDPS4rrY,      X86::VFMADDPS4mrY,       TB_ALIGN_32 },
01146     { X86::VFMADDPD4rrY,      X86::VFMADDPD4mrY,       TB_ALIGN_32 },
01147     { X86::VFNMADDSS4rr,      X86::VFNMADDSS4mr,       0           },
01148     { X86::VFNMADDSD4rr,      X86::VFNMADDSD4mr,       0           },
01149     { X86::VFNMADDPS4rr,      X86::VFNMADDPS4mr,       TB_ALIGN_16 },
01150     { X86::VFNMADDPD4rr,      X86::VFNMADDPD4mr,       TB_ALIGN_16 },
01151     { X86::VFNMADDPS4rrY,     X86::VFNMADDPS4mrY,      TB_ALIGN_32 },
01152     { X86::VFNMADDPD4rrY,     X86::VFNMADDPD4mrY,      TB_ALIGN_32 },
01153     { X86::VFMSUBSS4rr,       X86::VFMSUBSS4mr,        0           },
01154     { X86::VFMSUBSD4rr,       X86::VFMSUBSD4mr,        0           },
01155     { X86::VFMSUBPS4rr,       X86::VFMSUBPS4mr,        TB_ALIGN_16 },
01156     { X86::VFMSUBPD4rr,       X86::VFMSUBPD4mr,        TB_ALIGN_16 },
01157     { X86::VFMSUBPS4rrY,      X86::VFMSUBPS4mrY,       TB_ALIGN_32 },
01158     { X86::VFMSUBPD4rrY,      X86::VFMSUBPD4mrY,       TB_ALIGN_32 },
01159     { X86::VFNMSUBSS4rr,      X86::VFNMSUBSS4mr,       0           },
01160     { X86::VFNMSUBSD4rr,      X86::VFNMSUBSD4mr,       0           },
01161     { X86::VFNMSUBPS4rr,      X86::VFNMSUBPS4mr,       TB_ALIGN_16 },
01162     { X86::VFNMSUBPD4rr,      X86::VFNMSUBPD4mr,       TB_ALIGN_16 },
01163     { X86::VFNMSUBPS4rrY,     X86::VFNMSUBPS4mrY,      TB_ALIGN_32 },
01164     { X86::VFNMSUBPD4rrY,     X86::VFNMSUBPD4mrY,      TB_ALIGN_32 },
01165     { X86::VFMADDSUBPS4rr,    X86::VFMADDSUBPS4mr,     TB_ALIGN_16 },
01166     { X86::VFMADDSUBPD4rr,    X86::VFMADDSUBPD4mr,     TB_ALIGN_16 },
01167     { X86::VFMADDSUBPS4rrY,   X86::VFMADDSUBPS4mrY,    TB_ALIGN_32 },
01168     { X86::VFMADDSUBPD4rrY,   X86::VFMADDSUBPD4mrY,    TB_ALIGN_32 },
01169     { X86::VFMSUBADDPS4rr,    X86::VFMSUBADDPS4mr,     TB_ALIGN_16 },
01170     { X86::VFMSUBADDPD4rr,    X86::VFMSUBADDPD4mr,     TB_ALIGN_16 },
01171     { X86::VFMSUBADDPS4rrY,   X86::VFMSUBADDPS4mrY,    TB_ALIGN_32 },
01172     { X86::VFMSUBADDPD4rrY,   X86::VFMSUBADDPD4mrY,    TB_ALIGN_32 },
01173 
01174     // BMI/BMI2 foldable instructions
01175     { X86::ANDN32rr,          X86::ANDN32rm,            0 },
01176     { X86::ANDN64rr,          X86::ANDN64rm,            0 },
01177     { X86::MULX32rr,          X86::MULX32rm,            0 },
01178     { X86::MULX64rr,          X86::MULX64rm,            0 },
01179     { X86::PDEP32rr,          X86::PDEP32rm,            0 },
01180     { X86::PDEP64rr,          X86::PDEP64rm,            0 },
01181     { X86::PEXT32rr,          X86::PEXT32rm,            0 },
01182     { X86::PEXT64rr,          X86::PEXT64rm,            0 },
01183   };
01184 
01185   for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
01186     unsigned RegOp = OpTbl2[i].RegOp;
01187     unsigned MemOp = OpTbl2[i].MemOp;
01188     unsigned Flags = OpTbl2[i].Flags;
01189     AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
01190                   RegOp, MemOp,
01191                   // Index 2, folded load
01192                   Flags | TB_INDEX_2 | TB_FOLDED_LOAD);
01193   }
01194 
01195   static const X86OpTblEntry OpTbl3[] = {
01196     // FMA foldable instructions
01197     { X86::VFMADDSSr231r,         X86::VFMADDSSr231m,         0 },
01198     { X86::VFMADDSDr231r,         X86::VFMADDSDr231m,         0 },
01199     { X86::VFMADDSSr132r,         X86::VFMADDSSr132m,         0 },
01200     { X86::VFMADDSDr132r,         X86::VFMADDSDr132m,         0 },
01201     { X86::VFMADDSSr213r,         X86::VFMADDSSr213m,         0 },
01202     { X86::VFMADDSDr213r,         X86::VFMADDSDr213m,         0 },
01203     { X86::VFMADDSSr213r_Int,     X86::VFMADDSSr213m_Int,     0 },
01204     { X86::VFMADDSDr213r_Int,     X86::VFMADDSDr213m_Int,     0 },
01205 
01206     { X86::VFMADDPSr231r,         X86::VFMADDPSr231m,         TB_ALIGN_16 },
01207     { X86::VFMADDPDr231r,         X86::VFMADDPDr231m,         TB_ALIGN_16 },
01208     { X86::VFMADDPSr132r,         X86::VFMADDPSr132m,         TB_ALIGN_16 },
01209     { X86::VFMADDPDr132r,         X86::VFMADDPDr132m,         TB_ALIGN_16 },
01210     { X86::VFMADDPSr213r,         X86::VFMADDPSr213m,         TB_ALIGN_16 },
01211     { X86::VFMADDPDr213r,         X86::VFMADDPDr213m,         TB_ALIGN_16 },
01212     { X86::VFMADDPSr231rY,        X86::VFMADDPSr231mY,        TB_ALIGN_32 },
01213     { X86::VFMADDPDr231rY,        X86::VFMADDPDr231mY,        TB_ALIGN_32 },
01214     { X86::VFMADDPSr132rY,        X86::VFMADDPSr132mY,        TB_ALIGN_32 },
01215     { X86::VFMADDPDr132rY,        X86::VFMADDPDr132mY,        TB_ALIGN_32 },
01216     { X86::VFMADDPSr213rY,        X86::VFMADDPSr213mY,        TB_ALIGN_32 },
01217     { X86::VFMADDPDr213rY,        X86::VFMADDPDr213mY,        TB_ALIGN_32 },
01218 
01219     { X86::VFNMADDSSr231r,        X86::VFNMADDSSr231m,        0 },
01220     { X86::VFNMADDSDr231r,        X86::VFNMADDSDr231m,        0 },
01221     { X86::VFNMADDSSr132r,        X86::VFNMADDSSr132m,        0 },
01222     { X86::VFNMADDSDr132r,        X86::VFNMADDSDr132m,        0 },
01223     { X86::VFNMADDSSr213r,        X86::VFNMADDSSr213m,        0 },
01224     { X86::VFNMADDSDr213r,        X86::VFNMADDSDr213m,        0 },
01225     { X86::VFNMADDSSr213r_Int,    X86::VFNMADDSSr213m_Int,    0 },
01226     { X86::VFNMADDSDr213r_Int,    X86::VFNMADDSDr213m_Int,    0 },
01227 
01228     { X86::VFNMADDPSr231r,        X86::VFNMADDPSr231m,        TB_ALIGN_16 },
01229     { X86::VFNMADDPDr231r,        X86::VFNMADDPDr231m,        TB_ALIGN_16 },
01230     { X86::VFNMADDPSr132r,        X86::VFNMADDPSr132m,        TB_ALIGN_16 },
01231     { X86::VFNMADDPDr132r,        X86::VFNMADDPDr132m,        TB_ALIGN_16 },
01232     { X86::VFNMADDPSr213r,        X86::VFNMADDPSr213m,        TB_ALIGN_16 },
01233     { X86::VFNMADDPDr213r,        X86::VFNMADDPDr213m,        TB_ALIGN_16 },
01234     { X86::VFNMADDPSr231rY,       X86::VFNMADDPSr231mY,       TB_ALIGN_32 },
01235     { X86::VFNMADDPDr231rY,       X86::VFNMADDPDr231mY,       TB_ALIGN_32 },
01236     { X86::VFNMADDPSr132rY,       X86::VFNMADDPSr132mY,       TB_ALIGN_32 },
01237     { X86::VFNMADDPDr132rY,       X86::VFNMADDPDr132mY,       TB_ALIGN_32 },
01238     { X86::VFNMADDPSr213rY,       X86::VFNMADDPSr213mY,       TB_ALIGN_32 },
01239     { X86::VFNMADDPDr213rY,       X86::VFNMADDPDr213mY,       TB_ALIGN_32 },
01240 
01241     { X86::VFMSUBSSr231r,         X86::VFMSUBSSr231m,         0 },
01242     { X86::VFMSUBSDr231r,         X86::VFMSUBSDr231m,         0 },
01243     { X86::VFMSUBSSr132r,         X86::VFMSUBSSr132m,         0 },
01244     { X86::VFMSUBSDr132r,         X86::VFMSUBSDr132m,         0 },
01245     { X86::VFMSUBSSr213r,         X86::VFMSUBSSr213m,         0 },
01246     { X86::VFMSUBSDr213r,         X86::VFMSUBSDr213m,         0 },
01247     { X86::VFMSUBSSr213r_Int,     X86::VFMSUBSSr213m_Int,     0 },
01248     { X86::VFMSUBSDr213r_Int,     X86::VFMSUBSDr213m_Int,     0 },
01249 
01250     { X86::VFMSUBPSr231r,         X86::VFMSUBPSr231m,         TB_ALIGN_16 },
01251     { X86::VFMSUBPDr231r,         X86::VFMSUBPDr231m,         TB_ALIGN_16 },
01252     { X86::VFMSUBPSr132r,         X86::VFMSUBPSr132m,         TB_ALIGN_16 },
01253     { X86::VFMSUBPDr132r,         X86::VFMSUBPDr132m,         TB_ALIGN_16 },
01254     { X86::VFMSUBPSr213r,         X86::VFMSUBPSr213m,         TB_ALIGN_16 },
01255     { X86::VFMSUBPDr213r,         X86::VFMSUBPDr213m,         TB_ALIGN_16 },
01256     { X86::VFMSUBPSr231rY,        X86::VFMSUBPSr231mY,        TB_ALIGN_32 },
01257     { X86::VFMSUBPDr231rY,        X86::VFMSUBPDr231mY,        TB_ALIGN_32 },
01258     { X86::VFMSUBPSr132rY,        X86::VFMSUBPSr132mY,        TB_ALIGN_32 },
01259     { X86::VFMSUBPDr132rY,        X86::VFMSUBPDr132mY,        TB_ALIGN_32 },
01260     { X86::VFMSUBPSr213rY,        X86::VFMSUBPSr213mY,        TB_ALIGN_32 },
01261     { X86::VFMSUBPDr213rY,        X86::VFMSUBPDr213mY,        TB_ALIGN_32 },
01262 
01263     { X86::VFNMSUBSSr231r,        X86::VFNMSUBSSr231m,        0 },
01264     { X86::VFNMSUBSDr231r,        X86::VFNMSUBSDr231m,        0 },
01265     { X86::VFNMSUBSSr132r,        X86::VFNMSUBSSr132m,        0 },
01266     { X86::VFNMSUBSDr132r,        X86::VFNMSUBSDr132m,        0 },
01267     { X86::VFNMSUBSSr213r,        X86::VFNMSUBSSr213m,        0 },
01268     { X86::VFNMSUBSDr213r,        X86::VFNMSUBSDr213m,        0 },
01269     { X86::VFNMSUBSSr213r_Int,    X86::VFNMSUBSSr213m_Int,    0 },
01270     { X86::VFNMSUBSDr213r_Int,    X86::VFNMSUBSDr213m_Int,    0 },
01271 
01272     { X86::VFNMSUBPSr231r,        X86::VFNMSUBPSr231m,        TB_ALIGN_16 },
01273     { X86::VFNMSUBPDr231r,        X86::VFNMSUBPDr231m,        TB_ALIGN_16 },
01274     { X86::VFNMSUBPSr132r,        X86::VFNMSUBPSr132m,        TB_ALIGN_16 },
01275     { X86::VFNMSUBPDr132r,        X86::VFNMSUBPDr132m,        TB_ALIGN_16 },
01276     { X86::VFNMSUBPSr213r,        X86::VFNMSUBPSr213m,        TB_ALIGN_16 },
01277     { X86::VFNMSUBPDr213r,        X86::VFNMSUBPDr213m,        TB_ALIGN_16 },
01278     { X86::VFNMSUBPSr231rY,       X86::VFNMSUBPSr231mY,       TB_ALIGN_32 },
01279     { X86::VFNMSUBPDr231rY,       X86::VFNMSUBPDr231mY,       TB_ALIGN_32 },
01280     { X86::VFNMSUBPSr132rY,       X86::VFNMSUBPSr132mY,       TB_ALIGN_32 },
01281     { X86::VFNMSUBPDr132rY,       X86::VFNMSUBPDr132mY,       TB_ALIGN_32 },
01282     { X86::VFNMSUBPSr213rY,       X86::VFNMSUBPSr213mY,       TB_ALIGN_32 },
01283     { X86::VFNMSUBPDr213rY,       X86::VFNMSUBPDr213mY,       TB_ALIGN_32 },
01284 
01285     { X86::VFMADDSUBPSr231r,      X86::VFMADDSUBPSr231m,      TB_ALIGN_16 },
01286     { X86::VFMADDSUBPDr231r,      X86::VFMADDSUBPDr231m,      TB_ALIGN_16 },
01287     { X86::VFMADDSUBPSr132r,      X86::VFMADDSUBPSr132m,      TB_ALIGN_16 },
01288     { X86::VFMADDSUBPDr132r,      X86::VFMADDSUBPDr132m,      TB_ALIGN_16 },
01289     { X86::VFMADDSUBPSr213r,      X86::VFMADDSUBPSr213m,      TB_ALIGN_16 },
01290     { X86::VFMADDSUBPDr213r,      X86::VFMADDSUBPDr213m,      TB_ALIGN_16 },
01291     { X86::VFMADDSUBPSr231rY,     X86::VFMADDSUBPSr231mY,     TB_ALIGN_32 },
01292     { X86::VFMADDSUBPDr231rY,     X86::VFMADDSUBPDr231mY,     TB_ALIGN_32 },
01293     { X86::VFMADDSUBPSr132rY,     X86::VFMADDSUBPSr132mY,     TB_ALIGN_32 },
01294     { X86::VFMADDSUBPDr132rY,     X86::VFMADDSUBPDr132mY,     TB_ALIGN_32 },
01295     { X86::VFMADDSUBPSr213rY,     X86::VFMADDSUBPSr213mY,     TB_ALIGN_32 },
01296     { X86::VFMADDSUBPDr213rY,     X86::VFMADDSUBPDr213mY,     TB_ALIGN_32 },
01297 
01298     { X86::VFMSUBADDPSr231r,      X86::VFMSUBADDPSr231m,      TB_ALIGN_16 },
01299     { X86::VFMSUBADDPDr231r,      X86::VFMSUBADDPDr231m,      TB_ALIGN_16 },
01300     { X86::VFMSUBADDPSr132r,      X86::VFMSUBADDPSr132m,      TB_ALIGN_16 },
01301     { X86::VFMSUBADDPDr132r,      X86::VFMSUBADDPDr132m,      TB_ALIGN_16 },
01302     { X86::VFMSUBADDPSr213r,      X86::VFMSUBADDPSr213m,      TB_ALIGN_16 },
01303     { X86::VFMSUBADDPDr213r,      X86::VFMSUBADDPDr213m,      TB_ALIGN_16 },
01304     { X86::VFMSUBADDPSr231rY,     X86::VFMSUBADDPSr231mY,     TB_ALIGN_32 },
01305     { X86::VFMSUBADDPDr231rY,     X86::VFMSUBADDPDr231mY,     TB_ALIGN_32 },
01306     { X86::VFMSUBADDPSr132rY,     X86::VFMSUBADDPSr132mY,     TB_ALIGN_32 },
01307     { X86::VFMSUBADDPDr132rY,     X86::VFMSUBADDPDr132mY,     TB_ALIGN_32 },
01308     { X86::VFMSUBADDPSr213rY,     X86::VFMSUBADDPSr213mY,     TB_ALIGN_32 },
01309     { X86::VFMSUBADDPDr213rY,     X86::VFMSUBADDPDr213mY,     TB_ALIGN_32 },
01310 
01311     // FMA4 foldable patterns
01312     { X86::VFMADDSS4rr,           X86::VFMADDSS4rm,           0           },
01313     { X86::VFMADDSD4rr,           X86::VFMADDSD4rm,           0           },
01314     { X86::VFMADDPS4rr,           X86::VFMADDPS4rm,           TB_ALIGN_16 },
01315     { X86::VFMADDPD4rr,           X86::VFMADDPD4rm,           TB_ALIGN_16 },
01316     { X86::VFMADDPS4rrY,          X86::VFMADDPS4rmY,          TB_ALIGN_32 },
01317     { X86::VFMADDPD4rrY,          X86::VFMADDPD4rmY,          TB_ALIGN_32 },
01318     { X86::VFNMADDSS4rr,          X86::VFNMADDSS4rm,          0           },
01319     { X86::VFNMADDSD4rr,          X86::VFNMADDSD4rm,          0           },
01320     { X86::VFNMADDPS4rr,          X86::VFNMADDPS4rm,          TB_ALIGN_16 },
01321     { X86::VFNMADDPD4rr,          X86::VFNMADDPD4rm,          TB_ALIGN_16 },
01322     { X86::VFNMADDPS4rrY,         X86::VFNMADDPS4rmY,         TB_ALIGN_32 },
01323     { X86::VFNMADDPD4rrY,         X86::VFNMADDPD4rmY,         TB_ALIGN_32 },
01324     { X86::VFMSUBSS4rr,           X86::VFMSUBSS4rm,           0           },
01325     { X86::VFMSUBSD4rr,           X86::VFMSUBSD4rm,           0           },
01326     { X86::VFMSUBPS4rr,           X86::VFMSUBPS4rm,           TB_ALIGN_16 },
01327     { X86::VFMSUBPD4rr,           X86::VFMSUBPD4rm,           TB_ALIGN_16 },
01328     { X86::VFMSUBPS4rrY,          X86::VFMSUBPS4rmY,          TB_ALIGN_32 },
01329     { X86::VFMSUBPD4rrY,          X86::VFMSUBPD4rmY,          TB_ALIGN_32 },
01330     { X86::VFNMSUBSS4rr,          X86::VFNMSUBSS4rm,          0           },
01331     { X86::VFNMSUBSD4rr,          X86::VFNMSUBSD4rm,          0           },
01332     { X86::VFNMSUBPS4rr,          X86::VFNMSUBPS4rm,          TB_ALIGN_16 },
01333     { X86::VFNMSUBPD4rr,          X86::VFNMSUBPD4rm,          TB_ALIGN_16 },
01334     { X86::VFNMSUBPS4rrY,         X86::VFNMSUBPS4rmY,         TB_ALIGN_32 },
01335     { X86::VFNMSUBPD4rrY,         X86::VFNMSUBPD4rmY,         TB_ALIGN_32 },
01336     { X86::VFMADDSUBPS4rr,        X86::VFMADDSUBPS4rm,        TB_ALIGN_16 },
01337     { X86::VFMADDSUBPD4rr,        X86::VFMADDSUBPD4rm,        TB_ALIGN_16 },
01338     { X86::VFMADDSUBPS4rrY,       X86::VFMADDSUBPS4rmY,       TB_ALIGN_32 },
01339     { X86::VFMADDSUBPD4rrY,       X86::VFMADDSUBPD4rmY,       TB_ALIGN_32 },
01340     { X86::VFMSUBADDPS4rr,        X86::VFMSUBADDPS4rm,        TB_ALIGN_16 },
01341     { X86::VFMSUBADDPD4rr,        X86::VFMSUBADDPD4rm,        TB_ALIGN_16 },
01342     { X86::VFMSUBADDPS4rrY,       X86::VFMSUBADDPS4rmY,       TB_ALIGN_32 },
01343     { X86::VFMSUBADDPD4rrY,       X86::VFMSUBADDPD4rmY,       TB_ALIGN_32 },
01344   };
01345 
01346   for (unsigned i = 0, e = array_lengthof(OpTbl3); i != e; ++i) {
01347     unsigned RegOp = OpTbl3[i].RegOp;
01348     unsigned MemOp = OpTbl3[i].MemOp;
01349     unsigned Flags = OpTbl3[i].Flags;
01350     AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
01351                   RegOp, MemOp,
01352                   // Index 3, folded load
01353                   Flags | TB_INDEX_3 | TB_FOLDED_LOAD);
01354   }
01355 
01356 }
01357 
01358 void
01359 X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
01360                             MemOp2RegOpTableType &M2RTable,
01361                             unsigned RegOp, unsigned MemOp, unsigned Flags) {
01362     if ((Flags & TB_NO_FORWARD) == 0) {
01363       assert(!R2MTable.count(RegOp) && "Duplicate entry!");
01364       R2MTable[RegOp] = std::make_pair(MemOp, Flags);
01365     }
01366     if ((Flags & TB_NO_REVERSE) == 0) {
01367       assert(!M2RTable.count(MemOp) &&
01368            "Duplicated entries in unfolding maps?");
01369       M2RTable[MemOp] = std::make_pair(RegOp, Flags);
01370     }
01371 }
01372 
01373 bool
01374 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
01375                                     unsigned &SrcReg, unsigned &DstReg,
01376                                     unsigned &SubIdx) const {
01377   switch (MI.getOpcode()) {
01378   default: break;
01379   case X86::MOVSX16rr8:
01380   case X86::MOVZX16rr8:
01381   case X86::MOVSX32rr8:
01382   case X86::MOVZX32rr8:
01383   case X86::MOVSX64rr8:
01384   case X86::MOVZX64rr8:
01385     if (!TM.getSubtarget<X86Subtarget>().is64Bit())
01386       // It's not always legal to reference the low 8-bit of the larger
01387       // register in 32-bit mode.
01388       return false;
01389   case X86::MOVSX32rr16:
01390   case X86::MOVZX32rr16:
01391   case X86::MOVSX64rr16:
01392   case X86::MOVZX64rr16:
01393   case X86::MOVSX64rr32:
01394   case X86::MOVZX64rr32: {
01395     if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
01396       // Be conservative.
01397       return false;
01398     SrcReg = MI.getOperand(1).getReg();
01399     DstReg = MI.getOperand(0).getReg();
01400     switch (MI.getOpcode()) {
01401     default: llvm_unreachable("Unreachable!");
01402     case X86::MOVSX16rr8:
01403     case X86::MOVZX16rr8:
01404     case X86::MOVSX32rr8:
01405     case X86::MOVZX32rr8:
01406     case X86::MOVSX64rr8:
01407     case X86::MOVZX64rr8:
01408       SubIdx = X86::sub_8bit;
01409       break;
01410     case X86::MOVSX32rr16:
01411     case X86::MOVZX32rr16:
01412     case X86::MOVSX64rr16:
01413     case X86::MOVZX64rr16:
01414       SubIdx = X86::sub_16bit;
01415       break;
01416     case X86::MOVSX64rr32:
01417     case X86::MOVZX64rr32:
01418       SubIdx = X86::sub_32bit;
01419       break;
01420     }
01421     return true;
01422   }
01423   }
01424   return false;
01425 }
01426 
01427 /// isFrameOperand - Return true and the FrameIndex if the specified
01428 /// operand and follow operands form a reference to the stack frame.
01429 bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op,
01430                                   int &FrameIndex) const {
01431   if (MI->getOperand(Op).isFI() && MI->getOperand(Op+1).isImm() &&
01432       MI->getOperand(Op+2).isReg() && MI->getOperand(Op+3).isImm() &&
01433       MI->getOperand(Op+1).getImm() == 1 &&
01434       MI->getOperand(Op+2).getReg() == 0 &&
01435       MI->getOperand(Op+3).getImm() == 0) {
01436     FrameIndex = MI->getOperand(Op).getIndex();
01437     return true;
01438   }
01439   return false;
01440 }
01441 
01442 static bool isFrameLoadOpcode(int Opcode) {
01443   switch (Opcode) {
01444   default:
01445     return false;
01446   case X86::MOV8rm:
01447   case X86::MOV16rm:
01448   case X86::MOV32rm:
01449   case X86::MOV64rm:
01450   case X86::LD_Fp64m:
01451   case X86::MOVSSrm:
01452   case X86::MOVSDrm:
01453   case X86::MOVAPSrm:
01454   case X86::MOVAPDrm:
01455   case X86::MOVDQArm:
01456   case X86::VMOVSSrm:
01457   case X86::VMOVSDrm:
01458   case X86::VMOVAPSrm:
01459   case X86::VMOVAPDrm:
01460   case X86::VMOVDQArm:
01461   case X86::VMOVAPSYrm:
01462   case X86::VMOVAPDYrm:
01463   case X86::VMOVDQAYrm:
01464   case X86::MMX_MOVD64rm:
01465   case X86::MMX_MOVQ64rm:
01466     return true;
01467   }
01468 }
01469 
01470 static bool isFrameStoreOpcode(int Opcode) {
01471   switch (Opcode) {
01472   default: break;
01473   case X86::MOV8mr:
01474   case X86::MOV16mr:
01475   case X86::MOV32mr:
01476   case X86::MOV64mr:
01477   case X86::ST_FpP64m:
01478   case X86::MOVSSmr:
01479   case X86::MOVSDmr:
01480   case X86::MOVAPSmr:
01481   case X86::MOVAPDmr:
01482   case X86::MOVDQAmr:
01483   case X86::VMOVSSmr:
01484   case X86::VMOVSDmr:
01485   case X86::VMOVAPSmr:
01486   case X86::VMOVAPDmr:
01487   case X86::VMOVDQAmr:
01488   case X86::VMOVAPSYmr:
01489   case X86::VMOVAPDYmr:
01490   case X86::VMOVDQAYmr:
01491   case X86::MMX_MOVD64mr:
01492   case X86::MMX_MOVQ64mr:
01493   case X86::MMX_MOVNTQmr:
01494     return true;
01495   }
01496   return false;
01497 }
01498 
01499 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
01500                                            int &FrameIndex) const {
01501   if (isFrameLoadOpcode(MI->getOpcode()))
01502     if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
01503       return MI->getOperand(0).getReg();
01504   return 0;
01505 }
01506 
01507 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
01508                                                  int &FrameIndex) const {
01509   if (isFrameLoadOpcode(MI->getOpcode())) {
01510     unsigned Reg;
01511     if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
01512       return Reg;
01513     // Check for post-frame index elimination operations
01514     const MachineMemOperand *Dummy;
01515     return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
01516   }
01517   return 0;
01518 }
01519 
01520 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
01521                                           int &FrameIndex) const {
01522   if (isFrameStoreOpcode(MI->getOpcode()))
01523     if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
01524         isFrameOperand(MI, 0, FrameIndex))
01525       return MI->getOperand(X86::AddrNumOperands).getReg();
01526   return 0;
01527 }
01528 
01529 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
01530                                                 int &FrameIndex) const {
01531   if (isFrameStoreOpcode(MI->getOpcode())) {
01532     unsigned Reg;
01533     if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
01534       return Reg;
01535     // Check for post-frame index elimination operations
01536     const MachineMemOperand *Dummy;
01537     return hasStoreToStackSlot(MI, Dummy, FrameIndex);
01538   }
01539   return 0;
01540 }
01541 
01542 /// regIsPICBase - Return true if register is PIC base (i.e.g defined by
01543 /// X86::MOVPC32r.
01544 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
01545   // Don't waste compile time scanning use-def chains of physregs.
01546   if (!TargetRegisterInfo::isVirtualRegister(BaseReg))
01547     return false;
01548   bool isPICBase = false;
01549   for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
01550          E = MRI.def_end(); I != E; ++I) {
01551     MachineInstr *DefMI = I.getOperand().getParent();
01552     if (DefMI->getOpcode() != X86::MOVPC32r)
01553       return false;
01554     assert(!isPICBase && "More than one PIC base?");
01555     isPICBase = true;
01556   }
01557   return isPICBase;
01558 }
01559 
01560 bool
01561 X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
01562                                                 AliasAnalysis *AA) const {
01563   switch (MI->getOpcode()) {
01564   default: break;
01565   case X86::MOV8rm:
01566   case X86::MOV16rm:
01567   case X86::MOV32rm:
01568   case X86::MOV64rm:
01569   case X86::LD_Fp64m:
01570   case X86::MOVSSrm:
01571   case X86::MOVSDrm:
01572   case X86::MOVAPSrm:
01573   case X86::MOVUPSrm:
01574   case X86::MOVAPDrm:
01575   case X86::MOVDQArm:
01576   case X86::MOVDQUrm:
01577   case X86::VMOVSSrm:
01578   case X86::VMOVSDrm:
01579   case X86::VMOVAPSrm:
01580   case X86::VMOVUPSrm:
01581   case X86::VMOVAPDrm:
01582   case X86::VMOVDQArm:
01583   case X86::VMOVDQUrm:
01584   case X86::VMOVAPSYrm:
01585   case X86::VMOVUPSYrm:
01586   case X86::VMOVAPDYrm:
01587   case X86::VMOVDQAYrm:
01588   case X86::VMOVDQUYrm:
01589   case X86::MMX_MOVD64rm:
01590   case X86::MMX_MOVQ64rm:
01591   case X86::FsVMOVAPSrm:
01592   case X86::FsVMOVAPDrm:
01593   case X86::FsMOVAPSrm:
01594   case X86::FsMOVAPDrm: {
01595     // Loads from constant pools are trivially rematerializable.
01596     if (MI->getOperand(1).isReg() &&
01597         MI->getOperand(2).isImm() &&
01598         MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
01599         MI->isInvariantLoad(AA)) {
01600       unsigned BaseReg = MI->getOperand(1).getReg();
01601       if (BaseReg == 0 || BaseReg == X86::RIP)
01602         return true;
01603       // Allow re-materialization of PIC load.
01604       if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal())
01605         return false;
01606       const MachineFunction &MF = *MI->getParent()->getParent();
01607       const MachineRegisterInfo &MRI = MF.getRegInfo();
01608       return regIsPICBase(BaseReg, MRI);
01609     }
01610     return false;
01611   }
01612 
01613   case X86::LEA32r:
01614   case X86::LEA64r: {
01615     if (MI->getOperand(2).isImm() &&
01616         MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
01617         !MI->getOperand(4).isReg()) {
01618       // lea fi#, lea GV, etc. are all rematerializable.
01619       if (!MI->getOperand(1).isReg())
01620         return true;
01621       unsigned BaseReg = MI->getOperand(1).getReg();
01622       if (BaseReg == 0)
01623         return true;
01624       // Allow re-materialization of lea PICBase + x.
01625       const MachineFunction &MF = *MI->getParent()->getParent();
01626       const MachineRegisterInfo &MRI = MF.getRegInfo();
01627       return regIsPICBase(BaseReg, MRI);
01628     }
01629     return false;
01630   }
01631   }
01632 
01633   // All other instructions marked M_REMATERIALIZABLE are always trivially
01634   // rematerializable.
01635   return true;
01636 }
01637 
01638 /// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that
01639 /// would clobber the EFLAGS condition register. Note the result may be
01640 /// conservative. If it cannot definitely determine the safety after visiting
01641 /// a few instructions in each direction it assumes it's not safe.
01642 static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
01643                                   MachineBasicBlock::iterator I) {
01644   MachineBasicBlock::iterator E = MBB.end();
01645 
01646   // For compile time consideration, if we are not able to determine the
01647   // safety after visiting 4 instructions in each direction, we will assume
01648   // it's not safe.
01649   MachineBasicBlock::iterator Iter = I;
01650   for (unsigned i = 0; Iter != E && i < 4; ++i) {
01651     bool SeenDef = false;
01652     for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
01653       MachineOperand &MO = Iter->getOperand(j);
01654       if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
01655         SeenDef = true;
01656       if (!MO.isReg())
01657         continue;
01658       if (MO.getReg() == X86::EFLAGS) {
01659         if (MO.isUse())
01660           return false;
01661         SeenDef = true;
01662       }
01663     }
01664 
01665     if (SeenDef)
01666       // This instruction defines EFLAGS, no need to look any further.
01667       return true;
01668     ++Iter;
01669     // Skip over DBG_VALUE.
01670     while (Iter != E && Iter->isDebugValue())
01671       ++Iter;
01672   }
01673 
01674   // It is safe to clobber EFLAGS at the end of a block of no successor has it
01675   // live in.
01676   if (Iter == E) {
01677     for (MachineBasicBlock::succ_iterator SI = MBB.succ_begin(),
01678            SE = MBB.succ_end(); SI != SE; ++SI)
01679       if ((*SI)->isLiveIn(X86::EFLAGS))
01680         return false;
01681     return true;
01682   }
01683 
01684   MachineBasicBlock::iterator B = MBB.begin();
01685   Iter = I;
01686   for (unsigned i = 0; i < 4; ++i) {
01687     // If we make it to the beginning of the block, it's safe to clobber
01688     // EFLAGS iff EFLAGS is not live-in.
01689     if (Iter == B)
01690       return !MBB.isLiveIn(X86::EFLAGS);
01691 
01692     --Iter;
01693     // Skip over DBG_VALUE.
01694     while (Iter != B && Iter->isDebugValue())
01695       --Iter;
01696 
01697     bool SawKill = false;
01698     for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
01699       MachineOperand &MO = Iter->getOperand(j);
01700       // A register mask may clobber EFLAGS, but we should still look for a
01701       // live EFLAGS def.
01702       if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
01703         SawKill = true;
01704       if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
01705         if (MO.isDef()) return MO.isDead();
01706         if (MO.isKill()) SawKill = true;
01707       }
01708     }
01709 
01710     if (SawKill)
01711       // This instruction kills EFLAGS and doesn't redefine it, so
01712       // there's no need to look further.
01713       return true;
01714   }
01715 
01716   // Conservative answer.
01717   return false;
01718 }
01719 
01720 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
01721                                  MachineBasicBlock::iterator I,
01722                                  unsigned DestReg, unsigned SubIdx,
01723                                  const MachineInstr *Orig,
01724                                  const TargetRegisterInfo &TRI) const {
01725   DebugLoc DL = Orig->getDebugLoc();
01726 
01727   // MOV32r0 etc. are implemented with xor which clobbers condition code.
01728   // Re-materialize them as movri instructions to avoid side effects.
01729   bool Clone = true;
01730   unsigned Opc = Orig->getOpcode();
01731   switch (Opc) {
01732   default: break;
01733   case X86::MOV8r0:
01734   case X86::MOV16r0:
01735   case X86::MOV32r0:
01736   case X86::MOV64r0: {
01737     if (!isSafeToClobberEFLAGS(MBB, I)) {
01738       switch (Opc) {
01739       default: llvm_unreachable("Unreachable!");
01740       case X86::MOV8r0:  Opc = X86::MOV8ri;  break;
01741       case X86::MOV16r0: Opc = X86::MOV16ri; break;
01742       case X86::MOV32r0: Opc = X86::MOV32ri; break;
01743       case X86::MOV64r0: Opc = X86::MOV64ri64i32; break;
01744       }
01745       Clone = false;
01746     }
01747     break;
01748   }
01749   }
01750 
01751   if (Clone) {
01752     MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
01753     MBB.insert(I, MI);
01754   } else {
01755     BuildMI(MBB, I, DL, get(Opc)).addOperand(Orig->getOperand(0)).addImm(0);
01756   }
01757 
01758   MachineInstr *NewMI = prior(I);
01759   NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
01760 }
01761 
01762 /// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
01763 /// is not marked dead.
01764 static bool hasLiveCondCodeDef(MachineInstr *MI) {
01765   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
01766     MachineOperand &MO = MI->getOperand(i);
01767     if (MO.isReg() && MO.isDef() &&
01768         MO.getReg() == X86::EFLAGS && !MO.isDead()) {
01769       return true;
01770     }
01771   }
01772   return false;
01773 }
01774 
01775 /// getTruncatedShiftCount - check whether the shift count for a machine operand
01776 /// is non-zero.
01777 inline static unsigned getTruncatedShiftCount(MachineInstr *MI,
01778                                               unsigned ShiftAmtOperandIdx) {
01779   // The shift count is six bits with the REX.W prefix and five bits without.
01780   unsigned ShiftCountMask = (MI->getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
01781   unsigned Imm = MI->getOperand(ShiftAmtOperandIdx).getImm();
01782   return Imm & ShiftCountMask;
01783 }
01784 
01785 /// isTruncatedShiftCountForLEA - check whether the given shift count is appropriate
01786 /// can be represented by a LEA instruction.
01787 inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
01788   // Left shift instructions can be transformed into load-effective-address
01789   // instructions if we can encode them appropriately.
01790   // A LEA instruction utilizes a SIB byte to encode it's scale factor.
01791   // The SIB.scale field is two bits wide which means that we can encode any
01792   // shift amount less than 4.
01793   return ShAmt < 4 && ShAmt > 0;
01794 }
01795 
01796 /// convertToThreeAddressWithLEA - Helper for convertToThreeAddress when
01797 /// 16-bit LEA is disabled, use 32-bit LEA to form 3-address code by promoting
01798 /// to a 32-bit superregister and then truncating back down to a 16-bit
01799 /// subregister.
01800 MachineInstr *
01801 X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
01802                                            MachineFunction::iterator &MFI,
01803                                            MachineBasicBlock::iterator &MBBI,
01804                                            LiveVariables *LV) const {
01805   MachineInstr *MI = MBBI;
01806   unsigned Dest = MI->getOperand(0).getReg();
01807   unsigned Src = MI->getOperand(1).getReg();
01808   bool isDead = MI->getOperand(0).isDead();
01809   bool isKill = MI->getOperand(1).isKill();
01810 
01811   unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit()
01812     ? X86::LEA64_32r : X86::LEA32r;
01813   MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
01814   unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
01815   unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
01816 
01817   // Build and insert into an implicit UNDEF value. This is OK because
01818   // well be shifting and then extracting the lower 16-bits.
01819   // This has the potential to cause partial register stall. e.g.
01820   //   movw    (%rbp,%rcx,2), %dx
01821   //   leal    -65(%rdx), %esi
01822   // But testing has shown this *does* help performance in 64-bit mode (at
01823   // least on modern x86 machines).
01824   BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
01825   MachineInstr *InsMI =
01826     BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
01827     .addReg(leaInReg, RegState::Define, X86::sub_16bit)
01828     .addReg(Src, getKillRegState(isKill));
01829 
01830   MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(),
01831                                     get(Opc), leaOutReg);
01832   switch (MIOpc) {
01833   default: llvm_unreachable("Unreachable!");
01834   case X86::SHL16ri: {
01835     unsigned ShAmt = MI->getOperand(2).getImm();
01836     MIB.addReg(0).addImm(1 << ShAmt)
01837        .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
01838     break;
01839   }
01840   case X86::INC16r:
01841   case X86::INC64_16r:
01842     addRegOffset(MIB, leaInReg, true, 1);
01843     break;
01844   case X86::DEC16r:
01845   case X86::DEC64_16r:
01846     addRegOffset(MIB, leaInReg, true, -1);
01847     break;
01848   case X86::ADD16ri:
01849   case X86::ADD16ri8:
01850   case X86::ADD16ri_DB:
01851   case X86::ADD16ri8_DB:
01852     addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
01853     break;
01854   case X86::ADD16rr:
01855   case X86::ADD16rr_DB: {
01856     unsigned Src2 = MI->getOperand(2).getReg();
01857     bool isKill2 = MI->getOperand(2).isKill();
01858     unsigned leaInReg2 = 0;
01859     MachineInstr *InsMI2 = 0;
01860     if (Src == Src2) {
01861       // ADD16rr %reg1028<kill>, %reg1028
01862       // just a single insert_subreg.
01863       addRegReg(MIB, leaInReg, true, leaInReg, false);
01864     } else {
01865       leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
01866       // Build and insert into an implicit UNDEF value. This is OK because
01867       // well be shifting and then extracting the lower 16-bits.
01868       BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF),leaInReg2);
01869       InsMI2 =
01870         BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(TargetOpcode::COPY))
01871         .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
01872         .addReg(Src2, getKillRegState(isKill2));
01873       addRegReg(MIB, leaInReg, true, leaInReg2, true);
01874     }
01875     if (LV && isKill2 && InsMI2)
01876       LV->replaceKillInstruction(Src2, MI, InsMI2);
01877     break;
01878   }
01879   }
01880 
01881   MachineInstr *NewMI = MIB;
01882   MachineInstr *ExtMI =
01883     BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
01884     .addReg(Dest, RegState::Define | getDeadRegState(isDead))
01885     .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
01886 
01887   if (LV) {
01888     // Update live variables
01889     LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
01890     LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
01891     if (isKill)
01892       LV->replaceKillInstruction(Src, MI, InsMI);
01893     if (isDead)
01894       LV->replaceKillInstruction(Dest, MI, ExtMI);
01895   }
01896 
01897   return ExtMI;
01898 }
01899 
01900 /// convertToThreeAddress - This method must be implemented by targets that
01901 /// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
01902 /// may be able to convert a two-address instruction into a true
01903 /// three-address instruction on demand.  This allows the X86 target (for
01904 /// example) to convert ADD and SHL instructions into LEA instructions if they
01905 /// would require register copies due to two-addressness.
01906 ///
01907 /// This method returns a null pointer if the transformation cannot be
01908 /// performed, otherwise it returns the new instruction.
01909 ///
01910 MachineInstr *
01911 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
01912                                     MachineBasicBlock::iterator &MBBI,
01913                                     LiveVariables *LV) const {
01914   MachineInstr *MI = MBBI;
01915 
01916   // The following opcodes also sets the condition code register(s). Only
01917   // convert them to equivalent lea if the condition code register def's
01918   // are dead!
01919   if (hasLiveCondCodeDef(MI))
01920     return 0;
01921 
01922   MachineFunction &MF = *MI->getParent()->getParent();
01923   // All instructions input are two-addr instructions.  Get the known operands.
01924   const MachineOperand &Dest = MI->getOperand(0);
01925   const MachineOperand &Src = MI->getOperand(1);
01926 
01927   MachineInstr *NewMI = NULL;
01928   // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's.  When
01929   // we have better subtarget support, enable the 16-bit LEA generation here.
01930   // 16-bit LEA is also slow on Core2.
01931   bool DisableLEA16 = true;
01932   bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
01933 
01934   unsigned MIOpc = MI->getOpcode();
01935   switch (MIOpc) {
01936   case X86::SHUFPSrri: {
01937     assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
01938     if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
01939 
01940     unsigned B = MI->getOperand(1).getReg();
01941     unsigned C = MI->getOperand(2).getReg();
01942     if (B != C) return 0;
01943     unsigned M = MI->getOperand(3).getImm();
01944     NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
01945       .addOperand(Dest).addOperand(Src).addImm(M);
01946     break;
01947   }
01948   case X86::SHUFPDrri: {
01949     assert(MI->getNumOperands() == 4 && "Unknown shufpd instruction!");
01950     if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
01951 
01952     unsigned B = MI->getOperand(1).getReg();
01953     unsigned C = MI->getOperand(2).getReg();
01954     if (B != C) return 0;
01955     unsigned M = MI->getOperand(3).getImm();
01956 
01957     // Convert to PSHUFD mask.
01958     M = ((M & 1) << 1) | ((M & 1) << 3) | ((M & 2) << 4) | ((M & 2) << 6)| 0x44;
01959 
01960     NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
01961       .addOperand(Dest).addOperand(Src).addImm(M);
01962     break;
01963   }
01964   case X86::SHL64ri: {
01965     assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
01966     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
01967     if (!isTruncatedShiftCountForLEA(ShAmt)) return 0;
01968 
01969     // LEA can't handle RSP.
01970     if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
01971         !MF.getRegInfo().constrainRegClass(Src.getReg(),
01972                                            &X86::GR64_NOSPRegClass))
01973       return 0;
01974 
01975     NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
01976       .addOperand(Dest)
01977       .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
01978     break;
01979   }
01980   case X86::SHL32ri: {
01981     assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
01982     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
01983     if (!isTruncatedShiftCountForLEA(ShAmt)) return 0;
01984 
01985     // LEA can't handle ESP.
01986     if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
01987         !MF.getRegInfo().constrainRegClass(Src.getReg(),
01988                                            &X86::GR32_NOSPRegClass))
01989       return 0;
01990 
01991     unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
01992     NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc))
01993       .addOperand(Dest)
01994       .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
01995     break;
01996   }
01997   case X86::SHL16ri: {
01998     assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
01999     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
02000     if (!isTruncatedShiftCountForLEA(ShAmt)) return 0;
02001 
02002     if (DisableLEA16)
02003       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
02004     NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
02005       .addOperand(Dest)
02006       .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
02007     break;
02008   }
02009   default: {
02010 
02011     switch (MIOpc) {
02012     default: return 0;
02013     case X86::INC64r:
02014     case X86::INC32r:
02015     case X86::INC64_32r: {
02016       assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
02017       unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
02018         : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
02019       const TargetRegisterClass *RC = MIOpc == X86::INC64r ?
02020         (const TargetRegisterClass*)&X86::GR64_NOSPRegClass :
02021         (const TargetRegisterClass*)&X86::GR32_NOSPRegClass;
02022 
02023       // LEA can't handle RSP.
02024       if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
02025           !MF.getRegInfo().constrainRegClass(Src.getReg(), RC))
02026         return 0;
02027 
02028       NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
02029                         .addOperand(Dest).addOperand(Src), 1);
02030       break;
02031     }
02032     case X86::INC16r:
02033     case X86::INC64_16r:
02034       if (DisableLEA16)
02035         return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
02036       assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
02037       NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
02038                         .addOperand(Dest).addOperand(Src), 1);
02039       break;
02040     case X86::DEC64r:
02041     case X86::DEC32r:
02042     case X86::DEC64_32r: {
02043       assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
02044       unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
02045         : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
02046       const TargetRegisterClass *RC = MIOpc == X86::DEC64r ?
02047         (const TargetRegisterClass*)&X86::GR64_NOSPRegClass :
02048         (const TargetRegisterClass*)&X86::GR32_NOSPRegClass;
02049       // LEA can't handle RSP.
02050       if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
02051           !MF.getRegInfo().constrainRegClass(Src.getReg(), RC))
02052         return 0;
02053 
02054       NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
02055                         .addOperand(Dest).addOperand(Src), -1);
02056       break;
02057     }
02058     case X86::DEC16r:
02059     case X86::DEC64_16r:
02060       if (DisableLEA16)
02061         return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
02062       assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
02063       NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
02064                         .addOperand(Dest).addOperand(Src), -1);
02065       break;
02066     case X86::ADD64rr:
02067     case X86::ADD64rr_DB:
02068     case X86::ADD32rr:
02069     case X86::ADD32rr_DB: {
02070       assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
02071       unsigned Opc;
02072       const TargetRegisterClass *RC;
02073       if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB) {
02074         Opc = X86::LEA64r;
02075         RC = &X86::GR64_NOSPRegClass;
02076       } else {
02077         Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
02078         RC = &X86::GR32_NOSPRegClass;
02079       }
02080 
02081 
02082       unsigned Src2 = MI->getOperand(2).getReg();
02083       bool isKill2 = MI->getOperand(2).isKill();
02084 
02085       // LEA can't handle RSP.
02086       if (TargetRegisterInfo::isVirtualRegister(Src2) &&
02087           !MF.getRegInfo().constrainRegClass(Src2, RC))
02088         return 0;
02089 
02090       NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(Opc))
02091                         .addOperand(Dest),
02092                         Src.getReg(), Src.isKill(), Src2, isKill2);
02093 
02094       // Preserve undefness of the operands.
02095       bool isUndef = MI->getOperand(1).isUndef();
02096       bool isUndef2 = MI->getOperand(2).isUndef();
02097       NewMI->getOperand(1).setIsUndef(isUndef);
02098       NewMI->getOperand(3).setIsUndef(isUndef2);
02099 
02100       if (LV && isKill2)
02101         LV->replaceKillInstruction(Src2, MI, NewMI);
02102       break;
02103     }
02104     case X86::ADD16rr:
02105     case X86::ADD16rr_DB: {
02106       if (DisableLEA16)
02107         return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
02108       assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
02109       unsigned Src2 = MI->getOperand(2).getReg();
02110       bool isKill2 = MI->getOperand(2).isKill();
02111       NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
02112                         .addOperand(Dest),
02113                         Src.getReg(), Src.isKill(), Src2, isKill2);
02114 
02115       // Preserve undefness of the operands.
02116       bool isUndef = MI->getOperand(1).isUndef();
02117       bool isUndef2 = MI->getOperand(2).isUndef();
02118       NewMI->getOperand(1).setIsUndef(isUndef);
02119       NewMI->getOperand(3).setIsUndef(isUndef2);
02120 
02121       if (LV && isKill2)
02122         LV->replaceKillInstruction(Src2, MI, NewMI);
02123       break;
02124     }
02125     case X86::ADD64ri32:
02126     case X86::ADD64ri8:
02127     case X86::ADD64ri32_DB:
02128     case X86::ADD64ri8_DB:
02129       assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
02130       NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
02131                         .addOperand(Dest).addOperand(Src),
02132                         MI->getOperand(2).getImm());
02133       break;
02134     case X86::ADD32ri:
02135     case X86::ADD32ri8:
02136     case X86::ADD32ri_DB:
02137     case X86::ADD32ri8_DB: {
02138       assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
02139       unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
02140       NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
02141                         .addOperand(Dest).addOperand(Src),
02142                         MI->getOperand(2).getImm());
02143       break;
02144     }
02145     case X86::ADD16ri:
02146     case X86::ADD16ri8:
02147     case X86::ADD16ri_DB:
02148     case X86::ADD16ri8_DB:
02149       if (DisableLEA16)
02150         return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
02151       assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
02152       NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
02153                         .addOperand(Dest).addOperand(Src),
02154                         MI->getOperand(2).getImm());
02155       break;
02156     }
02157   }
02158   }
02159 
02160   if (!NewMI) return 0;
02161 
02162   if (LV) {  // Update live variables
02163     if (Src.isKill())
02164       LV->replaceKillInstruction(Src.getReg(), MI, NewMI);
02165     if (Dest.isDead())
02166       LV->replaceKillInstruction(Dest.getReg(), MI, NewMI);
02167   }
02168 
02169   MFI->insert(MBBI, NewMI);          // Insert the new inst
02170   return NewMI;
02171 }
02172 
02173 /// commuteInstruction - We have a few instructions that must be hacked on to
02174 /// commute them.
02175 ///
02176 MachineInstr *
02177 X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
02178   switch (MI->getOpcode()) {
02179   case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
02180   case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
02181   case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
02182   case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
02183   case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
02184   case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
02185     unsigned Opc;
02186     unsigned Size;
02187     switch (MI->getOpcode()) {
02188     default: llvm_unreachable("Unreachable!");
02189     case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
02190     case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
02191     case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
02192     case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
02193     case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
02194     case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
02195     }
02196     unsigned Amt = MI->getOperand(3).getImm();
02197     if (NewMI) {
02198       MachineFunction &MF = *MI->getParent()->getParent();
02199       MI = MF.CloneMachineInstr(MI);
02200       NewMI = false;
02201     }
02202     MI->setDesc(get(Opc));
02203     MI->getOperand(3).setImm(Size-Amt);
02204     return TargetInstrInfo::commuteInstruction(MI, NewMI);
02205   }
02206   case X86::CMOVB16rr:  case X86::CMOVB32rr:  case X86::CMOVB64rr:
02207   case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr:
02208   case X86::CMOVE16rr:  case X86::CMOVE32rr:  case X86::CMOVE64rr:
02209   case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr:
02210   case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr:
02211   case X86::CMOVA16rr:  case X86::CMOVA32rr:  case X86::CMOVA64rr:
02212   case X86::CMOVL16rr:  case X86::CMOVL32rr:  case X86::CMOVL64rr:
02213   case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr:
02214   case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr:
02215   case X86::CMOVG16rr:  case X86::CMOVG32rr:  case X86::CMOVG64rr:
02216   case X86::CMOVS16rr:  case X86::CMOVS32rr:  case X86::CMOVS64rr:
02217   case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr:
02218   case X86::CMOVP16rr:  case X86::CMOVP32rr:  case X86::CMOVP64rr:
02219   case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr:
02220   case X86::CMOVO16rr:  case X86::CMOVO32rr:  case X86::CMOVO64rr:
02221   case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: {
02222     unsigned Opc;
02223     switch (MI->getOpcode()) {
02224     default: llvm_unreachable("Unreachable!");
02225     case X86::CMOVB16rr:  Opc = X86::CMOVAE16rr; break;
02226     case X86::CMOVB32rr:  Opc = X86::CMOVAE32rr; break;
02227     case X86::CMOVB64rr:  Opc = X86::CMOVAE64rr; break;
02228     case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
02229     case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
02230     case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
02231     case X86::CMOVE16rr:  Opc = X86::CMOVNE16rr; break;
02232     case X86::CMOVE32rr:  Opc = X86::CMOVNE32rr; break;
02233     case X86::CMOVE64rr:  Opc = X86::CMOVNE64rr; break;
02234     case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
02235     case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
02236     case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
02237     case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
02238     case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
02239     case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
02240     case X86::CMOVA16rr:  Opc = X86::CMOVBE16rr; break;
02241     case X86::CMOVA32rr:  Opc = X86::CMOVBE32rr; break;
02242     case X86::CMOVA64rr:  Opc = X86::CMOVBE64rr; break;
02243     case X86::CMOVL16rr:  Opc = X86::CMOVGE16rr; break;
02244     case X86::CMOVL32rr:  Opc = X86::CMOVGE32rr; break;
02245     case X86::CMOVL64rr:  Opc = X86::CMOVGE64rr; break;
02246     case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
02247     case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
02248     case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
02249     case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
02250     case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
02251     case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
02252     case X86::CMOVG16rr:  Opc = X86::CMOVLE16rr; break;
02253     case X86::CMOVG32rr:  Opc = X86::CMOVLE32rr; break;
02254     case X86::CMOVG64rr:  Opc = X86::CMOVLE64rr; break;
02255     case X86::CMOVS16rr:  Opc = X86::CMOVNS16rr; break;
02256     case X86::CMOVS32rr:  Opc = X86::CMOVNS32rr; break;
02257     case X86::CMOVS64rr:  Opc = X86::CMOVNS64rr; break;
02258     case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
02259     case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
02260     case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
02261     case X86::CMOVP16rr:  Opc = X86::CMOVNP16rr; break;
02262     case X86::CMOVP32rr:  Opc = X86::CMOVNP32rr; break;
02263     case X86::CMOVP64rr:  Opc = X86::CMOVNP64rr; break;
02264     case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
02265     case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
02266     case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
02267     case X86::CMOVO16rr:  Opc = X86::CMOVNO16rr; break;
02268     case X86::CMOVO32rr:  Opc = X86::CMOVNO32rr; break;
02269     case X86::CMOVO64rr:  Opc = X86::CMOVNO64rr; break;
02270     case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
02271     case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
02272     case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
02273     }
02274     if (NewMI) {
02275       MachineFunction &MF = *MI->getParent()->getParent();
02276       MI = MF.CloneMachineInstr(MI);
02277       NewMI = false;
02278     }
02279     MI->setDesc(get(Opc));
02280     // Fallthrough intended.
02281   }
02282   default:
02283     return TargetInstrInfo::commuteInstruction(MI, NewMI);
02284   }
02285 }
02286 
02287 static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) {
02288   switch (BrOpc) {
02289   default: return X86::COND_INVALID;
02290   case X86::JE_4:  return X86::COND_E;
02291   case X86::JNE_4: return X86::COND_NE;
02292   case X86::JL_4:  return X86::COND_L;
02293   case X86::JLE_4: return X86::COND_LE;
02294   case X86::JG_4:  return X86::COND_G;
02295   case X86::JGE_4: return X86::COND_GE;
02296   case X86::JB_4:  return X86::COND_B;
02297   case X86::JBE_4: return X86::COND_BE;
02298   case X86::JA_4:  return X86::COND_A;
02299   case X86::JAE_4: return X86::COND_AE;
02300   case X86::JS_4:  return X86::COND_S;
02301   case X86::JNS_4: return X86::COND_NS;
02302   case X86::JP_4:  return X86::COND_P;
02303   case X86::JNP_4: return X86::COND_NP;
02304   case X86::JO_4:  return X86::COND_O;
02305   case X86::JNO_4: return X86::COND_NO;
02306   }
02307 }
02308 
02309 /// getCondFromSETOpc - return condition code of a SET opcode.
02310 static X86::CondCode getCondFromSETOpc(unsigned Opc) {
02311   switch (Opc) {
02312   default: return X86::COND_INVALID;
02313   case X86::SETAr:  case X86::SETAm:  return X86::COND_A;
02314   case X86::SETAEr: case X86::SETAEm: return X86::COND_AE;
02315   case X86::SETBr:  case X86::SETBm:  return X86::COND_B;
02316   case X86::SETBEr: case X86::SETBEm: return X86::COND_BE;
02317   case X86::SETEr:  case X86::SETEm:  return X86::COND_E;
02318   case X86::SETGr:  case X86::SETGm:  return X86::COND_G;
02319   case X86::SETGEr: case X86::SETGEm: return X86::COND_GE;
02320   case X86::SETLr:  case X86::SETLm:  return X86::COND_L;
02321   case X86::SETLEr: case X86::SETLEm: return X86::COND_LE;
02322   case X86::SETNEr: case X86::SETNEm: return X86::COND_NE;
02323   case X86::SETNOr: case X86::SETNOm: return X86::COND_NO;
02324   case X86::SETNPr: case X86::SETNPm: return X86::COND_NP;
02325   case X86::SETNSr: case X86::SETNSm: return X86::COND_NS;
02326   case X86::SETOr:  case X86::SETOm:  return X86::COND_O;
02327   case X86::SETPr:  case X86::SETPm:  return X86::COND_P;
02328   case X86::SETSr:  case X86::SETSm:  return X86::COND_S;
02329   }
02330 }
02331 
02332 /// getCondFromCmovOpc - return condition code of a CMov opcode.
02333 X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) {
02334   switch (Opc) {
02335   default: return X86::COND_INVALID;
02336   case X86::CMOVA16rm:  case X86::CMOVA16rr:  case X86::CMOVA32rm:
02337   case X86::CMOVA32rr:  case X86::CMOVA64rm:  case X86::CMOVA64rr:
02338     return X86::COND_A;
02339   case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm:
02340   case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr:
02341     return X86::COND_AE;
02342   case X86::CMOVB16rm:  case X86::CMOVB16rr:  case X86::CMOVB32rm:
02343   case X86::CMOVB32rr:  case X86::CMOVB64rm:  case X86::CMOVB64rr:
02344     return X86::COND_B;
02345   case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm:
02346   case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr:
02347     return X86::COND_BE;
02348   case X86::CMOVE16rm:  case X86::CMOVE16rr:  case X86::CMOVE32rm:
02349   case X86::CMOVE32rr:  case X86::CMOVE64rm:  case X86::CMOVE64rr:
02350     return X86::COND_E;
02351   case X86::CMOVG16rm:  case X86::CMOVG16rr:  case X86::CMOVG32rm:
02352   case X86::CMOVG32rr:  case X86::CMOVG64rm:  case X86::CMOVG64rr:
02353     return X86::COND_G;
02354   case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm:
02355   case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr:
02356     return X86::COND_GE;
02357   case X86::CMOVL16rm:  case X86::CMOVL16rr:  case X86::CMOVL32rm:
02358   case X86::CMOVL32rr:  case X86::CMOVL64rm:  case X86::CMOVL64rr:
02359     return X86::COND_L;
02360   case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm:
02361   case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr:
02362     return X86::COND_LE;
02363   case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm:
02364   case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr:
02365     return X86::COND_NE;
02366   case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm:
02367   case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr:
02368     return X86::COND_NO;
02369   case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm:
02370   case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr:
02371     return X86::COND_NP;
02372   case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm:
02373   case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr:
02374     return X86::COND_NS;
02375   case X86::CMOVO16rm:  case X86::CMOVO16rr:  case X86::CMOVO32rm:
02376   case X86::CMOVO32rr:  case X86::CMOVO64rm:  case X86::CMOVO64rr:
02377     return X86::COND_O;
02378   case X86::CMOVP16rm:  case X86::CMOVP16rr:  case X86::CMOVP32rm:
02379   case X86::CMOVP32rr:  case X86::CMOVP64rm:  case X86::CMOVP64rr:
02380     return X86::COND_P;
02381   case X86::CMOVS16rm:  case X86::CMOVS16rr:  case X86::CMOVS32rm:
02382   case X86::CMOVS32rr:  case X86::CMOVS64rm:  case X86::CMOVS64rr:
02383     return X86::COND_S;
02384   }
02385 }
02386 
02387 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
02388   switch (CC) {
02389   default: llvm_unreachable("Illegal condition code!");
02390   case X86::COND_E:  return X86::JE_4;
02391   case X86::COND_NE: return X86::JNE_4;
02392   case X86::COND_L:  return X86::JL_4;
02393   case X86::COND_LE: return X86::JLE_4;
02394   case X86::COND_G:  return X86::JG_4;
02395   case X86::COND_GE: return X86::JGE_4;
02396   case X86::COND_B:  return X86::JB_4;
02397   case X86::COND_BE: return X86::JBE_4;
02398   case X86::COND_A:  return X86::JA_4;
02399   case X86::COND_AE: return X86::JAE_4;
02400   case X86::COND_S:  return X86::JS_4;
02401   case X86::COND_NS: return X86::JNS_4;
02402   case X86::COND_P:  return X86::JP_4;
02403   case X86::COND_NP: return X86::JNP_4;
02404   case X86::COND_O:  return X86::JO_4;
02405   case X86::COND_NO: return X86::JNO_4;
02406   }
02407 }
02408 
02409 /// GetOppositeBranchCondition - Return the inverse of the specified condition,
02410 /// e.g. turning COND_E to COND_NE.
02411 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
02412   switch (CC) {
02413   default: llvm_unreachable("Illegal condition code!");
02414   case X86::COND_E:  return X86::COND_NE;
02415   case X86::COND_NE: return X86::COND_E;
02416   case X86::COND_L:  return X86::COND_GE;
02417   case X86::COND_LE: return X86::COND_G;
02418   case X86::COND_G:  return X86::COND_LE;
02419   case X86::COND_GE: return X86::COND_L;
02420   case X86::COND_B:  return X86::COND_AE;
02421   case X86::COND_BE: return X86::COND_A;
02422   case X86::COND_A:  return X86::COND_BE;
02423   case X86::COND_AE: return X86::COND_B;
02424   case X86::COND_S:  return X86::COND_NS;
02425   case X86::COND_NS: return X86::COND_S;
02426   case X86::COND_P:  return X86::COND_NP;
02427   case X86::COND_NP: return X86::COND_P;
02428   case X86::COND_O:  return X86::COND_NO;
02429   case X86::COND_NO: return X86::COND_O;
02430   }
02431 }
02432 
02433 /// getSwappedCondition - assume the flags are set by MI(a,b), return
02434 /// the condition code if we modify the instructions such that flags are
02435 /// set by MI(b,a).
02436 static X86::CondCode getSwappedCondition(X86::CondCode CC) {
02437   switch (CC) {
02438   default: return X86::COND_INVALID;
02439   case X86::COND_E:  return X86::COND_E;
02440   case X86::COND_NE: return X86::COND_NE;
02441   case X86::COND_L:  return X86::COND_G;
02442   case X86::COND_LE: return X86::COND_GE;
02443   case X86::COND_G:  return X86::COND_L;
02444   case X86::COND_GE: return X86::COND_LE;
02445   case X86::COND_B:  return X86::COND_A;
02446   case X86::COND_BE: return X86::COND_AE;
02447   case X86::COND_A:  return X86::COND_B;
02448   case X86::COND_AE: return X86::COND_BE;
02449   }
02450 }
02451 
02452 /// getSETFromCond - Return a set opcode for the given condition and
02453 /// whether it has memory operand.
02454 static unsigned getSETFromCond(X86::CondCode CC,
02455                                bool HasMemoryOperand) {
02456   static const uint16_t Opc[16][2] = {
02457     { X86::SETAr,  X86::SETAm  },
02458     { X86::SETAEr, X86::SETAEm },
02459     { X86::SETBr,  X86::SETBm  },
02460     { X86::SETBEr, X86::SETBEm },
02461     { X86::SETEr,  X86::SETEm  },
02462     { X86::SETGr,  X86::SETGm  },
02463     { X86::SETGEr, X86::SETGEm },
02464     { X86::SETLr,  X86::SETLm  },
02465     { X86::SETLEr, X86::SETLEm },
02466     { X86::SETNEr, X86::SETNEm },
02467     { X86::SETNOr, X86::SETNOm },
02468     { X86::SETNPr, X86::SETNPm },
02469     { X86::SETNSr, X86::SETNSm },
02470     { X86::SETOr,  X86::SETOm  },
02471     { X86::SETPr,  X86::SETPm  },
02472     { X86::SETSr,  X86::SETSm  }
02473   };
02474 
02475   assert(CC < 16 && "Can only handle standard cond codes");
02476   return Opc[CC][HasMemoryOperand ? 1 : 0];
02477 }
02478 
02479 /// getCMovFromCond - Return a cmov opcode for the given condition,
02480 /// register size in bytes, and operand type.
02481 static unsigned getCMovFromCond(X86::CondCode CC, unsigned RegBytes,
02482                                 bool HasMemoryOperand) {
02483   static const uint16_t Opc[32][3] = {
02484     { X86::CMOVA16rr,  X86::CMOVA32rr,  X86::CMOVA64rr  },
02485     { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr },
02486     { X86::CMOVB16rr,  X86::CMOVB32rr,  X86::CMOVB64rr  },
02487     { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr },
02488     { X86::CMOVE16rr,  X86::CMOVE32rr,  X86::CMOVE64rr  },
02489     { X86::CMOVG16rr,  X86::CMOVG32rr,  X86::CMOVG64rr  },
02490     { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr },
02491     { X86::CMOVL16rr,  X86::CMOVL32rr,  X86::CMOVL64rr  },
02492     { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr },
02493     { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr },
02494     { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr },
02495     { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr },
02496     { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr },
02497     { X86::CMOVO16rr,  X86::CMOVO32rr,  X86::CMOVO64rr  },
02498     { X86::CMOVP16rr,  X86::CMOVP32rr,  X86::CMOVP64rr  },
02499     { X86::CMOVS16rr,  X86::CMOVS32rr,  X86::CMOVS64rr  },
02500     { X86::CMOVA16rm,  X86::CMOVA32rm,  X86::CMOVA64rm  },
02501     { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm },
02502     { X86::CMOVB16rm,  X86::CMOVB32rm,  X86::CMOVB64rm  },
02503     { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm },
02504     { X86::CMOVE16rm,  X86::CMOVE32rm,  X86::CMOVE64rm  },
02505     { X86::CMOVG16rm,  X86::CMOVG32rm,  X86::CMOVG64rm  },
02506     { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm },
02507     { X86::CMOVL16rm,  X86::CMOVL32rm,  X86::CMOVL64rm  },
02508     { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm },
02509     { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm },
02510     { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm },
02511     { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm },
02512     { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm },
02513     { X86::CMOVO16rm,  X86::CMOVO32rm,  X86::CMOVO64rm  },
02514     { X86::CMOVP16rm,  X86::CMOVP32rm,  X86::CMOVP64rm  },
02515     { X86::CMOVS16rm,  X86::CMOVS32rm,  X86::CMOVS64rm  }
02516   };
02517 
02518   assert(CC < 16 && "Can only handle standard cond codes");
02519   unsigned Idx = HasMemoryOperand ? 16+CC : CC;
02520   switch(RegBytes) {
02521   default: llvm_unreachable("Illegal register size!");
02522   case 2: return Opc[Idx][0];
02523   case 4: return Opc[Idx][1];
02524   case 8: return Opc[Idx][2];
02525   }
02526 }
02527 
02528 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
02529   if (!MI->isTerminator()) return false;
02530 
02531   // Conditional branch is a special case.
02532   if (MI->isBranch() && !MI->isBarrier())
02533     return true;
02534   if (!MI->isPredicable())
02535     return true;
02536   return !isPredicated(MI);
02537 }
02538 
02539 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
02540                                  MachineBasicBlock *&TBB,
02541                                  MachineBasicBlock *&FBB,
02542                                  SmallVectorImpl<MachineOperand> &Cond,
02543                                  bool AllowModify) const {
02544   // Start from the bottom of the block and work up, examining the
02545   // terminator instructions.
02546   MachineBasicBlock::iterator I = MBB.end();
02547   MachineBasicBlock::iterator UnCondBrIter = MBB.end();
02548   while (I != MBB.begin()) {
02549     --I;
02550     if (I->isDebugValue())
02551       continue;
02552 
02553     // Working from the bottom, when we see a non-terminator instruction, we're
02554     // done.
02555     if (!isUnpredicatedTerminator(I))
02556       break;
02557 
02558     // A terminator that isn't a branch can't easily be handled by this
02559     // analysis.
02560     if (!I->isBranch())
02561       return true;
02562 
02563     // Handle unconditional branches.
02564     if (I->getOpcode() == X86::JMP_4) {
02565       UnCondBrIter = I;
02566 
02567       if (!AllowModify) {
02568         TBB = I->getOperand(0).getMBB();
02569         continue;
02570       }
02571 
02572       // If the block has any instructions after a JMP, delete them.
02573       while (llvm::next(I) != MBB.end())
02574         llvm::next(I)->eraseFromParent();
02575 
02576       Cond.clear();
02577       FBB = 0;
02578 
02579       // Delete the JMP if it's equivalent to a fall-through.
02580       if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
02581         TBB = 0;
02582         I->eraseFromParent();
02583         I = MBB.end();
02584         UnCondBrIter = MBB.end();
02585         continue;
02586       }
02587 
02588       // TBB is used to indicate the unconditional destination.
02589       TBB = I->getOperand(0).getMBB();
02590       continue;
02591     }
02592 
02593     // Handle conditional branches.
02594     X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode());
02595     if (BranchCode == X86::COND_INVALID)
02596       return true;  // Can't handle indirect branch.
02597 
02598     // Working from the bottom, handle the first conditional branch.
02599     if (Cond.empty()) {
02600       MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
02601       if (AllowModify && UnCondBrIter != MBB.end() &&
02602           MBB.isLayoutSuccessor(TargetBB)) {
02603         // If we can modify the code and it ends in something like:
02604         //
02605         //     jCC L1
02606         //     jmp L2
02607         //   L1:
02608         //     ...
02609         //   L2:
02610         //
02611         // Then we can change this to:
02612         //
02613         //     jnCC L2
02614         //   L1:
02615         //     ...
02616         //   L2:
02617         //
02618         // Which is a bit more efficient.
02619         // We conditionally jump to the fall-through block.
02620         BranchCode = GetOppositeBranchCondition(BranchCode);
02621         unsigned JNCC = GetCondBranchFromCond(BranchCode);
02622         MachineBasicBlock::iterator OldInst = I;
02623 
02624         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
02625           .addMBB(UnCondBrIter->getOperand(0).getMBB());
02626         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_4))
02627           .addMBB(TargetBB);
02628 
02629         OldInst->eraseFromParent();
02630         UnCondBrIter->eraseFromParent();
02631 
02632         // Restart the analysis.
02633         UnCondBrIter = MBB.end();
02634         I = MBB.end();
02635         continue;
02636       }
02637 
02638       FBB = TBB;
02639       TBB = I->getOperand(0).getMBB();
02640       Cond.push_back(MachineOperand::CreateImm(BranchCode));
02641       continue;
02642     }
02643 
02644     // Handle subsequent conditional branches. Only handle the case where all
02645     // conditional branches branch to the same destination and their condition
02646     // opcodes fit one of the special multi-branch idioms.
02647     assert(Cond.size() == 1);
02648     assert(TBB);
02649 
02650     // Only handle the case where all conditional branches branch to the same
02651     // destination.
02652     if (TBB != I->getOperand(0).getMBB())
02653       return true;
02654 
02655     // If the conditions are the same, we can leave them alone.
02656     X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
02657     if (OldBranchCode == BranchCode)
02658       continue;
02659 
02660     // If they differ, see if they fit one of the known patterns. Theoretically,
02661     // we could handle more patterns here, but we shouldn't expect to see them
02662     // if instruction selection has done a reasonable job.
02663     if ((OldBranchCode == X86::COND_NP &&
02664          BranchCode == X86::COND_E) ||
02665         (OldBranchCode == X86::COND_E &&
02666          BranchCode == X86::COND_NP))
02667       BranchCode = X86::COND_NP_OR_E;
02668     else if ((OldBranchCode == X86::COND_P &&
02669               BranchCode == X86::COND_NE) ||
02670              (OldBranchCode == X86::COND_NE &&
02671               BranchCode == X86::COND_P))
02672       BranchCode = X86::COND_NE_OR_P;
02673     else
02674       return true;
02675 
02676     // Update the MachineOperand.
02677     Cond[0].setImm(BranchCode);
02678   }
02679 
02680   return false;
02681 }
02682 
02683 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
02684   MachineBasicBlock::iterator I = MBB.end();
02685   unsigned Count = 0;
02686 
02687   while (I != MBB.begin()) {
02688     --I;
02689     if (I->isDebugValue())
02690       continue;
02691     if (I->getOpcode() != X86::JMP_4 &&
02692         getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
02693       break;
02694     // Remove the branch.
02695     I->eraseFromParent();
02696     I = MBB.end();
02697     ++Count;
02698   }
02699 
02700   return Count;
02701 }
02702 
02703 unsigned
02704 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
02705                            MachineBasicBlock *FBB,
02706                            const SmallVectorImpl<MachineOperand> &Cond,
02707                            DebugLoc DL) const {
02708   // Shouldn't be a fall through.
02709   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
02710   assert((Cond.size() == 1 || Cond.size() == 0) &&
02711          "X86 branch conditions have one component!");
02712 
02713   if (Cond.empty()) {
02714     // Unconditional branch?
02715     assert(!FBB && "Unconditional branch with multiple successors!");
02716     BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(TBB);
02717     return 1;
02718   }
02719 
02720   // Conditional branch.
02721   unsigned Count = 0;
02722   X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
02723   switch (CC) {
02724   case X86::COND_NP_OR_E:
02725     // Synthesize NP_OR_E with two branches.
02726     BuildMI(&MBB, DL, get(X86::JNP_4)).addMBB(TBB);
02727     ++Count;
02728     BuildMI(&MBB, DL, get(X86::JE_4)).addMBB(TBB);
02729     ++Count;
02730     break;
02731   case X86::COND_NE_OR_P:
02732     // Synthesize NE_OR_P with two branches.
02733     BuildMI(&MBB, DL, get(X86::JNE_4)).addMBB(TBB);
02734     ++Count;
02735     BuildMI(&MBB, DL, get(X86::JP_4)).addMBB(TBB);
02736     ++Count;
02737     break;
02738   default: {
02739     unsigned Opc = GetCondBranchFromCond(CC);
02740     BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
02741     ++Count;
02742   }
02743   }
02744   if (FBB) {
02745     // Two-way Conditional branch. Insert the second branch.
02746     BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(FBB);
02747     ++Count;
02748   }
02749   return Count;
02750 }
02751 
02752 bool X86InstrInfo::
02753 canInsertSelect(const MachineBasicBlock &MBB,
02754                 const SmallVectorImpl<MachineOperand> &Cond,
02755                 unsigned TrueReg, unsigned FalseReg,
02756                 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
02757   // Not all subtargets have cmov instructions.
02758   if (!TM.getSubtarget<X86Subtarget>().hasCMov())
02759     return false;
02760   if (Cond.size() != 1)
02761     return false;
02762   // We cannot do the composite conditions, at least not in SSA form.
02763   if ((X86::CondCode)Cond[0].getImm() > X86::COND_S)
02764     return false;
02765 
02766   // Check register classes.
02767   const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
02768   const TargetRegisterClass *RC =
02769     RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
02770   if (!RC)
02771     return false;
02772 
02773   // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
02774   if (X86::GR16RegClass.hasSubClassEq(RC) ||
02775       X86::GR32RegClass.hasSubClassEq(RC) ||
02776       X86::GR64RegClass.hasSubClassEq(RC)) {
02777     // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
02778     // Bridge. Probably Ivy Bridge as well.
02779     CondCycles = 2;
02780     TrueCycles = 2;
02781     FalseCycles = 2;
02782     return true;
02783   }
02784 
02785   // Can't do vectors.
02786   return false;
02787 }
02788 
02789 void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
02790                                 MachineBasicBlock::iterator I, DebugLoc DL,
02791                                 unsigned DstReg,
02792                                 const SmallVectorImpl<MachineOperand> &Cond,
02793                                 unsigned TrueReg, unsigned FalseReg) const {
02794    MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
02795    assert(Cond.size() == 1 && "Invalid Cond array");
02796    unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(),
02797                                   MRI.getRegClass(DstReg)->getSize(),
02798                                   false/*HasMemoryOperand*/);
02799    BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg);
02800 }
02801 
02802 /// isHReg - Test if the given register is a physical h register.
02803 static bool isHReg(unsigned Reg) {
02804   return X86::GR8_ABCD_HRegClass.contains(Reg);
02805 }
02806 
02807 // Try and copy between VR128/VR64 and GR64 registers.
02808 static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
02809                                         bool HasAVX) {
02810   // SrcReg(VR128) -> DestReg(GR64)
02811   // SrcReg(VR64)  -> DestReg(GR64)
02812   // SrcReg(GR64)  -> DestReg(VR128)
02813   // SrcReg(GR64)  -> DestReg(VR64)
02814 
02815   if (X86::GR64RegClass.contains(DestReg)) {
02816     if (X86::VR128RegClass.contains(SrcReg))
02817       // Copy from a VR128 register to a GR64 register.
02818       return HasAVX ? X86::VMOVPQIto64rr : X86::MOVPQIto64rr;
02819     if (X86::VR64RegClass.contains(SrcReg))
02820       // Copy from a VR64 register to a GR64 register.
02821       return X86::MOVSDto64rr;
02822   } else if (X86::GR64RegClass.contains(SrcReg)) {
02823     // Copy from a GR64 register to a VR128 register.
02824     if (X86::VR128RegClass.contains(DestReg))
02825       return HasAVX ? X86::VMOV64toPQIrr : X86::MOV64toPQIrr;
02826     // Copy from a GR64 register to a VR64 register.
02827     if (X86::VR64RegClass.contains(DestReg))
02828       return X86::MOV64toSDrr;
02829   }
02830 
02831   // SrcReg(FR32) -> DestReg(GR32)
02832   // SrcReg(GR32) -> DestReg(FR32)
02833 
02834   if (X86::GR32RegClass.contains(DestReg) && X86::FR32RegClass.contains(SrcReg))
02835     // Copy from a FR32 register to a GR32 register.
02836     return HasAVX ? X86::VMOVSS2DIrr : X86::MOVSS2DIrr;
02837 
02838   if (X86::FR32RegClass.contains(DestReg) && X86::GR32RegClass.contains(SrcReg))
02839     // Copy from a GR32 register to a FR32 register.
02840     return HasAVX ? X86::VMOVDI2SSrr : X86::MOVDI2SSrr;
02841 
02842   return 0;
02843 }
02844 
02845 void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
02846                                MachineBasicBlock::iterator MI, DebugLoc DL,
02847                                unsigned DestReg, unsigned SrcReg,
02848                                bool KillSrc) const {
02849   // First deal with the normal symmetric copies.
02850   bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
02851   unsigned Opc;
02852   if (X86::GR64RegClass.contains(DestReg, SrcReg))
02853     Opc = X86::MOV64rr;
02854   else if (X86::GR32RegClass.contains(DestReg, SrcReg))
02855     Opc = X86::MOV32rr;
02856   else if (X86::GR16RegClass.contains(DestReg, SrcReg))
02857     Opc = X86::MOV16rr;
02858   else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
02859     // Copying to or from a physical H register on x86-64 requires a NOREX
02860     // move.  Otherwise use a normal move.
02861     if ((isHReg(DestReg) || isHReg(SrcReg)) &&
02862         TM.getSubtarget<X86Subtarget>().is64Bit()) {
02863       Opc = X86::MOV8rr_NOREX;
02864       // Both operands must be encodable without an REX prefix.
02865       assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
02866              "8-bit H register can not be copied outside GR8_NOREX");
02867     } else
02868       Opc = X86::MOV8rr;
02869   } else if (X86::VR128RegClass.contains(DestReg, SrcReg))
02870     Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
02871   else if (X86::VR256RegClass.contains(DestReg, SrcReg))
02872     Opc = X86::VMOVAPSYrr;
02873   else if (X86::VR64RegClass.contains(DestReg, SrcReg))
02874     Opc = X86::MMX_MOVQ64rr;
02875   else
02876     Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, HasAVX);
02877 
02878   if (Opc) {
02879     BuildMI(MBB, MI, DL, get(Opc), DestReg)
02880       .addReg(SrcReg, getKillRegState(KillSrc));
02881     return;
02882   }
02883 
02884   // Moving EFLAGS to / from another register requires a push and a pop.
02885   // Notice that we have to adjust the stack if we don't want to clobber the
02886   // first frame index. See X86FrameLowering.cpp - colobbersTheStack.
02887   if (SrcReg == X86::EFLAGS) {
02888     if (X86::GR64RegClass.contains(DestReg)) {
02889       BuildMI(MBB, MI, DL, get(X86::PUSHF64));
02890       BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
02891       return;
02892     }
02893     if (X86::GR32RegClass.contains(DestReg)) {
02894       BuildMI(MBB, MI, DL, get(X86::PUSHF32));
02895       BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
02896       return;
02897     }
02898   }
02899   if (DestReg == X86::EFLAGS) {
02900     if (X86::GR64RegClass.contains(SrcReg)) {
02901       BuildMI(MBB, MI, DL, get(X86::PUSH64r))
02902         .addReg(SrcReg, getKillRegState(KillSrc));
02903       BuildMI(MBB, MI, DL, get(X86::POPF64));
02904       return;
02905     }
02906     if (X86::GR32RegClass.contains(SrcReg)) {
02907       BuildMI(MBB, MI, DL, get(X86::PUSH32r))
02908         .addReg(SrcReg, getKillRegState(KillSrc));
02909       BuildMI(MBB, MI, DL, get(X86::POPF32));
02910       return;
02911     }
02912   }
02913 
02914   DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
02915                << " to " << RI.getName(DestReg) << '\n');
02916   llvm_unreachable("Cannot emit physreg copy instruction");
02917 }
02918 
02919 static unsigned getLoadStoreRegOpcode(unsigned Reg,
02920                                       const TargetRegisterClass *RC,
02921                                       bool isStackAligned,
02922                                       const TargetMachine &TM,
02923                                       bool load) {
02924   bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
02925   switch (RC->getSize()) {
02926   default:
02927     llvm_unreachable("Unknown spill size");
02928   case 1:
02929     assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
02930     if (TM.getSubtarget<X86Subtarget>().is64Bit())
02931       // Copying to or from a physical H register on x86-64 requires a NOREX
02932       // move.  Otherwise use a normal move.
02933       if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
02934         return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
02935     return load ? X86::MOV8rm : X86::MOV8mr;
02936   case 2:
02937     assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
02938     return load ? X86::MOV16rm : X86::MOV16mr;
02939   case 4:
02940     if (X86::GR32RegClass.hasSubClassEq(RC))
02941       return load ? X86::MOV32rm : X86::MOV32mr;
02942     if (X86::FR32RegClass.hasSubClassEq(RC))
02943       return load ?
02944         (HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
02945         (HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
02946     if (X86::RFP32RegClass.hasSubClassEq(RC))
02947       return load ? X86::LD_Fp32m : X86::ST_Fp32m;
02948     llvm_unreachable("Unknown 4-byte regclass");
02949   case 8:
02950     if (X86::GR64RegClass.hasSubClassEq(RC))
02951       return load ? X86::MOV64rm : X86::MOV64mr;
02952     if (X86::FR64RegClass.hasSubClassEq(RC))
02953       return load ?
02954         (HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
02955         (HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
02956     if (X86::VR64RegClass.hasSubClassEq(RC))
02957       return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
02958     if (X86::RFP64RegClass.hasSubClassEq(RC))
02959       return load ? X86::LD_Fp64m : X86::ST_Fp64m;
02960     llvm_unreachable("Unknown 8-byte regclass");
02961   case 10:
02962     assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
02963     return load ? X86::LD_Fp80m : X86::ST_FpP80m;
02964   case 16: {
02965     assert(X86::VR128RegClass.hasSubClassEq(RC) && "Unknown 16-byte regclass");
02966     // If stack is realigned we can use aligned stores.
02967     if (isStackAligned)
02968       return load ?
02969         (HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm) :
02970         (HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr);
02971     else
02972       return load ?
02973         (HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm) :
02974         (HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr);
02975   }
02976   case 32:
02977     assert(X86::VR256RegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass");
02978     // If stack is realigned we can use aligned stores.
02979     if (isStackAligned)
02980       return load ? X86::VMOVAPSYrm : X86::VMOVAPSYmr;
02981     else
02982       return load ? X86::VMOVUPSYrm : X86::VMOVUPSYmr;
02983   }
02984 }
02985 
02986 static unsigned getStoreRegOpcode(unsigned SrcReg,
02987                                   const TargetRegisterClass *RC,
02988                                   bool isStackAligned,
02989                                   TargetMachine &TM) {
02990   return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, TM, false);
02991 }
02992 
02993 
02994 static unsigned getLoadRegOpcode(unsigned DestReg,
02995                                  const TargetRegisterClass *RC,
02996                                  bool isStackAligned,
02997                                  const TargetMachine &TM) {
02998   return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, TM, true);
02999 }
03000 
03001 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
03002                                        MachineBasicBlock::iterator MI,
03003                                        unsigned SrcReg, bool isKill, int FrameIdx,
03004                                        const TargetRegisterClass *RC,
03005                                        const TargetRegisterInfo *TRI) const {
03006   const MachineFunction &MF = *MBB.getParent();
03007   assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() &&
03008          "Stack slot too small for store");
03009   unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
03010   bool isAligned = (TM.getFrameLowering()->getStackAlignment() >= Alignment) ||
03011     RI.canRealignStack(MF);
03012   unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
03013   DebugLoc DL = MBB.findDebugLoc(MI);
03014   addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
03015     .addReg(SrcReg, getKillRegState(isKill));
03016 }
03017 
03018 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
03019                                   bool isKill,
03020                                   SmallVectorImpl<MachineOperand> &Addr,
03021                                   const TargetRegisterClass *RC,
03022                                   MachineInstr::mmo_iterator MMOBegin,
03023                                   MachineInstr::mmo_iterator MMOEnd,
03024                                   SmallVectorImpl<MachineInstr*> &NewMIs) const {
03025   unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
03026   bool isAligned = MMOBegin != MMOEnd &&
03027                    (*MMOBegin)->getAlignment() >= Alignment;
03028   unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
03029   DebugLoc DL;
03030   MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
03031   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
03032     MIB.addOperand(Addr[i]);
03033   MIB.addReg(SrcReg, getKillRegState(isKill));
03034   (*MIB).setMemRefs(MMOBegin, MMOEnd);
03035   NewMIs.push_back(MIB);
03036 }
03037 
03038 
03039 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
03040                                         MachineBasicBlock::iterator MI,
03041                                         unsigned DestReg, int FrameIdx,
03042                                         const TargetRegisterClass *RC,
03043                                         const TargetRegisterInfo *TRI) const {
03044   const MachineFunction &MF = *MBB.getParent();
03045   unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
03046   bool isAligned = (TM.getFrameLowering()->getStackAlignment() >= Alignment) ||
03047     RI.canRealignStack(MF);
03048   unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
03049   DebugLoc DL = MBB.findDebugLoc(MI);
03050   addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
03051 }
03052 
03053 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
03054                                  SmallVectorImpl<MachineOperand> &Addr,
03055                                  const TargetRegisterClass *RC,
03056                                  MachineInstr::mmo_iterator MMOBegin,
03057                                  MachineInstr::mmo_iterator MMOEnd,
03058                                  SmallVectorImpl<MachineInstr*> &NewMIs) const {
03059   unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
03060   bool isAligned = MMOBegin != MMOEnd &&
03061                    (*MMOBegin)->getAlignment() >= Alignment;
03062   unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
03063   DebugLoc DL;
03064   MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
03065   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
03066     MIB.addOperand(Addr[i]);
03067   (*MIB).setMemRefs(MMOBegin, MMOEnd);
03068   NewMIs.push_back(MIB);
03069 }
03070 
03071 bool X86InstrInfo::
03072 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2,
03073                int &CmpMask, int &CmpValue) const {
03074   switch (MI->getOpcode()) {
03075   default: break;
03076   case X86::CMP64ri32:
03077   case X86::CMP64ri8:
03078   case X86::CMP32ri:
03079   case X86::CMP32ri8:
03080   case X86::CMP16ri:
03081   case X86::CMP16ri8:
03082   case X86::CMP8ri:
03083     SrcReg = MI->getOperand(0).getReg();
03084     SrcReg2 = 0;
03085     CmpMask = ~0;
03086     CmpValue = MI->getOperand(1).getImm();
03087     return true;
03088   // A SUB can be used to perform comparison.
03089   case X86::SUB64rm:
03090   case X86::SUB32rm:
03091   case X86::SUB16rm:
03092   case X86::SUB8rm:
03093     SrcReg = MI->getOperand(1).getReg();
03094     SrcReg2 = 0;
03095     CmpMask = ~0;
03096     CmpValue = 0;
03097     return true;
03098   case X86::SUB64rr:
03099   case X86::SUB32rr:
03100   case X86::SUB16rr:
03101   case X86::SUB8rr:
03102     SrcReg = MI->getOperand(1).getReg();
03103     SrcReg2 = MI->getOperand(2).getReg();
03104     CmpMask = ~0;
03105     CmpValue = 0;
03106     return true;
03107   case X86::SUB64ri32:
03108   case X86::SUB64ri8:
03109   case X86::SUB32ri:
03110   case X86::SUB32ri8:
03111   case X86::SUB16ri:
03112   case X86::SUB16ri8:
03113   case X86::SUB8ri:
03114     SrcReg = MI->getOperand(1).getReg();
03115     SrcReg2 = 0;
03116     CmpMask = ~0;
03117     CmpValue = MI->getOperand(2).getImm();
03118     return true;
03119   case X86::CMP64rr:
03120   case X86::CMP32rr:
03121   case X86::CMP16rr:
03122   case X86::CMP8rr:
03123     SrcReg = MI->getOperand(0).getReg();
03124     SrcReg2 = MI->getOperand(1).getReg();
03125     CmpMask = ~0;
03126     CmpValue = 0;
03127     return true;
03128   case X86::TEST8rr:
03129   case X86::TEST16rr:
03130   case X86::TEST32rr:
03131   case X86::TEST64rr:
03132     SrcReg = MI->getOperand(0).getReg();
03133     if (MI->getOperand(1).getReg() != SrcReg) return false;
03134     // Compare against zero.
03135     SrcReg2 = 0;
03136     CmpMask = ~0;
03137     CmpValue = 0;
03138     return true;
03139   }
03140   return false;
03141 }
03142 
03143 /// isRedundantFlagInstr - check whether the first instruction, whose only
03144 /// purpose is to update flags, can be made redundant.
03145 /// CMPrr can be made redundant by SUBrr if the operands are the same.
03146 /// This function can be extended later on.
03147 /// SrcReg, SrcRegs: register operands for FlagI.
03148 /// ImmValue: immediate for FlagI if it takes an immediate.
03149 inline static bool isRedundantFlagInstr(MachineInstr *FlagI, unsigned SrcReg,
03150                                         unsigned SrcReg2, int ImmValue,
03151                                         MachineInstr *OI) {
03152   if (((FlagI->getOpcode() == X86::CMP64rr &&
03153         OI->getOpcode() == X86::SUB64rr) ||
03154        (FlagI->getOpcode() == X86::CMP32rr &&
03155         OI->getOpcode() == X86::SUB32rr)||
03156        (FlagI->getOpcode() == X86::CMP16rr &&
03157         OI->getOpcode() == X86::SUB16rr)||
03158        (FlagI->getOpcode() == X86::CMP8rr &&
03159         OI->getOpcode() == X86::SUB8rr)) &&
03160       ((OI->getOperand(1).getReg() == SrcReg &&
03161         OI->getOperand(2).getReg() == SrcReg2) ||
03162        (OI->getOperand(1).getReg() == SrcReg2 &&
03163         OI->getOperand(2).getReg() == SrcReg)))
03164     return true;
03165 
03166   if (((FlagI->getOpcode() == X86::CMP64ri32 &&
03167         OI->getOpcode() == X86::SUB64ri32) ||
03168        (FlagI->getOpcode() == X86::CMP64ri8 &&
03169         OI->getOpcode() == X86::SUB64ri8) ||
03170        (FlagI->getOpcode() == X86::CMP32ri &&
03171         OI->getOpcode() == X86::SUB32ri) ||
03172        (FlagI->getOpcode() == X86::CMP32ri8 &&
03173         OI->getOpcode() == X86::SUB32ri8) ||
03174        (FlagI->getOpcode() == X86::CMP16ri &&
03175         OI->getOpcode() == X86::SUB16ri) ||
03176        (FlagI->getOpcode() == X86::CMP16ri8 &&
03177         OI->getOpcode() == X86::SUB16ri8) ||
03178        (FlagI->getOpcode() == X86::CMP8ri &&
03179         OI->getOpcode() == X86::SUB8ri)) &&
03180       OI->getOperand(1).getReg() == SrcReg &&
03181       OI->getOperand(2).getImm() == ImmValue)
03182     return true;
03183   return false;
03184 }
03185 
03186 /// isDefConvertible - check whether the definition can be converted
03187 /// to remove a comparison against zero.
03188 inline static bool isDefConvertible(MachineInstr *MI) {
03189   switch (MI->getOpcode()) {
03190   default: return false;
03191 
03192   // The shift instructions only modify ZF if their shift count is non-zero.
03193   // N.B.: The processor truncates the shift count depending on the encoding.
03194   case X86::SAR8ri:    case X86::SAR16ri:  case X86::SAR32ri:case X86::SAR64ri:
03195   case X86::SHR8ri:    case X86::SHR16ri:  case X86::SHR32ri:case X86::SHR64ri:
03196      return getTruncatedShiftCount(MI, 2) != 0;
03197 
03198   // Some left shift instructions can be turned into LEA instructions but only
03199   // if their flags aren't used. Avoid transforming such instructions.
03200   case X86::SHL8ri:    case X86::SHL16ri:  case X86::SHL32ri:case X86::SHL64ri:{
03201     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
03202     if (isTruncatedShiftCountForLEA(ShAmt)) return false;
03203     return ShAmt != 0;
03204   }
03205 
03206   case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
03207   case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
03208      return getTruncatedShiftCount(MI, 3) != 0;
03209 
03210   case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
03211   case X86::SUB32ri8:  case X86::SUB16ri:  case X86::SUB16ri8:
03212   case X86::SUB8ri:    case X86::SUB64rr:  case X86::SUB32rr:
03213   case X86::SUB16rr:   case X86::SUB8rr:   case X86::SUB64rm:
03214   case X86::SUB32rm:   case X86::SUB16rm:  case X86::SUB8rm:
03215   case X86::DEC64r:    case X86::DEC32r:   case X86::DEC16r: case X86::DEC8r:
03216   case X86::DEC64_32r: case X86::DEC64_16r:
03217   case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
03218   case X86::ADD32ri8:  case X86::ADD16ri:  case X86::ADD16ri8:
03219   case X86::ADD8ri:    case X86::ADD64rr:  case X86::ADD32rr:
03220   case X86::ADD16rr:   case X86::ADD8rr:   case X86::ADD64rm:
03221   case X86::ADD32rm:   case X86::ADD16rm:  case X86::ADD8rm:
03222   case X86::INC64r:    case X86::INC32r:   case X86::INC16r: case X86::INC8r:
03223   case X86::INC64_32r: case X86::INC64_16r:
03224   case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
03225   case X86::AND32ri8:  case X86::AND16ri:  case X86::AND16ri8:
03226   case X86::AND8ri:    case X86::AND64rr:  case X86::AND32rr:
03227   case X86::AND16rr:   case X86::AND8rr:   case X86::AND64rm:
03228   case X86::AND32rm:   case X86::AND16rm:  case X86::AND8rm:
03229   case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
03230   case X86::XOR32ri8:  case X86::XOR16ri:  case X86::XOR16ri8:
03231   case X86::XOR8ri:    case X86::XOR64rr:  case X86::XOR32rr:
03232   case X86::XOR16rr:   case X86::XOR8rr:   case X86::XOR64rm:
03233   case X86::XOR32rm:   case X86::XOR16rm:  case X86::XOR8rm:
03234   case X86::OR64ri32:  case X86::OR64ri8:  case X86::OR32ri:
03235   case X86::OR32ri8:   case X86::OR16ri:   case X86::OR16ri8:
03236   case X86::OR8ri:     case X86::OR64rr:   case X86::OR32rr:
03237   case X86::OR16rr:    case X86::OR8rr:    case X86::OR64rm:
03238   case X86::OR32rm:    case X86::OR16rm:   case X86::OR8rm:
03239   case X86::NEG8r:     case X86::NEG16r:   case X86::NEG32r: case X86::NEG64r:
03240   case X86::SAR8r1:    case X86::SAR16r1:  case X86::SAR32r1:case X86::SAR64r1:
03241   case X86::SHR8r1:    case X86::SHR16r1:  case X86::SHR32r1:case X86::SHR64r1:
03242   case X86::SHL8r1:    case X86::SHL16r1:  case X86::SHL32r1:case X86::SHL64r1:
03243   case X86::ADC32ri:   case X86::ADC32ri8:
03244   case X86::ADC32rr:   case X86::ADC64ri32:
03245   case X86::ADC64ri8:  case X86::ADC64rr:
03246   case X86::SBB32ri:   case X86::SBB32ri8:
03247   case X86::SBB32rr:   case X86::SBB64ri32:
03248   case X86::SBB64ri8:  case X86::SBB64rr:
03249   case X86::ANDN32rr:  case X86::ANDN32rm:
03250   case X86::ANDN64rr:  case X86::ANDN64rm:
03251   case X86::BEXTR32rr: case X86::BEXTR64rr:
03252   case X86::BEXTR32rm: case X86::BEXTR64rm:
03253   case X86::BLSI32rr:  case X86::BLSI32rm:
03254   case X86::BLSI64rr:  case X86::BLSI64rm:
03255   case X86::BLSMSK32rr:case X86::BLSMSK32rm:
03256   case X86::BLSMSK64rr:case X86::BLSMSK64rm:
03257   case X86::BLSR32rr:  case X86::BLSR32rm:
03258   case X86::BLSR64rr:  case X86::BLSR64rm:
03259   case X86::BZHI32rr:  case X86::BZHI32rm:
03260   case X86::BZHI64rr:  case X86::BZHI64rm:
03261   case X86::LZCNT16rr: case X86::LZCNT16rm:
03262   case X86::LZCNT32rr: case X86::LZCNT32rm:
03263   case X86::LZCNT64rr: case X86::LZCNT64rm:
03264   case X86::POPCNT16rr:case X86::POPCNT16rm:
03265   case X86::POPCNT32rr:case X86::POPCNT32rm:
03266   case X86::POPCNT64rr:case X86::POPCNT64rm:
03267   case X86::TZCNT16rr: case X86::TZCNT16rm:
03268   case X86::TZCNT32rr: case X86::TZCNT32rm:
03269   case X86::TZCNT64rr: case X86::TZCNT64rm:
03270     return true;
03271   }
03272 }
03273 
03274 /// optimizeCompareInstr - Check if there exists an earlier instruction that
03275 /// operates on the same source operands and sets flags in the same way as
03276 /// Compare; remove Compare if possible.
03277 bool X86InstrInfo::
03278 optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
03279                      int CmpMask, int CmpValue,
03280                      const MachineRegisterInfo *MRI) const {
03281   // Check whether we can replace SUB with CMP.
03282   unsigned NewOpcode = 0;
03283   switch (CmpInstr->getOpcode()) {
03284   default: break;
03285   case X86::SUB64ri32:
03286   case X86::SUB64ri8:
03287   case X86::SUB32ri:
03288   case X86::SUB32ri8:
03289   case X86::SUB16ri:
03290   case X86::SUB16ri8:
03291   case X86::SUB8ri:
03292   case X86::SUB64rm:
03293   case X86::SUB32rm:
03294   case X86::SUB16rm:
03295   case X86::SUB8rm:
03296   case X86::SUB64rr:
03297   case X86::SUB32rr:
03298   case X86::SUB16rr:
03299   case X86::SUB8rr: {
03300     if (!MRI->use_nodbg_empty(CmpInstr->getOperand(0).getReg()))
03301       return false;
03302     // There is no use of the destination register, we can replace SUB with CMP.
03303     switch (CmpInstr->getOpcode()) {
03304     default: llvm_unreachable("Unreachable!");
03305     case X86::SUB64rm:   NewOpcode = X86::CMP64rm;   break;
03306     case X86::SUB32rm:   NewOpcode = X86::CMP32rm;   break;
03307     case X86::SUB16rm:   NewOpcode = X86::CMP16rm;   break;
03308     case X86::SUB8rm:    NewOpcode = X86::CMP8rm;    break;
03309     case X86::SUB64rr:   NewOpcode = X86::CMP64rr;   break;
03310     case X86::SUB32rr:   NewOpcode = X86::CMP32rr;   break;
03311     case X86::SUB16rr:   NewOpcode = X86::CMP16rr;   break;
03312     case X86::SUB8rr:    NewOpcode = X86::CMP8rr;    break;
03313     case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
03314     case X86::SUB64ri8:  NewOpcode = X86::CMP64ri8;  break;
03315     case X86::SUB32ri:   NewOpcode = X86::CMP32ri;   break;
03316     case X86::SUB32ri8:  NewOpcode = X86::CMP32ri8;  break;
03317     case X86::SUB16ri:   NewOpcode = X86::CMP16ri;   break;
03318     case X86::SUB16ri8:  NewOpcode = X86::CMP16ri8;  break;
03319     case X86::SUB8ri:    NewOpcode = X86::CMP8ri;    break;
03320     }
03321     CmpInstr->setDesc(get(NewOpcode));
03322     CmpInstr->RemoveOperand(0);
03323     // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
03324     if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
03325         NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
03326       return false;
03327   }
03328   }
03329 
03330   // Get the unique definition of SrcReg.
03331   MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
03332   if (!MI) return false;
03333 
03334   // CmpInstr is the first instruction of the BB.
03335   MachineBasicBlock::iterator I = CmpInstr, Def = MI;
03336 
03337   // If we are comparing against zero, check whether we can use MI to update
03338   // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
03339   bool IsCmpZero = (SrcReg2 == 0 && CmpValue == 0);
03340   if (IsCmpZero && (MI->getParent() != CmpInstr->getParent() ||
03341       !isDefConvertible(MI)))
03342     return false;
03343 
03344   // We are searching for an earlier instruction that can make CmpInstr
03345   // redundant and that instruction will be saved in Sub.
03346   MachineInstr *Sub = NULL;
03347   const TargetRegisterInfo *TRI = &getRegisterInfo();
03348 
03349   // We iterate backward, starting from the instruction before CmpInstr and
03350   // stop when reaching the definition of a source register or done with the BB.
03351   // RI points to the instruction before CmpInstr.
03352   // If the definition is in this basic block, RE points to the definition;
03353   // otherwise, RE is the rend of the basic block.
03354   MachineBasicBlock::reverse_iterator
03355       RI = MachineBasicBlock::reverse_iterator(I),
03356       RE = CmpInstr->getParent() == MI->getParent() ?
03357            MachineBasicBlock::reverse_iterator(++Def) /* points to MI */ :
03358            CmpInstr->getParent()->rend();
03359   MachineInstr *Movr0Inst = 0;
03360   for (; RI != RE; ++RI) {
03361     MachineInstr *Instr = &*RI;
03362     // Check whether CmpInstr can be made redundant by the current instruction.
03363     if (!IsCmpZero &&
03364         isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, Instr)) {
03365       Sub = Instr;
03366       break;
03367     }
03368 
03369     if (Instr->modifiesRegister(X86::EFLAGS, TRI) ||
03370         Instr->readsRegister(X86::EFLAGS, TRI)) {
03371       // This instruction modifies or uses EFLAGS.
03372 
03373       // MOV32r0 etc. are implemented with xor which clobbers condition code.
03374       // They are safe to move up, if the definition to EFLAGS is dead and
03375       // earlier instructions do not read or write EFLAGS.
03376       if (!Movr0Inst && (Instr->getOpcode() == X86::MOV8r0 ||
03377            Instr->getOpcode() == X86::MOV16r0 ||
03378            Instr->getOpcode() == X86::MOV32r0 ||
03379            Instr->getOpcode() == X86::MOV64r0) &&
03380           Instr->registerDefIsDead(X86::EFLAGS, TRI)) {
03381         Movr0Inst = Instr;
03382         continue;
03383       }
03384 
03385       // We can't remove CmpInstr.
03386       return false;
03387     }
03388   }
03389 
03390   // Return false if no candidates exist.
03391   if (!IsCmpZero && !Sub)
03392     return false;
03393 
03394   bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
03395                     Sub->getOperand(2).getReg() == SrcReg);
03396 
03397   // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
03398   // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
03399   // If we are done with the basic block, we need to check whether EFLAGS is
03400   // live-out.
03401   bool IsSafe = false;
03402   SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate;
03403   MachineBasicBlock::iterator E = CmpInstr->getParent()->end();
03404   for (++I; I != E; ++I) {
03405     const MachineInstr &Instr = *I;
03406     bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
03407     bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
03408     // We should check the usage if this instruction uses and updates EFLAGS.
03409     if (!UseEFLAGS && ModifyEFLAGS) {
03410       // It is safe to remove CmpInstr if EFLAGS is updated again.
03411       IsSafe = true;
03412       break;
03413     }
03414     if (!UseEFLAGS && !ModifyEFLAGS)
03415       continue;
03416 
03417     // EFLAGS is used by this instruction.
03418     X86::CondCode OldCC;
03419     bool OpcIsSET = false;
03420     if (IsCmpZero || IsSwapped) {
03421       // We decode the condition code from opcode.
03422       if (Instr.isBranch())
03423         OldCC = getCondFromBranchOpc(Instr.getOpcode());
03424       else {
03425         OldCC = getCondFromSETOpc(Instr.getOpcode());
03426         if (OldCC != X86::COND_INVALID)
03427           OpcIsSET = true;
03428         else
03429           OldCC = X86::getCondFromCMovOpc(Instr.getOpcode());
03430       }
03431       if (OldCC == X86::COND_INVALID) return false;
03432     }
03433     if (IsCmpZero) {
03434       switch (OldCC) {
03435       default: break;
03436       case X86::COND_A: case X86::COND_AE:
03437       case X86::COND_B: case X86::COND_BE:
03438       case X86::COND_G: case X86::COND_GE:
03439       case X86::COND_L: case X86::COND_LE:
03440       case X86::COND_O: case X86::COND_NO:
03441         // CF and OF are used, we can't perform this optimization.
03442         return false;
03443       }
03444     } else if (IsSwapped) {
03445       // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
03446       // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
03447       // We swap the condition code and synthesize the new opcode.
03448       X86::CondCode NewCC = getSwappedCondition(OldCC);
03449       if (NewCC == X86::COND_INVALID) return false;
03450 
03451       // Synthesize the new opcode.
03452       bool HasMemoryOperand = Instr.hasOneMemOperand();
03453       unsigned NewOpc;
03454       if (Instr.isBranch())
03455         NewOpc = GetCondBranchFromCond(NewCC);
03456       else if(OpcIsSET)
03457         NewOpc = getSETFromCond(NewCC, HasMemoryOperand);
03458       else {
03459         unsigned DstReg = Instr.getOperand(0).getReg();
03460         NewOpc = getCMovFromCond(NewCC, MRI->getRegClass(DstReg)->getSize(),
03461                                  HasMemoryOperand);
03462       }
03463 
03464       // Push the MachineInstr to OpsToUpdate.
03465       // If it is safe to remove CmpInstr, the condition code of these
03466       // instructions will be modified.
03467       OpsToUpdate.push_back(std::make_pair(&*I, NewOpc));
03468     }
03469     if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
03470       // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
03471       IsSafe = true;
03472       break;
03473     }
03474   }
03475 
03476   // If EFLAGS is not killed nor re-defined, we should check whether it is
03477   // live-out. If it is live-out, do not optimize.
03478   if ((IsCmpZero || IsSwapped) && !IsSafe) {
03479     MachineBasicBlock *MBB = CmpInstr->getParent();
03480     for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
03481              SE = MBB->succ_end(); SI != SE; ++SI)
03482       if ((*SI)->isLiveIn(X86::EFLAGS))
03483         return false;
03484   }
03485 
03486   // The instruction to be updated is either Sub or MI.
03487   Sub = IsCmpZero ? MI : Sub;
03488   // Move Movr0Inst to the appropriate place before Sub.
03489   if (Movr0Inst) {
03490     // Look backwards until we find a def that doesn't use the current EFLAGS.
03491     Def = Sub;
03492     MachineBasicBlock::reverse_iterator
03493       InsertI = MachineBasicBlock::reverse_iterator(++Def),
03494                 InsertE = Sub->getParent()->rend();
03495     for (; InsertI != InsertE; ++InsertI) {
03496       MachineInstr *Instr = &*InsertI;
03497       if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
03498           Instr->modifiesRegister(X86::EFLAGS, TRI)) {
03499         Sub->getParent()->remove(Movr0Inst);
03500         Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
03501                                    Movr0Inst);
03502         break;
03503       }
03504     }
03505     if (InsertI == InsertE)
03506       return false;
03507   }
03508 
03509   // Make sure Sub instruction defines EFLAGS and mark the def live.
03510   unsigned i = 0, e = Sub->getNumOperands();
03511   for (; i != e; ++i) {
03512     MachineOperand &MO = Sub->getOperand(i);
03513     if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
03514       MO.setIsDead(false);
03515       break;
03516     }
03517   }
03518   assert(i != e && "Unable to locate a def EFLAGS operand");
03519 
03520   CmpInstr->eraseFromParent();
03521 
03522   // Modify the condition code of instructions in OpsToUpdate.
03523   for (unsigned i = 0, e = OpsToUpdate.size(); i < e; i++)
03524     OpsToUpdate[i].first->setDesc(get(OpsToUpdate[i].second));
03525   return true;
03526 }
03527 
03528 /// optimizeLoadInstr - Try to remove the load by folding it to a register
03529 /// operand at the use. We fold the load instructions if load defines a virtual
03530 /// register, the virtual register is used once in the same BB, and the
03531 /// instructions in-between do not load or store, and have no side effects.
03532 MachineInstr* X86InstrInfo::
03533 optimizeLoadInstr(MachineInstr *MI, const MachineRegisterInfo *MRI,
03534                   unsigned &FoldAsLoadDefReg,
03535                   MachineInstr *&DefMI) const {
03536   if (FoldAsLoadDefReg == 0)
03537     return 0;
03538   // To be conservative, if there exists another load, clear the load candidate.
03539   if (MI->mayLoad()) {
03540     FoldAsLoadDefReg = 0;
03541     return 0;
03542   }
03543 
03544   // Check whether we can move DefMI here.
03545   DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
03546   assert(DefMI);
03547   bool SawStore = false;
03548   if (!DefMI->isSafeToMove(this, 0, SawStore))
03549     return 0;
03550 
03551   // We try to commute MI if possible.
03552   unsigned IdxEnd = (MI->isCommutable()) ? 2 : 1;
03553   for (unsigned Idx = 0; Idx < IdxEnd; Idx++) {
03554     // Collect information about virtual register operands of MI.
03555     unsigned SrcOperandId = 0;
03556     bool FoundSrcOperand = false;
03557     for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
03558       MachineOperand &MO = MI->getOperand(i);
03559       if (!MO.isReg())
03560         continue;
03561       unsigned Reg = MO.getReg();
03562       if (Reg != FoldAsLoadDefReg)
03563         continue;
03564       // Do not fold if we have a subreg use or a def or multiple uses.
03565       if (MO.getSubReg() || MO.isDef() || FoundSrcOperand)
03566         return 0;
03567 
03568       SrcOperandId = i;
03569       FoundSrcOperand = true;
03570     }
03571     if (!FoundSrcOperand) return 0;
03572 
03573     // Check whether we can fold the def into SrcOperandId.
03574     SmallVector<unsigned, 8> Ops;
03575     Ops.push_back(SrcOperandId);
03576     MachineInstr *FoldMI = foldMemoryOperand(MI, Ops, DefMI);
03577     if (FoldMI) {
03578       FoldAsLoadDefReg = 0;
03579       return FoldMI;
03580     }
03581 
03582     if (Idx == 1) {
03583       // MI was changed but it didn't help, commute it back!
03584       commuteInstruction(MI, false);
03585       return 0;
03586     }
03587 
03588     // Check whether we can commute MI and enable folding.
03589     if (MI->isCommutable()) {
03590       MachineInstr *NewMI = commuteInstruction(MI, false);
03591       // Unable to commute.
03592       if (!NewMI) return 0;
03593       if (NewMI != MI) {
03594         // New instruction. It doesn't need to be kept.
03595         NewMI->eraseFromParent();
03596         return 0;
03597       }
03598     }
03599   }
03600   return 0;
03601 }
03602 
03603 /// Expand2AddrUndef - Expand a single-def pseudo instruction to a two-addr
03604 /// instruction with two undef reads of the register being defined.  This is
03605 /// used for mapping:
03606 ///   %xmm4 = V_SET0
03607 /// to:
03608 ///   %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef>
03609 ///
03610 static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
03611                              const MCInstrDesc &Desc) {
03612   assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
03613   unsigned Reg = MIB->getOperand(0).getReg();
03614   MIB->setDesc(Desc);
03615 
03616   // MachineInstr::addOperand() will insert explicit operands before any
03617   // implicit operands.
03618   MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
03619   // But we don't trust that.
03620   assert(MIB->getOperand(1).getReg() == Reg &&
03621          MIB->getOperand(2).getReg() == Reg && "Misplaced operand");
03622   return true;
03623 }
03624 
03625 bool X86InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
03626   bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
03627   MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
03628   switch (MI->getOpcode()) {
03629   case X86::SETB_C8r:
03630     return Expand2AddrUndef(MIB, get(X86::SBB8rr));
03631   case X86::SETB_C16r:
03632     return Expand2AddrUndef(MIB, get(X86::SBB16rr));
03633   case X86::SETB_C32r:
03634     return Expand2AddrUndef(MIB, get(X86::SBB32rr));
03635   case X86::SETB_C64r:
03636     return Expand2AddrUndef(MIB, get(X86::SBB64rr));
03637   case X86::V_SET0:
03638   case X86::FsFLD0SS:
03639   case X86::FsFLD0SD:
03640     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
03641   case X86::AVX_SET0:
03642     assert(HasAVX && "AVX not supported");
03643     return Expand2AddrUndef(MIB, get(X86::VXORPSYrr));
03644   case X86::V_SETALLONES:
03645     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
03646   case X86::AVX2_SETALLONES:
03647     return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
03648   case X86::TEST8ri_NOREX:
03649     MI->setDesc(get(X86::TEST8ri));
03650     return true;
03651   }
03652   return false;
03653 }
03654 
03655 MachineInstr*
03656 X86InstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
03657                                        int FrameIx, uint64_t Offset,
03658                                        const MDNode *MDPtr,
03659                                        DebugLoc DL) const {
03660   X86AddressMode AM;
03661   AM.BaseType = X86AddressMode::FrameIndexBase;
03662   AM.Base.FrameIndex = FrameIx;
03663   MachineInstrBuilder MIB = BuildMI(MF, DL, get(X86::DBG_VALUE));
03664   addFullAddress(MIB, AM).addImm(Offset).addMetadata(MDPtr);
03665   return &*MIB;
03666 }
03667 
03668 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
03669                                      const SmallVectorImpl<MachineOperand> &MOs,
03670                                      MachineInstr *MI,
03671                                      const TargetInstrInfo &TII) {
03672   // Create the base instruction with the memory operand as the first part.
03673   // Omit the implicit operands, something BuildMI can't do.
03674   MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
03675                                               MI->getDebugLoc(), true);
03676   MachineInstrBuilder MIB(MF, NewMI);
03677   unsigned NumAddrOps = MOs.size();
03678   for (unsigned i = 0; i != NumAddrOps; ++i)
03679     MIB.addOperand(MOs[i]);
03680   if (NumAddrOps < 4)  // FrameIndex only
03681     addOffset(MIB, 0);
03682 
03683   // Loop over the rest of the ri operands, converting them over.
03684   unsigned NumOps = MI->getDesc().getNumOperands()-2;
03685   for (unsigned i = 0; i != NumOps; ++i) {
03686     MachineOperand &MO = MI->getOperand(i+2);
03687     MIB.addOperand(MO);
03688   }
03689   for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
03690     MachineOperand &MO = MI->getOperand(i);
03691     MIB.addOperand(MO);
03692   }
03693   return MIB;
03694 }
03695 
03696 static MachineInstr *FuseInst(MachineFunction &MF,
03697                               unsigned Opcode, unsigned OpNo,
03698                               const SmallVectorImpl<MachineOperand> &MOs,
03699                               MachineInstr *MI, const TargetInstrInfo &TII) {
03700   // Omit the implicit operands, something BuildMI can't do.
03701   MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
03702                                               MI->getDebugLoc(), true);
03703   MachineInstrBuilder MIB(MF, NewMI);
03704 
03705   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
03706     MachineOperand &MO = MI->getOperand(i);
03707     if (i == OpNo) {
03708       assert(MO.isReg() && "Expected to fold into reg operand!");
03709       unsigned NumAddrOps = MOs.size();
03710       for (unsigned i = 0; i != NumAddrOps; ++i)
03711         MIB.addOperand(MOs[i]);
03712       if (NumAddrOps < 4)  // FrameIndex only
03713         addOffset(MIB, 0);
03714     } else {
03715       MIB.addOperand(MO);
03716     }
03717   }
03718   return MIB;
03719 }
03720 
03721 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
03722                                 const SmallVectorImpl<MachineOperand> &MOs,
03723                                 MachineInstr *MI) {
03724   MachineFunction &MF = *MI->getParent()->getParent();
03725   MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode));
03726 
03727   unsigned NumAddrOps = MOs.size();
03728   for (unsigned i = 0; i != NumAddrOps; ++i)
03729     MIB.addOperand(MOs[i]);
03730   if (NumAddrOps < 4)  // FrameIndex only
03731     addOffset(MIB, 0);
03732   return MIB.addImm(0);
03733 }
03734 
03735 MachineInstr*
03736 X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
03737                                     MachineInstr *MI, unsigned i,
03738                                     const SmallVectorImpl<MachineOperand> &MOs,
03739                                     unsigned Size, unsigned Align) const {
03740   const DenseMap<unsigned, std::pair<unsigned,unsigned> > *OpcodeTablePtr = 0;
03741   bool isCallRegIndirect = TM.getSubtarget<X86Subtarget>().callRegIndirect();
03742   bool isTwoAddrFold = false;
03743 
03744   // Atom favors register form of call. So, we do not fold loads into calls
03745   // when X86Subtarget is Atom.
03746   if (isCallRegIndirect &&
03747     (MI->getOpcode() == X86::CALL32r || MI->getOpcode() == X86::CALL64r)) {
03748     return NULL;
03749   }
03750 
03751   unsigned NumOps = MI->getDesc().getNumOperands();
03752   bool isTwoAddr = NumOps > 1 &&
03753     MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
03754 
03755   // FIXME: AsmPrinter doesn't know how to handle
03756   // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
03757   if (MI->getOpcode() == X86::ADD32ri &&
03758       MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
03759     return NULL;
03760 
03761   MachineInstr *NewMI = NULL;
03762   // Folding a memory location into the two-address part of a two-address
03763   // instruction is different than folding it other places.  It requires
03764   // replacing the *two* registers with the memory location.
03765   if (isTwoAddr && NumOps >= 2 && i < 2 &&
03766       MI->getOperand(0).isReg() &&
03767       MI->getOperand(1).isReg() &&
03768       MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
03769     OpcodeTablePtr = &RegOp2MemOpTable2Addr;
03770     isTwoAddrFold = true;
03771   } else if (i == 0) { // If operand 0
03772     unsigned Opc = 0;
03773     switch (MI->getOpcode()) {
03774     default: break;
03775     case X86::MOV64r0: Opc = X86::MOV64mi32; break;
03776     case X86::MOV32r0: Opc = X86::MOV32mi;   break;
03777     case X86::MOV16r0: Opc = X86::MOV16mi;   break;
03778     case X86::MOV8r0:  Opc = X86::MOV8mi;    break;
03779     }
03780     if (Opc)
03781        NewMI = MakeM0Inst(*this, Opc, MOs, MI);
03782     if (NewMI)
03783       return NewMI;
03784 
03785     OpcodeTablePtr = &RegOp2MemOpTable0;
03786   } else if (i == 1) {
03787     OpcodeTablePtr = &RegOp2MemOpTable1;
03788   } else if (i == 2) {
03789     OpcodeTablePtr = &RegOp2MemOpTable2;
03790   } else if (i == 3) {
03791     OpcodeTablePtr = &RegOp2MemOpTable3;
03792   }
03793 
03794   // If table selected...
03795   if (OpcodeTablePtr) {
03796     // Find the Opcode to fuse
03797     DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
03798       OpcodeTablePtr->find(MI->getOpcode());
03799     if (I != OpcodeTablePtr->end()) {
03800       unsigned Opcode = I->second.first;
03801       unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
03802       if (Align < MinAlign)
03803         return NULL;
03804       bool NarrowToMOV32rm = false;
03805       if (Size) {
03806         unsigned RCSize = getRegClass(MI->getDesc(), i, &RI, MF)->getSize();
03807         if (Size < RCSize) {
03808           // Check if it's safe to fold the load. If the size of the object is
03809           // narrower than the load width, then it's not.
03810           if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
03811             return NULL;
03812           // If this is a 64-bit load, but the spill slot is 32, then we can do
03813           // a 32-bit load which is implicitly zero-extended. This likely is due
03814           // to liveintervalanalysis remat'ing a load from stack slot.
03815           if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
03816             return NULL;
03817           Opcode = X86::MOV32rm;
03818           NarrowToMOV32rm = true;
03819         }
03820       }
03821 
03822       if (isTwoAddrFold)
03823         NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this);
03824       else
03825         NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this);
03826 
03827       if (NarrowToMOV32rm) {
03828         // If this is the special case where we use a MOV32rm to load a 32-bit
03829         // value and zero-extend the top bits. Change the destination register
03830         // to a 32-bit one.
03831         unsigned DstReg = NewMI->getOperand(0).getReg();
03832         if (TargetRegisterInfo::isPhysicalRegister(DstReg))
03833           NewMI->getOperand(0).setReg(RI.getSubReg(DstReg,
03834                                                    X86::sub_32bit));
03835         else
03836           NewMI->getOperand(0).setSubReg(X86::sub_32bit);
03837       }
03838       return NewMI;
03839     }
03840   }
03841 
03842   // No fusion
03843   if (PrintFailedFusing && !MI->isCopy())
03844     dbgs() << "We failed to fuse operand " << i << " in " << *MI;
03845   return NULL;
03846 }
03847 
03848 /// hasPartialRegUpdate - Return true for all instructions that only update
03849 /// the first 32 or 64-bits of the destination register and leave the rest
03850 /// unmodified. This can be used to avoid folding loads if the instructions
03851 /// only update part of the destination register, and the non-updated part is
03852 /// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
03853 /// instructions breaks the partial register dependency and it can improve
03854 /// performance. e.g.:
03855 ///
03856 ///   movss (%rdi), %xmm0
03857 ///   cvtss2sd %xmm0, %xmm0
03858 ///
03859 /// Instead of
03860 ///   cvtss2sd (%rdi), %xmm0
03861 ///
03862 /// FIXME: This should be turned into a TSFlags.
03863 ///
03864 static bool hasPartialRegUpdate(unsigned Opcode) {
03865   switch (Opcode) {
03866   case X86::CVTSI2SSrr:
03867   case X86::CVTSI2SS64rr:
03868   case X86::CVTSI2SDrr:
03869   case X86::CVTSI2SD64rr:
03870   case X86::CVTSD2SSrr:
03871   case X86::Int_CVTSD2SSrr:
03872   case X86::CVTSS2SDrr:
03873   case X86::Int_CVTSS2SDrr:
03874   case X86::RCPSSr:
03875   case X86::RCPSSr_Int:
03876   case X86::ROUNDSDr:
03877   case X86::ROUNDSDr_Int:
03878   case X86::ROUNDSSr:
03879   case X86::ROUNDSSr_Int:
03880   case X86::RSQRTSSr:
03881   case X86::RSQRTSSr_Int:
03882   case X86::SQRTSSr:
03883   case X86::SQRTSSr_Int:
03884   // AVX encoded versions
03885   case X86::VCVTSD2SSrr:
03886   case X86::Int_VCVTSD2SSrr:
03887   case X86::VCVTSS2SDrr:
03888   case X86::Int_VCVTSS2SDrr:
03889   case X86::VRCPSSr:
03890   case X86::VROUNDSDr:
03891   case X86::VROUNDSDr_Int:
03892   case X86::VROUNDSSr:
03893   case X86::VROUNDSSr_Int:
03894   case X86::VRSQRTSSr:
03895   case X86::VSQRTSSr:
03896     return true;
03897   }
03898 
03899   return false;
03900 }
03901 
03902 /// getPartialRegUpdateClearance - Inform the ExeDepsFix pass how many idle
03903 /// instructions we would like before a partial register update.
03904 unsigned X86InstrInfo::
03905 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
03906                              const TargetRegisterInfo *TRI) const {
03907   if (OpNum != 0 || !hasPartialRegUpdate(MI->getOpcode()))
03908     return 0;
03909 
03910   // If MI is marked as reading Reg, the partial register update is wanted.
03911   const MachineOperand &MO = MI->getOperand(0);
03912   unsigned Reg = MO.getReg();
03913   if (TargetRegisterInfo::isVirtualRegister(Reg)) {
03914     if (MO.readsReg() || MI->readsVirtualRegister(Reg))
03915       return 0;
03916   } else {
03917     if (MI->readsRegister(Reg, TRI))
03918       return 0;
03919   }
03920 
03921   // If any of the preceding 16 instructions are reading Reg, insert a
03922   // dependency breaking instruction.  The magic number is based on a few
03923   // Nehalem experiments.
03924   return 16;
03925 }
03926 
03927 void X86InstrInfo::
03928 breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
03929                           const TargetRegisterInfo *TRI) const {
03930   unsigned Reg = MI->getOperand(OpNum).getReg();
03931   if (X86::VR128RegClass.contains(Reg)) {
03932     // These instructions are all floating point domain, so xorps is the best
03933     // choice.
03934     bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
03935     unsigned Opc = HasAVX ? X86::VXORPSrr : X86::XORPSrr;
03936     BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(Opc), Reg)
03937       .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
03938   } else if (X86::VR256RegClass.contains(Reg)) {
03939     // Use vxorps to clear the full ymm register.
03940     // It wants to read and write the xmm sub-register.
03941     unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm);
03942     BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(X86::VXORPSrr), XReg)
03943       .addReg(XReg, RegState::Undef).addReg(XReg, RegState::Undef)
03944       .addReg(Reg, RegState::ImplicitDefine);
03945   } else
03946     return;
03947   MI->addRegisterKilled(Reg, TRI, true);
03948 }
03949 
03950 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
03951                                                   MachineInstr *MI,
03952                                            const SmallVectorImpl<unsigned> &Ops,
03953                                                   int FrameIndex) const {
03954   // Check switch flag
03955   if (NoFusing) return NULL;
03956 
03957   // Unless optimizing for size, don't fold to avoid partial
03958   // register update stalls
03959   if (!MF.getFunction()->getAttributes().
03960         hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize) &&
03961       hasPartialRegUpdate(MI->getOpcode()))
03962     return 0;
03963 
03964   const MachineFrameInfo *MFI = MF.getFrameInfo();
03965   unsigned Size = MFI->getObjectSize(FrameIndex);
03966   unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
03967   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
03968     unsigned NewOpc = 0;
03969     unsigned RCSize = 0;
03970     switch (MI->getOpcode()) {
03971     default: return NULL;
03972     case X86::TEST8rr:  NewOpc = X86::CMP8ri; RCSize = 1; break;
03973     case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
03974     case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
03975     case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
03976     }
03977     // Check if it's safe to fold the load. If the size of the object is
03978     // narrower than the load width, then it's not.
03979     if (Size < RCSize)
03980       return NULL;
03981     // Change to CMPXXri r, 0 first.
03982     MI->setDesc(get(NewOpc));
03983     MI->getOperand(1).ChangeToImmediate(0);
03984   } else if (Ops.size() != 1)
03985     return NULL;
03986 
03987   SmallVector<MachineOperand,4> MOs;
03988   MOs.push_back(MachineOperand::CreateFI(FrameIndex));
03989   return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, Size, Alignment);
03990 }
03991 
03992 MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
03993                                                   MachineInstr *MI,
03994                                            const SmallVectorImpl<unsigned> &Ops,
03995                                                   MachineInstr *LoadMI) const {
03996   // Check switch flag
03997   if (NoFusing) return NULL;
03998 
03999   // Unless optimizing for size, don't fold to avoid partial
04000   // register update stalls
04001   if (!MF.getFunction()->getAttributes().
04002         hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize) &&
04003       hasPartialRegUpdate(MI->getOpcode()))
04004     return 0;
04005 
04006   // Determine the alignment of the load.
04007   unsigned Alignment = 0;
04008   if (LoadMI->hasOneMemOperand())
04009     Alignment = (*LoadMI->memoperands_begin())->getAlignment();
04010   else
04011     switch (LoadMI->getOpcode()) {
04012     case X86::AVX2_SETALLONES:
04013     case X86::AVX_SET0:
04014       Alignment = 32;
04015       break;
04016     case X86::V_SET0:
04017     case X86::V_SETALLONES:
04018       Alignment = 16;
04019       break;
04020     case X86::FsFLD0SD:
04021       Alignment = 8;
04022       break;
04023     case X86::FsFLD0SS:
04024       Alignment = 4;
04025       break;
04026     default:
04027       return 0;
04028     }
04029   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
04030     unsigned NewOpc = 0;
04031     switch (MI->getOpcode()) {
04032     default: return NULL;
04033     case X86::TEST8rr:  NewOpc = X86::CMP8ri; break;
04034     case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
04035     case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
04036     case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
04037     }
04038     // Change to CMPXXri r, 0 first.
04039     MI->setDesc(get(NewOpc));
04040     MI->getOperand(1).ChangeToImmediate(0);
04041   } else if (Ops.size() != 1)
04042     return NULL;
04043 
04044   // Make sure the subregisters match.
04045   // Otherwise we risk changing the size of the load.
04046   if (LoadMI->getOperand(0).getSubReg() != MI->getOperand(Ops[0]).getSubReg())
04047     return NULL;
04048 
04049   SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
04050   switch (LoadMI->getOpcode()) {
04051   case X86::V_SET0:
04052   case X86::V_SETALLONES:
04053   case X86::AVX2_SETALLONES:
04054   case X86::AVX_SET0:
04055   case X86::FsFLD0SD:
04056   case X86::FsFLD0SS: {
04057     // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
04058     // Create a constant-pool entry and operands to load from it.
04059 
04060     // Medium and large mode can't fold loads this way.
04061     if (TM.getCodeModel() != CodeModel::Small &&
04062         TM.getCodeModel() != CodeModel::Kernel)
04063       return NULL;
04064 
04065     // x86-32 PIC requires a PIC base register for constant pools.
04066     unsigned PICBase = 0;
04067     if (TM.getRelocationModel() == Reloc::PIC_) {
04068       if (TM.getSubtarget<X86Subtarget>().is64Bit())
04069         PICBase = X86::RIP;
04070       else
04071         // FIXME: PICBase = getGlobalBaseReg(&MF);
04072         // This doesn't work for several reasons.
04073         // 1. GlobalBaseReg may have been spilled.
04074         // 2. It may not be live at MI.
04075         return NULL;
04076     }
04077 
04078     // Create a constant-pool entry.
04079     MachineConstantPool &MCP = *MF.getConstantPool();
04080     Type *Ty;
04081     unsigned Opc = LoadMI->getOpcode();
04082     if (Opc == X86::FsFLD0SS)
04083       Ty = Type::getFloatTy(MF.getFunction()->getContext());
04084     else if (Opc == X86::FsFLD0SD)
04085       Ty = Type::getDoubleTy(MF.getFunction()->getContext());
04086     else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0)
04087       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 8);
04088     else
04089       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
04090 
04091     bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES);
04092     const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
04093                                     Constant::getNullValue(Ty);
04094     unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
04095 
04096     // Create operands to load from the constant pool entry.
04097     MOs.push_back(MachineOperand::CreateReg(PICBase, false));
04098     MOs.push_back(MachineOperand::CreateImm(1));
04099     MOs.push_back(MachineOperand::CreateReg(0, false));
04100     MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
04101     MOs.push_back(MachineOperand::CreateReg(0, false));
04102     break;
04103   }
04104   default: {
04105     if ((LoadMI->getOpcode() == X86::MOVSSrm ||
04106          LoadMI->getOpcode() == X86::VMOVSSrm) &&
04107         MF.getRegInfo().getRegClass(LoadMI->getOperand(0).getReg())->getSize()
04108           > 4)
04109       // These instructions only load 32 bits, we can't fold them if the
04110       // destination register is wider than 32 bits (4 bytes).
04111       return NULL;
04112     if ((LoadMI->getOpcode() == X86::MOVSDrm ||
04113          LoadMI->getOpcode() == X86::VMOVSDrm) &&
04114         MF.getRegInfo().getRegClass(LoadMI->getOperand(0).getReg())->getSize()
04115           > 8)
04116       // These instructions only load 64 bits, we can't fold them if the
04117       // destination register is wider than 64 bits (8 bytes).
04118       return NULL;
04119 
04120     // Folding a normal load. Just copy the load's address operands.
04121     unsigned NumOps = LoadMI->getDesc().getNumOperands();
04122     for (unsigned i = NumOps - X86::AddrNumOperands; i != NumOps; ++i)
04123       MOs.push_back(LoadMI->getOperand(i));
04124     break;
04125   }
04126   }
04127   return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, 0, Alignment);
04128 }
04129 
04130 
04131 bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
04132                                   const SmallVectorImpl<unsigned> &Ops) const {
04133   // Check switch flag
04134   if (NoFusing) return 0;
04135 
04136   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
04137     switch (MI->getOpcode()) {
04138     default: return false;
04139     case X86::TEST8rr:
04140     case X86::TEST16rr:
04141     case X86::TEST32rr:
04142     case X86::TEST64rr:
04143       return true;
04144     case X86::ADD32ri:
04145       // FIXME: AsmPrinter doesn't know how to handle
04146       // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
04147       if (MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
04148         return false;
04149       break;
04150     }
04151   }
04152 
04153   if (Ops.size() != 1)
04154     return false;
04155 
04156   unsigned OpNum = Ops[0];
04157   unsigned Opc = MI->getOpcode();
04158   unsigned NumOps = MI->getDesc().getNumOperands();
04159   bool isTwoAddr = NumOps > 1 &&
04160     MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
04161 
04162   // Folding a memory location into the two-address part of a two-address
04163   // instruction is different than folding it other places.  It requires
04164   // replacing the *two* registers with the memory location.
04165   const DenseMap<unsigned, std::pair<unsigned,unsigned> > *OpcodeTablePtr = 0;
04166   if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
04167     OpcodeTablePtr = &RegOp2MemOpTable2Addr;
04168   } else if (OpNum == 0) { // If operand 0
04169     switch (Opc) {
04170     case X86::MOV8r0:
04171     case X86::MOV16r0:
04172     case X86::MOV32r0:
04173     case X86::MOV64r0: return true;
04174     default: break;
04175     }
04176     OpcodeTablePtr = &RegOp2MemOpTable0;
04177   } else if (OpNum == 1) {
04178     OpcodeTablePtr = &RegOp2MemOpTable1;
04179   } else if (OpNum == 2) {
04180     OpcodeTablePtr = &RegOp2MemOpTable2;
04181   } else if (OpNum == 3) {
04182     OpcodeTablePtr = &RegOp2MemOpTable3;
04183   }
04184 
04185   if (OpcodeTablePtr && OpcodeTablePtr->count(Opc))
04186     return true;
04187   return TargetInstrInfo::canFoldMemoryOperand(MI, Ops);
04188 }
04189 
04190 bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
04191                                 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
04192                                 SmallVectorImpl<MachineInstr*> &NewMIs) const {
04193   DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
04194     MemOp2RegOpTable.find(MI->getOpcode());
04195   if (I == MemOp2RegOpTable.end())
04196     return false;
04197   unsigned Opc = I->second.first;
04198   unsigned Index = I->second.second & TB_INDEX_MASK;
04199   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
04200   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
04201   if (UnfoldLoad && !FoldedLoad)
04202     return false;
04203   UnfoldLoad &= FoldedLoad;
04204   if (UnfoldStore && !FoldedStore)
04205     return false;
04206   UnfoldStore &= FoldedStore;
04207 
04208   const MCInstrDesc &MCID = get(Opc);
04209   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
04210   if (!MI->hasOneMemOperand() &&
04211       RC == &X86::VR128RegClass &&
04212       !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
04213     // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
04214     // conservatively assume the address is unaligned. That's bad for
04215     // performance.
04216     return false;
04217   SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
04218   SmallVector<MachineOperand,2> BeforeOps;
04219   SmallVector<MachineOperand,2> AfterOps;
04220   SmallVector<MachineOperand,4> ImpOps;
04221   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
04222     MachineOperand &Op = MI->getOperand(i);
04223     if (i >= Index && i < Index + X86::AddrNumOperands)
04224       AddrOps.push_back(Op);
04225     else if (Op.isReg() && Op.isImplicit())
04226       ImpOps.push_back(Op);
04227     else if (i < Index)
04228       BeforeOps.push_back(Op);
04229     else if (i > Index)
04230       AfterOps.push_back(Op);
04231   }
04232 
04233   // Emit the load instruction.
04234   if (UnfoldLoad) {
04235     std::pair<MachineInstr::mmo_iterator,
04236               MachineInstr::mmo_iterator> MMOs =
04237       MF.extractLoadMemRefs(MI->memoperands_begin(),
04238                             MI->memoperands_end());
04239     loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
04240     if (UnfoldStore) {
04241       // Address operands cannot be marked isKill.
04242       for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
04243         MachineOperand &MO = NewMIs[0]->getOperand(i);
04244         if (MO.isReg())
04245           MO.setIsKill(false);
04246       }
04247     }
04248   }
04249 
04250   // Emit the data processing instruction.
04251   MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI->getDebugLoc(), true);
04252   MachineInstrBuilder MIB(MF, DataMI);
04253 
04254   if (FoldedStore)
04255     MIB.addReg(Reg, RegState::Define);
04256   for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
04257     MIB.addOperand(BeforeOps[i]);
04258   if (FoldedLoad)
04259     MIB.addReg(Reg);
04260   for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
04261     MIB.addOperand(AfterOps[i]);
04262   for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
04263     MachineOperand &MO = ImpOps[i];
04264     MIB.addReg(MO.getReg(),
04265                getDefRegState(MO.isDef()) |
04266                RegState::Implicit |
04267                getKillRegState(MO.isKill()) |
04268                getDeadRegState(MO.isDead()) |
04269                getUndefRegState(MO.isUndef()));
04270   }
04271   // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
04272   switch (DataMI->getOpcode()) {
04273   default: break;
04274   case X86::CMP64ri32:
04275   case X86::CMP64ri8:
04276   case X86::CMP32ri:
04277   case X86::CMP32ri8:
04278   case X86::CMP16ri:
04279   case X86::CMP16ri8:
04280   case X86::CMP8ri: {
04281     MachineOperand &MO0 = DataMI->getOperand(0);
04282     MachineOperand &MO1 = DataMI->getOperand(1);
04283     if (MO1.getImm() == 0) {
04284       unsigned NewOpc;
04285       switch (DataMI->getOpcode()) {
04286       default: llvm_unreachable("Unreachable!");
04287       case X86::CMP64ri8:
04288       case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
04289       case X86::CMP32ri8:
04290       case X86::CMP32ri:   NewOpc = X86::TEST32rr; break;
04291       case X86::CMP16ri8:
04292       case X86::CMP16ri:   NewOpc = X86::TEST16rr; break;
04293       case X86::CMP8ri:    NewOpc = X86::TEST8rr; break;
04294       }
04295       DataMI->setDesc(get(NewOpc));
04296       MO1.ChangeToRegister(MO0.getReg(), false);
04297     }
04298   }
04299   }
04300   NewMIs.push_back(DataMI);
04301 
04302   // Emit the store instruction.
04303   if (UnfoldStore) {
04304     const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
04305     std::pair<MachineInstr::mmo_iterator,
04306               MachineInstr::mmo_iterator> MMOs =
04307       MF.extractStoreMemRefs(MI->memoperands_begin(),
04308                              MI->memoperands_end());
04309     storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
04310   }
04311 
04312   return true;
04313 }
04314 
04315 bool
04316 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
04317                                   SmallVectorImpl<SDNode*> &NewNodes) const {
04318   if (!N->isMachineOpcode())
04319     return false;
04320 
04321   DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
04322     MemOp2RegOpTable.find(N->getMachineOpcode());
04323   if (I == MemOp2RegOpTable.end())
04324     return false;
04325   unsigned Opc = I->second.first;
04326   unsigned Index = I->second.second & TB_INDEX_MASK;
04327   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
04328   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
04329   const MCInstrDesc &MCID = get(Opc);
04330   MachineFunction &MF = DAG.getMachineFunction();
04331   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
04332   unsigned NumDefs = MCID.NumDefs;
04333   std::vector<SDValue> AddrOps;
04334   std::vector<SDValue> BeforeOps;
04335   std::vector<SDValue> AfterOps;
04336   SDLoc dl(N);
04337   unsigned NumOps = N->getNumOperands();
04338   for (unsigned i = 0; i != NumOps-1; ++i) {
04339     SDValue Op = N->getOperand(i);
04340     if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
04341       AddrOps.push_back(Op);
04342     else if (i < Index-NumDefs)
04343       BeforeOps.push_back(Op);
04344     else if (i > Index-NumDefs)
04345       AfterOps.push_back(Op);
04346   }
04347   SDValue Chain = N->getOperand(NumOps-1);
04348   AddrOps.push_back(Chain);
04349 
04350   // Emit the load instruction.
04351   SDNode *Load = 0;
04352   if (FoldedLoad) {
04353     EVT VT = *RC->vt_begin();
04354     std::pair<MachineInstr::mmo_iterator,
04355               MachineInstr::mmo_iterator> MMOs =
04356       MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
04357                             cast<MachineSDNode>(N)->memoperands_end());
04358     if (!(*MMOs.first) &&
04359         RC == &X86::VR128RegClass &&
04360         !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
04361       // Do not introduce a slow unaligned load.
04362       return false;
04363     unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
04364     bool isAligned = (*MMOs.first) &&
04365                      (*MMOs.first)->getAlignment() >= Alignment;
04366     Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, TM), dl,
04367                               VT, MVT::Other, AddrOps);
04368     NewNodes.push_back(Load);
04369 
04370     // Preserve memory reference information.
04371     cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
04372   }
04373 
04374   // Emit the data processing instruction.
04375   std::vector<EVT> VTs;
04376   const TargetRegisterClass *DstRC = 0;
04377   if (MCID.getNumDefs() > 0) {
04378     DstRC = getRegClass(MCID, 0, &RI, MF);
04379     VTs.push_back(*DstRC->vt_begin());
04380   }
04381   for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
04382     EVT VT = N->getValueType(i);
04383     if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
04384       VTs.push_back(VT);
04385   }
04386   if (Load)
04387     BeforeOps.push_back(SDValue(Load, 0));
04388   std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
04389   SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps);
04390   NewNodes.push_back(NewNode);
04391 
04392   // Emit the store instruction.
04393   if (FoldedStore) {
04394     AddrOps.pop_back();
04395     AddrOps.push_back(SDValue(NewNode, 0));
04396     AddrOps.push_back(Chain);
04397     std::pair<MachineInstr::mmo_iterator,
04398               MachineInstr::mmo_iterator> MMOs =
04399       MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
04400                              cast<MachineSDNode>(N)->memoperands_end());
04401     if (!(*MMOs.first) &&
04402         RC == &X86::VR128RegClass &&
04403         !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
04404       // Do not introduce a slow unaligned store.
04405       return false;
04406     unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
04407     bool isAligned = (*MMOs.first) &&
04408                      (*MMOs.first)->getAlignment() >= Alignment;
04409     SDNode *Store = DAG.getMachineNode(getStoreRegOpcode(0, DstRC,
04410                                                          isAligned, TM),
04411                                        dl, MVT::Other, AddrOps);
04412     NewNodes.push_back(Store);
04413 
04414     // Preserve memory reference information.
04415     cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
04416   }
04417 
04418   return true;
04419 }
04420 
04421 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
04422                                       bool UnfoldLoad, bool UnfoldStore,
04423                                       unsigned *LoadRegIndex) const {
04424   DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
04425     MemOp2RegOpTable.find(Opc);
04426   if (I == MemOp2RegOpTable.end())
04427     return 0;
04428   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
04429   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
04430   if (UnfoldLoad && !FoldedLoad)
04431     return 0;
04432   if (UnfoldStore && !FoldedStore)
04433     return 0;
04434   if (LoadRegIndex)
04435     *LoadRegIndex = I->second.second & TB_INDEX_MASK;
04436   return I->second.first;
04437 }
04438 
04439 bool
04440 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
04441                                      int64_t &Offset1, int64_t &Offset2) const {
04442   if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
04443     return false;
04444   unsigned Opc1 = Load1->getMachineOpcode();
04445   unsigned Opc2 = Load2->getMachineOpcode();
04446   switch (Opc1) {
04447   default: return false;
04448   case X86::MOV8rm:
04449   case X86::MOV16rm:
04450   case X86::MOV32rm:
04451   case X86::MOV64rm:
04452   case X86::LD_Fp32m:
04453   case X86::LD_Fp64m:
04454   case X86::LD_Fp80m:
04455   case X86::MOVSSrm:
04456   case X86::MOVSDrm:
04457   case X86::MMX_MOVD64rm:
04458   case X86::MMX_MOVQ64rm:
04459   case X86::FsMOVAPSrm:
04460   case X86::FsMOVAPDrm:
04461   case X86::MOVAPSrm:
04462   case X86::MOVUPSrm:
04463   case X86::MOVAPDrm:
04464   case X86::MOVDQArm:
04465   case X86::MOVDQUrm:
04466   // AVX load instructions
04467   case X86::VMOVSSrm:
04468   case X86::VMOVSDrm:
04469   case X86::FsVMOVAPSrm:
04470   case X86::FsVMOVAPDrm:
04471   case X86::VMOVAPSrm:
04472   case X86::VMOVUPSrm:
04473   case X86::VMOVAPDrm:
04474   case X86::VMOVDQArm:
04475   case X86::VMOVDQUrm:
04476   case X86::VMOVAPSYrm:
04477   case X86::VMOVUPSYrm:
04478   case X86::VMOVAPDYrm:
04479   case X86::VMOVDQAYrm:
04480   case X86::VMOVDQUYrm:
04481     break;
04482   }
04483   switch (Opc2) {
04484   default: return false;
04485   case X86::MOV8rm:
04486   case X86::MOV16rm:
04487   case X86::MOV32rm:
04488   case X86::MOV64rm:
04489   case X86::LD_Fp32m:
04490   case X86::LD_Fp64m:
04491   case X86::LD_Fp80m:
04492   case X86::MOVSSrm:
04493   case X86::MOVSDrm:
04494   case X86::MMX_MOVD64rm:
04495   case X86::MMX_MOVQ64rm:
04496   case X86::FsMOVAPSrm:
04497   case X86::FsMOVAPDrm:
04498   case X86::MOVAPSrm:
04499   case X86::MOVUPSrm:
04500   case X86::MOVAPDrm:
04501   case X86::MOVDQArm:
04502   case X86::MOVDQUrm:
04503   // AVX load instructions
04504   case X86::VMOVSSrm:
04505   case X86::VMOVSDrm:
04506   case X86::FsVMOVAPSrm:
04507   case X86::FsVMOVAPDrm:
04508   case X86::VMOVAPSrm:
04509   case X86::VMOVUPSrm:
04510   case X86::VMOVAPDrm:
04511   case X86::VMOVDQArm:
04512   case X86::VMOVDQUrm:
04513   case X86::VMOVAPSYrm:
04514   case X86::VMOVUPSYrm:
04515   case X86::VMOVAPDYrm:
04516   case X86::VMOVDQAYrm:
04517   case X86::VMOVDQUYrm:
04518     break;
04519   }
04520 
04521   // Check if chain operands and base addresses match.
04522   if (Load1->getOperand(0) != Load2->getOperand(0) ||
04523       Load1->getOperand(5) != Load2->getOperand(5))
04524     return false;
04525   // Segment operands should match as well.
04526   if (Load1->getOperand(4) != Load2->getOperand(4))
04527     return false;
04528   // Scale should be 1, Index should be Reg0.
04529   if (Load1->getOperand(1) == Load2->getOperand(1) &&
04530       Load1->getOperand(2) == Load2->getOperand(2)) {
04531     if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
04532       return false;
04533 
04534     // Now let's examine the displacements.
04535     if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
04536         isa<ConstantSDNode>(Load2->getOperand(3))) {
04537       Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
04538       Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
04539       return true;
04540     }
04541   }
04542   return false;
04543 }
04544 
04545 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
04546                                            int64_t Offset1, int64_t Offset2,
04547                                            unsigned NumLoads) const {
04548   assert(Offset2 > Offset1);
04549   if ((Offset2 - Offset1) / 8 > 64)
04550     return false;
04551 
04552   unsigned Opc1 = Load1->getMachineOpcode();
04553   unsigned Opc2 = Load2->getMachineOpcode();
04554   if (Opc1 != Opc2)
04555     return false;  // FIXME: overly conservative?
04556 
04557   switch (Opc1) {
04558   default: break;
04559   case X86::LD_Fp32m:
04560   case X86::LD_Fp64m:
04561   case X86::LD_Fp80m:
04562   case X86::MMX_MOVD64rm:
04563   case X86::MMX_MOVQ64rm:
04564     return false;
04565   }
04566 
04567   EVT VT = Load1->getValueType(0);
04568   switch (VT.getSimpleVT().SimpleTy) {
04569   default:
04570     // XMM registers. In 64-bit mode we can be a bit more aggressive since we
04571     // have 16 of them to play with.
04572     if (TM.getSubtargetImpl()->is64Bit()) {
04573       if (NumLoads >= 3)
04574         return false;
04575     } else if (NumLoads) {
04576       return false;
04577     }
04578     break;
04579   case MVT::i8:
04580   case MVT::i16:
04581   case MVT::i32:
04582   case MVT::i64:
04583   case MVT::f32:
04584   case MVT::f64:
04585     if (NumLoads)
04586       return false;
04587     break;
04588   }
04589 
04590   return true;
04591 }
04592 
04593 
04594 bool X86InstrInfo::
04595 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
04596   assert(Cond.size() == 1 && "Invalid X86 branch condition!");
04597   X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
04598   if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
04599     return true;
04600   Cond[0].setImm(GetOppositeBranchCondition(CC));
04601   return false;
04602 }
04603 
04604 bool X86InstrInfo::
04605 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
04606   // FIXME: Return false for x87 stack register classes for now. We can't
04607   // allow any loads of these registers before FpGet_ST0_80.
04608   return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
04609            RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
04610 }
04611 
04612 /// getGlobalBaseReg - Return a virtual register initialized with the
04613 /// the global base register value. Output instructions required to
04614 /// initialize the register in the function entry block, if necessary.
04615 ///
04616 /// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
04617 ///
04618 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
04619   assert(!TM.getSubtarget<X86Subtarget>().is64Bit() &&
04620          "X86-64 PIC uses RIP relative addressing");
04621 
04622   X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
04623   unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
04624   if (GlobalBaseReg != 0)
04625     return GlobalBaseReg;
04626 
04627   // Create the register. The code to initialize it is inserted
04628   // later, by the CGBR pass (below).
04629   MachineRegisterInfo &RegInfo = MF->getRegInfo();
04630   GlobalBaseReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
04631   X86FI->setGlobalBaseReg(GlobalBaseReg);
04632   return GlobalBaseReg;
04633 }
04634 
04635 // These are the replaceable SSE instructions. Some of these have Int variants
04636 // that we don't include here. We don't want to replace instructions selected
04637 // by intrinsics.
04638 static const uint16_t ReplaceableInstrs[][3] = {
04639   //PackedSingle     PackedDouble    PackedInt
04640   { X86::MOVAPSmr,   X86::MOVAPDmr,  X86::MOVDQAmr  },
04641   { X86::MOVAPSrm,   X86::MOVAPDrm,  X86::MOVDQArm  },
04642   { X86::MOVAPSrr,   X86::MOVAPDrr,  X86::MOVDQArr  },
04643   { X86::MOVUPSmr,   X86::MOVUPDmr,  X86::MOVDQUmr  },
04644   { X86::MOVUPSrm,   X86::MOVUPDrm,  X86::MOVDQUrm  },
04645   { X86::MOVNTPSmr,  X86::MOVNTPDmr, X86::MOVNTDQmr },
04646   { X86::ANDNPSrm,   X86::ANDNPDrm,  X86::PANDNrm   },
04647   { X86::ANDNPSrr,   X86::ANDNPDrr,  X86::PANDNrr   },
04648   { X86::ANDPSrm,    X86::ANDPDrm,   X86::PANDrm    },
04649   { X86::ANDPSrr,    X86::ANDPDrr,   X86::PANDrr    },
04650   { X86::ORPSrm,     X86::ORPDrm,    X86::PORrm     },
04651   { X86::ORPSrr,     X86::ORPDrr,    X86::PORrr     },
04652   { X86::XORPSrm,    X86::XORPDrm,   X86::PXORrm    },
04653   { X86::XORPSrr,    X86::XORPDrr,   X86::PXORrr    },
04654   // AVX 128-bit support
04655   { X86::VMOVAPSmr,  X86::VMOVAPDmr,  X86::VMOVDQAmr  },
04656   { X86::VMOVAPSrm,  X86::VMOVAPDrm,  X86::VMOVDQArm  },
04657   { X86::VMOVAPSrr,  X86::VMOVAPDrr,  X86::VMOVDQArr  },
04658   { X86::VMOVUPSmr,  X86::VMOVUPDmr,  X86::VMOVDQUmr  },
04659   { X86::VMOVUPSrm,  X86::VMOVUPDrm,  X86::VMOVDQUrm  },
04660   { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
04661   { X86::VANDNPSrm,  X86::VANDNPDrm,  X86::VPANDNrm   },
04662   { X86::VANDNPSrr,  X86::VANDNPDrr,  X86::VPANDNrr   },
04663   { X86::VANDPSrm,   X86::VANDPDrm,   X86::VPANDrm    },
04664   { X86::VANDPSrr,   X86::VANDPDrr,   X86::VPANDrr    },
04665   { X86::VORPSrm,    X86::VORPDrm,    X86::VPORrm     },
04666   { X86::VORPSrr,    X86::VORPDrr,    X86::VPORrr     },
04667   { X86::VXORPSrm,   X86::VXORPDrm,   X86::VPXORrm    },
04668   { X86::VXORPSrr,   X86::VXORPDrr,   X86::VPXORrr    },
04669   // AVX 256-bit support
04670   { X86::VMOVAPSYmr,   X86::VMOVAPDYmr,   X86::VMOVDQAYmr  },
04671   { X86::VMOVAPSYrm,   X86::VMOVAPDYrm,   X86::VMOVDQAYrm  },
04672   { X86::VMOVAPSYrr,   X86::VMOVAPDYrr,   X86::VMOVDQAYrr  },
04673   { X86::VMOVUPSYmr,   X86::VMOVUPDYmr,   X86::VMOVDQUYmr  },
04674   { X86::VMOVUPSYrm,   X86::VMOVUPDYrm,   X86::VMOVDQUYrm  },
04675   { X86::VMOVNTPSYmr,  X86::VMOVNTPDYmr,  X86::VMOVNTDQYmr }
04676 };
04677 
04678 static const uint16_t ReplaceableInstrsAVX2[][3] = {
04679   //PackedSingle       PackedDouble       PackedInt
04680   { X86::VANDNPSYrm,   X86::VANDNPDYrm,   X86::VPANDNYrm   },
04681   { X86::VANDNPSYrr,   X86::VANDNPDYrr,   X86::VPANDNYrr   },
04682   { X86::VANDPSYrm,    X86::VANDPDYrm,    X86::VPANDYrm    },
04683   { X86::VANDPSYrr,    X86::VANDPDYrr,    X86::VPANDYrr    },
04684   { X86::VORPSYrm,     X86::VORPDYrm,     X86::VPORYrm     },
04685   { X86::VORPSYrr,     X86::VORPDYrr,     X86::VPORYrr     },
04686   { X86::VXORPSYrm,    X86::VXORPDYrm,    X86::VPXORYrm    },
04687   { X86::VXORPSYrr,    X86::VXORPDYrr,    X86::VPXORYrr    },
04688   { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
04689   { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
04690   { X86::VINSERTF128rm,  X86::VINSERTF128rm,  X86::VINSERTI128rm },
04691   { X86::VINSERTF128rr,  X86::VINSERTF128rr,  X86::VINSERTI128rr },
04692   { X86::VPERM2F128rm,   X86::VPERM2F128rm,   X86::VPERM2I128rm },
04693   { X86::VPERM2F128rr,   X86::VPERM2F128rr,   X86::VPERM2I128rr }
04694 };
04695 
04696 // FIXME: Some shuffle and unpack instructions have equivalents in different
04697 // domains, but they require a bit more work than just switching opcodes.
04698 
04699 static const uint16_t *lookup(unsigned opcode, unsigned domain) {
04700   for (unsigned i = 0, e = array_lengthof(ReplaceableInstrs); i != e; ++i)
04701     if (ReplaceableInstrs[i][domain-1] == opcode)
04702       return ReplaceableInstrs[i];
04703   return 0;
04704 }
04705 
04706 static const uint16_t *lookupAVX2(unsigned opcode, unsigned domain) {
04707   for (unsigned i = 0, e = array_lengthof(ReplaceableInstrsAVX2); i != e; ++i)
04708     if (ReplaceableInstrsAVX2[i][domain-1] == opcode)
04709       return ReplaceableInstrsAVX2[i];
04710   return 0;
04711 }
04712 
04713 std::pair<uint16_t, uint16_t>
04714 X86InstrInfo::getExecutionDomain(const MachineInstr *MI) const {
04715   uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
04716   bool hasAVX2 = TM.getSubtarget<X86Subtarget>().hasAVX2();
04717   uint16_t validDomains = 0;
04718   if (domain && lookup(MI->getOpcode(), domain))
04719     validDomains = 0xe;
04720   else if (domain && lookupAVX2(MI->getOpcode(), domain))
04721     validDomains = hasAVX2 ? 0xe : 0x6;
04722   return std::make_pair(domain, validDomains);
04723 }
04724 
04725 void X86InstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
04726   assert(Domain>0 && Domain<4 && "Invalid execution domain");
04727   uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
04728   assert(dom && "Not an SSE instruction");
04729   const uint16_t *table = lookup(MI->getOpcode(), dom);
04730   if (!table) { // try the other table
04731     assert((TM.getSubtarget<X86Subtarget>().hasAVX2() || Domain < 3) &&
04732            "256-bit vector operations only available in AVX2");
04733     table = lookupAVX2(MI->getOpcode(), dom);
04734   }
04735   assert(table && "Cannot change domain");
04736   MI->setDesc(get(table[Domain-1]));
04737 }
04738 
04739 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
04740 void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
04741   NopInst.setOpcode(X86::NOOP);
04742 }
04743 
04744 bool X86InstrInfo::isHighLatencyDef(int opc) const {
04745   switch (opc) {
04746   default: return false;
04747   case X86::DIVSDrm:
04748   case X86::DIVSDrm_Int:
04749   case X86::DIVSDrr:
04750   case X86::DIVSDrr_Int:
04751   case X86::DIVSSrm:
04752   case X86::DIVSSrm_Int:
04753   case X86::DIVSSrr:
04754   case X86::DIVSSrr_Int:
04755   case X86::SQRTPDm:
04756   case X86::SQRTPDr:
04757   case X86::SQRTPSm:
04758   case X86::SQRTPSr:
04759   case X86::SQRTSDm:
04760   case X86::SQRTSDm_Int:
04761   case X86::SQRTSDr:
04762   case X86::SQRTSDr_Int:
04763   case X86::SQRTSSm:
04764   case X86::SQRTSSm_Int:
04765   case X86::SQRTSSr:
04766   case X86::SQRTSSr_Int:
04767   // AVX instructions with high latency
04768   case X86::VDIVSDrm:
04769   case X86::VDIVSDrm_Int:
04770   case X86::VDIVSDrr:
04771   case X86::VDIVSDrr_Int:
04772   case X86::VDIVSSrm:
04773   case X86::VDIVSSrm_Int:
04774   case X86::VDIVSSrr:
04775   case X86::VDIVSSrr_Int:
04776   case X86::VSQRTPDm:
04777   case X86::VSQRTPDr:
04778   case X86::VSQRTPSm:
04779   case X86::VSQRTPSr:
04780   case X86::VSQRTSDm:
04781   case X86::VSQRTSDm_Int:
04782   case X86::VSQRTSDr:
04783   case X86::VSQRTSSm:
04784   case X86::VSQRTSSm_Int:
04785   case X86::VSQRTSSr:
04786     return true;
04787   }
04788 }
04789 
04790 bool X86InstrInfo::
04791 hasHighOperandLatency(const InstrItineraryData *ItinData,
04792                       const MachineRegisterInfo *MRI,
04793                       const MachineInstr *DefMI, unsigned DefIdx,
04794                       const MachineInstr *UseMI, unsigned UseIdx) const {
04795   return isHighLatencyDef(DefMI->getOpcode());
04796 }
04797 
04798 namespace {
04799   /// CGBR - Create Global Base Reg pass. This initializes the PIC
04800   /// global base register for x86-32.
04801   struct CGBR : public MachineFunctionPass {
04802     static char ID;
04803     CGBR() : MachineFunctionPass(ID) {}
04804 
04805     virtual bool runOnMachineFunction(MachineFunction &MF) {
04806       const X86TargetMachine *TM =
04807         static_cast<const X86TargetMachine *>(&MF.getTarget());
04808 
04809       assert(!TM->getSubtarget<X86Subtarget>().is64Bit() &&
04810              "X86-64 PIC uses RIP relative addressing");
04811 
04812       // Only emit a global base reg in PIC mode.
04813       if (TM->getRelocationModel() != Reloc::PIC_)
04814         return false;
04815 
04816       X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
04817       unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
04818 
04819       // If we didn't need a GlobalBaseReg, don't insert code.
04820       if (GlobalBaseReg == 0)
04821         return false;
04822 
04823       // Insert the set of GlobalBaseReg into the first MBB of the function
04824       MachineBasicBlock &FirstMBB = MF.front();
04825       MachineBasicBlock::iterator MBBI = FirstMBB.begin();
04826       DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
04827       MachineRegisterInfo &RegInfo = MF.getRegInfo();
04828       const X86InstrInfo *TII = TM->getInstrInfo();
04829 
04830       unsigned PC;
04831       if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT())
04832         PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
04833       else
04834         PC = GlobalBaseReg;
04835 
04836       // Operand of MovePCtoStack is completely ignored by asm printer. It's
04837       // only used in JIT code emission as displacement to pc.
04838       BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
04839 
04840       // If we're using vanilla 'GOT' PIC style, we should use relative addressing
04841       // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
04842       if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT()) {
04843         // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
04844         BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
04845           .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
04846                                         X86II::MO_GOT_ABSOLUTE_ADDRESS);
04847       }
04848 
04849       return true;
04850     }
04851 
04852     virtual const char *getPassName() const {
04853       return "X86 PIC Global Base Reg Initialization";
04854     }
04855 
04856     virtual void getAnalysisUsage(AnalysisUsage &AU) const {
04857       AU.setPreservesCFG();
04858       MachineFunctionPass::getAnalysisUsage(AU);
04859     }
04860   };
04861 }
04862 
04863 char CGBR::ID = 0;
04864 FunctionPass*
04865 llvm::createGlobalBaseRegPass() { return new CGBR(); }
04866 
04867 namespace {
04868   struct LDTLSCleanup : public MachineFunctionPass {
04869     static char ID;
04870     LDTLSCleanup() : MachineFunctionPass(ID) {}
04871 
04872     virtual bool runOnMachineFunction(MachineFunction &MF) {
04873       X86MachineFunctionInfo* MFI = MF.getInfo<X86MachineFunctionInfo>();
04874       if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
04875         // No point folding accesses if there isn't at least two.
04876         return false;
04877       }
04878 
04879       MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
04880       return VisitNode(DT->getRootNode(), 0);
04881     }
04882 
04883     // Visit the dominator subtree rooted at Node in pre-order.
04884     // If TLSBaseAddrReg is non-null, then use that to replace any
04885     // TLS_base_addr instructions. Otherwise, create the register
04886     // when the first such instruction is seen, and then use it
04887     // as we encounter more instructions.
04888     bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
04889       MachineBasicBlock *BB = Node->getBlock();
04890       bool Changed = false;
04891 
04892       // Traverse the current block.
04893       for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
04894            ++I) {
04895         switch (I->getOpcode()) {
04896           case X86::TLS_base_addr32:
04897           case X86::TLS_base_addr64:
04898             if (TLSBaseAddrReg)
04899               I = ReplaceTLSBaseAddrCall(I, TLSBaseAddrReg);
04900             else
04901               I = SetRegister(I, &TLSBaseAddrReg);
04902             Changed = true;
04903             break;
04904           default:
04905             break;
04906         }
04907       }
04908 
04909       // Visit the children of this block in the dominator tree.
04910       for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end();
04911            I != E; ++I) {
04912         Changed |= VisitNode(*I, TLSBaseAddrReg);
04913       }
04914 
04915       return Changed;
04916     }
04917 
04918     // Replace the TLS_base_addr instruction I with a copy from
04919     // TLSBaseAddrReg, returning the new instruction.
04920     MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr *I,
04921                                          unsigned TLSBaseAddrReg) {
04922       MachineFunction *MF = I->getParent()->getParent();
04923       const X86TargetMachine *TM =
04924           static_cast<const X86TargetMachine *>(&MF->getTarget());
04925       const bool is64Bit = TM->getSubtarget<X86Subtarget>().is64Bit();
04926       const X86InstrInfo *TII = TM->getInstrInfo();
04927 
04928       // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
04929       MachineInstr *Copy = BuildMI(*I->getParent(), I, I->getDebugLoc(),
04930                                    TII->get(TargetOpcode::COPY),
04931                                    is64Bit ? X86::RAX : X86::EAX)
04932                                    .addReg(TLSBaseAddrReg);
04933 
04934       // Erase the TLS_base_addr instruction.
04935       I->eraseFromParent();
04936 
04937       return Copy;
04938     }
04939 
04940     // Create a virtal register in *TLSBaseAddrReg, and populate it by
04941     // inserting a copy instruction after I. Returns the new instruction.
04942     MachineInstr *SetRegister(MachineInstr *I, unsigned *TLSBaseAddrReg) {
04943       MachineFunction *MF = I->getParent()->getParent();
04944       const X86TargetMachine *TM =
04945           static_cast<const X86TargetMachine *>(&MF->getTarget());
04946       const bool is64Bit = TM->getSubtarget<X86Subtarget>().is64Bit();
04947       const X86InstrInfo *TII = TM->getInstrInfo();
04948 
04949       // Create a virtual register for the TLS base address.
04950       MachineRegisterInfo &RegInfo = MF->getRegInfo();
04951       *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
04952                                                       ? &X86::GR64RegClass
04953                                                       : &X86::GR32RegClass);
04954 
04955       // Insert a copy from RAX/EAX to TLSBaseAddrReg.
04956       MachineInstr *Next = I->getNextNode();
04957       MachineInstr *Copy = BuildMI(*I->getParent(), Next, I->getDebugLoc(),
04958                                    TII->get(TargetOpcode::COPY),
04959                                    *TLSBaseAddrReg)
04960                                    .addReg(is64Bit ? X86::RAX : X86::EAX);
04961 
04962       return Copy;
04963     }
04964 
04965     virtual const char *getPassName() const {
04966       return "Local Dynamic TLS Access Clean-up";
04967     }
04968 
04969     virtual void getAnalysisUsage(AnalysisUsage &AU) const {
04970       AU.setPreservesCFG();
04971       AU.addRequired<MachineDominatorTree>();
04972       MachineFunctionPass::getAnalysisUsage(AU);
04973     }
04974   };
04975 }
04976 
04977 char LDTLSCleanup::ID = 0;
04978 FunctionPass*
04979 llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }

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