LLVM API Documentation
00001 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===// 00002 // 00003 // The LLVM Compiler Infrastructure 00004 // 00005 // This file is distributed under the University of Illinois Open Source 00006 // License. See LICENSE.TXT for details. 00007 // 00008 //===----------------------------------------------------------------------===// 00009 // 00010 // This file defines the X86 specific subclass of TargetMachine. 00011 // 00012 //===----------------------------------------------------------------------===// 00013 00014 #include "X86TargetMachine.h" 00015 #include "X86.h" 00016 #include "llvm/CodeGen/MachineFunction.h" 00017 #include "llvm/CodeGen/Passes.h" 00018 #include "llvm/PassManager.h" 00019 #include "llvm/Support/CommandLine.h" 00020 #include "llvm/Support/FormattedStream.h" 00021 #include "llvm/Support/TargetRegistry.h" 00022 #include "llvm/Target/TargetOptions.h" 00023 using namespace llvm; 00024 00025 extern "C" void LLVMInitializeX86Target() { 00026 // Register the target. 00027 RegisterTargetMachine<X86_32TargetMachine> X(TheX86_32Target); 00028 RegisterTargetMachine<X86_64TargetMachine> Y(TheX86_64Target); 00029 } 00030 00031 void X86_32TargetMachine::anchor() { } 00032 00033 X86_32TargetMachine::X86_32TargetMachine(const Target &T, StringRef TT, 00034 StringRef CPU, StringRef FS, 00035 const TargetOptions &Options, 00036 Reloc::Model RM, CodeModel::Model CM, 00037 CodeGenOpt::Level OL) 00038 : X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false), 00039 DL(getSubtargetImpl()->isTargetDarwin() ? 00040 "e-p:32:32-f64:32:64-i64:32:64-f80:128:128-f128:128:128-" 00041 "n8:16:32-S128" : 00042 (getSubtargetImpl()->isTargetCygMing() || 00043 getSubtargetImpl()->isTargetWindows()) ? 00044 "e-p:32:32-f64:64:64-i64:64:64-f80:32:32-f128:128:128-" 00045 "n8:16:32-S32" : 00046 "e-p:32:32-f64:32:64-i64:32:64-f80:32:32-f128:128:128-" 00047 "n8:16:32-S128"), 00048 InstrInfo(*this), 00049 TLInfo(*this), 00050 TSInfo(*this), 00051 JITInfo(*this) { 00052 initAsmInfo(); 00053 } 00054 00055 void X86_64TargetMachine::anchor() { } 00056 00057 X86_64TargetMachine::X86_64TargetMachine(const Target &T, StringRef TT, 00058 StringRef CPU, StringRef FS, 00059 const TargetOptions &Options, 00060 Reloc::Model RM, CodeModel::Model CM, 00061 CodeGenOpt::Level OL) 00062 : X86TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true), 00063 // The x32 ABI dictates the ILP32 programming model for x64. 00064 DL(getSubtargetImpl()->isTarget64BitILP32() ? 00065 "e-p:32:32-s:64-f64:64:64-i64:64:64-f80:128:128-f128:128:128-" 00066 "n8:16:32:64-S128" : 00067 "e-p:64:64-s:64-f64:64:64-i64:64:64-f80:128:128-f128:128:128-" 00068 "n8:16:32:64-S128"), 00069 InstrInfo(*this), 00070 TLInfo(*this), 00071 TSInfo(*this), 00072 JITInfo(*this) { 00073 initAsmInfo(); 00074 } 00075 00076 /// X86TargetMachine ctor - Create an X86 target. 00077 /// 00078 X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT, 00079 StringRef CPU, StringRef FS, 00080 const TargetOptions &Options, 00081 Reloc::Model RM, CodeModel::Model CM, 00082 CodeGenOpt::Level OL, 00083 bool is64Bit) 00084 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 00085 Subtarget(TT, CPU, FS, Options.StackAlignmentOverride, is64Bit), 00086 FrameLowering(*this, Subtarget), 00087 InstrItins(Subtarget.getInstrItineraryData()){ 00088 // Determine the PICStyle based on the target selected. 00089 if (getRelocationModel() == Reloc::Static) { 00090 // Unless we're in PIC or DynamicNoPIC mode, set the PIC style to None. 00091 Subtarget.setPICStyle(PICStyles::None); 00092 } else if (Subtarget.is64Bit()) { 00093 // PIC in 64 bit mode is always rip-rel. 00094 Subtarget.setPICStyle(PICStyles::RIPRel); 00095 } else if (Subtarget.isTargetCygMing()) { 00096 Subtarget.setPICStyle(PICStyles::None); 00097 } else if (Subtarget.isTargetDarwin()) { 00098 if (getRelocationModel() == Reloc::PIC_) 00099 Subtarget.setPICStyle(PICStyles::StubPIC); 00100 else { 00101 assert(getRelocationModel() == Reloc::DynamicNoPIC); 00102 Subtarget.setPICStyle(PICStyles::StubDynamicNoPIC); 00103 } 00104 } else if (Subtarget.isTargetELF()) { 00105 Subtarget.setPICStyle(PICStyles::GOT); 00106 } 00107 00108 // default to hard float ABI 00109 if (Options.FloatABIType == FloatABI::Default) 00110 this->Options.FloatABIType = FloatABI::Hard; 00111 } 00112 00113 //===----------------------------------------------------------------------===// 00114 // Command line options for x86 00115 //===----------------------------------------------------------------------===// 00116 static cl::opt<bool> 00117 UseVZeroUpper("x86-use-vzeroupper", 00118 cl::desc("Minimize AVX to SSE transition penalty"), 00119 cl::init(true)); 00120 00121 // Temporary option to control early if-conversion for x86 while adding machine 00122 // models. 00123 static cl::opt<bool> 00124 X86EarlyIfConv("x86-early-ifcvt", 00125 cl::desc("Enable early if-conversion on X86")); 00126 00127 //===----------------------------------------------------------------------===// 00128 // X86 Analysis Pass Setup 00129 //===----------------------------------------------------------------------===// 00130 00131 void X86TargetMachine::addAnalysisPasses(PassManagerBase &PM) { 00132 // Add first the target-independent BasicTTI pass, then our X86 pass. This 00133 // allows the X86 pass to delegate to the target independent layer when 00134 // appropriate. 00135 PM.add(createBasicTargetTransformInfoPass(getTargetLowering())); 00136 PM.add(createX86TargetTransformInfoPass(this)); 00137 } 00138 00139 00140 //===----------------------------------------------------------------------===// 00141 // Pass Pipeline Configuration 00142 //===----------------------------------------------------------------------===// 00143 00144 namespace { 00145 /// X86 Code Generator Pass Configuration Options. 00146 class X86PassConfig : public TargetPassConfig { 00147 public: 00148 X86PassConfig(X86TargetMachine *TM, PassManagerBase &PM) 00149 : TargetPassConfig(TM, PM) {} 00150 00151 X86TargetMachine &getX86TargetMachine() const { 00152 return getTM<X86TargetMachine>(); 00153 } 00154 00155 const X86Subtarget &getX86Subtarget() const { 00156 return *getX86TargetMachine().getSubtargetImpl(); 00157 } 00158 00159 virtual bool addInstSelector(); 00160 virtual bool addILPOpts(); 00161 virtual bool addPreRegAlloc(); 00162 virtual bool addPostRegAlloc(); 00163 virtual bool addPreEmitPass(); 00164 }; 00165 } // namespace 00166 00167 TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) { 00168 return new X86PassConfig(this, PM); 00169 } 00170 00171 bool X86PassConfig::addInstSelector() { 00172 // Install an instruction selector. 00173 addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel())); 00174 00175 // For ELF, cleanup any local-dynamic TLS accesses. 00176 if (getX86Subtarget().isTargetELF() && getOptLevel() != CodeGenOpt::None) 00177 addPass(createCleanupLocalDynamicTLSPass()); 00178 00179 // For 32-bit, prepend instructions to set the "global base reg" for PIC. 00180 if (!getX86Subtarget().is64Bit()) 00181 addPass(createGlobalBaseRegPass()); 00182 00183 return false; 00184 } 00185 00186 bool X86PassConfig::addILPOpts() { 00187 if (X86EarlyIfConv && getX86Subtarget().hasCMov()) { 00188 addPass(&EarlyIfConverterID); 00189 return true; 00190 } 00191 return false; 00192 } 00193 00194 bool X86PassConfig::addPreRegAlloc() { 00195 return false; // -print-machineinstr shouldn't print after this. 00196 } 00197 00198 bool X86PassConfig::addPostRegAlloc() { 00199 addPass(createX86FloatingPointStackifierPass()); 00200 return true; // -print-machineinstr should print after this. 00201 } 00202 00203 bool X86PassConfig::addPreEmitPass() { 00204 bool ShouldPrint = false; 00205 if (getOptLevel() != CodeGenOpt::None && getX86Subtarget().hasSSE2()) { 00206 addPass(createExecutionDependencyFixPass(&X86::VR128RegClass)); 00207 ShouldPrint = true; 00208 } 00209 00210 if (getX86Subtarget().hasAVX() && UseVZeroUpper) { 00211 addPass(createX86IssueVZeroUpperPass()); 00212 ShouldPrint = true; 00213 } 00214 00215 if (getOptLevel() != CodeGenOpt::None && 00216 getX86Subtarget().padShortFunctions()) { 00217 addPass(createX86PadShortFunctions()); 00218 ShouldPrint = true; 00219 } 00220 if (getOptLevel() != CodeGenOpt::None && 00221 getX86Subtarget().LEAusesAG()){ 00222 addPass(createX86FixupLEAs()); 00223 ShouldPrint = true; 00224 } 00225 00226 return ShouldPrint; 00227 } 00228 00229 bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM, 00230 JITCodeEmitter &JCE) { 00231 PM.add(createX86JITCodeEmitterPass(*this, JCE)); 00232 00233 return false; 00234 }