58 cl::desc(
"Enable the machine combiner pass"),
63 cl::desc(
"Enable the tile register allocation pass"),
115 if (TT.isOSBinFormatMachO()) {
117 return std::make_unique<X86_64MachoTargetObjectFile>();
118 return std::make_unique<TargetLoweringObjectFileMachO>();
121 if (TT.isOSBinFormatCOFF())
122 return std::make_unique<TargetLoweringObjectFileCOFF>();
125 return std::make_unique<X86_64ELFTargetObjectFile>();
126 return std::make_unique<X86ELFTargetObjectFile>();
130 std::optional<Reloc::Model> RM) {
141 if (TT.isOSDarwin()) {
146 if (TT.isOSWindows() &&
is64Bit)
158 if (!TT.isOSDarwin())
173 bool Is64Bit = TT.isX86_64();
189 std::optional<Reloc::Model>
RM,
190 std::optional<CodeModel::Model> CM,
201 if (TT.isPS() || TT.isOSBinFormatMachO()) {
202 this->Options.TrapUnreachable = true;
203 this->Options.NoTrapAfterNoreturn = TT.isOSBinFormatMachO();
218 Attribute CPUAttr =
F.getFnAttribute(
"target-cpu");
219 Attribute TuneAttr =
F.getFnAttribute(
"tune-cpu");
220 Attribute FSAttr =
F.getFnAttribute(
"target-features");
228 : CPU ==
"x86-64" ?
"generic"
240 unsigned PreferVectorWidthOverride = 0;
241 Attribute PreferVecWidthAttr =
F.getFnAttribute(
"prefer-vector-width");
242 if (PreferVecWidthAttr.
isValid()) {
248 PreferVectorWidthOverride = Width;
253 unsigned RequiredVectorWidth = UINT32_MAX;
254 Attribute MinLegalVecWidthAttr =
F.getFnAttribute(
"min-legal-vector-width");
255 if (MinLegalVecWidthAttr.
isValid()) {
261 RequiredVectorWidth = Width;
272 unsigned FSStart =
Key.size();
279 bool SoftFloat =
F.getFnAttribute(
"use-soft-float").getValueAsBool();
283 Key += FS.empty() ?
"+soft-float" :
"+soft-float,";
289 FS =
Key.substr(FSStart);
291 auto &
I = SubtargetMap[
Key];
293 I = std::make_unique<X86Subtarget>(
295 MaybeAlign(
F.getParent()->getOverrideStackAlignment()),
296 PreferVectorWidthOverride, RequiredVectorWidth);
320 unsigned DestAS)
const {
321 assert(SrcAS != DestAS &&
"Expected different address spaces!");
324 return SrcAS < 256 && DestAS < 256;
368 void addIRPasses()
override;
369 bool addInstSelector()
override;
370 bool addIRTranslator()
override;
371 bool addLegalizeMachineIR()
override;
372 void addPreRegBankSelect()
override;
373 bool addRegBankSelect()
override;
374 bool addGlobalInstructionSelect()
override;
375 void addPreLegalizeMachineIR()
override;
376 bool addILPOpts()
override;
377 bool addPreISel()
override;
378 void addMachineSSAOptimization()
override;
379 void addPreRegAlloc()
override;
380 bool addPostFastRegAllocRewrite()
override;
381 void addPostRegAlloc()
override;
382 void addPreEmitPass()
override;
383 void addPreEmitPass2()
override;
384 void addPreSched2()
override;
385 bool addRegAssignAndRewriteOptimized()
override;
387 std::unique_ptr<CSEConfigBase> getCSEConfig()
const override;
393 X86ExecutionDomainFix() : ExecutionDomainFix(
ID,
X86::VR128XRegClass) {}
394 StringRef getPassName()
const override {
395 return "X86 Execution Dependency Fix";
398char X86ExecutionDomainFix::ID;
403 "X86 Execution Domain Fix",
false,
false)
409 return new X86PassConfig(*
this, PM);
419void X86PassConfig::addIRPasses() {
440 const Triple &TT = TM->getTargetTriple();
441 if (TT.isOSWindows()) {
445 if (TM->Options.JMCInstrument)
449bool X86PassConfig::addInstSelector() {
454 if (TM->getTargetTriple().isOSBinFormatELF() &&
463bool X86PassConfig::addIRTranslator() {
468void X86PassConfig::addPreRegBankSelect() {
474bool X86PassConfig::addLegalizeMachineIR() {
479bool X86PassConfig::addRegBankSelect() {
484bool X86PassConfig::addGlobalInstructionSelect() {
487 if (isGlobalISelAbortEnabled())
492void X86PassConfig::addPreLegalizeMachineIR() {
498bool X86PassConfig::addILPOpts() {
506bool X86PassConfig::addPreISel() {
508 const Triple &
TT = TM->getTargetTriple();
509 if (
TT.isOSWindows() &&
TT.isX86_32())
514void X86PassConfig::addPreRegAlloc() {
535void X86PassConfig::addMachineSSAOptimization() {
540void X86PassConfig::addPostRegAlloc() {
551void X86PassConfig::addPreSched2() {
556void X86PassConfig::addPreEmitPass() {
558 addPass(
new X86ExecutionDomainFix());
577void X86PassConfig::addPreEmitPass2() {
578 const Triple &
TT = TM->getTargetTriple();
579 const MCAsmInfo &MAI = TM->getMCAsmInfo();
596 if (
TT.isOSWindows() &&
TT.isX86_64())
602 if (!
TT.isOSDarwin() &&
603 (!
TT.isOSWindows() ||
607 if (
TT.isOSWindows()) {
625 return M->getModuleFlag(
"kcfi") ||
627 (
M->getFunction(
"objc_retainAutoreleasedReturnValue") ||
628 M->getFunction(
"objc_unsafeClaimAutoreleasedReturnValue")));
633 if (
TT.isOSWindows() &&
TT.isX86_64())
637bool X86PassConfig::addPostFastRegAllocRewrite() {
642std::unique_ptr<CSEConfigBase> X86PassConfig::getCSEConfig()
const {
653bool X86PassConfig::addRegAssignAndRewriteOptimized() {
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
static std::unique_ptr< TargetLoweringObjectFile > createTLOF(const Triple &TT)
static Reloc::Model getEffectiveRelocModel()
This file contains the simple types necessary to represent the attributes associated with functions a...
Provides analysis for continuously CSEing during GISel passes.
This file describes how to lower LLVM calls to machine code calls.
This file declares the IRTranslator pass.
Register const TargetRegisterInfo * TRI
#define INITIALIZE_PASS_DEPENDENCY(depName)
#define INITIALIZE_PASS_END(passName, arg, name, cfg, analysis)
#define INITIALIZE_PASS_BEGIN(passName, arg, name, cfg, analysis)
This file describes the interface of the MachineFunctionPass responsible for assigning the generic vi...
const GCNTargetMachine & getTM(const GCNSubtarget *STI)
This file defines the SmallString class.
static TableGen::Emitter::Opt Y("gen-skeleton-entry", EmitSkeleton, "Generate example skeleton entry")
Target-Independent Code Generator Pass Configuration Options pass.
static std::unique_ptr< TargetLoweringObjectFile > createTLOF()
#define LLVM_C_ABI
LLVM_C_ABI is the export/visibility macro used to mark symbols declared in llvm-c as exported when bu...
cl::opt< bool > X86EnableMachineCombinerPass
static bool is64Bit(const char *name)
static cl::opt< bool > EnableTileRAPass("x86-tile-ra", cl::desc("Enable the tile register allocation pass"), cl::init(true), cl::Hidden)
static CodeModel::Model getEffectiveX86CodeModel(const Triple &TT, std::optional< CodeModel::Model > CM, bool JIT)
static bool onlyAllocateTileRegisters(const TargetRegisterInfo &TRI, const MachineRegisterInfo &MRI, const Register Reg)
LLVM_C_ABI void LLVMInitializeX86Target()
cl::opt< bool > X86EnableMachineCombinerPass("x86-machine-combiner", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)
Functions, function parameters, and return types can have attributes to indicate how they should be t...
LLVM_ABI StringRef getValueAsString() const
Return the attribute's value as a string.
bool isValid() const
Return true if the attribute is any kind of attribute.
CodeGenTargetMachineImpl(const Target &T, StringRef DataLayoutString, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOptLevel OL)
virtual void reset()
Reset internal state.
Lightweight error class with error context and mandatory checking.
This pass is responsible for selecting generic machine instructions to target-specific instructions.
This class is intended to be used as a base class for asm properties and features specific to the tar...
ExceptionHandling getExceptionHandlingType() const
Function & getFunction()
Return the LLVM function that this machine code represents.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
const TargetRegisterClass * getRegClass(Register Reg) const
Return the register class of the specified virtual register.
A Module instance is used to store all the information related to an LLVM module.
PassRegistry - This class manages the registration and intitialization of the pass subsystem as appli...
static LLVM_ABI PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Wrapper class representing virtual and physical registers.
Instances of this class encapsulate one diagnostic report, allowing printing to a raw_ostream as a ca...
Represents a range in source code.
A ScheduleDAG for scheduling lists of MachineInstr.
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Add a postprocessing step to the DAG builder.
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
Represent a constant reference to a string, i.e.
bool getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
void setSupportsDebugEntryValues(bool Enable)
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with.
const Triple & getTargetTriple() const
void setMachineOutliner(bool Enable)
unsigned getPointerSize(unsigned AS) const
Get the pointer size for this target.
std::unique_ptr< const MCSubtargetInfo > STI
Target-Independent Code Generator Pass Configuration Options.
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
virtual void addMachineSSAOptimization()
addMachineSSAOptimization - Add standard passes that optimize machine instructions in SSA form.
virtual bool addRegAssignAndRewriteOptimized()
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
TargetSubtargetInfo - Generic base class for all target subtargets.
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
X86MachineFunctionInfo - This class is derived from MachineFunction and contains private X86 target-s...
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override
Returns true if a cast between SrcAS and DestAS is a noop.
MachineFunctionInfo * createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F, const TargetSubtargetInfo *STI) const override
Create the target's instance of MachineFunctionInfo.
yaml::MachineFunctionInfo * convertFuncInfoToYAML(const MachineFunction &MF) const override
Allocate and initialize an instance of the YAML representation of the MachineFunctionInfo.
const X86Subtarget * getSubtargetImpl() const =delete
ScheduleDAGInstrs * createMachineScheduler(MachineSchedContext *C) const override
Create an instance of ScheduleDAGInstrs to be run within the standard MachineScheduler pass for this ...
ScheduleDAGInstrs * createPostMachineScheduler(MachineSchedContext *C) const override
Similar to createMachineScheduler but used when postRA machine scheduling is enabled.
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &, PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange) const override
Parse out the target's MachineFunctionInfo from the YAML reprsentation.
~X86TargetMachine() override
TargetTransformInfo getTargetTransformInfo(const Function &F) const override
Get a TargetTransformInfo implementation for the target.
yaml::MachineFunctionInfo * createDefaultFuncInfoYAML() const override
Allocate and return a default initialized instance of the YAML representation for the MachineFunction...
X86TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, std::optional< Reloc::Model > RM, std::optional< CodeModel::Model > CM, CodeGenOptLevel OL, bool JIT)
Create an X86 target.
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
@ C
The default llvm calling convention, compatible with C.
@ X86
Windows x64, Windows Itanium (IA-64)
initializer< Ty > init(const Ty &Val)
This is an optimization pass for GlobalISel generic memory operations.
ScheduleDAGMILive * createSchedLive(MachineSchedContext *C)
Create the standard converging machine scheduler.
LLVM_ABI FunctionPass * createIndirectBrExpandPass()
void initializeX86LoadValueInjectionLoadHardeningLegacyPass(PassRegistry &)
FunctionPass * createX86LowerAMXIntrinsicsLegacyPass()
FunctionPass * createX86CompressEVEXLegacyPass()
FunctionPass * createX86FastTileConfigLegacyPass()
void initializeX86PartialReductionLegacyPass(PassRegistry &)
FunctionPass * createX86DomainReassignmentLegacyPass()
FunctionPass * createX86ExpandPseudoLegacyPass()
Returns an instance of the pseudo instruction expansion pass.
LLVM_ABI ModulePass * createJMCInstrumenterPass()
JMC instrument pass.
FunctionPass * createX86OptimizeLEAsLegacyPass()
void initializeCompressEVEXLegacyPass(PassRegistry &)
LLVM_ABI FunctionPass * createGreedyRegisterAllocator()
Greedy register allocation pass - This pass implements a global register allocator for optimized buil...
void initializeX86PostLegalizerCombinerLegacyPass(PassRegistry &)
FunctionPass * createX86DynAllocaExpanderLegacyPass()
void initializeX86DomainReassignmentLegacyPass(PassRegistry &)
@ DwarfCFI
DWARF-like instruction based exceptions.
FunctionPass * createX86TileConfigLegacyPass()
LLVM_ABI FunctionPass * createPseudoProbeInserter()
This pass inserts pseudo probe annotation for callsite profiling.
Target & getTheX86_32Target()
FunctionPass * createX86AvoidStoreForwardingBlocksLegacyPass()
void initializeX86LowerAMXIntrinsicsLegacyPassPass(PassRegistry &)
FunctionPass * createX86InsertX87WaitLegacyPass()
FunctionPass * createX86PartialReductionLegacyPass()
void initializeX86CmovConversionLegacyPass(PassRegistry &)
void initializeX86DynAllocaExpanderLegacyPass(PassRegistry &)
FunctionPass * createX86FixupSetCCLegacyPass()
LLVM_ABI std::unique_ptr< CSEConfigBase > getStandardCSEConfigForOpt(CodeGenOptLevel Level)
void initializeX86FastPreTileConfigLegacyPass(PassRegistry &)
FunctionPass * createX86SpeculativeExecutionSideEffectSuppressionLegacyPass()
LLVM_ABI char & EarlyIfConverterLegacyID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions.
FunctionPass * createX86LoadValueInjectionLoadHardeningLegacyPass()
FunctionPass * createX86PadShortFunctions()
Return a pass that pads short functions with NOOPs.
std::unique_ptr< ScheduleDAGMutation > createX86MacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createX86MacroFusionDAGMutation()); to X86TargetMachine::c...
LLVM_ABI void initializeMachineKCFILegacyPass(PassRegistry &)
LLVM_ABI char & MachineCombinerID
This pass performs instruction combining using trace metrics to estimate critical-path and resource d...
LLVM_ABI FunctionPass * createUnpackMachineBundlesLegacy(std::function< bool(const MachineFunction &)> Ftor)
static Reloc::Model getEffectiveRelocModel(std::optional< Reloc::Model > RM)
void initializeX86FastTileConfigLegacyPass(PassRegistry &)
void initializeX86FixupVectorConstantsLegacyPass(PassRegistry &)
FunctionPass * createX86IndirectBranchTrackingLegacyPass()
void initializeX86AsmPrinterPass(PassRegistry &)
FunctionPass * createX86LowerTileCopyLegacyPass()
void initializeX86ExpandPseudoLegacyPass(PassRegistry &)
ScheduleDAGMI * createSchedPostRA(MachineSchedContext *C)
Create a generic scheduler with no vreg liveness or DAG mutation passes.
FunctionPass * createX86CmovConversionLegacyPass()
FunctionPass * createX86ArgumentStackSlotLegacyPass()
LLVM_ABI FunctionPass * createKCFIPass()
Lowers KCFI operand bundles for indirect calls.
void initializeX86SpeculativeExecutionSideEffectSuppressionLegacyPass(PassRegistry &)
void initializeX86FixupInstTuningLegacyPass(PassRegistry &)
LLVM_ABI char & LiveRangeShrinkID
LiveRangeShrink pass.
void initializeX86FlagsCopyLoweringLegacyPass(PassRegistry &)
FunctionPass * createX86PostLegalizerCombinerLegacy()
void initializeX86AvoidTrailingCallLegacyPassPass(PassRegistry &)
FunctionPass * createX86ISelDag(X86TargetMachine &TM, CodeGenOptLevel OptLevel)
This pass converts a legalized DAG into a X86-specific DAG, ready for instruction scheduling.
FunctionPass * createX86FixupLEAsLegacyPass()
FunctionPass * createX86CallFrameOptimizationLegacyPass()
CodeGenOptLevel
Code generation optimization level.
void initializeX86CallFrameOptimizationLegacyPass(PassRegistry &)
LLVM_ABI FunctionPass * createCFGuardLongjmpPass()
Creates CFGuard longjmp target identification pass.
FunctionPass * createX86FlagsCopyLoweringLegacyPass()
FunctionPass * createCleanupLocalDynamicTLSLegacyPass()
LLVM_ATTRIBUTE_VISIBILITY_DEFAULT AnalysisKey InnerAnalysisManagerProxy< AnalysisManagerT, IRUnitT, ExtraArgTs... >::Key
void initializeX86FixupBWInstLegacyPass(PassRegistry &)
void initializeX86LoadValueInjectionRetHardeningLegacyPass(PassRegistry &)
void initializeX86FPStackifierLegacyPass(PassRegistry &)
void initializeX86LowerTileCopyLegacyPass(PassRegistry &)
LLVM_ABI FunctionPass * createInterleavedAccessPass()
InterleavedAccess Pass - This pass identifies and matches interleaved memory accesses to target speci...
void initializeX86SpeculativeLoadHardeningLegacyPass(PassRegistry &)
void initializeX86TileConfigLegacyPass(PassRegistry &)
LLVM_ABI void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
void initializeFixupLEAsLegacyPass(PassRegistry &)
FunctionPass * createX86PreTileConfigLegacyPass()
FunctionPass * createX86InsertVZeroUpperLegacyPass()
FunctionPass * createX86SpeculativeLoadHardeningLegacyPass()
void initializeX86LowerAMXTypeLegacyPassPass(PassRegistry &)
FunctionPass * createX86ReturnThunksLegacyPass()
void initializeX86ArgumentStackSlotLegacyPass(PassRegistry &)
LLVM_ABI FunctionPass * createCFGuardPass()
Insert Control Flow Guard checks on indirect function calls.
FunctionPass * createX86FixupBWInstsLegacyPass()
FunctionPass * createX86PreLegalizerCombinerLegacy()
FunctionPass * createX86FPStackifierLegacyPass()
void initializeX86PreTileConfigLegacyPass(PassRegistry &)
FunctionPass * createX86SuppressAPXForRelocationLegacyPass()
FunctionPass * createX86FastPreTileConfigLegacyPass()
FunctionPass * createX86LoadValueInjectionRetHardeningLegacyPass()
FunctionPass * createX86LowerAMXTypeLegacyPass()
LLVM_ABI FunctionPass * createEHContGuardTargetsPass()
Creates Windows EH Continuation Guard target identification pass.
void initializeX86ReturnThunksLegacyPass(PassRegistry &)
void initializeX86PreLegalizerCombinerLegacyPass(PassRegistry &)
void initializeX86SuppressAPXForRelocationLegacyPass(PassRegistry &)
FunctionPass * createX86WinEHStateLegacyPass()
FunctionPass * createX86FixupVectorConstantsLegacyPass()
void initializeX86FixupSetCCLegacyPass(PassRegistry &)
void initializeWinEHStateLegacyPass(PassRegistry &)
FunctionPass * createX86IndirectThunksPass()
This pass creates the thunks for the retpoline feature.
LLVM_ABI FunctionPass * createAtomicExpandLegacyPass()
AtomicExpandPass - At IR level this pass replace atomic instructions with __atomic_* library calls,...
FunctionPass * createX86WinEHUnwindV2LegacyPass()
BumpPtrAllocatorImpl<> BumpPtrAllocator
The standard BumpPtrAllocator which just uses the default template parameters.
Target & getTheX86_64Target()
FunctionPass * createX86FixupInstTuningLegacyPass()
LLVM_ABI FunctionPass * createCFIInstrInserter()
Creates CFI Instruction Inserter pass.
void initializeX86ExecutionDomainFixPass(PassRegistry &)
LLVM_ABI FunctionPass * createBreakFalseDepsLegacyPass()
Creates Break False Dependencies pass.
void initializeX86DAGToDAGISelLegacyPass(PassRegistry &)
void initializeX86OptimizeLEAsLegacyPass(PassRegistry &)
void initializeX86AvoidSFBLegacyPass(PassRegistry &)
void initializeX86WinEHUnwindV2LegacyPass(PassRegistry &)
FunctionPass * createX86AvoidTrailingCallLegacyPass()
LLVM_ABI void reportFatalUsageError(Error Err)
Report a fatal error that does not indicate a bug in LLVM.
FunctionPass * createX86GlobalBaseRegLegacyPass()
MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...
static FuncInfoTy * create(BumpPtrAllocator &Allocator, const Function &F, const SubtargetTy *STI)
Factory function: default behavior is to call new using the supplied allocator.
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
RegisterTargetMachine - Helper template for registering a target machine implementation,...
Targets should override this in a way that mirrors the implementation of llvm::MachineFunctionInfo.