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XCoreRegisterInfo.cpp
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00001 //===-- XCoreRegisterInfo.cpp - XCore Register Information ----------------===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file contains the XCore implementation of the MRegisterInfo class.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #include "XCoreRegisterInfo.h"
00015 #include "XCore.h"
00016 #include "XCoreInstrInfo.h"
00017 #include "XCoreMachineFunctionInfo.h"
00018 #include "llvm/ADT/BitVector.h"
00019 #include "llvm/ADT/STLExtras.h"
00020 #include "llvm/CodeGen/MachineFrameInfo.h"
00021 #include "llvm/CodeGen/MachineFunction.h"
00022 #include "llvm/CodeGen/MachineInstrBuilder.h"
00023 #include "llvm/CodeGen/MachineModuleInfo.h"
00024 #include "llvm/CodeGen/MachineRegisterInfo.h"
00025 #include "llvm/CodeGen/RegisterScavenging.h"
00026 #include "llvm/IR/Function.h"
00027 #include "llvm/IR/Type.h"
00028 #include "llvm/Support/Debug.h"
00029 #include "llvm/Support/ErrorHandling.h"
00030 #include "llvm/Support/MathExtras.h"
00031 #include "llvm/Support/raw_ostream.h"
00032 #include "llvm/Target/TargetFrameLowering.h"
00033 #include "llvm/Target/TargetMachine.h"
00034 #include "llvm/Target/TargetOptions.h"
00035 
00036 using namespace llvm;
00037 
00038 #define DEBUG_TYPE "xcore-reg-info"
00039 
00040 #define GET_REGINFO_TARGET_DESC
00041 #include "XCoreGenRegisterInfo.inc"
00042 
00043 XCoreRegisterInfo::XCoreRegisterInfo()
00044   : XCoreGenRegisterInfo(XCore::LR) {
00045 }
00046 
00047 // helper functions
00048 static inline bool isImmUs(unsigned val) {
00049   return val <= 11;
00050 }
00051 
00052 static inline bool isImmU6(unsigned val) {
00053   return val < (1 << 6);
00054 }
00055 
00056 static inline bool isImmU16(unsigned val) {
00057   return val < (1 << 16);
00058 }
00059 
00060 
00061 static void InsertFPImmInst(MachineBasicBlock::iterator II,
00062                             const XCoreInstrInfo &TII,
00063                             unsigned Reg, unsigned FrameReg, int Offset ) {
00064   MachineInstr &MI = *II;
00065   MachineBasicBlock &MBB = *MI.getParent();
00066   DebugLoc dl = MI.getDebugLoc();
00067 
00068   switch (MI.getOpcode()) {
00069   case XCore::LDWFI:
00070     BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg)
00071           .addReg(FrameReg)
00072           .addImm(Offset)
00073           .addMemOperand(*MI.memoperands_begin());
00074     break;
00075   case XCore::STWFI:
00076     BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus))
00077           .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
00078           .addReg(FrameReg)
00079           .addImm(Offset)
00080           .addMemOperand(*MI.memoperands_begin());
00081     break;
00082   case XCore::LDAWFI:
00083     BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg)
00084           .addReg(FrameReg)
00085           .addImm(Offset);
00086     break;
00087   default:
00088     llvm_unreachable("Unexpected Opcode");
00089   }
00090 }
00091 
00092 static void InsertFPConstInst(MachineBasicBlock::iterator II,
00093                               const XCoreInstrInfo &TII,
00094                               unsigned Reg, unsigned FrameReg,
00095                               int Offset, RegScavenger *RS ) {
00096   assert(RS && "requiresRegisterScavenging failed");
00097   MachineInstr &MI = *II;
00098   MachineBasicBlock &MBB = *MI.getParent();
00099   DebugLoc dl = MI.getDebugLoc();
00100   unsigned ScratchOffset = RS->scavengeRegister(&XCore::GRRegsRegClass, II, 0);
00101   RS->setUsed(ScratchOffset);
00102   TII.loadImmediate(MBB, II, ScratchOffset, Offset);
00103 
00104   switch (MI.getOpcode()) {
00105   case XCore::LDWFI:
00106     BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
00107           .addReg(FrameReg)
00108           .addReg(ScratchOffset, RegState::Kill)
00109           .addMemOperand(*MI.memoperands_begin());
00110     break;
00111   case XCore::STWFI:
00112     BuildMI(MBB, II, dl, TII.get(XCore::STW_l3r))
00113           .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
00114           .addReg(FrameReg)
00115           .addReg(ScratchOffset, RegState::Kill)
00116           .addMemOperand(*MI.memoperands_begin());
00117     break;
00118   case XCore::LDAWFI:
00119     BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
00120           .addReg(FrameReg)
00121           .addReg(ScratchOffset, RegState::Kill);
00122     break;
00123   default:
00124     llvm_unreachable("Unexpected Opcode");
00125   }
00126 }
00127 
00128 static void InsertSPImmInst(MachineBasicBlock::iterator II,
00129                             const XCoreInstrInfo &TII,
00130                             unsigned Reg, int Offset) {
00131   MachineInstr &MI = *II;
00132   MachineBasicBlock &MBB = *MI.getParent();
00133   DebugLoc dl = MI.getDebugLoc();
00134   bool isU6 = isImmU6(Offset);
00135 
00136   switch (MI.getOpcode()) {
00137   int NewOpcode;
00138   case XCore::LDWFI:
00139     NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
00140     BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
00141           .addImm(Offset)
00142           .addMemOperand(*MI.memoperands_begin());
00143     break;
00144   case XCore::STWFI:
00145     NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
00146     BuildMI(MBB, II, dl, TII.get(NewOpcode))
00147           .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
00148           .addImm(Offset)
00149           .addMemOperand(*MI.memoperands_begin());
00150     break;
00151   case XCore::LDAWFI:
00152     NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
00153     BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
00154           .addImm(Offset);
00155     break;
00156   default:
00157     llvm_unreachable("Unexpected Opcode");
00158   }
00159 }
00160 
00161 static void InsertSPConstInst(MachineBasicBlock::iterator II,
00162                                 const XCoreInstrInfo &TII,
00163                                 unsigned Reg, int Offset, RegScavenger *RS ) {
00164   assert(RS && "requiresRegisterScavenging failed");
00165   MachineInstr &MI = *II;
00166   MachineBasicBlock &MBB = *MI.getParent();
00167   DebugLoc dl = MI.getDebugLoc();
00168   unsigned OpCode = MI.getOpcode();
00169 
00170   unsigned ScratchBase;
00171   if (OpCode==XCore::STWFI) {
00172     ScratchBase = RS->scavengeRegister(&XCore::GRRegsRegClass, II, 0);
00173     RS->setUsed(ScratchBase);
00174   } else
00175     ScratchBase = Reg;
00176   BuildMI(MBB, II, dl, TII.get(XCore::LDAWSP_ru6), ScratchBase).addImm(0);
00177   unsigned ScratchOffset = RS->scavengeRegister(&XCore::GRRegsRegClass, II, 0);
00178   RS->setUsed(ScratchOffset);
00179   TII.loadImmediate(MBB, II, ScratchOffset, Offset);
00180 
00181   switch (OpCode) {
00182   case XCore::LDWFI:
00183     BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
00184           .addReg(ScratchBase, RegState::Kill)
00185           .addReg(ScratchOffset, RegState::Kill)
00186           .addMemOperand(*MI.memoperands_begin());
00187     break;
00188   case XCore::STWFI:
00189     BuildMI(MBB, II, dl, TII.get(XCore::STW_l3r))
00190           .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
00191           .addReg(ScratchBase, RegState::Kill)
00192           .addReg(ScratchOffset, RegState::Kill)
00193           .addMemOperand(*MI.memoperands_begin());
00194     break;
00195   case XCore::LDAWFI:
00196     BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
00197           .addReg(ScratchBase, RegState::Kill)
00198           .addReg(ScratchOffset, RegState::Kill);
00199     break;
00200   default:
00201     llvm_unreachable("Unexpected Opcode");
00202   }
00203 }
00204 
00205 bool XCoreRegisterInfo::needsFrameMoves(const MachineFunction &MF) {
00206   return MF.getMMI().hasDebugInfo() ||
00207     MF.getFunction()->needsUnwindTableEntry();
00208 }
00209 
00210 const MCPhysReg* XCoreRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
00211                                                                          const {
00212   // The callee saved registers LR & FP are explicitly handled during
00213   // emitPrologue & emitEpilogue and related functions.
00214   static const MCPhysReg CalleeSavedRegs[] = {
00215     XCore::R4, XCore::R5, XCore::R6, XCore::R7,
00216     XCore::R8, XCore::R9, XCore::R10,
00217     0
00218   };
00219   static const MCPhysReg CalleeSavedRegsFP[] = {
00220     XCore::R4, XCore::R5, XCore::R6, XCore::R7,
00221     XCore::R8, XCore::R9,
00222     0
00223   };
00224   const TargetFrameLowering *TFI = MF->getTarget().getFrameLowering();
00225   if (TFI->hasFP(*MF))
00226     return CalleeSavedRegsFP;
00227   return CalleeSavedRegs;
00228 }
00229 
00230 BitVector XCoreRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
00231   BitVector Reserved(getNumRegs());
00232   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
00233 
00234   Reserved.set(XCore::CP);
00235   Reserved.set(XCore::DP);
00236   Reserved.set(XCore::SP);
00237   Reserved.set(XCore::LR);
00238   if (TFI->hasFP(MF)) {
00239     Reserved.set(XCore::R10);
00240   }
00241   return Reserved;
00242 }
00243 
00244 bool
00245 XCoreRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
00246   return true;
00247 }
00248 
00249 bool
00250 XCoreRegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
00251   return true;
00252 }
00253 
00254 bool
00255 XCoreRegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const {
00256   return false;
00257 }
00258 
00259 void
00260 XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
00261                                        int SPAdj, unsigned FIOperandNum,
00262                                        RegScavenger *RS) const {
00263   assert(SPAdj == 0 && "Unexpected");
00264   MachineInstr &MI = *II;
00265   MachineOperand &FrameOp = MI.getOperand(FIOperandNum);
00266   int FrameIndex = FrameOp.getIndex();
00267 
00268   MachineFunction &MF = *MI.getParent()->getParent();
00269   const XCoreInstrInfo &TII =
00270           *static_cast<const XCoreInstrInfo*>(MF.getTarget().getInstrInfo());
00271 
00272   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
00273   int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
00274   int StackSize = MF.getFrameInfo()->getStackSize();
00275 
00276   #ifndef NDEBUG
00277   DEBUG(errs() << "\nFunction         : " 
00278         << MF.getName() << "\n");
00279   DEBUG(errs() << "<--------->\n");
00280   DEBUG(MI.print(errs()));
00281   DEBUG(errs() << "FrameIndex         : " << FrameIndex << "\n");
00282   DEBUG(errs() << "FrameOffset        : " << Offset << "\n");
00283   DEBUG(errs() << "StackSize          : " << StackSize << "\n");
00284   #endif
00285 
00286   Offset += StackSize;
00287 
00288   unsigned FrameReg = getFrameRegister(MF);
00289 
00290   // Special handling of DBG_VALUE instructions.
00291   if (MI.isDebugValue()) {
00292     MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/);
00293     MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
00294     return;
00295   }
00296 
00297   // fold constant into offset.
00298   Offset += MI.getOperand(FIOperandNum + 1).getImm();
00299   MI.getOperand(FIOperandNum + 1).ChangeToImmediate(0);
00300   
00301   assert(Offset%4 == 0 && "Misaligned stack offset");
00302   DEBUG(errs() << "Offset             : " << Offset << "\n" << "<--------->\n");
00303   Offset/=4;
00304   
00305   unsigned Reg = MI.getOperand(0).getReg();
00306   assert(XCore::GRRegsRegClass.contains(Reg) && "Unexpected register operand");
00307 
00308   if (TFI->hasFP(MF)) {
00309     if (isImmUs(Offset))
00310       InsertFPImmInst(II, TII, Reg, FrameReg, Offset);
00311     else
00312       InsertFPConstInst(II, TII, Reg, FrameReg, Offset, RS);
00313   } else {
00314     if (isImmU16(Offset))
00315       InsertSPImmInst(II, TII, Reg, Offset);
00316     else
00317       InsertSPConstInst(II, TII, Reg, Offset, RS);
00318   }
00319   // Erase old instruction.
00320   MachineBasicBlock &MBB = *MI.getParent();
00321   MBB.erase(II);
00322 }
00323 
00324 
00325 unsigned XCoreRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
00326   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
00327 
00328   return TFI->hasFP(MF) ? XCore::R10 : XCore::SP;
00329 }