#include <ScheduleDAGInstrs.h>

Inheritance diagram for llvm::ScheduleDAGInstrs:

Collaboration diagram for llvm::ScheduleDAGInstrs:

Public Member Functions
	ScheduleDAGInstrs (MachineFunction &mf, const MachineLoopInfo &mli, const MachineDominatorTree &mdt, bool IsPostRAFlag, LiveIntervals *LIS=0)
virtual	~ScheduleDAGInstrs ()
LiveIntervals *	getLIS () const
	Expose LiveIntervals for use in DAG mutators and such.
const TargetSchedModel *	getSchedModel () const
	Get the machine model for instruction scheduling.
const MCSchedClassDesc *	getSchedClass (SUnit *SU) const
	Resolve and cache a resolved scheduling class for an SUnit.
MachineBasicBlock::iterator	begin () const
	begin - Return an iterator to the top of the current scheduling region.
MachineBasicBlock::iterator	end () const
	end - Return an iterator to the bottom of the current scheduling region.
SUnit *	newSUnit (MachineInstr *MI)
	newSUnit - Creates a new SUnit and return a ptr to it.
SUnit *	getSUnit (MachineInstr *MI) const
	getSUnit - Return an existing SUnit for this MI, or NULL.
virtual void	startBlock (MachineBasicBlock *BB)
	startBlock - Prepare to perform scheduling in the given block.
virtual void	finishBlock ()
	finishBlock - Clean up after scheduling in the given block.
virtual void	enterRegion (MachineBasicBlock *bb, MachineBasicBlock::iterator begin, MachineBasicBlock::iterator end, unsigned endcount)
	Initialize the scheduler state for the next scheduling region.
virtual void	exitRegion ()
	Notify that the scheduler has finished scheduling the current region.
void	buildSchedGraph (AliasAnalysis AA, RegPressureTracker RPTracker=0)
void	addSchedBarrierDeps ()
virtual void	schedule ()=0
virtual void	finalizeSchedule ()
virtual void	dumpNode (const SUnit *SU) const
virtual std::string	getGraphNodeLabel (const SUnit *SU) const
	Return a label for a DAG node that points to an instruction.
virtual std::string	getDAGName () const
	Return a label for the region of code covered by the DAG.
Protected Types
typedef std::vector< std::pair < MachineInstr , MachineInstr > >	DbgValueVector
Protected Member Functions
void	initSUnits ()
void	addPhysRegDataDeps (SUnit *SU, unsigned OperIdx)
void	addPhysRegDeps (SUnit *SU, unsigned OperIdx)
void	addVRegDefDeps (SUnit *SU, unsigned OperIdx)
void	addVRegUseDeps (SUnit *SU, unsigned OperIdx)
Protected Attributes
const MachineLoopInfo &	MLI
const MachineDominatorTree &	MDT
const MachineFrameInfo *	MFI
LiveIntervals *	LIS
	Live Intervals provides reaching defs in preRA scheduling.
TargetSchedModel	SchedModel
	TargetSchedModel provides an interface to the machine model.
bool	IsPostRA
	isPostRA flag indicates vregs cannot be present.
bool	UnitLatencies
bool	CanHandleTerminators
MachineBasicBlock *	BB
	The block in which to insert instructions.
MachineBasicBlock::iterator	RegionBegin
	The beginning of the range to be scheduled.
MachineBasicBlock::iterator	RegionEnd
	The end of the range to be scheduled.
unsigned	EndIndex
DenseMap< MachineInstr , SUnit >	MISUnitMap
Reg2SUnitsMap	Defs
Reg2SUnitsMap	Uses
VReg2SUnitMap	VRegDefs
	Track the last instructon in this region defining each virtual register.
std::vector< SUnit * >	PendingLoads
DbgValueVector	DbgValues
MachineInstr *	FirstDbgValue

Detailed Description

ScheduleDAGInstrs - A ScheduleDAG subclass for scheduling lists of MachineInstrs.

Definition at line 69 of file ScheduleDAGInstrs.h.

Member Typedef Documentation

typedef std::vector<std::pair<MachineInstr *, MachineInstr *> > llvm::ScheduleDAGInstrs::DbgValueVector [protected]

DbgValues - Remember instruction that precedes DBG_VALUE. These are generated by buildSchedGraph but persist so they can be referenced when emitting the final schedule.

Definition at line 140 of file ScheduleDAGInstrs.h.

Constructor & Destructor Documentation

ScheduleDAGInstrs::ScheduleDAGInstrs	(	MachineFunction &	mf,
		const MachineLoopInfo &	mli,
		const MachineDominatorTree &	mdt,
		bool	IsPostRAFlag,
		LiveIntervals *	LIS = `0`
	)		`[explicit]`

Definition at line 45 of file ScheduleDAGInstrs.cpp.

References DbgValues, llvm::MachineRegisterInfo::getNumVirtRegs(), llvm::MCSubtargetInfo::getSchedModel(), llvm::TargetMachine::getSubtarget(), llvm::TargetSchedModel::init(), IsPostRA, LIS, llvm::ScheduleDAG::MRI, SchedModel, llvm::A64DB::ST, llvm::ScheduleDAG::TII, and llvm::ScheduleDAG::TM.

virtual llvm::ScheduleDAGInstrs::~ScheduleDAGInstrs ( ) [inline, virtual]

Definition at line 151 of file ScheduleDAGInstrs.h.

Member Function Documentation

void ScheduleDAGInstrs::addPhysRegDataDeps	(	SUnit *	SU,
		unsigned	OperIdx
	)		`[protected]`

MO is an operand of SU's instruction that defines a physical register. Add data dependencies from SU to any uses of the physical register.

Definition at line 241 of file ScheduleDAGInstrs.cpp.

References llvm::SUnit::addPred(), llvm::SDep::Artificial, llvm::TargetSchedModel::computeOperandLatency(), llvm::SparseMultiSet< ValueT, KeyFunctorT, SparseT >::contains(), llvm::SDep::Data, llvm::SparseMultiSet< ValueT, KeyFunctorT, SparseT >::end(), llvm::SparseMultiSet< ValueT, KeyFunctorT, SparseT >::find(), llvm::SUnit::getInstr(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::TargetMachine::getSubtarget(), llvm::SUnit::hasPhysRegDefs, I, llvm::MachineOperand::isDef(), llvm::MCRegisterInfo::DiffListIterator::isValid(), SchedModel, llvm::SDep::setLatency(), llvm::SDep::setMinLatency(), llvm::A64DB::ST, llvm::ScheduleDAG::TM, llvm::ScheduleDAG::TRI, and Uses.

Referenced by addPhysRegDeps().

void ScheduleDAGInstrs::addPhysRegDeps	(	SUnit *	SU,
		unsigned	OperIdx
	)		`[protected]`

addPhysRegDeps - Add register dependencies (data, anti, and output) from this SUnit to following instructions in the same scheduling region that depend the physical register referenced at OperIdx.

Definition at line 287 of file ScheduleDAGInstrs.cpp.

References addPhysRegDataDeps(), llvm::SUnit::addPred(), llvm::SDep::Anti, llvm::TargetSchedModel::computeOutputLatency(), llvm::SparseMultiSet< ValueT, KeyFunctorT, SparseT >::contains(), Defs, llvm::SparseMultiSet< ValueT, KeyFunctorT, SparseT >::end(), llvm::SparseMultiSet< ValueT, KeyFunctorT, SparseT >::equal_range(), llvm::ScheduleDAG::ExitSU, llvm::SparseMultiSet< ValueT, KeyFunctorT, SparseT >::find(), llvm::SUnit::getInstr(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::SUnit::hasPhysRegUses, I, llvm::SparseMultiSet< ValueT, KeyFunctorT, SparseT >::insert(), llvm::SUnit::isCall, llvm::MachineOperand::isDead(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isUse(), llvm::MCRegisterInfo::DiffListIterator::isValid(), llvm::A64CC::MI, llvm::SDep::Output, P, llvm::MachineInstr::registerDefIsDead(), SchedModel, llvm::SDep::setLatency(), llvm::SDep::setMinLatency(), llvm::ScheduleDAG::TRI, and Uses.

Referenced by buildSchedGraph().

void ScheduleDAGInstrs::addSchedBarrierDeps ( )

addSchedBarrierDeps - Add dependencies from instructions in the current list of instructions being scheduled to scheduling barrier. We want to make sure instructions which define registers that are either used by the terminator or are live-out are properly scheduled. This is especially important when the definition latency of the return value(s) are too high to be hidden by the branch or when the liveout registers used by instructions in the fallthrough block.

addSchedBarrierDeps - Add dependencies from instructions in the current list of instructions being scheduled to scheduling barrier by adding the exit SU to the register defs and use list. This is because we want to make sure instructions which define registers that are either used by the terminator or are live-out are properly scheduled. This is especially important when the definition latency of the return value(s) are too high to be hidden by the branch or when the liveout registers used by instructions in the fallthrough block.

Definition at line 202 of file ScheduleDAGInstrs.cpp.

References addVRegUseDeps(), BB, llvm::SparseMultiSet< ValueT, KeyFunctorT, SparseT >::contains(), llvm::SparseMultiSet< ValueT, KeyFunctorT, SparseT >::empty(), llvm::MachineBasicBlock::end(), llvm::ScheduleDAG::ExitSU, llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), I, llvm::SparseMultiSet< ValueT, KeyFunctorT, SparseT >::insert(), llvm::MachineInstr::isBarrier(), llvm::MachineInstr::isCall(), llvm::MachineOperand::isDef(), llvm::TargetRegisterInfo::isPhysicalRegister(), IsPostRA, llvm::MachineOperand::isReg(), llvm::MachineOperand::readsReg(), RegionEnd, llvm::SUnit::setInstr(), llvm::MachineBasicBlock::succ_begin(), llvm::MachineBasicBlock::succ_end(), llvm::ScheduleDAG::TRI, and Uses.

Referenced by buildSchedGraph().

void ScheduleDAGInstrs::addVRegDefDeps	(	SUnit *	SU,
		unsigned	OperIdx
	)		`[protected]`

addVRegDefDeps - Add register output and data dependencies from this SUnit to instructions that occur later in the same scheduling region if they read from or write to the virtual register defined at OperIdx.

TODO: Hoist loop induction variable increments. This has to be reevaluated. Generally, IV scheduling should be done before coalescing.

Definition at line 368 of file ScheduleDAGInstrs.cpp.

References llvm::SUnit::addPred(), llvm::TargetSchedModel::computeOutputLatency(), llvm::SparseSet< ValueT, KeyFunctorT, SparseT >::end(), llvm::ScheduleDAG::ExitSU, llvm::SparseSet< ValueT, KeyFunctorT, SparseT >::find(), llvm::SUnit::getInstr(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::hasOneDef(), llvm::SparseSet< ValueT, KeyFunctorT, SparseT >::insert(), llvm::A64CC::MI, llvm::ScheduleDAG::MRI, llvm::SDep::Output, SchedModel, llvm::SDep::setLatency(), llvm::SDep::setMinLatency(), llvm::VReg2SUnit::SU, and VRegDefs.

Referenced by buildSchedGraph().

void ScheduleDAGInstrs::addVRegUseDeps	(	SUnit *	SU,
		unsigned	OperIdx
	)		`[protected]`

addVRegUseDeps - Add a register data dependency if the instruction that defines the virtual register used at OperIdx is mapped to an SUnit. Add a register antidependency from this SUnit to instructions that occur later in the same scheduling region if they write the virtual register.

TODO: Handle ExitSU "uses" properly.

Definition at line 408 of file ScheduleDAGInstrs.cpp.

References llvm::SUnit::addPred(), llvm::TargetSubtargetInfo::adjustSchedDependency(), llvm::SDep::Anti, llvm::TargetSchedModel::computeOperandLatency(), llvm::SDep::Data, llvm::tgtok::Def, llvm::SparseSet< ValueT, KeyFunctorT, SparseT >::end(), llvm::SparseSet< ValueT, KeyFunctorT, SparseT >::find(), llvm::MachineInstr::findRegisterDefOperandIdx(), llvm::SUnit::getInstr(), llvm::LiveIntervals::getInstructionFromIndex(), llvm::LiveIntervals::getInstructionIndex(), llvm::LiveIntervals::getInterval(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::TargetMachine::getSubtarget(), getSUnit(), LIS, llvm::A64CC::MI, SchedModel, llvm::SDep::setLatency(), llvm::SDep::setMinLatency(), llvm::A64DB::ST, llvm::VReg2SUnit::SU, llvm::ScheduleDAG::TM, and VRegDefs.

Referenced by addSchedBarrierDeps(), and buildSchedGraph().

MachineBasicBlock::iterator llvm::ScheduleDAGInstrs::begin ( ) const [inline]

begin - Return an iterator to the top of the current scheduling region.

Definition at line 167 of file ScheduleDAGInstrs.h.

References RegionBegin.

Referenced by llvm::ScheduleDAGMI::dumpSchedule(), enterRegion(), and llvm::ScheduleDAGMI::schedule().

void ScheduleDAGInstrs::buildSchedGraph	(	AliasAnalysis *	AA,
		RegPressureTracker *	RPTracker = `0`
	)

buildSchedGraph - Build SUnits from the MachineBasicBlock that we are input.

If RegPressure is non null, compute register pressure as a side effect. The DAG builder is an efficient place to do it because it already visits operands.

Definition at line 695 of file ScheduleDAGInstrs.cpp.

References addChainDependency(), addPhysRegDeps(), llvm::SUnit::addPred(), addSchedBarrierDeps(), addVRegDefDeps(), addVRegUseDeps(), adjustChainDeps(), llvm::SDep::Artificial, llvm::SDep::Barrier, llvm::MapVector< KeyT, ValueT, MapType, VectorType >::begin(), llvm::SmallVectorTemplateCommon< T >::begin(), CanHandleTerminators, llvm::MapVector< KeyT, ValueT, MapType, VectorType >::clear(), llvm::SparseSet< ValueT, KeyFunctorT, SparseT >::clear(), llvm::SparseMultiSet< ValueT, KeyFunctorT, SparseT >::clear(), DbgValues, Defs, llvm::SmallVectorBase::empty(), llvm::SparseSet< ValueT, KeyFunctorT, SparseT >::empty(), llvm::SparseMultiSet< ValueT, KeyFunctorT, SparseT >::empty(), llvm::MapVector< KeyT, ValueT, MapType, VectorType >::end(), llvm::SmallVectorTemplateCommon< T >::end(), llvm::ScheduleDAG::ExitSU, llvm::MapVector< KeyT, ValueT, MapType, VectorType >::find(), FirstDbgValue, llvm::MachineInstr::getNumOperands(), llvm::MCRegisterInfo::getNumRegs(), llvm::MachineRegisterInfo::getNumVirtRegs(), llvm::MachineInstr::getOperand(), llvm::RegPressureTracker::getPos(), llvm::MachineOperand::getReg(), getUnderlyingObjectsForInstr(), I, llvm::ARM_PROC::IE, initSUnits(), llvm::MachineInstr::isDebugValue(), llvm::MachineOperand::isDef(), isGlobalMemoryObject(), llvm::MachineInstr::isInvariantLoad(), llvm::MachineInstr::isLabel(), llvm::TargetRegisterInfo::isPhysicalRegister(), IsPostRA, llvm::SUnit::isPred(), llvm::MachineOperand::isReg(), llvm::MachineInstr::isTerminator(), llvm::MachineInstr::mayLoad(), llvm::MachineInstr::mayStore(), MFI, llvm::A64CC::MI, MISUnitMap, llvm::ScheduleDAG::MRI, PendingLoads, llvm::prior(), llvm::MachineOperand::readsReg(), llvm::RegPressureTracker::recede(), RegionBegin, RegionEnd, llvm::SDep::setLatency(), llvm::SparseSet< ValueT, KeyFunctorT, SparseT >::setUniverse(), llvm::SparseMultiSet< ValueT, KeyFunctorT, SparseT >::setUniverse(), llvm::MapVector< KeyT, ValueT, MapType, VectorType >::size(), llvm::ScheduleDAG::TRI, Uses, and VRegDefs.

Referenced by llvm::ScheduleDAGMI::buildDAGWithRegPressure(), and llvm::DefaultVLIWScheduler::schedule().

void ScheduleDAGInstrs::dumpNode ( const SUnit * SU ) const [virtual]

Implements llvm::ScheduleDAG.

Definition at line 987 of file ScheduleDAGInstrs.cpp.

References llvm::MachineInstr::dump(), and llvm::SUnit::getInstr().

MachineBasicBlock::iterator llvm::ScheduleDAGInstrs::end ( ) const [inline]

end - Return an iterator to the bottom of the current scheduling region.

Definition at line 170 of file ScheduleDAGInstrs.h.

References RegionEnd.

Referenced by llvm::ScheduleDAGMI::dumpSchedule(), and enterRegion().

void ScheduleDAGInstrs::enterRegion	(	MachineBasicBlock *	bb,
		MachineBasicBlock::iterator	begin,
		MachineBasicBlock::iterator	end,
		unsigned	endcount
	)		`[virtual]`

Initialize the scheduler state for the next scheduling region.

Initialize the DAG and common scheduler state for the current scheduling region. This does not actually create the DAG, only clears it. The scheduling driver may call BuildSchedGraph multiple times per scheduling region.

Reimplemented in llvm::ScheduleDAGMI.

Definition at line 175 of file ScheduleDAGInstrs.cpp.

References BB, begin(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT >::clear(), llvm::ScheduleDAG::clearDAG(), end(), EndIndex, MISUnitMap, RegionBegin, and RegionEnd.

Referenced by llvm::VLIWPacketizerList::PacketizeMIs().

void ScheduleDAGInstrs::exitRegion ( ) [virtual]

Notify that the scheduler has finished scheduling the current region.

Close the current scheduling region. Don't clear any state in case the driver wants to refer to the previous scheduling region.

Definition at line 190 of file ScheduleDAGInstrs.cpp.

Referenced by llvm::VLIWPacketizerList::PacketizeMIs().

virtual void llvm::ScheduleDAGInstrs::finalizeSchedule ( ) [inline, virtual]

finalizeSchedule - Allow targets to perform final scheduling actions at the level of the whole MachineFunction. By default does nothing.

Definition at line 215 of file ScheduleDAGInstrs.h.

void ScheduleDAGInstrs::finishBlock ( ) [virtual]

finishBlock - Clean up after scheduling in the given block.

Definition at line 166 of file ScheduleDAGInstrs.cpp.

References BB.

Referenced by llvm::VLIWPacketizerList::PacketizeMIs().

std::string ScheduleDAGInstrs::getDAGName ( ) const [virtual]

Return a label for the region of code covered by the DAG.

Return the basic block label. It is not necessarilly unique because a block contains multiple scheduling regions. But it is fine for visualization.

Implements llvm::ScheduleDAG.

Definition at line 1007 of file ScheduleDAGInstrs.cpp.

References BB, and llvm::MachineBasicBlock::getFullName().

Referenced by llvm::ScheduleDAGMI::viewGraph().

std::string ScheduleDAGInstrs::getGraphNodeLabel ( const SUnit * SU ) const [virtual]

Return a label for a DAG node that points to an instruction.

Implements llvm::ScheduleDAG.

Definition at line 993 of file ScheduleDAGInstrs.cpp.

References llvm::ScheduleDAG::EntrySU, llvm::ScheduleDAG::ExitSU, llvm::SUnit::getInstr(), llvm::MachineInstr::print(), llvm::raw_string_ostream::str(), and llvm::ScheduleDAG::TM.

LiveIntervals* llvm::ScheduleDAGInstrs::getLIS ( ) const [inline]

Expose LiveIntervals for use in DAG mutators and such.

Definition at line 154 of file ScheduleDAGInstrs.h.

References LIS.

const MCSchedClassDesc* llvm::ScheduleDAGInstrs::getSchedClass ( SUnit * SU ) const [inline]

Resolve and cache a resolved scheduling class for an SUnit.

Definition at line 160 of file ScheduleDAGInstrs.h.

References llvm::SUnit::getInstr(), llvm::TargetSchedModel::resolveSchedClass(), llvm::SUnit::SchedClass, and SchedModel.

const TargetSchedModel* llvm::ScheduleDAGInstrs::getSchedModel ( ) const [inline]

Get the machine model for instruction scheduling.

Definition at line 157 of file ScheduleDAGInstrs.h.

References SchedModel.

Referenced by llvm::ConvergingVLIWScheduler::initialize().

SUnit * llvm::ScheduleDAGInstrs::getSUnit ( MachineInstr * MI ) const [inline]

getSUnit - Return an existing SUnit for this MI, or NULL.

Definition at line 246 of file ScheduleDAGInstrs.h.

References llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT >::end(), llvm::DenseMapBase< DerivedT, KeyT, ValueT, KeyInfoT >::find(), I, and MISUnitMap.

Referenced by addVRegUseDeps(), and llvm::ScheduleDAGMI::dumpSchedule().

void ScheduleDAGInstrs::initSUnits ( ) [protected]

Create an SUnit for each real instruction, numbered in top-down toplological order. The instruction order A < B, implies that no edge exists from B to A.

Map each real instruction to its SUnit.

After initSUnits, the SUnits vector cannot be resized and the scheduler may hang onto SUnit pointers. We may relax this in the future by using SUnit IDs instead of pointers.

MachineScheduler relies on initSUnits numbering the nodes by their order in the original instruction list.

Definition at line 671 of file ScheduleDAGInstrs.cpp.

References BB, llvm::TargetSchedModel::computeInstrLatency(), llvm::SUnit::getInstr(), I, llvm::SUnit::isCall, llvm::MachineInstr::isCall(), llvm::SUnit::isCommutable, llvm::MachineInstr::isCommutable(), llvm::MachineInstr::isDebugValue(), llvm::SUnit::Latency, llvm::A64CC::MI, MISUnitMap, newSUnit(), RegionBegin, RegionEnd, SchedModel, llvm::MachineBasicBlock::size(), and llvm::ScheduleDAG::SUnits.

Referenced by buildSchedGraph().

SUnit * llvm::ScheduleDAGInstrs::newSUnit ( MachineInstr * MI ) [inline]

newSUnit - Creates a new SUnit and return a ptr to it.

Definition at line 234 of file ScheduleDAGInstrs.h.

References llvm::ScheduleDAG::SUnits.

Referenced by initSUnits().

virtual void llvm::ScheduleDAGInstrs::schedule ( ) [pure virtual]

schedule - Order nodes according to selected style, filling in the Sequence member.

Typically, a scheduling algorithm will implement schedule() without overriding enterRegion() or exitRegion().

Implemented in llvm::ScheduleDAGMI, llvm::DefaultVLIWScheduler, and llvm::VLIWMachineScheduler.

void ScheduleDAGInstrs::startBlock ( MachineBasicBlock * BB ) [virtual]

startBlock - Prepare to perform scheduling in the given block.

Definition at line 162 of file ScheduleDAGInstrs.cpp.

References BB.

Referenced by llvm::VLIWPacketizerList::PacketizeMIs().

Member Data Documentation

MachineBasicBlock* llvm::ScheduleDAGInstrs::BB [protected]

The block in which to insert instructions.

State specific to the current scheduling region. ------------------------------------------------

Definition at line 99 of file ScheduleDAGInstrs.h.

Referenced by addSchedBarrierDeps(), llvm::ScheduleDAGMI::buildDAGWithRegPressure(), enterRegion(), finishBlock(), getDAGName(), llvm::ScheduleDAGMI::initRegPressure(), initSUnits(), llvm::ScheduleDAGMI::moveInstruction(), llvm::ScheduleDAGMI::placeDebugValues(), llvm::VLIWMachineScheduler::schedule(), and startBlock().

bool llvm::ScheduleDAGInstrs::CanHandleTerminators [protected]

The standard DAG builder does not normally include terminators as DAG nodes because it does not create the necessary dependencies to prevent reordering. A specialized scheduler can overide TargetInstrInfo::isSchedulingBoundary then enable this flag to indicate it has taken responsibility for scheduling the terminator correctly.

Definition at line 93 of file ScheduleDAGInstrs.h.

Referenced by buildSchedGraph(), and llvm::DefaultVLIWScheduler::DefaultVLIWScheduler().

DbgValueVector llvm::ScheduleDAGInstrs::DbgValues [protected]

Definition at line 141 of file ScheduleDAGInstrs.h.

Referenced by buildSchedGraph(), llvm::ScheduleDAGMI::placeDebugValues(), and ScheduleDAGInstrs().

Reg2SUnitsMap llvm::ScheduleDAGInstrs::Defs [protected]

State internal to DAG building. ------------------------------- Defs, Uses - Remember where defs and uses of each register are as we iterate upward through the instructions. This is allocated here instead of inside BuildSchedGraph to avoid the need for it to be initialized and destructed for each block.

Definition at line 125 of file ScheduleDAGInstrs.h.

Referenced by addPhysRegDeps(), and buildSchedGraph().

unsigned llvm::ScheduleDAGInstrs::EndIndex [protected]

The index in BB of RegionEnd.

This is the instruction number from the top of the current block, not the SlotIndex. It is only used by the AntiDepBreaker and should be removed once that client is obsolete.

Definition at line 112 of file ScheduleDAGInstrs.h.

Referenced by enterRegion().

MachineInstr* llvm::ScheduleDAGInstrs::FirstDbgValue [protected]

Definition at line 142 of file ScheduleDAGInstrs.h.

Referenced by buildSchedGraph(), and llvm::ScheduleDAGMI::placeDebugValues().

bool llvm::ScheduleDAGInstrs::IsPostRA [protected]

isPostRA flag indicates vregs cannot be present.

Definition at line 82 of file ScheduleDAGInstrs.h.

Referenced by addSchedBarrierDeps(), buildSchedGraph(), and ScheduleDAGInstrs().

LiveIntervals* llvm::ScheduleDAGInstrs::LIS [protected]

Live Intervals provides reaching defs in preRA scheduling.

Definition at line 76 of file ScheduleDAGInstrs.h.

Referenced by addVRegUseDeps(), getLIS(), and ScheduleDAGInstrs().

const MachineDominatorTree& llvm::ScheduleDAGInstrs::MDT [protected]

Definition at line 72 of file ScheduleDAGInstrs.h.

const MachineFrameInfo* llvm::ScheduleDAGInstrs::MFI [protected]

Definition at line 73 of file ScheduleDAGInstrs.h.

Referenced by buildSchedGraph().

DenseMap<MachineInstr*, SUnit*> llvm::ScheduleDAGInstrs::MISUnitMap [protected]

After calling BuildSchedGraph, each machine instruction in the current scheduling region is mapped to an SUnit.

Definition at line 116 of file ScheduleDAGInstrs.h.

Referenced by buildSchedGraph(), enterRegion(), getSUnit(), and initSUnits().

const MachineLoopInfo& llvm::ScheduleDAGInstrs::MLI [protected]

Definition at line 71 of file ScheduleDAGInstrs.h.

Referenced by llvm::VLIWMachineScheduler::schedule().

std::vector<SUnit *> llvm::ScheduleDAGInstrs::PendingLoads [protected]

PendingLoads - Remember where unknown loads are after the most recent unknown store, as we iterate. As with Defs and Uses, this is here to minimize construction/destruction.

Definition at line 134 of file ScheduleDAGInstrs.h.

Referenced by buildSchedGraph().

MachineBasicBlock::iterator llvm::ScheduleDAGInstrs::RegionBegin [protected]

The beginning of the range to be scheduled.

Definition at line 102 of file ScheduleDAGInstrs.h.

Referenced by begin(), buildSchedGraph(), enterRegion(), llvm::ScheduleDAGMI::initQueues(), llvm::ScheduleDAGMI::initRegPressure(), initSUnits(), llvm::ScheduleDAGMI::moveInstruction(), and llvm::ScheduleDAGMI::placeDebugValues().