#include "llvm/CodeGen/TargetRegisterInfo.h"

Public Types
using	iterator = const MCPhysReg *
using	const_iterator = const MCPhysReg *

Public Member Functions
unsigned	getID () const
	Return the register class ID number.
iterator	begin () const
	begin/end - Return all of the registers in this class.
iterator	end () const
unsigned	getNumRegs () const
	Return the number of registers in this class.
ArrayRef< MCPhysReg >	getRegisters () const
MCRegister	getRegister (unsigned i) const
	Return the specified register in the class.
bool	contains (Register Reg) const
	Return true if the specified register is included in this register class.
bool	contains (Register Reg1, Register Reg2) const
	Return true if both registers are in this class.
uint8_t	getCopyCost () const
	Return the cost of copying a value between two registers in this class.
bool	expensiveOrImpossibleToCopy () const
bool	isAllocatable () const
	Return true if this register class may be used to create virtual registers.
bool	isBaseClass () const
	Return true if this register class has a defined BaseClassOrder.
bool	hasSubClass (const TargetRegisterClass *RC) const
	Return true if the specified TargetRegisterClass is a proper sub-class of this TargetRegisterClass.
bool	hasSubClassEq (const TargetRegisterClass *RC) const
	Returns true if RC is a sub-class of or equal to this class.
bool	hasSuperClass (const TargetRegisterClass *RC) const
	Return true if the specified TargetRegisterClass is a proper super-class of this TargetRegisterClass.
bool	hasSuperClassEq (const TargetRegisterClass *RC) const
	Returns true if RC is a super-class of or equal to this class.
const uint32_t *	getSubClassMask () const
	Returns a bit vector of subclasses, including this one.
const uint16_t *	getSuperRegIndices () const
	Returns a 0-terminated list of sub-register indices that project some super-register class into this register class.
ArrayRef< unsigned >	superclasses () const
	Returns a list of super-classes.
bool	isASubClass () const
	Return true if this TargetRegisterClass is a subset class of at least one other TargetRegisterClass.
ArrayRef< MCPhysReg >	getRawAllocationOrder (const MachineFunction &MF, bool Rev=false) const
	Returns the preferred order for allocating registers from this register class in MF.
LaneBitmask	getLaneMask () const
	Returns the combination of all lane masks of register in this class.

Public Attributes
const MCRegisterClass *	MC
const uint32_t *	SubClassMask
const uint16_t *	SuperRegIndices
const LaneBitmask	LaneMask
const uint8_t	AllocationPriority
	Classes with a higher priority value are assigned first by register allocators using a greedy heuristic.
const bool	GlobalPriority
const uint8_t	TSFlags
	Configurable target specific flags.
const uint8_t	SpillStackID
const bool	HasDisjunctSubRegs
	Whether the class supports two (or more) disjunct subregister indices.
const bool	CoveredBySubRegs
	Whether a combination of subregisters can cover every register in the class.
const unsigned *	SuperClasses
const uint16_t	SuperClassesSize
ArrayRef< MCPhysReg >(*	OrderFunc )(const MachineFunction &, bool Rev)

Detailed Description

Definition at line 46 of file TargetRegisterInfo.h.

Member Typedef Documentation

◆ const_iterator

using llvm::TargetRegisterClass::const_iterator = const MCPhysReg *

Definition at line 49 of file TargetRegisterInfo.h.

◆ iterator

using llvm::TargetRegisterClass::iterator = const MCPhysReg *

Definition at line 48 of file TargetRegisterInfo.h.

Member Function Documentation

◆ begin()

iterator llvm::TargetRegisterClass::begin ( ) const

inline

begin/end - Return all of the registers in this class.

Definition at line 80 of file TargetRegisterInfo.h.

References MC.

Referenced by allocateSGPR32InputImpl(), llvm::HexagonBlockRanges::expandToSubRegs(), getRegisters(), getRegistersForValue(), and getRegistersForValue().

◆ contains() [1/2]

bool llvm::TargetRegisterClass::contains ( Register Reg ) const

inline

Return true if the specified register is included in this register class.

This does not include virtual registers.

FIXME: Historically this function has returned false when given vregs but it should probably only receive physical registers

Definition at line 97 of file TargetRegisterInfo.h.

References MC, and Reg.

Referenced by addHints(), llvm::MachineFunction::addLiveIn(), llvm::SIRegisterInfo::buildSpillLoadStore(), canFoldCopy(), llvm::PPCInstrInfo::ClobbersPredicate(), llvm::VirtRegAuxInfo::copyHint(), llvm::ARMBaseRegisterInfo::eliminateFrameIndex(), estimateRSStackSizeLimit(), llvm::SIInstrInfo::expandPostRAPseudo(), llvm::SIInstrInfo::foldImmediate(), llvm::R600InstrInfo::getIndirectIndexBegin(), llvm::M68kRegisterInfo::getMatchingMegaReg(), llvm::M68kRegisterInfo::getMaximalPhysRegClass(), llvm::AArch64RegisterInfo::getRegAllocationHints(), llvm::ARMBaseRegisterInfo::getRegAllocationHints(), llvm::PPCRegisterInfo::getRegAllocationHints(), llvm::X86RegisterInfo::getRegAllocationHints(), llvm::X86TargetLowering::getRegForInlineAsmConstraint(), llvm::PPCInstrInfo::insertSelect(), llvm::SIInstrInfo::isLegalRegOperand(), llvm::SIFrameLowering::restoreCalleeSavedRegisters(), llvm::rewriteT2FrameIndex(), llvm::CoalescerPair::setRegisters(), llvm::SystemZRegisterInfo::shouldCoalesce(), UpdateOperandRegClass(), and llvm::SIInstrInfo::verifyInstruction().

◆ contains() [2/2]

bool llvm::TargetRegisterClass::contains	(	Register	Reg1,
		Register	Reg2 ) const

inline

Return true if both registers are in this class.

FIXME: Historically this function has returned false when given a vregs but it should probably only receive physical registers

Definition at line 106 of file TargetRegisterInfo.h.

References llvm::Register::asMCReg(), llvm::Register::isPhysical(), and MC.

◆ end()

iterator llvm::TargetRegisterClass::end ( ) const

inline

Definition at line 81 of file TargetRegisterInfo.h.

References MC.

Referenced by getRegistersForValue(), and getRegistersForValue().

◆ expensiveOrImpossibleToCopy()

bool llvm::TargetRegisterClass::expensiveOrImpossibleToCopy ( ) const

inline

Returns: true if register class is very expensive to copy e.g. status flag register classes.

Definition at line 120 of file TargetRegisterInfo.h.

References MC.

Referenced by CheckForPhysRegDependency().

◆ getCopyCost()

uint8_t llvm::TargetRegisterClass::getCopyCost ( ) const

inline

Return the cost of copying a value between two registers in this class.

If this is the maximum value, the register may be impossible to copy.

Definition at line 116 of file TargetRegisterInfo.h.

References MC.

Referenced by CheckForPhysRegDependency().

◆ getID()

unsigned llvm::TargetRegisterClass::getID ( ) const

inline

Return the register class ID number.

Definition at line 76 of file TargetRegisterInfo.h.

References MC.

Referenced by llvm::RegsForValue::AddInlineAsmOperands(), llvm::HexagonEvaluator::composeWithSubRegIndex(), llvm::X86RegisterInfo::constrainRegClassToNonRex2(), llvm::RegisterBank::covers(), llvm::HexagonFrameLowering::determineCalleeSaves(), llvm::SITargetLowering::finalizeLowering(), llvm::HexagonRegisterInfo::getCallerSavedRegs(), llvm::WebAssembly::getCopyOpcodeForRegClass(), GetCostForDef(), llvm::SIRegisterInfo::getEquivalentVGPRClass(), llvm::HexagonRegisterInfo::getHexagonSubRegIndex(), llvm::ARMBaseRegisterInfo::getLargestLegalSuperClass(), llvm::SIRegisterInfo::getNumUsedPhysRegs(), llvm::AArch64RegisterInfo::getRegAllocationHints(), llvm::X86RegisterInfo::getRegAllocationHints(), llvm::AArch64RegisterBankInfo::getRegBankFromRegClass(), llvm::PPCRegisterBankInfo::getRegBankFromRegClass(), llvm::RISCVRegisterBankInfo::getRegBankFromRegClass(), llvm::SPIRVRegisterBankInfo::getRegBankFromRegClass(), llvm::AMDGPU::getRegBitWidth(), llvm::TargetRegisterInfo::getRegClassInfo(), llvm::AArch64RegisterInfo::getRegPressureLimit(), llvm::ARMBaseRegisterInfo::getRegPressureLimit(), llvm::MipsRegisterInfo::getRegPressureLimit(), llvm::PPCRegisterInfo::getRegPressureLimit(), llvm::SIRegisterInfo::getRegPressureLimit(), llvm::X86RegisterInfo::getRegPressureLimit(), hasSubClassEq(), INITIALIZE_PASS(), llvm::X86RegisterInfo::isNonRex2RegClass(), isTileRegister(), llvm::X86RegisterInfo::isTileRegisterClass(), IsWritingToVCCR(), llvm::WebAssemblyMCInstLower::lower(), llvm::HexagonTargetLowering::LowerFormalArguments(), llvm::InlineAsmLowering::lowerInlineAsm(), llvm::HexagonEvaluator::mask(), llvm::ResourcePriorityQueue::scheduledNode(), llvm::AMDGPUDAGToDAGISel::Select(), llvm::AArch64RegisterInfo::shouldCoalesce(), and llvm::HexagonRegisterInfo::shouldCoalesce().

◆ getLaneMask()

LaneBitmask llvm::TargetRegisterClass::getLaneMask ( ) const

inline

Returns the combination of all lane masks of register in this class.

The lane masks of the registers are the combination of all lane masks of their subregisters. Returns 1 if there are no subregisters.

Definition at line 217 of file TargetRegisterInfo.h.

References LaneMask.

Referenced by llvm::ScheduleDAGInstrs::getLaneMaskForMO(), and llvm::MachineRegisterInfo::getMaxLaneMaskForVReg().

◆ getNumRegs()

unsigned llvm::TargetRegisterClass::getNumRegs ( ) const

inline

Return the number of registers in this class.

Definition at line 84 of file TargetRegisterInfo.h.

References MC.

Referenced by llvm::RegisterClassInfo::computePSetLimit(), constrainRegClass(), llvm::R600InstrInfo::getIndirectIndexBegin(), llvm::M68kRegisterInfo::getMaximalPhysRegClass(), llvm::SITargetLowering::getRegForInlineAsmConstraint(), llvm::M68kRegisterInfo::getRegisterOrder(), getRegisters(), and llvm::SystemZRegisterInfo::shouldCoalesce().

◆ getRawAllocationOrder()

ArrayRef< MCPhysReg > llvm::TargetRegisterClass::getRawAllocationOrder	(	const MachineFunction &	MF,
		bool	Rev = false ) const

inline

Returns the preferred order for allocating registers from this register class in MF.

The raw order comes directly from the .td file and may include reserved registers that are not allocatable. Register allocators should also make sure to allocate callee-saved registers only after all the volatiles are used. The RegisterClassInfo class provides filtered allocation orders with callee-saved registers moved to the end.

The MachineFunction argument can be used to tune the allocatable registers based on the characteristics of the function, subtarget, or other criteria.

By default, this method returns all registers in the class.

Definition at line 209 of file TargetRegisterInfo.h.

References getRegisters(), and OrderFunc.

Referenced by getAllocatableSetForRC(), and llvm::RegScavenger::scavengeRegisterBackwards().

◆ getRegister()

MCRegister llvm::TargetRegisterClass::getRegister ( unsigned i ) const

inline

Return the specified register in the class.

Definition at line 91 of file TargetRegisterInfo.h.

References MC.

Referenced by llvm::R600InstrInfo::getIndirectIndexBegin(), llvm::SITargetLowering::getRegForInlineAsmConstraint(), llvm::M68kRegisterInfo::getRegisterOrder(), and llvm::tryFoldSPUpdateIntoPushPop().

◆ getRegisters()

ArrayRef< MCPhysReg > llvm::TargetRegisterClass::getRegisters ( ) const

inline

Definition at line 86 of file TargetRegisterInfo.h.

References llvm::ArrayRef(), begin(), and getNumRegs().

Referenced by llvm::SIMachineFunctionInfo::allocateVGPRSpillToAGPR(), llvm::RegAllocBase::getErrorAssignment(), llvm::SIRegisterInfo::getNumUsedPhysRegs(), and getRawAllocationOrder().

◆ getSubClassMask()

const uint32_t * llvm::TargetRegisterClass::getSubClassMask ( ) const

inline

Returns a bit vector of subclasses, including this one.

The vector is indexed by class IDs.

To use it, consider the returned array as a chunk of memory that contains an array of bits of size NumRegClasses. Each 32-bit chunk contains a bitset of the ID of the subclasses in big-endian style. I.e., the representation of the memory from left to right at the bit level looks like: [31 30 ... 1 0] [ 63 62 ... 33 32] ... [ XXX NumRegClasses NumRegClasses - 1 ... ] Where the number represents the class ID and XXX bits that should be ignored.

See the implementation of hasSubClassEq for an example of how it can be used.

Definition at line 170 of file TargetRegisterInfo.h.

References SubClassMask.

Referenced by llvm::TargetRegisterInfo::getAllocatableClass().

◆ getSuperRegIndices()

const uint16_t * llvm::TargetRegisterClass::getSuperRegIndices ( ) const

inline

Returns a 0-terminated list of sub-register indices that project some super-register class into this register class.

The list has an entry for each Idx such that:

There exists SuperRC where: For all Reg in SuperRC: this->contains(Reg:Idx)

Definition at line 181 of file TargetRegisterInfo.h.

References SuperRegIndices.

◆ hasSubClass()

bool llvm::TargetRegisterClass::hasSubClass ( const TargetRegisterClass * RC ) const

inline

Return true if the specified TargetRegisterClass is a proper sub-class of this TargetRegisterClass.

Definition at line 133 of file TargetRegisterInfo.h.

References hasSubClassEq().

Referenced by foldSimpleCrossClassCopies(), getCommonMinimalPhysRegClass(), llvm::M68kRegisterInfo::getMaximalPhysRegClass(), and hasSuperClass().

◆ hasSubClassEq()

bool llvm::TargetRegisterClass::hasSubClassEq ( const TargetRegisterClass * RC ) const

inline

Returns true if RC is a sub-class of or equal to this class.

Definition at line 138 of file TargetRegisterInfo.h.

References getID(), and SubClassMask.

Referenced by llvm::MachineFunction::addLiveIn(), canFoldCopy(), llvm::SIRegisterInfo::getCompatibleSubRegClass(), hasSubClass(), hasSuperClassEq(), UpdateOperandRegClass(), and llvm::RegisterBank::verify().

◆ hasSuperClass()

bool llvm::TargetRegisterClass::hasSuperClass ( const TargetRegisterClass * RC ) const

inline

Return true if the specified TargetRegisterClass is a proper super-class of this TargetRegisterClass.

Definition at line 145 of file TargetRegisterInfo.h.

References hasSubClass().

◆ hasSuperClassEq()

bool llvm::TargetRegisterClass::hasSuperClassEq ( const TargetRegisterClass * RC ) const

inline

Returns true if RC is a super-class of or equal to this class.

Definition at line 150 of file TargetRegisterInfo.h.

References hasSubClassEq().

Referenced by llvm::AArch64InstrInfo::emitLdStWithAddr(), llvm::SIInstrInfo::foldMemoryOperandImpl(), llvm::PPCInstrInfo::getOperandLatency(), isFPR64(), isFRClass(), isGPR64(), isGRClass(), llvm::SIRegisterInfo::isProperlyAlignedRC(), isVKClass(), llvm::Thumb1InstrInfo::loadRegFromStackSlot(), and llvm::SystemZRegisterInfo::shouldCoalesce().

◆ isAllocatable()

bool llvm::TargetRegisterClass::isAllocatable ( ) const

inline

Return true if this register class may be used to create virtual registers.

Definition at line 126 of file TargetRegisterInfo.h.

References MC.

Referenced by llvm::MachineRegisterInfo::createVirtualRegister(), llvm::TargetRegisterInfo::getAllocatableClass(), getAllocatableSetForRC(), and llvm::MachineRegisterInfo::setRegClass().

◆ isASubClass()

bool llvm::TargetRegisterClass::isASubClass ( ) const

inline

Return true if this TargetRegisterClass is a subset class of at least one other TargetRegisterClass.

Definition at line 194 of file TargetRegisterInfo.h.

References SuperClasses.

◆ isBaseClass()

bool llvm::TargetRegisterClass::isBaseClass ( ) const

inline

Return true if this register class has a defined BaseClassOrder.

Definition at line 129 of file TargetRegisterInfo.h.

References MC.

◆ superclasses()

ArrayRef< unsigned > llvm::TargetRegisterClass::superclasses ( ) const

inline

Returns a list of super-classes.

The classes are ordered by ID which is also a topological ordering from large to small classes. The list does NOT include the current class.

Definition at line 188 of file TargetRegisterInfo.h.

References llvm::ArrayRef(), SuperClasses, and SuperClassesSize.

Referenced by llvm::HexagonRegisterInfo::getHexagonSubRegIndex(), llvm::ARMBaseRegisterInfo::getLargestLegalSuperClass(), llvm::PPCRegisterInfo::getLargestLegalSuperClass(), and llvm::X86RegisterInfo::getLargestLegalSuperClass().

Member Data Documentation

◆ AllocationPriority

const uint8_t llvm::TargetRegisterClass::AllocationPriority

Classes with a higher priority value are assigned first by register allocators using a greedy heuristic.

The value is in the range [0,31].

Definition at line 58 of file TargetRegisterInfo.h.

◆ CoveredBySubRegs

const bool llvm::TargetRegisterClass::CoveredBySubRegs

Whether a combination of subregisters can cover every register in the class.

See also the CoveredBySubRegs description in Target.td.

Definition at line 70 of file TargetRegisterInfo.h.

Referenced by llvm::DeadLaneDetector::transferUsedLanes().

◆ GlobalPriority

const bool llvm::TargetRegisterClass::GlobalPriority

Definition at line 61 of file TargetRegisterInfo.h.

◆ HasDisjunctSubRegs

const bool llvm::TargetRegisterClass::HasDisjunctSubRegs

Whether the class supports two (or more) disjunct subregister indices.

Definition at line 67 of file TargetRegisterInfo.h.

Referenced by llvm::ScheduleDAGInstrs::getLaneMaskForMO(), and llvm::MachineRegisterInfo::shouldTrackSubRegLiveness().

◆ LaneMask

const LaneBitmask llvm::TargetRegisterClass::LaneMask

Definition at line 55 of file TargetRegisterInfo.h.

Referenced by getLaneMask(), llvm::rdf::PhysicalRegisterInfo::mapTo(), llvm::rdf::AggressiveCopyPropagation::run(), llvm::rdf::CopyPropagation::run(), and llvm::DeadLaneDetector::transferUsedLanes().

◆ MC

const MCRegisterClass* llvm::TargetRegisterClass::MC

Definition at line 52 of file TargetRegisterInfo.h.

Referenced by begin(), contains(), contains(), end(), expensiveOrImpossibleToCopy(), getCopyCost(), getID(), llvm::TargetRegisterInfo::getMatchingSuperReg(), getNumRegs(), getRegister(), isAllocatable(), and isBaseClass().

◆ OrderFunc

ArrayRef< MCPhysReg >(* llvm::TargetRegisterClass::OrderFunc) (const MachineFunction &, bool Rev)

Definition at line 72 of file TargetRegisterInfo.h.

Referenced by getRawAllocationOrder().

◆ SpillStackID

const uint8_t llvm::TargetRegisterClass::SpillStackID

Definition at line 65 of file TargetRegisterInfo.h.

Referenced by llvm::TargetRegisterInfo::getSpillStackID().

◆ SubClassMask

const uint32_t* llvm::TargetRegisterClass::SubClassMask

Definition at line 53 of file TargetRegisterInfo.h.

Referenced by getSubClassMask(), and hasSubClassEq().

◆ SuperClasses

const unsigned* llvm::TargetRegisterClass::SuperClasses

Definition at line 71 of file TargetRegisterInfo.h.

Referenced by isASubClass(), and superclasses().

◆ SuperClassesSize

const uint16_t llvm::TargetRegisterClass::SuperClassesSize

Definition at line 72 of file TargetRegisterInfo.h.

Referenced by superclasses().

◆ SuperRegIndices

const uint16_t* llvm::TargetRegisterClass::SuperRegIndices

Definition at line 54 of file TargetRegisterInfo.h.

Referenced by getSuperRegIndices().

◆ TSFlags

const uint8_t llvm::TargetRegisterClass::TSFlags

Configurable target specific flags.

Definition at line 64 of file TargetRegisterInfo.h.

Referenced by llvm::RISCVInstrInfo::copyPhysRegVector(), llvm::RISCVRegisterInfo::findVRegWithEncoding(), llvm::SIRegisterInfo::getRegClassAlignmentNumBits(), llvm::SIRegisterInfo::getSubRegAlignmentNumBits(), llvm::SIRegisterInfo::hasAGPRs(), llvm::SIRegisterInfo::hasSGPRs(), llvm::SIRegisterInfo::hasVGPRs(), llvm::RISCVRegisterInfo::isRVVRegClass(), isTupleInsertInstr(), llvm::RISCVInstrInfo::isVRegCopy(), llvm::RISCVRegisterInfo::isVRNRegClass(), and llvm::RISCVRegisterInfo::isVRRegClass().

The documentation for this class was generated from the following file:

include/llvm/CodeGen/TargetRegisterInfo.h

Public Types

Public Member Functions

Public Attributes

Detailed Description

Member Typedef Documentation

◆ const_iterator

◆ iterator

Member Function Documentation

◆ begin()

◆ contains() [1/2]

◆ contains() [2/2]

◆ end()

◆ expensiveOrImpossibleToCopy()

◆ getCopyCost()

◆ getID()

◆ getLaneMask()

◆ getNumRegs()

◆ getRawAllocationOrder()

◆ getRegister()

◆ getRegisters()

◆ getSubClassMask()

◆ getSuperRegIndices()

◆ hasSubClass()

◆ hasSubClassEq()

◆ hasSuperClass()

◆ hasSuperClassEq()

◆ isAllocatable()

◆ isASubClass()

◆ isBaseClass()

◆ superclasses()

Member Data Documentation

◆ AllocationPriority

◆ CoveredBySubRegs

◆ GlobalPriority

◆ HasDisjunctSubRegs

◆ LaneMask

◆ MC

◆ OrderFunc

◆ SpillStackID

◆ SubClassMask

◆ SuperClasses

◆ SuperClassesSize

◆ SuperRegIndices

◆ TSFlags