LLVM 19.0.0git
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Namespaces | |
namespace | Barrier |
namespace | CPol |
namespace | DepCtr |
namespace | DPP |
namespace | ElfNote |
namespace | EncValues |
namespace | Exp |
namespace | GenericVersion |
Generic target versions emitted by this version of LLVM. | |
namespace | HSAMD |
namespace | HWEncoding |
namespace | Hwreg |
namespace | ImplicitArg |
namespace | IsaInfo |
namespace | MTBUFFormat |
namespace | PALMD |
namespace | SDWA |
namespace | SendMsg |
namespace | Swizzle |
namespace | UfmtGFX10 |
namespace | UfmtGFX11 |
namespace | VGPRIndexMode |
namespace | VirtRegFlag |
namespace | VOP3PEncoding |
namespace | VOPD |
Classes | |
struct | CanBeVOPD |
struct | CustomOperand |
struct | CustomOperandVal |
struct | D16ImageDimIntrinsic |
struct | EncodingField |
struct | EncodingFields |
struct | GcnBufferFormatInfo |
struct | ImageDimIntrinsicInfo |
struct | IsaVersion |
Instruction set architecture version. More... | |
struct | MAIInstInfo |
struct | MCKernelDescriptor |
struct | MIMGBaseOpcodeInfo |
struct | MIMGBiasMappingInfo |
struct | MIMGDimInfo |
struct | MIMGG16MappingInfo |
struct | MIMGInfo |
struct | MIMGLZMappingInfo |
struct | MIMGMIPMappingInfo |
struct | MIMGOffsetMappingInfo |
struct | MTBUFInfo |
struct | MUBUFInfo |
struct | RsrcIntrinsic |
struct | SMInfo |
struct | VOP3CDPPAsmOnlyInfo |
struct | VOPC64DPPInfo |
struct | VOPCDPPAsmOnlyInfo |
struct | VOPDComponentInfo |
struct | VOPDInfo |
struct | VOPInfo |
struct | VOPTrue16Info |
struct | Waitcnt |
Represents the counter values to wait for in an s_waitcnt instruction. More... | |
struct | WMMAOpcodeMappingInfo |
Variables | |
const uint64_t | RSRC_DATA_FORMAT = 0xf00000000000LL |
const uint64_t | RSRC_ELEMENT_SIZE_SHIFT = (32 + 19) |
const uint64_t | RSRC_INDEX_STRIDE_SHIFT = (32 + 21) |
const uint64_t | RSRC_TID_ENABLE = UINT64_C(1) << (32 + 23) |
static constexpr uint32_t | ExtendedFltRoundOffset = 4 |
Offset of nonstandard values for llvm.get.rounding results from the largest supported mode. | |
static constexpr uint32_t | F32FltRoundOffset = 0 |
Offset in mode register of f32 rounding mode. | |
static constexpr uint32_t | F64FltRoundOffset = 2 |
Offset in mode register of f64/f16 rounding mode. | |
const uint64_t | FltRoundConversionTable |
const int | OPR_ID_UNKNOWN = -1 |
const int | OPR_ID_UNSUPPORTED = -2 |
const int | OPR_ID_DUPLICATE = -3 |
const int | OPR_VAL_INVALID = -4 |
anonymous enum |
Enumerator | |
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AMDHSA_COV4 | |
AMDHSA_COV5 | |
AMDHSA_COV6 |
Definition at line 52 of file AMDGPUBaseInfo.h.
enum llvm::AMDGPU::AMDGPUFltRounds : int8_t |
Return values used for llvm.get.rounding.
When both the F32 and F64/F16 modes are the same, returns the standard values. If they differ, returns an extended mode starting at 8.
Definition at line 96 of file SIModeRegisterDefaults.h.
Enumerator | |
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FEATURE_NONE | |
FEATURE_FMA | |
FEATURE_LDEXP | |
FEATURE_FP64 | |
FEATURE_FAST_FMA_F32 | |
FEATURE_FAST_DENORMAL_F32 | |
FEATURE_WAVE32 | |
FEATURE_XNACK | |
FEATURE_SRAMECC | |
FEATURE_WGP |
Definition at line 133 of file TargetParser.h.
Enumerator | |
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SGPR_SPILL |
Definition at line 1512 of file SIInstrInfo.h.
enum llvm::AMDGPU::Fixups |
Enumerator | |
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fixup_si_sopp_br | 16-bit PC relative fixup for SOPP branch instructions. |
LastTargetFixupKind | |
NumTargetFixupKinds |
Definition at line 16 of file AMDGPUFixupKinds.h.
enum llvm::AMDGPU::GPUKind : uint32_t |
GPU kinds supported by the AMDGPU target.
Definition at line 35 of file TargetParser.h.
Enumerator | |
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INT | |
FP16 | |
BF16 | |
FP32 | |
FP64 |
Definition at line 274 of file SIDefines.h.
Definition at line 198 of file SIDefines.h.
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strong |
Enumerator | |
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Initial | |
PreRAReentry | |
PostRA |
Definition at line 20 of file AMDGPUIGroupLP.h.
Definition at line 428 of file AMDGPU.h.
References llvm::AMDGPUAS::MAX_AMDGPU_ADDRESS.
Referenced by llvm::GCNTTIImpl::addrspacesMayAlias(), and llvm::AMDGPUAAResult::alias().
uint64_t llvm::AMDGPU::convertSMRDOffsetUnits | ( | const MCSubtargetInfo & | ST, |
uint64_t | ByteOffset | ||
) |
Convert ByteOffset
to dwords if the subtarget uses dword SMRD immediate offsets.
Definition at line 2905 of file AMDGPUBaseInfo.cpp.
References assert(), hasSMEMByteOffset(), and isDwordAligned().
Referenced by getSMRDEncodedLiteralOffset32(), and getSMRDEncodedOffset().
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Definition at line 1589 of file AMDGPUBaseInfo.cpp.
References Idx, Name, and Size.
Referenced by llvm::AMDGPU::DepCtr::decodeDepCtr().
unsigned llvm::AMDGPU::decodeExpcnt | ( | const IsaVersion & | Version, |
unsigned | Waitcnt | ||
) |
Waitcnt
for given isa Version
. Definition at line 1361 of file AMDGPUBaseInfo.cpp.
Referenced by decodeWaitcnt().
unsigned llvm::AMDGPU::decodeLgkmcnt | ( | const IsaVersion & | Version, |
unsigned | Waitcnt | ||
) |
Waitcnt
for given isa Version
. Definition at line 1366 of file AMDGPUBaseInfo.cpp.
Referenced by decodeWaitcnt().
Waitcnt llvm::AMDGPU::decodeLoadcntDscnt | ( | const IsaVersion & | Version, |
unsigned | LoadcntDscnt | ||
) |
LoadcntDscnt
for given isa Version
. Definition at line 1435 of file AMDGPUBaseInfo.cpp.
References llvm::AMDGPU::Waitcnt::DsCnt, and llvm::AMDGPU::Waitcnt::LoadCnt.
Waitcnt llvm::AMDGPU::decodeStorecntDscnt | ( | const IsaVersion & | Version, |
unsigned | StorecntDscnt | ||
) |
StorecntDscnt
for given isa Version
. Definition at line 1445 of file AMDGPUBaseInfo.cpp.
References llvm::AMDGPU::Waitcnt::DsCnt, and llvm::AMDGPU::Waitcnt::StoreCnt.
unsigned llvm::AMDGPU::decodeVmcnt | ( | const IsaVersion & | Version, |
unsigned | Waitcnt | ||
) |
Waitcnt
for given isa Version
. Definition at line 1353 of file AMDGPUBaseInfo.cpp.
Referenced by decodeWaitcnt().
Waitcnt llvm::AMDGPU::decodeWaitcnt | ( | const IsaVersion & | Version, |
unsigned | Encoded | ||
) |
Definition at line 1378 of file AMDGPUBaseInfo.cpp.
References decodeExpcnt(), decodeLgkmcnt(), decodeVmcnt(), llvm::AMDGPU::Waitcnt::DsCnt, llvm::AMDGPU::Waitcnt::ExpCnt, and llvm::AMDGPU::Waitcnt::LoadCnt.
void llvm::AMDGPU::decodeWaitcnt | ( | const IsaVersion & | Version, |
unsigned | Waitcnt, | ||
unsigned & | Vmcnt, | ||
unsigned & | Expcnt, | ||
unsigned & | Lgkmcnt | ||
) |
Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt
for given isa Version
, and writes decoded values into Vmcnt
, Expcnt
and Lgkmcnt
respectively.
Should not be used on gfx12+, the instruction which needs it is deprecated
Vmcnt
, Expcnt
and Lgkmcnt
are decoded as follows: Vmcnt
= Waitcnt
[3:0] (pre-gfx9) Vmcnt
= Waitcnt
[15:14,3:0] (gfx9,10) Vmcnt
= Waitcnt
[15:10] (gfx11) Expcnt
= Waitcnt
[6:4] (pre-gfx11) Expcnt
= Waitcnt
[2:0] (gfx11) Lgkmcnt
= Waitcnt
[11:8] (pre-gfx10) Lgkmcnt
= Waitcnt
[13:8] (gfx10) Lgkmcnt
= Waitcnt
[9:4] (gfx11)
Definition at line 1371 of file AMDGPUBaseInfo.cpp.
References decodeExpcnt(), decodeLgkmcnt(), and decodeVmcnt().
Referenced by llvm::AMDGPUInstPrinter::printSWaitCnt().
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Definition at line 1613 of file AMDGPUBaseInfo.cpp.
References encodeCustomOperandVal(), Idx, Name, OPR_ID_DUPLICATE, OPR_ID_UNKNOWN, OPR_ID_UNSUPPORTED, and Size.
Referenced by llvm::AMDGPU::DepCtr::encodeDepCtr().
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Definition at line 1606 of file AMDGPUBaseInfo.cpp.
References OPR_VAL_INVALID.
Referenced by encodeCustomOperand().
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Definition at line 1467 of file AMDGPUBaseInfo.cpp.
Referenced by encodeLoadcntDscnt(), and encodeStorecntDscnt().
unsigned llvm::AMDGPU::encodeExpcnt | ( | const IsaVersion & | Version, |
unsigned | Waitcnt, | ||
unsigned | Expcnt | ||
) |
Waitcnt
with encoded Expcnt
for given isa Version
. Definition at line 1395 of file AMDGPUBaseInfo.cpp.
Referenced by encodeWaitcnt().
unsigned llvm::AMDGPU::encodeLgkmcnt | ( | const IsaVersion & | Version, |
unsigned | Waitcnt, | ||
unsigned | Lgkmcnt | ||
) |
Waitcnt
with encoded Lgkmcnt
for given isa Version
. Definition at line 1401 of file AMDGPUBaseInfo.cpp.
Referenced by encodeWaitcnt().
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Definition at line 1455 of file AMDGPUBaseInfo.cpp.
Referenced by encodeLoadcntDscnt().
unsigned llvm::AMDGPU::encodeLoadcntDscnt | ( | const IsaVersion & | Version, |
const Waitcnt & | Decoded | ||
) |
Loadcnt
and Dscnt
components of Decoded
encoded as an immediate that can be used with S_WAIT_LOADCNT_DSCNT for given isa Version
. Definition at line 1481 of file AMDGPUBaseInfo.cpp.
References llvm::AMDGPU::Waitcnt::DsCnt, encodeLoadcntDscnt(), and llvm::AMDGPU::Waitcnt::LoadCnt.
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Definition at line 1473 of file AMDGPUBaseInfo.cpp.
References encodeDscnt(), encodeLoadcnt(), and getCombinedCountBitMask().
Referenced by encodeLoadcntDscnt().
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Definition at line 1461 of file AMDGPUBaseInfo.cpp.
Referenced by encodeStorecntDscnt().
unsigned llvm::AMDGPU::encodeStorecntDscnt | ( | const IsaVersion & | Version, |
const Waitcnt & | Decoded | ||
) |
Storecnt
and Dscnt
components of Decoded
encoded as an immediate that can be used with S_WAIT_STORECNT_DSCNT for given isa Version
. Definition at line 1493 of file AMDGPUBaseInfo.cpp.
References llvm::AMDGPU::Waitcnt::DsCnt, encodeStorecntDscnt(), and llvm::AMDGPU::Waitcnt::StoreCnt.
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Definition at line 1485 of file AMDGPUBaseInfo.cpp.
References encodeDscnt(), encodeStorecnt(), and getCombinedCountBitMask().
Referenced by encodeStorecntDscnt().
unsigned llvm::AMDGPU::encodeVmcnt | ( | const IsaVersion & | Version, |
unsigned | Waitcnt, | ||
unsigned | Vmcnt | ||
) |
Waitcnt
with encoded Vmcnt
for given isa Version
. Definition at line 1386 of file AMDGPUBaseInfo.cpp.
Referenced by encodeWaitcnt().
unsigned llvm::AMDGPU::encodeWaitcnt | ( | const IsaVersion & | Version, |
const Waitcnt & | Decoded | ||
) |
Definition at line 1416 of file AMDGPUBaseInfo.cpp.
References llvm::AMDGPU::Waitcnt::DsCnt, encodeWaitcnt(), llvm::AMDGPU::Waitcnt::ExpCnt, and llvm::AMDGPU::Waitcnt::LoadCnt.
unsigned llvm::AMDGPU::encodeWaitcnt | ( | const IsaVersion & | Version, |
unsigned | Vmcnt, | ||
unsigned | Expcnt, | ||
unsigned | Lgkmcnt | ||
) |
Encodes Vmcnt
, Expcnt
and Lgkmcnt
into Waitcnt for given isa Version
.
Should not be used on gfx12+, the instruction which needs it is deprecated
Vmcnt
, Expcnt
and Lgkmcnt
are encoded as follows: Waitcnt[2:0] = Expcnt
(gfx11+) Waitcnt[3:0] = Vmcnt
(pre-gfx9) Waitcnt[3:0] = Vmcnt
[3:0] (gfx9,10) Waitcnt[6:4] = Expcnt
(pre-gfx11) Waitcnt[9:4] = Lgkmcnt
(gfx11) Waitcnt[11:8] = Lgkmcnt
(pre-gfx10) Waitcnt[13:8] = Lgkmcnt
(gfx10) Waitcnt[15:10] = Vmcnt
(gfx11) Waitcnt[15:14] = Vmcnt
[5:4] (gfx9,10)
Vmcnt
, Expcnt
and Lgkmcnt
for given isa Version
. Definition at line 1407 of file AMDGPUBaseInfo.cpp.
References encodeExpcnt(), encodeLgkmcnt(), encodeVmcnt(), and getWaitcntBitMask().
Referenced by encodeWaitcnt().
void llvm::AMDGPU::fillAMDGPUFeatureMap | ( | StringRef | GPU, |
const Triple & | T, | ||
StringMap< bool > & | Features | ||
) |
Fills Features map with default values for given target GPU.
Definition at line 309 of file TargetParser.cpp.
References llvm::StringRef::empty(), GK_BARTS, GK_CAICOS, GK_CAYMAN, GK_CEDAR, GK_CYPRESS, GK_GFX1010, GK_GFX1011, GK_GFX1012, GK_GFX1013, GK_GFX1030, GK_GFX1031, GK_GFX1032, GK_GFX1033, GK_GFX1034, GK_GFX1035, GK_GFX1036, GK_GFX10_1_GENERIC, GK_GFX10_3_GENERIC, GK_GFX1100, GK_GFX1101, GK_GFX1102, GK_GFX1103, GK_GFX1150, GK_GFX1151, GK_GFX11_GENERIC, GK_GFX1200, GK_GFX1201, GK_GFX600, GK_GFX601, GK_GFX602, GK_GFX700, GK_GFX701, GK_GFX702, GK_GFX703, GK_GFX704, GK_GFX705, GK_GFX801, GK_GFX802, GK_GFX803, GK_GFX805, GK_GFX810, GK_GFX900, GK_GFX902, GK_GFX904, GK_GFX906, GK_GFX908, GK_GFX909, GK_GFX90A, GK_GFX90C, GK_GFX940, GK_GFX941, GK_GFX942, GK_GFX9_GENERIC, GK_JUNIPER, GK_NONE, GK_R600, GK_R630, GK_REDWOOD, GK_RS880, GK_RV670, GK_RV710, GK_RV730, GK_RV770, GK_SUMO, GK_TURKS, llvm_unreachable, parseArchAMDGCN(), and parseArchR600().
void llvm::AMDGPU::fillValidArchListAMDGCN | ( | SmallVectorImpl< StringRef > & | Values | ) |
Definition at line 210 of file TargetParser.cpp.
References llvm::CallingConv::C, and llvm::SmallVectorTemplateBase< T, bool >::push_back().
void llvm::AMDGPU::fillValidArchListR600 | ( | SmallVectorImpl< StringRef > & | Values | ) |
Definition at line 216 of file TargetParser.cpp.
References llvm::CallingConv::C, and llvm::SmallVectorTemplateBase< T, bool >::push_back().
LLVM_READONLY int llvm::AMDGPU::getAddr64Inst | ( | uint16_t | Opcode | ) |
Referenced by llvm::SIInstrInfo::legalizeOperands().
LLVM_READONLY unsigned llvm::AMDGPU::getAddrSizeMIMGOp | ( | const MIMGBaseOpcodeInfo * | BaseOpcode, |
const MIMGDimInfo * | Dim, | ||
bool | IsA16, | ||
bool | IsG16Supported | ||
) |
Definition at line 287 of file AMDGPUBaseInfo.cpp.
References llvm::AMDGPU::MIMGBaseOpcodeInfo::Coordinates, llvm::divideCeil(), llvm::AMDGPU::MIMGBaseOpcodeInfo::G16, llvm::AMDGPU::MIMGBaseOpcodeInfo::Gradients, llvm::AMDGPU::MIMGBaseOpcodeInfo::LodOrClampOrMip, llvm::AMDGPU::MIMGDimInfo::NumCoords, llvm::AMDGPU::MIMGBaseOpcodeInfo::NumExtraArgs, and llvm::AMDGPU::MIMGDimInfo::NumGradients.
Referenced by llvm::AMDGPUDisassembler::convertMIMGInst(), and llvm::SIInstrInfo::verifyInstruction().
Align llvm::AMDGPU::getAlign | ( | DataLayout const & | DL, |
const GlobalVariable * | GV | ||
) |
Definition at line 29 of file AMDGPUMemoryUtils.cpp.
References DL, llvm::Value::getPointerAlignment(), and llvm::GlobalValue::getValueType().
Definition at line 166 of file AMDGPUBaseInfo.cpp.
References getDefaultAMDHSACodeObjectVersion().
Referenced by llvm::SITargetLowering::allocateHSAUserSGPRs(), allocateHSAUserSGPRs(), llvm::SITargetLowering::allocateSpecialInputSGPRs(), llvm::AMDGPUAsmPrinter::doInitialization(), llvm::AMDGPU::HSAMD::MetadataStreamerMsgPackV4::emitKernel(), llvm::AMDGPUSubtarget::getImplicitArgNumBytes(), llvm::AMDGPULegalizerInfo::getSegmentAperture(), llvm::AMDGPULegalizerInfo::legalizeTrapHsaQueuePtr(), llvm::AMDGPULowerKernelAttributesPass::run(), llvm::AMDGPUResourceUsageAnalysis::runOnModule(), and llvm::AMDGPUDisassembler::setABIVersion().
Definition at line 179 of file AMDGPUBaseInfo.cpp.
References llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V4, llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V5, llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V6, and getDefaultAMDHSACodeObjectVersion().
Definition at line 198 of file TargetParser.cpp.
References FEATURE_NONE.
Definition at line 204 of file TargetParser.cpp.
References FEATURE_NONE.
Definition at line 152 of file TargetParser.cpp.
References llvm::StringRef::drop_back(), llvm::StringRef::empty(), getArchNameAMDGCN(), GK_GFX10_1_GENERIC, GK_GFX10_3_GENERIC, GK_GFX11_GENERIC, and GK_GFX9_GENERIC.
Definition at line 168 of file TargetParser.cpp.
Referenced by getArchFamilyNameAMDGCN(), llvm::AMDGPUTargetStreamer::getArchNameFromElfMach(), and getCanonicalArchName().
Definition at line 174 of file TargetParser.cpp.
Referenced by llvm::AMDGPUTargetStreamer::getArchNameFromElfMach(), and getCanonicalArchName().
std::pair< Register, unsigned > llvm::AMDGPU::getBaseWithConstantOffset | ( | MachineRegisterInfo & | MRI, |
Register | Reg, | ||
GISelKnownBits * | KnownBits = nullptr , |
||
bool | CheckNUW = false |
||
) |
Returns base register and constant offset.
Definition at line 20 of file AMDGPUGlobalISelUtils.cpp.
References assert(), llvm::sampleprof::Base, llvm::getDefIgnoringCopies(), llvm::MIPatternMatch::m_Copy(), llvm::MIPatternMatch::m_GOr(), llvm::MIPatternMatch::m_GPtrAdd(), llvm::MIPatternMatch::m_ICst(), llvm::MIPatternMatch::m_MInstr(), llvm::MIPatternMatch::m_Reg(), llvm::MIPatternMatch::mi_match(), MRI, llvm::MachineInstr::NoUWrap, and llvm::Offset.
Referenced by llvm::AMDGPURegisterBankInfo::applyMappingImpl(), computeIndirectRegIndex(), llvm::AMDGPURegisterBankInfo::setBufferOffsets(), and llvm::AMDGPULegalizerInfo::splitBufferOffsets().
LLVM_READONLY int llvm::AMDGPU::getBasicFromSDWAOp | ( | uint16_t | Opcode | ) |
Referenced by llvm::SIInstrInfo::verifyInstruction().
unsigned llvm::AMDGPU::getBvhcntBitMask | ( | const IsaVersion & | Version | ) |
Version
. Returns 0 for versions that do not support BVHcnt Definition at line 1317 of file AMDGPUBaseInfo.cpp.
LLVM_READONLY CanBeVOPD llvm::AMDGPU::getCanBeVOPD | ( | unsigned | Opc | ) |
Definition at line 521 of file AMDGPUBaseInfo.cpp.
References Info.
Referenced by shouldScheduleVOPDAdjacent().
Definition at line 300 of file TargetParser.cpp.
References assert(), getArchNameAMDGCN(), getArchNameR600(), GK_NONE, parseArchAMDGCN(), and parseArchR600().
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Definition at line 1420 of file AMDGPUBaseInfo.cpp.
Referenced by encodeLoadcntDscnt(), and encodeStorecntDscnt().
LLVM_READONLY int llvm::AMDGPU::getCommuteOrig | ( | uint16_t | Opcode | ) |
Referenced by llvm::SIInstrInfo::commuteOpcode().
LLVM_READONLY int llvm::AMDGPU::getCommuteRev | ( | uint16_t | Opcode | ) |
Referenced by llvm::SIInstrInfo::commuteOpcode().
Definition at line 245 of file AMDGPUBaseInfo.cpp.
References AMDHSA_COV4, AMDHSA_COV5, AMDHSA_COV6, and llvm::AMDGPU::ImplicitArg::COMPLETION_ACTION_OFFSET.
unsigned llvm::AMDGPU::getDefaultAMDHSACodeObjectVersion | ( | ) |
Definition at line 175 of file AMDGPUBaseInfo.cpp.
References DefaultAMDHSACodeObjectVersion.
Referenced by getAMDHSACodeObjectVersion().
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Definition at line 1558 of file AMDGPUBaseInfo.cpp.
Referenced by llvm::AMDGPU::DepCtr::getDefaultDepCtrEncoding().
Definition at line 234 of file AMDGPUBaseInfo.cpp.
References AMDHSA_COV4, AMDHSA_COV5, AMDHSA_COV6, and llvm::AMDGPU::ImplicitArg::DEFAULT_QUEUE_OFFSET.
LLVM_READONLY int llvm::AMDGPU::getDPPOp32 | ( | uint16_t | Opcode | ) |
LLVM_READONLY int llvm::AMDGPU::getDPPOp64 | ( | uint16_t | Opcode | ) |
unsigned llvm::AMDGPU::getDscntBitMask | ( | const IsaVersion & | Version | ) |
Version
. Returns 0 for versions that do not support DScnt Definition at line 1329 of file AMDGPUBaseInfo.cpp.
CodeObjectVersion | is a value returned by getAMDHSACodeObjectVersion(). |
Definition at line 192 of file AMDGPUBaseInfo.cpp.
References llvm::Triple::AMDHSA, llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V4, llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V5, llvm::ELF::ELFABIVERSION_AMDGPU_HSA_V6, and llvm::report_fatal_error().
Referenced by llvm::AMDGPUTargetELFStreamer::finish().
unsigned llvm::AMDGPU::getExpcntBitMask | ( | const IsaVersion & | Version | ) |
Version
. Definition at line 1321 of file AMDGPUBaseInfo.cpp.
Referenced by llvm::AMDGPUInstPrinter::printSWaitCnt().
LLVM_READONLY int llvm::AMDGPU::getFlatScratchInstSSfromSV | ( | uint16_t | Opcode | ) |
Opcode
of an SV (VADDR) form. LLVM_READONLY int llvm::AMDGPU::getFlatScratchInstSTfromSS | ( | uint16_t | Opcode | ) |
Opcode
of an SS (SADDR) form. Referenced by llvm::SIRegisterInfo::buildSpillLoadStore(), llvm::SIRegisterInfo::eliminateFrameIndex(), and getFlatScratchSpillOpcode().
LLVM_READONLY int llvm::AMDGPU::getFlatScratchInstSVfromSS | ( | uint16_t | Opcode | ) |
Opcode
of an SS (SADDR) form. Referenced by llvm::SIRegisterInfo::buildSpillLoadStore(), getFlatScratchSpillOpcode(), and llvm::SIInstrInfo::moveFlatAddrToVGPR().
LLVM_READONLY int llvm::AMDGPU::getFlatScratchInstSVfromSVS | ( | uint16_t | Opcode | ) |
Opcode
of an SVS (SADDR + VADDR) form. Referenced by llvm::SIRegisterInfo::eliminateFrameIndex().
LLVM_READONLY const GcnBufferFormatInfo * llvm::AMDGPU::getGcnBufferFormatInfo | ( | uint8_t | BitsPerComp, |
uint8_t | NumComponents, | ||
uint8_t | NumFormat, | ||
const MCSubtargetInfo & | STI | ||
) |
Definition at line 2984 of file AMDGPUBaseInfo.cpp.
References isGFX10(), and isGFX11Plus().
Referenced by getBufferFormatWithCompCount().
LLVM_READONLY const GcnBufferFormatInfo * llvm::AMDGPU::getGcnBufferFormatInfo | ( | uint8_t | Format, |
const MCSubtargetInfo & | STI | ||
) |
Definition at line 2997 of file AMDGPUBaseInfo.cpp.
References llvm::Format, isGFX10(), and isGFX11Plus().
LLVM_READONLY int llvm::AMDGPU::getGlobalSaddrOp | ( | uint16_t | Opcode | ) |
Opcode
of a VADDR form. LLVM_READONLY int llvm::AMDGPU::getGlobalVaddrOp | ( | uint16_t | Opcode | ) |
Opcode
of a SADDR form. Referenced by llvm::SIInstrInfo::moveFlatAddrToVGPR().
Definition at line 2035 of file AMDGPUBaseInfo.cpp.
References llvm::CallingConv::AMDGPU_PS, and F.
Referenced by generateEndPgm().
Definition at line 223 of file AMDGPUBaseInfo.cpp.
References AMDHSA_COV4, AMDHSA_COV5, AMDHSA_COV6, and llvm::AMDGPU::ImplicitArg::HOSTCALL_PTR_OFFSET.
LLVM_READONLY int llvm::AMDGPU::getIfAddr64Inst | ( | uint16_t | Opcode | ) |
Check if Opcode
is an Addr64 opcode.
Opcode
if it is an Addr64 opcode, otherwise -1. Referenced by llvm::SIInstrInfo::legalizeOperands().
const ImageDimIntrinsicInfo * llvm::AMDGPU::getImageDimIntrinsicByBaseOpcode | ( | unsigned | BaseOpcode, |
unsigned | Dim | ||
) |
Referenced by simplifyAMDGCNImageIntrinsic().
const ImageDimIntrinsicInfo * llvm::AMDGPU::getImageDimIntrinsicInfo | ( | unsigned | Intr | ) |
Definition at line 2031 of file AMDGPUBaseInfo.cpp.
References F.
Referenced by llvm::SIMachineFunctionInfo::SIMachineFunctionInfo().
Definition at line 2683 of file AMDGPUBaseInfo.cpp.
References llvm::Literal, and Signed.
Referenced by getInlineEncodingV2F16(), getInlineEncodingV2I16(), and isInlinableLiteralV216().
LLVM_READNONE std::optional< unsigned > llvm::AMDGPU::getInlineEncodingV2BF16 | ( | uint32_t | Literal | ) |
Definition at line 2744 of file AMDGPUBaseInfo.cpp.
References llvm::Literal, and Signed.
Referenced by llvm::SITargetLowering::checkAsmConstraintValA(), and isInlinableLiteralV2BF16().
LLVM_READNONE std::optional< unsigned > llvm::AMDGPU::getInlineEncodingV2F16 | ( | uint32_t | Literal | ) |
Definition at line 2772 of file AMDGPUBaseInfo.cpp.
References getInlineEncodingV216(), and llvm::Literal.
Referenced by llvm::SITargetLowering::checkAsmConstraintValA(), and isInlinableLiteralV2F16().
LLVM_READNONE std::optional< unsigned > llvm::AMDGPU::getInlineEncodingV2I16 | ( | uint32_t | Literal | ) |
Definition at line 2738 of file AMDGPUBaseInfo.cpp.
References getInlineEncodingV216(), and llvm::Literal.
Referenced by llvm::SITargetLowering::checkAsmConstraintValA(), and isInlinableLiteralV2I16().
F's
Name
attribute.Default
if attribute is not present.Default
and emits error if requested value cannot be converted to integer. std::pair< unsigned, unsigned > llvm::AMDGPU::getIntegerPairAttribute | ( | const Function & | F, |
StringRef | Name, | ||
std::pair< unsigned, unsigned > | Default, | ||
bool | OnlyFirstRequired = false |
||
) |
F's
Name
attribute in "first[,second]" format ("second" is optional unless OnlyFirstRequired
is false).Default
if attribute is not present.Default
and emits error if one of the requested values cannot be converted to integer, or OnlyFirstRequired
is false and "second" value is not present. Definition at line 1243 of file AMDGPUBaseInfo.cpp.
References A, llvm::Default, llvm::LLVMContext::emitError(), F, and Name.
Referenced by llvm::AMDGPUMachineFunction::AMDGPUMachineFunction(), llvm::AMDGPUSubtarget::getFlatWorkGroupSizes(), and llvm::AMDGPUSubtarget::getWavesPerEU().
SmallVector< unsigned > llvm::AMDGPU::getIntegerVecAttribute | ( | const Function & | F, |
StringRef | Name, | ||
unsigned | Size | ||
) |
F's
Name
attribute.Definition at line 1267 of file AMDGPUBaseInfo.cpp.
References A, assert(), llvm::Default, llvm::LLVMContext::emitError(), llvm::StringRef::empty(), F, Name, Size, and llvm::StringRef::split().
Referenced by llvm::AMDGPUSubtarget::getMaxNumWorkGroups().
Intrinsic::ID llvm::AMDGPU::getIntrinsicID | ( | const MachineInstr & | I | ) |
Return the intrinsic ID for opcodes with the G_AMDGPU_INTRIN_ prefix.
These opcodes have an Intrinsic::ID operand similar to a GIntrinsic. But they are not actual instances of GIntrinsics, so we cannot use GIntrinsic::getIntrinsicID() on them.
Definition at line 30 of file AMDGPUInstrInfo.cpp.
References I.
Referenced by llvm::AMDGPURegisterBankInfo::applyMappingImpl(), llvm::AMDGPURegisterBankInfo::getInstrMapping(), and llvm::AMDGPUInstructionSelector::select().
AMDGPU::IsaVersion llvm::AMDGPU::getIsaVersion | ( | StringRef | GPU | ) |
Definition at line 221 of file TargetParser.cpp.
References GK_GFX1010, GK_GFX1011, GK_GFX1012, GK_GFX1013, GK_GFX1030, GK_GFX1031, GK_GFX1032, GK_GFX1033, GK_GFX1034, GK_GFX1035, GK_GFX1036, GK_GFX10_1_GENERIC, GK_GFX10_3_GENERIC, GK_GFX1100, GK_GFX1101, GK_GFX1102, GK_GFX1103, GK_GFX1150, GK_GFX1151, GK_GFX11_GENERIC, GK_GFX1200, GK_GFX1201, GK_GFX600, GK_GFX601, GK_GFX602, GK_GFX700, GK_GFX701, GK_GFX702, GK_GFX703, GK_GFX704, GK_GFX705, GK_GFX801, GK_GFX802, GK_GFX803, GK_GFX805, GK_GFX810, GK_GFX900, GK_GFX902, GK_GFX904, GK_GFX906, GK_GFX908, GK_GFX909, GK_GFX90A, GK_GFX90C, GK_GFX940, GK_GFX941, GK_GFX942, GK_GFX9_GENERIC, and parseArchAMDGCN().
Referenced by llvm::AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor(), llvm::AMDGPU::IsaInfo::getAddressableNumSGPRs(), llvm::AMDGPU::MCKernelDescriptor::getDefaultAmdhsaKernelDescriptor(), llvm::AMDGPU::IsaInfo::getMaxNumSGPRs(), llvm::AMDGPU::IsaInfo::getMinNumSGPRs(), getNSAMaxSize(), llvm::AMDGPU::IsaInfo::getNumExtraSGPRs(), llvm::AMDGPU::IsaInfo::getSGPRAllocGranule(), llvm::AMDGPU::IsaInfo::getTotalNumSGPRs(), initDefaultAMDKernelCodeT(), llvm::AMDGPUInstPrinter::printSWaitCnt(), and llvm::AMDGPU::IsaInfo::AMDGPUTargetID::toString().
unsigned llvm::AMDGPU::getKmcntBitMask | ( | const IsaVersion & | Version | ) |
Version
. Returns 0 for versions that do not support KMcnt Definition at line 1333 of file AMDGPUBaseInfo.cpp.
unsigned llvm::AMDGPU::getLdsDwGranularity | ( | const MCSubtargetInfo & | ST | ) |
This
is used to calculate the lds size encoded for PAL metadata 3.0+ which must be defined in terms of bytes. Definition at line 3023 of file AMDGPUBaseInfo.cpp.
Referenced by EmitPALMetadataCommon().
unsigned llvm::AMDGPU::getLgkmcntBitMask | ( | const IsaVersion & | Version | ) |
Version
. Definition at line 1325 of file AMDGPUBaseInfo.cpp.
Referenced by llvm::AMDGPUInstPrinter::printSWaitCnt().
unsigned llvm::AMDGPU::getLoadcntBitMask | ( | const IsaVersion & | Version | ) |
Version
. Returns 0 for versions that do not support LOADcnt Definition at line 1309 of file AMDGPUBaseInfo.cpp.
LLVM_READONLY bool llvm::AMDGPU::getMAIIsDGEMM | ( | unsigned | Opc | ) |
Returns true if MAI operation is a double precision GEMM.
Definition at line 503 of file AMDGPUBaseInfo.cpp.
References Info.
Referenced by isDGEMM().
LLVM_READONLY bool llvm::AMDGPU::getMAIIsGFX940XDL | ( | unsigned | Opc | ) |
LLVM_READONLY int llvm::AMDGPU::getMaskedMIMGOp | ( | unsigned | Opc, |
unsigned | NewChannels | ||
) |
Definition at line 279 of file AMDGPUBaseInfo.cpp.
References llvm::AMDGPU::MIMGInfo::BaseOpcode, getMIMGInfo(), llvm::AMDGPU::MIMGInfo::MIMGEncoding, llvm::AMDGPU::MIMGInfo::Opcode, and llvm::AMDGPU::MIMGInfo::VAddrDwords.
unsigned llvm::AMDGPU::getMaxNumUserSGPRs | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 2151 of file AMDGPUBaseInfo.cpp.
Referenced by llvm::GCNUserSGPRUsageInfo::allocKernargPreloadSGPRs(), llvm::GCNSubtarget::getMaxNumUserSGPRs(), and llvm::GCNUserSGPRUsageInfo::getNumFreeUserSGPRs().
LLVM_READONLY int llvm::AMDGPU::getMCOpcode | ( | uint16_t | Opcode, |
unsigned | Gen | ||
) |
Definition at line 623 of file AMDGPUBaseInfo.cpp.
Referenced by llvm::SIInstrInfo::pseudoToMCOpcode().
unsigned llvm::AMDGPU::getMCReg | ( | unsigned | Reg, |
const MCSubtargetInfo & | STI | ||
) |
If Reg
is a pseudo reg, return the correct hardware register given STI
otherwise return Reg
.
Definition at line 2352 of file AMDGPUBaseInfo.cpp.
References llvm::Triple::getArch(), llvm::MCSubtargetInfo::getTargetTriple(), MAP_REG2REG, llvm::Triple::r600, and Reg.
Referenced by llvm::AMDGPUDisassembler::createRegOperand(), and AMDGPUMCInstLower::lowerOperand().
LLVM_READONLY int llvm::AMDGPU::getMFMAEarlyClobberOp | ( | uint16_t | Opcode | ) |
Referenced by llvm::SIInstrInfo::convertToThreeAddress(), and llvm::SIInstrInfo::pseudoToMCOpcode().
LLVM_READONLY const MIMGBaseOpcodeInfo * llvm::AMDGPU::getMIMGBaseOpcode | ( | unsigned | Opc | ) |
Definition at line 274 of file AMDGPUBaseInfo.cpp.
References getMIMGBaseOpcodeInfo(), getMIMGInfo(), and Info.
LLVM_READONLY const MIMGBaseOpcodeInfo * llvm::AMDGPU::getMIMGBaseOpcodeInfo | ( | unsigned | BaseOpcode | ) |
LLVM_READONLY const MIMGBiasMappingInfo * llvm::AMDGPU::getMIMGBiasMappingInfo | ( | unsigned | Bias | ) |
Referenced by simplifyAMDGCNImageIntrinsic().
LLVM_READONLY const MIMGDimInfo * llvm::AMDGPU::getMIMGDimInfo | ( | unsigned | DimEnum | ) |
LLVM_READONLY const MIMGDimInfo * llvm::AMDGPU::getMIMGDimInfoByAsmSuffix | ( | StringRef | AsmSuffix | ) |
LLVM_READONLY const MIMGDimInfo * llvm::AMDGPU::getMIMGDimInfoByEncoding | ( | uint8_t | DimEnc | ) |
Referenced by llvm::AMDGPUDisassembler::convertMIMGInst(), and llvm::SIInstrInfo::verifyInstruction().
LLVM_READONLY const MIMGG16MappingInfo * llvm::AMDGPU::getMIMGG16MappingInfo | ( | unsigned | G | ) |
LLVM_READONLY const MIMGInfo * llvm::AMDGPU::getMIMGInfo | ( | unsigned | Opc | ) |
LLVM_READONLY const MIMGLZMappingInfo * llvm::AMDGPU::getMIMGLZMappingInfo | ( | unsigned | L | ) |
Referenced by simplifyAMDGCNImageIntrinsic().
LLVM_READONLY const MIMGMIPMappingInfo * llvm::AMDGPU::getMIMGMIPMappingInfo | ( | unsigned | MIP | ) |
Referenced by simplifyAMDGCNImageIntrinsic().
LLVM_READONLY const MIMGOffsetMappingInfo * llvm::AMDGPU::getMIMGOffsetMappingInfo | ( | unsigned | Offset | ) |
Referenced by simplifyAMDGCNImageIntrinsic().
LLVM_READONLY int llvm::AMDGPU::getMIMGOpcode | ( | unsigned | BaseOpcode, |
unsigned | MIMGEncoding, | ||
unsigned | VDataDwords, | ||
unsigned | VAddrDwords | ||
) |
Definition at line 267 of file AMDGPUBaseInfo.cpp.
References Info.
Referenced by llvm::AMDGPUDisassembler::convertMIMGInst(), and llvm::AMDGPULegalizerInfo::legalizeBVHIntrinsic().
LLVM_READONLY int llvm::AMDGPU::getMTBUFBaseOpcode | ( | unsigned | Opc | ) |
Definition at line 407 of file AMDGPUBaseInfo.cpp.
References Info.
LLVM_READONLY int llvm::AMDGPU::getMTBUFElements | ( | unsigned | Opc | ) |
Definition at line 417 of file AMDGPUBaseInfo.cpp.
References Info.
LLVM_READONLY bool llvm::AMDGPU::getMTBUFHasSoffset | ( | unsigned | Opc | ) |
Definition at line 432 of file AMDGPUBaseInfo.cpp.
References Info.
LLVM_READONLY bool llvm::AMDGPU::getMTBUFHasSrsrc | ( | unsigned | Opc | ) |
Definition at line 427 of file AMDGPUBaseInfo.cpp.
References Info.
LLVM_READONLY bool llvm::AMDGPU::getMTBUFHasVAddr | ( | unsigned | Opc | ) |
Definition at line 422 of file AMDGPUBaseInfo.cpp.
References Info.
LLVM_READONLY int llvm::AMDGPU::getMTBUFOpcode | ( | unsigned | BaseOpc, |
unsigned | Elements | ||
) |
Definition at line 412 of file AMDGPUBaseInfo.cpp.
References Info.
LLVM_READONLY int llvm::AMDGPU::getMUBUFBaseOpcode | ( | unsigned | Opc | ) |
Definition at line 437 of file AMDGPUBaseInfo.cpp.
References Info.
LLVM_READONLY int llvm::AMDGPU::getMUBUFElements | ( | unsigned | Opc | ) |
Definition at line 447 of file AMDGPUBaseInfo.cpp.
References Info.
LLVM_READONLY bool llvm::AMDGPU::getMUBUFHasSoffset | ( | unsigned | Opc | ) |
Definition at line 462 of file AMDGPUBaseInfo.cpp.
References Info.
LLVM_READONLY bool llvm::AMDGPU::getMUBUFHasSrsrc | ( | unsigned | Opc | ) |
Definition at line 457 of file AMDGPUBaseInfo.cpp.
References Info.
LLVM_READONLY bool llvm::AMDGPU::getMUBUFHasVAddr | ( | unsigned | Opc | ) |
Definition at line 452 of file AMDGPUBaseInfo.cpp.
References Info.
LLVM_READONLY bool llvm::AMDGPU::getMUBUFIsBufferInv | ( | unsigned | Opc | ) |
Definition at line 467 of file AMDGPUBaseInfo.cpp.
References Info.
LLVM_READONLY int llvm::AMDGPU::getMUBUFOpcode | ( | unsigned | BaseOpc, |
unsigned | Elements | ||
) |
Definition at line 442 of file AMDGPUBaseInfo.cpp.
References Info.
LLVM_READONLY bool llvm::AMDGPU::getMUBUFTfe | ( | unsigned | Opc | ) |
Definition at line 472 of file AMDGPUBaseInfo.cpp.
References Info.
Referenced by llvm::SITargetLowering::AddMemOpInit().
Definition at line 209 of file AMDGPUBaseInfo.cpp.
References AMDHSA_COV4, AMDHSA_COV5, AMDHSA_COV6, and llvm::AMDGPU::ImplicitArg::MULTIGRID_SYNC_ARG_OFFSET.
LLVM_READONLY int16_t llvm::AMDGPU::getNamedOperandIdx | ( | uint16_t | Opcode, |
uint16_t | NamedIdx | ||
) |
Referenced by llvm::SITargetLowering::AddMemOpInit(), addSrcModifiersAndSrc(), llvm::SITargetLowering::AdjustInstrPostInstrSelection(), llvm::SIInstrInfo::areLoadsFromSameBasePtr(), llvm::SIInstrInfo::buildShrunkInst(), llvm::SIRegisterInfo::buildSpillLoadStore(), collectVOPModifiers(), llvm::SIInstrInfo::commuteInstructionImpl(), llvm::AMDGPUDisassembler::convertDPP8Inst(), llvm::AMDGPUDisassembler::convertMIMGInst(), llvm::AMDGPUDisassembler::convertSDWAInst(), llvm::SIInstrInfo::convertToThreeAddress(), llvm::AMDGPUDisassembler::convertTrue16OpSel(), llvm::AMDGPUDisassembler::convertVOP3DPPInst(), cvtVOP3DstOpSelOnly(), decodeAVLdSt(), llvm::AMDGPUDisassembler::decodeVOPDDstYOp(), llvm::SIRegisterInfo::eliminateFrameIndex(), llvm::SIInstrInfo::enforceOperandRCAlignment(), llvm::SIInstrInfo::findCommutedOpIndices(), llvm::SIInstrInfo::foldImmediate(), llvm::SIRegisterInfo::getFrameIndexInstrOffset(), llvm::AMDGPUDisassembler::getInstruction(), llvm::SIInstrInfo::getInstSizeInBytes(), llvm::SIInstrInfo::getMemOperandsWithOffsetWidth(), llvm::SIInstrInfo::getNamedImmOperand(), llvm::SIInstrInfo::getNamedOperand(), llvm::SIInstrInfo::getRegClass(), llvm::SIRegisterInfo::getScratchInstrOffset(), getSrcOperandIndices(), hasAny64BitVGPROperands(), hasNamedOperand(), llvm::SIInstrWorklist::insert(), insertNamedMCOperand(), IsAGPROperand(), llvm::SIInstrInfo::isBufferSMRD(), llvm::SIInstrInfo::isImmOperandLegal(), llvm::AMDGPUDisassembler::isMacDPP(), llvm::SIInstrInfo::isOperandLegal(), isSendMsgTraceDataOrGDS(), llvm::SIInstrInfo::legalizeOperands(), llvm::SIInstrInfo::legalizeOperandsVOP2(), llvm::SIInstrInfo::legalizeOperandsVOP3(), AMDGPUMCInstLower::lower(), llvm::SIInstrInfo::moveFlatAddrToVGPR(), llvm::SIInstrInfo::moveToVALUImpl(), nodesHaveSameOperandValue(), llvm::SIFrameLowering::processFunctionBeforeFrameFinalized(), llvm::SIInstrInfo::removeModOperands(), updateOperandIfDifferent(), and llvm::SIInstrInfo::verifyInstruction().
unsigned llvm::AMDGPU::getNSAMaxSize | ( | const MCSubtargetInfo & | STI, |
bool | HasSampler | ||
) |
Definition at line 2140 of file AMDGPUBaseInfo.cpp.
References llvm::MCSubtargetInfo::getCPU(), and getIsaVersion().
Referenced by llvm::GCNSubtarget::getNSAMaxSize().
unsigned llvm::AMDGPU::getNumFlatOffsetBits | ( | const MCSubtargetInfo & | ST | ) |
For pre-GFX12 FLAT instructions the offset must be positive; MSB is ignored and forced to zero.
Definition at line 2946 of file AMDGPUBaseInfo.cpp.
References isGFX10(), and isGFX12().
Referenced by llvm::SIInstrInfo::isLegalFLATOffset(), and llvm::SIInstrInfo::splitFlatOffset().
|
inline |
Definition at line 1399 of file AMDGPUBaseInfo.h.
References getOperandSize().
|
inline |
Definition at line 1346 of file AMDGPUBaseInfo.h.
References llvm_unreachable, OPERAND_INLINE_SPLIT_BARRIER_INT32, OPERAND_KIMM16, OPERAND_KIMM32, OPERAND_REG_IMM_BF16, OPERAND_REG_IMM_BF16_DEFERRED, OPERAND_REG_IMM_FP16, OPERAND_REG_IMM_FP16_DEFERRED, OPERAND_REG_IMM_FP32, OPERAND_REG_IMM_FP32_DEFERRED, OPERAND_REG_IMM_FP64, OPERAND_REG_IMM_INT16, OPERAND_REG_IMM_INT32, OPERAND_REG_IMM_INT64, OPERAND_REG_IMM_V2BF16, OPERAND_REG_IMM_V2FP16, OPERAND_REG_IMM_V2FP32, OPERAND_REG_IMM_V2INT16, OPERAND_REG_IMM_V2INT32, OPERAND_REG_INLINE_AC_BF16, OPERAND_REG_INLINE_AC_FP16, OPERAND_REG_INLINE_AC_FP32, OPERAND_REG_INLINE_AC_FP64, OPERAND_REG_INLINE_AC_INT16, OPERAND_REG_INLINE_AC_INT32, OPERAND_REG_INLINE_AC_V2BF16, OPERAND_REG_INLINE_AC_V2FP16, OPERAND_REG_INLINE_AC_V2INT16, OPERAND_REG_INLINE_C_BF16, OPERAND_REG_INLINE_C_FP16, OPERAND_REG_INLINE_C_FP32, OPERAND_REG_INLINE_C_FP64, OPERAND_REG_INLINE_C_INT16, OPERAND_REG_INLINE_C_INT32, OPERAND_REG_INLINE_C_INT64, OPERAND_REG_INLINE_C_V2BF16, OPERAND_REG_INLINE_C_V2FP16, OPERAND_REG_INLINE_C_V2FP32, OPERAND_REG_INLINE_C_V2INT16, OPERAND_REG_INLINE_C_V2INT32, and llvm::MCOperandInfo::OperandType.
Referenced by getOperandSize().
|
static |
Definition at line 1532 of file AMDGPUBaseInfo.cpp.
References Context, Name, and llvm::Test.
|
static |
Definition at line 1539 of file AMDGPUBaseInfo.cpp.
References Context, llvm::AMDGPU::CustomOperand< T >::Encoding, and llvm::Test.
|
static |
Definition at line 1517 of file AMDGPUBaseInfo.cpp.
References Cond, Context, Idx, OPR_ID_UNKNOWN, OPR_ID_UNSUPPORTED, and llvm::Test.
unsigned llvm::AMDGPU::getRegBitWidth | ( | const MCRegisterClass & | RC | ) |
Get the size in bits of a register from the register class RC
.
Definition at line 2591 of file AMDGPUBaseInfo.cpp.
References llvm::MCRegisterClass::getID(), and getRegBitWidth().
unsigned llvm::AMDGPU::getRegBitWidth | ( | const TargetRegisterClass & | RC | ) |
Get the size in bits of a register from the register class RC
.
Definition at line 2603 of file SIRegisterInfo.cpp.
References llvm::TargetRegisterClass::getID(), and getRegBitWidth().
Referenced by llvm::SIRegisterInfo::buildSpillLoadStore(), llvm::SIInstrInfo::canInsertSelect(), getRegBitWidth(), getRegOperandSize(), and llvm::SIRegisterInfo::getRegSplitParts().
Get the size in bits of a register from the register class RC
.
Definition at line 2452 of file AMDGPUBaseInfo.cpp.
References llvm_unreachable.
unsigned llvm::AMDGPU::getRegOperandSize | ( | const MCRegisterInfo * | MRI, |
const MCInstrDesc & | Desc, | ||
unsigned | OpNo | ||
) |
Get size of register operand.
Definition at line 2595 of file AMDGPUBaseInfo.cpp.
References assert(), and getRegBitWidth().
unsigned llvm::AMDGPU::getSamplecntBitMask | ( | const IsaVersion & | Version | ) |
Version
. Returns 0 for versions that do not support SAMPLEcnt Definition at line 1313 of file AMDGPUBaseInfo.cpp.
LLVM_READONLY int llvm::AMDGPU::getSDWAOp | ( | uint16_t | Opcode | ) |
LLVM_READONLY bool llvm::AMDGPU::getSMEMIsBuffer | ( | unsigned | Opc | ) |
Definition at line 477 of file AMDGPUBaseInfo.cpp.
References Info.
std::optional< int64_t > llvm::AMDGPU::getSMRDEncodedLiteralOffset32 | ( | const MCSubtargetInfo & | ST, |
int64_t | ByteOffset | ||
) |
Definition at line 2936 of file AMDGPUBaseInfo.cpp.
References convertSMRDOffsetUnits(), isCI(), and isDwordAligned().
std::optional< int64_t > llvm::AMDGPU::getSMRDEncodedOffset | ( | const MCSubtargetInfo & | ST, |
int64_t | ByteOffset, | ||
bool | IsBuffer | ||
) |
ByteOffset
in the SMRD offset field, or std::nullopt if it won't fit. On GFX9 and GFX10 S_LOAD instructions have a signed offset, on other subtargets it is unsigned. S_BUFFER has an unsigned offset for all subtargets. Definition at line 2914 of file AMDGPUBaseInfo.cpp.
References assert(), convertSMRDOffsetUnits(), hasSMEMByteOffset(), hasSMRDSignedImmOffset(), isDwordAligned(), isGFX12Plus(), and isLegalSMRDEncodedUnsignedOffset().
LLVM_READONLY int llvm::AMDGPU::getSOPKOp | ( | uint16_t | Opcode | ) |
LLVM_READONLY int llvm::AMDGPU::getSOPPWithRelaxation | ( | uint16_t | Opcode | ) |
unsigned llvm::AMDGPU::getStorecntBitMask | ( | const IsaVersion & | Version | ) |
Version
. returns 0 for versions that do not support STOREcnt or VScnt. STOREcnt and VScnt are the same counter, the name used depends on the ISA version. Definition at line 1337 of file AMDGPUBaseInfo.cpp.
int llvm::AMDGPU::getTotalNumVGPRs | ( | bool | has90AInsts, |
int32_t | ArgNumAGPR, | ||
int32_t | ArgNumVGPR | ||
) |
Definition at line 2277 of file AMDGPUBaseInfo.cpp.
References llvm::alignTo().
Referenced by llvm::AMDGPUResourceUsageAnalysis::SIFunctionResourceInfo::getTotalNumVGPRs().
LLVM_READONLY int llvm::AMDGPU::getVCMPXNoSDstOp | ( | uint16_t | Opcode | ) |
LLVM_READONLY int llvm::AMDGPU::getVCMPXOpFromVCMP | ( | uint16_t | Opcode | ) |
unsigned llvm::AMDGPU::getVmcntBitMask | ( | const IsaVersion & | Version | ) |
Version
. Definition at line 1303 of file AMDGPUBaseInfo.cpp.
Referenced by llvm::AMDGPUInstPrinter::printSWaitCnt().
LLVM_READONLY bool llvm::AMDGPU::getVOP1IsSingle | ( | unsigned | Opc | ) |
Definition at line 482 of file AMDGPUBaseInfo.cpp.
References Info.
LLVM_READONLY bool llvm::AMDGPU::getVOP2IsSingle | ( | unsigned | Opc | ) |
Definition at line 487 of file AMDGPUBaseInfo.cpp.
References Info.
LLVM_READONLY bool llvm::AMDGPU::getVOP3IsSingle | ( | unsigned | Opc | ) |
Definition at line 492 of file AMDGPUBaseInfo.cpp.
References Info.
LLVM_READONLY std::pair< unsigned, unsigned > llvm::AMDGPU::getVOPDComponents | ( | unsigned | VOPDOpcode | ) |
Definition at line 633 of file AMDGPUBaseInfo.cpp.
References assert(), and Info.
Referenced by getVOPDInstInfo().
LLVM_READONLY unsigned llvm::AMDGPU::getVOPDEncodingFamily | ( | const MCSubtargetInfo & | ST | ) |
ST
. Definition at line 513 of file AMDGPUBaseInfo.cpp.
References llvm::SIEncodingFamily::GFX11, llvm::SIEncodingFamily::GFX12, and llvm_unreachable.
LLVM_READONLY int llvm::AMDGPU::getVOPDFull | ( | unsigned | OpX, |
unsigned | OpY, | ||
unsigned | EncodingFamily | ||
) |
Definition at line 627 of file AMDGPUBaseInfo.cpp.
References Info.
LLVM_READONLY VOPD::InstInfo llvm::AMDGPU::getVOPDInstInfo | ( | const MCInstrDesc & | OpX, |
const MCInstrDesc & | OpY | ||
) |
Definition at line 729 of file AMDGPUBaseInfo.cpp.
Referenced by llvm::checkVOPDRegConstraints().
LLVM_READONLY VOPD::InstInfo llvm::AMDGPU::getVOPDInstInfo | ( | unsigned | VOPDOpcode, |
const MCInstrInfo * | InstrInfo | ||
) |
Definition at line 733 of file AMDGPUBaseInfo.cpp.
References llvm::AMDGPU::VOPD::COMPONENT_X, llvm::MCInstrInfo::get(), and getVOPDComponents().
LLVM_READONLY unsigned llvm::AMDGPU::getVOPDOpcode | ( | unsigned | Opc | ) |
Definition at line 529 of file AMDGPUBaseInfo.cpp.
References Info.
LLVM_READONLY int llvm::AMDGPU::getVOPe32 | ( | uint16_t | Opcode | ) |
Referenced by llvm::SIInstrInfo::hasVALU32BitEncoding().
LLVM_READONLY int llvm::AMDGPU::getVOPe64 | ( | uint16_t | Opcode | ) |
Referenced by llvm::SITargetLowering::EmitInstrWithCustomInserter().
unsigned llvm::AMDGPU::getWaitcntBitMask | ( | const IsaVersion & | Version | ) |
Version
. Definition at line 1341 of file AMDGPUBaseInfo.cpp.
Referenced by encodeWaitcnt().
bool llvm::AMDGPU::hasA16 | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 2123 of file AMDGPUBaseInfo.cpp.
References llvm::MCSubtargetInfo::hasFeature().
bool llvm::AMDGPU::hasAny64BitVGPROperands | ( | const MCInstrDesc & | OpDesc | ) |
Definition at line 3004 of file AMDGPUBaseInfo.cpp.
References getNamedOperandIdx(), llvm::MCInstrDesc::getOpcode(), Idx, and llvm::MCInstrDesc::operands().
Referenced by isDPALU_DPP().
bool llvm::AMDGPU::hasArchitectedFlatScratch | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 2257 of file AMDGPUBaseInfo.cpp.
References llvm::MCSubtargetInfo::hasFeature().
Referenced by llvm::AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor().
bool llvm::AMDGPU::hasDPPSrc1SGPR | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 2269 of file AMDGPUBaseInfo.cpp.
References llvm::MCSubtargetInfo::hasFeature().
bool llvm::AMDGPU::hasG16 | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 2127 of file AMDGPUBaseInfo.cpp.
References llvm::MCSubtargetInfo::hasFeature().
Referenced by llvm::AMDGPUDisassembler::convertMIMGInst().
bool llvm::AMDGPU::hasGDS | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 2136 of file AMDGPUBaseInfo.cpp.
References llvm::MCSubtargetInfo::hasFeature().
Referenced by llvm::AMDGPUDisassembler::getInstruction().
bool llvm::AMDGPU::hasGFX10_3Insts | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 2241 of file AMDGPUBaseInfo.cpp.
References llvm::MCSubtargetInfo::hasFeature().
Referenced by llvm::AMDGPU::IsaInfo::getMaxWavesPerEU(), and llvm::AMDGPU::IsaInfo::getVGPRAllocGranule().
unsigned llvm::AMDGPU::hasKernargPreload | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 2273 of file AMDGPUBaseInfo.cpp.
References llvm::MCSubtargetInfo::hasFeature().
Referenced by llvm::AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor(), llvm::AMDGPUAsmPrinter::emitFunctionBodyStart(), and llvm::AMDGPUDisassembler::hasKernargPreload().
bool llvm::AMDGPU::hasMAIInsts | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 2261 of file AMDGPUBaseInfo.cpp.
References llvm::MCSubtargetInfo::hasFeature().
bool llvm::AMDGPU::hasMIMG_R128 | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 2119 of file AMDGPUBaseInfo.cpp.
References llvm::MCSubtargetInfo::hasFeature().
|
inline |
Definition at line 365 of file AMDGPUBaseInfo.h.
References getNamedOperandIdx().
Referenced by llvm::SIInstrInfo::areLoadsFromSameBasePtr(), llvm::SIInstrInfo::buildShrunkInst(), llvm::AMDGPUDisassembler::convertDPP8Inst(), llvm::AMDGPUDisassembler::convertSDWAInst(), llvm::SIInstrInfo::convertToThreeAddress(), llvm::AMDGPUDisassembler::convertVOP3DPPInst(), llvm::AMDGPUDisassembler::convertVOP3PDPPInst(), llvm::AMDGPUDisassembler::convertVOPCDPPInst(), cvtVOP3DstOpSelOnly(), llvm::SIRegisterInfo::eliminateFrameIndex(), getFlatScratchSpillOpcode(), llvm::SIInstrInfo::getRegClass(), llvm::SIInstrInfo::hasModifiers(), llvm::AMDGPUDisassembler::isMacDPP(), isVOPD(), llvm::SIInstrInfo::moveToVALUImpl(), and llvm::SITargetLowering::PostISelFolding().
bool llvm::AMDGPU::hasPackedD16 | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 2131 of file AMDGPUBaseInfo.cpp.
References llvm::MCSubtargetInfo::hasFeature(), isCI(), and isSI().
Referenced by llvm::AMDGPUDisassembler::convertMIMGInst().
|
static |
Definition at line 2873 of file AMDGPUBaseInfo.cpp.
References isGCN3Encoding(), and isGFX10Plus().
Referenced by convertSMRDOffsetUnits(), getSMRDEncodedOffset(), and isLegalSMRDEncodedUnsignedOffset().
|
static |
Definition at line 2877 of file AMDGPUBaseInfo.cpp.
References isGFX9Plus().
Referenced by getSMRDEncodedOffset(), and isLegalSMRDEncodedSignedOffset().
bool llvm::AMDGPU::hasSRAMECC | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 2115 of file AMDGPUBaseInfo.cpp.
References llvm::MCSubtargetInfo::hasFeature().
bool llvm::AMDGPU::hasVOPD | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 2265 of file AMDGPUBaseInfo.cpp.
References llvm::MCSubtargetInfo::hasFeature().
Referenced by llvm::AMDGPUDisassembler::decodeMandatoryLiteralConstant().
bool llvm::AMDGPU::hasXNACK | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 2111 of file AMDGPUBaseInfo.cpp.
References llvm::MCSubtargetInfo::hasFeature().
void llvm::AMDGPU::initDefaultAMDKernelCodeT | ( | amd_kernel_code_t & | Header, |
const MCSubtargetInfo * | STI | ||
) |
Definition at line 1188 of file AMDGPUBaseInfo.cpp.
References AMD_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32, llvm::MCSubtargetInfo::getCPU(), llvm::MCSubtargetInfo::getFeatureBits(), getIsaVersion(), S_00B848_MEM_ORDERED, S_00B848_WGP_MODE, and llvm::FeatureBitset::test().
bool llvm::AMDGPU::insertWaveSizeFeature | ( | StringRef | GPU, |
const Triple & | T, | ||
StringMap< bool > & | Features, | ||
std::string & | ErrorMsg | ||
) |
Inserts wave size feature for given GPU into features map.
Definition at line 569 of file TargetParser.cpp.
References llvm::StringMap< ValueTy, AllocatorTy >::count(), llvm::StringRef::empty(), llvm::StringMap< ValueTy, AllocatorTy >::insert(), and isWave32Capable().
Definition at line 2818 of file AMDGPUBaseInfo.cpp.
References A, llvm::CallingConv::AMDGPU_CS, llvm::CallingConv::AMDGPU_CS_Chain, llvm::CallingConv::AMDGPU_CS_ChainPreserve, llvm::CallingConv::AMDGPU_ES, llvm::CallingConv::AMDGPU_Gfx, llvm::CallingConv::AMDGPU_GS, llvm::CallingConv::AMDGPU_HS, llvm::CallingConv::AMDGPU_KERNEL, llvm::CallingConv::AMDGPU_LS, llvm::CallingConv::AMDGPU_PS, llvm::CallingConv::AMDGPU_VS, CC, F, and llvm::CallingConv::SPIR_KERNEL.
Referenced by adjustInliningThresholdUsingCallee(), llvm::GCNTTIImpl::isSourceOfDivergence(), and llvm::AMDGPUInstrInfo::isUniformMMO().
Definition at line 2847 of file AMDGPUBaseInfo.cpp.
References llvm::CallingConv::AMDGPU_CS, llvm::CallingConv::AMDGPU_CS_Chain, llvm::CallingConv::AMDGPU_CS_ChainPreserve, llvm::CallingConv::AMDGPU_ES, llvm::CallingConv::AMDGPU_Gfx, llvm::CallingConv::AMDGPU_GS, llvm::CallingConv::AMDGPU_HS, llvm::CallingConv::AMDGPU_KERNEL, llvm::CallingConv::AMDGPU_LS, llvm::CallingConv::AMDGPU_PS, llvm::CallingConv::AMDGPU_VS, CC, llvm::CallBase::getCallingConv(), llvm::CallBase::paramHasAttr(), and llvm::CallingConv::SPIR_KERNEL.
LLVM_READNONE bool llvm::AMDGPU::isChainCC | ( | CallingConv::ID | CC | ) |
Definition at line 2097 of file AMDGPUBaseInfo.cpp.
References llvm::CallingConv::AMDGPU_CS_Chain, llvm::CallingConv::AMDGPU_CS_ChainPreserve, and CC.
Referenced by getCallOpcode(), llvm::AMDGPUCallLowering::handleImplicitCallArguments(), llvm::SITargetLowering::isEligibleForTailCallOptimization(), isModuleEntryFunctionCC(), llvm::SITargetLowering::LowerCall(), llvm::AMDGPUCallLowering::lowerTailCall(), and llvm::SIMachineFunctionInfo::SIMachineFunctionInfo().
bool llvm::AMDGPU::isCI | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 2157 of file AMDGPUBaseInfo.cpp.
References llvm::MCSubtargetInfo::hasFeature().
Referenced by llvm::AMDGPU::MTBUFFormat::getNfmtLookupTable(), getSMRDEncodedLiteralOffset32(), hasPackedD16(), and isNotGFX10Plus().
bool llvm::AMDGPU::isClobberedInFunction | ( | const LoadInst * | Load, |
MemorySSA * | MSSA, | ||
AAResults * | AA | ||
) |
Check is a Load
is clobbered in its function.
Definition at line 109 of file AMDGPUMemoryUtils.cpp.
References llvm::dbgs(), llvm::MemoryLocation::get(), llvm::MemorySSAWalker::getClobberingMemoryAccess(), llvm::MemorySSA::getWalker(), llvm::SmallSet< T, N, C >::insert(), llvm::MemorySSA::isLiveOnEntryDef(), isReallyAClobber(), and LLVM_DEBUG.
LLVM_READNONE bool llvm::AMDGPU::isCompute | ( | CallingConv::ID | cc | ) |
Definition at line 2067 of file AMDGPUBaseInfo.cpp.
References llvm::CallingConv::AMDGPU_CS, and isGraphics().
Referenced by EmitPALMetadataCommon(), llvm::SIProgramInfo::getPGMRSrc1(), llvm::SIProgramInfo::getPGMRSrc2(), llvm::AMDGPULegalizerInfo::loadInputValue(), llvm::R600InstrInfo::usesTextureCache(), and llvm::R600InstrInfo::usesVertexCache().
LLVM_READNONE bool llvm::AMDGPU::isCvt_F32_Fp8_Bf8_e64 | ( | unsigned | Opc | ) |
Definition at line 572 of file AMDGPUBaseInfo.cpp.
bool llvm::AMDGPU::isDPALU_DPP | ( | const MCInstrDesc & | OpDesc | ) |
Definition at line 3019 of file AMDGPUBaseInfo.cpp.
References hasAny64BitVGPROperands().
Referenced by llvm::SIInstrInfo::verifyInstruction().
Definition at line 2901 of file AMDGPUBaseInfo.cpp.
Referenced by convertSMRDOffsetUnits(), getSMRDEncodedLiteralOffset32(), and getSMRDEncodedOffset().
bool llvm::AMDGPU::isDynamicLDS | ( | const GlobalVariable & | GV | ) |
Definition at line 34 of file AMDGPUMemoryUtils.cpp.
References DL, llvm::GlobalValue::getParent(), llvm::Type::getPointerAddressSpace(), llvm::GlobalValue::getType(), llvm::GlobalValue::getValueType(), llvm::GlobalValue::hasExternalLinkage(), and llvm::AMDGPUAS::LOCAL_ADDRESS.
Referenced by isLDSVariableToLower().
LLVM_READNONE bool llvm::AMDGPU::isEntryFunctionCC | ( | CallingConv::ID | CC | ) |
Definition at line 2071 of file AMDGPUBaseInfo.cpp.
References llvm::CallingConv::AMDGPU_CS, llvm::CallingConv::AMDGPU_ES, llvm::CallingConv::AMDGPU_GS, llvm::CallingConv::AMDGPU_HS, llvm::CallingConv::AMDGPU_KERNEL, llvm::CallingConv::AMDGPU_LS, llvm::CallingConv::AMDGPU_PS, llvm::CallingConv::AMDGPU_VS, CC, and llvm::CallingConv::SPIR_KERNEL.
Referenced by llvm::SITargetLowering::CanLowerReturn(), llvm::GCNUserSGPRUsageInfo::GCNUserSGPRUsageInfo(), INITIALIZE_PASS(), isModuleEntryFunctionCC(), llvm::AMDGPULegalizerInfo::loadInputValue(), llvm::AMDGPUCallLowering::lowerFormalArguments(), llvm::SITargetLowering::LowerFormalArguments(), llvm::SITargetLowering::mayBeEmittedAsTailCall(), mustPreserveGV(), recursivelyVisitUsers(), and llvm::SIMachineFunctionInfo::usesAGPRs().
Definition at line 422 of file AMDGPU.h.
References llvm::AMDGPUAS::CONSTANT_ADDRESS, llvm::AMDGPUAS::CONSTANT_ADDRESS_32BIT, llvm::AMDGPUAS::GLOBAL_ADDRESS, and llvm::AMDGPUAS::MAX_AMDGPU_ADDRESS.
Referenced by llvm::SITargetLowering::allowsMisalignedMemoryAccessesImpl(), and llvm::GCNTTIImpl::rewriteIntrinsicWithAddressSpace().
Definition at line 415 of file AMDGPU.h.
References llvm::AMDGPUAS::CONSTANT_ADDRESS, llvm::AMDGPUAS::FLAT_ADDRESS, llvm::AMDGPUAS::GLOBAL_ADDRESS, and llvm::AMDGPUAS::MAX_AMDGPU_ADDRESS.
Referenced by llvm::AMDGPURegisterBankInfo::applyMappingImpl(), llvm::AMDGPURegisterBankInfo::getInstrMappingForLoad(), llvm::AMDGPURegisterBankInfo::getValueMappingForPtr(), llvm::AMDGPUTargetMachine::isNoopAddrSpaceCast(), llvm::AMDGPULegalizerInfo::legalizeAtomicCmpXChg(), llvm::SITargetLowering::shouldExpandAtomicRMWInIR(), and llvm::GCNTTIImpl::shouldPrefetchAddressSpace().
bool llvm::AMDGPU::isGCN3Encoding | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 2229 of file AMDGPUBaseInfo.cpp.
References llvm::MCSubtargetInfo::hasFeature().
Referenced by hasSMEMByteOffset().
LLVM_READNONE bool llvm::AMDGPU::isGenericAtomic | ( | unsigned | Opc | ) |
Definition at line 583 of file AMDGPUBaseInfo.cpp.
Referenced by llvm::SIInstrInfo::getGenericInstructionUniformity().
bool llvm::AMDGPU::isGFX10 | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 2189 of file AMDGPUBaseInfo.cpp.
References llvm::MCSubtargetInfo::hasFeature().
Referenced by getGcnBufferFormatInfo(), getNumFlatOffsetBits(), llvm::AMDGPU::MTBUFFormat::getUnifiedFormatName(), llvm::AMDGPUDisassembler::isGFX10(), isGFX10_GFX11(), isGFX10Before1030(), isGFX10Plus(), isGFX8_GFX9_GFX10(), isGFX9_GFX10(), isGFX9_GFX10_GFX11(), and llvm::AMDGPU::MTBUFFormat::isValidUnifiedFormat().
bool llvm::AMDGPU::isGFX10_3_GFX11 | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 2245 of file AMDGPUBaseInfo.cpp.
References isGFX10_BEncoding(), and isGFX12Plus().
bool llvm::AMDGPU::isGFX10_AEncoding | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 2233 of file AMDGPUBaseInfo.cpp.
References llvm::MCSubtargetInfo::hasFeature().
bool llvm::AMDGPU::isGFX10_BEncoding | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 2237 of file AMDGPUBaseInfo.cpp.
References llvm::MCSubtargetInfo::hasFeature().
Referenced by isGFX10_3_GFX11(), and isGFX10Before1030().
bool llvm::AMDGPU::isGFX10_GFX11 | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 2193 of file AMDGPUBaseInfo.cpp.
bool llvm::AMDGPU::isGFX10Before1030 | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 2225 of file AMDGPUBaseInfo.cpp.
References isGFX10(), and isGFX10_BEncoding().
bool llvm::AMDGPU::isGFX10Plus | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 2197 of file AMDGPUBaseInfo.cpp.
References isGFX10(), and isGFX11Plus().
Referenced by llvm::AMDGPUAsmPrinter::doFinalization(), generateEndPgm(), llvm::AMDGPU::MTBUFFormat::getDefaultFormatEncoding(), llvm::AMDGPU::IsaInfo::getEUsPerCU(), llvm::AMDGPU::IsaInfo::getLocalMemorySize(), llvm::AMDGPU::IsaInfo::getMaxWavesPerEU(), llvm::AMDGPU::IsaInfo::getMaxWorkGroupsPerCU(), llvm::AMDGPU::IsaInfo::getTotalNumVGPRs(), hasSMEMByteOffset(), llvm::GCNSubtarget::initializeSubtargetDependencies(), llvm::AMDGPUDisassembler::isGFX10Plus(), isGFX9Plus(), llvm::AMDGPU::Exp::isSupportedTgtId(), and llvm::AMDGPU::MTBUFFormat::isValidFormatEncoding().
bool llvm::AMDGPU::isGFX11 | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 2201 of file AMDGPUBaseInfo.cpp.
References llvm::MCSubtargetInfo::hasFeature().
Referenced by isGFX10_GFX11(), isGFX11Plus(), isGFX9_GFX10_GFX11(), and llvm::AMDGPULegalizerInfo::legalizeBVHIntrinsic().
bool llvm::AMDGPU::isGFX11Plus | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 2205 of file AMDGPUBaseInfo.cpp.
References isGFX11(), and isGFX12Plus().
Referenced by llvm::AMDGPU::MTBUFFormat::convertDfmtNfmt2Ufmt(), llvm::AMDGPU::SendMsg::decodeMsg(), llvm::AMDGPUTargetAsmStreamer::EmitCodeEnd(), llvm::AMDGPUTargetELFStreamer::EmitCodeEnd(), getGcnBufferFormatInfo(), llvm::AMDGPU::SendMsg::getMsgIdMask(), llvm::AMDGPU::MTBUFFormat::getUnifiedFormat(), imageIntrinsicOptimizerImpl(), isGFX10Plus(), llvm::AMDGPUDisassembler::isGFX11Plus(), isNotGFX11Plus(), llvm::AMDGPU::Exp::isSupportedTgtId(), llvm::AMDGPU::SendMsg::isValidMsgOp(), llvm::AMDGPU::SendMsg::isValidMsgStream(), llvm::AMDGPULegalizerInfo::legalizeBVHIntrinsic(), llvm::AMDGPU::SendMsg::msgRequiresOp(), and llvm::AMDGPU::SendMsg::msgSupportsStream().
bool llvm::AMDGPU::isGFX12 | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 2209 of file AMDGPUBaseInfo.cpp.
References llvm::MCSubtargetInfo::getFeatureBits().
Referenced by getNumFlatOffsetBits(), and isGFX12Plus().
bool llvm::AMDGPU::isGFX12Plus | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 2213 of file AMDGPUBaseInfo.cpp.
References isGFX12().
Referenced by llvm::SIInstrInfo::allowNegativeFlatOffset(), getSMRDEncodedOffset(), isGFX10_3_GFX11(), isGFX11Plus(), llvm::AMDGPUDisassembler::isGFX12Plus(), isLegalSMRDEncodedSignedOffset(), isLegalSMRDEncodedUnsignedOffset(), isNotGFX12Plus(), and llvm::AMDGPULegalizerInfo::legalizeBVHIntrinsic().
bool llvm::AMDGPU::isGFX8_GFX9_GFX10 | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 2177 of file AMDGPUBaseInfo.cpp.
bool llvm::AMDGPU::isGFX8Plus | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 2181 of file AMDGPUBaseInfo.cpp.
References isGFX9Plus(), and isVI().
bool llvm::AMDGPU::isGFX9 | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 2165 of file AMDGPUBaseInfo.cpp.
References llvm::MCSubtargetInfo::hasFeature().
Referenced by llvm::AMDGPU::MTBUFFormat::getNfmtLookupTable(), isGFX8_GFX9_GFX10(), llvm::AMDGPUDisassembler::isGFX9(), isGFX9_GFX10(), isGFX9_GFX10_GFX11(), isGFX9Plus(), and isNotGFX10Plus().
bool llvm::AMDGPU::isGFX90A | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 2249 of file AMDGPUBaseInfo.cpp.
References llvm::MCSubtargetInfo::hasFeature().
Referenced by llvm::AMDGPUAsmPrinter::doFinalization(), llvm::AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor(), llvm::AMDGPUTargetAsmStreamer::EmitCodeEnd(), llvm::AMDGPUTargetELFStreamer::EmitCodeEnd(), llvm::AMDGPU::MCKernelDescriptor::getDefaultAmdhsaKernelDescriptor(), and llvm::AMDGPU::IsaInfo::getMaxWavesPerEU().
bool llvm::AMDGPU::isGFX940 | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 2253 of file AMDGPUBaseInfo.cpp.
References llvm::MCSubtargetInfo::hasFeature().
bool llvm::AMDGPU::isGFX9_GFX10 | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 2169 of file AMDGPUBaseInfo.cpp.
bool llvm::AMDGPU::isGFX9_GFX10_GFX11 | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 2173 of file AMDGPUBaseInfo.cpp.
bool llvm::AMDGPU::isGFX9Plus | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 2185 of file AMDGPUBaseInfo.cpp.
References isGFX10Plus(), and isGFX9().
Referenced by hasSMRDSignedImmOffset(), isGFX8Plus(), and llvm::AMDGPUDisassembler::isGFX9Plus().
bool llvm::AMDGPU::isGlobalSegment | ( | const GlobalValue * | GV | ) |
Definition at line 1228 of file AMDGPUBaseInfo.cpp.
References llvm::GlobalValue::getAddressSpace(), and llvm::AMDGPUAS::GLOBAL_ADDRESS.
LLVM_READNONE bool llvm::AMDGPU::isGraphics | ( | CallingConv::ID | cc | ) |
Definition at line 2063 of file AMDGPUBaseInfo.cpp.
References llvm::CallingConv::AMDGPU_Gfx, and isShader().
Referenced by llvm::GCNUserSGPRUsageInfo::GCNUserSGPRUsageInfo(), isCompute(), llvm::SIInstrInfo::legalizeOperands(), llvm::AMDGPUCallLowering::lowerFormalArguments(), llvm::SITargetLowering::LowerFormalArguments(), and llvm::SIMachineFunctionInfo::SIMachineFunctionInfo().
bool llvm::AMDGPU::isGroupSegment | ( | const GlobalValue * | GV | ) |
Definition at line 1224 of file AMDGPUBaseInfo.cpp.
References llvm::GlobalValue::getAddressSpace(), and llvm::AMDGPUAS::LOCAL_ADDRESS.
bool llvm::AMDGPU::isHi | ( | unsigned | Reg, |
const MCRegisterInfo & | MRI | ||
) |
Reg
occupies the high 16-bits of a 32-bit register. The bit indicating isHi is the LSB of the encoding. Definition at line 2291 of file AMDGPUBaseInfo.cpp.
References llvm::AMDGPU::HWEncoding::IS_HI, MRI, and Reg.
Referenced by llvm::SIInstrInfo::copyPhysReg(), cvtVOP3DstOpSelOnly(), and llvm::SIRegisterInfo::SIRegisterInfo().
bool llvm::AMDGPU::isHsaAbi | ( | const MCSubtargetInfo & | STI | ) |
STI
is AMDHSA. Definition at line 162 of file AMDGPUBaseInfo.cpp.
References llvm::Triple::AMDHSA, llvm::Triple::getOS(), and llvm::MCSubtargetInfo::getTargetTriple().
|
inline |
Is this literal inlinable, and not one of the values intended for floating point values.
Definition at line 1406 of file AMDGPUBaseInfo.h.
References llvm::Literal.
Referenced by llvm::SITargetLowering::checkAsmConstraintVal(), clearUnusedBits(), isInlinableLiteral32(), isInlinableLiteral64(), isInlinableLiteralBF16(), isInlinableLiteralFP16(), llvm::SIInstrInfo::isInlineConstant(), and llvm::AMDGPUAsmPrinter::PrintAsmOperand().
LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteral32 | ( | int32_t | Literal, |
bool | HasInv2Pi | ||
) |
Definition at line 2619 of file AMDGPUBaseInfo.cpp.
References isInlinableIntLiteral(), and llvm::Literal.
Referenced by llvm::SITargetLowering::checkAsmConstraintValA(), llvm::SIRegisterInfo::eliminateFrameIndex(), isInlinableLiteralI16(), isInlineableLiteralOp16(), and llvm::SIInstrInfo::isInlineConstant().
LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteral64 | ( | int64_t | Literal, |
bool | HasInv2Pi | ||
) |
Is this literal inlinable.
Definition at line 2602 of file AMDGPUBaseInfo.cpp.
References isInlinableIntLiteral(), and llvm::Literal.
Referenced by llvm::SITargetLowering::checkAsmConstraintValA(), llvm::SIInstrInfo::isInlineConstant(), and llvm::SIInstrInfo::isOperandLegal().
LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteralBF16 | ( | int16_t | Literal, |
bool | HasInv2Pi | ||
) |
Definition at line 2645 of file AMDGPUBaseInfo.cpp.
References isInlinableIntLiteral(), and llvm::Literal.
Referenced by llvm::SITargetLowering::checkAsmConstraintValA(), isInlineableLiteralOp16(), and llvm::SIInstrInfo::isInlineConstant().
LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteralFP16 | ( | int16_t | Literal, |
bool | HasInv2Pi | ||
) |
Definition at line 2666 of file AMDGPUBaseInfo.cpp.
References isInlinableIntLiteral(), and llvm::Literal.
Referenced by llvm::SITargetLowering::checkAsmConstraintValA(), isInlineableLiteralOp16(), and llvm::SIInstrInfo::isInlineConstant().
LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteralI16 | ( | int32_t | Literal, |
bool | HasInv2Pi | ||
) |
Definition at line 2662 of file AMDGPUBaseInfo.cpp.
References isInlinableLiteral32(), and llvm::Literal.
Referenced by llvm::SITargetLowering::checkAsmConstraintValA(), and llvm::SIInstrInfo::isInlineConstant().
LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteralV216 | ( | uint32_t | Literal, |
uint8_t | OpType | ||
) |
Definition at line 2777 of file AMDGPUBaseInfo.cpp.
References getInlineEncodingV216(), isInlinableLiteralV2BF16(), llvm::Literal, llvm_unreachable, OPERAND_REG_IMM_V2BF16, OPERAND_REG_IMM_V2FP16, OPERAND_REG_IMM_V2INT16, OPERAND_REG_INLINE_AC_V2BF16, OPERAND_REG_INLINE_AC_V2FP16, OPERAND_REG_INLINE_AC_V2INT16, OPERAND_REG_INLINE_C_V2BF16, OPERAND_REG_INLINE_C_V2FP16, and OPERAND_REG_INLINE_C_V2INT16.
LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteralV2BF16 | ( | uint32_t | Literal | ) |
Definition at line 2802 of file AMDGPUBaseInfo.cpp.
References getInlineEncodingV2BF16(), and llvm::Literal.
Referenced by isInlinableLiteralV216(), and llvm::SIInstrInfo::isInlineConstant().
LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteralV2F16 | ( | uint32_t | Literal | ) |
Definition at line 2807 of file AMDGPUBaseInfo.cpp.
References getInlineEncodingV2F16(), and llvm::Literal.
Referenced by llvm::SIInstrInfo::isInlineConstant().
LLVM_READNONE bool llvm::AMDGPU::isInlinableLiteralV2I16 | ( | uint32_t | Literal | ) |
Definition at line 2797 of file AMDGPUBaseInfo.cpp.
References getInlineEncodingV2I16(), and llvm::Literal.
Referenced by llvm::SIInstrInfo::isInlineConstant().
LLVM_READNONE bool llvm::AMDGPU::isInlineValue | ( | unsigned | Reg | ) |
Definition at line 2372 of file AMDGPUBaseInfo.cpp.
References Reg.
Definition at line 2980 of file AMDGPUBaseInfo.cpp.
Referenced by llvm::SIInstrInfo::getGenericInstructionUniformity(), llvm::GCNTTIImpl::isAlwaysUniform(), and llvm::AMDGPUTargetLowering::isSDNodeAlwaysUniform().
Definition at line 2976 of file AMDGPUBaseInfo.cpp.
Referenced by llvm::SIInstrInfo::getGenericInstructionUniformity(), llvm::SITargetLowering::isSDNodeSourceOfDivergence(), and llvm::GCNTTIImpl::isSourceOfDivergence().
|
inline |
Definition at line 1250 of file AMDGPUBaseInfo.h.
References llvm::CallingConv::AMDGPU_KERNEL, CC, and llvm::CallingConv::SPIR_KERNEL.
Referenced by llvm::AMDGPUSubtarget::getImplicitArgNumBytes(), llvm::AMDGPULegalizerInfo::legalizeIntrinsic(), llvm::SITargetLowering::LowerFormalArguments(), llvm::AMDGPUCallLowering::lowerReturn(), and llvm::SITargetLowering::LowerReturn().
Definition at line 2107 of file AMDGPUBaseInfo.cpp.
References isModuleEntryFunctionCC().
bool llvm::AMDGPU::isKImmOperand | ( | const MCInstrDesc & | Desc, |
unsigned | OpNo | ||
) |
Is this a KImm operand?
Definition at line 2408 of file AMDGPUBaseInfo.cpp.
References assert(), OPERAND_KIMM_FIRST, and OPERAND_KIMM_LAST.
bool llvm::AMDGPU::isLDSVariableToLower | ( | const GlobalVariable & | GV | ) |
|
inline |
Definition at line 1496 of file AMDGPUBaseInfo.h.
References llvm::AMDGPU::DPP::ROW_NEWBCAST_FIRST, and llvm::AMDGPU::DPP::ROW_NEWBCAST_LAST.
Referenced by llvm::SIInstrInfo::expandMovDPP64(), and llvm::SIInstrInfo::verifyInstruction().
LLVM_READONLY bool llvm::AMDGPU::isLegalSMRDEncodedSignedOffset | ( | const MCSubtargetInfo & | ST, |
int64_t | EncodedOffset, | ||
bool | IsBuffer | ||
) |
Definition at line 2890 of file AMDGPUBaseInfo.cpp.
References hasSMRDSignedImmOffset(), and isGFX12Plus().
LLVM_READONLY bool llvm::AMDGPU::isLegalSMRDEncodedUnsignedOffset | ( | const MCSubtargetInfo & | ST, |
int64_t | EncodedOffset | ||
) |
Definition at line 2881 of file AMDGPUBaseInfo.cpp.
References hasSMEMByteOffset(), and isGFX12Plus().
Referenced by getSMRDEncodedOffset().
bool llvm::AMDGPU::isLegalSMRDImmOffset | ( | const MCSubtargetInfo & | ST, |
int64_t | ByteOffset | ||
) |
ByteOffset
should be the offset in bytes and not the encoded offset. LLVM_READNONE bool llvm::AMDGPU::isMAC | ( | unsigned | Opc | ) |
Definition at line 538 of file AMDGPUBaseInfo.cpp.
Referenced by llvm::AMDGPUDisassembler::getInstruction().
LLVM_READNONE bool llvm::AMDGPU::isModuleEntryFunctionCC | ( | CallingConv::ID | CC | ) |
Definition at line 2088 of file AMDGPUBaseInfo.cpp.
References llvm::CallingConv::AMDGPU_Gfx, CC, isChainCC(), and isEntryFunctionCC().
Referenced by isKernelCC().
bool llvm::AMDGPU::isNotGFX10Plus | ( | const MCSubtargetInfo & | STI | ) |
bool llvm::AMDGPU::isNotGFX11Plus | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 2217 of file AMDGPUBaseInfo.cpp.
References isGFX11Plus().
bool llvm::AMDGPU::isNotGFX12Plus | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 2215 of file AMDGPUBaseInfo.cpp.
References isGFX12Plus().
LLVM_READNONE bool llvm::AMDGPU::isPermlane16 | ( | unsigned | Opc | ) |
Definition at line 561 of file AMDGPUBaseInfo.cpp.
bool llvm::AMDGPU::isReadOnlySegment | ( | const GlobalValue * | GV | ) |
Definition at line 1232 of file AMDGPUBaseInfo.cpp.
References llvm::AMDGPUAS::CONSTANT_ADDRESS, llvm::AMDGPUAS::CONSTANT_ADDRESS_32BIT, and llvm::GlobalValue::getAddressSpace().
Referenced by llvm::AMDGPUTargetObjectFile::SelectSectionForGlobal().
Given a Def
clobbering a load from Ptr
according to the MSSA check if this is actually a memory update or an artificial clobber to facilitate ordering constraints.
Definition at line 68 of file AMDGPUMemoryUtils.cpp.
References I, llvm::AAResults::isNoAlias(), and Ptr.
Referenced by isClobberedInFunction().
bool llvm::AMDGPU::isSGPR | ( | unsigned | Reg, |
const MCRegisterInfo * | TRI | ||
) |
Is Reg - scalar register.
Definition at line 2284 of file AMDGPUBaseInfo.cpp.
References llvm::MCRegisterClass::contains(), Reg, and TRI.
LLVM_READNONE bool llvm::AMDGPU::isShader | ( | CallingConv::ID | cc | ) |
Definition at line 2046 of file AMDGPUBaseInfo.cpp.
References llvm::CallingConv::AMDGPU_CS, llvm::CallingConv::AMDGPU_CS_Chain, llvm::CallingConv::AMDGPU_CS_ChainPreserve, llvm::CallingConv::AMDGPU_ES, llvm::CallingConv::AMDGPU_GS, llvm::CallingConv::AMDGPU_HS, llvm::CallingConv::AMDGPU_LS, llvm::CallingConv::AMDGPU_PS, and llvm::CallingConv::AMDGPU_VS.
Referenced by llvm::SIModeRegisterDefaults::getDefaultForCallingConv(), isGraphics(), llvm::GCNSubtarget::isMesaGfxShader(), llvm::AMDGPUSubtarget::isMesaKernel(), llvm::R600TargetLowering::LowerFormalArguments(), llvm::AMDGPUCallLowering::lowerReturn(), llvm::SITargetLowering::LowerReturn(), and reservePrivateMemoryRegs().
bool llvm::AMDGPU::isSI | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 2153 of file AMDGPUBaseInfo.cpp.
References llvm::MCSubtargetInfo::hasFeature().
Referenced by llvm::AMDGPU::MTBUFFormat::getNfmtLookupTable(), hasPackedD16(), and isNotGFX10Plus().
bool llvm::AMDGPU::isSISrcFPOperand | ( | const MCInstrDesc & | Desc, |
unsigned | OpNo | ||
) |
Is this floating-point operand?
Definition at line 2415 of file AMDGPUBaseInfo.cpp.
References assert(), OPERAND_REG_IMM_FP16, OPERAND_REG_IMM_FP16_DEFERRED, OPERAND_REG_IMM_FP32, OPERAND_REG_IMM_FP32_DEFERRED, OPERAND_REG_IMM_FP64, OPERAND_REG_IMM_V2FP16, OPERAND_REG_IMM_V2FP32, OPERAND_REG_INLINE_AC_FP16, OPERAND_REG_INLINE_AC_FP32, OPERAND_REG_INLINE_AC_FP64, OPERAND_REG_INLINE_AC_V2FP16, OPERAND_REG_INLINE_C_FP16, OPERAND_REG_INLINE_C_FP32, OPERAND_REG_INLINE_C_FP64, OPERAND_REG_INLINE_C_V2FP16, and OPERAND_REG_INLINE_C_V2FP32.
bool llvm::AMDGPU::isSISrcInlinableOperand | ( | const MCInstrDesc & | Desc, |
unsigned | OpNo | ||
) |
Does this operand support only inlinable literals?
Definition at line 2441 of file AMDGPUBaseInfo.cpp.
References assert(), OPERAND_REG_INLINE_AC_FIRST, OPERAND_REG_INLINE_AC_LAST, OPERAND_REG_INLINE_C_FIRST, and OPERAND_REG_INLINE_C_LAST.
bool llvm::AMDGPU::isSISrcOperand | ( | const MCInstrDesc & | Desc, |
unsigned | OpNo | ||
) |
Is this an AMDGPU specific source operand? These include registers, inline constants, literals and mandatory literals (KImm).
Definition at line 2401 of file AMDGPUBaseInfo.cpp.
References assert(), OPERAND_SRC_FIRST, and OPERAND_SRC_LAST.
Referenced by llvm::SIInstrInfo::isImmOperandLegal(), and llvm::SIInstrInfo::isOperandLegal().
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static |
Definition at line 1570 of file AMDGPUBaseInfo.cpp.
Referenced by llvm::AMDGPU::DepCtr::isSymbolicDepCtrEncoding().
LLVM_READONLY bool llvm::AMDGPU::isTrue16Inst | ( | unsigned | Opc | ) |
Definition at line 605 of file AMDGPUBaseInfo.cpp.
References Info.
Referenced by llvm::SIInstrInfo::moveToVALUImpl().
LLVM_READNONE bool llvm::AMDGPU::isValid32BitLiteral | ( | uint64_t | Val, |
bool | IsFP64 | ||
) |
Definition at line 2811 of file AMDGPUBaseInfo.cpp.
Referenced by llvm::SIInstrInfo::isOperandLegal(), and AMDGPUDAGToDAGISel::Select().
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static |
Definition at line 1510 of file AMDGPUBaseInfo.cpp.
References llvm::AMDGPU::CustomOperand< T >::Cond, Context, llvm::StringRef::empty(), Idx, and llvm::AMDGPU::CustomOperand< T >::Name.
bool llvm::AMDGPU::isVI | ( | const MCSubtargetInfo & | STI | ) |
Definition at line 2161 of file AMDGPUBaseInfo.cpp.
References llvm::MCSubtargetInfo::hasFeature().
Referenced by llvm::AMDGPU::MTBUFFormat::getNfmtLookupTable(), isGFX8_GFX9_GFX10(), isGFX8Plus(), and isNotGFX10Plus().
LLVM_READONLY bool llvm::AMDGPU::isVOPC64DPP | ( | unsigned | Opc | ) |
Definition at line 497 of file AMDGPUBaseInfo.cpp.
Referenced by llvm::AMDGPUDisassembler::getInstruction().
LLVM_READONLY bool llvm::AMDGPU::isVOPCAsmOnly | ( | unsigned | Opc | ) |
Definition at line 501 of file AMDGPUBaseInfo.cpp.
LLVM_READONLY bool llvm::AMDGPU::isVOPD | ( | unsigned | Opc | ) |
Definition at line 534 of file AMDGPUBaseInfo.cpp.
References hasNamedOperand().
Referenced by getSrcOperandIndices().
const D16ImageDimIntrinsic * llvm::AMDGPU::lookupD16ImageDimIntrinsic | ( | unsigned | Intr | ) |
const RsrcIntrinsic * llvm::AMDGPU::lookupRsrcIntrinsic | ( | unsigned | Intr | ) |
LLVM_READONLY unsigned llvm::AMDGPU::mapWMMA2AddrTo3AddrOpcode | ( | unsigned | Opc | ) |
Definition at line 610 of file AMDGPUBaseInfo.cpp.
References Info.
Referenced by llvm::SIInstrInfo::convertToThreeAddress().
LLVM_READONLY unsigned llvm::AMDGPU::mapWMMA3AddrTo2AddrOpcode | ( | unsigned | Opc | ) |
Definition at line 615 of file AMDGPUBaseInfo.cpp.
References Info.
LLVM_READNONE unsigned llvm::AMDGPU::mc2PseudoReg | ( | unsigned | Reg | ) |
Convert hardware register Reg
to a pseudo register.
Definition at line 2368 of file AMDGPUBaseInfo.cpp.
References MAP_REG2REG.
Referenced by checkWriteLane().
AMDGPU::GPUKind llvm::AMDGPU::parseArchAMDGCN | ( | StringRef | CPU | ) |
Definition at line 180 of file TargetParser.cpp.
References llvm::CallingConv::C.
Referenced by fillAMDGPUFeatureMap(), getCanonicalArchName(), llvm::AMDGPUTargetStreamer::getElfMach(), getIsaVersion(), and isWave32Capable().
AMDGPU::GPUKind llvm::AMDGPU::parseArchR600 | ( | StringRef | CPU | ) |
Definition at line 189 of file TargetParser.cpp.
References llvm::CallingConv::C.
Referenced by fillAMDGPUFeatureMap(), getCanonicalArchName(), and llvm::AMDGPUTargetStreamer::getElfMach().
TT
, false otherwise. Definition at line 1238 of file AMDGPUBaseInfo.cpp.
References llvm::Triple::r600.
Referenced by llvm::AMDGPUTargetObjectFile::SelectSectionForGlobal(), and llvm::SITargetLowering::shouldEmitFixup().
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staticconstexpr |
Offset of nonstandard values for llvm.get.rounding results from the largest supported mode.
Definition at line 135 of file SIModeRegisterDefaults.h.
Referenced by decodeIndexFltRoundConversionTable(), and encodeFltRoundsTable().
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staticconstexpr |
Offset in mode register of f32 rounding mode.
Definition at line 138 of file SIModeRegisterDefaults.h.
Referenced by getModeRegisterRoundMode().
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staticconstexpr |
Offset in mode register of f64/f16 rounding mode.
Definition at line 141 of file SIModeRegisterDefaults.h.
Referenced by getModeRegisterRoundMode().
Definition at line 86 of file SIModeRegisterDefaults.cpp.
Referenced by decodeIndexFltRoundConversionTable(), and llvm::SITargetLowering::lowerGET_ROUNDING().
const int llvm::AMDGPU::OPR_ID_DUPLICATE = -3 |
Definition at line 25 of file AMDGPUAsmUtils.h.
Referenced by encodeCustomOperand().
const int llvm::AMDGPU::OPR_ID_UNKNOWN = -1 |
Definition at line 23 of file AMDGPUAsmUtils.h.
Referenced by encodeCustomOperand(), and getOprIdx().
const int llvm::AMDGPU::OPR_ID_UNSUPPORTED = -2 |
Definition at line 24 of file AMDGPUAsmUtils.h.
Referenced by encodeCustomOperand(), and getOprIdx().
const int llvm::AMDGPU::OPR_VAL_INVALID = -4 |
Definition at line 26 of file AMDGPUAsmUtils.h.
Referenced by encodeCustomOperandVal().
Definition at line 1504 of file SIInstrInfo.h.
Referenced by llvm::SIInstrInfo::getDefaultRsrcDataFormat().
Definition at line 1505 of file SIInstrInfo.h.
Referenced by llvm::SIInstrInfo::getScratchRsrcWords23().
Definition at line 1506 of file SIInstrInfo.h.
Referenced by llvm::SIInstrInfo::getScratchRsrcWords23().
Definition at line 1507 of file SIInstrInfo.h.
Referenced by llvm::SIInstrInfo::getScratchRsrcWords23().