LLVM  6.0.0svn
Namespaces | Enumerations | Functions
AArch64AddressingModes.h File Reference
#include "llvm/ADT/APFloat.h"
#include "llvm/ADT/APInt.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include <cassert>
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Namespaces

 llvm
 Compute iterated dominance frontiers using a linear time algorithm.
 
 llvm::AArch64_AM
 AArch64_AM - AArch64 Addressing Mode Stuff.
 

Enumerations

enum  llvm::AArch64_AM::ShiftExtendType {
  llvm::AArch64_AM::InvalidShiftExtend = -1, llvm::AArch64_AM::LSL = 0, llvm::AArch64_AM::LSR, llvm::AArch64_AM::ASR,
  llvm::AArch64_AM::ROR, llvm::AArch64_AM::MSL, llvm::AArch64_AM::UXTB, llvm::AArch64_AM::UXTH,
  llvm::AArch64_AM::UXTW, llvm::AArch64_AM::UXTX, llvm::AArch64_AM::SXTB, llvm::AArch64_AM::SXTH,
  llvm::AArch64_AM::SXTW, llvm::AArch64_AM::SXTX
}
 

Functions

static const charllvm::AArch64_AM::getShiftExtendName (AArch64_AM::ShiftExtendType ST)
 getShiftName - Get the string encoding for the shift type. More...
 
static AArch64_AM::ShiftExtendType llvm::AArch64_AM::getShiftType (unsigned Imm)
 getShiftType - Extract the shift type. More...
 
static unsigned llvm::AArch64_AM::getShiftValue (unsigned Imm)
 getShiftValue - Extract the shift value. More...
 
static unsigned llvm::AArch64_AM::getShifterImm (AArch64_AM::ShiftExtendType ST, unsigned Imm)
 getShifterImm - Encode the shift type and amount: imm: 6-bit shift amount shifter: 000 ==> lsl 001 ==> lsr 010 ==> asr 011 ==> ror 100 ==> msl {8-6} = shifter {5-0} = imm More...
 
static unsigned llvm::AArch64_AM::getArithShiftValue (unsigned Imm)
 getArithShiftValue - get the arithmetic shift value. More...
 
static AArch64_AM::ShiftExtendType llvm::AArch64_AM::getExtendType (unsigned Imm)
 getExtendType - Extract the extend type for operands of arithmetic ops. More...
 
static AArch64_AM::ShiftExtendType llvm::AArch64_AM::getArithExtendType (unsigned Imm)
 
unsigned llvm::AArch64_AM::getExtendEncoding (AArch64_AM::ShiftExtendType ET)
 Mapping from extend bits to required operation: shifter: 000 ==> uxtb 001 ==> uxth 010 ==> uxtw 011 ==> uxtx 100 ==> sxtb 101 ==> sxth 110 ==> sxtw 111 ==> sxtx. More...
 
static unsigned llvm::AArch64_AM::getArithExtendImm (AArch64_AM::ShiftExtendType ET, unsigned Imm)
 getArithExtendImm - Encode the extend type and shift amount for an arithmetic instruction: imm: 3-bit extend amount {5-3} = shifter {2-0} = imm3 More...
 
static bool llvm::AArch64_AM::getMemDoShift (unsigned Imm)
 getMemDoShift - Extract the "do shift" flag value for load/store instructions. More...
 
static AArch64_AM::ShiftExtendType llvm::AArch64_AM::getMemExtendType (unsigned Imm)
 getExtendType - Extract the extend type for the offset operand of loads/stores. More...
 
static unsigned llvm::AArch64_AM::getMemExtendImm (AArch64_AM::ShiftExtendType ET, bool DoShift)
 getExtendImm - Encode the extend type and amount for a load/store inst: doshift: should the offset be scaled by the access size shifter: 000 ==> uxtb 001 ==> uxth 010 ==> uxtw 011 ==> uxtx 100 ==> sxtb 101 ==> sxth 110 ==> sxtw 111 ==> sxtx {3-1} = shifter {0} = doshift More...
 
static uint64_t llvm::AArch64_AM::ror (uint64_t elt, unsigned size)
 
static bool llvm::AArch64_AM::processLogicalImmediate (uint64_t Imm, unsigned RegSize, uint64_t &Encoding)
 processLogicalImmediate - Determine if an immediate value can be encoded as the immediate operand of a logical instruction for the given register size. More...
 
static bool llvm::AArch64_AM::isLogicalImmediate (uint64_t imm, unsigned regSize)
 isLogicalImmediate - Return true if the immediate is valid for a logical immediate instruction of the given register size. More...
 
static uint64_t llvm::AArch64_AM::encodeLogicalImmediate (uint64_t imm, unsigned regSize)
 encodeLogicalImmediate - Return the encoded immediate value for a logical immediate instruction of the given register size. More...
 
static uint64_t llvm::AArch64_AM::decodeLogicalImmediate (uint64_t val, unsigned regSize)
 decodeLogicalImmediate - Decode a logical immediate value in the form "N:immr:imms" (where the immr and imms fields are each 6 bits) into the integer value it represents with regSize bits. More...
 
static bool llvm::AArch64_AM::isValidDecodeLogicalImmediate (uint64_t val, unsigned regSize)
 isValidDecodeLogicalImmediate - Check to see if the logical immediate value in the form "N:immr:imms" (where the immr and imms fields are each 6 bits) is a valid encoding for an integer value with regSize bits. More...
 
static float llvm::AArch64_AM::getFPImmFloat (unsigned Imm)
 
static int llvm::AArch64_AM::getFP16Imm (const APInt &Imm)
 getFP16Imm - Return an 8-bit floating-point version of the 16-bit floating-point value. More...
 
static int llvm::AArch64_AM::getFP16Imm (const APFloat &FPImm)
 
static int llvm::AArch64_AM::getFP32Imm (const APInt &Imm)
 getFP32Imm - Return an 8-bit floating-point version of the 32-bit floating-point value. More...
 
static int llvm::AArch64_AM::getFP32Imm (const APFloat &FPImm)
 
static int llvm::AArch64_AM::getFP64Imm (const APInt &Imm)
 getFP64Imm - Return an 8-bit floating-point version of the 64-bit floating-point value. More...
 
static int llvm::AArch64_AM::getFP64Imm (const APFloat &FPImm)
 
static bool llvm::AArch64_AM::isAdvSIMDModImmType1 (uint64_t Imm)
 
static uint8_t llvm::AArch64_AM::encodeAdvSIMDModImmType1 (uint64_t Imm)
 
static uint64_t llvm::AArch64_AM::decodeAdvSIMDModImmType1 (uint8_t Imm)
 
static bool llvm::AArch64_AM::isAdvSIMDModImmType2 (uint64_t Imm)
 
static uint8_t llvm::AArch64_AM::encodeAdvSIMDModImmType2 (uint64_t Imm)
 
static uint64_t llvm::AArch64_AM::decodeAdvSIMDModImmType2 (uint8_t Imm)
 
static bool llvm::AArch64_AM::isAdvSIMDModImmType3 (uint64_t Imm)
 
static uint8_t llvm::AArch64_AM::encodeAdvSIMDModImmType3 (uint64_t Imm)
 
static uint64_t llvm::AArch64_AM::decodeAdvSIMDModImmType3 (uint8_t Imm)
 
static bool llvm::AArch64_AM::isAdvSIMDModImmType4 (uint64_t Imm)
 
static uint8_t llvm::AArch64_AM::encodeAdvSIMDModImmType4 (uint64_t Imm)
 
static uint64_t llvm::AArch64_AM::decodeAdvSIMDModImmType4 (uint8_t Imm)
 
static bool llvm::AArch64_AM::isAdvSIMDModImmType5 (uint64_t Imm)
 
static uint8_t llvm::AArch64_AM::encodeAdvSIMDModImmType5 (uint64_t Imm)
 
static uint64_t llvm::AArch64_AM::decodeAdvSIMDModImmType5 (uint8_t Imm)
 
static bool llvm::AArch64_AM::isAdvSIMDModImmType6 (uint64_t Imm)
 
static uint8_t llvm::AArch64_AM::encodeAdvSIMDModImmType6 (uint64_t Imm)
 
static uint64_t llvm::AArch64_AM::decodeAdvSIMDModImmType6 (uint8_t Imm)
 
static bool llvm::AArch64_AM::isAdvSIMDModImmType7 (uint64_t Imm)
 
static uint8_t llvm::AArch64_AM::encodeAdvSIMDModImmType7 (uint64_t Imm)
 
static uint64_t llvm::AArch64_AM::decodeAdvSIMDModImmType7 (uint8_t Imm)
 
static bool llvm::AArch64_AM::isAdvSIMDModImmType8 (uint64_t Imm)
 
static uint64_t llvm::AArch64_AM::decodeAdvSIMDModImmType8 (uint8_t Imm)
 
static uint8_t llvm::AArch64_AM::encodeAdvSIMDModImmType8 (uint64_t Imm)
 
static bool llvm::AArch64_AM::isAdvSIMDModImmType9 (uint64_t Imm)
 
static uint8_t llvm::AArch64_AM::encodeAdvSIMDModImmType9 (uint64_t Imm)
 
static uint64_t llvm::AArch64_AM::decodeAdvSIMDModImmType9 (uint8_t Imm)
 
static bool llvm::AArch64_AM::isAdvSIMDModImmType10 (uint64_t Imm)
 
static uint8_t llvm::AArch64_AM::encodeAdvSIMDModImmType10 (uint64_t Imm)
 
static uint64_t llvm::AArch64_AM::decodeAdvSIMDModImmType10 (uint8_t Imm)
 
static bool llvm::AArch64_AM::isAdvSIMDModImmType11 (uint64_t Imm)
 
static uint8_t llvm::AArch64_AM::encodeAdvSIMDModImmType11 (uint64_t Imm)
 
static uint64_t llvm::AArch64_AM::decodeAdvSIMDModImmType11 (uint8_t Imm)
 
static bool llvm::AArch64_AM::isAdvSIMDModImmType12 (uint64_t Imm)
 
static uint8_t llvm::AArch64_AM::encodeAdvSIMDModImmType12 (uint64_t Imm)
 
static uint64_t llvm::AArch64_AM::decodeAdvSIMDModImmType12 (uint8_t Imm)
 
static bool llvm::AArch64_AM::isAnyMOVZMovAlias (uint64_t Value, int RegWidth)
 
static bool llvm::AArch64_AM::isMOVZMovAlias (uint64_t Value, int Shift, int RegWidth)
 
static bool llvm::AArch64_AM::isMOVNMovAlias (uint64_t Value, int Shift, int RegWidth)
 
static bool llvm::AArch64_AM::isAnyMOVWMovAlias (uint64_t Value, int RegWidth)