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AArch64AddressingModes.h
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1 //===- AArch64AddressingModes.h - AArch64 Addressing Modes ------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the AArch64 addressing mode implementation stuff.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64ADDRESSINGMODES_H
15 #define LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64ADDRESSINGMODES_H
16 
17 #include "llvm/ADT/APFloat.h"
18 #include "llvm/ADT/APInt.h"
21 #include <cassert>
22 
23 namespace llvm {
24 
25 /// AArch64_AM - AArch64 Addressing Mode Stuff
26 namespace AArch64_AM {
27 
28 //===----------------------------------------------------------------------===//
29 // Shifts
30 //
31 
34  LSL = 0,
35  LSR,
36  ASR,
37  ROR,
38  MSL,
39 
44 
49 };
50 
51 /// getShiftName - Get the string encoding for the shift type.
53  switch (ST) {
54  default: llvm_unreachable("unhandled shift type!");
55  case AArch64_AM::LSL: return "lsl";
56  case AArch64_AM::LSR: return "lsr";
57  case AArch64_AM::ASR: return "asr";
58  case AArch64_AM::ROR: return "ror";
59  case AArch64_AM::MSL: return "msl";
60  case AArch64_AM::UXTB: return "uxtb";
61  case AArch64_AM::UXTH: return "uxth";
62  case AArch64_AM::UXTW: return "uxtw";
63  case AArch64_AM::UXTX: return "uxtx";
64  case AArch64_AM::SXTB: return "sxtb";
65  case AArch64_AM::SXTH: return "sxth";
66  case AArch64_AM::SXTW: return "sxtw";
67  case AArch64_AM::SXTX: return "sxtx";
68  }
69  return nullptr;
70 }
71 
72 /// getShiftType - Extract the shift type.
73 static inline AArch64_AM::ShiftExtendType getShiftType(unsigned Imm) {
74  switch ((Imm >> 6) & 0x7) {
75  default: return AArch64_AM::InvalidShiftExtend;
76  case 0: return AArch64_AM::LSL;
77  case 1: return AArch64_AM::LSR;
78  case 2: return AArch64_AM::ASR;
79  case 3: return AArch64_AM::ROR;
80  case 4: return AArch64_AM::MSL;
81  }
82 }
83 
84 /// getShiftValue - Extract the shift value.
85 static inline unsigned getShiftValue(unsigned Imm) {
86  return Imm & 0x3f;
87 }
88 
89 /// getShifterImm - Encode the shift type and amount:
90 /// imm: 6-bit shift amount
91 /// shifter: 000 ==> lsl
92 /// 001 ==> lsr
93 /// 010 ==> asr
94 /// 011 ==> ror
95 /// 100 ==> msl
96 /// {8-6} = shifter
97 /// {5-0} = imm
99  unsigned Imm) {
100  assert((Imm & 0x3f) == Imm && "Illegal shifted immedate value!");
101  unsigned STEnc = 0;
102  switch (ST) {
103  default: llvm_unreachable("Invalid shift requested");
104  case AArch64_AM::LSL: STEnc = 0; break;
105  case AArch64_AM::LSR: STEnc = 1; break;
106  case AArch64_AM::ASR: STEnc = 2; break;
107  case AArch64_AM::ROR: STEnc = 3; break;
108  case AArch64_AM::MSL: STEnc = 4; break;
109  }
110  return (STEnc << 6) | (Imm & 0x3f);
111 }
112 
113 //===----------------------------------------------------------------------===//
114 // Extends
115 //
116 
117 /// getArithShiftValue - get the arithmetic shift value.
118 static inline unsigned getArithShiftValue(unsigned Imm) {
119  return Imm & 0x7;
120 }
121 
122 /// getExtendType - Extract the extend type for operands of arithmetic ops.
123 static inline AArch64_AM::ShiftExtendType getExtendType(unsigned Imm) {
124  assert((Imm & 0x7) == Imm && "invalid immediate!");
125  switch (Imm) {
126  default: llvm_unreachable("Compiler bug!");
127  case 0: return AArch64_AM::UXTB;
128  case 1: return AArch64_AM::UXTH;
129  case 2: return AArch64_AM::UXTW;
130  case 3: return AArch64_AM::UXTX;
131  case 4: return AArch64_AM::SXTB;
132  case 5: return AArch64_AM::SXTH;
133  case 6: return AArch64_AM::SXTW;
134  case 7: return AArch64_AM::SXTX;
135  }
136 }
137 
138 static inline AArch64_AM::ShiftExtendType getArithExtendType(unsigned Imm) {
139  return getExtendType((Imm >> 3) & 0x7);
140 }
141 
142 /// Mapping from extend bits to required operation:
143 /// shifter: 000 ==> uxtb
144 /// 001 ==> uxth
145 /// 010 ==> uxtw
146 /// 011 ==> uxtx
147 /// 100 ==> sxtb
148 /// 101 ==> sxth
149 /// 110 ==> sxtw
150 /// 111 ==> sxtx
152  switch (ET) {
153  default: llvm_unreachable("Invalid extend type requested");
154  case AArch64_AM::UXTB: return 0; break;
155  case AArch64_AM::UXTH: return 1; break;
156  case AArch64_AM::UXTW: return 2; break;
157  case AArch64_AM::UXTX: return 3; break;
158  case AArch64_AM::SXTB: return 4; break;
159  case AArch64_AM::SXTH: return 5; break;
160  case AArch64_AM::SXTW: return 6; break;
161  case AArch64_AM::SXTX: return 7; break;
162  }
163 }
164 
165 /// getArithExtendImm - Encode the extend type and shift amount for an
166 /// arithmetic instruction:
167 /// imm: 3-bit extend amount
168 /// {5-3} = shifter
169 /// {2-0} = imm3
171  unsigned Imm) {
172  assert((Imm & 0x7) == Imm && "Illegal shifted immedate value!");
173  return (getExtendEncoding(ET) << 3) | (Imm & 0x7);
174 }
175 
176 /// getMemDoShift - Extract the "do shift" flag value for load/store
177 /// instructions.
178 static inline bool getMemDoShift(unsigned Imm) {
179  return (Imm & 0x1) != 0;
180 }
181 
182 /// getExtendType - Extract the extend type for the offset operand of
183 /// loads/stores.
184 static inline AArch64_AM::ShiftExtendType getMemExtendType(unsigned Imm) {
185  return getExtendType((Imm >> 1) & 0x7);
186 }
187 
188 /// getExtendImm - Encode the extend type and amount for a load/store inst:
189 /// doshift: should the offset be scaled by the access size
190 /// shifter: 000 ==> uxtb
191 /// 001 ==> uxth
192 /// 010 ==> uxtw
193 /// 011 ==> uxtx
194 /// 100 ==> sxtb
195 /// 101 ==> sxth
196 /// 110 ==> sxtw
197 /// 111 ==> sxtx
198 /// {3-1} = shifter
199 /// {0} = doshift
201  bool DoShift) {
202  return (getExtendEncoding(ET) << 1) | unsigned(DoShift);
203 }
204 
205 static inline uint64_t ror(uint64_t elt, unsigned size) {
206  return ((elt & 1) << (size-1)) | (elt >> 1);
207 }
208 
209 /// processLogicalImmediate - Determine if an immediate value can be encoded
210 /// as the immediate operand of a logical instruction for the given register
211 /// size. If so, return true with "encoding" set to the encoded value in
212 /// the form N:immr:imms.
213 static inline bool processLogicalImmediate(uint64_t Imm, unsigned RegSize,
214  uint64_t &Encoding) {
215  if (Imm == 0ULL || Imm == ~0ULL ||
216  (RegSize != 64 && (Imm >> RegSize != 0 || Imm == ~0U)))
217  return false;
218 
219  // First, determine the element size.
220  unsigned Size = RegSize;
221 
222  do {
223  Size /= 2;
224  uint64_t Mask = (1ULL << Size) - 1;
225 
226  if ((Imm & Mask) != ((Imm >> Size) & Mask)) {
227  Size *= 2;
228  break;
229  }
230  } while (Size > 2);
231 
232  // Second, determine the rotation to make the element be: 0^m 1^n.
233  uint32_t CTO, I;
234  uint64_t Mask = ((uint64_t)-1LL) >> (64 - Size);
235  Imm &= Mask;
236 
237  if (isShiftedMask_64(Imm)) {
238  I = countTrailingZeros(Imm);
239  assert(I < 64 && "undefined behavior");
240  CTO = countTrailingOnes(Imm >> I);
241  } else {
242  Imm |= ~Mask;
243  if (!isShiftedMask_64(~Imm))
244  return false;
245 
246  unsigned CLO = countLeadingOnes(Imm);
247  I = 64 - CLO;
248  CTO = CLO + countTrailingOnes(Imm) - (64 - Size);
249  }
250 
251  // Encode in Immr the number of RORs it would take to get *from* 0^m 1^n
252  // to our target value, where I is the number of RORs to go the opposite
253  // direction.
254  assert(Size > I && "I should be smaller than element size");
255  unsigned Immr = (Size - I) & (Size - 1);
256 
257  // If size has a 1 in the n'th bit, create a value that has zeroes in
258  // bits [0, n] and ones above that.
259  uint64_t NImms = ~(Size-1) << 1;
260 
261  // Or the CTO value into the low bits, which must be below the Nth bit
262  // bit mentioned above.
263  NImms |= (CTO-1);
264 
265  // Extract the seventh bit and toggle it to create the N field.
266  unsigned N = ((NImms >> 6) & 1) ^ 1;
267 
268  Encoding = (N << 12) | (Immr << 6) | (NImms & 0x3f);
269  return true;
270 }
271 
272 /// isLogicalImmediate - Return true if the immediate is valid for a logical
273 /// immediate instruction of the given register size. Return false otherwise.
274 static inline bool isLogicalImmediate(uint64_t imm, unsigned regSize) {
275  uint64_t encoding;
276  return processLogicalImmediate(imm, regSize, encoding);
277 }
278 
279 /// encodeLogicalImmediate - Return the encoded immediate value for a logical
280 /// immediate instruction of the given register size.
281 static inline uint64_t encodeLogicalImmediate(uint64_t imm, unsigned regSize) {
282  uint64_t encoding = 0;
283  bool res = processLogicalImmediate(imm, regSize, encoding);
284  assert(res && "invalid logical immediate");
285  (void)res;
286  return encoding;
287 }
288 
289 /// decodeLogicalImmediate - Decode a logical immediate value in the form
290 /// "N:immr:imms" (where the immr and imms fields are each 6 bits) into the
291 /// integer value it represents with regSize bits.
292 static inline uint64_t decodeLogicalImmediate(uint64_t val, unsigned regSize) {
293  // Extract the N, imms, and immr fields.
294  unsigned N = (val >> 12) & 1;
295  unsigned immr = (val >> 6) & 0x3f;
296  unsigned imms = val & 0x3f;
297 
298  assert((regSize == 64 || N == 0) && "undefined logical immediate encoding");
299  int len = 31 - countLeadingZeros((N << 6) | (~imms & 0x3f));
300  assert(len >= 0 && "undefined logical immediate encoding");
301  unsigned size = (1 << len);
302  unsigned R = immr & (size - 1);
303  unsigned S = imms & (size - 1);
304  assert(S != size - 1 && "undefined logical immediate encoding");
305  uint64_t pattern = (1ULL << (S + 1)) - 1;
306  for (unsigned i = 0; i < R; ++i)
307  pattern = ror(pattern, size);
308 
309  // Replicate the pattern to fill the regSize.
310  while (size != regSize) {
311  pattern |= (pattern << size);
312  size *= 2;
313  }
314  return pattern;
315 }
316 
317 /// isValidDecodeLogicalImmediate - Check to see if the logical immediate value
318 /// in the form "N:immr:imms" (where the immr and imms fields are each 6 bits)
319 /// is a valid encoding for an integer value with regSize bits.
320 static inline bool isValidDecodeLogicalImmediate(uint64_t val,
321  unsigned regSize) {
322  // Extract the N and imms fields needed for checking.
323  unsigned N = (val >> 12) & 1;
324  unsigned imms = val & 0x3f;
325 
326  if (regSize == 32 && N != 0) // undefined logical immediate encoding
327  return false;
328  int len = 31 - countLeadingZeros((N << 6) | (~imms & 0x3f));
329  if (len < 0) // undefined logical immediate encoding
330  return false;
331  unsigned size = (1 << len);
332  unsigned S = imms & (size - 1);
333  if (S == size - 1) // undefined logical immediate encoding
334  return false;
335 
336  return true;
337 }
338 
339 //===----------------------------------------------------------------------===//
340 // Floating-point Immediates
341 //
342 static inline float getFPImmFloat(unsigned Imm) {
343  // We expect an 8-bit binary encoding of a floating-point number here.
344  union {
345  uint32_t I;
346  float F;
347  } FPUnion;
348 
349  uint8_t Sign = (Imm >> 7) & 0x1;
350  uint8_t Exp = (Imm >> 4) & 0x7;
351  uint8_t Mantissa = Imm & 0xf;
352 
353  // 8-bit FP iEEEE Float Encoding
354  // abcd efgh aBbbbbbc defgh000 00000000 00000000
355  //
356  // where B = NOT(b);
357 
358  FPUnion.I = 0;
359  FPUnion.I |= Sign << 31;
360  FPUnion.I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30;
361  FPUnion.I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25;
362  FPUnion.I |= (Exp & 0x3) << 23;
363  FPUnion.I |= Mantissa << 19;
364  return FPUnion.F;
365 }
366 
367 /// getFP16Imm - Return an 8-bit floating-point version of the 16-bit
368 /// floating-point value. If the value cannot be represented as an 8-bit
369 /// floating-point value, then return -1.
370 static inline int getFP16Imm(const APInt &Imm) {
371  uint32_t Sign = Imm.lshr(15).getZExtValue() & 1;
372  int32_t Exp = (Imm.lshr(10).getSExtValue() & 0x1f) - 15; // -14 to 15
373  int32_t Mantissa = Imm.getZExtValue() & 0x3ff; // 10 bits
374 
375  // We can handle 4 bits of mantissa.
376  // mantissa = (16+UInt(e:f:g:h))/16.
377  if (Mantissa & 0x3f)
378  return -1;
379  Mantissa >>= 6;
380 
381  // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
382  if (Exp < -3 || Exp > 4)
383  return -1;
384  Exp = ((Exp+3) & 0x7) ^ 4;
385 
386  return ((int)Sign << 7) | (Exp << 4) | Mantissa;
387 }
388 
389 static inline int getFP16Imm(const APFloat &FPImm) {
390  return getFP16Imm(FPImm.bitcastToAPInt());
391 }
392 
393 /// getFP32Imm - Return an 8-bit floating-point version of the 32-bit
394 /// floating-point value. If the value cannot be represented as an 8-bit
395 /// floating-point value, then return -1.
396 static inline int getFP32Imm(const APInt &Imm) {
397  uint32_t Sign = Imm.lshr(31).getZExtValue() & 1;
398  int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127; // -126 to 127
399  int64_t Mantissa = Imm.getZExtValue() & 0x7fffff; // 23 bits
400 
401  // We can handle 4 bits of mantissa.
402  // mantissa = (16+UInt(e:f:g:h))/16.
403  if (Mantissa & 0x7ffff)
404  return -1;
405  Mantissa >>= 19;
406  if ((Mantissa & 0xf) != Mantissa)
407  return -1;
408 
409  // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
410  if (Exp < -3 || Exp > 4)
411  return -1;
412  Exp = ((Exp+3) & 0x7) ^ 4;
413 
414  return ((int)Sign << 7) | (Exp << 4) | Mantissa;
415 }
416 
417 static inline int getFP32Imm(const APFloat &FPImm) {
418  return getFP32Imm(FPImm.bitcastToAPInt());
419 }
420 
421 /// getFP64Imm - Return an 8-bit floating-point version of the 64-bit
422 /// floating-point value. If the value cannot be represented as an 8-bit
423 /// floating-point value, then return -1.
424 static inline int getFP64Imm(const APInt &Imm) {
425  uint64_t Sign = Imm.lshr(63).getZExtValue() & 1;
426  int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023; // -1022 to 1023
427  uint64_t Mantissa = Imm.getZExtValue() & 0xfffffffffffffULL;
428 
429  // We can handle 4 bits of mantissa.
430  // mantissa = (16+UInt(e:f:g:h))/16.
431  if (Mantissa & 0xffffffffffffULL)
432  return -1;
433  Mantissa >>= 48;
434  if ((Mantissa & 0xf) != Mantissa)
435  return -1;
436 
437  // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
438  if (Exp < -3 || Exp > 4)
439  return -1;
440  Exp = ((Exp+3) & 0x7) ^ 4;
441 
442  return ((int)Sign << 7) | (Exp << 4) | Mantissa;
443 }
444 
445 static inline int getFP64Imm(const APFloat &FPImm) {
446  return getFP64Imm(FPImm.bitcastToAPInt());
447 }
448 
449 //===--------------------------------------------------------------------===//
450 // AdvSIMD Modified Immediates
451 //===--------------------------------------------------------------------===//
452 
453 // 0x00 0x00 0x00 abcdefgh 0x00 0x00 0x00 abcdefgh
454 static inline bool isAdvSIMDModImmType1(uint64_t Imm) {
455  return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
456  ((Imm & 0xffffff00ffffff00ULL) == 0);
457 }
458 
459 static inline uint8_t encodeAdvSIMDModImmType1(uint64_t Imm) {
460  return (Imm & 0xffULL);
461 }
462 
463 static inline uint64_t decodeAdvSIMDModImmType1(uint8_t Imm) {
464  uint64_t EncVal = Imm;
465  return (EncVal << 32) | EncVal;
466 }
467 
468 // 0x00 0x00 abcdefgh 0x00 0x00 0x00 abcdefgh 0x00
469 static inline bool isAdvSIMDModImmType2(uint64_t Imm) {
470  return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
471  ((Imm & 0xffff00ffffff00ffULL) == 0);
472 }
473 
474 static inline uint8_t encodeAdvSIMDModImmType2(uint64_t Imm) {
475  return (Imm & 0xff00ULL) >> 8;
476 }
477 
478 static inline uint64_t decodeAdvSIMDModImmType2(uint8_t Imm) {
479  uint64_t EncVal = Imm;
480  return (EncVal << 40) | (EncVal << 8);
481 }
482 
483 // 0x00 abcdefgh 0x00 0x00 0x00 abcdefgh 0x00 0x00
484 static inline bool isAdvSIMDModImmType3(uint64_t Imm) {
485  return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
486  ((Imm & 0xff00ffffff00ffffULL) == 0);
487 }
488 
489 static inline uint8_t encodeAdvSIMDModImmType3(uint64_t Imm) {
490  return (Imm & 0xff0000ULL) >> 16;
491 }
492 
493 static inline uint64_t decodeAdvSIMDModImmType3(uint8_t Imm) {
494  uint64_t EncVal = Imm;
495  return (EncVal << 48) | (EncVal << 16);
496 }
497 
498 // abcdefgh 0x00 0x00 0x00 abcdefgh 0x00 0x00 0x00
499 static inline bool isAdvSIMDModImmType4(uint64_t Imm) {
500  return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
501  ((Imm & 0x00ffffff00ffffffULL) == 0);
502 }
503 
504 static inline uint8_t encodeAdvSIMDModImmType4(uint64_t Imm) {
505  return (Imm & 0xff000000ULL) >> 24;
506 }
507 
508 static inline uint64_t decodeAdvSIMDModImmType4(uint8_t Imm) {
509  uint64_t EncVal = Imm;
510  return (EncVal << 56) | (EncVal << 24);
511 }
512 
513 // 0x00 abcdefgh 0x00 abcdefgh 0x00 abcdefgh 0x00 abcdefgh
514 static inline bool isAdvSIMDModImmType5(uint64_t Imm) {
515  return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
516  (((Imm & 0x00ff0000ULL) >> 16) == (Imm & 0x000000ffULL)) &&
517  ((Imm & 0xff00ff00ff00ff00ULL) == 0);
518 }
519 
520 static inline uint8_t encodeAdvSIMDModImmType5(uint64_t Imm) {
521  return (Imm & 0xffULL);
522 }
523 
524 static inline uint64_t decodeAdvSIMDModImmType5(uint8_t Imm) {
525  uint64_t EncVal = Imm;
526  return (EncVal << 48) | (EncVal << 32) | (EncVal << 16) | EncVal;
527 }
528 
529 // abcdefgh 0x00 abcdefgh 0x00 abcdefgh 0x00 abcdefgh 0x00
530 static inline bool isAdvSIMDModImmType6(uint64_t Imm) {
531  return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
532  (((Imm & 0xff000000ULL) >> 16) == (Imm & 0x0000ff00ULL)) &&
533  ((Imm & 0x00ff00ff00ff00ffULL) == 0);
534 }
535 
536 static inline uint8_t encodeAdvSIMDModImmType6(uint64_t Imm) {
537  return (Imm & 0xff00ULL) >> 8;
538 }
539 
540 static inline uint64_t decodeAdvSIMDModImmType6(uint8_t Imm) {
541  uint64_t EncVal = Imm;
542  return (EncVal << 56) | (EncVal << 40) | (EncVal << 24) | (EncVal << 8);
543 }
544 
545 // 0x00 0x00 abcdefgh 0xFF 0x00 0x00 abcdefgh 0xFF
546 static inline bool isAdvSIMDModImmType7(uint64_t Imm) {
547  return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
548  ((Imm & 0xffff00ffffff00ffULL) == 0x000000ff000000ffULL);
549 }
550 
551 static inline uint8_t encodeAdvSIMDModImmType7(uint64_t Imm) {
552  return (Imm & 0xff00ULL) >> 8;
553 }
554 
555 static inline uint64_t decodeAdvSIMDModImmType7(uint8_t Imm) {
556  uint64_t EncVal = Imm;
557  return (EncVal << 40) | (EncVal << 8) | 0x000000ff000000ffULL;
558 }
559 
560 // 0x00 abcdefgh 0xFF 0xFF 0x00 abcdefgh 0xFF 0xFF
561 static inline bool isAdvSIMDModImmType8(uint64_t Imm) {
562  return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
563  ((Imm & 0xff00ffffff00ffffULL) == 0x0000ffff0000ffffULL);
564 }
565 
566 static inline uint64_t decodeAdvSIMDModImmType8(uint8_t Imm) {
567  uint64_t EncVal = Imm;
568  return (EncVal << 48) | (EncVal << 16) | 0x0000ffff0000ffffULL;
569 }
570 
571 static inline uint8_t encodeAdvSIMDModImmType8(uint64_t Imm) {
572  return (Imm & 0x00ff0000ULL) >> 16;
573 }
574 
575 // abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh
576 static inline bool isAdvSIMDModImmType9(uint64_t Imm) {
577  return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
578  ((Imm >> 48) == (Imm & 0x0000ffffULL)) &&
579  ((Imm >> 56) == (Imm & 0x000000ffULL));
580 }
581 
582 static inline uint8_t encodeAdvSIMDModImmType9(uint64_t Imm) {
583  return (Imm & 0xffULL);
584 }
585 
586 static inline uint64_t decodeAdvSIMDModImmType9(uint8_t Imm) {
587  uint64_t EncVal = Imm;
588  EncVal |= (EncVal << 8);
589  EncVal |= (EncVal << 16);
590  EncVal |= (EncVal << 32);
591  return EncVal;
592 }
593 
594 // aaaaaaaa bbbbbbbb cccccccc dddddddd eeeeeeee ffffffff gggggggg hhhhhhhh
595 // cmode: 1110, op: 1
596 static inline bool isAdvSIMDModImmType10(uint64_t Imm) {
597  uint64_t ByteA = Imm & 0xff00000000000000ULL;
598  uint64_t ByteB = Imm & 0x00ff000000000000ULL;
599  uint64_t ByteC = Imm & 0x0000ff0000000000ULL;
600  uint64_t ByteD = Imm & 0x000000ff00000000ULL;
601  uint64_t ByteE = Imm & 0x00000000ff000000ULL;
602  uint64_t ByteF = Imm & 0x0000000000ff0000ULL;
603  uint64_t ByteG = Imm & 0x000000000000ff00ULL;
604  uint64_t ByteH = Imm & 0x00000000000000ffULL;
605 
606  return (ByteA == 0ULL || ByteA == 0xff00000000000000ULL) &&
607  (ByteB == 0ULL || ByteB == 0x00ff000000000000ULL) &&
608  (ByteC == 0ULL || ByteC == 0x0000ff0000000000ULL) &&
609  (ByteD == 0ULL || ByteD == 0x000000ff00000000ULL) &&
610  (ByteE == 0ULL || ByteE == 0x00000000ff000000ULL) &&
611  (ByteF == 0ULL || ByteF == 0x0000000000ff0000ULL) &&
612  (ByteG == 0ULL || ByteG == 0x000000000000ff00ULL) &&
613  (ByteH == 0ULL || ByteH == 0x00000000000000ffULL);
614 }
615 
616 static inline uint8_t encodeAdvSIMDModImmType10(uint64_t Imm) {
617  uint8_t BitA = (Imm & 0xff00000000000000ULL) != 0;
618  uint8_t BitB = (Imm & 0x00ff000000000000ULL) != 0;
619  uint8_t BitC = (Imm & 0x0000ff0000000000ULL) != 0;
620  uint8_t BitD = (Imm & 0x000000ff00000000ULL) != 0;
621  uint8_t BitE = (Imm & 0x00000000ff000000ULL) != 0;
622  uint8_t BitF = (Imm & 0x0000000000ff0000ULL) != 0;
623  uint8_t BitG = (Imm & 0x000000000000ff00ULL) != 0;
624  uint8_t BitH = (Imm & 0x00000000000000ffULL) != 0;
625 
626  uint8_t EncVal = BitA;
627  EncVal <<= 1;
628  EncVal |= BitB;
629  EncVal <<= 1;
630  EncVal |= BitC;
631  EncVal <<= 1;
632  EncVal |= BitD;
633  EncVal <<= 1;
634  EncVal |= BitE;
635  EncVal <<= 1;
636  EncVal |= BitF;
637  EncVal <<= 1;
638  EncVal |= BitG;
639  EncVal <<= 1;
640  EncVal |= BitH;
641  return EncVal;
642 }
643 
644 static inline uint64_t decodeAdvSIMDModImmType10(uint8_t Imm) {
645  uint64_t EncVal = 0;
646  if (Imm & 0x80) EncVal |= 0xff00000000000000ULL;
647  if (Imm & 0x40) EncVal |= 0x00ff000000000000ULL;
648  if (Imm & 0x20) EncVal |= 0x0000ff0000000000ULL;
649  if (Imm & 0x10) EncVal |= 0x000000ff00000000ULL;
650  if (Imm & 0x08) EncVal |= 0x00000000ff000000ULL;
651  if (Imm & 0x04) EncVal |= 0x0000000000ff0000ULL;
652  if (Imm & 0x02) EncVal |= 0x000000000000ff00ULL;
653  if (Imm & 0x01) EncVal |= 0x00000000000000ffULL;
654  return EncVal;
655 }
656 
657 // aBbbbbbc defgh000 0x00 0x00 aBbbbbbc defgh000 0x00 0x00
658 static inline bool isAdvSIMDModImmType11(uint64_t Imm) {
659  uint64_t BString = (Imm & 0x7E000000ULL) >> 25;
660  return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
661  (BString == 0x1f || BString == 0x20) &&
662  ((Imm & 0x0007ffff0007ffffULL) == 0);
663 }
664 
665 static inline uint8_t encodeAdvSIMDModImmType11(uint64_t Imm) {
666  uint8_t BitA = (Imm & 0x80000000ULL) != 0;
667  uint8_t BitB = (Imm & 0x20000000ULL) != 0;
668  uint8_t BitC = (Imm & 0x01000000ULL) != 0;
669  uint8_t BitD = (Imm & 0x00800000ULL) != 0;
670  uint8_t BitE = (Imm & 0x00400000ULL) != 0;
671  uint8_t BitF = (Imm & 0x00200000ULL) != 0;
672  uint8_t BitG = (Imm & 0x00100000ULL) != 0;
673  uint8_t BitH = (Imm & 0x00080000ULL) != 0;
674 
675  uint8_t EncVal = BitA;
676  EncVal <<= 1;
677  EncVal |= BitB;
678  EncVal <<= 1;
679  EncVal |= BitC;
680  EncVal <<= 1;
681  EncVal |= BitD;
682  EncVal <<= 1;
683  EncVal |= BitE;
684  EncVal <<= 1;
685  EncVal |= BitF;
686  EncVal <<= 1;
687  EncVal |= BitG;
688  EncVal <<= 1;
689  EncVal |= BitH;
690  return EncVal;
691 }
692 
693 static inline uint64_t decodeAdvSIMDModImmType11(uint8_t Imm) {
694  uint64_t EncVal = 0;
695  if (Imm & 0x80) EncVal |= 0x80000000ULL;
696  if (Imm & 0x40) EncVal |= 0x3e000000ULL;
697  else EncVal |= 0x40000000ULL;
698  if (Imm & 0x20) EncVal |= 0x01000000ULL;
699  if (Imm & 0x10) EncVal |= 0x00800000ULL;
700  if (Imm & 0x08) EncVal |= 0x00400000ULL;
701  if (Imm & 0x04) EncVal |= 0x00200000ULL;
702  if (Imm & 0x02) EncVal |= 0x00100000ULL;
703  if (Imm & 0x01) EncVal |= 0x00080000ULL;
704  return (EncVal << 32) | EncVal;
705 }
706 
707 // aBbbbbbb bbcdefgh 0x00 0x00 0x00 0x00 0x00 0x00
708 static inline bool isAdvSIMDModImmType12(uint64_t Imm) {
709  uint64_t BString = (Imm & 0x7fc0000000000000ULL) >> 54;
710  return ((BString == 0xff || BString == 0x100) &&
711  ((Imm & 0x0000ffffffffffffULL) == 0));
712 }
713 
714 static inline uint8_t encodeAdvSIMDModImmType12(uint64_t Imm) {
715  uint8_t BitA = (Imm & 0x8000000000000000ULL) != 0;
716  uint8_t BitB = (Imm & 0x0040000000000000ULL) != 0;
717  uint8_t BitC = (Imm & 0x0020000000000000ULL) != 0;
718  uint8_t BitD = (Imm & 0x0010000000000000ULL) != 0;
719  uint8_t BitE = (Imm & 0x0008000000000000ULL) != 0;
720  uint8_t BitF = (Imm & 0x0004000000000000ULL) != 0;
721  uint8_t BitG = (Imm & 0x0002000000000000ULL) != 0;
722  uint8_t BitH = (Imm & 0x0001000000000000ULL) != 0;
723 
724  uint8_t EncVal = BitA;
725  EncVal <<= 1;
726  EncVal |= BitB;
727  EncVal <<= 1;
728  EncVal |= BitC;
729  EncVal <<= 1;
730  EncVal |= BitD;
731  EncVal <<= 1;
732  EncVal |= BitE;
733  EncVal <<= 1;
734  EncVal |= BitF;
735  EncVal <<= 1;
736  EncVal |= BitG;
737  EncVal <<= 1;
738  EncVal |= BitH;
739  return EncVal;
740 }
741 
742 static inline uint64_t decodeAdvSIMDModImmType12(uint8_t Imm) {
743  uint64_t EncVal = 0;
744  if (Imm & 0x80) EncVal |= 0x8000000000000000ULL;
745  if (Imm & 0x40) EncVal |= 0x3fc0000000000000ULL;
746  else EncVal |= 0x4000000000000000ULL;
747  if (Imm & 0x20) EncVal |= 0x0020000000000000ULL;
748  if (Imm & 0x10) EncVal |= 0x0010000000000000ULL;
749  if (Imm & 0x08) EncVal |= 0x0008000000000000ULL;
750  if (Imm & 0x04) EncVal |= 0x0004000000000000ULL;
751  if (Imm & 0x02) EncVal |= 0x0002000000000000ULL;
752  if (Imm & 0x01) EncVal |= 0x0001000000000000ULL;
753  return (EncVal << 32) | EncVal;
754 }
755 
756 inline static bool isAnyMOVZMovAlias(uint64_t Value, int RegWidth) {
757  for (int Shift = 0; Shift <= RegWidth - 16; Shift += 16)
758  if ((Value & ~(0xffffULL << Shift)) == 0)
759  return true;
760 
761  return false;
762 }
763 
764 inline static bool isMOVZMovAlias(uint64_t Value, int Shift, int RegWidth) {
765  if (RegWidth == 32)
766  Value &= 0xffffffffULL;
767 
768  // "lsl #0" takes precedence: in practice this only affects "#0, lsl #0".
769  if (Value == 0 && Shift != 0)
770  return false;
771 
772  return (Value & ~(0xffffULL << Shift)) == 0;
773 }
774 
775 inline static bool isMOVNMovAlias(uint64_t Value, int Shift, int RegWidth) {
776  // MOVZ takes precedence over MOVN.
777  if (isAnyMOVZMovAlias(Value, RegWidth))
778  return false;
779 
780  Value = ~Value;
781  if (RegWidth == 32)
782  Value &= 0xffffffffULL;
783 
784  return isMOVZMovAlias(Value, Shift, RegWidth);
785 }
786 
787 inline static bool isAnyMOVWMovAlias(uint64_t Value, int RegWidth) {
788  if (isAnyMOVZMovAlias(Value, RegWidth))
789  return true;
790 
791  // It's not a MOVZ, but it might be a MOVN.
792  Value = ~Value;
793  if (RegWidth == 32)
794  Value &= 0xffffffffULL;
795 
796  return isAnyMOVZMovAlias(Value, RegWidth);
797 }
798 
799 } // end namespace AArch64_AM
800 
801 } // end namespace llvm
802 
803 #endif
static bool isAdvSIMDModImmType6(uint64_t Imm)
static uint64_t decodeAdvSIMDModImmType9(uint8_t Imm)
static float getFPImmFloat(unsigned Imm)
uint64_t getZExtValue() const
Get zero extended value.
Definition: APInt.h:1542
static uint8_t encodeAdvSIMDModImmType3(uint64_t Imm)
static unsigned getArithShiftValue(unsigned Imm)
getArithShiftValue - get the arithmetic shift value.
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
static int getFP16Imm(const APInt &Imm)
getFP16Imm - Return an 8-bit floating-point version of the 16-bit floating-point value.
static bool isAdvSIMDModImmType12(uint64_t Imm)
static bool isAdvSIMDModImmType4(uint64_t Imm)
static uint8_t encodeAdvSIMDModImmType1(uint64_t Imm)
static uint64_t decodeAdvSIMDModImmType3(uint8_t Imm)
static bool processLogicalImmediate(uint64_t Imm, unsigned RegSize, uint64_t &Encoding)
processLogicalImmediate - Determine if an immediate value can be encoded as the immediate operand of ...
static uint64_t decodeAdvSIMDModImmType12(uint8_t Imm)
static bool isMOVZMovAlias(uint64_t Value, int Shift, int RegWidth)
F(f)
static bool isAdvSIMDModImmType3(uint64_t Imm)
static bool isAnyMOVZMovAlias(uint64_t Value, int RegWidth)
std::size_t countLeadingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0&#39;s from the most significant bit to the least stopping at the first 1...
Definition: MathExtras.h:181
static bool getMemDoShift(unsigned Imm)
getMemDoShift - Extract the "do shift" flag value for load/store instructions.
static bool isAdvSIMDModImmType7(uint64_t Imm)
static uint64_t decodeAdvSIMDModImmType5(uint8_t Imm)
std::size_t countTrailingOnes(T Value, ZeroBehavior ZB=ZB_Width)
Count the number of ones from the least significant bit to the first zero bit.
Definition: MathExtras.h:470
static uint8_t encodeAdvSIMDModImmType6(uint64_t Imm)
static bool isLogicalImmediate(uint64_t imm, unsigned regSize)
isLogicalImmediate - Return true if the immediate is valid for a logical immediate instruction of the...
static bool isAdvSIMDModImmType5(uint64_t Imm)
This file implements a class to represent arbitrary precision integral constant values and operations...
static bool isMOVNMovAlias(uint64_t Value, int Shift, int RegWidth)
int64_t getSExtValue() const
Get sign extended value.
Definition: APInt.h:1554
static AArch64_AM::ShiftExtendType getMemExtendType(unsigned Imm)
getExtendType - Extract the extend type for the offset operand of loads/stores.
static bool isAdvSIMDModImmType2(uint64_t Imm)
static unsigned getShifterImm(AArch64_AM::ShiftExtendType ST, unsigned Imm)
getShifterImm - Encode the shift type and amount: imm: 6-bit shift amount shifter: 000 ==> lsl 001 ==...
static bool isAdvSIMDModImmType9(uint64_t Imm)
static unsigned getShiftValue(unsigned Imm)
getShiftValue - Extract the shift value.
std::size_t countTrailingZeros(T Val, ZeroBehavior ZB=ZB_Width)
Count number of 0&#39;s from the least significant bit to the most stopping at the first 1...
Definition: MathExtras.h:112
static int getFP32Imm(const APInt &Imm)
getFP32Imm - Return an 8-bit floating-point version of the 32-bit floating-point value.
static const char * getShiftExtendName(AArch64_AM::ShiftExtendType ST)
getShiftName - Get the string encoding for the shift type.
static AArch64_AM::ShiftExtendType getArithExtendType(unsigned Imm)
static uint64_t decodeLogicalImmediate(uint64_t val, unsigned regSize)
decodeLogicalImmediate - Decode a logical immediate value in the form "N:immr:imms" (where the immr a...
static unsigned getMemExtendImm(AArch64_AM::ShiftExtendType ET, bool DoShift)
getExtendImm - Encode the extend type and amount for a load/store inst: doshift: should the offset be...
static uint64_t decodeAdvSIMDModImmType6(uint8_t Imm)
static bool isAdvSIMDModImmType1(uint64_t Imm)
This file declares a class to represent arbitrary precision floating point values and provide a varie...
static bool isAdvSIMDModImmType8(uint64_t Imm)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static uint8_t encodeAdvSIMDModImmType12(uint64_t Imm)
APInt lshr(unsigned shiftAmt) const
Logical right-shift function.
Definition: APInt.h:959
unsigned getExtendEncoding(AArch64_AM::ShiftExtendType ET)
Mapping from extend bits to required operation: shifter: 000 ==> uxtb 001 ==> uxth 010 ==> uxtw 011 =...
static uint8_t encodeAdvSIMDModImmType2(uint64_t Imm)
static uint64_t encodeLogicalImmediate(uint64_t imm, unsigned regSize)
encodeLogicalImmediate - Return the encoded immediate value for a logical immediate instruction of th...
static int getFP64Imm(const APInt &Imm)
getFP64Imm - Return an 8-bit floating-point version of the 64-bit floating-point value.
static AArch64_AM::ShiftExtendType getExtendType(unsigned Imm)
getExtendType - Extract the extend type for operands of arithmetic ops.
static uint64_t decodeAdvSIMDModImmType7(uint8_t Imm)
Class for arbitrary precision integers.
Definition: APInt.h:69
static uint8_t encodeAdvSIMDModImmType10(uint64_t Imm)
static uint64_t decodeAdvSIMDModImmType1(uint8_t Imm)
static unsigned getArithExtendImm(AArch64_AM::ShiftExtendType ET, unsigned Imm)
getArithExtendImm - Encode the extend type and shift amount for an arithmetic instruction: imm: 3-bit...
static uint8_t encodeAdvSIMDModImmType5(uint64_t Imm)
static uint64_t decodeAdvSIMDModImmType8(uint8_t Imm)
static bool isAdvSIMDModImmType10(uint64_t Imm)
static uint8_t encodeAdvSIMDModImmType8(uint64_t Imm)
constexpr bool isShiftedMask_64(uint64_t Value)
Return true if the argument contains a non-empty sequence of ones with the remainder zero (64 bit ver...
Definition: MathExtras.h:415
static AArch64_AM::ShiftExtendType getShiftType(unsigned Imm)
getShiftType - Extract the shift type.
static bool isAnyMOVWMovAlias(uint64_t Value, int RegWidth)
static uint8_t encodeAdvSIMDModImmType4(uint64_t Imm)
static uint8_t encodeAdvSIMDModImmType11(uint64_t Imm)
static uint64_t decodeAdvSIMDModImmType10(uint8_t Imm)
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
static bool isValidDecodeLogicalImmediate(uint64_t val, unsigned regSize)
isValidDecodeLogicalImmediate - Check to see if the logical immediate value in the form "N:immr:imms"...
static uint64_t decodeAdvSIMDModImmType11(uint8_t Imm)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static uint64_t decodeAdvSIMDModImmType4(uint8_t Imm)
LLVM Value Representation.
Definition: Value.h:73
static uint64_t decodeAdvSIMDModImmType2(uint8_t Imm)
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
std::underlying_type< E >::type Mask()
Get a bitmask with 1s in all places up to the high-order bit of E&#39;s largest value.
Definition: BitmaskEnum.h:81
static uint64_t ror(uint64_t elt, unsigned size)
APInt bitcastToAPInt() const
Definition: APFloat.h:1094
static uint8_t encodeAdvSIMDModImmType9(uint64_t Imm)
static bool isAdvSIMDModImmType11(uint64_t Imm)
static uint8_t encodeAdvSIMDModImmType7(uint64_t Imm)
std::size_t countLeadingOnes(T Value, ZeroBehavior ZB=ZB_Width)
Count the number of ones from the most significant bit to the first zero bit.
Definition: MathExtras.h:454