LLVM  9.0.0svn
AArch64ELFObjectWriter.cpp
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1 //===-- AArch64ELFObjectWriter.cpp - AArch64 ELF Writer -------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file handles ELF-specific object emission, converting LLVM's internal
10 // fixups into the appropriate relocations.
11 //
12 //===----------------------------------------------------------------------===//
13 
17 #include "llvm/BinaryFormat/ELF.h"
18 #include "llvm/MC/MCContext.h"
20 #include "llvm/MC/MCFixup.h"
21 #include "llvm/MC/MCObjectWriter.h"
22 #include "llvm/MC/MCValue.h"
24 #include <cassert>
25 #include <cstdint>
26 
27 using namespace llvm;
28 
29 namespace {
30 
31 class AArch64ELFObjectWriter : public MCELFObjectTargetWriter {
32 public:
33  AArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32);
34 
35  ~AArch64ELFObjectWriter() override = default;
36 
37 protected:
38  unsigned getRelocType(MCContext &Ctx, const MCValue &Target,
39  const MCFixup &Fixup, bool IsPCRel) const override;
40  bool IsILP32;
41 };
42 
43 } // end anonymous namespace
44 
45 AArch64ELFObjectWriter::AArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32)
46  : MCELFObjectTargetWriter(/*Is64Bit*/ true, OSABI, ELF::EM_AARCH64,
47  /*HasRelocationAddend*/ true),
48  IsILP32(IsILP32) {}
49 
50 #define R_CLS(rtype) \
51  IsILP32 ? ELF::R_AARCH64_P32_##rtype : ELF::R_AARCH64_##rtype
52 #define BAD_ILP32_MOV(lp64rtype) \
53  "ILP32 absolute MOV relocation not " \
54  "supported (LP64 eqv: " #lp64rtype ")"
55 
56 // assumes IsILP32 is true
57 static bool isNonILP32reloc(const MCFixup &Fixup,
59  MCContext &Ctx) {
60  if ((unsigned)Fixup.getKind() != AArch64::fixup_aarch64_movw)
61  return false;
62  switch (RefKind) {
64  Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_UABS_G3));
65  return true;
67  Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_UABS_G2));
68  return true;
70  Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_SABS_G2));
71  return true;
73  Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_UABS_G2_NC));
74  return true;
76  Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_SABS_G1));
77  return true;
79  Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(MOVW_UABS_G1_NC));
80  return true;
82  Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSLD_MOVW_DTPREL_G2));
83  return true;
85  Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSLD_MOVW_DTPREL_G1_NC));
86  return true;
88  Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSLE_MOVW_TPREL_G2));
89  return true;
91  Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSLE_MOVW_TPREL_G1_NC));
92  return true;
94  Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSIE_MOVW_GOTTPREL_G1));
95  return true;
97  Ctx.reportError(Fixup.getLoc(), BAD_ILP32_MOV(TLSIE_MOVW_GOTTPREL_G0_NC));
98  return true;
99  default:
100  return false;
101  }
102  return false;
103 }
104 
106  const MCValue &Target,
107  const MCFixup &Fixup,
108  bool IsPCRel) const {
110  static_cast<AArch64MCExpr::VariantKind>(Target.getRefKind());
112  bool IsNC = AArch64MCExpr::isNotChecked(RefKind);
113 
114  assert((!Target.getSymA() ||
115  Target.getSymA()->getKind() == MCSymbolRefExpr::VK_None) &&
116  "Should only be expression-level modifiers here");
117 
118  assert((!Target.getSymB() ||
119  Target.getSymB()->getKind() == MCSymbolRefExpr::VK_None) &&
120  "Should only be expression-level modifiers here");
121 
122  if (IsPCRel) {
123  switch ((unsigned)Fixup.getKind()) {
124  case FK_Data_1:
125  Ctx.reportError(Fixup.getLoc(), "1-byte data relocations not supported");
126  return ELF::R_AARCH64_NONE;
127  case FK_Data_2:
128  return R_CLS(PREL16);
129  case FK_Data_4:
130  return R_CLS(PREL32);
131  case FK_Data_8:
132  if (IsILP32) {
133  Ctx.reportError(Fixup.getLoc(),
134  "ILP32 8 byte PC relative data "
135  "relocation not supported (LP64 eqv: PREL64)");
136  return ELF::R_AARCH64_NONE;
137  } else
138  return ELF::R_AARCH64_PREL64;
140  if (SymLoc != AArch64MCExpr::VK_ABS)
141  Ctx.reportError(Fixup.getLoc(),
142  "invalid symbol kind for ADR relocation");
143  return R_CLS(ADR_PREL_LO21);
145  if (SymLoc == AArch64MCExpr::VK_ABS && !IsNC)
146  return R_CLS(ADR_PREL_PG_HI21);
147  if (SymLoc == AArch64MCExpr::VK_ABS && IsNC) {
148  if (IsILP32) {
149  Ctx.reportError(Fixup.getLoc(),
150  "invalid fixup for 32-bit pcrel ADRP instruction "
151  "VK_ABS VK_NC");
152  return ELF::R_AARCH64_NONE;
153  } else {
154  return ELF::R_AARCH64_ADR_PREL_PG_HI21_NC;
155  }
156  }
157  if (SymLoc == AArch64MCExpr::VK_GOT && !IsNC)
158  return R_CLS(ADR_GOT_PAGE);
159  if (SymLoc == AArch64MCExpr::VK_GOTTPREL && !IsNC)
160  return R_CLS(TLSIE_ADR_GOTTPREL_PAGE21);
161  if (SymLoc == AArch64MCExpr::VK_TLSDESC && !IsNC)
162  return R_CLS(TLSDESC_ADR_PAGE21);
163  Ctx.reportError(Fixup.getLoc(),
164  "invalid symbol kind for ADRP relocation");
165  return ELF::R_AARCH64_NONE;
167  return R_CLS(JUMP26);
169  return R_CLS(CALL26);
171  if (SymLoc == AArch64MCExpr::VK_GOTTPREL)
172  return R_CLS(TLSIE_LD_GOTTPREL_PREL19);
173  if (SymLoc == AArch64MCExpr::VK_GOT)
174  return R_CLS(GOT_LD_PREL19);
175  return R_CLS(LD_PREL_LO19);
177  return R_CLS(TSTBR14);
179  return R_CLS(CONDBR19);
180  default:
181  Ctx.reportError(Fixup.getLoc(), "Unsupported pc-relative fixup kind");
182  return ELF::R_AARCH64_NONE;
183  }
184  } else {
185  if (IsILP32 && isNonILP32reloc(Fixup, RefKind, Ctx))
186  return ELF::R_AARCH64_NONE;
187  switch ((unsigned)Fixup.getKind()) {
188  case FK_Data_1:
189  Ctx.reportError(Fixup.getLoc(), "1-byte data relocations not supported");
190  return ELF::R_AARCH64_NONE;
191  case FK_Data_2:
192  return R_CLS(ABS16);
193  case FK_Data_4:
194  return R_CLS(ABS32);
195  case FK_Data_8:
196  if (IsILP32) {
197  Ctx.reportError(Fixup.getLoc(),
198  "ILP32 8 byte absolute data "
199  "relocation not supported (LP64 eqv: ABS64)");
200  return ELF::R_AARCH64_NONE;
201  } else
202  return ELF::R_AARCH64_ABS64;
204  if (RefKind == AArch64MCExpr::VK_DTPREL_HI12)
205  return R_CLS(TLSLD_ADD_DTPREL_HI12);
206  if (RefKind == AArch64MCExpr::VK_TPREL_HI12)
207  return R_CLS(TLSLE_ADD_TPREL_HI12);
208  if (RefKind == AArch64MCExpr::VK_DTPREL_LO12_NC)
209  return R_CLS(TLSLD_ADD_DTPREL_LO12_NC);
210  if (RefKind == AArch64MCExpr::VK_DTPREL_LO12)
211  return R_CLS(TLSLD_ADD_DTPREL_LO12);
212  if (RefKind == AArch64MCExpr::VK_TPREL_LO12_NC)
213  return R_CLS(TLSLE_ADD_TPREL_LO12_NC);
214  if (RefKind == AArch64MCExpr::VK_TPREL_LO12)
215  return R_CLS(TLSLE_ADD_TPREL_LO12);
216  if (RefKind == AArch64MCExpr::VK_TLSDESC_LO12)
217  return R_CLS(TLSDESC_ADD_LO12);
218  if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
219  return R_CLS(ADD_ABS_LO12_NC);
220 
221  Ctx.reportError(Fixup.getLoc(),
222  "invalid fixup for add (uimm12) instruction");
223  return ELF::R_AARCH64_NONE;
225  if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
226  return R_CLS(LDST8_ABS_LO12_NC);
227  if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC)
228  return R_CLS(TLSLD_LDST8_DTPREL_LO12);
229  if (SymLoc == AArch64MCExpr::VK_DTPREL && IsNC)
230  return R_CLS(TLSLD_LDST8_DTPREL_LO12_NC);
231  if (SymLoc == AArch64MCExpr::VK_TPREL && !IsNC)
232  return R_CLS(TLSLE_LDST8_TPREL_LO12);
233  if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC)
234  return R_CLS(TLSLE_LDST8_TPREL_LO12_NC);
235 
236  Ctx.reportError(Fixup.getLoc(),
237  "invalid fixup for 8-bit load/store instruction");
238  return ELF::R_AARCH64_NONE;
240  if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
241  return R_CLS(LDST16_ABS_LO12_NC);
242  if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC)
243  return R_CLS(TLSLD_LDST16_DTPREL_LO12);
244  if (SymLoc == AArch64MCExpr::VK_DTPREL && IsNC)
245  return R_CLS(TLSLD_LDST16_DTPREL_LO12_NC);
246  if (SymLoc == AArch64MCExpr::VK_TPREL && !IsNC)
247  return R_CLS(TLSLE_LDST16_TPREL_LO12);
248  if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC)
249  return R_CLS(TLSLE_LDST16_TPREL_LO12_NC);
250 
251  Ctx.reportError(Fixup.getLoc(),
252  "invalid fixup for 16-bit load/store instruction");
253  return ELF::R_AARCH64_NONE;
255  if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
256  return R_CLS(LDST32_ABS_LO12_NC);
257  if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC)
258  return R_CLS(TLSLD_LDST32_DTPREL_LO12);
259  if (SymLoc == AArch64MCExpr::VK_DTPREL && IsNC)
260  return R_CLS(TLSLD_LDST32_DTPREL_LO12_NC);
261  if (SymLoc == AArch64MCExpr::VK_TPREL && !IsNC)
262  return R_CLS(TLSLE_LDST32_TPREL_LO12);
263  if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC)
264  return R_CLS(TLSLE_LDST32_TPREL_LO12_NC);
265  if (SymLoc == AArch64MCExpr::VK_GOT && IsNC) {
266  if (IsILP32) {
267  return ELF::R_AARCH64_P32_LD32_GOT_LO12_NC;
268  } else {
269  Ctx.reportError(Fixup.getLoc(),
270  "LP64 4 byte unchecked GOT load/store relocation "
271  "not supported (ILP32 eqv: LD32_GOT_LO12_NC");
272  return ELF::R_AARCH64_NONE;
273  }
274  }
275  if (SymLoc == AArch64MCExpr::VK_GOT && !IsNC) {
276  if (IsILP32) {
277  Ctx.reportError(Fixup.getLoc(),
278  "ILP32 4 byte checked GOT load/store relocation "
279  "not supported (unchecked eqv: LD32_GOT_LO12_NC)");
280  } else {
281  Ctx.reportError(Fixup.getLoc(),
282  "LP64 4 byte checked GOT load/store relocation "
283  "not supported (unchecked/ILP32 eqv: "
284  "LD32_GOT_LO12_NC)");
285  }
286  return ELF::R_AARCH64_NONE;
287  }
288  if (SymLoc == AArch64MCExpr::VK_GOTTPREL && IsNC) {
289  if (IsILP32) {
290  return ELF::R_AARCH64_P32_TLSIE_LD32_GOTTPREL_LO12_NC;
291  } else {
292  Ctx.reportError(Fixup.getLoc(),
293  "LP64 32-bit load/store "
294  "relocation not supported (ILP32 eqv: "
295  "TLSIE_LD32_GOTTPREL_LO12_NC)");
296  return ELF::R_AARCH64_NONE;
297  }
298  }
299  if (SymLoc == AArch64MCExpr::VK_TLSDESC && !IsNC) {
300  if (IsILP32) {
301  return ELF::R_AARCH64_P32_TLSDESC_LD32_LO12;
302  } else {
303  Ctx.reportError(Fixup.getLoc(),
304  "LP64 4 byte TLSDESC load/store relocation "
305  "not supported (ILP32 eqv: TLSDESC_LD64_LO12)");
306  return ELF::R_AARCH64_NONE;
307  }
308  }
309 
310  Ctx.reportError(Fixup.getLoc(),
311  "invalid fixup for 32-bit load/store instruction "
312  "fixup_aarch64_ldst_imm12_scale4");
313  return ELF::R_AARCH64_NONE;
315  if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
316  return R_CLS(LDST64_ABS_LO12_NC);
317  if (SymLoc == AArch64MCExpr::VK_GOT && IsNC) {
318  if (!IsILP32) {
319  return ELF::R_AARCH64_LD64_GOT_LO12_NC;
320  } else {
321  Ctx.reportError(Fixup.getLoc(), "ILP32 64-bit load/store "
322  "relocation not supported (LP64 eqv: "
323  "LD64_GOT_LO12_NC)");
324  return ELF::R_AARCH64_NONE;
325  }
326  }
327  if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC)
328  return R_CLS(TLSLD_LDST64_DTPREL_LO12);
329  if (SymLoc == AArch64MCExpr::VK_DTPREL && IsNC)
330  return R_CLS(TLSLD_LDST64_DTPREL_LO12_NC);
331  if (SymLoc == AArch64MCExpr::VK_TPREL && !IsNC)
332  return R_CLS(TLSLE_LDST64_TPREL_LO12);
333  if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC)
334  return R_CLS(TLSLE_LDST64_TPREL_LO12_NC);
335  if (SymLoc == AArch64MCExpr::VK_GOTTPREL && IsNC) {
336  if (!IsILP32) {
337  return ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC;
338  } else {
339  Ctx.reportError(Fixup.getLoc(), "ILP32 64-bit load/store "
340  "relocation not supported (LP64 eqv: "
341  "TLSIE_LD64_GOTTPREL_LO12_NC)");
342  return ELF::R_AARCH64_NONE;
343  }
344  }
345  if (SymLoc == AArch64MCExpr::VK_TLSDESC) {
346  if (!IsILP32) {
347  return ELF::R_AARCH64_TLSDESC_LD64_LO12;
348  } else {
349  Ctx.reportError(Fixup.getLoc(), "ILP32 64-bit load/store "
350  "relocation not supported (LP64 eqv: "
351  "TLSDESC_LD64_LO12)");
352  return ELF::R_AARCH64_NONE;
353  }
354  }
355  Ctx.reportError(Fixup.getLoc(),
356  "invalid fixup for 64-bit load/store instruction");
357  return ELF::R_AARCH64_NONE;
359  if (SymLoc == AArch64MCExpr::VK_ABS && IsNC)
360  return R_CLS(LDST128_ABS_LO12_NC);
361  if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC)
362  return R_CLS(TLSLD_LDST128_DTPREL_LO12);
363  if (SymLoc == AArch64MCExpr::VK_DTPREL && IsNC)
364  return R_CLS(TLSLD_LDST128_DTPREL_LO12_NC);
365  if (SymLoc == AArch64MCExpr::VK_TPREL && !IsNC)
366  return R_CLS(TLSLE_LDST128_TPREL_LO12);
367  if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC)
368  return R_CLS(TLSLE_LDST128_TPREL_LO12_NC);
369 
370  Ctx.reportError(Fixup.getLoc(),
371  "invalid fixup for 128-bit load/store instruction");
372  return ELF::R_AARCH64_NONE;
373  // ILP32 case not reached here, tested with isNonILP32reloc
375  if (RefKind == AArch64MCExpr::VK_ABS_G3)
376  return ELF::R_AARCH64_MOVW_UABS_G3;
377  if (RefKind == AArch64MCExpr::VK_ABS_G2)
378  return ELF::R_AARCH64_MOVW_UABS_G2;
379  if (RefKind == AArch64MCExpr::VK_ABS_G2_S)
380  return ELF::R_AARCH64_MOVW_SABS_G2;
381  if (RefKind == AArch64MCExpr::VK_ABS_G2_NC)
382  return ELF::R_AARCH64_MOVW_UABS_G2_NC;
383  if (RefKind == AArch64MCExpr::VK_ABS_G1)
384  return R_CLS(MOVW_UABS_G1);
385  if (RefKind == AArch64MCExpr::VK_ABS_G1_S)
386  return ELF::R_AARCH64_MOVW_SABS_G1;
387  if (RefKind == AArch64MCExpr::VK_ABS_G1_NC)
388  return ELF::R_AARCH64_MOVW_UABS_G1_NC;
389  if (RefKind == AArch64MCExpr::VK_ABS_G0)
390  return R_CLS(MOVW_UABS_G0);
391  if (RefKind == AArch64MCExpr::VK_ABS_G0_S)
392  return R_CLS(MOVW_SABS_G0);
393  if (RefKind == AArch64MCExpr::VK_ABS_G0_NC)
394  return R_CLS(MOVW_UABS_G0_NC);
395  if (RefKind == AArch64MCExpr::VK_DTPREL_G2)
396  return ELF::R_AARCH64_TLSLD_MOVW_DTPREL_G2;
397  if (RefKind == AArch64MCExpr::VK_DTPREL_G1)
398  return R_CLS(TLSLD_MOVW_DTPREL_G1);
399  if (RefKind == AArch64MCExpr::VK_DTPREL_G1_NC)
400  return ELF::R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC;
401  if (RefKind == AArch64MCExpr::VK_DTPREL_G0)
402  return R_CLS(TLSLD_MOVW_DTPREL_G0);
403  if (RefKind == AArch64MCExpr::VK_DTPREL_G0_NC)
404  return R_CLS(TLSLD_MOVW_DTPREL_G0_NC);
405  if (RefKind == AArch64MCExpr::VK_TPREL_G2)
406  return ELF::R_AARCH64_TLSLE_MOVW_TPREL_G2;
407  if (RefKind == AArch64MCExpr::VK_TPREL_G1)
408  return R_CLS(TLSLE_MOVW_TPREL_G1);
409  if (RefKind == AArch64MCExpr::VK_TPREL_G1_NC)
410  return ELF::R_AARCH64_TLSLE_MOVW_TPREL_G1_NC;
411  if (RefKind == AArch64MCExpr::VK_TPREL_G0)
412  return R_CLS(TLSLE_MOVW_TPREL_G0);
413  if (RefKind == AArch64MCExpr::VK_TPREL_G0_NC)
414  return R_CLS(TLSLE_MOVW_TPREL_G0_NC);
415  if (RefKind == AArch64MCExpr::VK_GOTTPREL_G1)
416  return ELF::R_AARCH64_TLSIE_MOVW_GOTTPREL_G1;
417  if (RefKind == AArch64MCExpr::VK_GOTTPREL_G0_NC)
418  return ELF::R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC;
419  Ctx.reportError(Fixup.getLoc(),
420  "invalid fixup for movz/movk instruction");
421  return ELF::R_AARCH64_NONE;
423  return R_CLS(TLSDESC_CALL);
424  default:
425  Ctx.reportError(Fixup.getLoc(), "Unknown ELF relocation type");
426  return ELF::R_AARCH64_NONE;
427  }
428  }
429 
430  llvm_unreachable("Unimplemented fixup -> relocation");
431 }
432 
433 std::unique_ptr<MCObjectTargetWriter>
434 llvm::createAArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32) {
435  return llvm::make_unique<AArch64ELFObjectWriter>(OSABI, IsILP32);
436 }
This class represents lattice values for constants.
Definition: AllocatorList.h:23
This represents an "assembler immediate".
Definition: MCValue.h:39
VariantKind getKind() const
Definition: MCExpr.h:337
#define BAD_ILP32_MOV(lp64rtype)
#define R_CLS(rtype)
block Block Frequency true
Encode information on a single operation to perform on a byte sequence (e.g., an encoded instruction)...
Definition: MCFixup.h:73
const MCSymbolRefExpr * getSymB() const
Definition: MCValue.h:48
static unsigned getRelocType(const MCValue &Target, const MCFixupKind FixupKind, const bool IsPCRel)
Translates generic PPC fixup kind to Mach-O/PPC relocation type enum.
A four-byte fixup.
Definition: MCFixup.h:25
Context object for machine code objects.
Definition: MCContext.h:62
const MCSymbolRefExpr * getSymA() const
Definition: MCValue.h:47
void reportError(SMLoc L, const Twine &Msg)
Definition: MCContext.cpp:611
std::unique_ptr< MCObjectTargetWriter > createAArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32)
static bool isNonILP32reloc(const MCFixup &Fixup, AArch64MCExpr::VariantKind RefKind, MCContext &Ctx)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
A one-byte fixup.
Definition: MCFixup.h:23
PowerPC TLS Dynamic Call Fixup
SMLoc getLoc() const
Definition: MCFixup.h:165
Target - Wrapper for Target specific information.
static bool isNotChecked(VariantKind Kind)
A eight-byte fixup.
Definition: MCFixup.h:26
uint32_t getRefKind() const
Definition: MCValue.h:49
static VariantKind getSymbolLoc(VariantKind Kind)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
A two-byte fixup.
Definition: MCFixup.h:24
MCFixupKind getKind() const
Definition: MCFixup.h:122