LLVM  8.0.0svn
Classes | Macros | Functions | Variables
AArch64ISelLowering.cpp File Reference
#include "AArch64ISelLowering.h"
#include "AArch64CallingConvention.h"
#include "AArch64MachineFunctionInfo.h"
#include "AArch64PerfectShuffle.h"
#include "AArch64RegisterInfo.h"
#include "AArch64Subtarget.h"
#include "MCTargetDesc/AArch64AddressingModes.h"
#include "Utils/AArch64BaseInfo.h"
#include "llvm/ADT/APFloat.h"
#include "llvm/ADT/APInt.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/StringSwitch.h"
#include "llvm/ADT/Triple.h"
#include "llvm/ADT/Twine.h"
#include "llvm/Analysis/VectorUtils.h"
#include "llvm/CodeGen/CallingConvLower.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RuntimeLibcalls.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/CodeGen/TargetCallingConv.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/GetElementPtrTypeIterator.h"
#include "llvm/IR/GlobalValue.h"
#include "llvm/IR/IRBuilder.h"
#include "llvm/IR/Instruction.h"
#include "llvm/IR/Instructions.h"
#include "llvm/IR/Intrinsics.h"
#include "llvm/IR/Module.h"
#include "llvm/IR/OperandTraits.h"
#include "llvm/IR/Type.h"
#include "llvm/IR/Use.h"
#include "llvm/IR/Value.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/KnownBits.h"
#include "llvm/Support/MachineValueType.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include <algorithm>
#include <bitset>
#include <cassert>
#include <cctype>
#include <cstdint>
#include <cstdlib>
#include <iterator>
#include <limits>
#include <tuple>
#include <utility>
#include <vector>
#include "AArch64GenCallingConv.inc"

Go to the source code of this file.

Classes

struct  GenericSetCCInfo
 Helper structure to keep track of ISD::SET_CC operands. More...
 
struct  AArch64SetCCInfo
 Helper structure to keep track of a SET_CC lowered into AArch64 code. More...
 
union  SetCCInfo
 Helper structure to keep track of SetCC information. More...
 
struct  SetCCInfoAndKind
 Helper structure to be able to read SetCC information. More...
 

Macros

#define DEBUG_TYPE   "aarch64-lower"
 

Functions

 STATISTIC (NumTailCalls, "Number of tail calls")
 
 STATISTIC (NumShiftInserts, "Number of vector shift inserts")
 
 STATISTIC (NumOptimizedImms, "Number of times immediates were optimized")
 
static bool optimizeLogicalImm (SDValue Op, unsigned Size, uint64_t Imm, const APInt &Demanded, TargetLowering::TargetLoweringOpt &TLO, unsigned NewOpc)
 
static AArch64CC::CondCode changeIntCCToAArch64CC (ISD::CondCode CC)
 changeIntCCToAArch64CC - Convert a DAG integer condition code to an AArch64 CC More...
 
static void changeFPCCToAArch64CC (ISD::CondCode CC, AArch64CC::CondCode &CondCode, AArch64CC::CondCode &CondCode2)
 changeFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64 CC. More...
 
static void changeFPCCToANDAArch64CC (ISD::CondCode CC, AArch64CC::CondCode &CondCode, AArch64CC::CondCode &CondCode2)
 Convert a DAG fp condition code to an AArch64 CC. More...
 
static void changeVectorFPCCToAArch64CC (ISD::CondCode CC, AArch64CC::CondCode &CondCode, AArch64CC::CondCode &CondCode2, bool &Invert)
 changeVectorFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64 CC usable with the vector instructions. More...
 
static bool isLegalArithImmed (uint64_t C)
 
static bool isCMN (SDValue Op, ISD::CondCode CC)
 
static SDValue emitComparison (SDValue LHS, SDValue RHS, ISD::CondCode CC, const SDLoc &dl, SelectionDAG &DAG)
 
static SDValue emitConditionalComparison (SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue CCOp, AArch64CC::CondCode Predicate, AArch64CC::CondCode OutCC, const SDLoc &DL, SelectionDAG &DAG)
 Create a conditional comparison; Use CCMP, CCMN or FCCMP as appropriate. More...
 
static bool canEmitConjunction (const SDValue Val, bool &CanNegate, unsigned Depth=0)
 Returns true if Val is a tree of AND/OR/SETCC operations that can be expressed as a conjunction. More...
 
static SDValue emitConjunctionRec (SelectionDAG &DAG, SDValue Val, AArch64CC::CondCode &OutCC, bool Negate, SDValue CCOp, AArch64CC::CondCode Predicate)
 Emit conjunction or disjunction tree with the CMP/FCMP followed by a chain of CCMP/CFCMP ops. More...
 
static SDValue emitConjunction (SelectionDAG &DAG, SDValue Val, AArch64CC::CondCode &OutCC)
 Emit expression as a conjunction (a series of CCMP/CFCMP ops). More...
 
static unsigned getCmpOperandFoldingProfit (SDValue Op)
 Returns how profitable it is to fold a comparison's operand's shift and/or extension operations. More...
 
static SDValue getAArch64Cmp (SDValue LHS, SDValue RHS, ISD::CondCode CC, SDValue &AArch64cc, SelectionDAG &DAG, const SDLoc &dl)
 
static std::pair< SDValue, SDValuegetAArch64XALUOOp (AArch64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG)
 
static bool isOverflowIntrOpRes (SDValue Op)
 
static SDValue LowerXOR (SDValue Op, SelectionDAG &DAG)
 
static SDValue LowerADDC_ADDE_SUBC_SUBE (SDValue Op, SelectionDAG &DAG)
 
static SDValue LowerXALUO (SDValue Op, SelectionDAG &DAG)
 
static SDValue LowerPREFETCH (SDValue Op, SelectionDAG &DAG)
 
static SDValue LowerVectorFP_TO_INT (SDValue Op, SelectionDAG &DAG)
 
static SDValue LowerVectorINT_TO_FP (SDValue Op, SelectionDAG &DAG)
 
static SDValue LowerBITCAST (SDValue Op, SelectionDAG &DAG)
 
static EVT getExtensionTo64Bits (const EVT &OrigVT)
 
static SDValue addRequiredExtensionForVectorMULL (SDValue N, SelectionDAG &DAG, const EVT &OrigTy, const EVT &ExtTy, unsigned ExtOpcode)
 
static bool isExtendedBUILD_VECTOR (SDNode *N, SelectionDAG &DAG, bool isSigned)
 
static SDValue skipExtensionForVectorMULL (SDNode *N, SelectionDAG &DAG)
 
static bool isSignExtended (SDNode *N, SelectionDAG &DAG)
 
static bool isZeroExtended (SDNode *N, SelectionDAG &DAG)
 
static bool isAddSubSExt (SDNode *N, SelectionDAG &DAG)
 
static bool isAddSubZExt (SDNode *N, SelectionDAG &DAG)
 
static SDValue LowerMUL (SDValue Op, SelectionDAG &DAG)
 
static SDValue LowerMULH (SDValue Op, SelectionDAG &DAG)
 
static SDValue LowerTruncateVectorStore (SDLoc DL, StoreSDNode *ST, EVT VT, EVT MemVT, SelectionDAG &DAG)
 
static bool canGuaranteeTCO (CallingConv::ID CC)
 Return true if the calling convention is one that we can guarantee TCO for. More...
 
static bool mayTailCallThisCC (CallingConv::ID CC)
 Return true if we might ever do TCO for calls with this calling convention. More...
 
static SDValue getEstimate (const AArch64Subtarget *ST, unsigned Opcode, SDValue Operand, SelectionDAG &DAG, int &ExtraSteps)
 
static SDValue WidenVector (SDValue V64Reg, SelectionDAG &DAG)
 WidenVector - Given a value in the V64 register class, produce the equivalent value in the V128 register class. More...
 
static unsigned getExtFactor (SDValue &V)
 getExtFactor - Determine the adjustment factor for the position when generating an "extract from vector registers" instruction. More...
 
static SDValue NarrowVector (SDValue V128Reg, SelectionDAG &DAG)
 NarrowVector - Given a value in the V128 register class, produce the equivalent value in the V64 register class. More...
 
static bool isSingletonEXTMask (ArrayRef< int > M, EVT VT, unsigned &Imm)
 
static bool isEXTMask (ArrayRef< int > M, EVT VT, bool &ReverseEXT, unsigned &Imm)
 
static bool isREVMask (ArrayRef< int > M, EVT VT, unsigned BlockSize)
 isREVMask - Check if a vector shuffle corresponds to a REV instruction with the specified blocksize. More...
 
static bool isZIPMask (ArrayRef< int > M, EVT VT, unsigned &WhichResult)
 
static bool isUZPMask (ArrayRef< int > M, EVT VT, unsigned &WhichResult)
 
static bool isTRNMask (ArrayRef< int > M, EVT VT, unsigned &WhichResult)
 
static bool isZIP_v_undef_Mask (ArrayRef< int > M, EVT VT, unsigned &WhichResult)
 isZIP_v_undef_Mask - Special case of isZIPMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef". More...
 
static bool isUZP_v_undef_Mask (ArrayRef< int > M, EVT VT, unsigned &WhichResult)
 isUZP_v_undef_Mask - Special case of isUZPMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef". More...
 
static bool isTRN_v_undef_Mask (ArrayRef< int > M, EVT VT, unsigned &WhichResult)
 isTRN_v_undef_Mask - Special case of isTRNMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef". More...
 
static bool isINSMask (ArrayRef< int > M, int NumInputElements, bool &DstIsLeft, int &Anomaly)
 
static bool isConcatMask (ArrayRef< int > Mask, EVT VT, bool SplitLHS)
 
static SDValue tryFormConcatFromShuffle (SDValue Op, SelectionDAG &DAG)
 
static SDValue GeneratePerfectShuffle (unsigned PFEntry, SDValue LHS, SDValue RHS, SelectionDAG &DAG, const SDLoc &dl)
 GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit the specified operations to build the shuffle. More...
 
static SDValue GenerateTBL (SDValue Op, ArrayRef< int > ShuffleMask, SelectionDAG &DAG)
 
static unsigned getDUPLANEOp (EVT EltType)
 
static bool resolveBuildVector (BuildVectorSDNode *BVN, APInt &CnstBits, APInt &UndefBits)
 
static SDValue tryAdvSIMDModImm64 (unsigned NewOp, SDValue Op, SelectionDAG &DAG, const APInt &Bits)
 
static SDValue tryAdvSIMDModImm32 (unsigned NewOp, SDValue Op, SelectionDAG &DAG, const APInt &Bits, const SDValue *LHS=nullptr)
 
static SDValue tryAdvSIMDModImm16 (unsigned NewOp, SDValue Op, SelectionDAG &DAG, const APInt &Bits, const SDValue *LHS=nullptr)
 
static SDValue tryAdvSIMDModImm321s (unsigned NewOp, SDValue Op, SelectionDAG &DAG, const APInt &Bits)
 
static SDValue tryAdvSIMDModImm8 (unsigned NewOp, SDValue Op, SelectionDAG &DAG, const APInt &Bits)
 
static SDValue tryAdvSIMDModImmFP (unsigned NewOp, SDValue Op, SelectionDAG &DAG, const APInt &Bits)
 
static bool isAllConstantBuildVector (const SDValue &PotentialBVec, uint64_t &ConstVal)
 
static unsigned getIntrinsicID (const SDNode *N)
 
static SDValue tryLowerToSLI (SDNode *N, SelectionDAG &DAG)
 
static SDValue NormalizeBuildVector (SDValue Op, SelectionDAG &DAG)
 
static SDValue ConstantBuildVector (SDValue Op, SelectionDAG &DAG)
 
static bool getVShiftImm (SDValue Op, unsigned ElementBits, int64_t &Cnt)
 getVShiftImm - Check if this is a valid build_vector for the immediate operand of a vector shift operation, where all the elements of the build_vector must have the same constant integer value. More...
 
static bool isVShiftLImm (SDValue Op, EVT VT, bool isLong, int64_t &Cnt)
 isVShiftLImm - Check if this is a valid build_vector for the immediate operand of a vector shift left operation. More...
 
static bool isVShiftRImm (SDValue Op, EVT VT, bool isNarrow, int64_t &Cnt)
 isVShiftRImm - Check if this is a valid build_vector for the immediate operand of a vector shift right operation. More...
 
static SDValue EmitVectorComparison (SDValue LHS, SDValue RHS, AArch64CC::CondCode CC, bool NoNans, EVT VT, const SDLoc &dl, SelectionDAG &DAG)
 
static SDValue getReductionSDNode (unsigned Op, SDLoc DL, SDValue ScalarOp, SelectionDAG &DAG)
 
static bool memOpAlign (unsigned DstAlign, unsigned SrcAlign, unsigned AlignCheck)
 
static SDValue foldVectorXorShiftIntoCmp (SDNode *N, SelectionDAG &DAG, const AArch64Subtarget *Subtarget)
 Turn vector tests of the signbit in the form of: xor (sra X, elt_size(X)-1), -1 into: cmge X, X, #0. More...
 
static SDValue performIntegerAbsCombine (SDNode *N, SelectionDAG &DAG)
 
static SDValue performXorCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget)
 
static SDValue performMulCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget)
 
static SDValue performVectorCompareAndMaskUnaryOpCombine (SDNode *N, SelectionDAG &DAG)
 
static SDValue performIntToFpCombine (SDNode *N, SelectionDAG &DAG, const AArch64Subtarget *Subtarget)
 
static SDValue performFpToIntCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget)
 Fold a floating-point multiply by power of two into floating-point to fixed-point conversion. More...
 
static SDValue performFDivCombine (SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget)
 Fold a floating-point divide by power of two into fixed-point to floating-point conversion. More...
 
static bool findEXTRHalf (SDValue N, SDValue &Src, uint32_t &ShiftAmount, bool &FromHi)
 An EXTR instruction is made up of two shifts, ORed together. More...
 
static SDValue tryCombineToEXTR (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
 EXTR instruction extracts a contiguous chunk of bits from two existing registers viewed as a high/low pair. More...
 
static SDValue tryCombineToBSL (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
 
static SDValue performORCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget)
 
static SDValue performSRLCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
 
static SDValue performBitcastCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG)
 
static SDValue performConcatVectorsCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG)
 
static SDValue tryCombineFixedPointConvert (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG)
 
static SDValue tryExtendDUPToExtractHigh (SDValue N, SelectionDAG &DAG)
 
static bool isEssentiallyExtractSubvector (SDValue N)
 
static bool isSetCC (SDValue Op, SetCCInfoAndKind &SetCCInfo)
 Check whether or not Op is a SET_CC operation, either a generic or an AArch64 lowered one. More...
 
static bool isSetCCOrZExtSetCC (const SDValue &Op, SetCCInfoAndKind &Info)
 
static SDValue performSetccAddFolding (SDNode *Op, SelectionDAG &DAG)
 
static SDValue performAddSubLongCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG)
 
static SDValue tryCombineLongOpWithDup (unsigned IID, SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG)
 
static SDValue tryCombineShiftImm (unsigned IID, SDNode *N, SelectionDAG &DAG)
 
static SDValue tryCombineCRC32 (unsigned Mask, SDNode *N, SelectionDAG &DAG)
 
static SDValue combineAcrossLanesIntrinsic (unsigned Opc, SDNode *N, SelectionDAG &DAG)
 
static SDValue performIntrinsicCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget)
 
static SDValue performExtendCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG)
 
static SDValue splitStoreSplat (SelectionDAG &DAG, StoreSDNode &St, SDValue SplatVal, unsigned NumVecElts)
 
static SDValue replaceZeroVectorStore (SelectionDAG &DAG, StoreSDNode &St)
 Replace a splat of zeros to a vector store by scalar stores of WZR/XZR. More...
 
static SDValue replaceSplatVectorStore (SelectionDAG &DAG, StoreSDNode &St)
 Replace a splat of a scalar to a vector store by scalar stores of the scalar value. More...
 
static SDValue splitStores (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG, const AArch64Subtarget *Subtarget)
 
static SDValue performPostLD1Combine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, bool IsLaneOp)
 Target-specific DAG combine function for post-increment LD1 (lane) and post-increment LD1R. More...
 
static bool performTBISimplification (SDValue Addr, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG)
 Simplify Addr given that the top byte of it is ignored by HW during address translation. More...
 
static SDValue performSTORECombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG, const AArch64Subtarget *Subtarget)
 
static SDValue performNEONPostLDSTCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG)
 Target-specific DAG combine function for NEON load/store intrinsics to merge base address updates. More...
 
static bool checkValueWidth (SDValue V, unsigned width, ISD::LoadExtType &ExtType)
 
static bool isEquivalentMaskless (unsigned CC, unsigned width, ISD::LoadExtType ExtType, int AddConstant, int CompConstant)
 
static SDValue performCONDCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG, unsigned CCIndex, unsigned CmpIndex)
 
static SDValue performBRCONDCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG)
 
static SDValue getTestBitOperand (SDValue Op, unsigned &Bit, bool &Invert, SelectionDAG &DAG)
 
static SDValue performTBZCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG)
 
static SDValue performVSelectCombine (SDNode *N, SelectionDAG &DAG)
 
static SDValue performSelectCombine (SDNode *N, TargetLowering::DAGCombinerInfo &DCI)
 A vector select: "(select vL, vR, (setcc LHS, RHS))" is best performed with the compare-mask instructions rather than going via NZCV, even if LHS and RHS are really scalar. More...
 
static SDValue performNVCASTCombine (SDNode *N)
 Get rid of unnecessary NVCASTs (that don't change the type). More...
 
static SDValue performGlobalAddressCombine (SDNode *N, SelectionDAG &DAG, const AArch64Subtarget *Subtarget, const TargetMachine &TM)
 
static void ReplaceBITCASTResults (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG)
 
static void ReplaceReductionResults (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG, unsigned InterOp, unsigned AcrossOp)
 
static std::pair< SDValue, SDValuesplitInt128 (SDValue N, SelectionDAG &DAG)
 
static SDValue createGPRPairNode (SelectionDAG &DAG, SDValue V)
 
static void ReplaceCMP_SWAP_128Results (SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG, const AArch64Subtarget *Subtarget)
 
static ValueUseTlsOffset (IRBuilder<> &IRB, unsigned Offset)
 

Variables

static cl::opt< boolEnableAArch64SlrGeneration ("aarch64-shift-insert-generation", cl::Hidden, cl::desc("Allow AArch64 SLI/SRI formation"), cl::init(false))
 
cl::opt< boolEnableAArch64ELFLocalDynamicTLSGeneration ("aarch64-elf-ldtls-generation", cl::Hidden, cl::desc("Allow AArch64 Local Dynamic TLS code generation"), cl::init(false))
 
static cl::opt< boolEnableOptimizeLogicalImm ("aarch64-enable-logical-imm", cl::Hidden, cl::desc("Enable AArch64 logical imm instruction " "optimization"), cl::init(true))
 
static const MVT MVT_CC = MVT::i32
 Value type used for condition codes. More...
 

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE   "aarch64-lower"

Definition at line 91 of file AArch64ISelLowering.cpp.

Function Documentation

◆ addRequiredExtensionForVectorMULL()

static SDValue addRequiredExtensionForVectorMULL ( SDValue  N,
SelectionDAG DAG,
const EVT OrigTy,
const EVT ExtTy,
unsigned  ExtOpcode 
)
static

◆ canGuaranteeTCO()

static bool canGuaranteeTCO ( CallingConv::ID  CC)
static

Return true if the calling convention is one that we can guarantee TCO for.

Definition at line 3349 of file AArch64ISelLowering.cpp.

References llvm::CallingConv::Fast.

Referenced by mayTailCallThisCC().

◆ changeFPCCToAArch64CC()

static void changeFPCCToAArch64CC ( ISD::CondCode  CC,
AArch64CC::CondCode CondCode,
AArch64CC::CondCode CondCode2 
)
static

◆ changeFPCCToANDAArch64CC()

static void changeFPCCToANDAArch64CC ( ISD::CondCode  CC,
AArch64CC::CondCode CondCode,
AArch64CC::CondCode CondCode2 
)
static

Convert a DAG fp condition code to an AArch64 CC.

This differs from changeFPCCToAArch64CC in that it returns cond codes that should be AND'ed instead of OR'ed.

Definition at line 1414 of file AArch64ISelLowering.cpp.

References llvm::AArch64CC::AL, assert(), changeFPCCToAArch64CC(), llvm::AArch64CC::LE, llvm::AArch64CC::NE, llvm::AArch64CC::PL, llvm::ISD::SETONE, llvm::ISD::SETUEQ, and llvm::AArch64CC::VC.

Referenced by emitConjunctionRec().

◆ changeIntCCToAArch64CC()

static AArch64CC::CondCode changeIntCCToAArch64CC ( ISD::CondCode  CC)
static

◆ changeVectorFPCCToAArch64CC()

static void changeVectorFPCCToAArch64CC ( ISD::CondCode  CC,
AArch64CC::CondCode CondCode,
AArch64CC::CondCode CondCode2,
bool Invert 
)
static

changeVectorFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64 CC usable with the vector instructions.

Fewer operations are available without a real NZCV register, so we have to use less efficient combinations to get the same effect.

Definition at line 1444 of file AArch64ISelLowering.cpp.

References changeFPCCToAArch64CC(), llvm::AArch64CC::GE, llvm::ISD::getSetCCInverse(), LLVM_FALLTHROUGH, llvm::AArch64CC::MI, llvm::ISD::SETO, llvm::ISD::SETUEQ, llvm::ISD::SETUGE, llvm::ISD::SETUGT, llvm::ISD::SETULE, llvm::ISD::SETULT, and llvm::ISD::SETUO.

Referenced by EmitVectorComparison().

◆ checkValueWidth()

static bool checkValueWidth ( SDValue  V,
unsigned  width,
ISD::LoadExtType ExtType 
)
static

◆ combineAcrossLanesIntrinsic()

static SDValue combineAcrossLanesIntrinsic ( unsigned  Opc,
SDNode N,
SelectionDAG DAG 
)
static

◆ ConstantBuildVector()

static SDValue ConstantBuildVector ( SDValue  Op,
SelectionDAG DAG 
)
static

Definition at line 7144 of file AArch64ISelLowering.cpp.

References assert(), llvm::ISD::BITCAST, llvm::dbgs(), llvm::AArch64ISD::DUP, llvm::dyn_cast(), llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::AArch64ISD::FMOV, llvm::SelectionDAG::getBuildVector(), llvm::SelectionDAG::getConstant(), llvm::SDNode::getConstantOperandVal(), llvm::BuildVectorSDNode::getConstantSplatNode(), llvm::SelectionDAG::getContext(), getDUPLANEOp(), llvm::MVT::getIntegerVT(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getSplatBuildVector(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::EVT::getVectorVT(), llvm::SelectionDAG::getVTList(), llvm::ConstantSDNode::getZExtValue(), llvm::MVT::i64, llvm::ISD::INSERT_VECTOR_ELT, isConstant(), llvm::BuildVectorSDNode::isConstant(), llvm::EVT::isFloatingPoint(), llvm::EVT::isInteger(), llvm::SDValue::isUndef(), LLVM_DEBUG, llvm::AArch64ISD::MOVI, llvm::AArch64ISD::MOVIedit, llvm::AArch64ISD::MOVImsl, llvm::AArch64ISD::MOVIshift, llvm::AArch64ISD::MVNImsl, llvm::AArch64ISD::MVNIshift, NormalizeBuildVector(), llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::AArch64TargetLowering::ReconstructShuffle(), llvm::SelectionDAG::ReplaceAllUsesWith(), resolveBuildVector(), llvm::ISD::SCALAR_TO_VECTOR, tryAdvSIMDModImm16(), tryAdvSIMDModImm32(), tryAdvSIMDModImm321s(), tryAdvSIMDModImm64(), tryAdvSIMDModImm8(), tryAdvSIMDModImmFP(), llvm::AArch64ISD::UZP1, llvm::AArch64ISD::UZP2, llvm::MVT::v16i8, llvm::MVT::v1i64, llvm::MVT::v2f32, llvm::MVT::v2f64, llvm::MVT::v2i32, llvm::MVT::v2i64, llvm::MVT::v4f16, llvm::MVT::v4f32, llvm::MVT::v4i16, llvm::MVT::v4i32, llvm::MVT::v8f16, llvm::MVT::v8i16, llvm::MVT::v8i8, and WidenVector().

◆ createGPRPairNode()

static SDValue createGPRPairNode ( SelectionDAG DAG,
SDValue  V 
)
static

◆ emitComparison()

static SDValue emitComparison ( SDValue  LHS,
SDValue  RHS,
ISD::CondCode  CC,
const SDLoc dl,
SelectionDAG DAG 
)
static

◆ EmitVectorComparison()

static SDValue EmitVectorComparison ( SDValue  LHS,
SDValue  RHS,
AArch64CC::CondCode  CC,
bool  NoNans,
EVT  VT,
const SDLoc dl,
SelectionDAG DAG 
)
static

Definition at line 7691 of file AArch64ISelLowering.cpp.

References llvm::AArch64CC::AL, assert(), changeIntCCToAArch64CC(), llvm::EVT::changeVectorElementTypeToInteger(), changeVectorFPCCToAArch64CC(), llvm::AArch64ISD::CMEQ, llvm::AArch64ISD::CMEQz, llvm::AArch64ISD::CMGE, llvm::AArch64ISD::CMGEz, llvm::AArch64ISD::CMGT, llvm::AArch64ISD::CMGTz, llvm::AArch64ISD::CMHI, llvm::AArch64ISD::CMHS, llvm::AArch64ISD::CMLEz, llvm::AArch64ISD::CMLTz, llvm::dyn_cast(), llvm::AArch64CC::EQ, llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::AArch64ISD::FCMEQ, llvm::AArch64ISD::FCMEQz, llvm::AArch64ISD::FCMGE, llvm::AArch64ISD::FCMGEz, llvm::AArch64ISD::FCMGT, llvm::AArch64ISD::FCMGTz, llvm::AArch64ISD::FCMLEz, llvm::AArch64ISD::FCMLTz, llvm::ISD::FP_EXTEND, llvm::AArch64CC::GE, llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getNOT(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getSetCC(), llvm::SelectionDAG::getSExtOrTrunc(), llvm::EVT::getSizeInBits(), llvm::SelectionDAG::getSubtarget(), llvm::TargetLoweringBase::getTargetMachine(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::AArch64CC::GT, llvm::AArch64CC::HI, llvm::AArch64CC::HS, llvm::EVT::isFloatingPoint(), llvm::EVT::isInteger(), llvm::AArch64CC::LE, LLVM_FALLTHROUGH, llvm::AArch64CC::LO, llvm::AArch64CC::LS, llvm::AArch64CC::LT, llvm::AArch64CC::MI, llvm::AArch64CC::NE, llvm::bitc::NoNaNs, llvm::TargetOptions::NoNaNsFPMath, llvm::AArch64ISD::NOT, llvm::TargetMachine::Options, llvm::ISD::OR, llvm::SelectionDAG::ReplaceAllUsesWith(), resolveBuildVector(), llvm::MVT::v4f32, llvm::MVT::v4i16, and llvm::MVT::v4i32.

◆ findEXTRHalf()

static bool findEXTRHalf ( SDValue  N,
SDValue Src,
uint32_t ShiftAmount,
bool FromHi 
)
static

An EXTR instruction is made up of two shifts, ORed together.

This helper searches for and classifies those shifts.

Definition at line 9204 of file AArch64ISelLowering.cpp.

References llvm::SDNode::getConstantOperandVal(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::ISD::SHL, and llvm::ISD::SRL.

Referenced by tryCombineToEXTR().

◆ foldVectorXorShiftIntoCmp()

static SDValue foldVectorXorShiftIntoCmp ( SDNode N,
SelectionDAG DAG,
const AArch64Subtarget Subtarget 
)
static

◆ GeneratePerfectShuffle()

static SDValue GeneratePerfectShuffle ( unsigned  PFEntry,
SDValue  LHS,
SDValue  RHS,
SelectionDAG DAG,
const SDLoc dl 
)
static

◆ GenerateTBL()

static SDValue GenerateTBL ( SDValue  Op,
ArrayRef< int >  ShuffleMask,
SelectionDAG DAG 
)
static

◆ getAArch64Cmp()

static SDValue getAArch64Cmp ( SDValue  LHS,
SDValue  RHS,
ISD::CondCode  CC,
SDValue AArch64cc,
SelectionDAG DAG,
const SDLoc dl 
)
static

◆ getAArch64XALUOOp()

static std::pair<SDValue, SDValue> getAArch64XALUOOp ( AArch64CC::CondCode CC,
SDValue  Op,
SelectionDAG DAG 
)
static

◆ getCmpOperandFoldingProfit()

static unsigned getCmpOperandFoldingProfit ( SDValue  Op)
static

◆ getDUPLANEOp()

static unsigned getDUPLANEOp ( EVT  EltType)
static

Definition at line 6550 of file AArch64ISelLowering.cpp.

References llvm::ISD::BUILD_VECTOR, Concat, llvm::ISD::CONCAT_VECTORS, llvm::AArch64ISD::DUP, llvm::AArch64ISD::DUPLANE16, llvm::AArch64ISD::DUPLANE32, llvm::AArch64ISD::DUPLANE64, llvm::AArch64ISD::DUPLANE8, llvm::AArch64ISD::EXT, llvm::ISD::EXTRACT_SUBVECTOR, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, GeneratePerfectShuffle(), GenerateTBL(), llvm::SelectionDAG::getConstant(), getExtFactor(), llvm::ShuffleVectorSDNode::getMask(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getSizeInBits(), llvm::ShuffleVectorSDNode::getSplatIndex(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::ISD::INSERT_VECTOR_ELT, isEXTMask(), isINSMask(), llvm::EVT::isInteger(), isREVMask(), isSingletonEXTMask(), llvm::ShuffleVectorSDNode::isSplat(), isTRN_v_undef_Mask(), isTRNMask(), llvm::SDNode::isUndef(), isUZP_v_undef_Mask(), isUZPMask(), isZIP_v_undef_Mask(), isZIPMask(), llvm_unreachable, PerfectShuffleTable, llvm::AArch64ISD::REV16, llvm::AArch64ISD::REV32, llvm::AArch64ISD::REV64, llvm::ISD::SCALAR_TO_VECTOR, std::swap(), llvm::AArch64ISD::TRN1, llvm::AArch64ISD::TRN2, tryFormConcatFromShuffle(), llvm::AArch64ISD::UZP1, llvm::AArch64ISD::UZP2, llvm::NVPTX::PTXLdStInstCode::V2, WidenVector(), llvm::AArch64ISD::ZIP1, and llvm::AArch64ISD::ZIP2.

Referenced by ConstantBuildVector().

◆ getEstimate()

static SDValue getEstimate ( const AArch64Subtarget ST,
unsigned  Opcode,
SDValue  Operand,
SelectionDAG DAG,
int &  ExtraSteps 
)
static

Definition at line 5444 of file AArch64ISelLowering.cpp.

References C, llvm::TargetLowering::C_Memory, llvm::TargetLowering::C_Other, llvm::TargetLowering::C_RegisterClass, llvm::TargetLowering::CW_Constant, llvm::TargetLowering::CW_Default, llvm::TargetLowering::CW_Invalid, llvm::TargetLowering::CW_Register, llvm::dyn_cast(), Enabled, llvm::TargetLoweringBase::Enabled, llvm::StringRef::equals_lower(), llvm::MVT::f32, llvm::MVT::f64, llvm::Failed(), llvm::ISD::FMUL, llvm::AArch64ISD::FRECPE, llvm::AArch64ISD::FRECPS, llvm::AArch64ISD::FRSQRTE, llvm::AArch64ISD::FRSQRTS, llvm::StringRef::getAsInteger(), llvm::SelectionDAG::getConstantFP(), llvm::TargetLowering::getConstraintType(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getDataLayout(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::TargetLowering::getRegForInlineAsmConstraint(), llvm::SelectionDAG::getRegister(), llvm::EVT::getScalarType(), llvm::SelectionDAG::getSetCC(), llvm::AArch64TargetLowering::getSetCCResultType(), llvm::ConstantSDNode::getSExtValue(), llvm::TargetLowering::getSingleConstraintMatchWeight(), llvm::EVT::getSizeInBits(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getTargetBlockAddress(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetExternalSymbol(), llvm::SelectionDAG::getTargetGlobalAddress(), llvm::Value::getType(), llvm::SDValue::getValueType(), llvm::ConstantSDNode::getZExtValue(), llvm::AArch64Subtarget::hasFPARMv8(), llvm::AArch64Subtarget::hasNEON(), llvm::MVT::i32, llvm::MVT::i64, info, llvm::EVT::isFloatingPoint(), llvm::Type::isFloatingPointTy(), llvm::AArch64_AM::isLogicalImmediate(), llvm::isNullConstant(), llvm::isUInt< 32 >(), llvm::EVT::isVector(), llvm::Type::isVectorTy(), llvm::TargetLowering::LowerAsmOperandForConstraint(), llvm::MVT::Other, llvm::ISD::SELECT, llvm::SDNodeFlags::setAllowReassociation(), llvm::ISD::SETEQ, Size, llvm::StringRef::size(), llvm::StringRef::slice(), TRI, llvm::AArch64Subtarget::useRSqrt(), llvm::MVT::v1f32, llvm::MVT::v1f64, llvm::MVT::v2f32, llvm::MVT::v2f64, llvm::MVT::v4f32, and llvm::ISD::VSELECT.

◆ getExtensionTo64Bits()

static EVT getExtensionTo64Bits ( const EVT OrigVT)
static

◆ getExtFactor()

static unsigned getExtFactor ( SDValue V)
static

getExtFactor - Determine the adjustment factor for the position when generating an "extract from vector registers" instruction.

Definition at line 5880 of file AArch64ISelLowering.cpp.

References llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), and llvm::EVT::getVectorElementType().

Referenced by GeneratePerfectShuffle(), getDUPLANEOp(), and llvm::AArch64TargetLowering::ReconstructShuffle().

◆ getIntrinsicID()

static unsigned getIntrinsicID ( const SDNode N)
static

◆ getReductionSDNode()

static SDValue getReductionSDNode ( unsigned  Op,
SDLoc  DL,
SDValue  ScalarOp,
SelectionDAG DAG 
)
static

Definition at line 7850 of file AArch64ISelLowering.cpp.

References assert(), llvm::ISD::ATOMIC_LOAD_ADD, llvm::ISD::ATOMIC_LOAD_CLR, llvm::AArch64ISD::CALL, llvm::ISD::EXTRACT_VECTOR_ELT, llvm::SelectionDAG::getAtomic(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getCopyToReg(), llvm::SelectionDAG::getDataLayout(), llvm::SDNode::getFlags(), llvm::SelectionDAG::getMachineFunction(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::TargetLoweringBase::getPointerTy(), llvm::SelectionDAG::getRegister(), llvm::SelectionDAG::getRegisterMask(), llvm::SDValue::getSimpleValueType(), llvm::SelectionDAG::getSubtarget(), llvm::SelectionDAG::getTargetExternalSymbol(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::SelectionDAG::getVTList(), llvm::AArch64RegisterInfo::getWindowsStackProbePreservedMask(), llvm::MVT::Glue, llvm::SDNodeFlags::hasNoNaNs(), llvm::MVT::i32, llvm::MVT::i64, llvm::ISD::INTRINSIC_WO_CHAIN, llvm_unreachable, llvm::BitmaskEnumDetail::Mask(), llvm::MVT::Other, llvm::ISD::SHL, Size, llvm::AArch64ISD::SMAXV, llvm::AArch64ISD::SMINV, llvm::ISD::SRL, llvm::ISD::SUB, llvm::AArch64ISD::UADDV, llvm::AArch64ISD::UMAXV, llvm::AArch64ISD::UMINV, llvm::AArch64RegisterInfo::UpdateCustomCallPreservedMask(), llvm::ISD::VECREDUCE_ADD, llvm::ISD::VECREDUCE_FMAX, llvm::ISD::VECREDUCE_FMIN, llvm::ISD::VECREDUCE_SMAX, llvm::ISD::VECREDUCE_SMIN, llvm::ISD::VECREDUCE_UMAX, llvm::ISD::VECREDUCE_UMIN, and llvm::ISD::XOR.

◆ getTestBitOperand()

static SDValue getTestBitOperand ( SDValue  Op,
unsigned Bit,
bool Invert,
SelectionDAG DAG 
)
static

◆ getVShiftImm()

static bool getVShiftImm ( SDValue  Op,
unsigned  ElementBits,
int64_t &  Cnt 
)
static

getVShiftImm - Check if this is a valid build_vector for the immediate operand of a vector shift operation, where all the elements of the build_vector must have the same constant integer value.

Definition at line 7603 of file AArch64ISelLowering.cpp.

References llvm::ISD::BITCAST, llvm::dyn_cast(), llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::APInt::getSExtValue(), and llvm::BuildVectorSDNode::isConstantSplat().

Referenced by isVShiftLImm(), and isVShiftRImm().

◆ isAddSubSExt()

static bool isAddSubSExt ( SDNode N,
SelectionDAG DAG 
)
static

◆ isAddSubZExt()

static bool isAddSubZExt ( SDNode N,
SelectionDAG DAG 
)
static

◆ isAllConstantBuildVector()

static bool isAllConstantBuildVector ( const SDValue PotentialBVec,
uint64_t &  ConstVal 
)
static

◆ isCMN()

static bool isCMN ( SDValue  Op,
ISD::CondCode  CC 
)
static

◆ isConcatMask()

static bool isConcatMask ( ArrayRef< int >  Mask,
EVT  VT,
bool  SplitLHS 
)
static

◆ isEquivalentMaskless()

static bool isEquivalentMaskless ( unsigned  CC,
unsigned  width,
ISD::LoadExtType  ExtType,
int  AddConstant,
int  CompConstant 
)
static

◆ isEssentiallyExtractSubvector()

static bool isEssentiallyExtractSubvector ( SDValue  N)
static

◆ isExtendedBUILD_VECTOR()

static bool isExtendedBUILD_VECTOR ( SDNode N,
SelectionDAG DAG,
bool  isSigned 
)
static

◆ isEXTMask()

static bool isEXTMask ( ArrayRef< int >  M,
EVT  VT,
bool ReverseEXT,
unsigned Imm 
)
static

◆ isINSMask()

static bool isINSMask ( ArrayRef< int >  M,
int  NumInputElements,
bool DstIsLeft,
int &  Anomaly 
)
static

◆ isLegalArithImmed()

static bool isLegalArithImmed ( uint64_t  C)
static

Definition at line 1474 of file AArch64ISelLowering.cpp.

References llvm::dbgs(), and LLVM_DEBUG.

Referenced by getAArch64Cmp().

◆ isOverflowIntrOpRes()

static bool isOverflowIntrOpRes ( SDValue  Op)
static

◆ isREVMask()

static bool isREVMask ( ArrayRef< int >  M,
EVT  VT,
unsigned  BlockSize 
)
static

isREVMask - Check if a vector shuffle corresponds to a REV instruction with the specified blocksize.

(The order of the elements within each block of the vector is reversed.)

Definition at line 6181 of file AArch64ISelLowering.cpp.

References assert(), llvm::EVT::getScalarSizeInBits(), and llvm::EVT::getVectorNumElements().

Referenced by getDUPLANEOp(), and llvm::AArch64TargetLowering::isShuffleMaskLegal().

◆ isSetCC()

static bool isSetCC ( SDValue  Op,
SetCCInfoAndKind SetCCInfo 
)
static

Check whether or not Op is a SET_CC operation, either a generic or an AArch64 lowered one.

SetCCInfo is filled accordingly.

Postcondition
SetCCInfo is meanginfull only when this function returns true.
Returns
True when Op is a kind of SET_CC operation.

Definition at line 9647 of file AArch64ISelLowering.cpp.

References SetCCInfo::AArch64, GenericSetCCInfo::CC, AArch64SetCCInfo::CC, AArch64SetCCInfo::Cmp, llvm::AArch64ISD::CSEL, llvm::dyn_cast(), SetCCInfo::Generic, llvm::AArch64CC::getInvertedCondCode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), SetCCInfoAndKind::Info, SetCCInfoAndKind::IsAArch64, llvm::ConstantSDNode::isOne(), GenericSetCCInfo::Opnd0, GenericSetCCInfo::Opnd1, llvm::ISD::SETCC, and std::swap().

Referenced by isSetCCOrZExtSetCC().

◆ isSetCCOrZExtSetCC()

static bool isSetCCOrZExtSetCC ( const SDValue Op,
SetCCInfoAndKind Info 
)
static

◆ isSignExtended()

static bool isSignExtended ( SDNode N,
SelectionDAG DAG 
)
static

◆ isSingletonEXTMask()

static bool isSingletonEXTMask ( ArrayRef< int >  M,
EVT  VT,
unsigned Imm 
)
static

Definition at line 6109 of file AArch64ISelLowering.cpp.

References llvm::EVT::getVectorNumElements().

Referenced by getDUPLANEOp().

◆ isTRN_v_undef_Mask()

static bool isTRN_v_undef_Mask ( ArrayRef< int >  M,
EVT  VT,
unsigned WhichResult 
)
static

isTRN_v_undef_Mask - Special case of isTRNMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef".

Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.

Definition at line 6285 of file AArch64ISelLowering.cpp.

References llvm::EVT::getVectorNumElements().

Referenced by getDUPLANEOp(), and llvm::AArch64TargetLowering::isShuffleMaskLegal().

◆ isTRNMask()

static bool isTRNMask ( ArrayRef< int >  M,
EVT  VT,
unsigned WhichResult 
)
static

◆ isUZP_v_undef_Mask()

static bool isUZP_v_undef_Mask ( ArrayRef< int >  M,
EVT  VT,
unsigned WhichResult 
)
static

isUZP_v_undef_Mask - Special case of isUZPMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef".

Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,

Definition at line 6266 of file AArch64ISelLowering.cpp.

References llvm::EVT::getVectorNumElements().

Referenced by getDUPLANEOp(), and llvm::AArch64TargetLowering::isShuffleMaskLegal().

◆ isUZPMask()

static bool isUZPMask ( ArrayRef< int >  M,
EVT  VT,
unsigned WhichResult 
)
static

◆ isVShiftLImm()

static bool isVShiftLImm ( SDValue  Op,
EVT  VT,
bool  isLong,
int64_t &  Cnt 
)
static

isVShiftLImm - Check if this is a valid build_vector for the immediate operand of a vector shift left operation.

That value must be in the range: 0 <= Value < ElementBits for a left shift; or 0 <= Value <= ElementBits for a long left shift.

Definition at line 7623 of file AArch64ISelLowering.cpp.

References assert(), llvm::EVT::getScalarSizeInBits(), getVShiftImm(), and llvm::EVT::isVector().

Referenced by isVShiftRImm().

◆ isVShiftRImm()

static bool isVShiftRImm ( SDValue  Op,
EVT  VT,
bool  isNarrow,
int64_t &  Cnt 
)
static

◆ isZeroExtended()

static bool isZeroExtended ( SDNode N,
SelectionDAG DAG 
)
static

◆ isZIP_v_undef_Mask()

static bool isZIP_v_undef_Mask ( ArrayRef< int >  M,
EVT  VT,
unsigned WhichResult 
)
static

isZIP_v_undef_Mask - Special case of isZIPMask for canonical form of "vector_shuffle v, v", i.e., "vector_shuffle v, undef".

Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.

Definition at line 6249 of file AArch64ISelLowering.cpp.

References llvm::EVT::getVectorNumElements().

Referenced by getDUPLANEOp(), and llvm::AArch64TargetLowering::isShuffleMaskLegal().

◆ isZIPMask()

static bool isZIPMask ( ArrayRef< int >  M,
EVT  VT,
unsigned WhichResult 
)
static

◆ LowerADDC_ADDE_SUBC_SUBE()

static SDValue LowerADDC_ADDE_SUBC_SUBE ( SDValue  Op,
SelectionDAG DAG 
)
static

◆ LowerBITCAST()

static SDValue LowerBITCAST ( SDValue  Op,
SelectionDAG DAG 
)
static

◆ LowerMUL()

static SDValue LowerMUL ( SDValue  Op,
SelectionDAG DAG 
)
static

◆ LowerMULH()

static SDValue LowerMULH ( SDValue  Op,
SelectionDAG DAG 
)
static

◆ LowerPREFETCH()

static SDValue LowerPREFETCH ( SDValue  Op,
SelectionDAG DAG 
)
static

◆ LowerTruncateVectorStore()

static SDValue LowerTruncateVectorStore ( SDLoc  DL,
StoreSDNode ST,
EVT  VT,
EVT  MemVT,
SelectionDAG DAG 
)
static

◆ LowerVectorFP_TO_INT()

static SDValue LowerVectorFP_TO_INT ( SDValue  Op,
SelectionDAG DAG 
)
static

◆ LowerVectorINT_TO_FP()

static SDValue LowerVectorINT_TO_FP ( SDValue  Op,
SelectionDAG DAG 
)
static

◆ LowerXALUO()

static SDValue LowerXALUO ( SDValue  Op,
SelectionDAG DAG 
)
static

◆ LowerXOR()

static SDValue LowerXOR ( SDValue  Op,
SelectionDAG DAG 
)
static

◆ mayTailCallThisCC()

static bool mayTailCallThisCC ( CallingConv::ID  CC)
static

Return true if we might ever do TCO for calls with this calling convention.

Definition at line 3354 of file AArch64ISelLowering.cpp.

References llvm::ISD::ADD, llvm::MachineFunction::addLiveIn(), llvm::AArch64ISD::ADDlow, llvm::AArch64ISD::ADR, llvm::AArch64ISD::ADRP, llvm::CCValAssign::AExt, llvm::AArch64CC::AL, llvm::AMDGPU::HSAMD::Kernel::Arg::Key::Align, llvm::alignTo(), llvm::CCState::AnalyzeCallOperands(), llvm::CCState::AnalyzeReturn(), llvm::ISD::AND, llvm::ISD::ANY_EXTEND, Arg, llvm::Function::arg_begin(), llvm::Function::arg_end(), assert(), llvm::CCValAssign::BCvt, llvm::AArch64ISD::BIT, llvm::ISD::BITCAST, llvm::EVT::bitsGT(), llvm::EVT::bitsLT(), llvm::AArch64ISD::BRCOND, llvm::ISD::BRIND, llvm::CallingConv::C, C, llvm::AArch64ISD::CALL, Callee, canGuaranteeTCO(), llvm::StringSwitch< T, R >::Case(), llvm::AArch64ISD::CBNZ, llvm::AArch64ISD::CBZ, llvm::AArch64TargetLowering::CCAssignFnForCall(), changeFPCCToAArch64CC(), changeIntCCToAArch64CC(), llvm::CCState::CheckReturn(), llvm::AArch64Subtarget::classifyGlobalFunctionReference(), llvm::AArch64Subtarget::ClassifyGlobalReference(), contains(), Context, llvm::HexagonISD::CP, llvm::MachineFrameInfo::CreateFixedObject(), llvm::AArch64ISD::CSEL, llvm::AArch64ISD::CSINC, llvm::AArch64ISD::CSINV, llvm::AArch64ISD::CSNEG, llvm::ISD::CTPOP, llvm::dbgs(), llvm::StringSwitch< T, R >::Default(), llvm::Depth, llvm::dyn_cast(), emitComparison(), llvm::AArch64RegisterInfo::emitReservedArgRegCallError(), llvm::SmallVectorBase::empty(), EnableAArch64ELFLocalDynamicTLSGeneration, llvm::AArch64CC::EQ, F(), llvm::MVT::f128, llvm::MVT::f16, llvm::MVT::f32, llvm::MVT::f64, llvm::CallingConv::Fast, llvm::ISD::FNEG, llvm::ISD::FP_EXTEND, llvm::ISD::FP_ROUND, llvm::CCValAssign::FPExt, llvm::CCValAssign::Full, G, llvm::AArch64CC::GE, llvm::TLSModel::GeneralDynamic, getAArch64Cmp(), getAArch64XALUOOp(), llvm::ConstantPoolSDNode::getAlignment(), llvm::SelectionDAG::getBitcast(), llvm::BlockAddressSDNode::getBlockAddress(), llvm::AArch64FunctionInfo::getBytesInStackArgArea(), llvm::ISD::ArgFlagsTy::getByValAlign(), llvm::ISD::ArgFlagsTy::getByValSize(), llvm::AArch64RegisterInfo::getCalleeSavedRegsViaCopy(), llvm::Function::getCallingConv(), llvm::AArch64RegisterInfo::getCallPreservedMask(), llvm::SelectionDAG::getCALLSEQ_END(), llvm::SelectionDAG::getCALLSEQ_START(), llvm::TargetMachine::getCodeModel(), llvm::SelectionDAG::getConstant(), llvm::SDValue::getConstantOperandVal(), llvm::ConstantPoolSDNode::getConstVal(), llvm::SelectionDAG::getContext(), llvm::SelectionDAG::getCopyFromReg(), llvm::SelectionDAG::getCopyToReg(), llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getEntryNode(), llvm::MachinePointerInfo::getFixedStack(), llvm::MVT::getFloatingPointVT(), llvm::AArch64FunctionInfo::getForwardedMustTailRegParms(), llvm::SelectionDAG::getFrameIndex(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getFunction(), llvm::GlobalAddressSDNode::getGlobal(), llvm::MachinePointerInfo::getGOT(), llvm::JumpTableSDNode::getIndex(), llvm::MachineFunction::getInfo(), llvm::MVT::getIntegerVT(), llvm::SelectionDAG::getIntPtrConstant(), llvm::AArch64CC::getInvertedCondCode(), llvm::SelectionDAG::getLoad(), llvm::CCValAssign::getLocInfo(), llvm::CCValAssign::getLocMemOffset(), llvm::CCValAssign::getLocReg(), llvm::CCValAssign::getLocVT(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getMemcpy(), llvm::SelectionDAG::getMergeValues(), llvm::CCState::getNextStackOffset(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SDValue::getNumOperands(), llvm::MachineFrameInfo::getObjectOffset(), llvm::MachineFrameInfo::getObjectSize(), llvm::getOffset(), llvm::GlobalAddressSDNode::getOffset(), llvm::ConstantPoolSDNode::getOffset(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::TargetLoweringBase::getPointerTy(), llvm::MachineFunction::getRegInfo(), llvm::SelectionDAG::getRegister(), llvm::AArch64Subtarget::getRegisterInfo(), llvm::SelectionDAG::getRegisterMask(), llvm::EVT::getScalarSizeInBits(), llvm::ISD::getSetCCInverse(), llvm::ConstantSDNode::getSExtValue(), llvm::EVT::getSimpleVT(), llvm::EVT::getSizeInBits(), llvm::MVT::getSizeInBits(), llvm::MachinePointerInfo::getStack(), llvm::SelectionDAG::getStore(), llvm::SelectionDAG::getTarget(), llvm::MachineFunction::getTarget(), llvm::SelectionDAG::getTargetBlockAddress(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetConstantPool(), llvm::SelectionDAG::getTargetExternalSymbol(), llvm::SelectionDAG::getTargetExtractSubreg(), llvm::SelectionDAG::getTargetGlobalAddress(), llvm::SelectionDAG::getTargetInsertSubreg(), llvm::SelectionDAG::getTargetJumpTable(), llvm::SelectionDAG::getTargetLoweringInfo(), llvm::TargetLoweringBase::getTargetMachine(), llvm::TargetMachine::getTargetTriple(), llvm::AArch64RegisterInfo::getThisReturnPreservedMask(), llvm::AArch64RegisterInfo::getTLSCallPreservedMask(), llvm::TargetMachine::getTLSModel(), llvm::DataLayout::getTypeAllocSize(), llvm::EVT::getTypeForEVT(), llvm::SelectionDAG::getUNDEF(), llvm::SDValue::getValue(), llvm::SDValue::getValueSizeInBits(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::TargetLoweringBase::getValueType(), llvm::CCValAssign::getValVT(), llvm::AArch64FunctionInfo::getVarArgsFPRIndex(), llvm::AArch64FunctionInfo::getVarArgsFPRSize(), llvm::AArch64FunctionInfo::getVarArgsGPRIndex(), llvm::AArch64FunctionInfo::getVarArgsGPRSize(), llvm::AArch64FunctionInfo::getVarArgsStackIndex(), llvm::MVT::getVectorVT(), llvm::SelectionDAG::getVTList(), llvm::ConstantSDNode::getZExtValue(), llvm::MVT::Glue, llvm::TargetOptions::GuaranteedTailCallOpt, llvm::AArch64Subtarget::hasCustomCallingConv(), llvm::GlobalValue::hasExternalWeakLinkage(), llvm::Function::hasFnAttribute(), llvm::AArch64Subtarget::hasFullFP16(), llvm::AArch64Subtarget::hasNEON(), llvm::MipsISD::Hi, I, llvm::MVT::i1, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, llvm::AArch64FunctionInfo::incNumLocalDynamicTLSAccesses(), llvm::TLSModel::InitialExec, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::EVT::is64BitVector(), llvm::isAllOnesConstant(), llvm::ConstantSDNode::isAllOnesValue(), llvm::AArch64RegisterInfo::isAnyArgRegReserved(), llvm::ISD::ArgFlagsTy::isByVal(), llvm::AArch64Subtarget::isCallingConvWin64(), llvm::EVT::isFloatingPoint(), llvm::ISD::ArgFlagsTy::isInConsecutiveRegs(), llvm::EVT::isInteger(), llvm::AArch64Subtarget::isLittleEndian(), llvm::CCValAssign::isMemLoc(), llvm::isNullConstant(), llvm::ConstantSDNode::isNullValue(), llvm::ConstantSDNode::isOne(), llvm::isOneConstant(), llvm::Triple::isOSBinFormatELF(), llvm::Triple::isOSBinFormatMachO(), llvm::Triple::isOSWindows(), isOverflowIntrOpRes(), llvm::isPowerOf2_64(), llvm::CCValAssign::isRegLoc(), llvm::ISD::ArgFlagsTy::isReturned(), llvm::EVT::isSimple(), llvm::ISD::ArgFlagsTy::isSwiftSelf(), llvm::AArch64Subtarget::isTargetCOFF(), llvm::AArch64Subtarget::isTargetDarwin(), llvm::AArch64Subtarget::isTargetELF(), llvm::AArch64Subtarget::isTargetMachO(), llvm::AArch64Subtarget::isTargetWindows(), llvm::TargetLoweringBase::isTypeLegal(), llvm::EVT::isVector(), llvm::AArch64Subtarget::isXRegisterReserved(), llvm::ConstantFPSDNode::isZero(), llvm::HexagonISD::JT, llvm::CodeModel::Large, LLVM_DEBUG, llvm_unreachable, llvm::MipsISD::Lo, llvm::AArch64ISD::LOADgot, llvm::TLSModel::LocalDynamic, llvm::TLSModel::LocalExec, llvm::Log2_64(), llvm::TargetLowering::LowerToTLSEmulatedModel(), llvm::BitmaskEnumDetail::Mask(), llvm::AArch64II::MO_COFFSTUB, llvm::AArch64II::MO_DLLIMPORT, llvm::AArch64II::MO_G0, llvm::AArch64II::MO_G1, llvm::AArch64II::MO_G2, llvm::AArch64II::MO_G3, llvm::AArch64II::MO_GOT, llvm::AArch64II::MO_HI12, llvm::AArch64II::MO_NC, llvm::AArch64II::MO_NO_FLAG, llvm::AArch64II::MO_PAGE, llvm::AArch64II::MO_PAGEOFF, llvm::AArch64II::MO_TLS, llvm::MachineMemOperand::MODereferenceable, llvm::MachineMemOperand::MOInvariant, llvm::MachineMemOperand::MONonTemporal, MRI, N, llvm::AArch64CC::NE, llvm::TargetMachine::Options, llvm::ISD::OR, llvm::MVT::Other, llvm::TargetLowering::parametersInCSRMatch(), llvm::CallingConv::PreserveMost, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), Reg, llvm::report_fatal_error(), llvm::CCState::resultsCompatible(), llvm::AArch64ISD::RET_FLAG, llvm::MachineFrameInfo::setAdjustsStack(), llvm::ISD::SETCC, llvm::ISD::SETEQ, llvm::MachineFrameInfo::setFrameAddressIsTaken(), llvm::ISD::SETGE, llvm::ISD::SETGT, llvm::MachineFrameInfo::setHasTailCall(), llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETOEQ, llvm::ISD::SETONE, llvm::MachineFrameInfo::setReturnAddressIsTaken(), llvm::ISD::SETUEQ, llvm::ISD::SETUNE, llvm::CCValAssign::SExt, llvm::ISD::SHL, llvm::ISD::SHL_PARTS, llvm::ISD::SIGN_EXTEND, llvm::SmallVectorBase::size(), llvm::TargetLowering::softenSetCCOperands(), llvm::ISD::SRA, llvm::ISD::SRA_PARTS, llvm::ISD::SRL, llvm::ISD::SRL_PARTS, llvm::SPII::Store, llvm::ISD::SUB, std::swap(), llvm::CallingConv::Swift, llvm::AArch64ISD::TBNZ, llvm::AArch64ISD::TBZ, llvm::AArch64ISD::TC_RETURN, llvm::AArch64ISD::THREAD_POINTER, llvm::CodeModel::Tiny, llvm::AArch64ISD::TLSDESC_CALLSEQ, llvm::ISD::TokenFactor, TRI, llvm::ISD::TRUNCATE, llvm::TargetOptions::UnsafeFPMath, llvm::AArch64RegisterInfo::UpdateCustomCallPreservedMask(), llvm::SDNode::use_begin(), llvm::SDNode::use_end(), llvm::TargetMachine::useEmulatedTLS(), llvm::MVT::v16i8, llvm::MVT::v1i64, llvm::MVT::v2f32, llvm::MVT::v2f64, llvm::MVT::v2i32, llvm::MVT::v2i64, llvm::MVT::v4f16, llvm::MVT::v4f32, llvm::MVT::v4i16, llvm::MVT::v4i32, llvm::MVT::v8f16, llvm::MVT::v8i16, llvm::MVT::v8i8, llvm::CallingConv::WebKit_JS, llvm::AArch64ISD::WrapperLarge, llvm::ISD::XOR, llvm::ISD::ZERO_EXTEND, and llvm::CCValAssign::ZExt.

◆ memOpAlign()

static bool memOpAlign ( unsigned  DstAlign,
unsigned  SrcAlign,
unsigned  AlignCheck 
)
static

◆ NarrowVector()

static SDValue NarrowVector ( SDValue  V128Reg,
SelectionDAG DAG 
)
static

NarrowVector - Given a value in the V128 register class, produce the equivalent value in the V64 register class.

Definition at line 5887 of file AArch64ISelLowering.cpp.

References llvm::EVT::getSimpleVT(), llvm::SelectionDAG::getTargetExtractSubreg(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), and llvm::MVT::getVectorVT().

◆ NormalizeBuildVector()

static SDValue NormalizeBuildVector ( SDValue  Op,
SelectionDAG DAG 
)
static

◆ optimizeLogicalImm()

static bool optimizeLogicalImm ( SDValue  Op,
unsigned  Size,
uint64_t  Imm,
const APInt Demanded,
TargetLowering::TargetLoweringOpt TLO,
unsigned  NewOpc 
)
static

◆ performAddSubLongCombine()

static SDValue performAddSubLongCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI,
SelectionDAG DAG 
)
static

◆ performBitcastCombine()

static SDValue performBitcastCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI,
SelectionDAG DAG 
)
static

◆ performBRCONDCombine()

static SDValue performBRCONDCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI,
SelectionDAG DAG 
)
static

◆ performConcatVectorsCombine()

static SDValue performConcatVectorsCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI,
SelectionDAG DAG 
)
static

◆ performCONDCombine()

static SDValue performCONDCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI,
SelectionDAG DAG,
unsigned  CCIndex,
unsigned  CmpIndex 
)
static

◆ performExtendCombine()

static SDValue performExtendCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI,
SelectionDAG DAG 
)
static

◆ performFDivCombine()

static SDValue performFDivCombine ( SDNode N,
SelectionDAG DAG,
TargetLowering::DAGCombinerInfo DCI,
const AArch64Subtarget Subtarget 
)
static

◆ performFpToIntCombine()

static SDValue performFpToIntCombine ( SDNode N,
SelectionDAG DAG,
TargetLowering::DAGCombinerInfo DCI,
const AArch64Subtarget Subtarget 
)
static

◆ performGlobalAddressCombine()

static SDValue performGlobalAddressCombine ( SDNode N,
SelectionDAG DAG,
const AArch64Subtarget Subtarget,
const TargetMachine TM 
)
static

◆ performIntegerAbsCombine()

static SDValue performIntegerAbsCombine ( SDNode N,
SelectionDAG DAG 
)
static

◆ performIntrinsicCombine()

static SDValue performIntrinsicCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI,
const AArch64Subtarget Subtarget 
)
static

◆ performIntToFpCombine()

static SDValue performIntToFpCombine ( SDNode N,
SelectionDAG DAG,
const AArch64Subtarget Subtarget 
)
static

◆ performMulCombine()

static SDValue performMulCombine ( SDNode N,
SelectionDAG DAG,
TargetLowering::DAGCombinerInfo DCI,
const AArch64Subtarget Subtarget 
)
static

◆ performNEONPostLDSTCombine()

static SDValue performNEONPostLDSTCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI,
SelectionDAG DAG 
)
static

Target-specific DAG combine function for NEON load/store intrinsics to merge base address updates.

Definition at line 10439 of file AArch64ISelLowering.cpp.

References llvm::ISD::ADD, llvm::TargetLowering::DAGCombinerInfo::CombineTo(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::MemSDNode::getMemOperand(), llvm::MemSDNode::getMemoryVT(), llvm::SDValue::getNode(), llvm::SDNode::getNumOperands(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getRegister(), llvm::SDValue::getResNo(), llvm::EVT::getSizeInBits(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::EVT::getVectorNumElements(), llvm::SelectionDAG::getVTList(), llvm::SDNode::hasPredecessorHelper(), llvm::MVT::i64, llvm::SmallPtrSetImpl< PtrType >::insert(), llvm::TargetLowering::DAGCombinerInfo::isBeforeLegalize(), llvm::TargetLowering::DAGCombinerInfo::isCalledByLegalizer(), llvm::AArch64ISD::LD1x2post, llvm::AArch64ISD::LD1x3post, llvm::AArch64ISD::LD1x4post, llvm::AArch64ISD::LD2DUPpost, llvm::AArch64ISD::LD2LANEpost, llvm::AArch64ISD::LD2post, llvm::AArch64ISD::LD3DUPpost, llvm::AArch64ISD::LD3LANEpost, llvm::AArch64ISD::LD3post, llvm::AArch64ISD::LD4DUPpost, llvm::AArch64ISD::LD4LANEpost, llvm::AArch64ISD::LD4post, llvm_unreachable, llvm::makeArrayRef(), N, llvm::MVT::Other, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::AArch64ISD::ST1x2post, llvm::AArch64ISD::ST1x3post, llvm::AArch64ISD::ST1x4post, llvm::AArch64ISD::ST2LANEpost, llvm::AArch64ISD::ST2post, llvm::AArch64ISD::ST3LANEpost, llvm::AArch64ISD::ST3post, llvm::AArch64ISD::ST4LANEpost, llvm::AArch64ISD::ST4post, llvm::SDNode::use_begin(), and llvm::SDNode::use_end().

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

◆ performNVCASTCombine()

static SDValue performNVCASTCombine ( SDNode N)
static

Get rid of unnecessary NVCASTs (that don't change the type).

Definition at line 11078 of file AArch64ISelLowering.cpp.

References llvm::SDNode::getOperand(), llvm::SDValue::getValueType(), and llvm::SDNode::getValueType().

Referenced by llvm::AArch64TargetLowering::PerformDAGCombine().

◆ performORCombine()

static SDValue performORCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI,
const AArch64Subtarget Subtarget 
)
static

◆ performPostLD1Combine()

static SDValue performPostLD1Combine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI,
bool  IsLaneOp 
)
static

◆ performSelectCombine()

static SDValue performSelectCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI 
)
static

◆ performSetccAddFolding()

static SDValue performSetccAddFolding ( SDNode Op,
SelectionDAG DAG 
)
static

◆ performSRLCombine()

static SDValue performSRLCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI 
)
static

◆ performSTORECombine()

static SDValue performSTORECombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI,
SelectionDAG DAG,
const AArch64Subtarget Subtarget 
)
static

◆ performTBISimplification()

static bool performTBISimplification ( SDValue  Addr,
TargetLowering::DAGCombinerInfo DCI,
SelectionDAG DAG 
)
static

◆ performTBZCombine()

static SDValue performTBZCombine ( SDNode N,
TargetLowering::DAGCombinerInfo DCI,
SelectionDAG DAG 
)
static

◆ performVectorCompareAndMaskUnaryOpCombine()

static SDValue performVectorCompareAndMaskUnaryOpCombine ( SDNode N,
SelectionDAG DAG 
)
static

◆ performVSelectCombine()

static SDValue performVSelectCombine ( SDNode N,
SelectionDAG DAG 
)
static

◆ performXorCombine()

static SDValue performXorCombine ( SDNode N,
SelectionDAG DAG,
TargetLowering::DAGCombinerInfo DCI,
const AArch64Subtarget Subtarget 
)
static

◆ ReplaceBITCASTResults()

static void ReplaceBITCASTResults ( SDNode N,
SmallVectorImpl< SDValue > &  Results,
SelectionDAG DAG 
)
static

◆ ReplaceCMP_SWAP_128Results()

static void ReplaceCMP_SWAP_128Results ( SDNode N,
SmallVectorImpl< SDValue > &  Results,
SelectionDAG DAG,
const AArch64Subtarget Subtarget 
)
static

◆ ReplaceReductionResults()

static void ReplaceReductionResults ( SDNode N,
SmallVectorImpl< SDValue > &  Results,
SelectionDAG DAG,
unsigned  InterOp,
unsigned  AcrossOp 
)
static

◆ replaceSplatVectorStore()

static SDValue replaceSplatVectorStore ( SelectionDAG DAG,
StoreSDNode St 
)
static

Replace a splat of a scalar to a vector store by scalar stores of the scalar value.

The load store optimizer pass will merge them to store pair stores. This has better performance than a splat of the scalar followed by a split vector store. Even if the stores are not merged it is four stores vs a dup, followed by an ext.b and two stores.

Definition at line 10183 of file AArch64ISelLowering.cpp.

References llvm::dyn_cast(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::StoreSDNode::getValue(), llvm::SDValue::getValueType(), llvm::EVT::getVectorNumElements(), llvm::ConstantSDNode::getZExtValue(), I, llvm::ISD::INSERT_VECTOR_ELT, llvm::EVT::isFloatingPoint(), and splitStoreSplat().

Referenced by splitStores().

◆ replaceZeroVectorStore()

static SDValue replaceZeroVectorStore ( SelectionDAG DAG,
StoreSDNode St 
)
static

Replace a splat of zeros to a vector store by scalar stores of WZR/XZR.

The load store optimizer pass will merge them to store pair stores. This should be better than a movi to create the vector zero followed by a vector store if the zero constant is not re-used, since one instructions and one register live range will be removed.

For example, the final generated code should be:

stp xzr, xzr, [x0]

instead of:

movi v0.2d, #0 str q0, [x0]

Definition at line 10125 of file AArch64ISelLowering.cpp.

References llvm::ISD::BUILD_VECTOR, llvm::StoreSDNode::getBasePtr(), llvm::SDNode::getConstantOperandVal(), llvm::SelectionDAG::getCopyFromReg(), llvm::SelectionDAG::getEntryNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::EVT::getSizeInBits(), llvm::StoreSDNode::getValue(), llvm::SDValue::getValueType(), llvm::EVT::getVectorElementType(), llvm::EVT::getVectorNumElements(), llvm::SDValue::hasOneUse(), I, llvm::MVT::i32, llvm::MVT::i64, llvm::SelectionDAG::isBaseWithConstantOffset(), llvm::isNullConstant(), llvm::isNullFPConstant(), and splitStoreSplat().

Referenced by splitStores().

◆ resolveBuildVector()

static bool resolveBuildVector ( BuildVectorSDNode BVN,
APInt CnstBits,
APInt UndefBits 
)
static

◆ skipExtensionForVectorMULL()

static SDValue skipExtensionForVectorMULL ( SDNode N,
SelectionDAG DAG 
)
static

◆ splitInt128()

static std::pair<SDValue, SDValue> splitInt128 ( SDValue  N,
SelectionDAG DAG 
)
static

◆ splitStores()

static SDValue splitStores ( SDNode N,
TargetLowering::DAGCombinerInfo DCI,
SelectionDAG DAG,
const AArch64Subtarget Subtarget 
)
static

◆ splitStoreSplat()

static SDValue splitStoreSplat ( SelectionDAG DAG,
StoreSDNode St,
SDValue  SplatVal,
unsigned  NumVecElts 
)
static

◆ STATISTIC() [1/3]

STATISTIC ( NumTailCalls  ,
"Number of tail calls  
)

◆ STATISTIC() [2/3]

STATISTIC ( NumShiftInserts  ,
"Number of vector shift inserts"   
)

◆ STATISTIC() [3/3]

STATISTIC ( NumOptimizedImms  ,
"Number of times immediates were optimized"   
)

◆ tryAdvSIMDModImm16()

static SDValue tryAdvSIMDModImm16 ( unsigned  NewOp,
SDValue  Op,
SelectionDAG DAG,
const APInt Bits,
const SDValue LHS = nullptr 
)
static

◆ tryAdvSIMDModImm32()

static SDValue tryAdvSIMDModImm32 ( unsigned  NewOp,
SDValue  Op,
SelectionDAG DAG,
const APInt Bits,
const SDValue LHS = nullptr 
)
static

◆ tryAdvSIMDModImm321s()

static SDValue tryAdvSIMDModImm321s ( unsigned  NewOp,
SDValue  Op,
SelectionDAG DAG,
const APInt Bits 
)
static

◆ tryAdvSIMDModImm64()

static SDValue tryAdvSIMDModImm64 ( unsigned  NewOp,
SDValue  Op,
SelectionDAG DAG,
const APInt Bits 
)
static

◆ tryAdvSIMDModImm8()

static SDValue tryAdvSIMDModImm8 ( unsigned  NewOp,
SDValue  Op,
SelectionDAG DAG,
const APInt Bits 
)
static

◆ tryAdvSIMDModImmFP()

static SDValue tryAdvSIMDModImmFP ( unsigned  NewOp,
SDValue  Op,
SelectionDAG DAG,
const APInt Bits 
)
static

◆ tryCombineCRC32()

static SDValue tryCombineCRC32 ( unsigned  Mask,
SDNode N,
SelectionDAG DAG 
)
static

◆ tryCombineFixedPointConvert()

static SDValue tryCombineFixedPointConvert ( SDNode N,
TargetLowering::DAGCombinerInfo DCI,
SelectionDAG DAG 
)
static

◆ tryCombineLongOpWithDup()

static SDValue tryCombineLongOpWithDup ( unsigned  IID,
SDNode N,
TargetLowering::DAGCombinerInfo DCI,
SelectionDAG DAG 
)
static

◆ tryCombineShiftImm()

static SDValue tryCombineShiftImm ( unsigned  IID,
SDNode N,
SelectionDAG DAG 
)
static

◆ tryCombineToBSL()

static SDValue tryCombineToBSL ( SDNode N,
TargetLowering::DAGCombinerInfo DCI 
)
static

◆ tryCombineToEXTR()

static SDValue tryCombineToEXTR ( SDNode N,
TargetLowering::DAGCombinerInfo DCI 
)
static

EXTR instruction extracts a contiguous chunk of bits from two existing registers viewed as a high/low pair.

This function looks for the pattern: (or (shl VAL1, #N), (srl VAL2, #RegWidth-N)) and replaces it with an EXTR. Can't quite be done in TableGen because the two immediates aren't independent.

Definition at line 9226 of file AArch64ISelLowering.cpp.

References assert(), llvm::TargetLowering::DAGCombinerInfo::DAG, llvm::AArch64ISD::EXTR, findEXTRHalf(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getNode(), llvm::SDNode::getOpcode(), llvm::SDNode::getOperand(), llvm::EVT::getSizeInBits(), llvm::SDNode::getValueType(), llvm::MVT::i32, llvm::MVT::i64, llvm::ISD::OR, and std::swap().

Referenced by performORCombine().

◆ tryExtendDUPToExtractHigh()

static SDValue tryExtendDUPToExtractHigh ( SDValue  N,
SelectionDAG DAG 
)
static

◆ tryFormConcatFromShuffle()

static SDValue tryFormConcatFromShuffle ( SDValue  Op,
SelectionDAG DAG 
)
static

◆ tryLowerToSLI()

static SDValue tryLowerToSLI ( SDNode N,
SelectionDAG DAG 
)
static

◆ UseTlsOffset()

static Value* UseTlsOffset ( IRBuilder<> &  IRB,
unsigned  Offset 
)
static

◆ WidenVector()

static SDValue WidenVector ( SDValue  V64Reg,
SelectionDAG DAG 
)
static

Variable Documentation

◆ EnableAArch64ELFLocalDynamicTLSGeneration

cl::opt<bool> EnableAArch64ELFLocalDynamicTLSGeneration("aarch64-elf-ldtls-generation", cl::Hidden, cl::desc("Allow AArch64 Local Dynamic TLS code generation"), cl::init(false))

Referenced by mayTailCallThisCC().

◆ EnableAArch64SlrGeneration

cl::opt<bool> EnableAArch64SlrGeneration("aarch64-shift-insert-generation", cl::Hidden, cl::desc("Allow AArch64 SLI/SRI formation"), cl::init(false))
static

Referenced by tryLowerToSLI().

◆ EnableOptimizeLogicalImm

cl::opt<bool> EnableOptimizeLogicalImm("aarch64-enable-logical-imm", cl::Hidden, cl::desc("Enable AArch64 logical imm instruction " "optimization"), cl::init(true))
static

◆ MVT_CC

const MVT MVT_CC = MVT::i32
static

Value type used for condition codes.

Definition at line 117 of file AArch64ISelLowering.cpp.