LLVM  7.0.0svn
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1 //==-- AArch64ISelLowering.h - AArch64 DAG Lowering Interface ----*- C++ -*-==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that AArch64 uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
18 #include "AArch64.h"
22 #include "llvm/IR/CallingConv.h"
23 #include "llvm/IR/Instruction.h"
25 namespace llvm {
27 namespace AArch64ISD {
29 enum NodeType : unsigned {
31  WrapperLarge, // 4-instruction MOVZ/MOVK sequence for 64-bit addresses.
32  CALL, // Function call.
34  // Produces the full sequence of instructions for getting the thread pointer
35  // offset of a variable into X0, using the TLSDesc model.
37  ADRP, // Page address of a TargetGlobalAddress operand.
38  ADDlow, // Add the low 12 bits of a TargetGlobalAddress operand.
39  LOADgot, // Load from automatically generated descriptor (e.g. Global
40  // Offset Table, TLS record).
41  RET_FLAG, // Return with a flag operand. Operand 0 is the chain operand.
42  BRCOND, // Conditional branch instruction; "b.cond".
44  FCSEL, // Conditional move instruction.
45  CSINV, // Conditional select invert.
46  CSNEG, // Conditional select negate.
47  CSINC, // Conditional select increment.
49  // Pointer to the thread's local storage area. Materialised from TPIDR_EL0 on
50  // ELF.
52  ADC,
53  SBC, // adc, sbc instructions
55  // Arithmetic instructions which write flags.
62  // Conditional compares. Operands: left,right,falsecc,cc,flags
67  // Floating point comparison
70  // Scalar extract
73  // Scalar-to-vector duplication
74  DUP,
80  // Vector immedate moves
89  // Vector immediate ops
93  // Vector bit select: similar to ISD::VSELECT but not all bits within an
94  // element must be identical.
95  BSL,
97  // Vector arithmetic negation
98  NEG,
100  // Vector shuffles
112  // Vector shift by scalar
117  // Vector shift by scalar (again)
124  // Vector comparisons
134  // Vector zero comparisons
146  // Vector across-lanes addition
147  // Only the lower result lane is defined.
151  // Vector across-lanes min/max
152  // Only the lower result lane is defined.
158  // Vector bitwise negation
161  // Vector bitwise selection
164  // Compare-and-branch
170  // Tail calls
173  // Custom prefetch handling
176  // {s|u}int to FP within a FP register.
180  /// Natural vector cast. ISD::BITCAST is not natural in the big-endian
181  /// world w.r.t vectors; which causes additional REV instructions to be
182  /// generated to compensate for the byte-swapping. But sometimes we do
183  /// need to re-interpret the data in SIMD vector registers in big-endian
184  /// mode without emitting such REV instructions.
190  // Reciprocal estimates and steps.
194  // NEON Load/Store with post-increment base updates
218 };
220 } // end namespace AArch64ISD
222 namespace {
224 // Any instruction that defines a 32-bit result zeros out the high half of the
225 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
226 // be copying from a truncate. But any other 32-bit operation will zero-extend
227 // up to 64 bits.
228 // FIXME: X86 also checks for CMOV here. Do we need something similar?
229 static inline bool isDef32(const SDNode &N) {
230  unsigned Opc = N.getOpcode();
231  return Opc != ISD::TRUNCATE && Opc != TargetOpcode::EXTRACT_SUBREG &&
232  Opc != ISD::CopyFromReg;
233 }
235 } // end anonymous namespace
237 class AArch64Subtarget;
241 public:
242  explicit AArch64TargetLowering(const TargetMachine &TM,
243  const AArch64Subtarget &STI);
245  /// Selects the correct CCAssignFn for a given CallingConvention value.
246  CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const;
248  /// Selects the correct CCAssignFn for a given CallingConvention value.
249  CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC) const;
251  /// Determine which of the bits specified in Mask are known to be either zero
252  /// or one and return them in the KnownZero/KnownOne bitsets.
253  void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known,
254  const APInt &DemandedElts,
255  const SelectionDAG &DAG,
256  unsigned Depth = 0) const override;
258  bool targetShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
259  TargetLoweringOpt &TLO) const override;
261  MVT getScalarShiftAmountTy(const DataLayout &DL, EVT) const override;
263  /// Returns true if the target allows unaligned memory accesses of the
264  /// specified type.
265  bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace = 0,
266  unsigned Align = 1,
267  bool *Fast = nullptr) const override;
269  /// Provide custom lowering hooks for some operations.
270  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
272  const char *getTargetNodeName(unsigned Opcode) const override;
274  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
276  /// Returns true if a cast between SrcAS and DestAS is a noop.
277  bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
278  // Addrspacecasts are always noops.
279  return true;
280  }
282  /// This method returns a target specific FastISel object, or null if the
283  /// target does not support "fast" ISel.
285  const TargetLibraryInfo *libInfo) const override;
287  bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
289  bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
291  /// Return true if the given shuffle mask can be codegen'd directly, or if it
292  /// should be stack expanded.
293  bool isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override;
295  /// Return the ISD::SETCC ValueType.
296  EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
297  EVT VT) const override;
299  SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
301  MachineBasicBlock *EmitF128CSEL(MachineInstr &MI,
302  MachineBasicBlock *BB) const;
305  EmitInstrWithCustomInserter(MachineInstr &MI,
306  MachineBasicBlock *MBB) const override;
308  bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
309  MachineFunction &MF,
310  unsigned Intrinsic) const override;
312  bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy,
313  EVT NewVT) const override;
315  bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
316  bool isTruncateFree(EVT VT1, EVT VT2) const override;
318  bool isProfitableToHoist(Instruction *I) const override;
320  bool isZExtFree(Type *Ty1, Type *Ty2) const override;
321  bool isZExtFree(EVT VT1, EVT VT2) const override;
322  bool isZExtFree(SDValue Val, EVT VT2) const override;
324  bool hasPairedLoad(EVT LoadedType, unsigned &RequiredAligment) const override;
326  unsigned getMaxSupportedInterleaveFactor() const override { return 4; }
328  bool lowerInterleavedLoad(LoadInst *LI,
330  ArrayRef<unsigned> Indices,
331  unsigned Factor) const override;
332  bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
333  unsigned Factor) const override;
335  bool isLegalAddImmediate(int64_t) const override;
336  bool isLegalICmpImmediate(int64_t) const override;
338  EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
339  bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
340  MachineFunction &MF) const override;
342  /// Return true if the addressing mode represented by AM is legal for this
343  /// target, for a load/store of the specified type.
344  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
345  unsigned AS,
346  Instruction *I = nullptr) const override;
348  /// \brief Return the cost of the scaling factor used in the addressing
349  /// mode represented by AM for this target, for a load/store
350  /// of the specified type.
351  /// If the AM is supported, the return value must be >= 0.
352  /// If the AM is not supported, it returns a negative value.
353  int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty,
354  unsigned AS) const override;
356  /// Return true if an FMA operation is faster than a pair of fmul and fadd
357  /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
358  /// returns true, otherwise fmuladd is expanded to fmul + fadd.
359  bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
361  const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
363  /// \brief Returns false if N is a bit extraction pattern of (X >> C) & Mask.
364  bool isDesirableToCommuteWithShift(const SDNode *N) const override;
366  /// \brief Returns true if it is beneficial to convert a load of a constant
367  /// to just the constant itself.
368  bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
369  Type *Ty) const override;
371  /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
372  /// with this index.
373  bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
374  unsigned Index) const override;
376  Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
377  AtomicOrdering Ord) const override;
378  Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
379  Value *Addr, AtomicOrdering Ord) const override;
381  void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const override;
384  shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
385  bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
387  shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
389  bool shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override;
391  bool useLoadStackGuardNode() const override;
393  getPreferredVectorAction(EVT VT) const override;
395  /// If the target has a standard location for the stack protector cookie,
396  /// returns the address of that location. Otherwise, returns nullptr.
397  Value *getIRStackGuard(IRBuilder<> &IRB) const override;
399  /// If the target has a standard location for the unsafe stack pointer,
400  /// returns the address of that location. Otherwise, returns nullptr.
401  Value *getSafeStackPointerLocation(IRBuilder<> &IRB) const override;
403  /// If a physical register, this returns the register that receives the
404  /// exception address on entry to an EH pad.
405  unsigned
406  getExceptionPointerRegister(const Constant *PersonalityFn) const override {
407  // FIXME: This is a guess. Has this been defined yet?
408  return AArch64::X0;
409  }
411  /// If a physical register, this returns the register that receives the
412  /// exception typeid on entry to a landing pad.
413  unsigned
414  getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
415  // FIXME: This is a guess. Has this been defined yet?
416  return AArch64::X1;
417  }
419  bool isIntDivCheap(EVT VT, AttributeList Attr) const override;
421  bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
422  const SelectionDAG &DAG) const override {
423  // Do not merge to float value size (128 bytes) if no implicit
424  // float attribute is set.
426  bool NoFloat = DAG.getMachineFunction().getFunction().hasFnAttribute(
427  Attribute::NoImplicitFloat);
429  if (NoFloat)
430  return (MemVT.getSizeInBits() <= 64);
431  return true;
432  }
434  bool isCheapToSpeculateCttz() const override {
435  return true;
436  }
438  bool isCheapToSpeculateCtlz() const override {
439  return true;
440  }
442  bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override;
444  bool hasAndNotCompare(SDValue) const override {
445  // 'bics'
446  return true;
447  }
449  bool hasBitPreservingFPLogic(EVT VT) const override {
450  // FIXME: Is this always true? It should be true for vectors at least.
451  return VT == MVT::f32 || VT == MVT::f64;
452  }
454  bool supportSplitCSR(MachineFunction *MF) const override {
456  MF->getFunction().hasFnAttribute(Attribute::NoUnwind);
457  }
458  void initializeSplitCSR(MachineBasicBlock *Entry) const override;
459  void insertCopiesSplitCSR(
460  MachineBasicBlock *Entry,
461  const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
463  bool supportSwiftError() const override {
464  return true;
465  }
467  /// Enable aggressive FMA fusion on targets that want it.
468  bool enableAggressiveFMAFusion(EVT VT) const override;
470  /// Returns the size of the platform's va_list object.
471  unsigned getVaListSizeInBits(const DataLayout &DL) const override;
473  /// Returns true if \p VecTy is a legal interleaved access type. This
474  /// function checks the vector element type and the overall width of the
475  /// vector.
476  bool isLegalInterleavedAccessType(VectorType *VecTy,
477  const DataLayout &DL) const;
479  /// Returns the number of interleaved accesses that will be generated when
480  /// lowering accesses of the given type.
481  unsigned getNumInterleavedAccesses(VectorType *VecTy,
482  const DataLayout &DL) const;
484  MachineMemOperand::Flags getMMOFlags(const Instruction &I) const override;
486  bool functionArgumentNeedsConsecutiveRegisters(Type *Ty,
487  CallingConv::ID CallConv,
488  bool isVarArg) const override;
489 private:
490  bool isExtFreeImpl(const Instruction *Ext) const override;
492  /// Keep a pointer to the AArch64Subtarget around so that we can
493  /// make the right decision when generating code for different targets.
494  const AArch64Subtarget *Subtarget;
496  void addTypeForNEON(MVT VT, MVT PromotedBitwiseVT);
497  void addDRTypeForNEON(MVT VT);
498  void addQRTypeForNEON(MVT VT);
500  SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
501  bool isVarArg,
503  const SDLoc &DL, SelectionDAG &DAG,
504  SmallVectorImpl<SDValue> &InVals) const override;
506  SDValue LowerCall(CallLoweringInfo & /*CLI*/,
507  SmallVectorImpl<SDValue> &InVals) const override;
509  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
510  CallingConv::ID CallConv, bool isVarArg,
512  const SDLoc &DL, SelectionDAG &DAG,
513  SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
514  SDValue ThisVal) const;
516  SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
518  bool isEligibleForTailCallOptimization(
519  SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
521  const SmallVectorImpl<SDValue> &OutVals,
522  const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const;
524  /// Finds the incoming stack arguments which overlap the given fixed stack
525  /// object and incorporates their load into the current chain. This prevents
526  /// an upcoming store from clobbering the stack argument before it's used.
527  SDValue addTokenForArgument(SDValue Chain, SelectionDAG &DAG,
528  MachineFrameInfo &MFI, int ClobberedFI) const;
530  bool DoesCalleeRestoreStack(CallingConv::ID CallCC, bool TailCallOpt) const;
532  void saveVarArgRegisters(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &DL,
533  SDValue &Chain) const;
535  bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
536  bool isVarArg,
538  LLVMContext &Context) const override;
540  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
542  const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
543  SelectionDAG &DAG) const override;
545  SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
546  unsigned Flag) const;
547  SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG,
548  unsigned Flag) const;
549  SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG,
550  unsigned Flag) const;
551  SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
552  unsigned Flag) const;
553  template <class NodeTy>
554  SDValue getGOT(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const;
555  template <class NodeTy>
556  SDValue getAddrLarge(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const;
557  template <class NodeTy>
558  SDValue getAddr(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const;
559  SDValue LowerADDROFRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
560  SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
561  SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
562  SDValue LowerDarwinGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
563  SDValue LowerELFGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
564  SDValue LowerELFTLSDescCallSeq(SDValue SymAddr, const SDLoc &DL,
565  SelectionDAG &DAG) const;
566  SDValue LowerWindowsGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
567  SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
568  SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
569  SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
570  SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
572  SDValue TVal, SDValue FVal, const SDLoc &dl,
573  SelectionDAG &DAG) const;
574  SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
575  SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
576  SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
577  SDValue LowerAAPCS_VASTART(SDValue Op, SelectionDAG &DAG) const;
578  SDValue LowerDarwin_VASTART(SDValue Op, SelectionDAG &DAG) const;
579  SDValue LowerWin64_VASTART(SDValue Op, SelectionDAG &DAG) const;
580  SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
581  SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
582  SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
583  SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
588  SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
591  SDValue LowerVectorSRA_SRL_SHL(SDValue Op, SelectionDAG &DAG) const;
592  SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
593  SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
594  SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const;
595  SDValue LowerCTPOP(SDValue Op, SelectionDAG &DAG) const;
596  SDValue LowerF128Call(SDValue Op, SelectionDAG &DAG,
597  RTLIB::Libcall Call) const;
598  SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
599  SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
600  SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
601  SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
602  SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
603  SDValue LowerVectorAND(SDValue Op, SelectionDAG &DAG) const;
604  SDValue LowerVectorOR(SDValue Op, SelectionDAG &DAG) const;
606  SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
607  SDValue LowerVECREDUCE(SDValue Op, SelectionDAG &DAG) const;
608  SDValue LowerATOMIC_LOAD_SUB(SDValue Op, SelectionDAG &DAG) const;
609  SDValue LowerATOMIC_LOAD_AND(SDValue Op, SelectionDAG &DAG) const;
611  SDValue LowerWindowsDYNAMIC_STACKALLOC(SDValue Op, SDValue Chain,
612  SDValue &Size,
613  SelectionDAG &DAG) const;
615  SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
616  std::vector<SDNode *> *Created) const override;
617  SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
618  int &ExtraSteps, bool &UseOneConst,
619  bool Reciprocal) const override;
620  SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
621  int &ExtraSteps) const override;
622  unsigned combineRepeatedFPDivisors() const override;
624  ConstraintType getConstraintType(StringRef Constraint) const override;
625  unsigned getRegisterByName(const char* RegName, EVT VT,
626  SelectionDAG &DAG) const override;
628  /// Examine constraint string and operand type and determine a weight value.
629  /// The operand object must already have been set up with the operand type.
631  getSingleConstraintMatchWeight(AsmOperandInfo &info,
632  const char *constraint) const override;
634  std::pair<unsigned, const TargetRegisterClass *>
635  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
636  StringRef Constraint, MVT VT) const override;
638  const char *LowerXConstraint(EVT ConstraintVT) const override;
640  void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
641  std::vector<SDValue> &Ops,
642  SelectionDAG &DAG) const override;
644  unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
645  if (ConstraintCode == "Q")
647  // FIXME: clang has code for 'Ump', 'Utf', 'Usa', and 'Ush' but these are
648  // followed by llvm_unreachable so we'll leave them unimplemented in
649  // the backend for now.
650  return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
651  }
653  bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
654  bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
655  bool getIndexedAddressParts(SDNode *Op, SDValue &Base, SDValue &Offset,
656  ISD::MemIndexedMode &AM, bool &IsInc,
657  SelectionDAG &DAG) const;
658  bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
660  SelectionDAG &DAG) const override;
661  bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
662  SDValue &Offset, ISD::MemIndexedMode &AM,
663  SelectionDAG &DAG) const override;
665  void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
666  SelectionDAG &DAG) const override;
668  bool shouldNormalizeToSelectSequence(LLVMContext &, EVT) const override;
670  void finalizeLowering(MachineFunction &MF) const override;
671 };
673 namespace AArch64 {
675  const TargetLibraryInfo *libInfo);
676 } // end namespace AArch64
678 } // end namespace llvm
680 #endif
static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG)
static SDValue LowerCallResult(SDValue Chain, SDValue InFlag, const SmallVectorImpl< CCValAssign > &RVLocs, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals)
LowerCallResult - Lower the result values of a call into the appropriate copies out of appropriate ph...
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:836
unsigned getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:111
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
LLVMContext & Context
bool supportSplitCSR(MachineFunction *MF) const override
Return true if the target supports that a subset of CSRs for the given machine function is handled ex...
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
an instruction that atomically checks whether a specified value is in a memory location, and, if it is, stores a new value there.
Definition: Instructions.h:514
static SDValue LowerVACOPY(SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
This class represents a function call, abstracting a target machine&#39;s calling convention.
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit...
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change...
Function Alias Analysis Results
This instruction constructs a fixed permutation of two input vectors.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:302
An instruction for reading from memory.
Definition: Instructions.h:164
an instruction that atomically reads a memory location, combines it with another value, and then stores the result back.
Definition: Instructions.h:677
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
A convenience struct that encapsulates a DAG, and two SDValues for returning information from TargetL...
static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG)
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
Definition: IRBuilder.h:677
static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, const SparcSubtarget *Subtarget)
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override
Returns true if a cast between SrcAS and DestAS is a noop.
Atomic ordering for LLVM&#39;s memory model.
static SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG)
This is a fast-path instruction selection class that generates poor code and doesn&#39;t support illegal ...
Definition: FastISel.h:67
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:292
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:385
static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG)
This contains information for each constraint that we are lowering.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
An instruction for storing to memory.
Definition: Instructions.h:306
Natural vector cast.
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:918
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG)
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
amdgpu Simplify well known AMD library false Value * Callee
unsigned getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG)
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:121
bool hasAndNotCompare(SDValue) const override
Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) != Y —> (~X & Y) ...
Machine Value Type.
static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG)
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:69
This is an important base class in LLVM.
Definition: Constant.h:42
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
Definition: ISDOpcodes.h:893
static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
lazy value info
Extended Value Type.
Definition: ValueTypes.h:34
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
static Value * LowerCTPOP(LLVMContext &Context, Value *V, Instruction *IP)
Emit the code to lower ctpop of V before the specified instruction IP.
CCState - This class holds information needed while lowering arguments and return values...
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:194
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:212
Provides information about what library functions are available for the current target.
Definition: NVPTXBaseInfo.h:22
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:843
Represents one node in the SelectionDAG.
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:43
static bool Enabled
Definition: Statistic.cpp:51
const Function & getFunction() const
Return the LLVM function that this machine code represents.
bool hasBitPreservingFPLogic(EVT VT) const override
Return true if it is safe to transform an integer-domain bitwise operation into the equivalent floati...
Class to represent vector types.
Definition: DerivedTypes.h:393
Class for arbitrary precision integers.
Definition: APInt.h:69
bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT, const SelectionDAG &DAG) const override
Returns if it&#39;s reasonable to merge stores to MemVT size.
static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG)
static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
Flags values. These may be or&#39;d together.
static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
Representation of each machine instruction.
Definition: MachineInstr.h:60
static unsigned getScalingFactorCost(const TargetTransformInfo &TTI, const LSRUse &LU, const Formula &F, const Loop &L)
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...
Definition: ISDOpcodes.h:175
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
LLVM Value Representation.
Definition: Value.h:73
static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG)
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
unsigned getMaxSupportedInterleaveFactor() const override
Get the maximum supported factor for interleaved memory accesses.
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:59
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
bool isCheapToSpeculateCttz() const override
Return true if it is cheap to speculate a call to intrinsic cttz.
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:452
bool isCheapToSpeculateCtlz() const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
This file describes how to lower LLVM code to machine code.
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:873