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AArch64ISelLowering.h
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1 //==-- AArch64ISelLowering.h - AArch64 DAG Lowering Interface ----*- C++ -*-==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that AArch64 uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H
16 #define LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H
17 
18 #include "AArch64.h"
22 #include "llvm/IR/CallingConv.h"
23 #include "llvm/IR/Instruction.h"
24 
25 namespace llvm {
26 
27 namespace AArch64ISD {
28 
29 enum NodeType : unsigned {
31  WrapperLarge, // 4-instruction MOVZ/MOVK sequence for 64-bit addresses.
32  CALL, // Function call.
33 
34  // Produces the full sequence of instructions for getting the thread pointer
35  // offset of a variable into X0, using the TLSDesc model.
37  ADRP, // Page address of a TargetGlobalAddress operand.
38  ADDlow, // Add the low 12 bits of a TargetGlobalAddress operand.
39  LOADgot, // Load from automatically generated descriptor (e.g. Global
40  // Offset Table, TLS record).
41  RET_FLAG, // Return with a flag operand. Operand 0 is the chain operand.
42  BRCOND, // Conditional branch instruction; "b.cond".
44  FCSEL, // Conditional move instruction.
45  CSINV, // Conditional select invert.
46  CSNEG, // Conditional select negate.
47  CSINC, // Conditional select increment.
48 
49  // Pointer to the thread's local storage area. Materialised from TPIDR_EL0 on
50  // ELF.
52  ADC,
53  SBC, // adc, sbc instructions
54 
55  // Arithmetic instructions which write flags.
61 
62  // Conditional compares. Operands: left,right,falsecc,cc,flags
66 
67  // Floating point comparison
69 
70  // Scalar extract
72 
73  // Scalar-to-vector duplication
74  DUP,
79 
80  // Vector immedate moves
88 
89  // Vector immediate ops
92 
93  // Vector bit select: similar to ISD::VSELECT but not all bits within an
94  // element must be identical.
95  BSL,
96 
97  // Vector arithmetic negation
98  NEG,
99 
100  // Vector shuffles
111 
112  // Vector shift by scalar
116 
117  // Vector shift by scalar (again)
123 
124  // Vector comparisons
133 
134  // Vector zero comparisons
145 
146  // Vector across-lanes addition
147  // Only the lower result lane is defined.
150 
151  // Vector across-lanes min/max
152  // Only the lower result lane is defined.
157 
158  // Vector bitwise negation
160 
161  // Vector bitwise selection
163 
164  // Compare-and-branch
169 
170  // Tail calls
172 
173  // Custom prefetch handling
175 
176  // {s|u}int to FP within a FP register.
179 
180  /// Natural vector cast. ISD::BITCAST is not natural in the big-endian
181  /// world w.r.t vectors; which causes additional REV instructions to be
182  /// generated to compensate for the byte-swapping. But sometimes we do
183  /// need to re-interpret the data in SIMD vector registers in big-endian
184  /// mode without emitting such REV instructions.
186 
189 
190  // Reciprocal estimates and steps.
193 
194  // NEON Load/Store with post-increment base updates
218 };
219 
220 } // end namespace AArch64ISD
221 
222 namespace {
223 
224 // Any instruction that defines a 32-bit result zeros out the high half of the
225 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
226 // be copying from a truncate. But any other 32-bit operation will zero-extend
227 // up to 64 bits.
228 // FIXME: X86 also checks for CMOV here. Do we need something similar?
229 static inline bool isDef32(const SDNode &N) {
230  unsigned Opc = N.getOpcode();
231  return Opc != ISD::TRUNCATE && Opc != TargetOpcode::EXTRACT_SUBREG &&
232  Opc != ISD::CopyFromReg;
233 }
234 
235 } // end anonymous namespace
236 
237 class AArch64Subtarget;
239 
241 public:
242  explicit AArch64TargetLowering(const TargetMachine &TM,
243  const AArch64Subtarget &STI);
244 
245  /// Selects the correct CCAssignFn for a given CallingConvention value.
246  CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const;
247 
248  /// Selects the correct CCAssignFn for a given CallingConvention value.
249  CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC) const;
250 
251  /// Determine which of the bits specified in Mask are known to be either zero
252  /// or one and return them in the KnownZero/KnownOne bitsets.
253  void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known,
254  const APInt &DemandedElts,
255  const SelectionDAG &DAG,
256  unsigned Depth = 0) const override;
257 
258  bool targetShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
259  TargetLoweringOpt &TLO) const override;
260 
261  MVT getScalarShiftAmountTy(const DataLayout &DL, EVT) const override;
262 
263  /// Returns true if the target allows unaligned memory accesses of the
264  /// specified type.
265  bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace = 0,
266  unsigned Align = 1,
267  bool *Fast = nullptr) const override;
268 
269  /// Provide custom lowering hooks for some operations.
270  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
271 
272  const char *getTargetNodeName(unsigned Opcode) const override;
273 
274  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
275 
276  /// Returns true if a cast between SrcAS and DestAS is a noop.
277  bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
278  // Addrspacecasts are always noops.
279  return true;
280  }
281 
282  /// This method returns a target specific FastISel object, or null if the
283  /// target does not support "fast" ISel.
285  const TargetLibraryInfo *libInfo) const override;
286 
287  bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
288 
289  bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
290 
291  /// Return true if the given shuffle mask can be codegen'd directly, or if it
292  /// should be stack expanded.
293  bool isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override;
294 
295  /// Return the ISD::SETCC ValueType.
296  EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
297  EVT VT) const override;
298 
299  SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
300 
301  MachineBasicBlock *EmitF128CSEL(MachineInstr &MI,
302  MachineBasicBlock *BB) const;
303 
305  EmitInstrWithCustomInserter(MachineInstr &MI,
306  MachineBasicBlock *MBB) const override;
307 
308  bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
309  unsigned Intrinsic) const override;
310 
311  bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
312  bool isTruncateFree(EVT VT1, EVT VT2) const override;
313 
314  bool isProfitableToHoist(Instruction *I) const override;
315 
316  bool isZExtFree(Type *Ty1, Type *Ty2) const override;
317  bool isZExtFree(EVT VT1, EVT VT2) const override;
318  bool isZExtFree(SDValue Val, EVT VT2) const override;
319 
320  bool hasPairedLoad(EVT LoadedType, unsigned &RequiredAligment) const override;
321 
322  unsigned getMaxSupportedInterleaveFactor() const override { return 4; }
323 
324  bool lowerInterleavedLoad(LoadInst *LI,
326  ArrayRef<unsigned> Indices,
327  unsigned Factor) const override;
328  bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
329  unsigned Factor) const override;
330 
331  bool isLegalAddImmediate(int64_t) const override;
332  bool isLegalICmpImmediate(int64_t) const override;
333 
334  EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
335  bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
336  MachineFunction &MF) const override;
337 
338  /// Return true if the addressing mode represented by AM is legal for this
339  /// target, for a load/store of the specified type.
340  bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
341  unsigned AS,
342  Instruction *I = nullptr) const override;
343 
344  /// \brief Return the cost of the scaling factor used in the addressing
345  /// mode represented by AM for this target, for a load/store
346  /// of the specified type.
347  /// If the AM is supported, the return value must be >= 0.
348  /// If the AM is not supported, it returns a negative value.
349  int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty,
350  unsigned AS) const override;
351 
352  /// Return true if an FMA operation is faster than a pair of fmul and fadd
353  /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
354  /// returns true, otherwise fmuladd is expanded to fmul + fadd.
355  bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
356 
357  const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
358 
359  /// \brief Returns false if N is a bit extraction pattern of (X >> C) & Mask.
360  bool isDesirableToCommuteWithShift(const SDNode *N) const override;
361 
362  /// \brief Returns true if it is beneficial to convert a load of a constant
363  /// to just the constant itself.
364  bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
365  Type *Ty) const override;
366 
367  Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
368  AtomicOrdering Ord) const override;
369  Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
370  Value *Addr, AtomicOrdering Ord) const override;
371 
372  void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const override;
373 
375  shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
376  bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
378  shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
379 
380  bool shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override;
381 
382  bool useLoadStackGuardNode() const override;
384  getPreferredVectorAction(EVT VT) const override;
385 
386  /// If the target has a standard location for the stack protector cookie,
387  /// returns the address of that location. Otherwise, returns nullptr.
388  Value *getIRStackGuard(IRBuilder<> &IRB) const override;
389 
390  /// If the target has a standard location for the unsafe stack pointer,
391  /// returns the address of that location. Otherwise, returns nullptr.
392  Value *getSafeStackPointerLocation(IRBuilder<> &IRB) const override;
393 
394  /// If a physical register, this returns the register that receives the
395  /// exception address on entry to an EH pad.
396  unsigned
397  getExceptionPointerRegister(const Constant *PersonalityFn) const override {
398  // FIXME: This is a guess. Has this been defined yet?
399  return AArch64::X0;
400  }
401 
402  /// If a physical register, this returns the register that receives the
403  /// exception typeid on entry to a landing pad.
404  unsigned
405  getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
406  // FIXME: This is a guess. Has this been defined yet?
407  return AArch64::X1;
408  }
409 
410  bool isIntDivCheap(EVT VT, AttributeList Attr) const override;
411 
412  bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
413  const SelectionDAG &DAG) const override {
414  // Do not merge to float value size (128 bytes) if no implicit
415  // float attribute is set.
416 
417  bool NoFloat = DAG.getMachineFunction().getFunction()->hasFnAttribute(
418  Attribute::NoImplicitFloat);
419 
420  if (NoFloat)
421  return (MemVT.getSizeInBits() <= 64);
422  return true;
423  }
424 
425  bool isCheapToSpeculateCttz() const override {
426  return true;
427  }
428 
429  bool isCheapToSpeculateCtlz() const override {
430  return true;
431  }
432 
433  bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override;
434 
435  bool hasAndNotCompare(SDValue) const override {
436  // 'bics'
437  return true;
438  }
439 
440  bool hasBitPreservingFPLogic(EVT VT) const override {
441  // FIXME: Is this always true? It should be true for vectors at least.
442  return VT == MVT::f32 || VT == MVT::f64;
443  }
444 
445  bool supportSplitCSR(MachineFunction *MF) const override {
447  MF->getFunction()->hasFnAttribute(Attribute::NoUnwind);
448  }
449  void initializeSplitCSR(MachineBasicBlock *Entry) const override;
450  void insertCopiesSplitCSR(
451  MachineBasicBlock *Entry,
452  const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
453 
454  bool supportSwiftError() const override {
455  return true;
456  }
457 
458  /// Returns the size of the platform's va_list object.
459  unsigned getVaListSizeInBits(const DataLayout &DL) const override;
460 
461  /// Returns true if \p VecTy is a legal interleaved access type. This
462  /// function checks the vector element type and the overall width of the
463  /// vector.
464  bool isLegalInterleavedAccessType(VectorType *VecTy,
465  const DataLayout &DL) const;
466 
467  /// Returns the number of interleaved accesses that will be generated when
468  /// lowering accesses of the given type.
469  unsigned getNumInterleavedAccesses(VectorType *VecTy,
470  const DataLayout &DL) const;
471 
472  MachineMemOperand::Flags getMMOFlags(const Instruction &I) const override;
473 
474  bool functionArgumentNeedsConsecutiveRegisters(Type *Ty,
475  CallingConv::ID CallConv,
476  bool isVarArg) const override;
477 private:
478  bool isExtFreeImpl(const Instruction *Ext) const override;
479 
480  /// Keep a pointer to the AArch64Subtarget around so that we can
481  /// make the right decision when generating code for different targets.
482  const AArch64Subtarget *Subtarget;
483 
484  void addTypeForNEON(MVT VT, MVT PromotedBitwiseVT);
485  void addDRTypeForNEON(MVT VT);
486  void addQRTypeForNEON(MVT VT);
487 
488  SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
489  bool isVarArg,
491  const SDLoc &DL, SelectionDAG &DAG,
492  SmallVectorImpl<SDValue> &InVals) const override;
493 
494  SDValue LowerCall(CallLoweringInfo & /*CLI*/,
495  SmallVectorImpl<SDValue> &InVals) const override;
496 
497  SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
498  CallingConv::ID CallConv, bool isVarArg,
500  const SDLoc &DL, SelectionDAG &DAG,
501  SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
502  SDValue ThisVal) const;
503 
504  SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
505 
506  bool isEligibleForTailCallOptimization(
507  SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
509  const SmallVectorImpl<SDValue> &OutVals,
510  const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const;
511 
512  /// Finds the incoming stack arguments which overlap the given fixed stack
513  /// object and incorporates their load into the current chain. This prevents
514  /// an upcoming store from clobbering the stack argument before it's used.
515  SDValue addTokenForArgument(SDValue Chain, SelectionDAG &DAG,
516  MachineFrameInfo &MFI, int ClobberedFI) const;
517 
518  bool DoesCalleeRestoreStack(CallingConv::ID CallCC, bool TailCallOpt) const;
519 
520  void saveVarArgRegisters(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &DL,
521  SDValue &Chain) const;
522 
523  bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
524  bool isVarArg,
526  LLVMContext &Context) const override;
527 
528  SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
530  const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
531  SelectionDAG &DAG) const override;
532 
533  SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
534  unsigned Flag) const;
535  SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG,
536  unsigned Flag) const;
537  SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG,
538  unsigned Flag) const;
539  SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
540  unsigned Flag) const;
541  template <class NodeTy>
542  SDValue getGOT(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const;
543  template <class NodeTy>
544  SDValue getAddrLarge(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const;
545  template <class NodeTy>
546  SDValue getAddr(NodeTy *N, SelectionDAG &DAG, unsigned Flags = 0) const;
547  SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
548  SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
549  SDValue LowerDarwinGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
550  SDValue LowerELFGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
551  SDValue LowerELFTLSDescCallSeq(SDValue SymAddr, const SDLoc &DL,
552  SelectionDAG &DAG) const;
553  SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
554  SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
555  SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
556  SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
558  SDValue TVal, SDValue FVal, const SDLoc &dl,
559  SelectionDAG &DAG) const;
560  SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
561  SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
562  SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
563  SDValue LowerAAPCS_VASTART(SDValue Op, SelectionDAG &DAG) const;
564  SDValue LowerDarwin_VASTART(SDValue Op, SelectionDAG &DAG) const;
565  SDValue LowerWin64_VASTART(SDValue Op, SelectionDAG &DAG) const;
566  SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
567  SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
568  SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
569  SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
574  SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
576  SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
577  SDValue LowerVectorSRA_SRL_SHL(SDValue Op, SelectionDAG &DAG) const;
578  SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
579  SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
580  SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const;
581  SDValue LowerCTPOP(SDValue Op, SelectionDAG &DAG) const;
582  SDValue LowerF128Call(SDValue Op, SelectionDAG &DAG,
583  RTLIB::Libcall Call) const;
584  SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
585  SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
586  SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
587  SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
588  SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
589  SDValue LowerVectorAND(SDValue Op, SelectionDAG &DAG) const;
590  SDValue LowerVectorOR(SDValue Op, SelectionDAG &DAG) const;
592  SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
593  SDValue LowerVECREDUCE(SDValue Op, SelectionDAG &DAG) const;
594 
595  SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
596  std::vector<SDNode *> *Created) const override;
597  SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
598  int &ExtraSteps, bool &UseOneConst,
599  bool Reciprocal) const override;
600  SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
601  int &ExtraSteps) const override;
602  unsigned combineRepeatedFPDivisors() const override;
603 
604  ConstraintType getConstraintType(StringRef Constraint) const override;
605  unsigned getRegisterByName(const char* RegName, EVT VT,
606  SelectionDAG &DAG) const override;
607 
608  /// Examine constraint string and operand type and determine a weight value.
609  /// The operand object must already have been set up with the operand type.
611  getSingleConstraintMatchWeight(AsmOperandInfo &info,
612  const char *constraint) const override;
613 
614  std::pair<unsigned, const TargetRegisterClass *>
615  getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
616  StringRef Constraint, MVT VT) const override;
617 
618  const char *LowerXConstraint(EVT ConstraintVT) const override;
619 
620  void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
621  std::vector<SDValue> &Ops,
622  SelectionDAG &DAG) const override;
623 
624  unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
625  if (ConstraintCode == "Q")
627  // FIXME: clang has code for 'Ump', 'Utf', 'Usa', and 'Ush' but these are
628  // followed by llvm_unreachable so we'll leave them unimplemented in
629  // the backend for now.
630  return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
631  }
632 
633  bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
634  bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
636  ISD::MemIndexedMode &AM, bool &IsInc,
637  SelectionDAG &DAG) const;
638  bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
640  SelectionDAG &DAG) const override;
641  bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
642  SDValue &Offset, ISD::MemIndexedMode &AM,
643  SelectionDAG &DAG) const override;
644 
645  void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
646  SelectionDAG &DAG) const override;
647 
648  bool shouldNormalizeToSelectSequence(LLVMContext &, EVT) const override;
649 };
650 
651 namespace AArch64 {
653  const TargetLibraryInfo *libInfo);
654 } // end namespace AArch64
655 
656 } // end namespace llvm
657 
658 #endif
static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG)
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:43
static SDValue LowerCallResult(SDValue Chain, SDValue InFlag, const SmallVectorImpl< CCValAssign > &RVLocs, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl< SDValue > &InVals)
LowerCallResult - Lower the result values of a call into the appropriate copies out of appropriate ph...
BUILTIN_OP_END - This must be the last enum value in this list.
Definition: ISDOpcodes.h:834
unsigned getExceptionSelectorRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception typeid on entry to a la...
A parsed version of the target data layout string in and methods for querying it. ...
Definition: DataLayout.h:109
constexpr char Align[]
Key for Kernel::Arg::Metadata::mAlign.
This represents an addressing mode of: BaseGV + BaseOffs + BaseReg + Scale*ScaleReg If BaseGV is null...
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
LLVMContext & Context
bool supportSplitCSR(MachineFunction *MF) const override
Return true if the target supports that a subset of CSRs for the given machine function is handled ex...
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
an instruction that atomically checks whether a specified value is in a memory location, and, if it is, stores a new value there.
Definition: Instructions.h:514
static SDValue LowerVACOPY(SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
This class represents a function call, abstracting a target machine&#39;s calling convention.
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit...
bool CCAssignFn(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State)
CCAssignFn - This function assigns a location for Val, updating State to reflect the change...
Function Alias Analysis Results
This instruction constructs a fixed permutation of two input vectors.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Definition: Function.h:262
An instruction for reading from memory.
Definition: Instructions.h:164
an instruction that atomically reads a memory location, combines it with another value, and then stores the result back.
Definition: Instructions.h:677
AtomicExpansionKind
Enum that specifies what an atomic load/AtomicRMWInst is expanded to, if at all.
bool supportSwiftError() const override
Return true if the target supports swifterror attribute.
A convenience struct that encapsulates a DAG, and two SDValues for returning information from TargetL...
static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG)
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
Definition: APFloat.h:42
This provides a uniform API for creating instructions and inserting them into a basic block: either a...
Definition: IRBuilder.h:668
static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, const SparcSubtarget *Subtarget)
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override
Returns true if a cast between SrcAS and DestAS is a noop.
AtomicOrdering
Atomic ordering for LLVM&#39;s memory model.
static SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG)
This is a fast-path instruction selection class that generates poor code and doesn&#39;t support illegal ...
Definition: FastISel.h:67
unsigned getSizeInBits() const
Return the size of the specified value type in bits.
Definition: ValueTypes.h:292
MachineFunction & getMachineFunction() const
Definition: SelectionDAG.h:385
static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG)
This contains information for each constraint that we are lowering.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory)...
Definition: APInt.h:33
An instruction for storing to memory.
Definition: Instructions.h:306
Natural vector cast.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out...
Definition: ISDOpcodes.h:916
virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const
static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG)
FastISel * createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo)
amdgpu Simplify well known AMD library false Value * Callee
unsigned getExceptionPointerRegister(const Constant *PersonalityFn) const override
If a physical register, this returns the register that receives the exception address on entry to an ...
static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG)
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
Flag
These should be considered private to the implementation of the MCInstrDesc class.
Definition: MCInstrDesc.h:121
bool hasAndNotCompare(SDValue) const override
Return true if the target should transform: (X & Y) == Y —> (~X & Y) == 0 (X & Y) != Y —> (~X & Y) ...
Machine Value Type.
static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG)
The instances of the Type class are immutable: once they are created, they are never changed...
Definition: Type.h:46
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:69
static bool getIndexedAddressParts(SDNode *Ptr, EVT VT, SDValue &Base, SDValue &Offset, bool &IsInc, SelectionDAG &DAG)
This is an important base class in LLVM.
Definition: Constant.h:42
static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG, const SparcSubtarget *Subtarget)
lazy value info
Extended Value Type.
Definition: ValueTypes.h:34
const AMDGPUAS & AS
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This structure contains all information that is necessary for lowering calls.
static Value * LowerCTPOP(LLVMContext &Context, Value *V, Instruction *IP)
LowerCTPOP - Emit the code to lower ctpop of V before the specified instruction IP.
CCState - This class holds information needed while lowering arguments and return values...
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Definition: Function.h:194
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Definition: SelectionDAG.h:209
Provides information about what library functions are available for the current target.
AddressSpace
Definition: NVPTXBaseInfo.h:22
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
Definition: ISDOpcodes.h:841
Represents one node in the SelectionDAG.
static bool Enabled
Definition: Statistic.cpp:49
bool hasBitPreservingFPLogic(EVT VT) const override
Return true if it is safe to transform an integer-domain bitwise operation into the equivalent floati...
Class to represent vector types.
Definition: DerivedTypes.h:393
Class for arbitrary precision integers.
Definition: APInt.h:69
bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT, const SelectionDAG &DAG) const override
Returns if it&#39;s reasonable to merge stores to MemVT size.
static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG)
static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
Flags
Flags values. These may be or&#39;d together.
static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG, const SparcTargetLowering &TLI, bool hasHardQuad)
Representation of each machine instruction.
Definition: MachineInstr.h:59
static unsigned getScalingFactorCost(const TargetTransformInfo &TTI, const LSRUse &LU, const Formula &F, const Loop &L)
#define I(x, y, z)
Definition: MD5.cpp:58
#define N
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...
Definition: ISDOpcodes.h:175
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
LegalizeTypeAction
This enum indicates whether a types are legal for a target, and if not, what action should be used to...
LLVM Value Representation.
Definition: Value.h:73
static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG)
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
unsigned getMaxSupportedInterleaveFactor() const override
Get the maximum supported factor for interleaved memory accesses.
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:57
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
bool isCheapToSpeculateCttz() const override
Return true if it is cheap to speculate a call to intrinsic cttz.
TRUNCATE - Completely drop the high bits.
Definition: ISDOpcodes.h:451
bool isCheapToSpeculateCtlz() const override
Return true if it is cheap to speculate a call to intrinsic ctlz.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation...
static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, const X86Subtarget &Subtarget, SelectionDAG &DAG)
This file describes how to lower LLVM code to machine code.
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
Definition: ISDOpcodes.h:871