LLVM  7.0.0svn
AArch64InstPrinter.cpp
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1 //==-- AArch64InstPrinter.cpp - Convert AArch64 MCInst to assembly syntax --==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This class prints an AArch64 MCInst to a .s file.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "AArch64InstPrinter.h"
16 #include "Utils/AArch64BaseInfo.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/ADT/StringExtras.h"
19 #include "llvm/ADT/StringRef.h"
20 #include "llvm/MC/MCAsmInfo.h"
21 #include "llvm/MC/MCExpr.h"
22 #include "llvm/MC/MCInst.h"
23 #include "llvm/MC/MCRegisterInfo.h"
25 #include "llvm/Support/Casting.h"
27 #include "llvm/Support/Format.h"
30 #include <cassert>
31 #include <cstdint>
32 #include <string>
33 
34 using namespace llvm;
35 
36 #define DEBUG_TYPE "asm-printer"
37 
38 #define GET_INSTRUCTION_NAME
39 #define PRINT_ALIAS_INSTR
40 #include "AArch64GenAsmWriter.inc"
41 #define GET_INSTRUCTION_NAME
42 #define PRINT_ALIAS_INSTR
43 #include "AArch64GenAsmWriter1.inc"
44 
46  const MCInstrInfo &MII,
47  const MCRegisterInfo &MRI)
48  : MCInstPrinter(MAI, MII, MRI) {}
49 
51  const MCInstrInfo &MII,
52  const MCRegisterInfo &MRI)
53  : AArch64InstPrinter(MAI, MII, MRI) {}
54 
55 void AArch64InstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
56  // This is for .cfi directives.
57  OS << getRegisterName(RegNo);
58 }
59 
61  StringRef Annot,
62  const MCSubtargetInfo &STI) {
63  // Check for special encodings and print the canonical alias instead.
64 
65  unsigned Opcode = MI->getOpcode();
66 
67  if (Opcode == AArch64::SYSxt)
68  if (printSysAlias(MI, STI, O)) {
69  printAnnotation(O, Annot);
70  return;
71  }
72 
73  // SBFM/UBFM should print to a nicer aliased form if possible.
74  if (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri ||
75  Opcode == AArch64::UBFMXri || Opcode == AArch64::UBFMWri) {
76  const MCOperand &Op0 = MI->getOperand(0);
77  const MCOperand &Op1 = MI->getOperand(1);
78  const MCOperand &Op2 = MI->getOperand(2);
79  const MCOperand &Op3 = MI->getOperand(3);
80 
81  bool IsSigned = (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri);
82  bool Is64Bit = (Opcode == AArch64::SBFMXri || Opcode == AArch64::UBFMXri);
83  if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) {
84  const char *AsmMnemonic = nullptr;
85 
86  switch (Op3.getImm()) {
87  default:
88  break;
89  case 7:
90  if (IsSigned)
91  AsmMnemonic = "sxtb";
92  else if (!Is64Bit)
93  AsmMnemonic = "uxtb";
94  break;
95  case 15:
96  if (IsSigned)
97  AsmMnemonic = "sxth";
98  else if (!Is64Bit)
99  AsmMnemonic = "uxth";
100  break;
101  case 31:
102  // *xtw is only valid for signed 64-bit operations.
103  if (Is64Bit && IsSigned)
104  AsmMnemonic = "sxtw";
105  break;
106  }
107 
108  if (AsmMnemonic) {
109  O << '\t' << AsmMnemonic << '\t' << getRegisterName(Op0.getReg())
110  << ", " << getRegisterName(getWRegFromXReg(Op1.getReg()));
111  printAnnotation(O, Annot);
112  return;
113  }
114  }
115 
116  // All immediate shifts are aliases, implemented using the Bitfield
117  // instruction. In all cases the immediate shift amount shift must be in
118  // the range 0 to (reg.size -1).
119  if (Op2.isImm() && Op3.isImm()) {
120  const char *AsmMnemonic = nullptr;
121  int shift = 0;
122  int64_t immr = Op2.getImm();
123  int64_t imms = Op3.getImm();
124  if (Opcode == AArch64::UBFMWri && imms != 0x1F && ((imms + 1) == immr)) {
125  AsmMnemonic = "lsl";
126  shift = 31 - imms;
127  } else if (Opcode == AArch64::UBFMXri && imms != 0x3f &&
128  ((imms + 1 == immr))) {
129  AsmMnemonic = "lsl";
130  shift = 63 - imms;
131  } else if (Opcode == AArch64::UBFMWri && imms == 0x1f) {
132  AsmMnemonic = "lsr";
133  shift = immr;
134  } else if (Opcode == AArch64::UBFMXri && imms == 0x3f) {
135  AsmMnemonic = "lsr";
136  shift = immr;
137  } else if (Opcode == AArch64::SBFMWri && imms == 0x1f) {
138  AsmMnemonic = "asr";
139  shift = immr;
140  } else if (Opcode == AArch64::SBFMXri && imms == 0x3f) {
141  AsmMnemonic = "asr";
142  shift = immr;
143  }
144  if (AsmMnemonic) {
145  O << '\t' << AsmMnemonic << '\t' << getRegisterName(Op0.getReg())
146  << ", " << getRegisterName(Op1.getReg()) << ", #" << shift;
147  printAnnotation(O, Annot);
148  return;
149  }
150  }
151 
152  // SBFIZ/UBFIZ aliases
153  if (Op2.getImm() > Op3.getImm()) {
154  O << '\t' << (IsSigned ? "sbfiz" : "ubfiz") << '\t'
155  << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op1.getReg())
156  << ", #" << (Is64Bit ? 64 : 32) - Op2.getImm() << ", #" << Op3.getImm() + 1;
157  printAnnotation(O, Annot);
158  return;
159  }
160 
161  // Otherwise SBFX/UBFX is the preferred form
162  O << '\t' << (IsSigned ? "sbfx" : "ubfx") << '\t'
163  << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op1.getReg())
164  << ", #" << Op2.getImm() << ", #" << Op3.getImm() - Op2.getImm() + 1;
165  printAnnotation(O, Annot);
166  return;
167  }
168 
169  if (Opcode == AArch64::BFMXri || Opcode == AArch64::BFMWri) {
170  const MCOperand &Op0 = MI->getOperand(0); // Op1 == Op0
171  const MCOperand &Op2 = MI->getOperand(2);
172  int ImmR = MI->getOperand(3).getImm();
173  int ImmS = MI->getOperand(4).getImm();
174 
175  if ((Op2.getReg() == AArch64::WZR || Op2.getReg() == AArch64::XZR) &&
176  (ImmR == 0 || ImmS < ImmR)) {
177  // BFC takes precedence over its entire range, sligtly differently to BFI.
178  int BitWidth = Opcode == AArch64::BFMXri ? 64 : 32;
179  int LSB = (BitWidth - ImmR) % BitWidth;
180  int Width = ImmS + 1;
181 
182  O << "\tbfc\t" << getRegisterName(Op0.getReg())
183  << ", #" << LSB << ", #" << Width;
184  printAnnotation(O, Annot);
185  return;
186  } else if (ImmS < ImmR) {
187  // BFI alias
188  int BitWidth = Opcode == AArch64::BFMXri ? 64 : 32;
189  int LSB = (BitWidth - ImmR) % BitWidth;
190  int Width = ImmS + 1;
191 
192  O << "\tbfi\t" << getRegisterName(Op0.getReg()) << ", "
193  << getRegisterName(Op2.getReg()) << ", #" << LSB << ", #" << Width;
194  printAnnotation(O, Annot);
195  return;
196  }
197 
198  int LSB = ImmR;
199  int Width = ImmS - ImmR + 1;
200  // Otherwise BFXIL the preferred form
201  O << "\tbfxil\t"
202  << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op2.getReg())
203  << ", #" << LSB << ", #" << Width;
204  printAnnotation(O, Annot);
205  return;
206  }
207 
208  // Symbolic operands for MOVZ, MOVN and MOVK already imply a shift
209  // (e.g. :gottprel_g1: is always going to be "lsl #16") so it should not be
210  // printed.
211  if ((Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi ||
212  Opcode == AArch64::MOVNXi || Opcode == AArch64::MOVNWi) &&
213  MI->getOperand(1).isExpr()) {
214  if (Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi)
215  O << "\tmovz\t";
216  else
217  O << "\tmovn\t";
218 
219  O << getRegisterName(MI->getOperand(0).getReg()) << ", #";
220  MI->getOperand(1).getExpr()->print(O, &MAI);
221  return;
222  }
223 
224  if ((Opcode == AArch64::MOVKXi || Opcode == AArch64::MOVKWi) &&
225  MI->getOperand(2).isExpr()) {
226  O << "\tmovk\t" << getRegisterName(MI->getOperand(0).getReg()) << ", #";
227  MI->getOperand(2).getExpr()->print(O, &MAI);
228  return;
229  }
230 
231  // MOVZ, MOVN and "ORR wzr, #imm" instructions are aliases for MOV, but their
232  // domains overlap so they need to be prioritized. The chain is "MOVZ lsl #0 >
233  // MOVZ lsl #N > MOVN lsl #0 > MOVN lsl #N > ORR". The highest instruction
234  // that can represent the move is the MOV alias, and the rest get printed
235  // normally.
236  if ((Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi) &&
237  MI->getOperand(1).isImm() && MI->getOperand(2).isImm()) {
238  int RegWidth = Opcode == AArch64::MOVZXi ? 64 : 32;
239  int Shift = MI->getOperand(2).getImm();
240  uint64_t Value = (uint64_t)MI->getOperand(1).getImm() << Shift;
241 
242  if (AArch64_AM::isMOVZMovAlias(Value, Shift,
243  Opcode == AArch64::MOVZXi ? 64 : 32)) {
244  O << "\tmov\t" << getRegisterName(MI->getOperand(0).getReg()) << ", #"
245  << formatImm(SignExtend64(Value, RegWidth));
246  return;
247  }
248  }
249 
250  if ((Opcode == AArch64::MOVNXi || Opcode == AArch64::MOVNWi) &&
251  MI->getOperand(1).isImm() && MI->getOperand(2).isImm()) {
252  int RegWidth = Opcode == AArch64::MOVNXi ? 64 : 32;
253  int Shift = MI->getOperand(2).getImm();
254  uint64_t Value = ~((uint64_t)MI->getOperand(1).getImm() << Shift);
255  if (RegWidth == 32)
256  Value = Value & 0xffffffff;
257 
258  if (AArch64_AM::isMOVNMovAlias(Value, Shift, RegWidth)) {
259  O << "\tmov\t" << getRegisterName(MI->getOperand(0).getReg()) << ", #"
260  << formatImm(SignExtend64(Value, RegWidth));
261  return;
262  }
263  }
264 
265  if ((Opcode == AArch64::ORRXri || Opcode == AArch64::ORRWri) &&
266  (MI->getOperand(1).getReg() == AArch64::XZR ||
267  MI->getOperand(1).getReg() == AArch64::WZR) &&
268  MI->getOperand(2).isImm()) {
269  int RegWidth = Opcode == AArch64::ORRXri ? 64 : 32;
271  MI->getOperand(2).getImm(), RegWidth);
272  if (!AArch64_AM::isAnyMOVWMovAlias(Value, RegWidth)) {
273  O << "\tmov\t" << getRegisterName(MI->getOperand(0).getReg()) << ", #"
274  << formatImm(SignExtend64(Value, RegWidth));
275  return;
276  }
277  }
278 
279  if (Opcode == AArch64::CompilerBarrier) {
280  O << '\t' << MAI.getCommentString() << " COMPILER BARRIER";
281  printAnnotation(O, Annot);
282  return;
283  }
284 
285  // Instruction TSB is specified as a one operand instruction, but 'csync' is
286  // not encoded, so for printing it is treated as a special case here:
287  if (Opcode == AArch64::TSB) {
288  O << "\ttsb\tcsync";
289  return;
290  }
291 
292  if (!printAliasInstr(MI, STI, O))
293  printInstruction(MI, STI, O);
294 
295  printAnnotation(O, Annot);
296 }
297 
298 static bool isTblTbxInstruction(unsigned Opcode, StringRef &Layout,
299  bool &IsTbx) {
300  switch (Opcode) {
301  case AArch64::TBXv8i8One:
302  case AArch64::TBXv8i8Two:
303  case AArch64::TBXv8i8Three:
304  case AArch64::TBXv8i8Four:
305  IsTbx = true;
306  Layout = ".8b";
307  return true;
308  case AArch64::TBLv8i8One:
309  case AArch64::TBLv8i8Two:
310  case AArch64::TBLv8i8Three:
311  case AArch64::TBLv8i8Four:
312  IsTbx = false;
313  Layout = ".8b";
314  return true;
315  case AArch64::TBXv16i8One:
316  case AArch64::TBXv16i8Two:
317  case AArch64::TBXv16i8Three:
318  case AArch64::TBXv16i8Four:
319  IsTbx = true;
320  Layout = ".16b";
321  return true;
322  case AArch64::TBLv16i8One:
323  case AArch64::TBLv16i8Two:
324  case AArch64::TBLv16i8Three:
325  case AArch64::TBLv16i8Four:
326  IsTbx = false;
327  Layout = ".16b";
328  return true;
329  default:
330  return false;
331  }
332 }
333 
335  unsigned Opcode;
336  const char *Mnemonic;
337  const char *Layout;
339  bool HasLane;
341 };
342 
343 static const LdStNInstrDesc LdStNInstInfo[] = {
344  { AArch64::LD1i8, "ld1", ".b", 1, true, 0 },
345  { AArch64::LD1i16, "ld1", ".h", 1, true, 0 },
346  { AArch64::LD1i32, "ld1", ".s", 1, true, 0 },
347  { AArch64::LD1i64, "ld1", ".d", 1, true, 0 },
348  { AArch64::LD1i8_POST, "ld1", ".b", 2, true, 1 },
349  { AArch64::LD1i16_POST, "ld1", ".h", 2, true, 2 },
350  { AArch64::LD1i32_POST, "ld1", ".s", 2, true, 4 },
351  { AArch64::LD1i64_POST, "ld1", ".d", 2, true, 8 },
352  { AArch64::LD1Rv16b, "ld1r", ".16b", 0, false, 0 },
353  { AArch64::LD1Rv8h, "ld1r", ".8h", 0, false, 0 },
354  { AArch64::LD1Rv4s, "ld1r", ".4s", 0, false, 0 },
355  { AArch64::LD1Rv2d, "ld1r", ".2d", 0, false, 0 },
356  { AArch64::LD1Rv8b, "ld1r", ".8b", 0, false, 0 },
357  { AArch64::LD1Rv4h, "ld1r", ".4h", 0, false, 0 },
358  { AArch64::LD1Rv2s, "ld1r", ".2s", 0, false, 0 },
359  { AArch64::LD1Rv1d, "ld1r", ".1d", 0, false, 0 },
360  { AArch64::LD1Rv16b_POST, "ld1r", ".16b", 1, false, 1 },
361  { AArch64::LD1Rv8h_POST, "ld1r", ".8h", 1, false, 2 },
362  { AArch64::LD1Rv4s_POST, "ld1r", ".4s", 1, false, 4 },
363  { AArch64::LD1Rv2d_POST, "ld1r", ".2d", 1, false, 8 },
364  { AArch64::LD1Rv8b_POST, "ld1r", ".8b", 1, false, 1 },
365  { AArch64::LD1Rv4h_POST, "ld1r", ".4h", 1, false, 2 },
366  { AArch64::LD1Rv2s_POST, "ld1r", ".2s", 1, false, 4 },
367  { AArch64::LD1Rv1d_POST, "ld1r", ".1d", 1, false, 8 },
368  { AArch64::LD1Onev16b, "ld1", ".16b", 0, false, 0 },
369  { AArch64::LD1Onev8h, "ld1", ".8h", 0, false, 0 },
370  { AArch64::LD1Onev4s, "ld1", ".4s", 0, false, 0 },
371  { AArch64::LD1Onev2d, "ld1", ".2d", 0, false, 0 },
372  { AArch64::LD1Onev8b, "ld1", ".8b", 0, false, 0 },
373  { AArch64::LD1Onev4h, "ld1", ".4h", 0, false, 0 },
374  { AArch64::LD1Onev2s, "ld1", ".2s", 0, false, 0 },
375  { AArch64::LD1Onev1d, "ld1", ".1d", 0, false, 0 },
376  { AArch64::LD1Onev16b_POST, "ld1", ".16b", 1, false, 16 },
377  { AArch64::LD1Onev8h_POST, "ld1", ".8h", 1, false, 16 },
378  { AArch64::LD1Onev4s_POST, "ld1", ".4s", 1, false, 16 },
379  { AArch64::LD1Onev2d_POST, "ld1", ".2d", 1, false, 16 },
380  { AArch64::LD1Onev8b_POST, "ld1", ".8b", 1, false, 8 },
381  { AArch64::LD1Onev4h_POST, "ld1", ".4h", 1, false, 8 },
382  { AArch64::LD1Onev2s_POST, "ld1", ".2s", 1, false, 8 },
383  { AArch64::LD1Onev1d_POST, "ld1", ".1d", 1, false, 8 },
384  { AArch64::LD1Twov16b, "ld1", ".16b", 0, false, 0 },
385  { AArch64::LD1Twov8h, "ld1", ".8h", 0, false, 0 },
386  { AArch64::LD1Twov4s, "ld1", ".4s", 0, false, 0 },
387  { AArch64::LD1Twov2d, "ld1", ".2d", 0, false, 0 },
388  { AArch64::LD1Twov8b, "ld1", ".8b", 0, false, 0 },
389  { AArch64::LD1Twov4h, "ld1", ".4h", 0, false, 0 },
390  { AArch64::LD1Twov2s, "ld1", ".2s", 0, false, 0 },
391  { AArch64::LD1Twov1d, "ld1", ".1d", 0, false, 0 },
392  { AArch64::LD1Twov16b_POST, "ld1", ".16b", 1, false, 32 },
393  { AArch64::LD1Twov8h_POST, "ld1", ".8h", 1, false, 32 },
394  { AArch64::LD1Twov4s_POST, "ld1", ".4s", 1, false, 32 },
395  { AArch64::LD1Twov2d_POST, "ld1", ".2d", 1, false, 32 },
396  { AArch64::LD1Twov8b_POST, "ld1", ".8b", 1, false, 16 },
397  { AArch64::LD1Twov4h_POST, "ld1", ".4h", 1, false, 16 },
398  { AArch64::LD1Twov2s_POST, "ld1", ".2s", 1, false, 16 },
399  { AArch64::LD1Twov1d_POST, "ld1", ".1d", 1, false, 16 },
400  { AArch64::LD1Threev16b, "ld1", ".16b", 0, false, 0 },
401  { AArch64::LD1Threev8h, "ld1", ".8h", 0, false, 0 },
402  { AArch64::LD1Threev4s, "ld1", ".4s", 0, false, 0 },
403  { AArch64::LD1Threev2d, "ld1", ".2d", 0, false, 0 },
404  { AArch64::LD1Threev8b, "ld1", ".8b", 0, false, 0 },
405  { AArch64::LD1Threev4h, "ld1", ".4h", 0, false, 0 },
406  { AArch64::LD1Threev2s, "ld1", ".2s", 0, false, 0 },
407  { AArch64::LD1Threev1d, "ld1", ".1d", 0, false, 0 },
408  { AArch64::LD1Threev16b_POST, "ld1", ".16b", 1, false, 48 },
409  { AArch64::LD1Threev8h_POST, "ld1", ".8h", 1, false, 48 },
410  { AArch64::LD1Threev4s_POST, "ld1", ".4s", 1, false, 48 },
411  { AArch64::LD1Threev2d_POST, "ld1", ".2d", 1, false, 48 },
412  { AArch64::LD1Threev8b_POST, "ld1", ".8b", 1, false, 24 },
413  { AArch64::LD1Threev4h_POST, "ld1", ".4h", 1, false, 24 },
414  { AArch64::LD1Threev2s_POST, "ld1", ".2s", 1, false, 24 },
415  { AArch64::LD1Threev1d_POST, "ld1", ".1d", 1, false, 24 },
416  { AArch64::LD1Fourv16b, "ld1", ".16b", 0, false, 0 },
417  { AArch64::LD1Fourv8h, "ld1", ".8h", 0, false, 0 },
418  { AArch64::LD1Fourv4s, "ld1", ".4s", 0, false, 0 },
419  { AArch64::LD1Fourv2d, "ld1", ".2d", 0, false, 0 },
420  { AArch64::LD1Fourv8b, "ld1", ".8b", 0, false, 0 },
421  { AArch64::LD1Fourv4h, "ld1", ".4h", 0, false, 0 },
422  { AArch64::LD1Fourv2s, "ld1", ".2s", 0, false, 0 },
423  { AArch64::LD1Fourv1d, "ld1", ".1d", 0, false, 0 },
424  { AArch64::LD1Fourv16b_POST, "ld1", ".16b", 1, false, 64 },
425  { AArch64::LD1Fourv8h_POST, "ld1", ".8h", 1, false, 64 },
426  { AArch64::LD1Fourv4s_POST, "ld1", ".4s", 1, false, 64 },
427  { AArch64::LD1Fourv2d_POST, "ld1", ".2d", 1, false, 64 },
428  { AArch64::LD1Fourv8b_POST, "ld1", ".8b", 1, false, 32 },
429  { AArch64::LD1Fourv4h_POST, "ld1", ".4h", 1, false, 32 },
430  { AArch64::LD1Fourv2s_POST, "ld1", ".2s", 1, false, 32 },
431  { AArch64::LD1Fourv1d_POST, "ld1", ".1d", 1, false, 32 },
432  { AArch64::LD2i8, "ld2", ".b", 1, true, 0 },
433  { AArch64::LD2i16, "ld2", ".h", 1, true, 0 },
434  { AArch64::LD2i32, "ld2", ".s", 1, true, 0 },
435  { AArch64::LD2i64, "ld2", ".d", 1, true, 0 },
436  { AArch64::LD2i8_POST, "ld2", ".b", 2, true, 2 },
437  { AArch64::LD2i16_POST, "ld2", ".h", 2, true, 4 },
438  { AArch64::LD2i32_POST, "ld2", ".s", 2, true, 8 },
439  { AArch64::LD2i64_POST, "ld2", ".d", 2, true, 16 },
440  { AArch64::LD2Rv16b, "ld2r", ".16b", 0, false, 0 },
441  { AArch64::LD2Rv8h, "ld2r", ".8h", 0, false, 0 },
442  { AArch64::LD2Rv4s, "ld2r", ".4s", 0, false, 0 },
443  { AArch64::LD2Rv2d, "ld2r", ".2d", 0, false, 0 },
444  { AArch64::LD2Rv8b, "ld2r", ".8b", 0, false, 0 },
445  { AArch64::LD2Rv4h, "ld2r", ".4h", 0, false, 0 },
446  { AArch64::LD2Rv2s, "ld2r", ".2s", 0, false, 0 },
447  { AArch64::LD2Rv1d, "ld2r", ".1d", 0, false, 0 },
448  { AArch64::LD2Rv16b_POST, "ld2r", ".16b", 1, false, 2 },
449  { AArch64::LD2Rv8h_POST, "ld2r", ".8h", 1, false, 4 },
450  { AArch64::LD2Rv4s_POST, "ld2r", ".4s", 1, false, 8 },
451  { AArch64::LD2Rv2d_POST, "ld2r", ".2d", 1, false, 16 },
452  { AArch64::LD2Rv8b_POST, "ld2r", ".8b", 1, false, 2 },
453  { AArch64::LD2Rv4h_POST, "ld2r", ".4h", 1, false, 4 },
454  { AArch64::LD2Rv2s_POST, "ld2r", ".2s", 1, false, 8 },
455  { AArch64::LD2Rv1d_POST, "ld2r", ".1d", 1, false, 16 },
456  { AArch64::LD2Twov16b, "ld2", ".16b", 0, false, 0 },
457  { AArch64::LD2Twov8h, "ld2", ".8h", 0, false, 0 },
458  { AArch64::LD2Twov4s, "ld2", ".4s", 0, false, 0 },
459  { AArch64::LD2Twov2d, "ld2", ".2d", 0, false, 0 },
460  { AArch64::LD2Twov8b, "ld2", ".8b", 0, false, 0 },
461  { AArch64::LD2Twov4h, "ld2", ".4h", 0, false, 0 },
462  { AArch64::LD2Twov2s, "ld2", ".2s", 0, false, 0 },
463  { AArch64::LD2Twov16b_POST, "ld2", ".16b", 1, false, 32 },
464  { AArch64::LD2Twov8h_POST, "ld2", ".8h", 1, false, 32 },
465  { AArch64::LD2Twov4s_POST, "ld2", ".4s", 1, false, 32 },
466  { AArch64::LD2Twov2d_POST, "ld2", ".2d", 1, false, 32 },
467  { AArch64::LD2Twov8b_POST, "ld2", ".8b", 1, false, 16 },
468  { AArch64::LD2Twov4h_POST, "ld2", ".4h", 1, false, 16 },
469  { AArch64::LD2Twov2s_POST, "ld2", ".2s", 1, false, 16 },
470  { AArch64::LD3i8, "ld3", ".b", 1, true, 0 },
471  { AArch64::LD3i16, "ld3", ".h", 1, true, 0 },
472  { AArch64::LD3i32, "ld3", ".s", 1, true, 0 },
473  { AArch64::LD3i64, "ld3", ".d", 1, true, 0 },
474  { AArch64::LD3i8_POST, "ld3", ".b", 2, true, 3 },
475  { AArch64::LD3i16_POST, "ld3", ".h", 2, true, 6 },
476  { AArch64::LD3i32_POST, "ld3", ".s", 2, true, 12 },
477  { AArch64::LD3i64_POST, "ld3", ".d", 2, true, 24 },
478  { AArch64::LD3Rv16b, "ld3r", ".16b", 0, false, 0 },
479  { AArch64::LD3Rv8h, "ld3r", ".8h", 0, false, 0 },
480  { AArch64::LD3Rv4s, "ld3r", ".4s", 0, false, 0 },
481  { AArch64::LD3Rv2d, "ld3r", ".2d", 0, false, 0 },
482  { AArch64::LD3Rv8b, "ld3r", ".8b", 0, false, 0 },
483  { AArch64::LD3Rv4h, "ld3r", ".4h", 0, false, 0 },
484  { AArch64::LD3Rv2s, "ld3r", ".2s", 0, false, 0 },
485  { AArch64::LD3Rv1d, "ld3r", ".1d", 0, false, 0 },
486  { AArch64::LD3Rv16b_POST, "ld3r", ".16b", 1, false, 3 },
487  { AArch64::LD3Rv8h_POST, "ld3r", ".8h", 1, false, 6 },
488  { AArch64::LD3Rv4s_POST, "ld3r", ".4s", 1, false, 12 },
489  { AArch64::LD3Rv2d_POST, "ld3r", ".2d", 1, false, 24 },
490  { AArch64::LD3Rv8b_POST, "ld3r", ".8b", 1, false, 3 },
491  { AArch64::LD3Rv4h_POST, "ld3r", ".4h", 1, false, 6 },
492  { AArch64::LD3Rv2s_POST, "ld3r", ".2s", 1, false, 12 },
493  { AArch64::LD3Rv1d_POST, "ld3r", ".1d", 1, false, 24 },
494  { AArch64::LD3Threev16b, "ld3", ".16b", 0, false, 0 },
495  { AArch64::LD3Threev8h, "ld3", ".8h", 0, false, 0 },
496  { AArch64::LD3Threev4s, "ld3", ".4s", 0, false, 0 },
497  { AArch64::LD3Threev2d, "ld3", ".2d", 0, false, 0 },
498  { AArch64::LD3Threev8b, "ld3", ".8b", 0, false, 0 },
499  { AArch64::LD3Threev4h, "ld3", ".4h", 0, false, 0 },
500  { AArch64::LD3Threev2s, "ld3", ".2s", 0, false, 0 },
501  { AArch64::LD3Threev16b_POST, "ld3", ".16b", 1, false, 48 },
502  { AArch64::LD3Threev8h_POST, "ld3", ".8h", 1, false, 48 },
503  { AArch64::LD3Threev4s_POST, "ld3", ".4s", 1, false, 48 },
504  { AArch64::LD3Threev2d_POST, "ld3", ".2d", 1, false, 48 },
505  { AArch64::LD3Threev8b_POST, "ld3", ".8b", 1, false, 24 },
506  { AArch64::LD3Threev4h_POST, "ld3", ".4h", 1, false, 24 },
507  { AArch64::LD3Threev2s_POST, "ld3", ".2s", 1, false, 24 },
508  { AArch64::LD4i8, "ld4", ".b", 1, true, 0 },
509  { AArch64::LD4i16, "ld4", ".h", 1, true, 0 },
510  { AArch64::LD4i32, "ld4", ".s", 1, true, 0 },
511  { AArch64::LD4i64, "ld4", ".d", 1, true, 0 },
512  { AArch64::LD4i8_POST, "ld4", ".b", 2, true, 4 },
513  { AArch64::LD4i16_POST, "ld4", ".h", 2, true, 8 },
514  { AArch64::LD4i32_POST, "ld4", ".s", 2, true, 16 },
515  { AArch64::LD4i64_POST, "ld4", ".d", 2, true, 32 },
516  { AArch64::LD4Rv16b, "ld4r", ".16b", 0, false, 0 },
517  { AArch64::LD4Rv8h, "ld4r", ".8h", 0, false, 0 },
518  { AArch64::LD4Rv4s, "ld4r", ".4s", 0, false, 0 },
519  { AArch64::LD4Rv2d, "ld4r", ".2d", 0, false, 0 },
520  { AArch64::LD4Rv8b, "ld4r", ".8b", 0, false, 0 },
521  { AArch64::LD4Rv4h, "ld4r", ".4h", 0, false, 0 },
522  { AArch64::LD4Rv2s, "ld4r", ".2s", 0, false, 0 },
523  { AArch64::LD4Rv1d, "ld4r", ".1d", 0, false, 0 },
524  { AArch64::LD4Rv16b_POST, "ld4r", ".16b", 1, false, 4 },
525  { AArch64::LD4Rv8h_POST, "ld4r", ".8h", 1, false, 8 },
526  { AArch64::LD4Rv4s_POST, "ld4r", ".4s", 1, false, 16 },
527  { AArch64::LD4Rv2d_POST, "ld4r", ".2d", 1, false, 32 },
528  { AArch64::LD4Rv8b_POST, "ld4r", ".8b", 1, false, 4 },
529  { AArch64::LD4Rv4h_POST, "ld4r", ".4h", 1, false, 8 },
530  { AArch64::LD4Rv2s_POST, "ld4r", ".2s", 1, false, 16 },
531  { AArch64::LD4Rv1d_POST, "ld4r", ".1d", 1, false, 32 },
532  { AArch64::LD4Fourv16b, "ld4", ".16b", 0, false, 0 },
533  { AArch64::LD4Fourv8h, "ld4", ".8h", 0, false, 0 },
534  { AArch64::LD4Fourv4s, "ld4", ".4s", 0, false, 0 },
535  { AArch64::LD4Fourv2d, "ld4", ".2d", 0, false, 0 },
536  { AArch64::LD4Fourv8b, "ld4", ".8b", 0, false, 0 },
537  { AArch64::LD4Fourv4h, "ld4", ".4h", 0, false, 0 },
538  { AArch64::LD4Fourv2s, "ld4", ".2s", 0, false, 0 },
539  { AArch64::LD4Fourv16b_POST, "ld4", ".16b", 1, false, 64 },
540  { AArch64::LD4Fourv8h_POST, "ld4", ".8h", 1, false, 64 },
541  { AArch64::LD4Fourv4s_POST, "ld4", ".4s", 1, false, 64 },
542  { AArch64::LD4Fourv2d_POST, "ld4", ".2d", 1, false, 64 },
543  { AArch64::LD4Fourv8b_POST, "ld4", ".8b", 1, false, 32 },
544  { AArch64::LD4Fourv4h_POST, "ld4", ".4h", 1, false, 32 },
545  { AArch64::LD4Fourv2s_POST, "ld4", ".2s", 1, false, 32 },
546  { AArch64::ST1i8, "st1", ".b", 0, true, 0 },
547  { AArch64::ST1i16, "st1", ".h", 0, true, 0 },
548  { AArch64::ST1i32, "st1", ".s", 0, true, 0 },
549  { AArch64::ST1i64, "st1", ".d", 0, true, 0 },
550  { AArch64::ST1i8_POST, "st1", ".b", 1, true, 1 },
551  { AArch64::ST1i16_POST, "st1", ".h", 1, true, 2 },
552  { AArch64::ST1i32_POST, "st1", ".s", 1, true, 4 },
553  { AArch64::ST1i64_POST, "st1", ".d", 1, true, 8 },
554  { AArch64::ST1Onev16b, "st1", ".16b", 0, false, 0 },
555  { AArch64::ST1Onev8h, "st1", ".8h", 0, false, 0 },
556  { AArch64::ST1Onev4s, "st1", ".4s", 0, false, 0 },
557  { AArch64::ST1Onev2d, "st1", ".2d", 0, false, 0 },
558  { AArch64::ST1Onev8b, "st1", ".8b", 0, false, 0 },
559  { AArch64::ST1Onev4h, "st1", ".4h", 0, false, 0 },
560  { AArch64::ST1Onev2s, "st1", ".2s", 0, false, 0 },
561  { AArch64::ST1Onev1d, "st1", ".1d", 0, false, 0 },
562  { AArch64::ST1Onev16b_POST, "st1", ".16b", 1, false, 16 },
563  { AArch64::ST1Onev8h_POST, "st1", ".8h", 1, false, 16 },
564  { AArch64::ST1Onev4s_POST, "st1", ".4s", 1, false, 16 },
565  { AArch64::ST1Onev2d_POST, "st1", ".2d", 1, false, 16 },
566  { AArch64::ST1Onev8b_POST, "st1", ".8b", 1, false, 8 },
567  { AArch64::ST1Onev4h_POST, "st1", ".4h", 1, false, 8 },
568  { AArch64::ST1Onev2s_POST, "st1", ".2s", 1, false, 8 },
569  { AArch64::ST1Onev1d_POST, "st1", ".1d", 1, false, 8 },
570  { AArch64::ST1Twov16b, "st1", ".16b", 0, false, 0 },
571  { AArch64::ST1Twov8h, "st1", ".8h", 0, false, 0 },
572  { AArch64::ST1Twov4s, "st1", ".4s", 0, false, 0 },
573  { AArch64::ST1Twov2d, "st1", ".2d", 0, false, 0 },
574  { AArch64::ST1Twov8b, "st1", ".8b", 0, false, 0 },
575  { AArch64::ST1Twov4h, "st1", ".4h", 0, false, 0 },
576  { AArch64::ST1Twov2s, "st1", ".2s", 0, false, 0 },
577  { AArch64::ST1Twov1d, "st1", ".1d", 0, false, 0 },
578  { AArch64::ST1Twov16b_POST, "st1", ".16b", 1, false, 32 },
579  { AArch64::ST1Twov8h_POST, "st1", ".8h", 1, false, 32 },
580  { AArch64::ST1Twov4s_POST, "st1", ".4s", 1, false, 32 },
581  { AArch64::ST1Twov2d_POST, "st1", ".2d", 1, false, 32 },
582  { AArch64::ST1Twov8b_POST, "st1", ".8b", 1, false, 16 },
583  { AArch64::ST1Twov4h_POST, "st1", ".4h", 1, false, 16 },
584  { AArch64::ST1Twov2s_POST, "st1", ".2s", 1, false, 16 },
585  { AArch64::ST1Twov1d_POST, "st1", ".1d", 1, false, 16 },
586  { AArch64::ST1Threev16b, "st1", ".16b", 0, false, 0 },
587  { AArch64::ST1Threev8h, "st1", ".8h", 0, false, 0 },
588  { AArch64::ST1Threev4s, "st1", ".4s", 0, false, 0 },
589  { AArch64::ST1Threev2d, "st1", ".2d", 0, false, 0 },
590  { AArch64::ST1Threev8b, "st1", ".8b", 0, false, 0 },
591  { AArch64::ST1Threev4h, "st1", ".4h", 0, false, 0 },
592  { AArch64::ST1Threev2s, "st1", ".2s", 0, false, 0 },
593  { AArch64::ST1Threev1d, "st1", ".1d", 0, false, 0 },
594  { AArch64::ST1Threev16b_POST, "st1", ".16b", 1, false, 48 },
595  { AArch64::ST1Threev8h_POST, "st1", ".8h", 1, false, 48 },
596  { AArch64::ST1Threev4s_POST, "st1", ".4s", 1, false, 48 },
597  { AArch64::ST1Threev2d_POST, "st1", ".2d", 1, false, 48 },
598  { AArch64::ST1Threev8b_POST, "st1", ".8b", 1, false, 24 },
599  { AArch64::ST1Threev4h_POST, "st1", ".4h", 1, false, 24 },
600  { AArch64::ST1Threev2s_POST, "st1", ".2s", 1, false, 24 },
601  { AArch64::ST1Threev1d_POST, "st1", ".1d", 1, false, 24 },
602  { AArch64::ST1Fourv16b, "st1", ".16b", 0, false, 0 },
603  { AArch64::ST1Fourv8h, "st1", ".8h", 0, false, 0 },
604  { AArch64::ST1Fourv4s, "st1", ".4s", 0, false, 0 },
605  { AArch64::ST1Fourv2d, "st1", ".2d", 0, false, 0 },
606  { AArch64::ST1Fourv8b, "st1", ".8b", 0, false, 0 },
607  { AArch64::ST1Fourv4h, "st1", ".4h", 0, false, 0 },
608  { AArch64::ST1Fourv2s, "st1", ".2s", 0, false, 0 },
609  { AArch64::ST1Fourv1d, "st1", ".1d", 0, false, 0 },
610  { AArch64::ST1Fourv16b_POST, "st1", ".16b", 1, false, 64 },
611  { AArch64::ST1Fourv8h_POST, "st1", ".8h", 1, false, 64 },
612  { AArch64::ST1Fourv4s_POST, "st1", ".4s", 1, false, 64 },
613  { AArch64::ST1Fourv2d_POST, "st1", ".2d", 1, false, 64 },
614  { AArch64::ST1Fourv8b_POST, "st1", ".8b", 1, false, 32 },
615  { AArch64::ST1Fourv4h_POST, "st1", ".4h", 1, false, 32 },
616  { AArch64::ST1Fourv2s_POST, "st1", ".2s", 1, false, 32 },
617  { AArch64::ST1Fourv1d_POST, "st1", ".1d", 1, false, 32 },
618  { AArch64::ST2i8, "st2", ".b", 0, true, 0 },
619  { AArch64::ST2i16, "st2", ".h", 0, true, 0 },
620  { AArch64::ST2i32, "st2", ".s", 0, true, 0 },
621  { AArch64::ST2i64, "st2", ".d", 0, true, 0 },
622  { AArch64::ST2i8_POST, "st2", ".b", 1, true, 2 },
623  { AArch64::ST2i16_POST, "st2", ".h", 1, true, 4 },
624  { AArch64::ST2i32_POST, "st2", ".s", 1, true, 8 },
625  { AArch64::ST2i64_POST, "st2", ".d", 1, true, 16 },
626  { AArch64::ST2Twov16b, "st2", ".16b", 0, false, 0 },
627  { AArch64::ST2Twov8h, "st2", ".8h", 0, false, 0 },
628  { AArch64::ST2Twov4s, "st2", ".4s", 0, false, 0 },
629  { AArch64::ST2Twov2d, "st2", ".2d", 0, false, 0 },
630  { AArch64::ST2Twov8b, "st2", ".8b", 0, false, 0 },
631  { AArch64::ST2Twov4h, "st2", ".4h", 0, false, 0 },
632  { AArch64::ST2Twov2s, "st2", ".2s", 0, false, 0 },
633  { AArch64::ST2Twov16b_POST, "st2", ".16b", 1, false, 32 },
634  { AArch64::ST2Twov8h_POST, "st2", ".8h", 1, false, 32 },
635  { AArch64::ST2Twov4s_POST, "st2", ".4s", 1, false, 32 },
636  { AArch64::ST2Twov2d_POST, "st2", ".2d", 1, false, 32 },
637  { AArch64::ST2Twov8b_POST, "st2", ".8b", 1, false, 16 },
638  { AArch64::ST2Twov4h_POST, "st2", ".4h", 1, false, 16 },
639  { AArch64::ST2Twov2s_POST, "st2", ".2s", 1, false, 16 },
640  { AArch64::ST3i8, "st3", ".b", 0, true, 0 },
641  { AArch64::ST3i16, "st3", ".h", 0, true, 0 },
642  { AArch64::ST3i32, "st3", ".s", 0, true, 0 },
643  { AArch64::ST3i64, "st3", ".d", 0, true, 0 },
644  { AArch64::ST3i8_POST, "st3", ".b", 1, true, 3 },
645  { AArch64::ST3i16_POST, "st3", ".h", 1, true, 6 },
646  { AArch64::ST3i32_POST, "st3", ".s", 1, true, 12 },
647  { AArch64::ST3i64_POST, "st3", ".d", 1, true, 24 },
648  { AArch64::ST3Threev16b, "st3", ".16b", 0, false, 0 },
649  { AArch64::ST3Threev8h, "st3", ".8h", 0, false, 0 },
650  { AArch64::ST3Threev4s, "st3", ".4s", 0, false, 0 },
651  { AArch64::ST3Threev2d, "st3", ".2d", 0, false, 0 },
652  { AArch64::ST3Threev8b, "st3", ".8b", 0, false, 0 },
653  { AArch64::ST3Threev4h, "st3", ".4h", 0, false, 0 },
654  { AArch64::ST3Threev2s, "st3", ".2s", 0, false, 0 },
655  { AArch64::ST3Threev16b_POST, "st3", ".16b", 1, false, 48 },
656  { AArch64::ST3Threev8h_POST, "st3", ".8h", 1, false, 48 },
657  { AArch64::ST3Threev4s_POST, "st3", ".4s", 1, false, 48 },
658  { AArch64::ST3Threev2d_POST, "st3", ".2d", 1, false, 48 },
659  { AArch64::ST3Threev8b_POST, "st3", ".8b", 1, false, 24 },
660  { AArch64::ST3Threev4h_POST, "st3", ".4h", 1, false, 24 },
661  { AArch64::ST3Threev2s_POST, "st3", ".2s", 1, false, 24 },
662  { AArch64::ST4i8, "st4", ".b", 0, true, 0 },
663  { AArch64::ST4i16, "st4", ".h", 0, true, 0 },
664  { AArch64::ST4i32, "st4", ".s", 0, true, 0 },
665  { AArch64::ST4i64, "st4", ".d", 0, true, 0 },
666  { AArch64::ST4i8_POST, "st4", ".b", 1, true, 4 },
667  { AArch64::ST4i16_POST, "st4", ".h", 1, true, 8 },
668  { AArch64::ST4i32_POST, "st4", ".s", 1, true, 16 },
669  { AArch64::ST4i64_POST, "st4", ".d", 1, true, 32 },
670  { AArch64::ST4Fourv16b, "st4", ".16b", 0, false, 0 },
671  { AArch64::ST4Fourv8h, "st4", ".8h", 0, false, 0 },
672  { AArch64::ST4Fourv4s, "st4", ".4s", 0, false, 0 },
673  { AArch64::ST4Fourv2d, "st4", ".2d", 0, false, 0 },
674  { AArch64::ST4Fourv8b, "st4", ".8b", 0, false, 0 },
675  { AArch64::ST4Fourv4h, "st4", ".4h", 0, false, 0 },
676  { AArch64::ST4Fourv2s, "st4", ".2s", 0, false, 0 },
677  { AArch64::ST4Fourv16b_POST, "st4", ".16b", 1, false, 64 },
678  { AArch64::ST4Fourv8h_POST, "st4", ".8h", 1, false, 64 },
679  { AArch64::ST4Fourv4s_POST, "st4", ".4s", 1, false, 64 },
680  { AArch64::ST4Fourv2d_POST, "st4", ".2d", 1, false, 64 },
681  { AArch64::ST4Fourv8b_POST, "st4", ".8b", 1, false, 32 },
682  { AArch64::ST4Fourv4h_POST, "st4", ".4h", 1, false, 32 },
683  { AArch64::ST4Fourv2s_POST, "st4", ".2s", 1, false, 32 },
684 };
685 
686 static const LdStNInstrDesc *getLdStNInstrDesc(unsigned Opcode) {
687  unsigned Idx;
688  for (Idx = 0; Idx != array_lengthof(LdStNInstInfo); ++Idx)
689  if (LdStNInstInfo[Idx].Opcode == Opcode)
690  return &LdStNInstInfo[Idx];
691 
692  return nullptr;
693 }
694 
696  StringRef Annot,
697  const MCSubtargetInfo &STI) {
698  unsigned Opcode = MI->getOpcode();
699  StringRef Layout;
700 
701  bool IsTbx;
702  if (isTblTbxInstruction(MI->getOpcode(), Layout, IsTbx)) {
703  O << "\t" << (IsTbx ? "tbx" : "tbl") << Layout << '\t'
704  << getRegisterName(MI->getOperand(0).getReg(), AArch64::vreg) << ", ";
705 
706  unsigned ListOpNum = IsTbx ? 2 : 1;
707  printVectorList(MI, ListOpNum, STI, O, "");
708 
709  O << ", "
710  << getRegisterName(MI->getOperand(ListOpNum + 1).getReg(), AArch64::vreg);
711  printAnnotation(O, Annot);
712  return;
713  }
714 
715  if (const LdStNInstrDesc *LdStDesc = getLdStNInstrDesc(Opcode)) {
716  O << "\t" << LdStDesc->Mnemonic << LdStDesc->Layout << '\t';
717 
718  // Now onto the operands: first a vector list with possible lane
719  // specifier. E.g. { v0 }[2]
720  int OpNum = LdStDesc->ListOperand;
721  printVectorList(MI, OpNum++, STI, O, "");
722 
723  if (LdStDesc->HasLane)
724  O << '[' << MI->getOperand(OpNum++).getImm() << ']';
725 
726  // Next the address: [xN]
727  unsigned AddrReg = MI->getOperand(OpNum++).getReg();
728  O << ", [" << getRegisterName(AddrReg) << ']';
729 
730  // Finally, there might be a post-indexed offset.
731  if (LdStDesc->NaturalOffset != 0) {
732  unsigned Reg = MI->getOperand(OpNum++).getReg();
733  if (Reg != AArch64::XZR)
734  O << ", " << getRegisterName(Reg);
735  else {
736  assert(LdStDesc->NaturalOffset && "no offset on post-inc instruction?");
737  O << ", #" << LdStDesc->NaturalOffset;
738  }
739  }
740 
741  printAnnotation(O, Annot);
742  return;
743  }
744 
745  AArch64InstPrinter::printInst(MI, O, Annot, STI);
746 }
747 
749  const MCSubtargetInfo &STI,
750  raw_ostream &O) {
751 #ifndef NDEBUG
752  unsigned Opcode = MI->getOpcode();
753  assert(Opcode == AArch64::SYSxt && "Invalid opcode for SYS alias!");
754 #endif
755 
756  const MCOperand &Op1 = MI->getOperand(0);
757  const MCOperand &Cn = MI->getOperand(1);
758  const MCOperand &Cm = MI->getOperand(2);
759  const MCOperand &Op2 = MI->getOperand(3);
760 
761  unsigned Op1Val = Op1.getImm();
762  unsigned CnVal = Cn.getImm();
763  unsigned CmVal = Cm.getImm();
764  unsigned Op2Val = Op2.getImm();
765 
766  uint16_t Encoding = Op2Val;
767  Encoding |= CmVal << 3;
768  Encoding |= CnVal << 7;
769  Encoding |= Op1Val << 11;
770 
771  bool NeedsReg;
772  std::string Ins;
773  std::string Name;
774 
775  if (CnVal == 7) {
776  switch (CmVal) {
777  default: return false;
778  // IC aliases
779  case 1: case 5: {
780  const AArch64IC::IC *IC = AArch64IC::lookupICByEncoding(Encoding);
781  if (!IC || !IC->haveFeatures(STI.getFeatureBits()))
782  return false;
783 
784  NeedsReg = IC->NeedsReg;
785  Ins = "ic\t";
786  Name = std::string(IC->Name);
787  }
788  break;
789  // DC aliases
790  case 4: case 6: case 10: case 11: case 12: case 14:
791  {
792  const AArch64DC::DC *DC = AArch64DC::lookupDCByEncoding(Encoding);
793  if (!DC || !DC->haveFeatures(STI.getFeatureBits()))
794  return false;
795 
796  NeedsReg = true;
797  Ins = "dc\t";
798  Name = std::string(DC->Name);
799  }
800  break;
801  // AT aliases
802  case 8: case 9: {
803  const AArch64AT::AT *AT = AArch64AT::lookupATByEncoding(Encoding);
804  if (!AT || !AT->haveFeatures(STI.getFeatureBits()))
805  return false;
806 
807  NeedsReg = true;
808  Ins = "at\t";
809  Name = std::string(AT->Name);
810  }
811  break;
812  }
813  } else if (CnVal == 8) {
814  // TLBI aliases
815  const AArch64TLBI::TLBI *TLBI = AArch64TLBI::lookupTLBIByEncoding(Encoding);
816  if (!TLBI || !TLBI->haveFeatures(STI.getFeatureBits()))
817  return false;
818 
819  NeedsReg = TLBI->NeedsReg;
820  Ins = "tlbi\t";
821  Name = std::string(TLBI->Name);
822  }
823  else
824  return false;
825 
826  std::string Str = Ins + Name;
827  std::transform(Str.begin(), Str.end(), Str.begin(), ::tolower);
828 
829  O << '\t' << Str;
830  if (NeedsReg)
831  O << ", " << getRegisterName(MI->getOperand(4).getReg());
832 
833  return true;
834 }
835 
836 void AArch64InstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
837  const MCSubtargetInfo &STI,
838  raw_ostream &O) {
839  const MCOperand &Op = MI->getOperand(OpNo);
840  if (Op.isReg()) {
841  unsigned Reg = Op.getReg();
842  O << getRegisterName(Reg);
843  } else if (Op.isImm()) {
844  printImm(MI, OpNo, STI, O);
845  } else {
846  assert(Op.isExpr() && "unknown operand kind in printOperand");
847  Op.getExpr()->print(O, &MAI);
848  }
849 }
850 
851 void AArch64InstPrinter::printImm(const MCInst *MI, unsigned OpNo,
852  const MCSubtargetInfo &STI,
853  raw_ostream &O) {
854  const MCOperand &Op = MI->getOperand(OpNo);
855  O << "#" << formatImm(Op.getImm());
856 }
857 
858 void AArch64InstPrinter::printImmHex(const MCInst *MI, unsigned OpNo,
859  const MCSubtargetInfo &STI,
860  raw_ostream &O) {
861  const MCOperand &Op = MI->getOperand(OpNo);
862  O << format("#%#llx", Op.getImm());
863 }
864 
866  unsigned Imm, raw_ostream &O) {
867  const MCOperand &Op = MI->getOperand(OpNo);
868  if (Op.isReg()) {
869  unsigned Reg = Op.getReg();
870  if (Reg == AArch64::XZR)
871  O << "#" << Imm;
872  else
873  O << getRegisterName(Reg);
874  } else
875  llvm_unreachable("unknown operand kind in printPostIncOperand64");
876 }
877 
878 void AArch64InstPrinter::printVRegOperand(const MCInst *MI, unsigned OpNo,
879  const MCSubtargetInfo &STI,
880  raw_ostream &O) {
881  const MCOperand &Op = MI->getOperand(OpNo);
882  assert(Op.isReg() && "Non-register vreg operand!");
883  unsigned Reg = Op.getReg();
884  O << getRegisterName(Reg, AArch64::vreg);
885 }
886 
888  const MCSubtargetInfo &STI,
889  raw_ostream &O) {
890  const MCOperand &Op = MI->getOperand(OpNo);
891  assert(Op.isImm() && "System instruction C[nm] operands must be immediates!");
892  O << "c" << Op.getImm();
893 }
894 
895 void AArch64InstPrinter::printAddSubImm(const MCInst *MI, unsigned OpNum,
896  const MCSubtargetInfo &STI,
897  raw_ostream &O) {
898  const MCOperand &MO = MI->getOperand(OpNum);
899  if (MO.isImm()) {
900  unsigned Val = (MO.getImm() & 0xfff);
901  assert(Val == MO.getImm() && "Add/sub immediate out of range!");
902  unsigned Shift =
903  AArch64_AM::getShiftValue(MI->getOperand(OpNum + 1).getImm());
904  O << '#' << formatImm(Val);
905  if (Shift != 0)
906  printShifter(MI, OpNum + 1, STI, O);
907 
908  if (CommentStream)
909  *CommentStream << '=' << formatImm(Val << Shift) << '\n';
910  } else {
911  assert(MO.isExpr() && "Unexpected operand type!");
912  MO.getExpr()->print(O, &MAI);
913  printShifter(MI, OpNum + 1, STI, O);
914  }
915 }
916 
917 template <typename T>
918 void AArch64InstPrinter::printLogicalImm(const MCInst *MI, unsigned OpNum,
919  const MCSubtargetInfo &STI,
920  raw_ostream &O) {
921  uint64_t Val = MI->getOperand(OpNum).getImm();
922  O << "#0x";
923  O.write_hex(AArch64_AM::decodeLogicalImmediate(Val, 8 * sizeof(T)));
924 }
925 
926 void AArch64InstPrinter::printShifter(const MCInst *MI, unsigned OpNum,
927  const MCSubtargetInfo &STI,
928  raw_ostream &O) {
929  unsigned Val = MI->getOperand(OpNum).getImm();
930  // LSL #0 should not be printed.
932  AArch64_AM::getShiftValue(Val) == 0)
933  return;
935  << " #" << AArch64_AM::getShiftValue(Val);
936 }
937 
939  const MCSubtargetInfo &STI,
940  raw_ostream &O) {
941  O << getRegisterName(MI->getOperand(OpNum).getReg());
942  printShifter(MI, OpNum + 1, STI, O);
943 }
944 
946  const MCSubtargetInfo &STI,
947  raw_ostream &O) {
948  O << getRegisterName(MI->getOperand(OpNum).getReg());
949  printArithExtend(MI, OpNum + 1, STI, O);
950 }
951 
952 void AArch64InstPrinter::printArithExtend(const MCInst *MI, unsigned OpNum,
953  const MCSubtargetInfo &STI,
954  raw_ostream &O) {
955  unsigned Val = MI->getOperand(OpNum).getImm();
957  unsigned ShiftVal = AArch64_AM::getArithShiftValue(Val);
958 
959  // If the destination or first source register operand is [W]SP, print
960  // UXTW/UXTX as LSL, and if the shift amount is also zero, print nothing at
961  // all.
962  if (ExtType == AArch64_AM::UXTW || ExtType == AArch64_AM::UXTX) {
963  unsigned Dest = MI->getOperand(0).getReg();
964  unsigned Src1 = MI->getOperand(1).getReg();
965  if ( ((Dest == AArch64::SP || Src1 == AArch64::SP) &&
966  ExtType == AArch64_AM::UXTX) ||
967  ((Dest == AArch64::WSP || Src1 == AArch64::WSP) &&
968  ExtType == AArch64_AM::UXTW) ) {
969  if (ShiftVal != 0)
970  O << ", lsl #" << ShiftVal;
971  return;
972  }
973  }
974  O << ", " << AArch64_AM::getShiftExtendName(ExtType);
975  if (ShiftVal != 0)
976  O << " #" << ShiftVal;
977 }
978 
979 static void printMemExtendImpl(bool SignExtend, bool DoShift,
980  unsigned Width, char SrcRegKind,
981  raw_ostream &O) {
982  // sxtw, sxtx, uxtw or lsl (== uxtx)
983  bool IsLSL = !SignExtend && SrcRegKind == 'x';
984  if (IsLSL)
985  O << "lsl";
986  else
987  O << (SignExtend ? 's' : 'u') << "xt" << SrcRegKind;
988 
989  if (DoShift || IsLSL)
990  O << " #" << Log2_32(Width / 8);
991 }
992 
993 void AArch64InstPrinter::printMemExtend(const MCInst *MI, unsigned OpNum,
994  raw_ostream &O, char SrcRegKind,
995  unsigned Width) {
996  bool SignExtend = MI->getOperand(OpNum).getImm();
997  bool DoShift = MI->getOperand(OpNum + 1).getImm();
998  printMemExtendImpl(SignExtend, DoShift, Width, SrcRegKind, O);
999 }
1000 
1001 template <bool SignExtend, int ExtWidth, char SrcRegKind, char Suffix>
1003  unsigned OpNum,
1004  const MCSubtargetInfo &STI,
1005  raw_ostream &O) {
1006  printOperand(MI, OpNum, STI, O);
1007  if (Suffix == 's' || Suffix == 'd')
1008  O << '.' << Suffix;
1009  else
1010  assert(Suffix == 0 && "Unsupported suffix size");
1011 
1012  bool DoShift = ExtWidth != 8;
1013  if (SignExtend || DoShift || SrcRegKind == 'w') {
1014  O << ", ";
1015  printMemExtendImpl(SignExtend, DoShift, ExtWidth, SrcRegKind, O);
1016  }
1017 }
1018 
1019 void AArch64InstPrinter::printCondCode(const MCInst *MI, unsigned OpNum,
1020  const MCSubtargetInfo &STI,
1021  raw_ostream &O) {
1023  O << AArch64CC::getCondCodeName(CC);
1024 }
1025 
1027  const MCSubtargetInfo &STI,
1028  raw_ostream &O) {
1031 }
1032 
1033 void AArch64InstPrinter::printAMNoIndex(const MCInst *MI, unsigned OpNum,
1034  const MCSubtargetInfo &STI,
1035  raw_ostream &O) {
1036  O << '[' << getRegisterName(MI->getOperand(OpNum).getReg()) << ']';
1037 }
1038 
1039 template<int Scale>
1040 void AArch64InstPrinter::printImmScale(const MCInst *MI, unsigned OpNum,
1041  const MCSubtargetInfo &STI,
1042  raw_ostream &O) {
1043  O << '#' << formatImm(Scale * MI->getOperand(OpNum).getImm());
1044 }
1045 
1047  unsigned Scale, raw_ostream &O) {
1048  const MCOperand MO = MI->getOperand(OpNum);
1049  if (MO.isImm()) {
1050  O << "#" << formatImm(MO.getImm() * Scale);
1051  } else {
1052  assert(MO.isExpr() && "Unexpected operand type!");
1053  MO.getExpr()->print(O, &MAI);
1054  }
1055 }
1056 
1057 void AArch64InstPrinter::printAMIndexedWB(const MCInst *MI, unsigned OpNum,
1058  unsigned Scale, raw_ostream &O) {
1059  const MCOperand MO1 = MI->getOperand(OpNum + 1);
1060  O << '[' << getRegisterName(MI->getOperand(OpNum).getReg());
1061  if (MO1.isImm()) {
1062  O << ", #" << formatImm(MO1.getImm() * Scale);
1063  } else {
1064  assert(MO1.isExpr() && "Unexpected operand type!");
1065  O << ", ";
1066  MO1.getExpr()->print(O, &MAI);
1067  }
1068  O << ']';
1069 }
1070 
1071 template <bool IsSVEPrefetch>
1072 void AArch64InstPrinter::printPrefetchOp(const MCInst *MI, unsigned OpNum,
1073  const MCSubtargetInfo &STI,
1074  raw_ostream &O) {
1075  unsigned prfop = MI->getOperand(OpNum).getImm();
1076  if (IsSVEPrefetch) {
1077  if (auto PRFM = AArch64SVEPRFM::lookupSVEPRFMByEncoding(prfop)) {
1078  O << PRFM->Name;
1079  return;
1080  }
1081  } else if (auto PRFM = AArch64PRFM::lookupPRFMByEncoding(prfop)) {
1082  O << PRFM->Name;
1083  return;
1084  }
1085 
1086  O << '#' << formatImm(prfop);
1087 }
1088 
1089 void AArch64InstPrinter::printPSBHintOp(const MCInst *MI, unsigned OpNum,
1090  const MCSubtargetInfo &STI,
1091  raw_ostream &O) {
1092  unsigned psbhintop = MI->getOperand(OpNum).getImm();
1093  auto PSB = AArch64PSBHint::lookupPSBByEncoding(psbhintop);
1094  if (PSB)
1095  O << PSB->Name;
1096  else
1097  O << '#' << formatImm(psbhintop);
1098 }
1099 
1101  const MCSubtargetInfo &STI,
1102  raw_ostream &O) {
1103  const MCOperand &MO = MI->getOperand(OpNum);
1104  float FPImm =
1105  MO.isFPImm() ? MO.getFPImm() : AArch64_AM::getFPImmFloat(MO.getImm());
1106 
1107  // 8 decimal places are enough to perfectly represent permitted floats.
1108  O << format("#%.8f", FPImm);
1109 }
1110 
1111 static unsigned getNextVectorRegister(unsigned Reg, unsigned Stride = 1) {
1112  while (Stride--) {
1113  switch (Reg) {
1114  default:
1115  llvm_unreachable("Vector register expected!");
1116  case AArch64::Q0: Reg = AArch64::Q1; break;
1117  case AArch64::Q1: Reg = AArch64::Q2; break;
1118  case AArch64::Q2: Reg = AArch64::Q3; break;
1119  case AArch64::Q3: Reg = AArch64::Q4; break;
1120  case AArch64::Q4: Reg = AArch64::Q5; break;
1121  case AArch64::Q5: Reg = AArch64::Q6; break;
1122  case AArch64::Q6: Reg = AArch64::Q7; break;
1123  case AArch64::Q7: Reg = AArch64::Q8; break;
1124  case AArch64::Q8: Reg = AArch64::Q9; break;
1125  case AArch64::Q9: Reg = AArch64::Q10; break;
1126  case AArch64::Q10: Reg = AArch64::Q11; break;
1127  case AArch64::Q11: Reg = AArch64::Q12; break;
1128  case AArch64::Q12: Reg = AArch64::Q13; break;
1129  case AArch64::Q13: Reg = AArch64::Q14; break;
1130  case AArch64::Q14: Reg = AArch64::Q15; break;
1131  case AArch64::Q15: Reg = AArch64::Q16; break;
1132  case AArch64::Q16: Reg = AArch64::Q17; break;
1133  case AArch64::Q17: Reg = AArch64::Q18; break;
1134  case AArch64::Q18: Reg = AArch64::Q19; break;
1135  case AArch64::Q19: Reg = AArch64::Q20; break;
1136  case AArch64::Q20: Reg = AArch64::Q21; break;
1137  case AArch64::Q21: Reg = AArch64::Q22; break;
1138  case AArch64::Q22: Reg = AArch64::Q23; break;
1139  case AArch64::Q23: Reg = AArch64::Q24; break;
1140  case AArch64::Q24: Reg = AArch64::Q25; break;
1141  case AArch64::Q25: Reg = AArch64::Q26; break;
1142  case AArch64::Q26: Reg = AArch64::Q27; break;
1143  case AArch64::Q27: Reg = AArch64::Q28; break;
1144  case AArch64::Q28: Reg = AArch64::Q29; break;
1145  case AArch64::Q29: Reg = AArch64::Q30; break;
1146  case AArch64::Q30: Reg = AArch64::Q31; break;
1147  // Vector lists can wrap around.
1148  case AArch64::Q31:
1149  Reg = AArch64::Q0;
1150  break;
1151  case AArch64::Z0: Reg = AArch64::Z1; break;
1152  case AArch64::Z1: Reg = AArch64::Z2; break;
1153  case AArch64::Z2: Reg = AArch64::Z3; break;
1154  case AArch64::Z3: Reg = AArch64::Z4; break;
1155  case AArch64::Z4: Reg = AArch64::Z5; break;
1156  case AArch64::Z5: Reg = AArch64::Z6; break;
1157  case AArch64::Z6: Reg = AArch64::Z7; break;
1158  case AArch64::Z7: Reg = AArch64::Z8; break;
1159  case AArch64::Z8: Reg = AArch64::Z9; break;
1160  case AArch64::Z9: Reg = AArch64::Z10; break;
1161  case AArch64::Z10: Reg = AArch64::Z11; break;
1162  case AArch64::Z11: Reg = AArch64::Z12; break;
1163  case AArch64::Z12: Reg = AArch64::Z13; break;
1164  case AArch64::Z13: Reg = AArch64::Z14; break;
1165  case AArch64::Z14: Reg = AArch64::Z15; break;
1166  case AArch64::Z15: Reg = AArch64::Z16; break;
1167  case AArch64::Z16: Reg = AArch64::Z17; break;
1168  case AArch64::Z17: Reg = AArch64::Z18; break;
1169  case AArch64::Z18: Reg = AArch64::Z19; break;
1170  case AArch64::Z19: Reg = AArch64::Z20; break;
1171  case AArch64::Z20: Reg = AArch64::Z21; break;
1172  case AArch64::Z21: Reg = AArch64::Z22; break;
1173  case AArch64::Z22: Reg = AArch64::Z23; break;
1174  case AArch64::Z23: Reg = AArch64::Z24; break;
1175  case AArch64::Z24: Reg = AArch64::Z25; break;
1176  case AArch64::Z25: Reg = AArch64::Z26; break;
1177  case AArch64::Z26: Reg = AArch64::Z27; break;
1178  case AArch64::Z27: Reg = AArch64::Z28; break;
1179  case AArch64::Z28: Reg = AArch64::Z29; break;
1180  case AArch64::Z29: Reg = AArch64::Z30; break;
1181  case AArch64::Z30: Reg = AArch64::Z31; break;
1182  // Vector lists can wrap around.
1183  case AArch64::Z31:
1184  Reg = AArch64::Z0;
1185  break;
1186  }
1187  }
1188  return Reg;
1189 }
1190 
1191 template<unsigned size>
1193  unsigned OpNum,
1194  const MCSubtargetInfo &STI,
1195  raw_ostream &O) {
1196  static_assert(size == 64 || size == 32,
1197  "Template parameter must be either 32 or 64");
1198  unsigned Reg = MI->getOperand(OpNum).getReg();
1199 
1200  unsigned Sube = (size == 32) ? AArch64::sube32 : AArch64::sube64;
1201  unsigned Subo = (size == 32) ? AArch64::subo32 : AArch64::subo64;
1202 
1203  unsigned Even = MRI.getSubReg(Reg, Sube);
1204  unsigned Odd = MRI.getSubReg(Reg, Subo);
1205  O << getRegisterName(Even) << ", " << getRegisterName(Odd);
1206 }
1207 
1208 void AArch64InstPrinter::printVectorList(const MCInst *MI, unsigned OpNum,
1209  const MCSubtargetInfo &STI,
1210  raw_ostream &O,
1211  StringRef LayoutSuffix) {
1212  unsigned Reg = MI->getOperand(OpNum).getReg();
1213 
1214  O << "{ ";
1215 
1216  // Work out how many registers there are in the list (if there is an actual
1217  // list).
1218  unsigned NumRegs = 1;
1219  if (MRI.getRegClass(AArch64::DDRegClassID).contains(Reg) ||
1220  MRI.getRegClass(AArch64::ZPR2RegClassID).contains(Reg) ||
1221  MRI.getRegClass(AArch64::QQRegClassID).contains(Reg))
1222  NumRegs = 2;
1223  else if (MRI.getRegClass(AArch64::DDDRegClassID).contains(Reg) ||
1224  MRI.getRegClass(AArch64::ZPR3RegClassID).contains(Reg) ||
1225  MRI.getRegClass(AArch64::QQQRegClassID).contains(Reg))
1226  NumRegs = 3;
1227  else if (MRI.getRegClass(AArch64::DDDDRegClassID).contains(Reg) ||
1228  MRI.getRegClass(AArch64::ZPR4RegClassID).contains(Reg) ||
1229  MRI.getRegClass(AArch64::QQQQRegClassID).contains(Reg))
1230  NumRegs = 4;
1231 
1232  // Now forget about the list and find out what the first register is.
1233  if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::dsub0))
1234  Reg = FirstReg;
1235  else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::qsub0))
1236  Reg = FirstReg;
1237  else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::zsub0))
1238  Reg = FirstReg;
1239 
1240  // If it's a D-reg, we need to promote it to the equivalent Q-reg before
1241  // printing (otherwise getRegisterName fails).
1242  if (MRI.getRegClass(AArch64::FPR64RegClassID).contains(Reg)) {
1243  const MCRegisterClass &FPR128RC =
1244  MRI.getRegClass(AArch64::FPR128RegClassID);
1245  Reg = MRI.getMatchingSuperReg(Reg, AArch64::dsub, &FPR128RC);
1246  }
1247 
1248  for (unsigned i = 0; i < NumRegs; ++i, Reg = getNextVectorRegister(Reg)) {
1249  if (MRI.getRegClass(AArch64::ZPRRegClassID).contains(Reg))
1250  O << getRegisterName(Reg) << LayoutSuffix;
1251  else
1252  O << getRegisterName(Reg, AArch64::vreg) << LayoutSuffix;
1253 
1254  if (i + 1 != NumRegs)
1255  O << ", ";
1256  }
1257 
1258  O << " }";
1259 }
1260 
1261 void
1263  unsigned OpNum,
1264  const MCSubtargetInfo &STI,
1265  raw_ostream &O) {
1266  printVectorList(MI, OpNum, STI, O, "");
1267 }
1268 
1269 template <unsigned NumLanes, char LaneKind>
1271  const MCSubtargetInfo &STI,
1272  raw_ostream &O) {
1273  std::string Suffix(".");
1274  if (NumLanes)
1275  Suffix += itostr(NumLanes) + LaneKind;
1276  else
1277  Suffix += LaneKind;
1278 
1279  printVectorList(MI, OpNum, STI, O, Suffix);
1280 }
1281 
1282 void AArch64InstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum,
1283  const MCSubtargetInfo &STI,
1284  raw_ostream &O) {
1285  O << "[" << MI->getOperand(OpNum).getImm() << "]";
1286 }
1287 
1289  const MCSubtargetInfo &STI,
1290  raw_ostream &O) {
1291  const MCOperand &Op = MI->getOperand(OpNum);
1292 
1293  // If the label has already been resolved to an immediate offset (say, when
1294  // we're running the disassembler), just print the immediate.
1295  if (Op.isImm()) {
1296  O << "#" << formatImm(Op.getImm() * 4);
1297  return;
1298  }
1299 
1300  // If the branch target is simply an address then print it in hex.
1301  const MCConstantExpr *BranchTarget =
1302  dyn_cast<MCConstantExpr>(MI->getOperand(OpNum).getExpr());
1303  int64_t Address;
1304  if (BranchTarget && BranchTarget->evaluateAsAbsolute(Address)) {
1305  O << "0x";
1306  O.write_hex(Address);
1307  } else {
1308  // Otherwise, just print the expression.
1309  MI->getOperand(OpNum).getExpr()->print(O, &MAI);
1310  }
1311 }
1312 
1313 void AArch64InstPrinter::printAdrpLabel(const MCInst *MI, unsigned OpNum,
1314  const MCSubtargetInfo &STI,
1315  raw_ostream &O) {
1316  const MCOperand &Op = MI->getOperand(OpNum);
1317 
1318  // If the label has already been resolved to an immediate offset (say, when
1319  // we're running the disassembler), just print the immediate.
1320  if (Op.isImm()) {
1321  O << "#" << formatImm(Op.getImm() * (1 << 12));
1322  return;
1323  }
1324 
1325  // Otherwise, just print the expression.
1326  MI->getOperand(OpNum).getExpr()->print(O, &MAI);
1327 }
1328 
1330  const MCSubtargetInfo &STI,
1331  raw_ostream &O) {
1332  unsigned Val = MI->getOperand(OpNo).getImm();
1333  unsigned Opcode = MI->getOpcode();
1334 
1335  StringRef Name;
1336  if (Opcode == AArch64::ISB) {
1337  auto ISB = AArch64ISB::lookupISBByEncoding(Val);
1338  Name = ISB ? ISB->Name : "";
1339  } else if (Opcode == AArch64::TSB) {
1340  auto TSB = AArch64TSB::lookupTSBByEncoding(Val);
1341  Name = TSB ? TSB->Name : "";
1342  } else {
1343  auto DB = AArch64DB::lookupDBByEncoding(Val);
1344  Name = DB ? DB->Name : "";
1345  }
1346  if (!Name.empty())
1347  O << Name;
1348  else
1349  O << "#" << Val;
1350 }
1351 
1353  const MCSubtargetInfo &STI,
1354  raw_ostream &O) {
1355  unsigned Val = MI->getOperand(OpNo).getImm();
1356 
1357  // Horrible hack for the one register that has identical encodings but
1358  // different names in MSR and MRS. Because of this, one of MRS and MSR is
1359  // going to get the wrong entry
1360  if (Val == AArch64SysReg::DBGDTRRX_EL0) {
1361  O << "DBGDTRRX_EL0";
1362  return;
1363  }
1364 
1366  if (Reg && Reg->Readable && Reg->haveFeatures(STI.getFeatureBits()))
1367  O << Reg->Name;
1368  else
1370 }
1371 
1373  const MCSubtargetInfo &STI,
1374  raw_ostream &O) {
1375  unsigned Val = MI->getOperand(OpNo).getImm();
1376 
1377  // Horrible hack for the one register that has identical encodings but
1378  // different names in MSR and MRS. Because of this, one of MRS and MSR is
1379  // going to get the wrong entry
1380  if (Val == AArch64SysReg::DBGDTRTX_EL0) {
1381  O << "DBGDTRTX_EL0";
1382  return;
1383  }
1384 
1386  if (Reg && Reg->Writeable && Reg->haveFeatures(STI.getFeatureBits()))
1387  O << Reg->Name;
1388  else
1390 }
1391 
1393  const MCSubtargetInfo &STI,
1394  raw_ostream &O) {
1395  unsigned Val = MI->getOperand(OpNo).getImm();
1396 
1397  auto PState = AArch64PState::lookupPStateByEncoding(Val);
1398  if (PState && PState->haveFeatures(STI.getFeatureBits()))
1399  O << PState->Name;
1400  else
1401  O << "#" << formatImm(Val);
1402 }
1403 
1405  const MCSubtargetInfo &STI,
1406  raw_ostream &O) {
1407  unsigned RawVal = MI->getOperand(OpNo).getImm();
1408  uint64_t Val = AArch64_AM::decodeAdvSIMDModImmType10(RawVal);
1409  O << format("#%#016llx", Val);
1410 }
1411 
1412 template<int64_t Angle, int64_t Remainder>
1414  const MCSubtargetInfo &STI,
1415  raw_ostream &O) {
1416  unsigned Val = MI->getOperand(OpNo).getImm();
1417  O << "#" << (Val * Angle) + Remainder;
1418 }
1419 
1420 void AArch64InstPrinter::printSVEPattern(const MCInst *MI, unsigned OpNum,
1421  const MCSubtargetInfo &STI,
1422  raw_ostream &O) {
1423  unsigned Val = MI->getOperand(OpNum).getImm();
1424  if (auto Pat = AArch64SVEPredPattern::lookupSVEPREDPATByEncoding(Val))
1425  O << Pat->Name;
1426  else
1427  O << '#' << formatImm(Val);
1428 }
1429 
1430 template <char suffix>
1431 void AArch64InstPrinter::printSVERegOp(const MCInst *MI, unsigned OpNum,
1432  const MCSubtargetInfo &STI,
1433  raw_ostream &O) {
1434  switch (suffix) {
1435  case 0:
1436  case 'b':
1437  case 'h':
1438  case 's':
1439  case 'd':
1440  case 'q':
1441  break;
1442  default: llvm_unreachable("Invalid kind specifier.");
1443  }
1444 
1445  unsigned Reg = MI->getOperand(OpNum).getReg();
1446  O << getRegisterName(Reg);
1447  if (suffix != 0)
1448  O << '.' << suffix;
1449 }
1450 
1451 template <typename T>
1453  typename std::make_unsigned<T>::type HexValue = Value;
1454 
1455  if (getPrintImmHex())
1456  O << '#' << formatHex((uint64_t)HexValue);
1457  else
1458  O << '#' << formatDec(Value);
1459 
1460  if (CommentStream) {
1461  // Do the opposite to that used for instruction operands.
1462  if (getPrintImmHex())
1463  *CommentStream << '=' << formatDec(HexValue) << '\n';
1464  else
1465  *CommentStream << '=' << formatHex((uint64_t)Value) << '\n';
1466  }
1467 }
1468 
1469 template <typename T>
1470 void AArch64InstPrinter::printImm8OptLsl(const MCInst *MI, unsigned OpNum,
1471  const MCSubtargetInfo &STI,
1472  raw_ostream &O) {
1473  unsigned UnscaledVal = MI->getOperand(OpNum).getImm();
1474  unsigned Shift = MI->getOperand(OpNum + 1).getImm();
1476  "Unexepected shift type!");
1477 
1478  // #0 lsl #8 is never pretty printed
1479  if ((UnscaledVal == 0) && (AArch64_AM::getShiftValue(Shift) != 0)) {
1480  O << '#' << formatImm(UnscaledVal);
1481  printShifter(MI, OpNum + 1, STI, O);
1482  return;
1483  }
1484 
1485  T Val;
1486  if (std::is_signed<T>())
1487  Val = (int8_t)UnscaledVal * (1 << AArch64_AM::getShiftValue(Shift));
1488  else
1489  Val = (uint8_t)UnscaledVal * (1 << AArch64_AM::getShiftValue(Shift));
1490 
1491  printImmSVE(Val, O);
1492 }
1493 
1494 template <typename T>
1496  const MCSubtargetInfo &STI,
1497  raw_ostream &O) {
1498  typedef typename std::make_signed<T>::type SignedT;
1499  typedef typename std::make_unsigned<T>::type UnsignedT;
1500 
1501  uint64_t Val = MI->getOperand(OpNum).getImm();
1502  UnsignedT PrintVal = AArch64_AM::decodeLogicalImmediate(Val, 64);
1503 
1504  // Prefer the default format for 16bit values, hex otherwise.
1505  if ((int16_t)PrintVal == (SignedT)PrintVal)
1506  printImmSVE((T)PrintVal, O);
1507  else if ((uint16_t)PrintVal == PrintVal)
1508  printImmSVE(PrintVal, O);
1509  else
1510  O << '#' << formatHex((uint64_t)PrintVal);
1511 }
1512 
1513 template <int Width>
1514 void AArch64InstPrinter::printZPRasFPR(const MCInst *MI, unsigned OpNum,
1515  const MCSubtargetInfo &STI,
1516  raw_ostream &O) {
1517  unsigned Base;
1518  switch (Width) {
1519  case 8: Base = AArch64::B0; break;
1520  case 16: Base = AArch64::H0; break;
1521  case 32: Base = AArch64::S0; break;
1522  case 64: Base = AArch64::D0; break;
1523  case 128: Base = AArch64::Q0; break;
1524  default:
1525  llvm_unreachable("Unsupported width");
1526  }
1527  unsigned Reg = MI->getOperand(OpNum).getReg();
1528  O << getRegisterName(Reg - AArch64::Z0 + Base);
1529 }
1530 
1531 template <unsigned ImmIs0, unsigned ImmIs1>
1532 void AArch64InstPrinter::printExactFPImm(const MCInst *MI, unsigned OpNum,
1533  const MCSubtargetInfo &STI,
1534  raw_ostream &O) {
1535  auto *Imm0Desc = AArch64ExactFPImm::lookupExactFPImmByEnum(ImmIs0);
1536  auto *Imm1Desc = AArch64ExactFPImm::lookupExactFPImmByEnum(ImmIs1);
1537  unsigned Val = MI->getOperand(OpNum).getImm();
1538  O << "#" << (Val ? Imm1Desc->Repr : Imm0Desc->Repr);
1539 }
1540 
1541 void AArch64InstPrinter::printGPR64as32(const MCInst *MI, unsigned OpNum,
1542  const MCSubtargetInfo &STI,
1543  raw_ostream &O) {
1544  unsigned Reg = MI->getOperand(OpNum).getReg();
1545  O << getRegisterName(getWRegFromXReg(Reg));
1546 }
void printImm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printAMIndexedWB(const MCInst *MI, unsigned OpNum, unsigned Scale, raw_ostream &O)
bool isImm() const
Definition: MCInst.h:59
static float getFPImmFloat(unsigned Imm)
void printRegName(raw_ostream &OS, unsigned RegNo) const override
Print the assembler register name.
void printShifter(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
static unsigned getArithShiftValue(unsigned Imm)
getArithShiftValue - get the arithmetic shift value.
void printVectorIndex(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printSysCROperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
static const LdStNInstrDesc LdStNInstInfo[]
void printSystemPStateField(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
static CondCode getInvertedCondCode(CondCode Code)
unsigned Reg
format_object< Ts... > format(const char *Fmt, const Ts &... Vals)
These are helper functions used to produce formatted output.
Definition: Format.h:124
bool isReg() const
Definition: MCInst.h:58
void printImmHex(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printFPImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
static bool isMOVZMovAlias(uint64_t Value, int Shift, int RegWidth)
void printGPRSeqPairsClassOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
bool haveFeatures(FeatureBitset ActiveFeatures) const
void printMemExtend(const MCInst *MI, unsigned OpNum, raw_ostream &O, char SrcRegKind, unsigned Width)
void printSVELogicalImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot, const MCSubtargetInfo &STI) override
Print the specified MCInst to the specified raw_ostream.
void printUImm12Offset(const MCInst *MI, unsigned OpNum, unsigned Scale, raw_ostream &O)
void printImplicitlyTypedVectorList(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Print a list of vector registers where the type suffix is implicit (i.e.
static ManagedStatic< DebugCounter > DC
bool contains(unsigned Reg) const
contains - Return true if the specified register is included in this register class.
const FeatureBitset & getFeatureBits() const
void printSVERegOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printPrefetchOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVRegOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
format_object< int64_t > formatDec(int64_t Value) const
Utility functions to print decimal/hexadecimal values.
static const char * getCondCodeName(CondCode Code)
void printGPR64as32(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:65
static bool isMOVNMovAlias(uint64_t Value, int Shift, int RegWidth)
static unsigned getNextVectorRegister(unsigned Reg, unsigned Stride=1)
void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &O) override
std::string itostr(int64_t X)
Definition: StringExtras.h:229
void printInverseCondCode(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
AArch64InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
raw_ostream & write_hex(unsigned long long N)
Output N in hexadecimal, without any prefix or padding.
format_object< int64_t > formatImm(int64_t Value) const
Utility function to print immediates in decimal or hex.
Definition: MCInstPrinter.h:96
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:133
void printAlignedLabel(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
const MCExpr * getExpr() const
Definition: MCInst.h:96
MCRegisterClass - Base class of TargetRegisterClass.
void printImm8OptLsl(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot, const MCSubtargetInfo &STI) override
Print the specified MCInst to the specified raw_ostream.
void printImmSVE(T Value, raw_ostream &O)
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:161
static const char * getRegisterName(unsigned RegNo, unsigned AltIdx=AArch64::NoRegAltName)
static unsigned getWRegFromXReg(unsigned Reg)
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
void printLogicalImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
static unsigned getShiftValue(unsigned Imm)
getShiftValue - Extract the shift value.
int64_t getImm() const
Definition: MCInst.h:76
void print(raw_ostream &OS, const MCAsmInfo *MAI, bool InParens=false) const
Definition: MCExpr.cpp:42
unsigned const MachineRegisterInfo * MRI
void printPSBHintOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, const MCRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg...
static const char * getShiftExtendName(AArch64_AM::ShiftExtendType ST)
getShiftName - Get the string encoding for the shift type.
bool getPrintImmHex() const
Definition: MCInstPrinter.h:89
static AArch64_AM::ShiftExtendType getArithExtendType(unsigned Imm)
bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &O) override
static uint64_t decodeLogicalImmediate(uint64_t val, unsigned regSize)
decodeLogicalImmediate - Decode a logical immediate value in the form "N:immr:imms" (where the immr a...
bool isFPImm() const
Definition: MCInst.h:60
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:24
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
StringRef getCommentString() const
Definition: MCAsmInfo.h:481
bool isExpr() const
Definition: MCInst.h:61
void printSIMDType10Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printArithExtend(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printMSRSystemRegister(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAdrpLabel(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const char * Name
void printPostIncOperand(const MCInst *MI, unsigned OpNo, unsigned Imm, raw_ostream &O)
void printBarrierOption(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printSVEPattern(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAMNoIndex(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
auto size(R &&Range, typename std::enable_if< std::is_same< typename std::iterator_traits< decltype(Range.begin())>::iterator_category, std::random_access_iterator_tag >::value, void >::type *=nullptr) -> decltype(std::distance(Range.begin(), Range.end()))
Get the size of a range.
Definition: STLExtras.h:1032
void printZPRasFPR(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:182
void printMRSSystemRegister(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:787
raw_ostream * CommentStream
A stream that comments can be emitted to if desired.
Definition: MCInstPrinter.h:45
void printComplexRotationOp(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printTypedVectorList(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printShiftedRegister(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
Definition: MathExtras.h:539
static const LdStNInstrDesc * getLdStNInstrDesc(unsigned Opcode)
std::string genericRegisterString(uint32_t Bits)
bool evaluateAsAbsolute(int64_t &Res, const MCAsmLayout &Layout, const SectionAddrMap &Addrs) const
Try to evaluate the expression to an absolute value.
Definition: MCExpr.cpp:452
bool haveFeatures(FeatureBitset ActiveFeatures) const
const MCAsmInfo & MAI
Definition: MCInstPrinter.h:46
void printExtendedRegister(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printExactFPImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorList(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O, StringRef LayoutSuffix)
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
Definition: MCInstPrinter.h:40
void printAddSubImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
static AArch64_AM::ShiftExtendType getShiftType(unsigned Imm)
getShiftType - Extract the shift type.
static bool isAnyMOVWMovAlias(uint64_t Value, int RegWidth)
void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
static uint64_t decodeAdvSIMDModImmType10(uint8_t Imm)
format_object< int64_t > formatHex(int64_t Value) const
void printRegWithShiftExtend(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Generic base class for all target subtargets.
const MCInstrInfo & MII
Definition: MCInstPrinter.h:47
AArch64AppleInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:323
constexpr int64_t SignExtend64(uint64_t x)
Sign-extend the number in the bottom B bits of X to a 64-bit integer.
Definition: MathExtras.h:749
OutputIt transform(R &&Range, OutputIt d_first, UnaryPredicate P)
Wrapper function around std::transform to apply a function to a range and store the result elsewhere...
Definition: STLExtras.h:990
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
Definition: Value.h:73
void printImmScale(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAnnotation(raw_ostream &OS, StringRef Annot)
Utility function for printing annotations.
const SysReg * lookupSysRegByEncoding(uint16_t)
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:46
static bool isTblTbxInstruction(unsigned Opcode, StringRef &Layout, bool &IsTbx)
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
unsigned getOpcode() const
Definition: MCInst.h:174
static void printMemExtendImpl(bool SignExtend, bool DoShift, unsigned Width, char SrcRegKind, raw_ostream &O)
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:35
bool printSysAlias(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &O)
double getFPImm() const
Definition: MCInst.h:86
const MCRegisterClass & getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
const MCRegisterInfo & MRI
Definition: MCInstPrinter.h:48
void printCondCode(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)