LLVM  9.0.0svn
AArch64InstPrinter.cpp
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1 //==-- AArch64InstPrinter.cpp - Convert AArch64 MCInst to assembly syntax --==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This class prints an AArch64 MCInst to a .s file.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "AArch64InstPrinter.h"
15 #include "Utils/AArch64BaseInfo.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/ADT/StringExtras.h"
18 #include "llvm/ADT/StringRef.h"
19 #include "llvm/MC/MCAsmInfo.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCInst.h"
22 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/Support/Casting.h"
26 #include "llvm/Support/Format.h"
29 #include <cassert>
30 #include <cstdint>
31 #include <string>
32 
33 using namespace llvm;
34 
35 #define DEBUG_TYPE "asm-printer"
36 
37 #define GET_INSTRUCTION_NAME
38 #define PRINT_ALIAS_INSTR
39 #include "AArch64GenAsmWriter.inc"
40 #define GET_INSTRUCTION_NAME
41 #define PRINT_ALIAS_INSTR
42 #include "AArch64GenAsmWriter1.inc"
43 
45  const MCInstrInfo &MII,
46  const MCRegisterInfo &MRI)
47  : MCInstPrinter(MAI, MII, MRI) {}
48 
50  const MCInstrInfo &MII,
51  const MCRegisterInfo &MRI)
52  : AArch64InstPrinter(MAI, MII, MRI) {}
53 
54 void AArch64InstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
55  // This is for .cfi directives.
56  OS << getRegisterName(RegNo);
57 }
58 
60  StringRef Annot,
61  const MCSubtargetInfo &STI) {
62  // Check for special encodings and print the canonical alias instead.
63 
64  unsigned Opcode = MI->getOpcode();
65 
66  if (Opcode == AArch64::SYSxt)
67  if (printSysAlias(MI, STI, O)) {
68  printAnnotation(O, Annot);
69  return;
70  }
71 
72  if (atomicBarrierDroppedOnZero(Opcode) &&
73  (MI->getOperand(0).getReg() == AArch64::XZR ||
74  MI->getOperand(0).getReg() == AArch64::WZR))
75  printAnnotation(O, "acquire semantics dropped since destination is zero");
76 
77  // SBFM/UBFM should print to a nicer aliased form if possible.
78  if (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri ||
79  Opcode == AArch64::UBFMXri || Opcode == AArch64::UBFMWri) {
80  const MCOperand &Op0 = MI->getOperand(0);
81  const MCOperand &Op1 = MI->getOperand(1);
82  const MCOperand &Op2 = MI->getOperand(2);
83  const MCOperand &Op3 = MI->getOperand(3);
84 
85  bool IsSigned = (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri);
86  bool Is64Bit = (Opcode == AArch64::SBFMXri || Opcode == AArch64::UBFMXri);
87  if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) {
88  const char *AsmMnemonic = nullptr;
89 
90  switch (Op3.getImm()) {
91  default:
92  break;
93  case 7:
94  if (IsSigned)
95  AsmMnemonic = "sxtb";
96  else if (!Is64Bit)
97  AsmMnemonic = "uxtb";
98  break;
99  case 15:
100  if (IsSigned)
101  AsmMnemonic = "sxth";
102  else if (!Is64Bit)
103  AsmMnemonic = "uxth";
104  break;
105  case 31:
106  // *xtw is only valid for signed 64-bit operations.
107  if (Is64Bit && IsSigned)
108  AsmMnemonic = "sxtw";
109  break;
110  }
111 
112  if (AsmMnemonic) {
113  O << '\t' << AsmMnemonic << '\t' << getRegisterName(Op0.getReg())
114  << ", " << getRegisterName(getWRegFromXReg(Op1.getReg()));
115  printAnnotation(O, Annot);
116  return;
117  }
118  }
119 
120  // All immediate shifts are aliases, implemented using the Bitfield
121  // instruction. In all cases the immediate shift amount shift must be in
122  // the range 0 to (reg.size -1).
123  if (Op2.isImm() && Op3.isImm()) {
124  const char *AsmMnemonic = nullptr;
125  int shift = 0;
126  int64_t immr = Op2.getImm();
127  int64_t imms = Op3.getImm();
128  if (Opcode == AArch64::UBFMWri && imms != 0x1F && ((imms + 1) == immr)) {
129  AsmMnemonic = "lsl";
130  shift = 31 - imms;
131  } else if (Opcode == AArch64::UBFMXri && imms != 0x3f &&
132  ((imms + 1 == immr))) {
133  AsmMnemonic = "lsl";
134  shift = 63 - imms;
135  } else if (Opcode == AArch64::UBFMWri && imms == 0x1f) {
136  AsmMnemonic = "lsr";
137  shift = immr;
138  } else if (Opcode == AArch64::UBFMXri && imms == 0x3f) {
139  AsmMnemonic = "lsr";
140  shift = immr;
141  } else if (Opcode == AArch64::SBFMWri && imms == 0x1f) {
142  AsmMnemonic = "asr";
143  shift = immr;
144  } else if (Opcode == AArch64::SBFMXri && imms == 0x3f) {
145  AsmMnemonic = "asr";
146  shift = immr;
147  }
148  if (AsmMnemonic) {
149  O << '\t' << AsmMnemonic << '\t' << getRegisterName(Op0.getReg())
150  << ", " << getRegisterName(Op1.getReg()) << ", #" << shift;
151  printAnnotation(O, Annot);
152  return;
153  }
154  }
155 
156  // SBFIZ/UBFIZ aliases
157  if (Op2.getImm() > Op3.getImm()) {
158  O << '\t' << (IsSigned ? "sbfiz" : "ubfiz") << '\t'
159  << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op1.getReg())
160  << ", #" << (Is64Bit ? 64 : 32) - Op2.getImm() << ", #" << Op3.getImm() + 1;
161  printAnnotation(O, Annot);
162  return;
163  }
164 
165  // Otherwise SBFX/UBFX is the preferred form
166  O << '\t' << (IsSigned ? "sbfx" : "ubfx") << '\t'
167  << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op1.getReg())
168  << ", #" << Op2.getImm() << ", #" << Op3.getImm() - Op2.getImm() + 1;
169  printAnnotation(O, Annot);
170  return;
171  }
172 
173  if (Opcode == AArch64::BFMXri || Opcode == AArch64::BFMWri) {
174  const MCOperand &Op0 = MI->getOperand(0); // Op1 == Op0
175  const MCOperand &Op2 = MI->getOperand(2);
176  int ImmR = MI->getOperand(3).getImm();
177  int ImmS = MI->getOperand(4).getImm();
178 
179  if ((Op2.getReg() == AArch64::WZR || Op2.getReg() == AArch64::XZR) &&
180  (ImmR == 0 || ImmS < ImmR)) {
181  // BFC takes precedence over its entire range, sligtly differently to BFI.
182  int BitWidth = Opcode == AArch64::BFMXri ? 64 : 32;
183  int LSB = (BitWidth - ImmR) % BitWidth;
184  int Width = ImmS + 1;
185 
186  O << "\tbfc\t" << getRegisterName(Op0.getReg())
187  << ", #" << LSB << ", #" << Width;
188  printAnnotation(O, Annot);
189  return;
190  } else if (ImmS < ImmR) {
191  // BFI alias
192  int BitWidth = Opcode == AArch64::BFMXri ? 64 : 32;
193  int LSB = (BitWidth - ImmR) % BitWidth;
194  int Width = ImmS + 1;
195 
196  O << "\tbfi\t" << getRegisterName(Op0.getReg()) << ", "
197  << getRegisterName(Op2.getReg()) << ", #" << LSB << ", #" << Width;
198  printAnnotation(O, Annot);
199  return;
200  }
201 
202  int LSB = ImmR;
203  int Width = ImmS - ImmR + 1;
204  // Otherwise BFXIL the preferred form
205  O << "\tbfxil\t"
206  << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op2.getReg())
207  << ", #" << LSB << ", #" << Width;
208  printAnnotation(O, Annot);
209  return;
210  }
211 
212  // Symbolic operands for MOVZ, MOVN and MOVK already imply a shift
213  // (e.g. :gottprel_g1: is always going to be "lsl #16") so it should not be
214  // printed.
215  if ((Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi ||
216  Opcode == AArch64::MOVNXi || Opcode == AArch64::MOVNWi) &&
217  MI->getOperand(1).isExpr()) {
218  if (Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi)
219  O << "\tmovz\t";
220  else
221  O << "\tmovn\t";
222 
223  O << getRegisterName(MI->getOperand(0).getReg()) << ", #";
224  MI->getOperand(1).getExpr()->print(O, &MAI);
225  return;
226  }
227 
228  if ((Opcode == AArch64::MOVKXi || Opcode == AArch64::MOVKWi) &&
229  MI->getOperand(2).isExpr()) {
230  O << "\tmovk\t" << getRegisterName(MI->getOperand(0).getReg()) << ", #";
231  MI->getOperand(2).getExpr()->print(O, &MAI);
232  return;
233  }
234 
235  // MOVZ, MOVN and "ORR wzr, #imm" instructions are aliases for MOV, but their
236  // domains overlap so they need to be prioritized. The chain is "MOVZ lsl #0 >
237  // MOVZ lsl #N > MOVN lsl #0 > MOVN lsl #N > ORR". The highest instruction
238  // that can represent the move is the MOV alias, and the rest get printed
239  // normally.
240  if ((Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi) &&
241  MI->getOperand(1).isImm() && MI->getOperand(2).isImm()) {
242  int RegWidth = Opcode == AArch64::MOVZXi ? 64 : 32;
243  int Shift = MI->getOperand(2).getImm();
244  uint64_t Value = (uint64_t)MI->getOperand(1).getImm() << Shift;
245 
246  if (AArch64_AM::isMOVZMovAlias(Value, Shift,
247  Opcode == AArch64::MOVZXi ? 64 : 32)) {
248  O << "\tmov\t" << getRegisterName(MI->getOperand(0).getReg()) << ", #"
249  << formatImm(SignExtend64(Value, RegWidth));
250  return;
251  }
252  }
253 
254  if ((Opcode == AArch64::MOVNXi || Opcode == AArch64::MOVNWi) &&
255  MI->getOperand(1).isImm() && MI->getOperand(2).isImm()) {
256  int RegWidth = Opcode == AArch64::MOVNXi ? 64 : 32;
257  int Shift = MI->getOperand(2).getImm();
258  uint64_t Value = ~((uint64_t)MI->getOperand(1).getImm() << Shift);
259  if (RegWidth == 32)
260  Value = Value & 0xffffffff;
261 
262  if (AArch64_AM::isMOVNMovAlias(Value, Shift, RegWidth)) {
263  O << "\tmov\t" << getRegisterName(MI->getOperand(0).getReg()) << ", #"
264  << formatImm(SignExtend64(Value, RegWidth));
265  return;
266  }
267  }
268 
269  if ((Opcode == AArch64::ORRXri || Opcode == AArch64::ORRWri) &&
270  (MI->getOperand(1).getReg() == AArch64::XZR ||
271  MI->getOperand(1).getReg() == AArch64::WZR) &&
272  MI->getOperand(2).isImm()) {
273  int RegWidth = Opcode == AArch64::ORRXri ? 64 : 32;
275  MI->getOperand(2).getImm(), RegWidth);
276  if (!AArch64_AM::isAnyMOVWMovAlias(Value, RegWidth)) {
277  O << "\tmov\t" << getRegisterName(MI->getOperand(0).getReg()) << ", #"
278  << formatImm(SignExtend64(Value, RegWidth));
279  return;
280  }
281  }
282 
283  if (Opcode == AArch64::CompilerBarrier) {
284  O << '\t' << MAI.getCommentString() << " COMPILER BARRIER";
285  printAnnotation(O, Annot);
286  return;
287  }
288 
289  // Instruction TSB is specified as a one operand instruction, but 'csync' is
290  // not encoded, so for printing it is treated as a special case here:
291  if (Opcode == AArch64::TSB) {
292  O << "\ttsb\tcsync";
293  return;
294  }
295 
296  if (!printAliasInstr(MI, STI, O))
297  printInstruction(MI, STI, O);
298 
299  printAnnotation(O, Annot);
300 }
301 
302 static bool isTblTbxInstruction(unsigned Opcode, StringRef &Layout,
303  bool &IsTbx) {
304  switch (Opcode) {
305  case AArch64::TBXv8i8One:
306  case AArch64::TBXv8i8Two:
307  case AArch64::TBXv8i8Three:
308  case AArch64::TBXv8i8Four:
309  IsTbx = true;
310  Layout = ".8b";
311  return true;
312  case AArch64::TBLv8i8One:
313  case AArch64::TBLv8i8Two:
314  case AArch64::TBLv8i8Three:
315  case AArch64::TBLv8i8Four:
316  IsTbx = false;
317  Layout = ".8b";
318  return true;
319  case AArch64::TBXv16i8One:
320  case AArch64::TBXv16i8Two:
321  case AArch64::TBXv16i8Three:
322  case AArch64::TBXv16i8Four:
323  IsTbx = true;
324  Layout = ".16b";
325  return true;
326  case AArch64::TBLv16i8One:
327  case AArch64::TBLv16i8Two:
328  case AArch64::TBLv16i8Three:
329  case AArch64::TBLv16i8Four:
330  IsTbx = false;
331  Layout = ".16b";
332  return true;
333  default:
334  return false;
335  }
336 }
337 
339  unsigned Opcode;
340  const char *Mnemonic;
341  const char *Layout;
343  bool HasLane;
345 };
346 
347 static const LdStNInstrDesc LdStNInstInfo[] = {
348  { AArch64::LD1i8, "ld1", ".b", 1, true, 0 },
349  { AArch64::LD1i16, "ld1", ".h", 1, true, 0 },
350  { AArch64::LD1i32, "ld1", ".s", 1, true, 0 },
351  { AArch64::LD1i64, "ld1", ".d", 1, true, 0 },
352  { AArch64::LD1i8_POST, "ld1", ".b", 2, true, 1 },
353  { AArch64::LD1i16_POST, "ld1", ".h", 2, true, 2 },
354  { AArch64::LD1i32_POST, "ld1", ".s", 2, true, 4 },
355  { AArch64::LD1i64_POST, "ld1", ".d", 2, true, 8 },
356  { AArch64::LD1Rv16b, "ld1r", ".16b", 0, false, 0 },
357  { AArch64::LD1Rv8h, "ld1r", ".8h", 0, false, 0 },
358  { AArch64::LD1Rv4s, "ld1r", ".4s", 0, false, 0 },
359  { AArch64::LD1Rv2d, "ld1r", ".2d", 0, false, 0 },
360  { AArch64::LD1Rv8b, "ld1r", ".8b", 0, false, 0 },
361  { AArch64::LD1Rv4h, "ld1r", ".4h", 0, false, 0 },
362  { AArch64::LD1Rv2s, "ld1r", ".2s", 0, false, 0 },
363  { AArch64::LD1Rv1d, "ld1r", ".1d", 0, false, 0 },
364  { AArch64::LD1Rv16b_POST, "ld1r", ".16b", 1, false, 1 },
365  { AArch64::LD1Rv8h_POST, "ld1r", ".8h", 1, false, 2 },
366  { AArch64::LD1Rv4s_POST, "ld1r", ".4s", 1, false, 4 },
367  { AArch64::LD1Rv2d_POST, "ld1r", ".2d", 1, false, 8 },
368  { AArch64::LD1Rv8b_POST, "ld1r", ".8b", 1, false, 1 },
369  { AArch64::LD1Rv4h_POST, "ld1r", ".4h", 1, false, 2 },
370  { AArch64::LD1Rv2s_POST, "ld1r", ".2s", 1, false, 4 },
371  { AArch64::LD1Rv1d_POST, "ld1r", ".1d", 1, false, 8 },
372  { AArch64::LD1Onev16b, "ld1", ".16b", 0, false, 0 },
373  { AArch64::LD1Onev8h, "ld1", ".8h", 0, false, 0 },
374  { AArch64::LD1Onev4s, "ld1", ".4s", 0, false, 0 },
375  { AArch64::LD1Onev2d, "ld1", ".2d", 0, false, 0 },
376  { AArch64::LD1Onev8b, "ld1", ".8b", 0, false, 0 },
377  { AArch64::LD1Onev4h, "ld1", ".4h", 0, false, 0 },
378  { AArch64::LD1Onev2s, "ld1", ".2s", 0, false, 0 },
379  { AArch64::LD1Onev1d, "ld1", ".1d", 0, false, 0 },
380  { AArch64::LD1Onev16b_POST, "ld1", ".16b", 1, false, 16 },
381  { AArch64::LD1Onev8h_POST, "ld1", ".8h", 1, false, 16 },
382  { AArch64::LD1Onev4s_POST, "ld1", ".4s", 1, false, 16 },
383  { AArch64::LD1Onev2d_POST, "ld1", ".2d", 1, false, 16 },
384  { AArch64::LD1Onev8b_POST, "ld1", ".8b", 1, false, 8 },
385  { AArch64::LD1Onev4h_POST, "ld1", ".4h", 1, false, 8 },
386  { AArch64::LD1Onev2s_POST, "ld1", ".2s", 1, false, 8 },
387  { AArch64::LD1Onev1d_POST, "ld1", ".1d", 1, false, 8 },
388  { AArch64::LD1Twov16b, "ld1", ".16b", 0, false, 0 },
389  { AArch64::LD1Twov8h, "ld1", ".8h", 0, false, 0 },
390  { AArch64::LD1Twov4s, "ld1", ".4s", 0, false, 0 },
391  { AArch64::LD1Twov2d, "ld1", ".2d", 0, false, 0 },
392  { AArch64::LD1Twov8b, "ld1", ".8b", 0, false, 0 },
393  { AArch64::LD1Twov4h, "ld1", ".4h", 0, false, 0 },
394  { AArch64::LD1Twov2s, "ld1", ".2s", 0, false, 0 },
395  { AArch64::LD1Twov1d, "ld1", ".1d", 0, false, 0 },
396  { AArch64::LD1Twov16b_POST, "ld1", ".16b", 1, false, 32 },
397  { AArch64::LD1Twov8h_POST, "ld1", ".8h", 1, false, 32 },
398  { AArch64::LD1Twov4s_POST, "ld1", ".4s", 1, false, 32 },
399  { AArch64::LD1Twov2d_POST, "ld1", ".2d", 1, false, 32 },
400  { AArch64::LD1Twov8b_POST, "ld1", ".8b", 1, false, 16 },
401  { AArch64::LD1Twov4h_POST, "ld1", ".4h", 1, false, 16 },
402  { AArch64::LD1Twov2s_POST, "ld1", ".2s", 1, false, 16 },
403  { AArch64::LD1Twov1d_POST, "ld1", ".1d", 1, false, 16 },
404  { AArch64::LD1Threev16b, "ld1", ".16b", 0, false, 0 },
405  { AArch64::LD1Threev8h, "ld1", ".8h", 0, false, 0 },
406  { AArch64::LD1Threev4s, "ld1", ".4s", 0, false, 0 },
407  { AArch64::LD1Threev2d, "ld1", ".2d", 0, false, 0 },
408  { AArch64::LD1Threev8b, "ld1", ".8b", 0, false, 0 },
409  { AArch64::LD1Threev4h, "ld1", ".4h", 0, false, 0 },
410  { AArch64::LD1Threev2s, "ld1", ".2s", 0, false, 0 },
411  { AArch64::LD1Threev1d, "ld1", ".1d", 0, false, 0 },
412  { AArch64::LD1Threev16b_POST, "ld1", ".16b", 1, false, 48 },
413  { AArch64::LD1Threev8h_POST, "ld1", ".8h", 1, false, 48 },
414  { AArch64::LD1Threev4s_POST, "ld1", ".4s", 1, false, 48 },
415  { AArch64::LD1Threev2d_POST, "ld1", ".2d", 1, false, 48 },
416  { AArch64::LD1Threev8b_POST, "ld1", ".8b", 1, false, 24 },
417  { AArch64::LD1Threev4h_POST, "ld1", ".4h", 1, false, 24 },
418  { AArch64::LD1Threev2s_POST, "ld1", ".2s", 1, false, 24 },
419  { AArch64::LD1Threev1d_POST, "ld1", ".1d", 1, false, 24 },
420  { AArch64::LD1Fourv16b, "ld1", ".16b", 0, false, 0 },
421  { AArch64::LD1Fourv8h, "ld1", ".8h", 0, false, 0 },
422  { AArch64::LD1Fourv4s, "ld1", ".4s", 0, false, 0 },
423  { AArch64::LD1Fourv2d, "ld1", ".2d", 0, false, 0 },
424  { AArch64::LD1Fourv8b, "ld1", ".8b", 0, false, 0 },
425  { AArch64::LD1Fourv4h, "ld1", ".4h", 0, false, 0 },
426  { AArch64::LD1Fourv2s, "ld1", ".2s", 0, false, 0 },
427  { AArch64::LD1Fourv1d, "ld1", ".1d", 0, false, 0 },
428  { AArch64::LD1Fourv16b_POST, "ld1", ".16b", 1, false, 64 },
429  { AArch64::LD1Fourv8h_POST, "ld1", ".8h", 1, false, 64 },
430  { AArch64::LD1Fourv4s_POST, "ld1", ".4s", 1, false, 64 },
431  { AArch64::LD1Fourv2d_POST, "ld1", ".2d", 1, false, 64 },
432  { AArch64::LD1Fourv8b_POST, "ld1", ".8b", 1, false, 32 },
433  { AArch64::LD1Fourv4h_POST, "ld1", ".4h", 1, false, 32 },
434  { AArch64::LD1Fourv2s_POST, "ld1", ".2s", 1, false, 32 },
435  { AArch64::LD1Fourv1d_POST, "ld1", ".1d", 1, false, 32 },
436  { AArch64::LD2i8, "ld2", ".b", 1, true, 0 },
437  { AArch64::LD2i16, "ld2", ".h", 1, true, 0 },
438  { AArch64::LD2i32, "ld2", ".s", 1, true, 0 },
439  { AArch64::LD2i64, "ld2", ".d", 1, true, 0 },
440  { AArch64::LD2i8_POST, "ld2", ".b", 2, true, 2 },
441  { AArch64::LD2i16_POST, "ld2", ".h", 2, true, 4 },
442  { AArch64::LD2i32_POST, "ld2", ".s", 2, true, 8 },
443  { AArch64::LD2i64_POST, "ld2", ".d", 2, true, 16 },
444  { AArch64::LD2Rv16b, "ld2r", ".16b", 0, false, 0 },
445  { AArch64::LD2Rv8h, "ld2r", ".8h", 0, false, 0 },
446  { AArch64::LD2Rv4s, "ld2r", ".4s", 0, false, 0 },
447  { AArch64::LD2Rv2d, "ld2r", ".2d", 0, false, 0 },
448  { AArch64::LD2Rv8b, "ld2r", ".8b", 0, false, 0 },
449  { AArch64::LD2Rv4h, "ld2r", ".4h", 0, false, 0 },
450  { AArch64::LD2Rv2s, "ld2r", ".2s", 0, false, 0 },
451  { AArch64::LD2Rv1d, "ld2r", ".1d", 0, false, 0 },
452  { AArch64::LD2Rv16b_POST, "ld2r", ".16b", 1, false, 2 },
453  { AArch64::LD2Rv8h_POST, "ld2r", ".8h", 1, false, 4 },
454  { AArch64::LD2Rv4s_POST, "ld2r", ".4s", 1, false, 8 },
455  { AArch64::LD2Rv2d_POST, "ld2r", ".2d", 1, false, 16 },
456  { AArch64::LD2Rv8b_POST, "ld2r", ".8b", 1, false, 2 },
457  { AArch64::LD2Rv4h_POST, "ld2r", ".4h", 1, false, 4 },
458  { AArch64::LD2Rv2s_POST, "ld2r", ".2s", 1, false, 8 },
459  { AArch64::LD2Rv1d_POST, "ld2r", ".1d", 1, false, 16 },
460  { AArch64::LD2Twov16b, "ld2", ".16b", 0, false, 0 },
461  { AArch64::LD2Twov8h, "ld2", ".8h", 0, false, 0 },
462  { AArch64::LD2Twov4s, "ld2", ".4s", 0, false, 0 },
463  { AArch64::LD2Twov2d, "ld2", ".2d", 0, false, 0 },
464  { AArch64::LD2Twov8b, "ld2", ".8b", 0, false, 0 },
465  { AArch64::LD2Twov4h, "ld2", ".4h", 0, false, 0 },
466  { AArch64::LD2Twov2s, "ld2", ".2s", 0, false, 0 },
467  { AArch64::LD2Twov16b_POST, "ld2", ".16b", 1, false, 32 },
468  { AArch64::LD2Twov8h_POST, "ld2", ".8h", 1, false, 32 },
469  { AArch64::LD2Twov4s_POST, "ld2", ".4s", 1, false, 32 },
470  { AArch64::LD2Twov2d_POST, "ld2", ".2d", 1, false, 32 },
471  { AArch64::LD2Twov8b_POST, "ld2", ".8b", 1, false, 16 },
472  { AArch64::LD2Twov4h_POST, "ld2", ".4h", 1, false, 16 },
473  { AArch64::LD2Twov2s_POST, "ld2", ".2s", 1, false, 16 },
474  { AArch64::LD3i8, "ld3", ".b", 1, true, 0 },
475  { AArch64::LD3i16, "ld3", ".h", 1, true, 0 },
476  { AArch64::LD3i32, "ld3", ".s", 1, true, 0 },
477  { AArch64::LD3i64, "ld3", ".d", 1, true, 0 },
478  { AArch64::LD3i8_POST, "ld3", ".b", 2, true, 3 },
479  { AArch64::LD3i16_POST, "ld3", ".h", 2, true, 6 },
480  { AArch64::LD3i32_POST, "ld3", ".s", 2, true, 12 },
481  { AArch64::LD3i64_POST, "ld3", ".d", 2, true, 24 },
482  { AArch64::LD3Rv16b, "ld3r", ".16b", 0, false, 0 },
483  { AArch64::LD3Rv8h, "ld3r", ".8h", 0, false, 0 },
484  { AArch64::LD3Rv4s, "ld3r", ".4s", 0, false, 0 },
485  { AArch64::LD3Rv2d, "ld3r", ".2d", 0, false, 0 },
486  { AArch64::LD3Rv8b, "ld3r", ".8b", 0, false, 0 },
487  { AArch64::LD3Rv4h, "ld3r", ".4h", 0, false, 0 },
488  { AArch64::LD3Rv2s, "ld3r", ".2s", 0, false, 0 },
489  { AArch64::LD3Rv1d, "ld3r", ".1d", 0, false, 0 },
490  { AArch64::LD3Rv16b_POST, "ld3r", ".16b", 1, false, 3 },
491  { AArch64::LD3Rv8h_POST, "ld3r", ".8h", 1, false, 6 },
492  { AArch64::LD3Rv4s_POST, "ld3r", ".4s", 1, false, 12 },
493  { AArch64::LD3Rv2d_POST, "ld3r", ".2d", 1, false, 24 },
494  { AArch64::LD3Rv8b_POST, "ld3r", ".8b", 1, false, 3 },
495  { AArch64::LD3Rv4h_POST, "ld3r", ".4h", 1, false, 6 },
496  { AArch64::LD3Rv2s_POST, "ld3r", ".2s", 1, false, 12 },
497  { AArch64::LD3Rv1d_POST, "ld3r", ".1d", 1, false, 24 },
498  { AArch64::LD3Threev16b, "ld3", ".16b", 0, false, 0 },
499  { AArch64::LD3Threev8h, "ld3", ".8h", 0, false, 0 },
500  { AArch64::LD3Threev4s, "ld3", ".4s", 0, false, 0 },
501  { AArch64::LD3Threev2d, "ld3", ".2d", 0, false, 0 },
502  { AArch64::LD3Threev8b, "ld3", ".8b", 0, false, 0 },
503  { AArch64::LD3Threev4h, "ld3", ".4h", 0, false, 0 },
504  { AArch64::LD3Threev2s, "ld3", ".2s", 0, false, 0 },
505  { AArch64::LD3Threev16b_POST, "ld3", ".16b", 1, false, 48 },
506  { AArch64::LD3Threev8h_POST, "ld3", ".8h", 1, false, 48 },
507  { AArch64::LD3Threev4s_POST, "ld3", ".4s", 1, false, 48 },
508  { AArch64::LD3Threev2d_POST, "ld3", ".2d", 1, false, 48 },
509  { AArch64::LD3Threev8b_POST, "ld3", ".8b", 1, false, 24 },
510  { AArch64::LD3Threev4h_POST, "ld3", ".4h", 1, false, 24 },
511  { AArch64::LD3Threev2s_POST, "ld3", ".2s", 1, false, 24 },
512  { AArch64::LD4i8, "ld4", ".b", 1, true, 0 },
513  { AArch64::LD4i16, "ld4", ".h", 1, true, 0 },
514  { AArch64::LD4i32, "ld4", ".s", 1, true, 0 },
515  { AArch64::LD4i64, "ld4", ".d", 1, true, 0 },
516  { AArch64::LD4i8_POST, "ld4", ".b", 2, true, 4 },
517  { AArch64::LD4i16_POST, "ld4", ".h", 2, true, 8 },
518  { AArch64::LD4i32_POST, "ld4", ".s", 2, true, 16 },
519  { AArch64::LD4i64_POST, "ld4", ".d", 2, true, 32 },
520  { AArch64::LD4Rv16b, "ld4r", ".16b", 0, false, 0 },
521  { AArch64::LD4Rv8h, "ld4r", ".8h", 0, false, 0 },
522  { AArch64::LD4Rv4s, "ld4r", ".4s", 0, false, 0 },
523  { AArch64::LD4Rv2d, "ld4r", ".2d", 0, false, 0 },
524  { AArch64::LD4Rv8b, "ld4r", ".8b", 0, false, 0 },
525  { AArch64::LD4Rv4h, "ld4r", ".4h", 0, false, 0 },
526  { AArch64::LD4Rv2s, "ld4r", ".2s", 0, false, 0 },
527  { AArch64::LD4Rv1d, "ld4r", ".1d", 0, false, 0 },
528  { AArch64::LD4Rv16b_POST, "ld4r", ".16b", 1, false, 4 },
529  { AArch64::LD4Rv8h_POST, "ld4r", ".8h", 1, false, 8 },
530  { AArch64::LD4Rv4s_POST, "ld4r", ".4s", 1, false, 16 },
531  { AArch64::LD4Rv2d_POST, "ld4r", ".2d", 1, false, 32 },
532  { AArch64::LD4Rv8b_POST, "ld4r", ".8b", 1, false, 4 },
533  { AArch64::LD4Rv4h_POST, "ld4r", ".4h", 1, false, 8 },
534  { AArch64::LD4Rv2s_POST, "ld4r", ".2s", 1, false, 16 },
535  { AArch64::LD4Rv1d_POST, "ld4r", ".1d", 1, false, 32 },
536  { AArch64::LD4Fourv16b, "ld4", ".16b", 0, false, 0 },
537  { AArch64::LD4Fourv8h, "ld4", ".8h", 0, false, 0 },
538  { AArch64::LD4Fourv4s, "ld4", ".4s", 0, false, 0 },
539  { AArch64::LD4Fourv2d, "ld4", ".2d", 0, false, 0 },
540  { AArch64::LD4Fourv8b, "ld4", ".8b", 0, false, 0 },
541  { AArch64::LD4Fourv4h, "ld4", ".4h", 0, false, 0 },
542  { AArch64::LD4Fourv2s, "ld4", ".2s", 0, false, 0 },
543  { AArch64::LD4Fourv16b_POST, "ld4", ".16b", 1, false, 64 },
544  { AArch64::LD4Fourv8h_POST, "ld4", ".8h", 1, false, 64 },
545  { AArch64::LD4Fourv4s_POST, "ld4", ".4s", 1, false, 64 },
546  { AArch64::LD4Fourv2d_POST, "ld4", ".2d", 1, false, 64 },
547  { AArch64::LD4Fourv8b_POST, "ld4", ".8b", 1, false, 32 },
548  { AArch64::LD4Fourv4h_POST, "ld4", ".4h", 1, false, 32 },
549  { AArch64::LD4Fourv2s_POST, "ld4", ".2s", 1, false, 32 },
550  { AArch64::ST1i8, "st1", ".b", 0, true, 0 },
551  { AArch64::ST1i16, "st1", ".h", 0, true, 0 },
552  { AArch64::ST1i32, "st1", ".s", 0, true, 0 },
553  { AArch64::ST1i64, "st1", ".d", 0, true, 0 },
554  { AArch64::ST1i8_POST, "st1", ".b", 1, true, 1 },
555  { AArch64::ST1i16_POST, "st1", ".h", 1, true, 2 },
556  { AArch64::ST1i32_POST, "st1", ".s", 1, true, 4 },
557  { AArch64::ST1i64_POST, "st1", ".d", 1, true, 8 },
558  { AArch64::ST1Onev16b, "st1", ".16b", 0, false, 0 },
559  { AArch64::ST1Onev8h, "st1", ".8h", 0, false, 0 },
560  { AArch64::ST1Onev4s, "st1", ".4s", 0, false, 0 },
561  { AArch64::ST1Onev2d, "st1", ".2d", 0, false, 0 },
562  { AArch64::ST1Onev8b, "st1", ".8b", 0, false, 0 },
563  { AArch64::ST1Onev4h, "st1", ".4h", 0, false, 0 },
564  { AArch64::ST1Onev2s, "st1", ".2s", 0, false, 0 },
565  { AArch64::ST1Onev1d, "st1", ".1d", 0, false, 0 },
566  { AArch64::ST1Onev16b_POST, "st1", ".16b", 1, false, 16 },
567  { AArch64::ST1Onev8h_POST, "st1", ".8h", 1, false, 16 },
568  { AArch64::ST1Onev4s_POST, "st1", ".4s", 1, false, 16 },
569  { AArch64::ST1Onev2d_POST, "st1", ".2d", 1, false, 16 },
570  { AArch64::ST1Onev8b_POST, "st1", ".8b", 1, false, 8 },
571  { AArch64::ST1Onev4h_POST, "st1", ".4h", 1, false, 8 },
572  { AArch64::ST1Onev2s_POST, "st1", ".2s", 1, false, 8 },
573  { AArch64::ST1Onev1d_POST, "st1", ".1d", 1, false, 8 },
574  { AArch64::ST1Twov16b, "st1", ".16b", 0, false, 0 },
575  { AArch64::ST1Twov8h, "st1", ".8h", 0, false, 0 },
576  { AArch64::ST1Twov4s, "st1", ".4s", 0, false, 0 },
577  { AArch64::ST1Twov2d, "st1", ".2d", 0, false, 0 },
578  { AArch64::ST1Twov8b, "st1", ".8b", 0, false, 0 },
579  { AArch64::ST1Twov4h, "st1", ".4h", 0, false, 0 },
580  { AArch64::ST1Twov2s, "st1", ".2s", 0, false, 0 },
581  { AArch64::ST1Twov1d, "st1", ".1d", 0, false, 0 },
582  { AArch64::ST1Twov16b_POST, "st1", ".16b", 1, false, 32 },
583  { AArch64::ST1Twov8h_POST, "st1", ".8h", 1, false, 32 },
584  { AArch64::ST1Twov4s_POST, "st1", ".4s", 1, false, 32 },
585  { AArch64::ST1Twov2d_POST, "st1", ".2d", 1, false, 32 },
586  { AArch64::ST1Twov8b_POST, "st1", ".8b", 1, false, 16 },
587  { AArch64::ST1Twov4h_POST, "st1", ".4h", 1, false, 16 },
588  { AArch64::ST1Twov2s_POST, "st1", ".2s", 1, false, 16 },
589  { AArch64::ST1Twov1d_POST, "st1", ".1d", 1, false, 16 },
590  { AArch64::ST1Threev16b, "st1", ".16b", 0, false, 0 },
591  { AArch64::ST1Threev8h, "st1", ".8h", 0, false, 0 },
592  { AArch64::ST1Threev4s, "st1", ".4s", 0, false, 0 },
593  { AArch64::ST1Threev2d, "st1", ".2d", 0, false, 0 },
594  { AArch64::ST1Threev8b, "st1", ".8b", 0, false, 0 },
595  { AArch64::ST1Threev4h, "st1", ".4h", 0, false, 0 },
596  { AArch64::ST1Threev2s, "st1", ".2s", 0, false, 0 },
597  { AArch64::ST1Threev1d, "st1", ".1d", 0, false, 0 },
598  { AArch64::ST1Threev16b_POST, "st1", ".16b", 1, false, 48 },
599  { AArch64::ST1Threev8h_POST, "st1", ".8h", 1, false, 48 },
600  { AArch64::ST1Threev4s_POST, "st1", ".4s", 1, false, 48 },
601  { AArch64::ST1Threev2d_POST, "st1", ".2d", 1, false, 48 },
602  { AArch64::ST1Threev8b_POST, "st1", ".8b", 1, false, 24 },
603  { AArch64::ST1Threev4h_POST, "st1", ".4h", 1, false, 24 },
604  { AArch64::ST1Threev2s_POST, "st1", ".2s", 1, false, 24 },
605  { AArch64::ST1Threev1d_POST, "st1", ".1d", 1, false, 24 },
606  { AArch64::ST1Fourv16b, "st1", ".16b", 0, false, 0 },
607  { AArch64::ST1Fourv8h, "st1", ".8h", 0, false, 0 },
608  { AArch64::ST1Fourv4s, "st1", ".4s", 0, false, 0 },
609  { AArch64::ST1Fourv2d, "st1", ".2d", 0, false, 0 },
610  { AArch64::ST1Fourv8b, "st1", ".8b", 0, false, 0 },
611  { AArch64::ST1Fourv4h, "st1", ".4h", 0, false, 0 },
612  { AArch64::ST1Fourv2s, "st1", ".2s", 0, false, 0 },
613  { AArch64::ST1Fourv1d, "st1", ".1d", 0, false, 0 },
614  { AArch64::ST1Fourv16b_POST, "st1", ".16b", 1, false, 64 },
615  { AArch64::ST1Fourv8h_POST, "st1", ".8h", 1, false, 64 },
616  { AArch64::ST1Fourv4s_POST, "st1", ".4s", 1, false, 64 },
617  { AArch64::ST1Fourv2d_POST, "st1", ".2d", 1, false, 64 },
618  { AArch64::ST1Fourv8b_POST, "st1", ".8b", 1, false, 32 },
619  { AArch64::ST1Fourv4h_POST, "st1", ".4h", 1, false, 32 },
620  { AArch64::ST1Fourv2s_POST, "st1", ".2s", 1, false, 32 },
621  { AArch64::ST1Fourv1d_POST, "st1", ".1d", 1, false, 32 },
622  { AArch64::ST2i8, "st2", ".b", 0, true, 0 },
623  { AArch64::ST2i16, "st2", ".h", 0, true, 0 },
624  { AArch64::ST2i32, "st2", ".s", 0, true, 0 },
625  { AArch64::ST2i64, "st2", ".d", 0, true, 0 },
626  { AArch64::ST2i8_POST, "st2", ".b", 1, true, 2 },
627  { AArch64::ST2i16_POST, "st2", ".h", 1, true, 4 },
628  { AArch64::ST2i32_POST, "st2", ".s", 1, true, 8 },
629  { AArch64::ST2i64_POST, "st2", ".d", 1, true, 16 },
630  { AArch64::ST2Twov16b, "st2", ".16b", 0, false, 0 },
631  { AArch64::ST2Twov8h, "st2", ".8h", 0, false, 0 },
632  { AArch64::ST2Twov4s, "st2", ".4s", 0, false, 0 },
633  { AArch64::ST2Twov2d, "st2", ".2d", 0, false, 0 },
634  { AArch64::ST2Twov8b, "st2", ".8b", 0, false, 0 },
635  { AArch64::ST2Twov4h, "st2", ".4h", 0, false, 0 },
636  { AArch64::ST2Twov2s, "st2", ".2s", 0, false, 0 },
637  { AArch64::ST2Twov16b_POST, "st2", ".16b", 1, false, 32 },
638  { AArch64::ST2Twov8h_POST, "st2", ".8h", 1, false, 32 },
639  { AArch64::ST2Twov4s_POST, "st2", ".4s", 1, false, 32 },
640  { AArch64::ST2Twov2d_POST, "st2", ".2d", 1, false, 32 },
641  { AArch64::ST2Twov8b_POST, "st2", ".8b", 1, false, 16 },
642  { AArch64::ST2Twov4h_POST, "st2", ".4h", 1, false, 16 },
643  { AArch64::ST2Twov2s_POST, "st2", ".2s", 1, false, 16 },
644  { AArch64::ST3i8, "st3", ".b", 0, true, 0 },
645  { AArch64::ST3i16, "st3", ".h", 0, true, 0 },
646  { AArch64::ST3i32, "st3", ".s", 0, true, 0 },
647  { AArch64::ST3i64, "st3", ".d", 0, true, 0 },
648  { AArch64::ST3i8_POST, "st3", ".b", 1, true, 3 },
649  { AArch64::ST3i16_POST, "st3", ".h", 1, true, 6 },
650  { AArch64::ST3i32_POST, "st3", ".s", 1, true, 12 },
651  { AArch64::ST3i64_POST, "st3", ".d", 1, true, 24 },
652  { AArch64::ST3Threev16b, "st3", ".16b", 0, false, 0 },
653  { AArch64::ST3Threev8h, "st3", ".8h", 0, false, 0 },
654  { AArch64::ST3Threev4s, "st3", ".4s", 0, false, 0 },
655  { AArch64::ST3Threev2d, "st3", ".2d", 0, false, 0 },
656  { AArch64::ST3Threev8b, "st3", ".8b", 0, false, 0 },
657  { AArch64::ST3Threev4h, "st3", ".4h", 0, false, 0 },
658  { AArch64::ST3Threev2s, "st3", ".2s", 0, false, 0 },
659  { AArch64::ST3Threev16b_POST, "st3", ".16b", 1, false, 48 },
660  { AArch64::ST3Threev8h_POST, "st3", ".8h", 1, false, 48 },
661  { AArch64::ST3Threev4s_POST, "st3", ".4s", 1, false, 48 },
662  { AArch64::ST3Threev2d_POST, "st3", ".2d", 1, false, 48 },
663  { AArch64::ST3Threev8b_POST, "st3", ".8b", 1, false, 24 },
664  { AArch64::ST3Threev4h_POST, "st3", ".4h", 1, false, 24 },
665  { AArch64::ST3Threev2s_POST, "st3", ".2s", 1, false, 24 },
666  { AArch64::ST4i8, "st4", ".b", 0, true, 0 },
667  { AArch64::ST4i16, "st4", ".h", 0, true, 0 },
668  { AArch64::ST4i32, "st4", ".s", 0, true, 0 },
669  { AArch64::ST4i64, "st4", ".d", 0, true, 0 },
670  { AArch64::ST4i8_POST, "st4", ".b", 1, true, 4 },
671  { AArch64::ST4i16_POST, "st4", ".h", 1, true, 8 },
672  { AArch64::ST4i32_POST, "st4", ".s", 1, true, 16 },
673  { AArch64::ST4i64_POST, "st4", ".d", 1, true, 32 },
674  { AArch64::ST4Fourv16b, "st4", ".16b", 0, false, 0 },
675  { AArch64::ST4Fourv8h, "st4", ".8h", 0, false, 0 },
676  { AArch64::ST4Fourv4s, "st4", ".4s", 0, false, 0 },
677  { AArch64::ST4Fourv2d, "st4", ".2d", 0, false, 0 },
678  { AArch64::ST4Fourv8b, "st4", ".8b", 0, false, 0 },
679  { AArch64::ST4Fourv4h, "st4", ".4h", 0, false, 0 },
680  { AArch64::ST4Fourv2s, "st4", ".2s", 0, false, 0 },
681  { AArch64::ST4Fourv16b_POST, "st4", ".16b", 1, false, 64 },
682  { AArch64::ST4Fourv8h_POST, "st4", ".8h", 1, false, 64 },
683  { AArch64::ST4Fourv4s_POST, "st4", ".4s", 1, false, 64 },
684  { AArch64::ST4Fourv2d_POST, "st4", ".2d", 1, false, 64 },
685  { AArch64::ST4Fourv8b_POST, "st4", ".8b", 1, false, 32 },
686  { AArch64::ST4Fourv4h_POST, "st4", ".4h", 1, false, 32 },
687  { AArch64::ST4Fourv2s_POST, "st4", ".2s", 1, false, 32 },
688 };
689 
690 static const LdStNInstrDesc *getLdStNInstrDesc(unsigned Opcode) {
691  unsigned Idx;
692  for (Idx = 0; Idx != array_lengthof(LdStNInstInfo); ++Idx)
693  if (LdStNInstInfo[Idx].Opcode == Opcode)
694  return &LdStNInstInfo[Idx];
695 
696  return nullptr;
697 }
698 
700  StringRef Annot,
701  const MCSubtargetInfo &STI) {
702  unsigned Opcode = MI->getOpcode();
703  StringRef Layout;
704 
705  bool IsTbx;
706  if (isTblTbxInstruction(MI->getOpcode(), Layout, IsTbx)) {
707  O << "\t" << (IsTbx ? "tbx" : "tbl") << Layout << '\t'
708  << getRegisterName(MI->getOperand(0).getReg(), AArch64::vreg) << ", ";
709 
710  unsigned ListOpNum = IsTbx ? 2 : 1;
711  printVectorList(MI, ListOpNum, STI, O, "");
712 
713  O << ", "
714  << getRegisterName(MI->getOperand(ListOpNum + 1).getReg(), AArch64::vreg);
715  printAnnotation(O, Annot);
716  return;
717  }
718 
719  if (const LdStNInstrDesc *LdStDesc = getLdStNInstrDesc(Opcode)) {
720  O << "\t" << LdStDesc->Mnemonic << LdStDesc->Layout << '\t';
721 
722  // Now onto the operands: first a vector list with possible lane
723  // specifier. E.g. { v0 }[2]
724  int OpNum = LdStDesc->ListOperand;
725  printVectorList(MI, OpNum++, STI, O, "");
726 
727  if (LdStDesc->HasLane)
728  O << '[' << MI->getOperand(OpNum++).getImm() << ']';
729 
730  // Next the address: [xN]
731  unsigned AddrReg = MI->getOperand(OpNum++).getReg();
732  O << ", [" << getRegisterName(AddrReg) << ']';
733 
734  // Finally, there might be a post-indexed offset.
735  if (LdStDesc->NaturalOffset != 0) {
736  unsigned Reg = MI->getOperand(OpNum++).getReg();
737  if (Reg != AArch64::XZR)
738  O << ", " << getRegisterName(Reg);
739  else {
740  assert(LdStDesc->NaturalOffset && "no offset on post-inc instruction?");
741  O << ", #" << LdStDesc->NaturalOffset;
742  }
743  }
744 
745  printAnnotation(O, Annot);
746  return;
747  }
748 
749  AArch64InstPrinter::printInst(MI, O, Annot, STI);
750 }
751 
753  const MCSubtargetInfo &STI,
754  raw_ostream &O) {
755 #ifndef NDEBUG
756  unsigned Opcode = MI->getOpcode();
757  assert(Opcode == AArch64::SYSxt && "Invalid opcode for SYS alias!");
758 #endif
759 
760  const MCOperand &Op1 = MI->getOperand(0);
761  const MCOperand &Cn = MI->getOperand(1);
762  const MCOperand &Cm = MI->getOperand(2);
763  const MCOperand &Op2 = MI->getOperand(3);
764 
765  unsigned Op1Val = Op1.getImm();
766  unsigned CnVal = Cn.getImm();
767  unsigned CmVal = Cm.getImm();
768  unsigned Op2Val = Op2.getImm();
769 
770  uint16_t Encoding = Op2Val;
771  Encoding |= CmVal << 3;
772  Encoding |= CnVal << 7;
773  Encoding |= Op1Val << 11;
774 
775  bool NeedsReg;
776  std::string Ins;
777  std::string Name;
778 
779  if (CnVal == 7) {
780  switch (CmVal) {
781  default: return false;
782  // Maybe IC, maybe Prediction Restriction
783  case 1:
784  switch (Op1Val) {
785  default: return false;
786  case 0: goto Search_IC;
787  case 3: goto Search_PRCTX;
788  }
789  // Prediction Restriction aliases
790  case 3: {
791  Search_PRCTX:
792  const AArch64PRCTX::PRCTX *PRCTX = AArch64PRCTX::lookupPRCTXByEncoding(Encoding >> 3);
793  if (!PRCTX || !PRCTX->haveFeatures(STI.getFeatureBits()))
794  return false;
795 
796  NeedsReg = PRCTX->NeedsReg;
797  switch (Op2Val) {
798  default: return false;
799  case 4: Ins = "cfp\t"; break;
800  case 5: Ins = "dvp\t"; break;
801  case 7: Ins = "cpp\t"; break;
802  }
803  Name = std::string(PRCTX->Name);
804  }
805  break;
806  // IC aliases
807  case 5: {
808  Search_IC:
809  const AArch64IC::IC *IC = AArch64IC::lookupICByEncoding(Encoding);
810  if (!IC || !IC->haveFeatures(STI.getFeatureBits()))
811  return false;
812 
813  NeedsReg = IC->NeedsReg;
814  Ins = "ic\t";
815  Name = std::string(IC->Name);
816  }
817  break;
818  // DC aliases
819  case 4: case 6: case 10: case 11: case 12: case 13: case 14:
820  {
821  const AArch64DC::DC *DC = AArch64DC::lookupDCByEncoding(Encoding);
822  if (!DC || !DC->haveFeatures(STI.getFeatureBits()))
823  return false;
824 
825  NeedsReg = true;
826  Ins = "dc\t";
827  Name = std::string(DC->Name);
828  }
829  break;
830  // AT aliases
831  case 8: case 9: {
832  const AArch64AT::AT *AT = AArch64AT::lookupATByEncoding(Encoding);
833  if (!AT || !AT->haveFeatures(STI.getFeatureBits()))
834  return false;
835 
836  NeedsReg = true;
837  Ins = "at\t";
838  Name = std::string(AT->Name);
839  }
840  break;
841  }
842  } else if (CnVal == 8) {
843  // TLBI aliases
844  const AArch64TLBI::TLBI *TLBI = AArch64TLBI::lookupTLBIByEncoding(Encoding);
845  if (!TLBI || !TLBI->haveFeatures(STI.getFeatureBits()))
846  return false;
847 
848  NeedsReg = TLBI->NeedsReg;
849  Ins = "tlbi\t";
850  Name = std::string(TLBI->Name);
851  }
852  else
853  return false;
854 
855  std::string Str = Ins + Name;
856  std::transform(Str.begin(), Str.end(), Str.begin(), ::tolower);
857 
858  O << '\t' << Str;
859  if (NeedsReg)
860  O << ", " << getRegisterName(MI->getOperand(4).getReg());
861 
862  return true;
863 }
864 
865 void AArch64InstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
866  const MCSubtargetInfo &STI,
867  raw_ostream &O) {
868  const MCOperand &Op = MI->getOperand(OpNo);
869  if (Op.isReg()) {
870  unsigned Reg = Op.getReg();
871  O << getRegisterName(Reg);
872  } else if (Op.isImm()) {
873  printImm(MI, OpNo, STI, O);
874  } else {
875  assert(Op.isExpr() && "unknown operand kind in printOperand");
876  Op.getExpr()->print(O, &MAI);
877  }
878 }
879 
880 void AArch64InstPrinter::printImm(const MCInst *MI, unsigned OpNo,
881  const MCSubtargetInfo &STI,
882  raw_ostream &O) {
883  const MCOperand &Op = MI->getOperand(OpNo);
884  O << "#" << formatImm(Op.getImm());
885 }
886 
887 void AArch64InstPrinter::printImmHex(const MCInst *MI, unsigned OpNo,
888  const MCSubtargetInfo &STI,
889  raw_ostream &O) {
890  const MCOperand &Op = MI->getOperand(OpNo);
891  O << format("#%#llx", Op.getImm());
892 }
893 
895  unsigned Imm, raw_ostream &O) {
896  const MCOperand &Op = MI->getOperand(OpNo);
897  if (Op.isReg()) {
898  unsigned Reg = Op.getReg();
899  if (Reg == AArch64::XZR)
900  O << "#" << Imm;
901  else
902  O << getRegisterName(Reg);
903  } else
904  llvm_unreachable("unknown operand kind in printPostIncOperand64");
905 }
906 
907 void AArch64InstPrinter::printVRegOperand(const MCInst *MI, unsigned OpNo,
908  const MCSubtargetInfo &STI,
909  raw_ostream &O) {
910  const MCOperand &Op = MI->getOperand(OpNo);
911  assert(Op.isReg() && "Non-register vreg operand!");
912  unsigned Reg = Op.getReg();
913  O << getRegisterName(Reg, AArch64::vreg);
914 }
915 
917  const MCSubtargetInfo &STI,
918  raw_ostream &O) {
919  const MCOperand &Op = MI->getOperand(OpNo);
920  assert(Op.isImm() && "System instruction C[nm] operands must be immediates!");
921  O << "c" << Op.getImm();
922 }
923 
924 void AArch64InstPrinter::printAddSubImm(const MCInst *MI, unsigned OpNum,
925  const MCSubtargetInfo &STI,
926  raw_ostream &O) {
927  const MCOperand &MO = MI->getOperand(OpNum);
928  if (MO.isImm()) {
929  unsigned Val = (MO.getImm() & 0xfff);
930  assert(Val == MO.getImm() && "Add/sub immediate out of range!");
931  unsigned Shift =
932  AArch64_AM::getShiftValue(MI->getOperand(OpNum + 1).getImm());
933  O << '#' << formatImm(Val);
934  if (Shift != 0)
935  printShifter(MI, OpNum + 1, STI, O);
936 
937  if (CommentStream)
938  *CommentStream << '=' << formatImm(Val << Shift) << '\n';
939  } else {
940  assert(MO.isExpr() && "Unexpected operand type!");
941  MO.getExpr()->print(O, &MAI);
942  printShifter(MI, OpNum + 1, STI, O);
943  }
944 }
945 
946 template <typename T>
947 void AArch64InstPrinter::printLogicalImm(const MCInst *MI, unsigned OpNum,
948  const MCSubtargetInfo &STI,
949  raw_ostream &O) {
950  uint64_t Val = MI->getOperand(OpNum).getImm();
951  O << "#0x";
952  O.write_hex(AArch64_AM::decodeLogicalImmediate(Val, 8 * sizeof(T)));
953 }
954 
955 void AArch64InstPrinter::printShifter(const MCInst *MI, unsigned OpNum,
956  const MCSubtargetInfo &STI,
957  raw_ostream &O) {
958  unsigned Val = MI->getOperand(OpNum).getImm();
959  // LSL #0 should not be printed.
961  AArch64_AM::getShiftValue(Val) == 0)
962  return;
964  << " #" << AArch64_AM::getShiftValue(Val);
965 }
966 
968  const MCSubtargetInfo &STI,
969  raw_ostream &O) {
970  O << getRegisterName(MI->getOperand(OpNum).getReg());
971  printShifter(MI, OpNum + 1, STI, O);
972 }
973 
975  const MCSubtargetInfo &STI,
976  raw_ostream &O) {
977  O << getRegisterName(MI->getOperand(OpNum).getReg());
978  printArithExtend(MI, OpNum + 1, STI, O);
979 }
980 
981 void AArch64InstPrinter::printArithExtend(const MCInst *MI, unsigned OpNum,
982  const MCSubtargetInfo &STI,
983  raw_ostream &O) {
984  unsigned Val = MI->getOperand(OpNum).getImm();
986  unsigned ShiftVal = AArch64_AM::getArithShiftValue(Val);
987 
988  // If the destination or first source register operand is [W]SP, print
989  // UXTW/UXTX as LSL, and if the shift amount is also zero, print nothing at
990  // all.
991  if (ExtType == AArch64_AM::UXTW || ExtType == AArch64_AM::UXTX) {
992  unsigned Dest = MI->getOperand(0).getReg();
993  unsigned Src1 = MI->getOperand(1).getReg();
994  if ( ((Dest == AArch64::SP || Src1 == AArch64::SP) &&
995  ExtType == AArch64_AM::UXTX) ||
996  ((Dest == AArch64::WSP || Src1 == AArch64::WSP) &&
997  ExtType == AArch64_AM::UXTW) ) {
998  if (ShiftVal != 0)
999  O << ", lsl #" << ShiftVal;
1000  return;
1001  }
1002  }
1003  O << ", " << AArch64_AM::getShiftExtendName(ExtType);
1004  if (ShiftVal != 0)
1005  O << " #" << ShiftVal;
1006 }
1007 
1008 static void printMemExtendImpl(bool SignExtend, bool DoShift,
1009  unsigned Width, char SrcRegKind,
1010  raw_ostream &O) {
1011  // sxtw, sxtx, uxtw or lsl (== uxtx)
1012  bool IsLSL = !SignExtend && SrcRegKind == 'x';
1013  if (IsLSL)
1014  O << "lsl";
1015  else
1016  O << (SignExtend ? 's' : 'u') << "xt" << SrcRegKind;
1017 
1018  if (DoShift || IsLSL)
1019  O << " #" << Log2_32(Width / 8);
1020 }
1021 
1022 void AArch64InstPrinter::printMemExtend(const MCInst *MI, unsigned OpNum,
1023  raw_ostream &O, char SrcRegKind,
1024  unsigned Width) {
1025  bool SignExtend = MI->getOperand(OpNum).getImm();
1026  bool DoShift = MI->getOperand(OpNum + 1).getImm();
1027  printMemExtendImpl(SignExtend, DoShift, Width, SrcRegKind, O);
1028 }
1029 
1030 template <bool SignExtend, int ExtWidth, char SrcRegKind, char Suffix>
1032  unsigned OpNum,
1033  const MCSubtargetInfo &STI,
1034  raw_ostream &O) {
1035  printOperand(MI, OpNum, STI, O);
1036  if (Suffix == 's' || Suffix == 'd')
1037  O << '.' << Suffix;
1038  else
1039  assert(Suffix == 0 && "Unsupported suffix size");
1040 
1041  bool DoShift = ExtWidth != 8;
1042  if (SignExtend || DoShift || SrcRegKind == 'w') {
1043  O << ", ";
1044  printMemExtendImpl(SignExtend, DoShift, ExtWidth, SrcRegKind, O);
1045  }
1046 }
1047 
1048 void AArch64InstPrinter::printCondCode(const MCInst *MI, unsigned OpNum,
1049  const MCSubtargetInfo &STI,
1050  raw_ostream &O) {
1052  O << AArch64CC::getCondCodeName(CC);
1053 }
1054 
1056  const MCSubtargetInfo &STI,
1057  raw_ostream &O) {
1060 }
1061 
1062 void AArch64InstPrinter::printAMNoIndex(const MCInst *MI, unsigned OpNum,
1063  const MCSubtargetInfo &STI,
1064  raw_ostream &O) {
1065  O << '[' << getRegisterName(MI->getOperand(OpNum).getReg()) << ']';
1066 }
1067 
1068 template<int Scale>
1069 void AArch64InstPrinter::printImmScale(const MCInst *MI, unsigned OpNum,
1070  const MCSubtargetInfo &STI,
1071  raw_ostream &O) {
1072  O << '#' << formatImm(Scale * MI->getOperand(OpNum).getImm());
1073 }
1074 
1076  unsigned Scale, raw_ostream &O) {
1077  const MCOperand MO = MI->getOperand(OpNum);
1078  if (MO.isImm()) {
1079  O << "#" << formatImm(MO.getImm() * Scale);
1080  } else {
1081  assert(MO.isExpr() && "Unexpected operand type!");
1082  MO.getExpr()->print(O, &MAI);
1083  }
1084 }
1085 
1086 void AArch64InstPrinter::printAMIndexedWB(const MCInst *MI, unsigned OpNum,
1087  unsigned Scale, raw_ostream &O) {
1088  const MCOperand MO1 = MI->getOperand(OpNum + 1);
1089  O << '[' << getRegisterName(MI->getOperand(OpNum).getReg());
1090  if (MO1.isImm()) {
1091  O << ", #" << formatImm(MO1.getImm() * Scale);
1092  } else {
1093  assert(MO1.isExpr() && "Unexpected operand type!");
1094  O << ", ";
1095  MO1.getExpr()->print(O, &MAI);
1096  }
1097  O << ']';
1098 }
1099 
1100 template <bool IsSVEPrefetch>
1101 void AArch64InstPrinter::printPrefetchOp(const MCInst *MI, unsigned OpNum,
1102  const MCSubtargetInfo &STI,
1103  raw_ostream &O) {
1104  unsigned prfop = MI->getOperand(OpNum).getImm();
1105  if (IsSVEPrefetch) {
1106  if (auto PRFM = AArch64SVEPRFM::lookupSVEPRFMByEncoding(prfop)) {
1107  O << PRFM->Name;
1108  return;
1109  }
1110  } else if (auto PRFM = AArch64PRFM::lookupPRFMByEncoding(prfop)) {
1111  O << PRFM->Name;
1112  return;
1113  }
1114 
1115  O << '#' << formatImm(prfop);
1116 }
1117 
1118 void AArch64InstPrinter::printPSBHintOp(const MCInst *MI, unsigned OpNum,
1119  const MCSubtargetInfo &STI,
1120  raw_ostream &O) {
1121  unsigned psbhintop = MI->getOperand(OpNum).getImm();
1122  auto PSB = AArch64PSBHint::lookupPSBByEncoding(psbhintop);
1123  if (PSB)
1124  O << PSB->Name;
1125  else
1126  O << '#' << formatImm(psbhintop);
1127 }
1128 
1129 void AArch64InstPrinter::printBTIHintOp(const MCInst *MI, unsigned OpNum,
1130  const MCSubtargetInfo &STI,
1131  raw_ostream &O) {
1132  unsigned btihintop = (MI->getOperand(OpNum).getImm() ^ 32) >> 1;
1133  auto BTI = AArch64BTIHint::lookupBTIByEncoding(btihintop);
1134  if (BTI)
1135  O << BTI->Name;
1136  else
1137  O << '#' << formatImm(btihintop);
1138 }
1139 
1141  const MCSubtargetInfo &STI,
1142  raw_ostream &O) {
1143  const MCOperand &MO = MI->getOperand(OpNum);
1144  float FPImm =
1145  MO.isFPImm() ? MO.getFPImm() : AArch64_AM::getFPImmFloat(MO.getImm());
1146 
1147  // 8 decimal places are enough to perfectly represent permitted floats.
1148  O << format("#%.8f", FPImm);
1149 }
1150 
1151 static unsigned getNextVectorRegister(unsigned Reg, unsigned Stride = 1) {
1152  while (Stride--) {
1153  switch (Reg) {
1154  default:
1155  llvm_unreachable("Vector register expected!");
1156  case AArch64::Q0: Reg = AArch64::Q1; break;
1157  case AArch64::Q1: Reg = AArch64::Q2; break;
1158  case AArch64::Q2: Reg = AArch64::Q3; break;
1159  case AArch64::Q3: Reg = AArch64::Q4; break;
1160  case AArch64::Q4: Reg = AArch64::Q5; break;
1161  case AArch64::Q5: Reg = AArch64::Q6; break;
1162  case AArch64::Q6: Reg = AArch64::Q7; break;
1163  case AArch64::Q7: Reg = AArch64::Q8; break;
1164  case AArch64::Q8: Reg = AArch64::Q9; break;
1165  case AArch64::Q9: Reg = AArch64::Q10; break;
1166  case AArch64::Q10: Reg = AArch64::Q11; break;
1167  case AArch64::Q11: Reg = AArch64::Q12; break;
1168  case AArch64::Q12: Reg = AArch64::Q13; break;
1169  case AArch64::Q13: Reg = AArch64::Q14; break;
1170  case AArch64::Q14: Reg = AArch64::Q15; break;
1171  case AArch64::Q15: Reg = AArch64::Q16; break;
1172  case AArch64::Q16: Reg = AArch64::Q17; break;
1173  case AArch64::Q17: Reg = AArch64::Q18; break;
1174  case AArch64::Q18: Reg = AArch64::Q19; break;
1175  case AArch64::Q19: Reg = AArch64::Q20; break;
1176  case AArch64::Q20: Reg = AArch64::Q21; break;
1177  case AArch64::Q21: Reg = AArch64::Q22; break;
1178  case AArch64::Q22: Reg = AArch64::Q23; break;
1179  case AArch64::Q23: Reg = AArch64::Q24; break;
1180  case AArch64::Q24: Reg = AArch64::Q25; break;
1181  case AArch64::Q25: Reg = AArch64::Q26; break;
1182  case AArch64::Q26: Reg = AArch64::Q27; break;
1183  case AArch64::Q27: Reg = AArch64::Q28; break;
1184  case AArch64::Q28: Reg = AArch64::Q29; break;
1185  case AArch64::Q29: Reg = AArch64::Q30; break;
1186  case AArch64::Q30: Reg = AArch64::Q31; break;
1187  // Vector lists can wrap around.
1188  case AArch64::Q31:
1189  Reg = AArch64::Q0;
1190  break;
1191  case AArch64::Z0: Reg = AArch64::Z1; break;
1192  case AArch64::Z1: Reg = AArch64::Z2; break;
1193  case AArch64::Z2: Reg = AArch64::Z3; break;
1194  case AArch64::Z3: Reg = AArch64::Z4; break;
1195  case AArch64::Z4: Reg = AArch64::Z5; break;
1196  case AArch64::Z5: Reg = AArch64::Z6; break;
1197  case AArch64::Z6: Reg = AArch64::Z7; break;
1198  case AArch64::Z7: Reg = AArch64::Z8; break;
1199  case AArch64::Z8: Reg = AArch64::Z9; break;
1200  case AArch64::Z9: Reg = AArch64::Z10; break;
1201  case AArch64::Z10: Reg = AArch64::Z11; break;
1202  case AArch64::Z11: Reg = AArch64::Z12; break;
1203  case AArch64::Z12: Reg = AArch64::Z13; break;
1204  case AArch64::Z13: Reg = AArch64::Z14; break;
1205  case AArch64::Z14: Reg = AArch64::Z15; break;
1206  case AArch64::Z15: Reg = AArch64::Z16; break;
1207  case AArch64::Z16: Reg = AArch64::Z17; break;
1208  case AArch64::Z17: Reg = AArch64::Z18; break;
1209  case AArch64::Z18: Reg = AArch64::Z19; break;
1210  case AArch64::Z19: Reg = AArch64::Z20; break;
1211  case AArch64::Z20: Reg = AArch64::Z21; break;
1212  case AArch64::Z21: Reg = AArch64::Z22; break;
1213  case AArch64::Z22: Reg = AArch64::Z23; break;
1214  case AArch64::Z23: Reg = AArch64::Z24; break;
1215  case AArch64::Z24: Reg = AArch64::Z25; break;
1216  case AArch64::Z25: Reg = AArch64::Z26; break;
1217  case AArch64::Z26: Reg = AArch64::Z27; break;
1218  case AArch64::Z27: Reg = AArch64::Z28; break;
1219  case AArch64::Z28: Reg = AArch64::Z29; break;
1220  case AArch64::Z29: Reg = AArch64::Z30; break;
1221  case AArch64::Z30: Reg = AArch64::Z31; break;
1222  // Vector lists can wrap around.
1223  case AArch64::Z31:
1224  Reg = AArch64::Z0;
1225  break;
1226  }
1227  }
1228  return Reg;
1229 }
1230 
1231 template<unsigned size>
1233  unsigned OpNum,
1234  const MCSubtargetInfo &STI,
1235  raw_ostream &O) {
1236  static_assert(size == 64 || size == 32,
1237  "Template parameter must be either 32 or 64");
1238  unsigned Reg = MI->getOperand(OpNum).getReg();
1239 
1240  unsigned Sube = (size == 32) ? AArch64::sube32 : AArch64::sube64;
1241  unsigned Subo = (size == 32) ? AArch64::subo32 : AArch64::subo64;
1242 
1243  unsigned Even = MRI.getSubReg(Reg, Sube);
1244  unsigned Odd = MRI.getSubReg(Reg, Subo);
1245  O << getRegisterName(Even) << ", " << getRegisterName(Odd);
1246 }
1247 
1248 void AArch64InstPrinter::printVectorList(const MCInst *MI, unsigned OpNum,
1249  const MCSubtargetInfo &STI,
1250  raw_ostream &O,
1251  StringRef LayoutSuffix) {
1252  unsigned Reg = MI->getOperand(OpNum).getReg();
1253 
1254  O << "{ ";
1255 
1256  // Work out how many registers there are in the list (if there is an actual
1257  // list).
1258  unsigned NumRegs = 1;
1259  if (MRI.getRegClass(AArch64::DDRegClassID).contains(Reg) ||
1260  MRI.getRegClass(AArch64::ZPR2RegClassID).contains(Reg) ||
1261  MRI.getRegClass(AArch64::QQRegClassID).contains(Reg))
1262  NumRegs = 2;
1263  else if (MRI.getRegClass(AArch64::DDDRegClassID).contains(Reg) ||
1264  MRI.getRegClass(AArch64::ZPR3RegClassID).contains(Reg) ||
1265  MRI.getRegClass(AArch64::QQQRegClassID).contains(Reg))
1266  NumRegs = 3;
1267  else if (MRI.getRegClass(AArch64::DDDDRegClassID).contains(Reg) ||
1268  MRI.getRegClass(AArch64::ZPR4RegClassID).contains(Reg) ||
1269  MRI.getRegClass(AArch64::QQQQRegClassID).contains(Reg))
1270  NumRegs = 4;
1271 
1272  // Now forget about the list and find out what the first register is.
1273  if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::dsub0))
1274  Reg = FirstReg;
1275  else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::qsub0))
1276  Reg = FirstReg;
1277  else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::zsub0))
1278  Reg = FirstReg;
1279 
1280  // If it's a D-reg, we need to promote it to the equivalent Q-reg before
1281  // printing (otherwise getRegisterName fails).
1282  if (MRI.getRegClass(AArch64::FPR64RegClassID).contains(Reg)) {
1283  const MCRegisterClass &FPR128RC =
1284  MRI.getRegClass(AArch64::FPR128RegClassID);
1285  Reg = MRI.getMatchingSuperReg(Reg, AArch64::dsub, &FPR128RC);
1286  }
1287 
1288  for (unsigned i = 0; i < NumRegs; ++i, Reg = getNextVectorRegister(Reg)) {
1289  if (MRI.getRegClass(AArch64::ZPRRegClassID).contains(Reg))
1290  O << getRegisterName(Reg) << LayoutSuffix;
1291  else
1292  O << getRegisterName(Reg, AArch64::vreg) << LayoutSuffix;
1293 
1294  if (i + 1 != NumRegs)
1295  O << ", ";
1296  }
1297 
1298  O << " }";
1299 }
1300 
1301 void
1303  unsigned OpNum,
1304  const MCSubtargetInfo &STI,
1305  raw_ostream &O) {
1306  printVectorList(MI, OpNum, STI, O, "");
1307 }
1308 
1309 template <unsigned NumLanes, char LaneKind>
1311  const MCSubtargetInfo &STI,
1312  raw_ostream &O) {
1313  std::string Suffix(".");
1314  if (NumLanes)
1315  Suffix += itostr(NumLanes) + LaneKind;
1316  else
1317  Suffix += LaneKind;
1318 
1319  printVectorList(MI, OpNum, STI, O, Suffix);
1320 }
1321 
1322 void AArch64InstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum,
1323  const MCSubtargetInfo &STI,
1324  raw_ostream &O) {
1325  O << "[" << MI->getOperand(OpNum).getImm() << "]";
1326 }
1327 
1329  const MCSubtargetInfo &STI,
1330  raw_ostream &O) {
1331  const MCOperand &Op = MI->getOperand(OpNum);
1332 
1333  // If the label has already been resolved to an immediate offset (say, when
1334  // we're running the disassembler), just print the immediate.
1335  if (Op.isImm()) {
1336  O << "#" << formatImm(Op.getImm() * 4);
1337  return;
1338  }
1339 
1340  // If the branch target is simply an address then print it in hex.
1341  const MCConstantExpr *BranchTarget =
1342  dyn_cast<MCConstantExpr>(MI->getOperand(OpNum).getExpr());
1343  int64_t Address;
1344  if (BranchTarget && BranchTarget->evaluateAsAbsolute(Address)) {
1345  O << "0x";
1346  O.write_hex(Address);
1347  } else {
1348  // Otherwise, just print the expression.
1349  MI->getOperand(OpNum).getExpr()->print(O, &MAI);
1350  }
1351 }
1352 
1353 void AArch64InstPrinter::printAdrpLabel(const MCInst *MI, unsigned OpNum,
1354  const MCSubtargetInfo &STI,
1355  raw_ostream &O) {
1356  const MCOperand &Op = MI->getOperand(OpNum);
1357 
1358  // If the label has already been resolved to an immediate offset (say, when
1359  // we're running the disassembler), just print the immediate.
1360  if (Op.isImm()) {
1361  O << "#" << formatImm(Op.getImm() * (1 << 12));
1362  return;
1363  }
1364 
1365  // Otherwise, just print the expression.
1366  MI->getOperand(OpNum).getExpr()->print(O, &MAI);
1367 }
1368 
1370  const MCSubtargetInfo &STI,
1371  raw_ostream &O) {
1372  unsigned Val = MI->getOperand(OpNo).getImm();
1373  unsigned Opcode = MI->getOpcode();
1374 
1375  StringRef Name;
1376  if (Opcode == AArch64::ISB) {
1377  auto ISB = AArch64ISB::lookupISBByEncoding(Val);
1378  Name = ISB ? ISB->Name : "";
1379  } else if (Opcode == AArch64::TSB) {
1380  auto TSB = AArch64TSB::lookupTSBByEncoding(Val);
1381  Name = TSB ? TSB->Name : "";
1382  } else {
1383  auto DB = AArch64DB::lookupDBByEncoding(Val);
1384  Name = DB ? DB->Name : "";
1385  }
1386  if (!Name.empty())
1387  O << Name;
1388  else
1389  O << "#" << Val;
1390 }
1391 
1393  const MCSubtargetInfo &STI,
1394  raw_ostream &O) {
1395  unsigned Val = MI->getOperand(OpNo).getImm();
1396 
1397  // Horrible hack for the one register that has identical encodings but
1398  // different names in MSR and MRS. Because of this, one of MRS and MSR is
1399  // going to get the wrong entry
1400  if (Val == AArch64SysReg::DBGDTRRX_EL0) {
1401  O << "DBGDTRRX_EL0";
1402  return;
1403  }
1404 
1406  if (Reg && Reg->Readable && Reg->haveFeatures(STI.getFeatureBits()))
1407  O << Reg->Name;
1408  else
1410 }
1411 
1413  const MCSubtargetInfo &STI,
1414  raw_ostream &O) {
1415  unsigned Val = MI->getOperand(OpNo).getImm();
1416 
1417  // Horrible hack for the one register that has identical encodings but
1418  // different names in MSR and MRS. Because of this, one of MRS and MSR is
1419  // going to get the wrong entry
1420  if (Val == AArch64SysReg::DBGDTRTX_EL0) {
1421  O << "DBGDTRTX_EL0";
1422  return;
1423  }
1424 
1426  if (Reg && Reg->Writeable && Reg->haveFeatures(STI.getFeatureBits()))
1427  O << Reg->Name;
1428  else
1430 }
1431 
1433  const MCSubtargetInfo &STI,
1434  raw_ostream &O) {
1435  unsigned Val = MI->getOperand(OpNo).getImm();
1436 
1437  auto PState = AArch64PState::lookupPStateByEncoding(Val);
1438  if (PState && PState->haveFeatures(STI.getFeatureBits()))
1439  O << PState->Name;
1440  else
1441  O << "#" << formatImm(Val);
1442 }
1443 
1445  const MCSubtargetInfo &STI,
1446  raw_ostream &O) {
1447  unsigned RawVal = MI->getOperand(OpNo).getImm();
1448  uint64_t Val = AArch64_AM::decodeAdvSIMDModImmType10(RawVal);
1449  O << format("#%#016llx", Val);
1450 }
1451 
1452 template<int64_t Angle, int64_t Remainder>
1454  const MCSubtargetInfo &STI,
1455  raw_ostream &O) {
1456  unsigned Val = MI->getOperand(OpNo).getImm();
1457  O << "#" << (Val * Angle) + Remainder;
1458 }
1459 
1460 void AArch64InstPrinter::printSVEPattern(const MCInst *MI, unsigned OpNum,
1461  const MCSubtargetInfo &STI,
1462  raw_ostream &O) {
1463  unsigned Val = MI->getOperand(OpNum).getImm();
1464  if (auto Pat = AArch64SVEPredPattern::lookupSVEPREDPATByEncoding(Val))
1465  O << Pat->Name;
1466  else
1467  O << '#' << formatImm(Val);
1468 }
1469 
1470 template <char suffix>
1471 void AArch64InstPrinter::printSVERegOp(const MCInst *MI, unsigned OpNum,
1472  const MCSubtargetInfo &STI,
1473  raw_ostream &O) {
1474  switch (suffix) {
1475  case 0:
1476  case 'b':
1477  case 'h':
1478  case 's':
1479  case 'd':
1480  case 'q':
1481  break;
1482  default: llvm_unreachable("Invalid kind specifier.");
1483  }
1484 
1485  unsigned Reg = MI->getOperand(OpNum).getReg();
1486  O << getRegisterName(Reg);
1487  if (suffix != 0)
1488  O << '.' << suffix;
1489 }
1490 
1491 template <typename T>
1493  typename std::make_unsigned<T>::type HexValue = Value;
1494 
1495  if (getPrintImmHex())
1496  O << '#' << formatHex((uint64_t)HexValue);
1497  else
1498  O << '#' << formatDec(Value);
1499 
1500  if (CommentStream) {
1501  // Do the opposite to that used for instruction operands.
1502  if (getPrintImmHex())
1503  *CommentStream << '=' << formatDec(HexValue) << '\n';
1504  else
1505  *CommentStream << '=' << formatHex((uint64_t)Value) << '\n';
1506  }
1507 }
1508 
1509 template <typename T>
1510 void AArch64InstPrinter::printImm8OptLsl(const MCInst *MI, unsigned OpNum,
1511  const MCSubtargetInfo &STI,
1512  raw_ostream &O) {
1513  unsigned UnscaledVal = MI->getOperand(OpNum).getImm();
1514  unsigned Shift = MI->getOperand(OpNum + 1).getImm();
1516  "Unexepected shift type!");
1517 
1518  // #0 lsl #8 is never pretty printed
1519  if ((UnscaledVal == 0) && (AArch64_AM::getShiftValue(Shift) != 0)) {
1520  O << '#' << formatImm(UnscaledVal);
1521  printShifter(MI, OpNum + 1, STI, O);
1522  return;
1523  }
1524 
1525  T Val;
1526  if (std::is_signed<T>())
1527  Val = (int8_t)UnscaledVal * (1 << AArch64_AM::getShiftValue(Shift));
1528  else
1529  Val = (uint8_t)UnscaledVal * (1 << AArch64_AM::getShiftValue(Shift));
1530 
1531  printImmSVE(Val, O);
1532 }
1533 
1534 template <typename T>
1536  const MCSubtargetInfo &STI,
1537  raw_ostream &O) {
1538  typedef typename std::make_signed<T>::type SignedT;
1539  typedef typename std::make_unsigned<T>::type UnsignedT;
1540 
1541  uint64_t Val = MI->getOperand(OpNum).getImm();
1542  UnsignedT PrintVal = AArch64_AM::decodeLogicalImmediate(Val, 64);
1543 
1544  // Prefer the default format for 16bit values, hex otherwise.
1545  if ((int16_t)PrintVal == (SignedT)PrintVal)
1546  printImmSVE((T)PrintVal, O);
1547  else if ((uint16_t)PrintVal == PrintVal)
1548  printImmSVE(PrintVal, O);
1549  else
1550  O << '#' << formatHex((uint64_t)PrintVal);
1551 }
1552 
1553 template <int Width>
1554 void AArch64InstPrinter::printZPRasFPR(const MCInst *MI, unsigned OpNum,
1555  const MCSubtargetInfo &STI,
1556  raw_ostream &O) {
1557  unsigned Base;
1558  switch (Width) {
1559  case 8: Base = AArch64::B0; break;
1560  case 16: Base = AArch64::H0; break;
1561  case 32: Base = AArch64::S0; break;
1562  case 64: Base = AArch64::D0; break;
1563  case 128: Base = AArch64::Q0; break;
1564  default:
1565  llvm_unreachable("Unsupported width");
1566  }
1567  unsigned Reg = MI->getOperand(OpNum).getReg();
1568  O << getRegisterName(Reg - AArch64::Z0 + Base);
1569 }
1570 
1571 template <unsigned ImmIs0, unsigned ImmIs1>
1572 void AArch64InstPrinter::printExactFPImm(const MCInst *MI, unsigned OpNum,
1573  const MCSubtargetInfo &STI,
1574  raw_ostream &O) {
1575  auto *Imm0Desc = AArch64ExactFPImm::lookupExactFPImmByEnum(ImmIs0);
1576  auto *Imm1Desc = AArch64ExactFPImm::lookupExactFPImmByEnum(ImmIs1);
1577  unsigned Val = MI->getOperand(OpNum).getImm();
1578  O << "#" << (Val ? Imm1Desc->Repr : Imm0Desc->Repr);
1579 }
1580 
1581 void AArch64InstPrinter::printGPR64as32(const MCInst *MI, unsigned OpNum,
1582  const MCSubtargetInfo &STI,
1583  raw_ostream &O) {
1584  unsigned Reg = MI->getOperand(OpNum).getReg();
1585  O << getRegisterName(getWRegFromXReg(Reg));
1586 }
void printImm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printAMIndexedWB(const MCInst *MI, unsigned OpNum, unsigned Scale, raw_ostream &O)
bool isImm() const
Definition: MCInst.h:58
static float getFPImmFloat(unsigned Imm)
void printRegName(raw_ostream &OS, unsigned RegNo) const override
Print the assembler register name.
void printShifter(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
static unsigned getArithShiftValue(unsigned Imm)
getArithShiftValue - get the arithmetic shift value.
void printVectorIndex(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printSysCROperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
This class represents lattice values for constants.
Definition: AllocatorList.h:23
static const LdStNInstrDesc LdStNInstInfo[]
amdgpu Simplify well known AMD library false FunctionCallee Value const Twine & Name
void printSystemPStateField(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
static CondCode getInvertedCondCode(CondCode Code)
unsigned Reg
format_object< Ts... > format(const char *Fmt, const Ts &... Vals)
These are helper functions used to produce formatted output.
Definition: Format.h:123
bool isReg() const
Definition: MCInst.h:57
void printImmHex(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printFPImmOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
static bool isMOVZMovAlias(uint64_t Value, int Shift, int RegWidth)
void printGPRSeqPairsClassOperand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
bool haveFeatures(FeatureBitset ActiveFeatures) const
void printMemExtend(const MCInst *MI, unsigned OpNum, raw_ostream &O, char SrcRegKind, unsigned Width)
void printSVELogicalImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot, const MCSubtargetInfo &STI) override
Print the specified MCInst to the specified raw_ostream.
void printUImm12Offset(const MCInst *MI, unsigned OpNum, unsigned Scale, raw_ostream &O)
void printImplicitlyTypedVectorList(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Print a list of vector registers where the type suffix is implicit (i.e.
static ManagedStatic< DebugCounter > DC
bool contains(unsigned Reg) const
contains - Return true if the specified register is included in this register class.
const FeatureBitset & getFeatureBits() const
void printSVERegOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printPrefetchOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVRegOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
format_object< int64_t > formatDec(int64_t Value) const
Utility functions to print decimal/hexadecimal values.
static const char * getCondCodeName(CondCode Code)
void printGPR64as32(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:126
unsigned getReg() const
Returns the register number.
Definition: MCInst.h:64
static bool isMOVNMovAlias(uint64_t Value, int Shift, int RegWidth)
static bool atomicBarrierDroppedOnZero(unsigned Opcode)
static unsigned getNextVectorRegister(unsigned Reg, unsigned Stride=1)
void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &O) override
std::string itostr(int64_t X)
Definition: StringExtras.h:238
void printInverseCondCode(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
AArch64InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
raw_ostream & write_hex(unsigned long long N)
Output N in hexadecimal, without any prefix or padding.
format_object< int64_t > formatImm(int64_t Value) const
Utility function to print immediates in decimal or hex.
Definition: MCInstPrinter.h:95
void printAlignedLabel(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
const MCExpr * getExpr() const
Definition: MCInst.h:95
MCRegisterClass - Base class of TargetRegisterClass.
void printImm8OptLsl(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot, const MCSubtargetInfo &STI) override
Print the specified MCInst to the specified raw_ostream.
void printImmSVE(T Value, raw_ostream &O)
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
static const char * getRegisterName(unsigned RegNo, unsigned AltIdx=AArch64::NoRegAltName)
static unsigned getWRegFromXReg(unsigned Reg)
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
void printLogicalImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:55
static unsigned getShiftValue(unsigned Imm)
getShiftValue - Extract the shift value.
int64_t getImm() const
Definition: MCInst.h:75
void print(raw_ostream &OS, const MCAsmInfo *MAI, bool InParens=false) const
Definition: MCExpr.cpp:41
unsigned const MachineRegisterInfo * MRI
void printPSBHintOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, const MCRegisterClass *RC) const
Return a super-register of the specified register Reg so its sub-register of index SubIdx is Reg...
static const char * getShiftExtendName(AArch64_AM::ShiftExtendType ST)
getShiftName - Get the string encoding for the shift type.
bool getPrintImmHex() const
Definition: MCInstPrinter.h:88
static AArch64_AM::ShiftExtendType getArithExtendType(unsigned Imm)
void printBTIHintOp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &O) override
static uint64_t decodeLogicalImmediate(uint64_t val, unsigned regSize)
decodeLogicalImmediate - Decode a logical immediate value in the form "N:immr:imms" (where the immr a...
bool isFPImm() const
Definition: MCInst.h:59
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:23
unsigned getSubReg(unsigned Reg, unsigned Idx) const
Returns the physical register number of sub-register "Index" for physical register RegNo...
StringRef getCommentString() const
Definition: MCAsmInfo.h:485
bool isExpr() const
Definition: MCInst.h:60
void printSIMDType10Operand(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printArithExtend(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printMSRSystemRegister(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAdrpLabel(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
const char * Name
void printPostIncOperand(const MCInst *MI, unsigned OpNo, unsigned Imm, raw_ostream &O)
void printBarrierOption(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printSVEPattern(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAMNoIndex(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
auto size(R &&Range, typename std::enable_if< std::is_same< typename std::iterator_traits< decltype(Range.begin())>::iterator_category, std::random_access_iterator_tag >::value, void >::type *=nullptr) -> decltype(std::distance(Range.begin(), Range.end()))
Get the size of a range.
Definition: STLExtras.h:1166
void printZPRasFPR(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:179
void printMRSSystemRegister(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
constexpr size_t array_lengthof(T(&)[N])
Find the length of an array.
Definition: STLExtras.h:1043
raw_ostream * CommentStream
A stream that comments can be emitted to if desired.
Definition: MCInstPrinter.h:44
void printComplexRotationOp(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
void printTypedVectorList(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printShiftedRegister(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
Definition: MathExtras.h:538
static const LdStNInstrDesc * getLdStNInstrDesc(unsigned Opcode)
std::string genericRegisterString(uint32_t Bits)
bool evaluateAsAbsolute(int64_t &Res, const MCAsmLayout &Layout, const SectionAddrMap &Addrs) const
Try to evaluate the expression to an absolute value.
Definition: MCExpr.cpp:455
bool haveFeatures(FeatureBitset ActiveFeatures) const
const MCAsmInfo & MAI
Definition: MCInstPrinter.h:45
void printExtendedRegister(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printExactFPImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printVectorList(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O, StringRef LayoutSuffix)
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
Definition: MCInstPrinter.h:39
void printAddSubImm(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
static AArch64_AM::ShiftExtendType getShiftType(unsigned Imm)
getShiftType - Extract the shift type.
static bool isAnyMOVWMovAlias(uint64_t Value, int RegWidth)
void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O)
static uint64_t decodeAdvSIMDModImmType10(uint8_t Imm)
format_object< int64_t > formatHex(int64_t Value) const
void printRegWithShiftExtend(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
Generic base class for all target subtargets.
const MCInstrInfo & MII
Definition: MCInstPrinter.h:46
AArch64AppleInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:322
constexpr int64_t SignExtend64(uint64_t x)
Sign-extend the number in the bottom B bits of X to a 64-bit integer.
Definition: MathExtras.h:748
OutputIt transform(R &&Range, OutputIt d_first, UnaryPredicate P)
Wrapper function around std::transform to apply a function to a range and store the result elsewhere...
Definition: STLExtras.h:1267
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
LLVM Value Representation.
Definition: Value.h:72
void printImmScale(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)
void printAnnotation(raw_ostream &OS, StringRef Annot)
Utility function for printing annotations.
const SysReg * lookupSysRegByEncoding(uint16_t)
This class implements an extremely fast bulk output stream that can only output to a stream...
Definition: raw_ostream.h:45
static bool isTblTbxInstruction(unsigned Opcode, StringRef &Layout, bool &IsTbx)
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
unsigned getOpcode() const
Definition: MCInst.h:171
static void printMemExtendImpl(bool SignExtend, bool DoShift, unsigned Width, char SrcRegKind, raw_ostream &O)
Instances of this class represent operands of the MCInst class.
Definition: MCInst.h:34
bool printSysAlias(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &O)
double getFPImm() const
Definition: MCInst.h:85
const MCRegisterClass & getRegClass(unsigned i) const
Returns the register class associated with the enumeration value.
const MCRegisterInfo & MRI
Definition: MCInstPrinter.h:47
void printCondCode(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O)