LLVM  6.0.0svn
Macros | Enumerations | Functions | Variables
AArch64InstrInfo.cpp File Reference
#include "AArch64InstrInfo.h"
#include "AArch64MachineFunctionInfo.h"
#include "AArch64Subtarget.h"
#include "MCTargetDesc/AArch64AddressingModes.h"
#include "Utils/AArch64BaseInfo.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/LiveRegUnits.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineMemOperand.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/StackMaps.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/GlobalValue.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include <cassert>
#include <cstdint>
#include <iterator>
#include <utility>
#include "AArch64GenInstrInfo.inc"
Include dependency graph for AArch64InstrInfo.cpp:

Go to the source code of this file.

Macros

#define GET_INSTRINFO_CTOR_DTOR
 

Enumerations

enum  AccessKind { AK_Write = 0x01, AK_Read = 0x10, AK_All = 0x11 }
 
enum  FMAInstKind { FMAInstKind::Default, FMAInstKind::Indexed, FMAInstKind::Accumulator }
 
enum  MachineOutlinerClass {
  MachineOutlinerDefault, MachineOutlinerTailCall, MachineOutlinerNoLRSave, MachineOutlinerDefault,
  MachineOutlinerTailCall
}
 Constants defining how certain sequences should be outlined. More...
 

Functions

static void parseCondBranch (MachineInstr *LastInst, MachineBasicBlock *&Target, SmallVectorImpl< MachineOperand > &Cond)
 
static unsigned getBranchDisplacementBits (unsigned Opc)
 
static unsigned removeCopies (const MachineRegisterInfo &MRI, unsigned VReg)
 
static unsigned canFoldIntoCSel (const MachineRegisterInfo &MRI, unsigned VReg, unsigned *NewVReg=nullptr)
 
static bool canBeExpandedToORR (const MachineInstr &MI, unsigned BitSize)
 Returns true if a MOVi32imm or MOVi64imm can be expanded to an ORRxx. More...
 
static bool UpdateOperandRegClass (MachineInstr &Instr)
 
static unsigned convertToNonFlagSettingOpc (const MachineInstr &MI)
 Return the opcode that does not set flags when possible - otherwise return the original opcode. More...
 
static bool areCFlagsAccessedBetweenInstrs (MachineBasicBlock::iterator From, MachineBasicBlock::iterator To, const TargetRegisterInfo *TRI, const AccessKind AccessToCheck=AK_All)
 True when condition flags are accessed (either by writing or reading) on the instruction trace starting at From and ending at To. More...
 
static unsigned sForm (MachineInstr &Instr)
 Get opcode of S version of Instr. More...
 
static bool areCFlagsAliveInSuccessors (MachineBasicBlock *MBB)
 Check if AArch64::NZCV should be alive in successors of MBB. More...
 
static AArch64CC::CondCode findCondCodeUsedByInstr (const MachineInstr &Instr)
 Find a condition code used by the instruction. More...
 
static UsedNZCV getUsedNZCV (AArch64CC::CondCode CC)
 
static bool isADDSRegImm (unsigned Opcode)
 
static bool isSUBSRegImm (unsigned Opcode)
 
static bool canInstrSubstituteCmpInstr (MachineInstr *MI, MachineInstr *CmpInstr, const TargetRegisterInfo *TRI)
 Check if CmpInstr can be substituted by MI. More...
 
static bool scaleOffset (unsigned Opc, int64_t &Offset)
 
static bool canPairLdStOpc (unsigned FirstOpc, unsigned SecondOpc)
 
static const MachineInstrBuilderAddSubReg (const MachineInstrBuilder &MIB, unsigned Reg, unsigned SubIdx, unsigned State, const TargetRegisterInfo *TRI)
 
static bool forwardCopyWillClobberTuple (unsigned DestReg, unsigned SrcReg, unsigned NumRegs)
 
static bool isCombineInstrSettingFlag (unsigned Opc)
 
static bool isCombineInstrCandidate32 (unsigned Opc)
 
static bool isCombineInstrCandidate64 (unsigned Opc)
 
static bool isCombineInstrCandidateFP (const MachineInstr &Inst)
 
static bool isCombineInstrCandidate (unsigned Opc)
 
static bool canCombine (MachineBasicBlock &MBB, MachineOperand &MO, unsigned CombineOpc, unsigned ZeroReg=0, bool CheckZeroReg=false)
 
static bool canCombineWithMUL (MachineBasicBlock &MBB, MachineOperand &MO, unsigned MulOpc, unsigned ZeroReg)
 
static bool canCombineWithFMUL (MachineBasicBlock &MBB, MachineOperand &MO, unsigned MulOpc)
 
static bool getMaddPatterns (MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns)
 Find instructions that can be turned into madd. More...
 
static bool getFMAPatterns (MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern > &Patterns)
 Floating-Point Support. More...
 
static MachineInstrgenFusedMultiply (MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo *TII, MachineInstr &Root, SmallVectorImpl< MachineInstr *> &InsInstrs, unsigned IdxMulOpd, unsigned MaddOpc, const TargetRegisterClass *RC, FMAInstKind kind=FMAInstKind::Default)
 genFusedMultiply - Generate fused multiply instructions. More...
 
static MachineInstrgenMaddR (MachineFunction &MF, MachineRegisterInfo &MRI, const TargetInstrInfo *TII, MachineInstr &Root, SmallVectorImpl< MachineInstr *> &InsInstrs, unsigned IdxMulOpd, unsigned MaddOpc, unsigned VR, const TargetRegisterClass *RC)
 genMaddR - Generate madd instruction and combine mul and add using an extra virtual register Example - an ADD intermediate needs to be stored in a register: MUL I=A,B,0 ADD R,I,Imm ==> ORR V, ZR, Imm ==> MADD R,A,B,V More...
 

Variables

static cl::opt< unsignedTBZDisplacementBits ("aarch64-tbz-offset-bits", cl::Hidden, cl::init(14), cl::desc("Restrict range of TB[N]Z instructions (DEBUG)"))
 
static cl::opt< unsignedCBZDisplacementBits ("aarch64-cbz-offset-bits", cl::Hidden, cl::init(19), cl::desc("Restrict range of CB[N]Z instructions (DEBUG)"))
 
static cl::opt< unsignedBCCDisplacementBits ("aarch64-bcc-offset-bits", cl::Hidden, cl::init(19), cl::desc("Restrict range of Bcc instructions (DEBUG)"))
 

Macro Definition Documentation

◆ GET_INSTRINFO_CTOR_DTOR

#define GET_INSTRINFO_CTOR_DTOR

Definition at line 53 of file AArch64InstrInfo.cpp.

Enumeration Type Documentation

◆ AccessKind

enum AccessKind
Enumerator
AK_Write 
AK_Read 
AK_All 

Definition at line 1185 of file AArch64InstrInfo.cpp.

◆ FMAInstKind

enum FMAInstKind
strong
Enumerator
Default 
Indexed 
Accumulator 

Definition at line 3775 of file AArch64InstrInfo.cpp.

◆ MachineOutlinerClass

Constants defining how certain sequences should be outlined.

This encompasses how an outlined function should be called, and what kind of frame should be emitted for that outlined function.

MachineOutlinerDefault implies that the function should be called with a save and restore of LR to the stack.

That is,

I1 Save LR OUTLINED_FUNCTION: I2 –> BL OUTLINED_FUNCTION I1 I3 Restore LR I2 I3 RET

  • Call construction overhead: 3 (save + BL + restore)
  • Frame construction overhead: 1 (ret)
  • Requires stack fixups? Yes

MachineOutlinerTailCall implies that the function is being created from a sequence of instructions ending in a return.

That is,

I1 OUTLINED_FUNCTION: I2 –> B OUTLINED_FUNCTION I1 RET I2 RET

  • Call construction overhead: 1 (B)
  • Frame construction overhead: 0 (Return included in sequence)
  • Requires stack fixups? No

MachineOutlinerNoLRSave implies that the function should be called using a BL instruction, but doesn't require LR to be saved and restored. This happens when LR is known to be dead.

That is,

I1 OUTLINED_FUNCTION: I2 –> BL OUTLINED_FUNCTION I1 I3 I2 I3 RET

  • Call construction overhead: 1 (BL)
  • Frame construction overhead: 1 (RET)
  • Requires stack fixups? No
Enumerator
MachineOutlinerDefault 
MachineOutlinerTailCall 

Emit a save, restore, call, and return.

MachineOutlinerNoLRSave 

Only emit a branch.

Emit a call and return.

MachineOutlinerDefault 
MachineOutlinerTailCall 

Definition at line 4593 of file AArch64InstrInfo.cpp.

Function Documentation

◆ AddSubReg()

static const MachineInstrBuilder& AddSubReg ( const MachineInstrBuilder MIB,
unsigned  Reg,
unsigned  SubIdx,
unsigned  State,
const TargetRegisterInfo TRI 
)
static

◆ areCFlagsAccessedBetweenInstrs()

static bool areCFlagsAccessedBetweenInstrs ( MachineBasicBlock::iterator  From,
MachineBasicBlock::iterator  To,
const TargetRegisterInfo TRI,
const AccessKind  AccessToCheck = AK_All 
)
static

True when condition flags are accessed (either by writing or reading) on the instruction trace starting at From and ending at To.

Note: If From and To are from different blocks it's assumed CC are accessed on the path.

Definition at line 1192 of file AArch64InstrInfo.cpp.

References AK_Read, AK_Write, assert(), llvm::find_if(), llvm::MachineInstrBundleIterator< Ty, IsReverse >::getReverse(), MI, llvm::MachineInstr::modifiesRegister(), and llvm::MachineInstr::readsRegister().

Referenced by canInstrSubstituteCmpInstr(), and llvm::AArch64InstrInfo::optimizeCondBranch().

◆ areCFlagsAliveInSuccessors()

static bool areCFlagsAliveInSuccessors ( MachineBasicBlock MBB)
static

Check if AArch64::NZCV should be alive in successors of MBB.

Definition at line 1325 of file AArch64InstrInfo.cpp.

References C, N, llvm::operator|=(), llvm::MachineBasicBlock::successors(), and llvm::Z.

Referenced by canInstrSubstituteCmpInstr().

◆ canBeExpandedToORR()

static bool canBeExpandedToORR ( const MachineInstr MI,
unsigned  BitSize 
)
static

Returns true if a MOVi32imm or MOVi64imm can be expanded to an ORRxx.

Definition at line 665 of file AArch64InstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOperand(), and llvm::AArch64_AM::processLogicalImmediate().

Referenced by llvm::AArch64InstrInfo::isAsCheapAsAMove().

◆ canCombine()

static bool canCombine ( MachineBasicBlock MBB,
MachineOperand MO,
unsigned  CombineOpc,
unsigned  ZeroReg = 0,
bool  CheckZeroReg = false 
)
static

◆ canCombineWithFMUL()

static bool canCombineWithFMUL ( MachineBasicBlock MBB,
MachineOperand MO,
unsigned  MulOpc 
)
static

Definition at line 3384 of file AArch64InstrInfo.cpp.

References canCombine().

Referenced by getFMAPatterns().

◆ canCombineWithMUL()

static bool canCombineWithMUL ( MachineBasicBlock MBB,
MachineOperand MO,
unsigned  MulOpc,
unsigned  ZeroReg 
)
static

Definition at line 3377 of file AArch64InstrInfo.cpp.

References canCombine().

Referenced by getMaddPatterns().

◆ canFoldIntoCSel()

static unsigned canFoldIntoCSel ( const MachineRegisterInfo MRI,
unsigned  VReg,
unsigned NewVReg = nullptr 
)
static

◆ canInstrSubstituteCmpInstr()

static bool canInstrSubstituteCmpInstr ( MachineInstr MI,
MachineInstr CmpInstr,
const TargetRegisterInfo TRI 
)
static

Check if CmpInstr can be substituted by MI.

CmpInstr can be substituted:

  • CmpInstr is either 'ADDS vreg, 0' or 'SUBS vreg, 0'
  • and, MI and CmpInstr are from the same MachineBB
  • and, condition flags are not alive in successors of the CmpInstr parent
  • and, if MI opcode is the S form there must be no defs of flags between MI and CmpInstr or if MI opcode is not the S form there must be neither defs of flags nor uses of flags between MI and CmpInstr.
  • and C/V flags are not used after CmpInstr

Definition at line 1447 of file AArch64InstrInfo.cpp.

References llvm::MachineInstr::addRegisterDefined(), AK_All, AK_Write, areCFlagsAccessedBetweenInstrs(), areCFlagsAliveInSuccessors(), assert(), E, llvm::MachineInstr::eraseFromParent(), findCondCodeUsedByInstr(), llvm::ilist_node_impl< OptionsT >::getIterator(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getParent(), llvm::AArch64InstrInfo::getRegisterInfo(), llvm::MachineRegisterInfo::getUniqueVRegDef(), getUsedNZCV(), I, llvm::MachineBasicBlock::instr_end(), llvm::AArch64CC::Invalid, isADDSRegImm(), isSUBSRegImm(), MI, llvm::MachineInstr::modifiesRegister(), MRI, llvm::MachineInstr::readsRegister(), llvm::MachineInstr::setDesc(), sForm(), and UpdateOperandRegClass().

◆ canPairLdStOpc()

static bool canPairLdStOpc ( unsigned  FirstOpc,
unsigned  SecondOpc 
)
static

Definition at line 2147 of file AArch64InstrInfo.cpp.

Referenced by llvm::AArch64InstrInfo::shouldClusterMemOps().

◆ convertToNonFlagSettingOpc()

static unsigned convertToNonFlagSettingOpc ( const MachineInstr MI)
static

Return the opcode that does not set flags when possible - otherwise return the original opcode.

The caller is responsible to do the actual substitution and legality checking.

Definition at line 1140 of file AArch64InstrInfo.cpp.

References llvm::MachineInstr::definesRegister(), and llvm::MachineInstr::getOpcode().

Referenced by getMaddPatterns(), and llvm::AArch64InstrInfo::optimizeCompareInstr().

◆ findCondCodeUsedByInstr()

static AArch64CC::CondCode findCondCodeUsedByInstr ( const MachineInstr Instr)
static

Find a condition code used by the instruction.

Returns AArch64CC::Invalid if either the instruction does not use condition codes or we don't optimize CmpInstr in the presence of such instructions.

Definition at line 1356 of file AArch64InstrInfo.cpp.

References assert(), llvm::MachineInstr::findRegisterUseOperandIdx(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::AArch64CC::Invalid.

Referenced by canInstrSubstituteCmpInstr().

◆ forwardCopyWillClobberTuple()

static bool forwardCopyWillClobberTuple ( unsigned  DestReg,
unsigned  SrcReg,
unsigned  NumRegs 
)
static

Definition at line 2225 of file AArch64InstrInfo.cpp.

Referenced by llvm::AArch64InstrInfo::copyPhysRegTuple().

◆ genFusedMultiply()

static MachineInstr* genFusedMultiply ( MachineFunction MF,
MachineRegisterInfo MRI,
const TargetInstrInfo TII,
MachineInstr Root,
SmallVectorImpl< MachineInstr *> &  InsInstrs,
unsigned  IdxMulOpd,
unsigned  MaddOpc,
const TargetRegisterClass RC,
FMAInstKind  kind = FMAInstKind::Default 
)
static

genFusedMultiply - Generate fused multiply instructions.

This function supports both integer and floating point instructions. A typical example: F|MUL I=A,B,0 F|ADD R,I,C ==> F|MADD R,A,B,C

Parameters
MFContaining MachineFunction
MRIRegister information
TIITarget information
Rootis the F|ADD instruction
[out]InsInstrsis a vector of machine instructions and will contain the generated madd instruction
IdxMulOpdis index of operand in Root that is the result of the F|MUL. In the example above IdxMulOpd is 1.
MaddOpcthe opcode fo the f|madd instruction
RCRegister class of operands
kindof fma instruction (addressing mode) to be generated

Definition at line 3794 of file AArch64InstrInfo.cpp.

References Accumulator, assert(), llvm::BuildMI(), llvm::MachineRegisterInfo::constrainRegClass(), Default, llvm::MCInstrInfo::get(), llvm::MachineInstr::getDebugLoc(), llvm::MachineOperand::getImm(), llvm::getKillRegState(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getUniqueVRegDef(), Indexed, llvm::MachineOperand::isKill(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::ISD::MUL, and llvm::SmallVectorTemplateBase< T, isPodLike >::push_back().

Referenced by llvm::AArch64InstrInfo::genAlternativeCodeSequence().

◆ genMaddR()

static MachineInstr* genMaddR ( MachineFunction MF,
MachineRegisterInfo MRI,
const TargetInstrInfo TII,
MachineInstr Root,
SmallVectorImpl< MachineInstr *> &  InsInstrs,
unsigned  IdxMulOpd,
unsigned  MaddOpc,
unsigned  VR,
const TargetRegisterClass RC 
)
static

genMaddR - Generate madd instruction and combine mul and add using an extra virtual register Example - an ADD intermediate needs to be stored in a register: MUL I=A,B,0 ADD R,I,Imm ==> ORR V, ZR, Imm ==> MADD R,A,B,V

Parameters
MFContaining MachineFunction
MRIRegister information
TIITarget information
Rootis the ADD instruction
[out]InsInstrsis a vector of machine instructions and will contain the generated madd instruction
IdxMulOpdis index of operand in Root that is the result of the MUL. In the example above IdxMulOpd is 1.
MaddOpcthe opcode fo the madd instruction
VRis a virtual register that holds the value of an ADD operand (V in the example above).
RCRegister class of operands

Definition at line 3863 of file AArch64InstrInfo.cpp.

References assert(), llvm::BuildMI(), llvm::MachineRegisterInfo::constrainRegClass(), llvm::MCInstrInfo::get(), llvm::MachineInstr::getDebugLoc(), llvm::getKillRegState(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineRegisterInfo::getUniqueVRegDef(), llvm::MachineOperand::isKill(), llvm::TargetRegisterInfo::isVirtualRegister(), llvm::ISD::MUL, and llvm::SmallVectorTemplateBase< T, isPodLike >::push_back().

Referenced by llvm::AArch64InstrInfo::genAlternativeCodeSequence().

◆ getBranchDisplacementBits()

static unsigned getBranchDisplacementBits ( unsigned  Opc)
static

◆ getFMAPatterns()

static bool getFMAPatterns ( MachineInstr Root,
SmallVectorImpl< MachineCombinerPattern > &  Patterns 
)
static

◆ getMaddPatterns()

static bool getMaddPatterns ( MachineInstr Root,
SmallVectorImpl< MachineCombinerPattern > &  Patterns 
)
static

◆ getUsedNZCV()

static UsedNZCV getUsedNZCV ( AArch64CC::CondCode  CC)
static

◆ isADDSRegImm()

static bool isADDSRegImm ( unsigned  Opcode)
static

Definition at line 1428 of file AArch64InstrInfo.cpp.

Referenced by canInstrSubstituteCmpInstr().

◆ isCombineInstrCandidate()

static bool isCombineInstrCandidate ( unsigned  Opc)
static

Definition at line 3341 of file AArch64InstrInfo.cpp.

References isCombineInstrCandidate32(), and isCombineInstrCandidate64().

Referenced by getMaddPatterns().

◆ isCombineInstrCandidate32()

static bool isCombineInstrCandidate32 ( unsigned  Opc)
static

Definition at line 3281 of file AArch64InstrInfo.cpp.

Referenced by isCombineInstrCandidate().

◆ isCombineInstrCandidate64()

static bool isCombineInstrCandidate64 ( unsigned  Opc)
static

Definition at line 3300 of file AArch64InstrInfo.cpp.

Referenced by isCombineInstrCandidate().

◆ isCombineInstrCandidateFP()

static bool isCombineInstrCandidateFP ( const MachineInstr Inst)
static

◆ isCombineInstrSettingFlag()

static bool isCombineInstrSettingFlag ( unsigned  Opc)
static

Definition at line 3262 of file AArch64InstrInfo.cpp.

Referenced by getMaddPatterns().

◆ isSUBSRegImm()

static bool isSUBSRegImm ( unsigned  Opcode)
static

Definition at line 1432 of file AArch64InstrInfo.cpp.

Referenced by canInstrSubstituteCmpInstr().

◆ parseCondBranch()

static void parseCondBranch ( MachineInstr LastInst,
MachineBasicBlock *&  Target,
SmallVectorImpl< MachineOperand > &  Cond 
)
static

◆ removeCopies()

static unsigned removeCopies ( const MachineRegisterInfo MRI,
unsigned  VReg 
)
static

◆ scaleOffset()

static bool scaleOffset ( unsigned  Opc,
int64_t &  Offset 
)
static

Definition at line 2113 of file AArch64InstrInfo.cpp.

Referenced by llvm::AArch64InstrInfo::shouldClusterMemOps().

◆ sForm()

static unsigned sForm ( MachineInstr Instr)
static

Get opcode of S version of Instr.

If Instr is S version its opcode is returned. AArch64::INSTRUCTION_LIST_END is returned if Instr does not have S version or we are not interested in it.

Definition at line 1278 of file AArch64InstrInfo.cpp.

References llvm::MachineInstr::getOpcode().

Referenced by canInstrSubstituteCmpInstr().

◆ UpdateOperandRegClass()

static bool UpdateOperandRegClass ( MachineInstr Instr)
static

Variable Documentation

◆ BCCDisplacementBits

cl::opt<unsigned> BCCDisplacementBits("aarch64-bcc-offset-bits", cl::Hidden, cl::init(19), cl::desc("Restrict range of Bcc instructions (DEBUG)"))
static

◆ CBZDisplacementBits

cl::opt<unsigned> CBZDisplacementBits("aarch64-cbz-offset-bits", cl::Hidden, cl::init(19), cl::desc("Restrict range of CB[N]Z instructions (DEBUG)"))
static

◆ TBZDisplacementBits

cl::opt<unsigned> TBZDisplacementBits("aarch64-tbz-offset-bits", cl::Hidden, cl::init(14), cl::desc("Restrict range of TB[N]Z instructions (DEBUG)"))
static