LLVM  7.0.0svn
AArch64MCTargetDesc.cpp
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1 //===-- AArch64MCTargetDesc.cpp - AArch64 Target Descriptions ---*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file provides AArch64 specific target descriptions.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "AArch64MCTargetDesc.h"
15 #include "AArch64ELFStreamer.h"
16 #include "AArch64MCAsmInfo.h"
17 #include "AArch64WinCOFFStreamer.h"
19 #include "llvm/MC/MCAsmBackend.h"
20 #include "llvm/MC/MCCodeEmitter.h"
22 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/MC/MCObjectWriter.h"
24 #include "llvm/MC/MCRegisterInfo.h"
25 #include "llvm/MC/MCStreamer.h"
29 
30 using namespace llvm;
31 
32 #define GET_INSTRINFO_MC_DESC
33 #include "AArch64GenInstrInfo.inc"
34 
35 #define GET_SUBTARGETINFO_MC_DESC
36 #include "AArch64GenSubtargetInfo.inc"
37 
38 #define GET_REGINFO_MC_DESC
39 #include "AArch64GenRegisterInfo.inc"
40 
42  MCInstrInfo *X = new MCInstrInfo();
43  InitAArch64MCInstrInfo(X);
44  return X;
45 }
46 
47 static MCSubtargetInfo *
49  if (CPU.empty())
50  CPU = "generic";
51 
52  return createAArch64MCSubtargetInfoImpl(TT, CPU, FS);
53 }
54 
56  for (unsigned Reg = AArch64::NoRegister + 1;
57  Reg < AArch64::NUM_TARGET_REGS; ++Reg) {
58  unsigned CV = MRI->getEncodingValue(Reg);
59  MRI->mapLLVMRegToCVReg(Reg, CV);
60  }
61 }
62 
65  InitAArch64MCRegisterInfo(X, AArch64::LR);
67  return X;
68 }
69 
71  const Triple &TheTriple) {
72  MCAsmInfo *MAI;
73  if (TheTriple.isOSBinFormatMachO())
74  MAI = new AArch64MCAsmInfoDarwin();
75  else if (TheTriple.isWindowsMSVCEnvironment())
77  else if (TheTriple.isOSBinFormatCOFF())
78  MAI = new AArch64MCAsmInfoGNUCOFF();
79  else {
80  assert(TheTriple.isOSBinFormatELF() && "Invalid target");
81  MAI = new AArch64MCAsmInfoELF(TheTriple);
82  }
83 
84  // Initial state of the frame pointer is SP.
85  unsigned Reg = MRI.getDwarfRegNum(AArch64::SP, true);
86  MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 0);
87  MAI->addInitialFrameState(Inst);
88 
89  return MAI;
90 }
91 
93  unsigned SyntaxVariant,
94  const MCAsmInfo &MAI,
95  const MCInstrInfo &MII,
96  const MCRegisterInfo &MRI) {
97  if (SyntaxVariant == 0)
98  return new AArch64InstPrinter(MAI, MII, MRI);
99  if (SyntaxVariant == 1)
100  return new AArch64AppleInstPrinter(MAI, MII, MRI);
101 
102  return nullptr;
103 }
104 
106  std::unique_ptr<MCAsmBackend> &&TAB,
107  std::unique_ptr<MCObjectWriter> &&OW,
108  std::unique_ptr<MCCodeEmitter> &&Emitter,
109  bool RelaxAll) {
110  return createAArch64ELFStreamer(Ctx, std::move(TAB), std::move(OW),
111  std::move(Emitter), RelaxAll);
112 }
113 
115  std::unique_ptr<MCAsmBackend> &&TAB,
116  std::unique_ptr<MCObjectWriter> &&OW,
117  std::unique_ptr<MCCodeEmitter> &&Emitter,
118  bool RelaxAll,
119  bool DWARFMustBeAtTheEnd) {
120  return createMachOStreamer(Ctx, std::move(TAB), std::move(OW),
121  std::move(Emitter), RelaxAll, DWARFMustBeAtTheEnd,
122  /*LabelSections*/ true);
123 }
124 
125 static MCStreamer *
126 createWinCOFFStreamer(MCContext &Ctx, std::unique_ptr<MCAsmBackend> &&TAB,
127  std::unique_ptr<MCObjectWriter> &&OW,
128  std::unique_ptr<MCCodeEmitter> &&Emitter, bool RelaxAll,
129  bool IncrementalLinkerCompatible) {
130  return createAArch64WinCOFFStreamer(Ctx, std::move(TAB), std::move(OW),
131  std::move(Emitter), RelaxAll,
132  IncrementalLinkerCompatible);
133 }
134 
135 namespace {
136 
137 class AArch64MCInstrAnalysis : public MCInstrAnalysis {
138 public:
139  AArch64MCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
140 
141  bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
142  uint64_t &Target) const override {
143  if (Inst.getNumOperands() == 0 ||
144  Info->get(Inst.getOpcode()).OpInfo[0].OperandType !=
146  return false;
147 
148  int64_t Imm = Inst.getOperand(0).getImm() * 4;
149  Target = Addr + Imm;
150  return true;
151  }
152 };
153 
154 } // end anonymous namespace
155 
157  return new AArch64MCInstrAnalysis(Info);
158 }
159 
160 // Force static initialization.
161 extern "C" void LLVMInitializeAArch64TargetMC() {
163  &getTheARM64Target()}) {
164  // Register the MC asm info.
166 
167  // Register the MC instruction info.
169 
170  // Register the MC register info.
172 
173  // Register the MC subtarget info.
175 
176  // Register the MC instruction analyzer.
178 
179  // Register the MC Code Emitter
181 
182  // Register the obj streamers.
186 
187  // Register the obj target streamer.
190 
191  // Register the asm streamer.
194  // Register the MCInstPrinter.
196  }
197 
198  // Register the asm backend.
203 }
Target & getTheAArch64beTarget()
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
static MCInstrAnalysis * createAArch64InstrAnalysis(const MCInstrInfo *Info)
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:586
Target & getTheAArch64leTarget()
static void RegisterMCInstrAnalysis(Target &T, Target::MCInstrAnalysisCtorFnTy Fn)
RegisterMCInstrAnalysis - Register a MCInstrAnalysis implementation for the given target...
unsigned Reg
MCWinCOFFStreamer * createAArch64WinCOFFStreamer(MCContext &Context, std::unique_ptr< MCAsmBackend > MAB, std::unique_ptr< MCObjectWriter > OW, std::unique_ptr< MCCodeEmitter > Emitter, bool RelaxAll, bool IncrementalLinkerCompatible)
static MCInstrInfo * createAArch64MCInstrInfo()
static void RegisterMCInstPrinter(Target &T, Target::MCInstPrinterCtorTy Fn)
RegisterMCInstPrinter - Register a MCInstPrinter implementation for the given target.
static void RegisterAsmTargetStreamer(Target &T, Target::AsmTargetStreamerCtorTy Fn)
MCAsmBackend * createAArch64leAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
int getDwarfRegNum(unsigned RegNum, bool isEH) const
Map a target register to an equivalent dwarf register number.
Target & getTheARM64Target()
static void RegisterCOFFStreamer(Target &T, Target::COFFStreamerCtorTy Fn)
Context object for machine code objects.
Definition: MCContext.h:63
void addInitialFrameState(const MCCFIInstruction &Inst)
Definition: MCAsmInfo.h:596
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:133
static MCSubtargetInfo * createAArch64MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
MCELFStreamer * createAArch64ELFStreamer(MCContext &Context, std::unique_ptr< MCAsmBackend > TAB, std::unique_ptr< MCObjectWriter > OW, std::unique_ptr< MCCodeEmitter > Emitter, bool RelaxAll)
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:161
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:56
int64_t getImm() const
Definition: MCInst.h:76
static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn)
RegisterMCAsmBackend - Register a MCAsmBackend implementation for the given target.
Streaming machine code generation interface.
Definition: MCStreamer.h:183
unsigned const MachineRegisterInfo * MRI
static MCCFIInstruction createDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it...
Definition: MCDwarf.h:453
static MCRegisterInfo * createAArch64MCRegisterInfo(const Triple &Triple)
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
Definition: Triple.h:591
static void RegisterMachOStreamer(Target &T, Target::MachOStreamerCtorTy Fn)
MCStreamer * createELFStreamer(MCContext &Ctx, std::unique_ptr< MCAsmBackend > &&TAB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&CE, bool RelaxAll)
static MCAsmInfo * createAArch64MCAsmInfo(const MCRegisterInfo &MRI, const Triple &TheTriple)
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:24
unsigned getNumOperands() const
Definition: MCInst.h:184
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:596
static MCInstPrinter * createAArch64MCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
static void RegisterMCSubtargetInfo(Target &T, Target::MCSubtargetInfoCtorFnTy Fn)
RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for the given target...
static void RegisterObjectTargetStreamer(Target &T, Target::ObjectTargetStreamerCtorTy Fn)
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
MCTargetStreamer * createAArch64ObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
MCCodeEmitter * createAArch64MCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:182
static void RegisterMCCodeEmitter(Target &T, Target::MCCodeEmitterCtorTy Fn)
RegisterMCCodeEmitter - Register a MCCodeEmitter implementation for the given target.
static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn)
RegisterMCRegInfo - Register a MCRegisterInfo implementation for the given target.
Target - Wrapper for Target specific information.
static MCStreamer * createWinCOFFStreamer(MCContext &Ctx, std::unique_ptr< MCAsmBackend > &&TAB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&Emitter, bool RelaxAll, bool IncrementalLinkerCompatible)
MCAsmBackend * createAArch64beAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
void initLLVMToCVRegMapping(MCRegisterInfo *MRI)
OperandType
Operands are tagged with one of the values of this enum.
Definition: MCInstrDesc.h:44
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
Definition: MCInstPrinter.h:40
uint16_t getEncodingValue(unsigned RegNo) const
Returns the encoding for RegNo.
void mapLLVMRegToCVReg(unsigned LLVMReg, int CVReg)
MCTargetStreamer * createAArch64AsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrint, bool isVerboseAsm)
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:45
static void RegisterMCInstrInfo(Target &T, Target::MCInstrInfoCtorFnTy Fn)
RegisterMCInstrInfo - Register a MCInstrInfo implementation for the given target. ...
Generic base class for all target subtargets.
static void RegisterELFStreamer(Target &T, Target::ELFStreamerCtorTy Fn)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
RegisterMCAsmInfoFn - Helper template for registering a target assembly info implementation.
constexpr char Size[]
Key for Kernel::Arg::Metadata::mSize.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
MCStreamer * createMachOStreamer(MCContext &Ctx, std::unique_ptr< MCAsmBackend > &&TAB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&CE, bool RelaxAll, bool DWARFMustBeAtTheEnd, bool LabelSections=false)
unsigned getOpcode() const
Definition: MCInst.h:174
bool isWindowsMSVCEnvironment() const
Checks if the environment could be MSVC.
Definition: Triple.h:521
void LLVMInitializeAArch64TargetMC()