LLVM  9.0.0svn
AArch64MCTargetDesc.cpp
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1 //===-- AArch64MCTargetDesc.cpp - AArch64 Target Descriptions ---*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides AArch64 specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "AArch64MCTargetDesc.h"
14 #include "AArch64ELFStreamer.h"
15 #include "AArch64MCAsmInfo.h"
16 #include "AArch64WinCOFFStreamer.h"
19 #include "llvm/MC/MCAsmBackend.h"
20 #include "llvm/MC/MCCodeEmitter.h"
22 #include "llvm/MC/MCInstrInfo.h"
23 #include "llvm/MC/MCObjectWriter.h"
24 #include "llvm/MC/MCRegisterInfo.h"
25 #include "llvm/MC/MCStreamer.h"
27 #include "llvm/Support/Endian.h"
30 
31 using namespace llvm;
32 
33 #define GET_INSTRINFO_MC_DESC
34 #define GET_INSTRINFO_MC_HELPERS
35 #include "AArch64GenInstrInfo.inc"
36 
37 #define GET_SUBTARGETINFO_MC_DESC
38 #include "AArch64GenSubtargetInfo.inc"
39 
40 #define GET_REGINFO_MC_DESC
41 #include "AArch64GenRegisterInfo.inc"
42 
44  MCInstrInfo *X = new MCInstrInfo();
45  InitAArch64MCInstrInfo(X);
46  return X;
47 }
48 
49 static MCSubtargetInfo *
51  if (CPU.empty())
52  CPU = "generic";
53 
54  return createAArch64MCSubtargetInfoImpl(TT, CPU, FS);
55 }
56 
58  for (unsigned Reg = AArch64::NoRegister + 1;
59  Reg < AArch64::NUM_TARGET_REGS; ++Reg) {
60  unsigned CV = MRI->getEncodingValue(Reg);
61  MRI->mapLLVMRegToCVReg(Reg, CV);
62  }
63 }
64 
67  InitAArch64MCRegisterInfo(X, AArch64::LR);
69  return X;
70 }
71 
73  const Triple &TheTriple) {
74  MCAsmInfo *MAI;
75  if (TheTriple.isOSBinFormatMachO())
76  MAI = new AArch64MCAsmInfoDarwin();
77  else if (TheTriple.isWindowsMSVCEnvironment())
79  else if (TheTriple.isOSBinFormatCOFF())
80  MAI = new AArch64MCAsmInfoGNUCOFF();
81  else {
82  assert(TheTriple.isOSBinFormatELF() && "Invalid target");
83  MAI = new AArch64MCAsmInfoELF(TheTriple);
84  }
85 
86  // Initial state of the frame pointer is SP.
87  unsigned Reg = MRI.getDwarfRegNum(AArch64::SP, true);
88  MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 0);
89  MAI->addInitialFrameState(Inst);
90 
91  return MAI;
92 }
93 
95  unsigned SyntaxVariant,
96  const MCAsmInfo &MAI,
97  const MCInstrInfo &MII,
98  const MCRegisterInfo &MRI) {
99  if (SyntaxVariant == 0)
100  return new AArch64InstPrinter(MAI, MII, MRI);
101  if (SyntaxVariant == 1)
102  return new AArch64AppleInstPrinter(MAI, MII, MRI);
103 
104  return nullptr;
105 }
106 
108  std::unique_ptr<MCAsmBackend> &&TAB,
109  std::unique_ptr<MCObjectWriter> &&OW,
110  std::unique_ptr<MCCodeEmitter> &&Emitter,
111  bool RelaxAll) {
112  return createAArch64ELFStreamer(Ctx, std::move(TAB), std::move(OW),
113  std::move(Emitter), RelaxAll);
114 }
115 
117  std::unique_ptr<MCAsmBackend> &&TAB,
118  std::unique_ptr<MCObjectWriter> &&OW,
119  std::unique_ptr<MCCodeEmitter> &&Emitter,
120  bool RelaxAll,
121  bool DWARFMustBeAtTheEnd) {
122  return createMachOStreamer(Ctx, std::move(TAB), std::move(OW),
123  std::move(Emitter), RelaxAll, DWARFMustBeAtTheEnd,
124  /*LabelSections*/ true);
125 }
126 
127 static MCStreamer *
128 createWinCOFFStreamer(MCContext &Ctx, std::unique_ptr<MCAsmBackend> &&TAB,
129  std::unique_ptr<MCObjectWriter> &&OW,
130  std::unique_ptr<MCCodeEmitter> &&Emitter, bool RelaxAll,
131  bool IncrementalLinkerCompatible) {
132  return createAArch64WinCOFFStreamer(Ctx, std::move(TAB), std::move(OW),
133  std::move(Emitter), RelaxAll,
134  IncrementalLinkerCompatible);
135 }
136 
137 namespace {
138 
139 class AArch64MCInstrAnalysis : public MCInstrAnalysis {
140 public:
141  AArch64MCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
142 
143  bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size,
144  uint64_t &Target) const override {
145  // Search for a PC-relative argument.
146  // This will handle instructions like bcc (where the first argument is the
147  // condition code) and cbz (where it is a register).
148  const auto &Desc = Info->get(Inst.getOpcode());
149  for (unsigned i = 0, e = Inst.getNumOperands(); i != e; i++) {
150  if (Desc.OpInfo[i].OperandType == MCOI::OPERAND_PCREL) {
151  int64_t Imm = Inst.getOperand(i).getImm() * 4;
152  Target = Addr + Imm;
153  return true;
154  }
155  }
156  return false;
157  }
158 
159  std::vector<std::pair<uint64_t, uint64_t>>
160  findPltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents,
161  uint64_t GotPltSectionVA,
162  const Triple &TargetTriple) const override {
163  // Do a lightweight parsing of PLT entries.
164  std::vector<std::pair<uint64_t, uint64_t>> Result;
165  for (uint64_t Byte = 0, End = PltContents.size(); Byte + 7 < End;
166  Byte += 4) {
167  uint32_t Insn = support::endian::read32le(PltContents.data() + Byte);
168  // Check for adrp.
169  if ((Insn & 0x9f000000) != 0x90000000)
170  continue;
171  uint64_t Imm = (((PltSectionVA + Byte) >> 12) << 12) +
172  (((Insn >> 29) & 3) << 12) + (((Insn >> 5) & 0x3ffff) << 14);
173  uint32_t Insn2 = support::endian::read32le(PltContents.data() + Byte + 4);
174  // Check for: ldr Xt, [Xn, #pimm].
175  if (Insn2 >> 22 == 0x3e5) {
176  Imm += ((Insn2 >> 10) & 0xfff) << 3;
177  Result.push_back(std::make_pair(PltSectionVA + Byte, Imm));
178  Byte += 4;
179  }
180  }
181  return Result;
182  }
183 };
184 
185 } // end anonymous namespace
186 
188  return new AArch64MCInstrAnalysis(Info);
189 }
190 
191 // Force static initialization.
192 extern "C" void LLVMInitializeAArch64TargetMC() {
194  &getTheARM64Target()}) {
195  // Register the MC asm info.
197 
198  // Register the MC instruction info.
200 
201  // Register the MC register info.
203 
204  // Register the MC subtarget info.
206 
207  // Register the MC instruction analyzer.
209 
210  // Register the MC Code Emitter
212 
213  // Register the obj streamers.
217 
218  // Register the obj target streamer.
221 
222  // Register the asm streamer.
225  // Register the MCInstPrinter.
227  }
228 
229  // Register the asm backend.
234 }
Target & getTheAArch64beTarget()
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
static MCInstrAnalysis * createAArch64InstrAnalysis(const MCInstrInfo *Info)
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:602
Target & getTheAArch64leTarget()
static void RegisterMCInstrAnalysis(Target &T, Target::MCInstrAnalysisCtorFnTy Fn)
RegisterMCInstrAnalysis - Register a MCInstrAnalysis implementation for the given target...
unsigned Reg
MCWinCOFFStreamer * createAArch64WinCOFFStreamer(MCContext &Context, std::unique_ptr< MCAsmBackend > MAB, std::unique_ptr< MCObjectWriter > OW, std::unique_ptr< MCCodeEmitter > Emitter, bool RelaxAll, bool IncrementalLinkerCompatible)
static MCInstrInfo * createAArch64MCInstrInfo()
static void RegisterMCInstPrinter(Target &T, Target::MCInstPrinterCtorTy Fn)
RegisterMCInstPrinter - Register a MCInstPrinter implementation for the given target.
static void RegisterAsmTargetStreamer(Target &T, Target::AsmTargetStreamerCtorTy Fn)
MCAsmBackend * createAArch64leAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
int getDwarfRegNum(unsigned RegNum, bool isEH) const
Map a target register to an equivalent dwarf register number.
Target & getTheARM64Target()
static void RegisterCOFFStreamer(Target &T, Target::COFFStreamerCtorTy Fn)
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:126
Context object for machine code objects.
Definition: MCContext.h:62
void addInitialFrameState(const MCCFIInstruction &Inst)
Definition: MCAsmInfo.h:600
static MCSubtargetInfo * createAArch64MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS)
MCELFStreamer * createAArch64ELFStreamer(MCContext &Context, std::unique_ptr< MCAsmBackend > TAB, std::unique_ptr< MCObjectWriter > OW, std::unique_ptr< MCCodeEmitter > Emitter, bool RelaxAll)
Instances of this class represent a single low-level machine instruction.
Definition: MCInst.h:158
Analysis containing CSE Info
Definition: CSEInfo.cpp:20
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
This class is intended to be used as a base class for asm properties and features specific to the tar...
Definition: MCAsmInfo.h:55
int64_t getImm() const
Definition: MCInst.h:75
static void RegisterMCAsmBackend(Target &T, Target::MCAsmBackendCtorTy Fn)
RegisterMCAsmBackend - Register a MCAsmBackend implementation for the given target.
Streaming machine code generation interface.
Definition: MCStreamer.h:188
unsigned const MachineRegisterInfo * MRI
static MCCFIInstruction createDefCfa(MCSymbol *L, unsigned Register, int Offset)
.cfi_def_cfa defines a rule for computing CFA as: take address from Register and add Offset to it...
Definition: MCDwarf.h:460
static MCRegisterInfo * createAArch64MCRegisterInfo(const Triple &Triple)
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
Definition: Triple.h:607
static void RegisterMachOStreamer(Target &T, Target::MachOStreamerCtorTy Fn)
size_t size() const
size - Get the array size.
Definition: ArrayRef.h:148
MCStreamer * createELFStreamer(MCContext &Ctx, std::unique_ptr< MCAsmBackend > &&TAB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&CE, bool RelaxAll)
static MCAsmInfo * createAArch64MCAsmInfo(const MCRegisterInfo &MRI, const Triple &TheTriple)
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:23
unsigned getNumOperands() const
Definition: MCInst.h:181
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:612
static MCInstPrinter * createAArch64MCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)
static void RegisterMCSubtargetInfo(Target &T, Target::MCSubtargetInfoCtorFnTy Fn)
RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for the given target...
static void RegisterObjectTargetStreamer(Target &T, Target::ObjectTargetStreamerCtorTy Fn)
const T * data() const
Definition: ArrayRef.h:145
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
MCTargetStreamer * createAArch64ObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
MCCodeEmitter * createAArch64MCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
const MCOperand & getOperand(unsigned i) const
Definition: MCInst.h:179
static void RegisterMCCodeEmitter(Target &T, Target::MCCodeEmitterCtorTy Fn)
RegisterMCCodeEmitter - Register a MCCodeEmitter implementation for the given target.
static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn)
RegisterMCRegInfo - Register a MCRegisterInfo implementation for the given target.
Target - Wrapper for Target specific information.
static MCStreamer * createWinCOFFStreamer(MCContext &Ctx, std::unique_ptr< MCAsmBackend > &&TAB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&Emitter, bool RelaxAll, bool IncrementalLinkerCompatible)
MCAsmBackend * createAArch64beAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
void initLLVMToCVRegMapping(MCRegisterInfo *MRI)
This is an instance of a target assembly language printer that converts an MCInst to valid target ass...
Definition: MCInstPrinter.h:39
uint16_t getEncodingValue(unsigned RegNo) const
Returns the encoding for RegNo.
void mapLLVMRegToCVReg(unsigned LLVMReg, int CVReg)
MCTargetStreamer * createAArch64AsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrint, bool isVerboseAsm)
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode...
Definition: MCInstrInfo.h:44
static void RegisterMCInstrInfo(Target &T, Target::MCInstrInfoCtorFnTy Fn)
RegisterMCInstrInfo - Register a MCInstrInfo implementation for the given target. ...
uint32_t read32le(const void *P)
Definition: Endian.h:368
Generic base class for all target subtargets.
uint32_t Size
Definition: Profile.cpp:46
static void RegisterELFStreamer(Target &T, Target::ELFStreamerCtorTy Fn)
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
RegisterMCAsmInfoFn - Helper template for registering a target assembly info implementation.
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
MCStreamer * createMachOStreamer(MCContext &Ctx, std::unique_ptr< MCAsmBackend > &&TAB, std::unique_ptr< MCObjectWriter > &&OW, std::unique_ptr< MCCodeEmitter > &&CE, bool RelaxAll, bool DWARFMustBeAtTheEnd, bool LabelSections=false)
unsigned getOpcode() const
Definition: MCInst.h:171
bool isWindowsMSVCEnvironment() const
Checks if the environment could be MSVC.
Definition: Triple.h:537
void LLVMInitializeAArch64TargetMC()