LLVM  9.0.0svn
AArch64MCTargetDesc.h
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1 //===-- AArch64MCTargetDesc.h - AArch64 Target Descriptions -----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides AArch64 specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64MCTARGETDESC_H
14 #define LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64MCTARGETDESC_H
15 
16 #include "llvm/Support/DataTypes.h"
17 
18 #include <memory>
19 
20 namespace llvm {
21 class formatted_raw_ostream;
22 class MCAsmBackend;
23 class MCCodeEmitter;
24 class MCContext;
25 class MCInstrInfo;
26 class MCInstPrinter;
27 class MCRegisterInfo;
28 class MCObjectTargetWriter;
29 class MCStreamer;
30 class MCSubtargetInfo;
31 class MCTargetOptions;
32 class MCTargetStreamer;
33 class StringRef;
34 class Target;
35 class Triple;
36 class raw_ostream;
37 class raw_pwrite_stream;
38 
39 Target &getTheAArch64leTarget();
40 Target &getTheAArch64beTarget();
41 Target &getTheARM64Target();
42 
43 MCCodeEmitter *createAArch64MCCodeEmitter(const MCInstrInfo &MCII,
44  const MCRegisterInfo &MRI,
45  MCContext &Ctx);
46 MCAsmBackend *createAArch64leAsmBackend(const Target &T,
47  const MCSubtargetInfo &STI,
48  const MCRegisterInfo &MRI,
49  const MCTargetOptions &Options);
50 MCAsmBackend *createAArch64beAsmBackend(const Target &T,
51  const MCSubtargetInfo &STI,
52  const MCRegisterInfo &MRI,
53  const MCTargetOptions &Options);
54 
55 std::unique_ptr<MCObjectTargetWriter>
56 createAArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32);
57 
58 std::unique_ptr<MCObjectTargetWriter>
60 
61 std::unique_ptr<MCObjectTargetWriter> createAArch64WinCOFFObjectWriter();
62 
63 MCTargetStreamer *createAArch64AsmTargetStreamer(MCStreamer &S,
64  formatted_raw_ostream &OS,
65  MCInstPrinter *InstPrint,
66  bool isVerboseAsm);
67 
68 MCTargetStreamer *createAArch64ObjectTargetStreamer(MCStreamer &S,
69  const MCSubtargetInfo &STI);
70 
71 namespace AArch64_MC {
73 }
74 
75 } // End llvm namespace
76 
77 // Defines symbolic names for AArch64 registers. This defines a mapping from
78 // register name to register number.
79 //
80 #define GET_REGINFO_ENUM
81 #include "AArch64GenRegisterInfo.inc"
82 
83 // Defines symbolic names for the AArch64 instructions.
84 //
85 #define GET_INSTRINFO_ENUM
86 #define GET_INSTRINFO_MC_HELPER_DECLS
87 #include "AArch64GenInstrInfo.inc"
88 
89 #define GET_SUBTARGETINFO_ENUM
90 #include "AArch64GenSubtargetInfo.inc"
91 
92 #endif
Target & getTheAArch64beTarget()
This class represents lattice values for constants.
Definition: AllocatorList.h:23
std::unique_ptr< MCObjectTargetWriter > createAArch64MachObjectWriter(uint32_t CPUType, uint32_t CPUSubtype)
Target & getTheAArch64leTarget()
MCAsmBackend * createAArch64leAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
Target & getTheARM64Target()
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
unsigned const MachineRegisterInfo * MRI
std::unique_ptr< MCObjectTargetWriter > createAArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32)
MCTargetStreamer * createAArch64ObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
MCCodeEmitter * createAArch64MCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
MCAsmBackend * createAArch64beAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCRegisterInfo &MRI, const MCTargetOptions &Options)
void initLLVMToCVRegMapping(MCRegisterInfo *MRI)
MCTargetStreamer * createAArch64AsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrint, bool isVerboseAsm)
std::unique_ptr< MCObjectTargetWriter > createAArch64WinCOFFObjectWriter()