LLVM  6.0.0svn
AArch64MCTargetDesc.h
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1 //===-- AArch64MCTargetDesc.h - AArch64 Target Descriptions -----*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file provides AArch64 specific target descriptions.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64MCTARGETDESC_H
15 #define LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64MCTARGETDESC_H
16 
17 #include "llvm/Support/DataTypes.h"
18 
19 #include <memory>
20 
21 namespace llvm {
22 class formatted_raw_ostream;
23 class MCAsmBackend;
24 class MCCodeEmitter;
25 class MCContext;
26 class MCInstrInfo;
27 class MCInstPrinter;
28 class MCRegisterInfo;
29 class MCObjectWriter;
30 class MCStreamer;
31 class MCSubtargetInfo;
32 class MCTargetOptions;
33 class MCTargetStreamer;
34 class StringRef;
35 class Target;
36 class Triple;
37 class raw_ostream;
38 class raw_pwrite_stream;
39 
40 Target &getTheAArch64leTarget();
41 Target &getTheAArch64beTarget();
42 Target &getTheARM64Target();
43 
44 MCCodeEmitter *createAArch64MCCodeEmitter(const MCInstrInfo &MCII,
45  const MCRegisterInfo &MRI,
46  MCContext &Ctx);
47 MCAsmBackend *createAArch64leAsmBackend(const Target &T,
48  const MCRegisterInfo &MRI,
49  const Triple &TT, StringRef CPU,
50  const MCTargetOptions &Options);
51 MCAsmBackend *createAArch64beAsmBackend(const Target &T,
52  const MCRegisterInfo &MRI,
53  const Triple &TT, StringRef CPU,
54  const MCTargetOptions &Options);
55 
56 std::unique_ptr<MCObjectWriter>
57 createAArch64ELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI,
58  bool IsLittleEndian, bool IsILP32);
59 
60 std::unique_ptr<MCObjectWriter>
61 createAArch64MachObjectWriter(raw_pwrite_stream &OS, uint32_t CPUType,
62  uint32_t CPUSubtype);
63 
64 std::unique_ptr<MCObjectWriter>
65 createAArch64WinCOFFObjectWriter(raw_pwrite_stream &OS);
66 
67 MCTargetStreamer *createAArch64AsmTargetStreamer(MCStreamer &S,
68  formatted_raw_ostream &OS,
69  MCInstPrinter *InstPrint,
70  bool isVerboseAsm);
71 
72 MCTargetStreamer *createAArch64ObjectTargetStreamer(MCStreamer &S,
73  const MCSubtargetInfo &STI);
74 
75 namespace AArch64_MC {
77 }
78 
79 } // End llvm namespace
80 
81 // Defines symbolic names for AArch64 registers. This defines a mapping from
82 // register name to register number.
83 //
84 #define GET_REGINFO_ENUM
85 #include "AArch64GenRegisterInfo.inc"
86 
87 // Defines symbolic names for the AArch64 instructions.
88 //
89 #define GET_INSTRINFO_ENUM
90 #include "AArch64GenInstrInfo.inc"
91 
92 #define GET_SUBTARGETINFO_ENUM
93 #include "AArch64GenSubtargetInfo.inc"
94 
95 #endif
Target & getTheAArch64beTarget()
std::unique_ptr< MCObjectWriter > createAArch64ELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI, bool IsLittleEndian, bool IsILP32)
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
Target & getTheAArch64leTarget()
Target & getTheARM64Target()
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
unsigned const MachineRegisterInfo * MRI
MCTargetStreamer * createAArch64ObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
MCCodeEmitter * createAArch64MCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx)
std::unique_ptr< MCObjectWriter > createAArch64WinCOFFObjectWriter(raw_pwrite_stream &OS)
void initLLVMToCVRegMapping(MCRegisterInfo *MRI)
std::unique_ptr< MCObjectWriter > createAArch64MachObjectWriter(raw_pwrite_stream &OS, uint32_t CPUType, uint32_t CPUSubtype)
MCTargetStreamer * createAArch64AsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS, MCInstPrinter *InstPrint, bool isVerboseAsm)
MCAsmBackend * createAArch64leAsmBackend(const Target &T, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU, const MCTargetOptions &Options)
MCAsmBackend * createAArch64beAsmBackend(const Target &T, const MCRegisterInfo &MRI, const Triple &TT, StringRef CPU, const MCTargetOptions &Options)