LLVM  6.0.0svn
AArch64StorePairSuppress.cpp
Go to the documentation of this file.
1 //===--- AArch64StorePairSuppress.cpp --- Suppress store pair formation ---===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This pass identifies floating point stores that should not be combined into
11 // store pairs. Later we may do the same for floating point loads.
12 // ===---------------------------------------------------------------------===//
13 
14 #include "AArch64InstrInfo.h"
21 #include "llvm/Support/Debug.h"
23 
24 using namespace llvm;
25 
26 #define DEBUG_TYPE "aarch64-stp-suppress"
27 
28 #define STPSUPPRESS_PASS_NAME "AArch64 Store Pair Suppression"
29 
30 namespace {
31 class AArch64StorePairSuppress : public MachineFunctionPass {
32  const AArch64InstrInfo *TII;
33  const TargetRegisterInfo *TRI;
34  const MachineRegisterInfo *MRI;
35  TargetSchedModel SchedModel;
36  MachineTraceMetrics *Traces;
38 
39 public:
40  static char ID;
41  AArch64StorePairSuppress() : MachineFunctionPass(ID) {
43  }
44 
45  StringRef getPassName() const override { return STPSUPPRESS_PASS_NAME; }
46 
47  bool runOnMachineFunction(MachineFunction &F) override;
48 
49 private:
50  bool shouldAddSTPToBlock(const MachineBasicBlock *BB);
51 
52  bool isNarrowFPStore(const MachineInstr &MI);
53 
54  void getAnalysisUsage(AnalysisUsage &AU) const override {
55  AU.setPreservesCFG();
59  }
60 };
62 } // anonymous
63 
64 INITIALIZE_PASS(AArch64StorePairSuppress, "aarch64-stp-suppress",
65  STPSUPPRESS_PASS_NAME, false, false)
66 
68  return new AArch64StorePairSuppress();
69 }
70 
71 /// Return true if an STP can be added to this block without increasing the
72 /// critical resource height. STP is good to form in Ld/St limited blocks and
73 /// bad to form in float-point limited blocks. This is true independent of the
74 /// critical path. If the critical path is longer than the resource height, the
75 /// extra vector ops can limit physreg renaming. Otherwise, it could simply
76 /// oversaturate the vector units.
77 bool AArch64StorePairSuppress::shouldAddSTPToBlock(const MachineBasicBlock *BB) {
78  if (!MinInstr)
79  MinInstr = Traces->getEnsemble(MachineTraceMetrics::TS_MinInstrCount);
80 
81  MachineTraceMetrics::Trace BBTrace = MinInstr->getTrace(BB);
82  unsigned ResLength = BBTrace.getResourceLength();
83 
84  // Get the machine model's scheduling class for STPQi.
85  // Bypass TargetSchedule's SchedClass resolution since we only have an opcode.
86  unsigned SCIdx = TII->get(AArch64::STPDi).getSchedClass();
87  const MCSchedClassDesc *SCDesc =
88  SchedModel.getMCSchedModel()->getSchedClassDesc(SCIdx);
89 
90  // If a subtarget does not define resources for STPQi, bail here.
91  if (SCDesc->isValid() && !SCDesc->isVariant()) {
92  unsigned ResLenWithSTP = BBTrace.getResourceLength(None, SCDesc);
93  if (ResLenWithSTP > ResLength) {
94  DEBUG(dbgs() << " Suppress STP in BB: " << BB->getNumber()
95  << " resources " << ResLength << " -> " << ResLenWithSTP
96  << "\n");
97  return false;
98  }
99  }
100  return true;
101 }
102 
103 /// Return true if this is a floating-point store smaller than the V reg. On
104 /// cyclone, these require a vector shuffle before storing a pair.
105 /// Ideally we would call getMatchingPairOpcode() and have the machine model
106 /// tell us if it's profitable with no cpu knowledge here.
107 ///
108 /// FIXME: We plan to develop a decent Target abstraction for simple loads and
109 /// stores. Until then use a nasty switch similar to AArch64LoadStoreOptimizer.
110 bool AArch64StorePairSuppress::isNarrowFPStore(const MachineInstr &MI) {
111  switch (MI.getOpcode()) {
112  default:
113  return false;
114  case AArch64::STRSui:
115  case AArch64::STRDui:
116  case AArch64::STURSi:
117  case AArch64::STURDi:
118  return true;
119  }
120 }
121 
122 bool AArch64StorePairSuppress::runOnMachineFunction(MachineFunction &MF) {
123  if (skipFunction(*MF.getFunction()))
124  return false;
125 
126  const TargetSubtargetInfo &ST = MF.getSubtarget();
127  TII = static_cast<const AArch64InstrInfo *>(ST.getInstrInfo());
128  TRI = ST.getRegisterInfo();
129  MRI = &MF.getRegInfo();
130  SchedModel.init(ST.getSchedModel(), &ST, TII);
131  Traces = &getAnalysis<MachineTraceMetrics>();
132  MinInstr = nullptr;
133 
134  DEBUG(dbgs() << "*** " << getPassName() << ": " << MF.getName() << '\n');
135 
136  if (!SchedModel.hasInstrSchedModel()) {
137  DEBUG(dbgs() << " Skipping pass: no machine model present.\n");
138  return false;
139  }
140 
141  // Check for a sequence of stores to the same base address. We don't need to
142  // precisely determine whether a store pair can be formed. But we do want to
143  // filter out most situations where we can't form store pairs to avoid
144  // computing trace metrics in those cases.
145  for (auto &MBB : MF) {
146  bool SuppressSTP = false;
147  unsigned PrevBaseReg = 0;
148  for (auto &MI : MBB) {
149  if (!isNarrowFPStore(MI))
150  continue;
151  unsigned BaseReg;
152  int64_t Offset;
153  if (TII->getMemOpBaseRegImmOfs(MI, BaseReg, Offset, TRI)) {
154  if (PrevBaseReg == BaseReg) {
155  // If this block can take STPs, skip ahead to the next block.
156  if (!SuppressSTP && shouldAddSTPToBlock(MI.getParent()))
157  break;
158  // Otherwise, continue unpairing the stores in this block.
159  DEBUG(dbgs() << "Unpairing store " << MI << "\n");
160  SuppressSTP = true;
161  TII->suppressLdStPair(MI);
162  }
163  PrevBaseReg = BaseReg;
164  } else
165  PrevBaseReg = 0;
166  }
167  }
168  // This pass just sets some internal MachineMemOperand flags. It can't really
169  // invalidate anything.
170  return false;
171 }
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
A trace ensemble is a collection of traces selected using the same strategy, for example &#39;minimum res...
F(f)
AnalysisUsage & addRequired()
MachineFunctionPass - This class adapts the FunctionPass interface to allow convenient creation of pa...
Provide an instruction scheduling machine model to CodeGen passes.
const HexagonInstrInfo * TII
unsigned getOpcode() const
Returns the opcode of this MachineInstr.
Definition: MachineInstr.h:290
Select the trace through a block that has the fewest instructions.
#define STPSUPPRESS_PASS_NAME
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they&#39;re not in a MachineFuncti...
virtual const TargetInstrInfo * getInstrInfo() const
bool isValid() const
Definition: MCSchedule.h:118
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
INITIALIZE_PASS(AArch64StorePairSuppress, "aarch64-stp-suppress", STPSUPPRESS_PASS_NAME, false, false) FunctionPass *llvm
unsigned const MachineRegisterInfo * MRI
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
void getAnalysisUsage(AnalysisUsage &AU) const override
getAnalysisUsage - Subclasses that override getAnalysisUsage must call this.
Summarize the scheduling resources required for an instruction of a particular scheduling class...
Definition: MCSchedule.h:101
Represent the analysis usage information of a pass.
FunctionPass class - This class is used to implement most global optimizations.
Definition: Pass.h:285
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
A trace represents a plausible sequence of executed basic blocks that passes through the current basi...
void setPreservesCFG()
This function should be called by the pass, iff they do not:
Definition: Pass.cpp:285
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
Definition: Debug.cpp:132
bool isVariant() const
Definition: MCSchedule.h:121
const MachineBasicBlock * getParent() const
Definition: MachineInstr.h:139
MachineRegisterInfo - Keep track of information for virtual and physical registers, including vreg register classes, use/def chains for registers, etc.
TargetSubtargetInfo - Generic base class for all target subtargets.
Representation of each machine instruction.
Definition: MachineInstr.h:59
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
FunctionPass * createAArch64StorePairSuppressPass()
const Function * getFunction() const
getFunction - Return the LLVM function that this machine code represents
unsigned getResourceLength(ArrayRef< const MachineBasicBlock *> Extrablocks=None, ArrayRef< const MCSchedClassDesc *> ExtraInstrs=None, ArrayRef< const MCSchedClassDesc *> RemoveInstrs=None) const
Return the resource length of the trace.
#define DEBUG(X)
Definition: Debug.h:118
IRTranslator LLVM IR MI
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg, int64_t &Offset, const TargetRegisterInfo *TRI) const override
Get the base register and byte offset of a load/store instr.
const MCSchedModel & getSchedModel() const
Get the machine model for this subtarget&#39;s CPU.
void initializeAArch64StorePairSuppressPass(PassRegistry &)