LLVM  7.0.0svn
AArch64Subtarget.cpp
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1 //===-- AArch64Subtarget.cpp - AArch64 Subtarget Information ----*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the AArch64 specific subclass of TargetSubtarget.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "AArch64Subtarget.h"
15 
16 #include "AArch64.h"
17 #include "AArch64InstrInfo.h"
18 #include "AArch64PBQPRegAlloc.h"
19 #include "AArch64TargetMachine.h"
20 
21 #include "AArch64CallLowering.h"
22 #include "AArch64LegalizerInfo.h"
26 #include "llvm/IR/GlobalValue.h"
28 
29 using namespace llvm;
30 
31 #define DEBUG_TYPE "aarch64-subtarget"
32 
33 #define GET_SUBTARGETINFO_CTOR
34 #define GET_SUBTARGETINFO_TARGET_DESC
35 #include "AArch64GenSubtargetInfo.inc"
36 
37 static cl::opt<bool>
38 EnableEarlyIfConvert("aarch64-early-ifcvt", cl::desc("Enable the early if "
39  "converter pass"), cl::init(true), cl::Hidden);
40 
41 // If OS supports TBI, use this flag to enable it.
42 static cl::opt<bool>
43 UseAddressTopByteIgnored("aarch64-use-tbi", cl::desc("Assume that top byte of "
44  "an address is ignored"), cl::init(false), cl::Hidden);
45 
46 static cl::opt<bool>
47  UseNonLazyBind("aarch64-enable-nonlazybind",
48  cl::desc("Call nonlazybind functions via direct GOT load"),
49  cl::init(false), cl::Hidden);
50 
52 AArch64Subtarget::initializeSubtargetDependencies(StringRef FS,
53  StringRef CPUString) {
54  // Determine default and user-specified characteristics
55 
56  if (CPUString.empty())
57  CPUString = "generic";
58 
59  ParseSubtargetFeatures(CPUString, FS);
60  initializeProperties();
61 
62  return *this;
63 }
64 
65 void AArch64Subtarget::initializeProperties() {
66  // Initialize CPU specific properties. We should add a tablegen feature for
67  // this in the future so we can specify it together with the subtarget
68  // features.
69  switch (ARMProcFamily) {
70  case Cyclone:
71  CacheLineSize = 64;
72  PrefetchDistance = 280;
73  MinPrefetchStride = 2048;
75  break;
76  case CortexA57:
79  break;
80  case ExynosM1:
82  MaxJumpTableSize = 8;
85  break;
86  case ExynosM3:
88  MaxJumpTableSize = 20;
91  break;
92  case Falkor:
94  // FIXME: remove this to enable 64-bit SLP if performance looks good.
96  CacheLineSize = 128;
97  PrefetchDistance = 820;
98  MinPrefetchStride = 2048;
100  break;
101  case Saphira:
103  // FIXME: remove this to enable 64-bit SLP if performance looks good.
105  break;
106  case Kryo:
109  CacheLineSize = 128;
110  PrefetchDistance = 740;
111  MinPrefetchStride = 1024;
113  // FIXME: remove this to enable 64-bit SLP if performance looks good.
115  break;
116  case ThunderX2T99:
117  CacheLineSize = 64;
119  PrefLoopAlignment = 2;
121  PrefetchDistance = 128;
122  MinPrefetchStride = 1024;
124  // FIXME: remove this to enable 64-bit SLP if performance looks good.
126  break;
127  case ThunderX:
128  case ThunderXT88:
129  case ThunderXT81:
130  case ThunderXT83:
131  CacheLineSize = 128;
133  PrefLoopAlignment = 2;
134  // FIXME: remove this to enable 64-bit SLP if performance looks good.
136  break;
137  case CortexA35: break;
138  case CortexA53:
140  break;
141  case CortexA55: break;
142  case CortexA72:
143  case CortexA73:
144  case CortexA75:
146  break;
147  case Others: break;
148  }
149 }
150 
151 AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU,
152  const std::string &FS,
153  const TargetMachine &TM, bool LittleEndian)
154  : AArch64GenSubtargetInfo(TT, CPU, FS),
155  ReserveX18(AArch64::isX18ReservedByDefault(TT)), IsLittle(LittleEndian),
157  InstrInfo(initializeSubtargetDependencies(FS, CPU)), TSInfo(),
158  TLInfo(TM, *this) {
160  Legalizer.reset(new AArch64LegalizerInfo(*this));
161 
162  auto *RBI = new AArch64RegisterBankInfo(*getRegisterInfo());
163 
164  // FIXME: At this point, we can't rely on Subtarget having RBI.
165  // It's awkward to mix passing RBI and the Subtarget; should we pass
166  // TII/TRI as well?
168  *static_cast<const AArch64TargetMachine *>(&TM), *this, *RBI));
169 
170  RegBankInfo.reset(RBI);
171 }
172 
174  return CallLoweringInfo.get();
175 }
176 
178  return InstSelector.get();
179 }
180 
182  return Legalizer.get();
183 }
184 
186  return RegBankInfo.get();
187 }
188 
189 /// Find the target operand flags that describe how a global value should be
190 /// referenced for the current subtarget.
191 unsigned char
193  const TargetMachine &TM) const {
194  // MachO large model always goes via a GOT, simply to get a single 8-byte
195  // absolute relocation on all global addresses.
197  return AArch64II::MO_GOT;
198 
199  unsigned Flags = GV->hasDLLImportStorageClass() ? AArch64II::MO_DLLIMPORT
201 
202  if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
203  return AArch64II::MO_GOT | Flags;
204 
205  // The small code model's direct accesses use ADRP, which cannot
206  // necessarily produce the value 0 (if the code is above 4GB).
208  return AArch64II::MO_GOT | Flags;
209 
210  return Flags;
211 }
212 
214  const GlobalValue *GV, const TargetMachine &TM) const {
215  // MachO large model always goes via a GOT, because we don't have the
216  // relocations available to do anything else..
217  if (TM.getCodeModel() == CodeModel::Large && isTargetMachO() &&
218  !GV->hasInternalLinkage())
219  return AArch64II::MO_GOT;
220 
221  // NonLazyBind goes via GOT unless we know it's available locally.
222  auto *F = dyn_cast<Function>(GV);
223  if (UseNonLazyBind && F && F->hasFnAttribute(Attribute::NonLazyBind) &&
224  !TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
225  return AArch64II::MO_GOT;
226 
227  return AArch64II::MO_NO_FLAG;
228 }
229 
231  unsigned NumRegionInstrs) const {
232  // LNT run (at least on Cyclone) showed reasonably significant gains for
233  // bi-directional scheduling. 253.perlbmk.
234  Policy.OnlyTopDown = false;
235  Policy.OnlyBottomUp = false;
236  // Enabling or Disabling the latency heuristic is a close call: It seems to
237  // help nearly no benchmark on out-of-order architectures, on the other hand
238  // it regresses register pressure on a few benchmarking.
240 }
241 
243  return EnableEarlyIfConvert;
244 }
245 
248  return false;
249 
250  if (TargetTriple.isiOS()) {
251  unsigned Major, Minor, Micro;
252  TargetTriple.getiOSVersion(Major, Minor, Micro);
253  return Major >= 8;
254  }
255 
256  return false;
257 }
258 
259 std::unique_ptr<PBQPRAConstraint>
261  return balanceFPOps() ? llvm::make_unique<A57ChainingConstraint>() : nullptr;
262 }
263 
265  // We usually compute max call frame size after ISel. Do the computation now
266  // if the .mir file didn't specify it. Note that this will probably give you
267  // bogus values after PEI has eliminated the callframe setup/destroy pseudo
268  // instructions, specify explicitely if you need it to be correct.
269  MachineFrameInfo &MFI = MF.getFrameInfo();
270  if (!MFI.isMaxCallFrameSizeComputed())
271  MFI.computeMaxCallFrameSize(MF);
272 }
void getiOSVersion(unsigned &Major, unsigned &Minor, unsigned &Micro) const
getiOSVersion - Parse the version number as with getOSVersion.
Definition: Triple.cpp:1063
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
unsigned char ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const
ClassifyGlobalReference - Find the target operand flags that describe how a global value should be re...
const InstructionSelector * getInstructionSelector() const override
This class provides the information for the target register banks.
AArch64SelectionDAGInfo TSInfo
bool hasDLLImportStorageClass() const
Definition: GlobalValue.h:261
F(f)
bool hasExternalWeakLinkage() const
Definition: GlobalValue.h:436
const CallLowering * getCallLowering() const override
void mirFileLoaded(MachineFunction &MF) const override
void overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const override
This file declares the targeting of the RegisterBankInfo class for AArch64.
Holds all the information related to register banks.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
static cl::opt< bool > EnableEarlyIfConvert("aarch64-early-ifcvt", cl::desc("Enable the early if " "converter pass"), cl::init(true), cl::Hidden)
std::unique_ptr< InstructionSelector > InstSelector
MO_GOT - This flag indicates that a symbol operand represents the address of the GOT entry for the sy...
const AArch64RegisterInfo * getRegisterInfo() const override
This file declares the targeting of the Machinelegalizer class for AArch64.
LLVM_NODISCARD LLVM_ATTRIBUTE_ALWAYS_INLINE bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:133
bool isiOS() const
Is this an iOS triple.
Definition: Triple.h:449
bool supportsAddressTopByteIgnored() const
CPU has TBI (top byte of addresses is ignored during HW address translation) and OS enables it...
bool enableEarlyIfConversion() const override
const AArch64TargetLowering * getTargetLowering() const override
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:410
bool shouldAssumeDSOLocal(const Module &M, const GlobalValue *GV) const
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
bool isX18ReservedByDefault(const Triple &TT)
bool useSmallAddressing() const
bool hasInternalLinkage() const
Definition: GlobalValue.h:433
void computeMaxCallFrameSize(const MachineFunction &MF)
Computes the maximum size of a callframe and the AdjustsStack property.
std::unique_ptr< CallLowering > CallLoweringInfo
GlobalISel related APIs.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
AArch64InstrInfo InstrInfo
void ParseSubtargetFeatures(StringRef CPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
CodeModel::Model getCodeModel() const
Returns the code model.
std::unique_ptr< RegisterBankInfo > RegBankInfo
Provides the logic to select generic machine instructions.
Define a generic scheduling policy for targets that don&#39;t provide their own MachineSchedStrategy.
This class provides the information for the target register banks.
std::unique_ptr< PBQPRAConstraint > getCustomPBQPConstraints() const override
AArch64Subtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const TargetMachine &TM, bool LittleEndian)
This constructor initializes the data members to match that of the specified triple.
const LegalizerInfo * getLegalizerInfo() const override
static cl::opt< bool > UseNonLazyBind("aarch64-enable-nonlazybind", cl::desc("Call nonlazybind functions via direct GOT load"), cl::init(false), cl::Hidden)
MO_DLLIMPORT - On a symbol operand, this represents that the reference to the symbol is for an import...
AArch64FrameLowering FrameLowering
InstructionSelector * createAArch64InstructionSelector(const AArch64TargetMachine &, AArch64Subtarget &, AArch64RegisterBankInfo &)
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:323
This file describes how to lower LLVM calls to machine code calls.
Triple TargetTriple
TargetTriple - What processor and OS we&#39;re targeting.
ARMProcFamilyEnum ARMProcFamily
ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:565
const RegisterBankInfo * getRegBankInfo() const override
bool isMaxCallFrameSizeComputed() const
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:59
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
AArch64TargetLowering TLInfo
unsigned char classifyGlobalFunctionReference(const GlobalValue *GV, const TargetMachine &TM) const
static cl::opt< bool > UseAddressTopByteIgnored("aarch64-use-tbi", cl::desc("Assume that top byte of " "an address is ignored"), cl::init(false), cl::Hidden)