LLVM  9.0.0svn
AArch64Subtarget.cpp
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1 //===-- AArch64Subtarget.cpp - AArch64 Subtarget Information ----*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the AArch64 specific subclass of TargetSubtarget.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "AArch64Subtarget.h"
14 
15 #include "AArch64.h"
16 #include "AArch64CallLowering.h"
17 #include "AArch64InstrInfo.h"
18 #include "AArch64LegalizerInfo.h"
19 #include "AArch64PBQPRegAlloc.h"
21 #include "AArch64TargetMachine.h"
25 #include "llvm/IR/GlobalValue.h"
27 
28 using namespace llvm;
29 
30 #define DEBUG_TYPE "aarch64-subtarget"
31 
32 #define GET_SUBTARGETINFO_CTOR
33 #define GET_SUBTARGETINFO_TARGET_DESC
34 #include "AArch64GenSubtargetInfo.inc"
35 
36 static cl::opt<bool>
37 EnableEarlyIfConvert("aarch64-early-ifcvt", cl::desc("Enable the early if "
38  "converter pass"), cl::init(true), cl::Hidden);
39 
40 // If OS supports TBI, use this flag to enable it.
41 static cl::opt<bool>
42 UseAddressTopByteIgnored("aarch64-use-tbi", cl::desc("Assume that top byte of "
43  "an address is ignored"), cl::init(false), cl::Hidden);
44 
45 static cl::opt<bool>
46  UseNonLazyBind("aarch64-enable-nonlazybind",
47  cl::desc("Call nonlazybind functions via direct GOT load"),
48  cl::init(false), cl::Hidden);
49 
51 AArch64Subtarget::initializeSubtargetDependencies(StringRef FS,
52  StringRef CPUString) {
53  // Determine default and user-specified characteristics
54 
55  if (CPUString.empty())
56  CPUString = "generic";
57 
58  ParseSubtargetFeatures(CPUString, FS);
59  initializeProperties();
60 
61  return *this;
62 }
63 
64 void AArch64Subtarget::initializeProperties() {
65  // Initialize CPU specific properties. We should add a tablegen feature for
66  // this in the future so we can specify it together with the subtarget
67  // features.
68  switch (ARMProcFamily) {
69  case Others:
70  break;
71  case CortexA35:
72  break;
73  case CortexA53:
75  break;
76  case CortexA55:
77  break;
78  case CortexA57:
81  break;
82  case CortexA72:
83  case CortexA73:
84  case CortexA75:
86  break;
87  case Cyclone:
88  CacheLineSize = 64;
89  PrefetchDistance = 280;
90  MinPrefetchStride = 2048;
92  break;
93  case ExynosM1:
95  MaxJumpTableSize = 8;
98  break;
99  case ExynosM3:
101  MaxJumpTableSize = 20;
103  PrefLoopAlignment = 4;
104  break;
105  case Falkor:
107  // FIXME: remove this to enable 64-bit SLP if performance looks good.
109  CacheLineSize = 128;
110  PrefetchDistance = 820;
111  MinPrefetchStride = 2048;
113  break;
114  case Kryo:
117  CacheLineSize = 128;
118  PrefetchDistance = 740;
119  MinPrefetchStride = 1024;
121  // FIXME: remove this to enable 64-bit SLP if performance looks good.
123  break;
124  case Saphira:
126  // FIXME: remove this to enable 64-bit SLP if performance looks good.
128  break;
129  case ThunderX2T99:
130  CacheLineSize = 64;
132  PrefLoopAlignment = 2;
134  PrefetchDistance = 128;
135  MinPrefetchStride = 1024;
137  // FIXME: remove this to enable 64-bit SLP if performance looks good.
139  break;
140  case ThunderX:
141  case ThunderXT88:
142  case ThunderXT81:
143  case ThunderXT83:
144  CacheLineSize = 128;
146  PrefLoopAlignment = 2;
147  // FIXME: remove this to enable 64-bit SLP if performance looks good.
149  break;
150  case TSV110:
151  CacheLineSize = 64;
153  PrefLoopAlignment = 2;
154  break;
155  }
156 }
157 
158 AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU,
159  const std::string &FS,
160  const TargetMachine &TM, bool LittleEndian)
161  : AArch64GenSubtargetInfo(TT, CPU, FS),
162  ReserveXRegister(AArch64::GPR64commonRegClass.getNumRegs()),
163  CustomCallSavedXRegs(AArch64::GPR64commonRegClass.getNumRegs()),
164  IsLittle(LittleEndian),
166  InstrInfo(initializeSubtargetDependencies(FS, CPU)), TSInfo(),
167  TLInfo(TM, *this) {
169  ReserveXRegister.set(18);
170 
172  Legalizer.reset(new AArch64LegalizerInfo(*this));
173 
174  auto *RBI = new AArch64RegisterBankInfo(*getRegisterInfo());
175 
176  // FIXME: At this point, we can't rely on Subtarget having RBI.
177  // It's awkward to mix passing RBI and the Subtarget; should we pass
178  // TII/TRI as well?
180  *static_cast<const AArch64TargetMachine *>(&TM), *this, *RBI));
181 
182  RegBankInfo.reset(RBI);
183 }
184 
186  return CallLoweringInfo.get();
187 }
188 
190  return InstSelector.get();
191 }
192 
194  return Legalizer.get();
195 }
196 
198  return RegBankInfo.get();
199 }
200 
201 /// Find the target operand flags that describe how a global value should be
202 /// referenced for the current subtarget.
203 unsigned char
205  const TargetMachine &TM) const {
206  // MachO large model always goes via a GOT, simply to get a single 8-byte
207  // absolute relocation on all global addresses.
209  return AArch64II::MO_GOT;
210 
211  if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV)) {
212  if (GV->hasDLLImportStorageClass())
216  return AArch64II::MO_GOT;
217  }
218 
219  // The small code model's direct accesses use ADRP, which cannot
220  // necessarily produce the value 0 (if the code is above 4GB).
221  // Same for the tiny code model, where we have a pc relative LDR.
222  if ((useSmallAddressing() || TM.getCodeModel() == CodeModel::Tiny) &&
224  return AArch64II::MO_GOT;
225 
226  return AArch64II::MO_NO_FLAG;
227 }
228 
230  const GlobalValue *GV, const TargetMachine &TM) const {
231  // MachO large model always goes via a GOT, because we don't have the
232  // relocations available to do anything else..
233  if (TM.getCodeModel() == CodeModel::Large && isTargetMachO() &&
234  !GV->hasInternalLinkage())
235  return AArch64II::MO_GOT;
236 
237  // NonLazyBind goes via GOT unless we know it's available locally.
238  auto *F = dyn_cast<Function>(GV);
239  if (UseNonLazyBind && F && F->hasFnAttribute(Attribute::NonLazyBind) &&
240  !TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
241  return AArch64II::MO_GOT;
242 
243  return AArch64II::MO_NO_FLAG;
244 }
245 
247  unsigned NumRegionInstrs) const {
248  // LNT run (at least on Cyclone) showed reasonably significant gains for
249  // bi-directional scheduling. 253.perlbmk.
250  Policy.OnlyTopDown = false;
251  Policy.OnlyBottomUp = false;
252  // Enabling or Disabling the latency heuristic is a close call: It seems to
253  // help nearly no benchmark on out-of-order architectures, on the other hand
254  // it regresses register pressure on a few benchmarking.
256 }
257 
259  return EnableEarlyIfConvert;
260 }
261 
264  return false;
265 
266  if (TargetTriple.isiOS()) {
267  unsigned Major, Minor, Micro;
268  TargetTriple.getiOSVersion(Major, Minor, Micro);
269  return Major >= 8;
270  }
271 
272  return false;
273 }
274 
275 std::unique_ptr<PBQPRAConstraint>
277  return balanceFPOps() ? llvm::make_unique<A57ChainingConstraint>() : nullptr;
278 }
279 
281  // We usually compute max call frame size after ISel. Do the computation now
282  // if the .mir file didn't specify it. Note that this will probably give you
283  // bogus values after PEI has eliminated the callframe setup/destroy pseudo
284  // instructions, specify explicitly if you need it to be correct.
285  MachineFrameInfo &MFI = MF.getFrameInfo();
286  if (!MFI.isMaxCallFrameSizeComputed())
287  MFI.computeMaxCallFrameSize(MF);
288 }
const Triple & getTargetTriple() const
void getiOSVersion(unsigned &Major, unsigned &Minor, unsigned &Micro) const
getiOSVersion - Parse the version number as with getOSVersion.
Definition: Triple.cpp:1091
BitVector & set()
Definition: BitVector.h:397
This class represents lattice values for constants.
Definition: AllocatorList.h:23
unsigned char ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const
ClassifyGlobalReference - Find the target operand flags that describe how a global value should be re...
const InstructionSelector * getInstructionSelector() const override
This class provides the information for the target register banks.
AArch64SelectionDAGInfo TSInfo
bool hasDLLImportStorageClass() const
Definition: GlobalValue.h:261
F(f)
bool hasExternalWeakLinkage() const
Definition: GlobalValue.h:436
const CallLowering * getCallLowering() const override
void mirFileLoaded(MachineFunction &MF) const override
void overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const override
This file declares the targeting of the RegisterBankInfo class for AArch64.
Holds all the information related to register banks.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted...
LLVM_NODISCARD bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:126
static cl::opt< bool > EnableEarlyIfConvert("aarch64-early-ifcvt", cl::desc("Enable the early if " "converter pass"), cl::init(true), cl::Hidden)
std::unique_ptr< InstructionSelector > InstSelector
MO_GOT - This flag indicates that a symbol operand represents the address of the GOT entry for the sy...
const AArch64RegisterInfo * getRegisterInfo() const override
This file declares the targeting of the Machinelegalizer class for AArch64.
bool isiOS() const
Is this an iOS triple.
Definition: Triple.h:455
bool supportsAddressTopByteIgnored() const
CPU has TBI (top byte of addresses is ignored during HW address translation) and OS enables it...
bool enableEarlyIfConversion() const override
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:527
const AArch64TargetLowering * getTargetLowering() const override
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:422
bool shouldAssumeDSOLocal(const Module &M, const GlobalValue *GV) const
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
bool isX18ReservedByDefault(const Triple &TT)
bool useSmallAddressing() const
bool hasInternalLinkage() const
Definition: GlobalValue.h:433
void computeMaxCallFrameSize(const MachineFunction &MF)
Computes the maximum size of a callframe and the AdjustsStack property.
std::unique_ptr< CallLowering > CallLoweringInfo
GlobalISel related APIs.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
AArch64InstrInfo InstrInfo
void ParseSubtargetFeatures(StringRef CPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
CodeModel::Model getCodeModel() const
Returns the code model.
std::unique_ptr< RegisterBankInfo > RegBankInfo
Provides the logic to select generic machine instructions.
Define a generic scheduling policy for targets that don&#39;t provide their own MachineSchedStrategy.
This class provides the information for the target register banks.
std::unique_ptr< PBQPRAConstraint > getCustomPBQPConstraints() const override
AArch64Subtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const TargetMachine &TM, bool LittleEndian)
This constructor initializes the data members to match that of the specified triple.
const LegalizerInfo * getLegalizerInfo() const override
static cl::opt< bool > UseNonLazyBind("aarch64-enable-nonlazybind", cl::desc("Call nonlazybind functions via direct GOT load"), cl::init(false), cl::Hidden)
MO_COFFSTUB - On a symbol operand "FOO", this indicates that the reference is actually to the "...
MO_DLLIMPORT - On a symbol operand, this represents that the reference to the symbol is for an import...
AArch64FrameLowering FrameLowering
InstructionSelector * createAArch64InstructionSelector(const AArch64TargetMachine &, AArch64Subtarget &, AArch64RegisterBankInfo &)
LLVM_NODISCARD std::enable_if<!is_simple_type< Y >::value, typename cast_retty< X, const Y >::ret_type >::type dyn_cast(const Y &Val)
Definition: Casting.h:322
This file describes how to lower LLVM calls to machine code calls.
Triple TargetTriple
TargetTriple - What processor and OS we&#39;re targeting.
ARMProcFamilyEnum ARMProcFamily
ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
Module * getParent()
Get the module that this global value is contained inside of...
Definition: GlobalValue.h:565
const RegisterBankInfo * getRegBankInfo() const override
bool isMaxCallFrameSizeComputed() const
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:58
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
AArch64TargetLowering TLInfo
unsigned char classifyGlobalFunctionReference(const GlobalValue *GV, const TargetMachine &TM) const
static cl::opt< bool > UseAddressTopByteIgnored("aarch64-use-tbi", cl::desc("Assume that top byte of " "an address is ignored"), cl::init(false), cl::Hidden)