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AArch64Subtarget.h
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1 //===--- AArch64Subtarget.h - Define Subtarget for the AArch64 -*- C++ -*--===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file declares the AArch64 specific subclass of TargetSubtarget.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
15 #define LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
16 
17 #include "AArch64FrameLowering.h"
18 #include "AArch64ISelLowering.h"
19 #include "AArch64InstrInfo.h"
20 #include "AArch64RegisterInfo.h"
27 #include "llvm/IR/DataLayout.h"
28 #include <string>
29 
30 #define GET_SUBTARGETINFO_HEADER
31 #include "AArch64GenSubtargetInfo.inc"
32 
33 namespace llvm {
34 class GlobalValue;
35 class StringRef;
36 class Triple;
37 
39 public:
40  enum ARMProcFamilyEnum : uint8_t {
59  };
60 
61 protected:
62  /// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
64 
65  bool HasV8_1aOps = false;
66  bool HasV8_2aOps = false;
67  bool HasV8_3aOps = false;
68 
69  bool HasFPARMv8 = false;
70  bool HasNEON = false;
71  bool HasCrypto = false;
72  bool HasDotProd = false;
73  bool HasCRC = false;
74  bool HasLSE = false;
75  bool HasRAS = false;
76  bool HasRDM = false;
77  bool HasPerfMon = false;
78  bool HasFullFP16 = false;
79  bool HasSPE = false;
80  bool HasLSLFast = false;
81  bool HasSVE = false;
82  bool HasRCPC = false;
83 
84  // HasZeroCycleRegMove - Has zero-cycle register mov instructions.
85  bool HasZeroCycleRegMove = false;
86 
87  // HasZeroCycleZeroing - Has zero-cycle zeroing instructions.
88  bool HasZeroCycleZeroing = false;
90 
91  // StrictAlign - Disallow unaligned memory accesses.
92  bool StrictAlign = false;
93 
94  // NegativeImmediates - transform instructions with negative immediates
95  bool NegativeImmediates = true;
96 
97  // Enable 64-bit vectorization in SLP.
99 
100  bool UseAA = false;
102  bool BalanceFPOps = false;
103  bool CustomAsCheapAsMove = false;
104  bool UsePostRAScheduler = false;
106  bool Paired128IsSlow = false;
107  bool STRQroIsSlow = false;
111  bool HasFuseAES = false;
112  bool HasFuseLiterals = false;
114  bool UseRSqrt = false;
115  uint8_t MaxInterleaveFactor = 2;
117  uint16_t CacheLineSize = 0;
118  uint16_t PrefetchDistance = 0;
119  uint16_t MinPrefetchStride = 1;
120  unsigned MaxPrefetchIterationsAhead = UINT_MAX;
121  unsigned PrefFunctionAlignment = 0;
122  unsigned PrefLoopAlignment = 0;
123  unsigned MaxJumpTableSize = 0;
124  unsigned WideningBaseCost = 0;
125 
126  // ReserveX18 - X18 is not available as a general purpose register.
128 
129  bool IsLittle;
130 
131  /// TargetTriple - What processor and OS we're targeting.
133 
138 
139  /// GlobalISel related APIs.
140  std::unique_ptr<CallLowering> CallLoweringInfo;
141  std::unique_ptr<InstructionSelector> InstSelector;
142  std::unique_ptr<LegalizerInfo> Legalizer;
143  std::unique_ptr<RegisterBankInfo> RegBankInfo;
144 
145 private:
146  /// initializeSubtargetDependencies - Initializes using CPUString and the
147  /// passed in feature string so that we can use initializer lists for
148  /// subtarget initialization.
149  AArch64Subtarget &initializeSubtargetDependencies(StringRef FS,
150  StringRef CPUString);
151 
152  /// Initialize properties based on the selected processor family.
153  void initializeProperties();
154 
155 public:
156  /// This constructor initializes the data members to match that
157  /// of the specified triple.
158  AArch64Subtarget(const Triple &TT, const std::string &CPU,
159  const std::string &FS, const TargetMachine &TM,
160  bool LittleEndian);
161 
163  return &TSInfo;
164  }
165  const AArch64FrameLowering *getFrameLowering() const override {
166  return &FrameLowering;
167  }
168  const AArch64TargetLowering *getTargetLowering() const override {
169  return &TLInfo;
170  }
171  const AArch64InstrInfo *getInstrInfo() const override { return &InstrInfo; }
172  const AArch64RegisterInfo *getRegisterInfo() const override {
173  return &getInstrInfo()->getRegisterInfo();
174  }
175  const CallLowering *getCallLowering() const override;
176  const InstructionSelector *getInstructionSelector() const override;
177  const LegalizerInfo *getLegalizerInfo() const override;
178  const RegisterBankInfo *getRegBankInfo() const override;
179  const Triple &getTargetTriple() const { return TargetTriple; }
180  bool enableMachineScheduler() const override { return true; }
181  bool enablePostRAScheduler() const override {
182  return UsePostRAScheduler;
183  }
184 
185  /// Returns ARM processor family.
186  /// Avoid this function! CPU specifics should be kept local to this class
187  /// and preferably modeled with SubtargetFeatures or properties in
188  /// initializeProperties().
190  return ARMProcFamily;
191  }
192 
193  bool hasV8_1aOps() const { return HasV8_1aOps; }
194  bool hasV8_2aOps() const { return HasV8_2aOps; }
195  bool hasV8_3aOps() const { return HasV8_3aOps; }
196 
197  bool hasZeroCycleRegMove() const { return HasZeroCycleRegMove; }
198 
199  bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; }
200 
203  }
204 
205  bool requiresStrictAlign() const { return StrictAlign; }
206 
207  bool isXRaySupported() const override { return true; }
208 
209  unsigned getMinVectorRegisterBitWidth() const {
211  }
212 
213  bool isX18Reserved() const { return ReserveX18; }
214  bool hasFPARMv8() const { return HasFPARMv8; }
215  bool hasNEON() const { return HasNEON; }
216  bool hasCrypto() const { return HasCrypto; }
217  bool hasDotProd() const { return HasDotProd; }
218  bool hasCRC() const { return HasCRC; }
219  bool hasLSE() const { return HasLSE; }
220  bool hasRAS() const { return HasRAS; }
221  bool hasRDM() const { return HasRDM; }
222  bool balanceFPOps() const { return BalanceFPOps; }
225  }
228  bool isPaired128Slow() const { return Paired128IsSlow; }
229  bool isSTRQroSlow() const { return STRQroIsSlow; }
232  }
235  bool hasFuseAES() const { return HasFuseAES; }
236  bool hasFuseLiterals() const { return HasFuseLiterals; }
237 
238  /// \brief Return true if the CPU supports any kind of instruction fusion.
239  bool hasFusion() const {
242  }
243 
244  bool useRSqrt() const { return UseRSqrt; }
245  unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
248  }
249  unsigned getCacheLineSize() const { return CacheLineSize; }
250  unsigned getPrefetchDistance() const { return PrefetchDistance; }
251  unsigned getMinPrefetchStride() const { return MinPrefetchStride; }
252  unsigned getMaxPrefetchIterationsAhead() const {
254  }
255  unsigned getPrefFunctionAlignment() const { return PrefFunctionAlignment; }
256  unsigned getPrefLoopAlignment() const { return PrefLoopAlignment; }
257 
258  unsigned getMaximumJumpTableSize() const { return MaxJumpTableSize; }
259 
260  unsigned getWideningBaseCost() const { return WideningBaseCost; }
261 
262  /// CPU has TBI (top byte of addresses is ignored during HW address
263  /// translation) and OS enables it.
264  bool supportsAddressTopByteIgnored() const;
265 
266  bool hasPerfMon() const { return HasPerfMon; }
267  bool hasFullFP16() const { return HasFullFP16; }
268  bool hasSPE() const { return HasSPE; }
269  bool hasLSLFast() const { return HasLSLFast; }
270  bool hasSVE() const { return HasSVE; }
271  bool hasRCPC() const { return HasRCPC; }
272 
273  bool isLittleEndian() const { return IsLittle; }
274 
275  bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
276  bool isTargetIOS() const { return TargetTriple.isiOS(); }
277  bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
278  bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
279  bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
280  bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
281 
282  bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
283  bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
284  bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
285 
286  bool useAA() const override { return UseAA; }
287 
288  bool useSmallAddressing() const {
289  switch (TLInfo.getTargetMachine().getCodeModel()) {
290  case CodeModel::Kernel:
291  // Kernel is currently allowed only for Fuchsia targets,
292  // where it is the same as Small for almost all purposes.
293  case CodeModel::Small:
294  return true;
295  default:
296  return false;
297  }
298  }
299 
300  /// ParseSubtargetFeatures - Parses features string setting specified
301  /// subtarget options. Definition of function is auto generated by tblgen.
303 
304  /// ClassifyGlobalReference - Find the target operand flags that describe
305  /// how a global value should be referenced for the current subtarget.
306  unsigned char ClassifyGlobalReference(const GlobalValue *GV,
307  const TargetMachine &TM) const;
308 
309  unsigned char classifyGlobalFunctionReference(const GlobalValue *GV,
310  const TargetMachine &TM) const;
311 
313  unsigned NumRegionInstrs) const override;
314 
315  bool enableEarlyIfConversion() const override;
316 
317  std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const override;
318 
320  switch (CC) {
321  case CallingConv::C:
322  return isTargetWindows();
323  case CallingConv::Win64:
324  return true;
325  default:
326  return false;
327  }
328  }
329 
330  void mirFileLoaded(MachineFunction &MF) const override;
331 };
332 } // End llvm namespace
333 
334 #endif
const Triple & getTargetTriple() const
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:470
bool isMisaligned128StoreSlow() const
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
The C convention as implemented on Windows/x86-64 and AArch64.
Definition: CallingConv.h:154
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:588
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:35
bool predictableSelectIsExpensive() const
bool hasZeroCycleZeroing() const
unsigned char ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const
ClassifyGlobalReference - Find the target operand flags that describe how a global value should be re...
const InstructionSelector * getInstructionSelector() const override
AArch64SelectionDAGInfo TSInfo
const AArch64FrameLowering * getFrameLowering() const override
bool isOSFuchsia() const
Definition: Triple.h:490
const CallLowering * getCallLowering() const override
bool isCallingConvWin64(CallingConv::ID CC) const
bool hasCustomCheapAsMoveHandling() const
void mirFileLoaded(MachineFunction &MF) const override
void overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const override
unsigned getCacheLineSize() const
Holds all the information related to register banks.
bool hasFusion() const
Return true if the CPU supports any kind of instruction fusion.
bool hasArithmeticBccFusion() const
bool hasZeroCycleRegMove() const
std::unique_ptr< InstructionSelector > InstSelector
bool useAlternateSExtLoadCVTF32Pattern() const
const AArch64RegisterInfo * getRegisterInfo() const override
std::unique_ptr< LegalizerInfo > Legalizer
unsigned getPrefetchDistance() const
bool useAA() const override
bool isiOS() const
Is this an iOS triple.
Definition: Triple.h:451
unsigned getWideningBaseCost() const
bool enableMachineScheduler() const override
bool supportsAddressTopByteIgnored() const
CPU has TBI (top byte of addresses is ignored during HW address translation) and OS enables it...
bool enableEarlyIfConversion() const override
unsigned getMinVectorRegisterBitWidth() const
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:562
const AArch64TargetLowering * getTargetLowering() const override
const AArch64RegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
bool requiresStrictAlign() const
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
Definition: Triple.h:593
bool isXRaySupported() const override
unsigned getPrefFunctionAlignment() const
bool useSmallAddressing() const
std::unique_ptr< CallLowering > CallLoweringInfo
GlobalISel related APIs.
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:598
const TargetMachine & getTargetMachine() const
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
unsigned getMinPrefetchStride() const
const AArch64SelectionDAGInfo * getSelectionDAGInfo() const override
bool hasArithmeticCbzFusion() const
AArch64InstrInfo InstrInfo
unsigned getMaximumJumpTableSize() const
void ParseSubtargetFeatures(StringRef CPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
bool isOSLinux() const
Tests whether the OS is Linux.
Definition: Triple.h:572
bool enablePostRAScheduler() const override
CodeModel::Model getCodeModel() const
Returns the code model.
unsigned getMaxInterleaveFactor() const
std::unique_ptr< RegisterBankInfo > RegBankInfo
Provides the logic to select generic machine instructions.
Define a generic scheduling policy for targets that don&#39;t provide their own MachineSchedStrategy.
std::unique_ptr< PBQPRAConstraint > getCustomPBQPConstraints() const override
AArch64Subtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const TargetMachine &TM, bool LittleEndian)
This constructor initializes the data members to match that of the specified triple.
const LegalizerInfo * getLegalizerInfo() const override
AArch64FrameLowering FrameLowering
ARMProcFamilyEnum getProcFamily() const
Returns ARM processor family.
bool hasZeroCycleZeroingFPWorkaround() const
Triple TargetTriple
TargetTriple - What processor and OS we&#39;re targeting.
ARMProcFamilyEnum ARMProcFamily
ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
unsigned getMaxPrefetchIterationsAhead() const
const AArch64InstrInfo * getInstrInfo() const override
This file describes how to lower LLVM calls to machine code calls.
const RegisterBankInfo * getRegBankInfo() const override
bool isAndroid() const
Tests whether the target is Android.
Definition: Triple.h:621
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:59
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
AArch64TargetLowering TLInfo
unsigned char classifyGlobalFunctionReference(const GlobalValue *GV, const TargetMachine &TM) const
unsigned getPrefLoopAlignment() const
unsigned getVectorInsertExtractBaseCost() const