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AArch64Subtarget.h
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1 //===--- AArch64Subtarget.h - Define Subtarget for the AArch64 -*- C++ -*--===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file declares the AArch64 specific subclass of TargetSubtarget.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
15 #define LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
16 
17 #include "AArch64FrameLowering.h"
18 #include "AArch64ISelLowering.h"
19 #include "AArch64InstrInfo.h"
20 #include "AArch64RegisterInfo.h"
27 #include "llvm/IR/DataLayout.h"
28 #include <string>
29 
30 #define GET_SUBTARGETINFO_HEADER
31 #include "AArch64GenSubtargetInfo.inc"
32 
33 namespace llvm {
34 class GlobalValue;
35 class StringRef;
36 class Triple;
37 
39 public:
40  enum ARMProcFamilyEnum : uint8_t {
59  };
60 
61 protected:
62  /// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
64 
65  bool HasV8_1aOps = false;
66  bool HasV8_2aOps = false;
67  bool HasV8_3aOps = false;
68 
69  bool HasFPARMv8 = false;
70  bool HasNEON = false;
71  bool HasCrypto = false;
72  bool HasDotProd = false;
73  bool HasCRC = false;
74  bool HasLSE = false;
75  bool HasRAS = false;
76  bool HasRDM = false;
77  bool HasPerfMon = false;
78  bool HasFullFP16 = false;
79  bool HasSPE = false;
80  bool HasLSLFast = false;
81  bool HasSVE = false;
82  bool HasRCPC = false;
83 
84  // HasZeroCycleRegMove - Has zero-cycle register mov instructions.
85  bool HasZeroCycleRegMove = false;
86 
87  // HasZeroCycleZeroing - Has zero-cycle zeroing instructions.
88  bool HasZeroCycleZeroing = false;
89 
90  // StrictAlign - Disallow unaligned memory accesses.
91  bool StrictAlign = false;
92 
93  // NegativeImmediates - transform instructions with negative immediates
94  bool NegativeImmediates = true;
95 
96  // Enable 64-bit vectorization in SLP.
98 
99  bool UseAA = false;
101  bool BalanceFPOps = false;
102  bool CustomAsCheapAsMove = false;
103  bool UsePostRAScheduler = false;
105  bool Paired128IsSlow = false;
106  bool STRQroIsSlow = false;
110  bool HasFuseAES = false;
111  bool HasFuseLiterals = false;
113  bool UseRSqrt = false;
114  uint8_t MaxInterleaveFactor = 2;
116  uint16_t CacheLineSize = 0;
117  uint16_t PrefetchDistance = 0;
118  uint16_t MinPrefetchStride = 1;
119  unsigned MaxPrefetchIterationsAhead = UINT_MAX;
120  unsigned PrefFunctionAlignment = 0;
121  unsigned PrefLoopAlignment = 0;
122  unsigned MaxJumpTableSize = 0;
123  unsigned WideningBaseCost = 0;
124 
125  // ReserveX18 - X18 is not available as a general purpose register.
127 
128  bool IsLittle;
129 
130  /// TargetTriple - What processor and OS we're targeting.
132 
137 
138  /// GlobalISel related APIs.
139  std::unique_ptr<CallLowering> CallLoweringInfo;
140  std::unique_ptr<InstructionSelector> InstSelector;
141  std::unique_ptr<LegalizerInfo> Legalizer;
142  std::unique_ptr<RegisterBankInfo> RegBankInfo;
143 
144 private:
145  /// initializeSubtargetDependencies - Initializes using CPUString and the
146  /// passed in feature string so that we can use initializer lists for
147  /// subtarget initialization.
148  AArch64Subtarget &initializeSubtargetDependencies(StringRef FS,
149  StringRef CPUString);
150 
151  /// Initialize properties based on the selected processor family.
152  void initializeProperties();
153 
154 public:
155  /// This constructor initializes the data members to match that
156  /// of the specified triple.
157  AArch64Subtarget(const Triple &TT, const std::string &CPU,
158  const std::string &FS, const TargetMachine &TM,
159  bool LittleEndian);
160 
162  return &TSInfo;
163  }
164  const AArch64FrameLowering *getFrameLowering() const override {
165  return &FrameLowering;
166  }
167  const AArch64TargetLowering *getTargetLowering() const override {
168  return &TLInfo;
169  }
170  const AArch64InstrInfo *getInstrInfo() const override { return &InstrInfo; }
171  const AArch64RegisterInfo *getRegisterInfo() const override {
172  return &getInstrInfo()->getRegisterInfo();
173  }
174  const CallLowering *getCallLowering() const override;
175  const InstructionSelector *getInstructionSelector() const override;
176  const LegalizerInfo *getLegalizerInfo() const override;
177  const RegisterBankInfo *getRegBankInfo() const override;
178  const Triple &getTargetTriple() const { return TargetTriple; }
179  bool enableMachineScheduler() const override { return true; }
180  bool enablePostRAScheduler() const override {
181  return UsePostRAScheduler;
182  }
183 
184  /// Returns ARM processor family.
185  /// Avoid this function! CPU specifics should be kept local to this class
186  /// and preferably modeled with SubtargetFeatures or properties in
187  /// initializeProperties().
189  return ARMProcFamily;
190  }
191 
192  bool hasV8_1aOps() const { return HasV8_1aOps; }
193  bool hasV8_2aOps() const { return HasV8_2aOps; }
194  bool hasV8_3aOps() const { return HasV8_3aOps; }
195 
196  bool hasZeroCycleRegMove() const { return HasZeroCycleRegMove; }
197 
198  bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; }
199 
200  bool requiresStrictAlign() const { return StrictAlign; }
201 
202  bool isXRaySupported() const override { return true; }
203 
204  unsigned getMinVectorRegisterBitWidth() const {
206  }
207 
208  bool isX18Reserved() const { return ReserveX18; }
209  bool hasFPARMv8() const { return HasFPARMv8; }
210  bool hasNEON() const { return HasNEON; }
211  bool hasCrypto() const { return HasCrypto; }
212  bool hasDotProd() const { return HasDotProd; }
213  bool hasCRC() const { return HasCRC; }
214  bool hasLSE() const { return HasLSE; }
215  bool hasRAS() const { return HasRAS; }
216  bool hasRDM() const { return HasRDM; }
217  bool balanceFPOps() const { return BalanceFPOps; }
220  }
223  bool isPaired128Slow() const { return Paired128IsSlow; }
224  bool isSTRQroSlow() const { return STRQroIsSlow; }
227  }
230  bool hasFuseAES() const { return HasFuseAES; }
231  bool hasFuseLiterals() const { return HasFuseLiterals; }
232 
233  /// \brief Return true if the CPU supports any kind of instruction fusion.
234  bool hasFusion() const {
237  }
238 
239  bool useRSqrt() const { return UseRSqrt; }
240  unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
243  }
244  unsigned getCacheLineSize() const { return CacheLineSize; }
245  unsigned getPrefetchDistance() const { return PrefetchDistance; }
246  unsigned getMinPrefetchStride() const { return MinPrefetchStride; }
247  unsigned getMaxPrefetchIterationsAhead() const {
249  }
250  unsigned getPrefFunctionAlignment() const { return PrefFunctionAlignment; }
251  unsigned getPrefLoopAlignment() const { return PrefLoopAlignment; }
252 
253  unsigned getMaximumJumpTableSize() const { return MaxJumpTableSize; }
254 
255  unsigned getWideningBaseCost() const { return WideningBaseCost; }
256 
257  /// CPU has TBI (top byte of addresses is ignored during HW address
258  /// translation) and OS enables it.
259  bool supportsAddressTopByteIgnored() const;
260 
261  bool hasPerfMon() const { return HasPerfMon; }
262  bool hasFullFP16() const { return HasFullFP16; }
263  bool hasSPE() const { return HasSPE; }
264  bool hasLSLFast() const { return HasLSLFast; }
265  bool hasSVE() const { return HasSVE; }
266  bool hasRCPC() const { return HasRCPC; }
267 
268  bool isLittleEndian() const { return IsLittle; }
269 
270  bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
271  bool isTargetIOS() const { return TargetTriple.isiOS(); }
272  bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
273  bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
274  bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
275  bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
276 
277  bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
278  bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
279  bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
280 
281  bool useAA() const override { return UseAA; }
282 
283  bool useSmallAddressing() const {
284  switch (TLInfo.getTargetMachine().getCodeModel()) {
285  case CodeModel::Kernel:
286  // Kernel is currently allowed only for Fuchsia targets,
287  // where it is the same as Small for almost all purposes.
288  case CodeModel::Small:
289  return true;
290  default:
291  return false;
292  }
293  }
294 
295  /// ParseSubtargetFeatures - Parses features string setting specified
296  /// subtarget options. Definition of function is auto generated by tblgen.
298 
299  /// ClassifyGlobalReference - Find the target operand flags that describe
300  /// how a global value should be referenced for the current subtarget.
301  unsigned char ClassifyGlobalReference(const GlobalValue *GV,
302  const TargetMachine &TM) const;
303 
304  unsigned char classifyGlobalFunctionReference(const GlobalValue *GV,
305  const TargetMachine &TM) const;
306 
307  /// This function returns the name of a function which has an interface
308  /// like the non-standard bzero function, if such a function exists on
309  /// the current subtarget and it is considered prefereable over
310  /// memset with zero passed as the second argument. Otherwise it
311  /// returns null.
312  const char *getBZeroEntry() const;
313 
315  unsigned NumRegionInstrs) const override;
316 
317  bool enableEarlyIfConversion() const override;
318 
319  std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const override;
320 
322  switch (CC) {
323  case CallingConv::C:
324  return isTargetWindows();
325  case CallingConv::Win64:
326  return true;
327  default:
328  return false;
329  }
330  }
331 };
332 } // End llvm namespace
333 
334 #endif
const Triple & getTargetTriple() const
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:470
bool isMisaligned128StoreSlow() const
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:588
bool predictableSelectIsExpensive() const
bool hasZeroCycleZeroing() const
unsigned char ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const
ClassifyGlobalReference - Find the target operand flags that describe how a global value should be re...
const InstructionSelector * getInstructionSelector() const override
AArch64SelectionDAGInfo TSInfo
const AArch64FrameLowering * getFrameLowering() const override
bool isOSFuchsia() const
Definition: Triple.h:490
const CallLowering * getCallLowering() const override
bool isCallingConvWin64(CallingConv::ID CC) const
bool hasCustomCheapAsMoveHandling() const
void overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const override
unsigned getCacheLineSize() const
Holds all the information related to register banks.
bool hasFusion() const
Return true if the CPU supports any kind of instruction fusion.
bool hasArithmeticBccFusion() const
bool hasZeroCycleRegMove() const
std::unique_ptr< InstructionSelector > InstSelector
bool useAlternateSExtLoadCVTF32Pattern() const
const AArch64RegisterInfo * getRegisterInfo() const override
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:35
std::unique_ptr< LegalizerInfo > Legalizer
unsigned getPrefetchDistance() const
bool useAA() const override
bool isiOS() const
Is this an iOS triple.
Definition: Triple.h:451
unsigned getWideningBaseCost() const
bool enableMachineScheduler() const override
bool supportsAddressTopByteIgnored() const
CPU has TBI (top byte of addresses is ignored during HW address translation) and OS enables it...
bool enableEarlyIfConversion() const override
unsigned getMinVectorRegisterBitWidth() const
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:562
const AArch64TargetLowering * getTargetLowering() const override
const AArch64RegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
bool requiresStrictAlign() const
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
Definition: Triple.h:593
bool isXRaySupported() const override
unsigned getPrefFunctionAlignment() const
bool useSmallAddressing() const
std::unique_ptr< CallLowering > CallLoweringInfo
GlobalISel related APIs.
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:598
const TargetMachine & getTargetMachine() const
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
unsigned getMinPrefetchStride() const
const AArch64SelectionDAGInfo * getSelectionDAGInfo() const override
bool hasArithmeticCbzFusion() const
AArch64InstrInfo InstrInfo
unsigned getMaximumJumpTableSize() const
void ParseSubtargetFeatures(StringRef CPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
bool isOSLinux() const
Tests whether the OS is Linux.
Definition: Triple.h:572
bool enablePostRAScheduler() const override
CodeModel::Model getCodeModel() const
Returns the code model.
unsigned getMaxInterleaveFactor() const
std::unique_ptr< RegisterBankInfo > RegBankInfo
const char * getBZeroEntry() const
This function returns the name of a function which has an interface like the non-standard bzero funct...
Provides the logic to select generic machine instructions.
Define a generic scheduling policy for targets that don&#39;t provide their own MachineSchedStrategy.
std::unique_ptr< PBQPRAConstraint > getCustomPBQPConstraints() const override
AArch64Subtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const TargetMachine &TM, bool LittleEndian)
This constructor initializes the data members to match that of the specified triple.
const LegalizerInfo * getLegalizerInfo() const override
AArch64FrameLowering FrameLowering
ARMProcFamilyEnum getProcFamily() const
Returns ARM processor family.
The C convention as implemented on Windows/x86-64 and AArch64.
Definition: CallingConv.h:154
Triple TargetTriple
TargetTriple - What processor and OS we&#39;re targeting.
ARMProcFamilyEnum ARMProcFamily
ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
unsigned getMaxPrefetchIterationsAhead() const
const AArch64InstrInfo * getInstrInfo() const override
This file describes how to lower LLVM calls to machine code calls.
const RegisterBankInfo * getRegBankInfo() const override
bool isAndroid() const
Tests whether the target is Android.
Definition: Triple.h:621
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:57
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
AArch64TargetLowering TLInfo
unsigned char classifyGlobalFunctionReference(const GlobalValue *GV, const TargetMachine &TM) const
unsigned getPrefLoopAlignment() const
unsigned getVectorInsertExtractBaseCost() const