LLVM  8.0.0svn
AArch64Subtarget.h
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1 //===--- AArch64Subtarget.h - Define Subtarget for the AArch64 -*- C++ -*--===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file declares the AArch64 specific subclass of TargetSubtarget.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
15 #define LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
16 
17 #include "AArch64FrameLowering.h"
18 #include "AArch64ISelLowering.h"
19 #include "AArch64InstrInfo.h"
20 #include "AArch64RegisterInfo.h"
27 #include "llvm/IR/DataLayout.h"
28 #include <string>
29 
30 #define GET_SUBTARGETINFO_HEADER
31 #include "AArch64GenSubtargetInfo.inc"
32 
33 namespace llvm {
34 class GlobalValue;
35 class StringRef;
36 class Triple;
37 
39 public:
40  enum ARMProcFamilyEnum : uint8_t {
60  };
61 
62 protected:
63  /// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
65 
66  bool HasV8_1aOps = false;
67  bool HasV8_2aOps = false;
68  bool HasV8_3aOps = false;
69  bool HasV8_4aOps = false;
70  bool HasV8_5aOps = false;
71 
72  bool HasFPARMv8 = false;
73  bool HasNEON = false;
74  bool HasCrypto = false;
75  bool HasDotProd = false;
76  bool HasCRC = false;
77  bool HasLSE = false;
78  bool HasRAS = false;
79  bool HasRDM = false;
80  bool HasPerfMon = false;
81  bool HasFullFP16 = false;
82  bool HasFP16FML = false;
83  bool HasSPE = false;
84 
85  // ARMv8.4 Crypto extensions
86  bool HasSM4 = true;
87  bool HasSHA3 = true;
88 
89  bool HasSHA2 = true;
90  bool HasAES = true;
91 
92  bool HasLSLFast = false;
93  bool HasSVE = false;
94  bool HasRCPC = false;
95  bool HasAggressiveFMA = false;
96 
97  // Armv8.5-A Extensions
98  bool HasAlternativeNZCV = false;
99  bool HasFRInt3264 = false;
100  bool HasSpecRestrict = false;
101  bool HasSpecCtrl = false;
102  bool HasPredCtrl = false;
103  bool HasCCDP = false;
104  bool HasBTI = false;
105  bool HasRandGen = false;
106  bool HasMTE = false;
107 
108  // HasZeroCycleRegMove - Has zero-cycle register mov instructions.
109  bool HasZeroCycleRegMove = false;
110 
111  // HasZeroCycleZeroing - Has zero-cycle zeroing instructions.
112  bool HasZeroCycleZeroing = false;
113  bool HasZeroCycleZeroingGP = false;
114  bool HasZeroCycleZeroingFP = false;
116 
117  // StrictAlign - Disallow unaligned memory accesses.
118  bool StrictAlign = false;
119 
120  // NegativeImmediates - transform instructions with negative immediates
121  bool NegativeImmediates = true;
122 
123  // Enable 64-bit vectorization in SLP.
125 
126  bool UseAA = false;
128  bool BalanceFPOps = false;
129  bool CustomAsCheapAsMove = false;
130  bool ExynosAsCheapAsMove = false;
131  bool UsePostRAScheduler = false;
133  bool Paired128IsSlow = false;
134  bool STRQroIsSlow = false;
138  bool HasFuseAddress = false;
139  bool HasFuseAES = false;
140  bool HasFuseCryptoEOR = false;
141  bool HasFuseCCSelect = false;
142  bool HasFuseLiterals = false;
144  bool UseRSqrt = false;
145  uint8_t MaxInterleaveFactor = 2;
147  uint16_t CacheLineSize = 0;
148  uint16_t PrefetchDistance = 0;
149  uint16_t MinPrefetchStride = 1;
150  unsigned MaxPrefetchIterationsAhead = UINT_MAX;
151  unsigned PrefFunctionAlignment = 0;
152  unsigned PrefLoopAlignment = 0;
153  unsigned MaxJumpTableSize = 0;
154  unsigned WideningBaseCost = 0;
155 
156  // ReserveXRegister[i] - X#i is not available as a general purpose register.
158 
159  // CustomCallUsedXRegister[i] - X#i call saved.
161 
162  bool IsLittle;
163 
164  /// TargetTriple - What processor and OS we're targeting.
166 
171 
172  /// GlobalISel related APIs.
173  std::unique_ptr<CallLowering> CallLoweringInfo;
174  std::unique_ptr<InstructionSelector> InstSelector;
175  std::unique_ptr<LegalizerInfo> Legalizer;
176  std::unique_ptr<RegisterBankInfo> RegBankInfo;
177 
178 private:
179  /// initializeSubtargetDependencies - Initializes using CPUString and the
180  /// passed in feature string so that we can use initializer lists for
181  /// subtarget initialization.
182  AArch64Subtarget &initializeSubtargetDependencies(StringRef FS,
183  StringRef CPUString);
184 
185  /// Initialize properties based on the selected processor family.
186  void initializeProperties();
187 
188 public:
189  /// This constructor initializes the data members to match that
190  /// of the specified triple.
191  AArch64Subtarget(const Triple &TT, const std::string &CPU,
192  const std::string &FS, const TargetMachine &TM,
193  bool LittleEndian);
194 
196  return &TSInfo;
197  }
198  const AArch64FrameLowering *getFrameLowering() const override {
199  return &FrameLowering;
200  }
201  const AArch64TargetLowering *getTargetLowering() const override {
202  return &TLInfo;
203  }
204  const AArch64InstrInfo *getInstrInfo() const override { return &InstrInfo; }
205  const AArch64RegisterInfo *getRegisterInfo() const override {
206  return &getInstrInfo()->getRegisterInfo();
207  }
208  const CallLowering *getCallLowering() const override;
209  const InstructionSelector *getInstructionSelector() const override;
210  const LegalizerInfo *getLegalizerInfo() const override;
211  const RegisterBankInfo *getRegBankInfo() const override;
212  const Triple &getTargetTriple() const { return TargetTriple; }
213  bool enableMachineScheduler() const override { return true; }
214  bool enablePostRAScheduler() const override {
215  return UsePostRAScheduler;
216  }
217 
218  /// Returns ARM processor family.
219  /// Avoid this function! CPU specifics should be kept local to this class
220  /// and preferably modeled with SubtargetFeatures or properties in
221  /// initializeProperties().
223  return ARMProcFamily;
224  }
225 
226  bool hasV8_1aOps() const { return HasV8_1aOps; }
227  bool hasV8_2aOps() const { return HasV8_2aOps; }
228  bool hasV8_3aOps() const { return HasV8_3aOps; }
229  bool hasV8_4aOps() const { return HasV8_4aOps; }
230  bool hasV8_5aOps() const { return HasV8_5aOps; }
231 
232  bool hasZeroCycleRegMove() const { return HasZeroCycleRegMove; }
233 
235 
237 
240  }
241 
242  bool requiresStrictAlign() const { return StrictAlign; }
243 
244  bool isXRaySupported() const override { return true; }
245 
246  unsigned getMinVectorRegisterBitWidth() const {
248  }
249 
250  bool isXRegisterReserved(size_t i) const { return ReserveXRegister[i]; }
251  unsigned getNumXRegisterReserved() const { return ReserveXRegister.count(); }
252  bool isXRegCustomCalleeSaved(size_t i) const {
253  return CustomCallSavedXRegs[i];
254  }
255  bool hasCustomCallingConv() const { return CustomCallSavedXRegs.any(); }
256  bool hasFPARMv8() const { return HasFPARMv8; }
257  bool hasNEON() const { return HasNEON; }
258  bool hasCrypto() const { return HasCrypto; }
259  bool hasDotProd() const { return HasDotProd; }
260  bool hasCRC() const { return HasCRC; }
261  bool hasLSE() const { return HasLSE; }
262  bool hasRAS() const { return HasRAS; }
263  bool hasRDM() const { return HasRDM; }
264  bool hasSM4() const { return HasSM4; }
265  bool hasSHA3() const { return HasSHA3; }
266  bool hasSHA2() const { return HasSHA2; }
267  bool hasAES() const { return HasAES; }
268  bool balanceFPOps() const { return BalanceFPOps; }
271  }
275  bool isPaired128Slow() const { return Paired128IsSlow; }
276  bool isSTRQroSlow() const { return STRQroIsSlow; }
279  }
282  bool hasFuseAddress() const { return HasFuseAddress; }
283  bool hasFuseAES() const { return HasFuseAES; }
284  bool hasFuseCryptoEOR() const { return HasFuseCryptoEOR; }
285  bool hasFuseCCSelect() const { return HasFuseCCSelect; }
286  bool hasFuseLiterals() const { return HasFuseLiterals; }
287 
288  /// Return true if the CPU supports any kind of instruction fusion.
289  bool hasFusion() const {
292  }
293 
294  bool useRSqrt() const { return UseRSqrt; }
295  unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
298  }
299  unsigned getCacheLineSize() const { return CacheLineSize; }
300  unsigned getPrefetchDistance() const { return PrefetchDistance; }
301  unsigned getMinPrefetchStride() const { return MinPrefetchStride; }
302  unsigned getMaxPrefetchIterationsAhead() const {
304  }
305  unsigned getPrefFunctionAlignment() const { return PrefFunctionAlignment; }
306  unsigned getPrefLoopAlignment() const { return PrefLoopAlignment; }
307 
308  unsigned getMaximumJumpTableSize() const { return MaxJumpTableSize; }
309 
310  unsigned getWideningBaseCost() const { return WideningBaseCost; }
311 
312  /// CPU has TBI (top byte of addresses is ignored during HW address
313  /// translation) and OS enables it.
314  bool supportsAddressTopByteIgnored() const;
315 
316  bool hasPerfMon() const { return HasPerfMon; }
317  bool hasFullFP16() const { return HasFullFP16; }
318  bool hasFP16FML() const { return HasFP16FML; }
319  bool hasSPE() const { return HasSPE; }
320  bool hasLSLFast() const { return HasLSLFast; }
321  bool hasSVE() const { return HasSVE; }
322  bool hasRCPC() const { return HasRCPC; }
323  bool hasAggressiveFMA() const { return HasAggressiveFMA; }
324  bool hasAlternativeNZCV() const { return HasAlternativeNZCV; }
325  bool hasFRInt3264() const { return HasFRInt3264; }
326  bool hasSpecRestrict() const { return HasSpecRestrict; }
327  bool hasSpecCtrl() const { return HasSpecCtrl; }
328  bool hasPredCtrl() const { return HasPredCtrl; }
329  bool hasCCDP() const { return HasCCDP; }
330  bool hasBTI() const { return HasBTI; }
331  bool hasRandGen() const { return HasRandGen; }
332  bool hasMTE() const { return HasMTE; }
333 
334  bool isLittleEndian() const { return IsLittle; }
335 
336  bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
337  bool isTargetIOS() const { return TargetTriple.isiOS(); }
338  bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
339  bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
340  bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
341  bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
342 
343  bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
344  bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
345  bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
346 
347  bool useAA() const override { return UseAA; }
348 
349  bool useSmallAddressing() const {
350  switch (TLInfo.getTargetMachine().getCodeModel()) {
351  case CodeModel::Kernel:
352  // Kernel is currently allowed only for Fuchsia targets,
353  // where it is the same as Small for almost all purposes.
354  case CodeModel::Small:
355  return true;
356  default:
357  return false;
358  }
359  }
360 
361  /// ParseSubtargetFeatures - Parses features string setting specified
362  /// subtarget options. Definition of function is auto generated by tblgen.
364 
365  /// ClassifyGlobalReference - Find the target operand flags that describe
366  /// how a global value should be referenced for the current subtarget.
367  unsigned char ClassifyGlobalReference(const GlobalValue *GV,
368  const TargetMachine &TM) const;
369 
370  unsigned char classifyGlobalFunctionReference(const GlobalValue *GV,
371  const TargetMachine &TM) const;
372 
374  unsigned NumRegionInstrs) const override;
375 
376  bool enableEarlyIfConversion() const override;
377 
378  std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const override;
379 
381  switch (CC) {
382  case CallingConv::C:
383  return isTargetWindows();
384  case CallingConv::Win64:
385  return true;
386  default:
387  return false;
388  }
389  }
390 
391  void mirFileLoaded(MachineFunction &MF) const override;
392 };
393 } // End llvm namespace
394 
395 #endif
const Triple & getTargetTriple() const
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:474
bool hasAlternativeNZCV() const
bool isMisaligned128StoreSlow() const
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
bool hasCustomCallingConv() const
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:592
bool predictableSelectIsExpensive() const
unsigned char ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const
ClassifyGlobalReference - Find the target operand flags that describe how a global value should be re...
const InstructionSelector * getInstructionSelector() const override
AArch64SelectionDAGInfo TSInfo
const AArch64FrameLowering * getFrameLowering() const override
bool isOSFuchsia() const
Definition: Triple.h:494
const CallLowering * getCallLowering() const override
bool isCallingConvWin64(CallingConv::ID CC) const
bool hasCustomCheapAsMoveHandling() const
void mirFileLoaded(MachineFunction &MF) const override
void overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const override
unsigned getCacheLineSize() const
Holds all the information related to register banks.
bool hasFusion() const
Return true if the CPU supports any kind of instruction fusion.
bool hasArithmeticBccFusion() const
bool hasZeroCycleRegMove() const
The C convention as implemented on Windows/x86-64 and AArch64.
Definition: CallingConv.h:154
std::unique_ptr< InstructionSelector > InstSelector
bool useAlternateSExtLoadCVTF32Pattern() const
const AArch64RegisterInfo * getRegisterInfo() const override
std::unique_ptr< LegalizerInfo > Legalizer
unsigned getPrefetchDistance() const
bool useAA() const override
bool isiOS() const
Is this an iOS triple.
Definition: Triple.h:455
unsigned getWideningBaseCost() const
bool enableMachineScheduler() const override
bool isXRegisterReserved(size_t i) const
bool supportsAddressTopByteIgnored() const
CPU has TBI (top byte of addresses is ignored during HW address translation) and OS enables it...
bool enableEarlyIfConversion() const override
unsigned getMinVectorRegisterBitWidth() const
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:566
const AArch64TargetLowering * getTargetLowering() const override
const AArch64RegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
bool requiresStrictAlign() const
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
Definition: Triple.h:597
bool hasExynosCheapAsMoveHandling() const
bool isXRaySupported() const override
bool any() const
any - Returns true if any bit is set.
Definition: BitVector.h:181
unsigned getPrefFunctionAlignment() const
bool useSmallAddressing() const
std::unique_ptr< CallLowering > CallLoweringInfo
GlobalISel related APIs.
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:602
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:35
const TargetMachine & getTargetMachine() const
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
unsigned getMinPrefetchStride() const
const AArch64SelectionDAGInfo * getSelectionDAGInfo() const override
bool hasArithmeticCbzFusion() const
size_type count() const
count - Returns the number of bits which are set.
Definition: BitVector.h:173
AArch64InstrInfo InstrInfo
unsigned getMaximumJumpTableSize() const
void ParseSubtargetFeatures(StringRef CPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
bool isOSLinux() const
Tests whether the OS is Linux.
Definition: Triple.h:576
bool enablePostRAScheduler() const override
CodeModel::Model getCodeModel() const
Returns the code model.
unsigned getMaxInterleaveFactor() const
unsigned getNumXRegisterReserved() const
std::unique_ptr< RegisterBankInfo > RegBankInfo
Provides the logic to select generic machine instructions.
Define a generic scheduling policy for targets that don&#39;t provide their own MachineSchedStrategy.
std::unique_ptr< PBQPRAConstraint > getCustomPBQPConstraints() const override
AArch64Subtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const TargetMachine &TM, bool LittleEndian)
This constructor initializes the data members to match that of the specified triple.
const LegalizerInfo * getLegalizerInfo() const override
AArch64FrameLowering FrameLowering
ARMProcFamilyEnum getProcFamily() const
Returns ARM processor family.
bool hasZeroCycleZeroingFPWorkaround() const
Triple TargetTriple
TargetTriple - What processor and OS we&#39;re targeting.
ARMProcFamilyEnum ARMProcFamily
ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
bool hasZeroCycleZeroingFP() const
bool hasZeroCycleZeroingGP() const
unsigned getMaxPrefetchIterationsAhead() const
bool isXRegCustomCalleeSaved(size_t i) const
const AArch64InstrInfo * getInstrInfo() const override
This file describes how to lower LLVM calls to machine code calls.
const RegisterBankInfo * getRegBankInfo() const override
bool isAndroid() const
Tests whether the target is Android.
Definition: Triple.h:625
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:59
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
AArch64TargetLowering TLInfo
unsigned char classifyGlobalFunctionReference(const GlobalValue *GV, const TargetMachine &TM) const
unsigned getPrefLoopAlignment() const
unsigned getVectorInsertExtractBaseCost() const