LLVM  9.0.0svn
AArch64Subtarget.h
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1 //===--- AArch64Subtarget.h - Define Subtarget for the AArch64 -*- C++ -*--===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares the AArch64 specific subclass of TargetSubtarget.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
14 #define LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
15 
16 #include "AArch64FrameLowering.h"
17 #include "AArch64ISelLowering.h"
18 #include "AArch64InstrInfo.h"
19 #include "AArch64RegisterInfo.h"
26 #include "llvm/IR/DataLayout.h"
27 #include <string>
28 
29 #define GET_SUBTARGETINFO_HEADER
30 #include "AArch64GenSubtargetInfo.inc"
31 
32 namespace llvm {
33 class GlobalValue;
34 class StringRef;
35 class Triple;
36 
38 public:
39  enum ARMProcFamilyEnum : uint8_t {
61  };
62 
63 protected:
64  /// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
66 
67  bool HasV8_1aOps = false;
68  bool HasV8_2aOps = false;
69  bool HasV8_3aOps = false;
70  bool HasV8_4aOps = false;
71  bool HasV8_5aOps = false;
72 
73  bool HasFPARMv8 = false;
74  bool HasNEON = false;
75  bool HasCrypto = false;
76  bool HasDotProd = false;
77  bool HasCRC = false;
78  bool HasLSE = false;
79  bool HasRAS = false;
80  bool HasRDM = false;
81  bool HasPerfMon = false;
82  bool HasFullFP16 = false;
83  bool HasFP16FML = false;
84  bool HasSPE = false;
85 
86  // ARMv8.1 extensions
87  bool HasVH = false;
88  bool HasPAN = false;
89  bool HasLOR = false;
90 
91  // ARMv8.2 extensions
92  bool HasPsUAO = false;
93  bool HasPAN_RWV = false;
94  bool HasCCPP = false;
95 
96  // ARMv8.3 extensions
97  bool HasPA = false;
98  bool HasJS = false;
99  bool HasCCIDX = false;
100  bool HasComplxNum = false;
101 
102  // ARMv8.4 extensions
103  bool HasNV = false;
104  bool HasRASv8_4 = false;
105  bool HasMPAM = false;
106  bool HasDIT = false;
107  bool HasTRACEV8_4 = false;
108  bool HasAM = false;
109  bool HasSEL2 = false;
110  bool HasTLB_RMI = false;
111  bool HasFMI = false;
112  bool HasRCPC_IMMO = false;
113  // ARMv8.4 Crypto extensions
114  bool HasSM4 = true;
115  bool HasSHA3 = true;
116 
117  bool HasSHA2 = true;
118  bool HasAES = true;
119 
120  bool HasLSLFast = false;
121  bool HasSVE = false;
122  bool HasRCPC = false;
123  bool HasAggressiveFMA = false;
124 
125  // Armv8.5-A Extensions
126  bool HasAlternativeNZCV = false;
127  bool HasFRInt3264 = false;
128  bool HasSpecRestrict = false;
129  bool HasSSBS = false;
130  bool HasSB = false;
131  bool HasPredRes = false;
132  bool HasCCDP = false;
133  bool HasBTI = false;
134  bool HasRandGen = false;
135  bool HasMTE = false;
136 
137  // HasZeroCycleRegMove - Has zero-cycle register mov instructions.
138  bool HasZeroCycleRegMove = false;
139 
140  // HasZeroCycleZeroing - Has zero-cycle zeroing instructions.
141  bool HasZeroCycleZeroing = false;
142  bool HasZeroCycleZeroingGP = false;
143  bool HasZeroCycleZeroingFP = false;
145 
146  // StrictAlign - Disallow unaligned memory accesses.
147  bool StrictAlign = false;
148 
149  // NegativeImmediates - transform instructions with negative immediates
150  bool NegativeImmediates = true;
151 
152  // Enable 64-bit vectorization in SLP.
154 
155  bool UseAA = false;
157  bool BalanceFPOps = false;
158  bool CustomAsCheapAsMove = false;
159  bool ExynosAsCheapAsMove = false;
160  bool UsePostRAScheduler = false;
162  bool Paired128IsSlow = false;
163  bool STRQroIsSlow = false;
167  bool HasFuseAddress = false;
168  bool HasFuseAES = false;
170  bool HasFuseCCSelect = false;
171  bool HasFuseCryptoEOR = false;
172  bool HasFuseLiterals = false;
174  bool UseRSqrt = false;
175  bool Force32BitJumpTables = false;
176  bool UseEL1ForTP = false;
177  bool UseEL2ForTP = false;
178  bool UseEL3ForTP = false;
179  uint8_t MaxInterleaveFactor = 2;
181  uint16_t CacheLineSize = 0;
182  uint16_t PrefetchDistance = 0;
183  uint16_t MinPrefetchStride = 1;
184  unsigned MaxPrefetchIterationsAhead = UINT_MAX;
185  unsigned PrefFunctionAlignment = 0;
186  unsigned PrefLoopAlignment = 0;
187  unsigned MaxJumpTableSize = 0;
188  unsigned WideningBaseCost = 0;
189 
190  // ReserveXRegister[i] - X#i is not available as a general purpose register.
192 
193  // CustomCallUsedXRegister[i] - X#i call saved.
195 
196  bool IsLittle;
197 
198  /// TargetTriple - What processor and OS we're targeting.
200 
205 
206  /// GlobalISel related APIs.
207  std::unique_ptr<CallLowering> CallLoweringInfo;
208  std::unique_ptr<InstructionSelector> InstSelector;
209  std::unique_ptr<LegalizerInfo> Legalizer;
210  std::unique_ptr<RegisterBankInfo> RegBankInfo;
211 
212 private:
213  /// initializeSubtargetDependencies - Initializes using CPUString and the
214  /// passed in feature string so that we can use initializer lists for
215  /// subtarget initialization.
216  AArch64Subtarget &initializeSubtargetDependencies(StringRef FS,
217  StringRef CPUString);
218 
219  /// Initialize properties based on the selected processor family.
220  void initializeProperties();
221 
222 public:
223  /// This constructor initializes the data members to match that
224  /// of the specified triple.
225  AArch64Subtarget(const Triple &TT, const std::string &CPU,
226  const std::string &FS, const TargetMachine &TM,
227  bool LittleEndian);
228 
230  return &TSInfo;
231  }
232  const AArch64FrameLowering *getFrameLowering() const override {
233  return &FrameLowering;
234  }
235  const AArch64TargetLowering *getTargetLowering() const override {
236  return &TLInfo;
237  }
238  const AArch64InstrInfo *getInstrInfo() const override { return &InstrInfo; }
239  const AArch64RegisterInfo *getRegisterInfo() const override {
240  return &getInstrInfo()->getRegisterInfo();
241  }
242  const CallLowering *getCallLowering() const override;
243  const InstructionSelector *getInstructionSelector() const override;
244  const LegalizerInfo *getLegalizerInfo() const override;
245  const RegisterBankInfo *getRegBankInfo() const override;
246  const Triple &getTargetTriple() const { return TargetTriple; }
247  bool enableMachineScheduler() const override { return true; }
248  bool enablePostRAScheduler() const override {
249  return UsePostRAScheduler;
250  }
251 
252  /// Returns ARM processor family.
253  /// Avoid this function! CPU specifics should be kept local to this class
254  /// and preferably modeled with SubtargetFeatures or properties in
255  /// initializeProperties().
257  return ARMProcFamily;
258  }
259 
260  bool hasV8_1aOps() const { return HasV8_1aOps; }
261  bool hasV8_2aOps() const { return HasV8_2aOps; }
262  bool hasV8_3aOps() const { return HasV8_3aOps; }
263  bool hasV8_4aOps() const { return HasV8_4aOps; }
264  bool hasV8_5aOps() const { return HasV8_5aOps; }
265 
266  bool hasZeroCycleRegMove() const { return HasZeroCycleRegMove; }
267 
269 
271 
274  }
275 
276  bool requiresStrictAlign() const { return StrictAlign; }
277 
278  bool isXRaySupported() const override { return true; }
279 
280  unsigned getMinVectorRegisterBitWidth() const {
282  }
283 
284  bool isXRegisterReserved(size_t i) const { return ReserveXRegister[i]; }
285  unsigned getNumXRegisterReserved() const { return ReserveXRegister.count(); }
286  bool isXRegCustomCalleeSaved(size_t i) const {
287  return CustomCallSavedXRegs[i];
288  }
289  bool hasCustomCallingConv() const { return CustomCallSavedXRegs.any(); }
290  bool hasFPARMv8() const { return HasFPARMv8; }
291  bool hasNEON() const { return HasNEON; }
292  bool hasCrypto() const { return HasCrypto; }
293  bool hasDotProd() const { return HasDotProd; }
294  bool hasCRC() const { return HasCRC; }
295  bool hasLSE() const { return HasLSE; }
296  bool hasRAS() const { return HasRAS; }
297  bool hasRDM() const { return HasRDM; }
298  bool hasSM4() const { return HasSM4; }
299  bool hasSHA3() const { return HasSHA3; }
300  bool hasSHA2() const { return HasSHA2; }
301  bool hasAES() const { return HasAES; }
302  bool balanceFPOps() const { return BalanceFPOps; }
305  }
309  bool isPaired128Slow() const { return Paired128IsSlow; }
310  bool isSTRQroSlow() const { return STRQroIsSlow; }
313  }
316  bool hasFuseAddress() const { return HasFuseAddress; }
317  bool hasFuseAES() const { return HasFuseAES; }
319  bool hasFuseCCSelect() const { return HasFuseCCSelect; }
320  bool hasFuseCryptoEOR() const { return HasFuseCryptoEOR; }
321  bool hasFuseLiterals() const { return HasFuseLiterals; }
322 
323  /// Return true if the CPU supports any kind of instruction fusion.
324  bool hasFusion() const {
328  }
329 
330  bool useEL1ForTP() const { return UseEL1ForTP; }
331  bool useEL2ForTP() const { return UseEL2ForTP; }
332  bool useEL3ForTP() const { return UseEL3ForTP; }
333 
334  bool useRSqrt() const { return UseRSqrt; }
336  unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
339  }
340  unsigned getCacheLineSize() const { return CacheLineSize; }
341  unsigned getPrefetchDistance() const { return PrefetchDistance; }
342  unsigned getMinPrefetchStride() const { return MinPrefetchStride; }
343  unsigned getMaxPrefetchIterationsAhead() const {
345  }
346  unsigned getPrefFunctionAlignment() const { return PrefFunctionAlignment; }
347  unsigned getPrefLoopAlignment() const { return PrefLoopAlignment; }
348 
349  unsigned getMaximumJumpTableSize() const { return MaxJumpTableSize; }
350 
351  unsigned getWideningBaseCost() const { return WideningBaseCost; }
352 
353  /// CPU has TBI (top byte of addresses is ignored during HW address
354  /// translation) and OS enables it.
355  bool supportsAddressTopByteIgnored() const;
356 
357  bool hasPerfMon() const { return HasPerfMon; }
358  bool hasFullFP16() const { return HasFullFP16; }
359  bool hasFP16FML() const { return HasFP16FML; }
360  bool hasSPE() const { return HasSPE; }
361  bool hasLSLFast() const { return HasLSLFast; }
362  bool hasSVE() const { return HasSVE; }
363  bool hasRCPC() const { return HasRCPC; }
364  bool hasAggressiveFMA() const { return HasAggressiveFMA; }
365  bool hasAlternativeNZCV() const { return HasAlternativeNZCV; }
366  bool hasFRInt3264() const { return HasFRInt3264; }
367  bool hasSpecRestrict() const { return HasSpecRestrict; }
368  bool hasSSBS() const { return HasSSBS; }
369  bool hasSB() const { return HasSB; }
370  bool hasPredRes() const { return HasPredRes; }
371  bool hasCCDP() const { return HasCCDP; }
372  bool hasBTI() const { return HasBTI; }
373  bool hasRandGen() const { return HasRandGen; }
374  bool hasMTE() const { return HasMTE; }
375 
376  bool isLittleEndian() const { return IsLittle; }
377 
378  bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
379  bool isTargetIOS() const { return TargetTriple.isiOS(); }
380  bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
381  bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
382  bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
383  bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
384 
385  bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
386  bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
387  bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
388 
389  bool useAA() const override { return UseAA; }
390 
391  bool hasVH() const { return HasVH; }
392  bool hasPAN() const { return HasPAN; }
393  bool hasLOR() const { return HasLOR; }
394 
395  bool hasPsUAO() const { return HasPsUAO; }
396  bool hasPAN_RWV() const { return HasPAN_RWV; }
397  bool hasCCPP() const { return HasCCPP; }
398 
399  bool hasPA() const { return HasPA; }
400  bool hasJS() const { return HasJS; }
401  bool hasCCIDX() const { return HasCCIDX; }
402  bool hasComplxNum() const { return HasComplxNum; }
403 
404  bool hasNV() const { return HasNV; }
405  bool hasRASv8_4() const { return HasRASv8_4; }
406  bool hasMPAM() const { return HasMPAM; }
407  bool hasDIT() const { return HasDIT; }
408  bool hasTRACEV8_4() const { return HasTRACEV8_4; }
409  bool hasAM() const { return HasAM; }
410  bool hasSEL2() const { return HasSEL2; }
411  bool hasTLB_RMI() const { return HasTLB_RMI; }
412  bool hasFMI() const { return HasFMI; }
413  bool hasRCPC_IMMO() const { return HasRCPC_IMMO; }
414 
415  bool useSmallAddressing() const {
416  switch (TLInfo.getTargetMachine().getCodeModel()) {
417  case CodeModel::Kernel:
418  // Kernel is currently allowed only for Fuchsia targets,
419  // where it is the same as Small for almost all purposes.
420  case CodeModel::Small:
421  return true;
422  default:
423  return false;
424  }
425  }
426 
427  /// ParseSubtargetFeatures - Parses features string setting specified
428  /// subtarget options. Definition of function is auto generated by tblgen.
430 
431  /// ClassifyGlobalReference - Find the target operand flags that describe
432  /// how a global value should be referenced for the current subtarget.
433  unsigned char ClassifyGlobalReference(const GlobalValue *GV,
434  const TargetMachine &TM) const;
435 
436  unsigned char classifyGlobalFunctionReference(const GlobalValue *GV,
437  const TargetMachine &TM) const;
438 
440  unsigned NumRegionInstrs) const override;
441 
442  bool enableEarlyIfConversion() const override;
443 
444  std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const override;
445 
447  switch (CC) {
448  case CallingConv::C:
449  case CallingConv::Fast:
450  case CallingConv::Swift:
451  return isTargetWindows();
452  case CallingConv::Win64:
453  return true;
454  default:
455  return false;
456  }
457  }
458 
459  void mirFileLoaded(MachineFunction &MF) const override;
460 };
461 } // End llvm namespace
462 
463 #endif
const Triple & getTargetTriple() const
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:476
bool hasAlternativeNZCV() const
bool isMisaligned128StoreSlow() const
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool hasCustomCallingConv() const
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:614
bool predictableSelectIsExpensive() const
unsigned char ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const
ClassifyGlobalReference - Find the target operand flags that describe how a global value should be re...
const InstructionSelector * getInstructionSelector() const override
AArch64SelectionDAGInfo TSInfo
const AArch64FrameLowering * getFrameLowering() const override
bool isOSFuchsia() const
Definition: Triple.h:496
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
const CallLowering * getCallLowering() const override
bool isCallingConvWin64(CallingConv::ID CC) const
bool hasCustomCheapAsMoveHandling() const
void mirFileLoaded(MachineFunction &MF) const override
void overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const override
bool hasFuseArithmeticLogic() const
unsigned getCacheLineSize() const
Holds all the information related to register banks.
bool hasFusion() const
Return true if the CPU supports any kind of instruction fusion.
bool hasArithmeticBccFusion() const
bool hasZeroCycleRegMove() const
bool force32BitJumpTables() const
std::unique_ptr< InstructionSelector > InstSelector
bool useAlternateSExtLoadCVTF32Pattern() const
const AArch64RegisterInfo * getRegisterInfo() const override
std::unique_ptr< LegalizerInfo > Legalizer
unsigned getPrefetchDistance() const
bool useAA() const override
bool isiOS() const
Is this an iOS triple.
Definition: Triple.h:457
unsigned getWideningBaseCost() const
bool enableMachineScheduler() const override
bool isXRegisterReserved(size_t i) const
bool supportsAddressTopByteIgnored() const
CPU has TBI (top byte of addresses is ignored during HW address translation) and OS enables it...
bool enableEarlyIfConversion() const override
unsigned getMinVectorRegisterBitWidth() const
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:529
const AArch64TargetLowering * getTargetLowering() const override
const AArch64RegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
bool requiresStrictAlign() const
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
Definition: Triple.h:619
bool hasExynosCheapAsMoveHandling() const
bool isXRaySupported() const override
bool any() const
any - Returns true if any bit is set.
Definition: BitVector.h:180
unsigned getPrefFunctionAlignment() const
bool useSmallAddressing() const
std::unique_ptr< CallLowering > CallLoweringInfo
GlobalISel related APIs.
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:624
const TargetMachine & getTargetMachine() const
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
unsigned getMinPrefetchStride() const
const AArch64SelectionDAGInfo * getSelectionDAGInfo() const override
bool hasArithmeticCbzFusion() const
size_type count() const
count - Returns the number of bits which are set.
Definition: BitVector.h:172
The C convention as implemented on Windows/x86-64 and AArch64.
Definition: CallingConv.h:153
AArch64InstrInfo InstrInfo
unsigned getMaximumJumpTableSize() const
void ParseSubtargetFeatures(StringRef CPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
bool isOSLinux() const
Tests whether the OS is Linux.
Definition: Triple.h:577
bool enablePostRAScheduler() const override
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
CodeModel::Model getCodeModel() const
Returns the code model.
unsigned getMaxInterleaveFactor() const
unsigned getNumXRegisterReserved() const
std::unique_ptr< RegisterBankInfo > RegBankInfo
Provides the logic to select generic machine instructions.
Define a generic scheduling policy for targets that don&#39;t provide their own MachineSchedStrategy.
std::unique_ptr< PBQPRAConstraint > getCustomPBQPConstraints() const override
AArch64Subtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const TargetMachine &TM, bool LittleEndian)
This constructor initializes the data members to match that of the specified triple.
const LegalizerInfo * getLegalizerInfo() const override
AArch64FrameLowering FrameLowering
ARMProcFamilyEnum getProcFamily() const
Returns ARM processor family.
bool hasZeroCycleZeroingFPWorkaround() const
Triple TargetTriple
TargetTriple - What processor and OS we&#39;re targeting.
ARMProcFamilyEnum ARMProcFamily
ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
bool hasZeroCycleZeroingFP() const
bool hasZeroCycleZeroingGP() const
unsigned getMaxPrefetchIterationsAhead() const
bool isXRegCustomCalleeSaved(size_t i) const
const AArch64InstrInfo * getInstrInfo() const override
This file describes how to lower LLVM calls to machine code calls.
const RegisterBankInfo * getRegBankInfo() const override
bool isAndroid() const
Tests whether the target is Android.
Definition: Triple.h:652
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:65
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
AArch64TargetLowering TLInfo
unsigned char classifyGlobalFunctionReference(const GlobalValue *GV, const TargetMachine &TM) const
unsigned getPrefLoopAlignment() const
unsigned getVectorInsertExtractBaseCost() const