LLVM  7.0.0svn
AArch64Subtarget.h
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1 //===--- AArch64Subtarget.h - Define Subtarget for the AArch64 -*- C++ -*--===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file declares the AArch64 specific subclass of TargetSubtarget.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
15 #define LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
16 
17 #include "AArch64FrameLowering.h"
18 #include "AArch64ISelLowering.h"
19 #include "AArch64InstrInfo.h"
20 #include "AArch64RegisterInfo.h"
27 #include "llvm/IR/DataLayout.h"
28 #include <string>
29 
30 #define GET_SUBTARGETINFO_HEADER
31 #include "AArch64GenSubtargetInfo.inc"
32 
33 namespace llvm {
34 class GlobalValue;
35 class StringRef;
36 class Triple;
37 
39 public:
40  enum ARMProcFamilyEnum : uint8_t {
60  };
61 
62 protected:
63  /// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
65 
66  bool HasV8_1aOps = false;
67  bool HasV8_2aOps = false;
68  bool HasV8_3aOps = false;
69 
70  bool HasFPARMv8 = false;
71  bool HasNEON = false;
72  bool HasCrypto = false;
73  bool HasDotProd = false;
74  bool HasCRC = false;
75  bool HasLSE = false;
76  bool HasRAS = false;
77  bool HasRDM = false;
78  bool HasPerfMon = false;
79  bool HasFullFP16 = false;
80  bool HasSPE = false;
81  bool HasLSLFast = false;
82  bool HasSVE = false;
83  bool HasRCPC = false;
84  bool HasAggressiveFMA = false;
85 
86  // HasZeroCycleRegMove - Has zero-cycle register mov instructions.
87  bool HasZeroCycleRegMove = false;
88 
89  // HasZeroCycleZeroing - Has zero-cycle zeroing instructions.
90  bool HasZeroCycleZeroing = false;
92 
93  // StrictAlign - Disallow unaligned memory accesses.
94  bool StrictAlign = false;
95 
96  // NegativeImmediates - transform instructions with negative immediates
97  bool NegativeImmediates = true;
98 
99  // Enable 64-bit vectorization in SLP.
101 
102  bool UseAA = false;
104  bool BalanceFPOps = false;
105  bool CustomAsCheapAsMove = false;
106  bool ExynosAsCheapAsMove = false;
107  bool UsePostRAScheduler = false;
109  bool Paired128IsSlow = false;
110  bool STRQroIsSlow = false;
114  bool HasFuseAddress = false;
115  bool HasFuseAES = false;
116  bool HasFuseCCSelect = false;
117  bool HasFuseLiterals = false;
119  bool UseRSqrt = false;
120  uint8_t MaxInterleaveFactor = 2;
122  uint16_t CacheLineSize = 0;
123  uint16_t PrefetchDistance = 0;
124  uint16_t MinPrefetchStride = 1;
125  unsigned MaxPrefetchIterationsAhead = UINT_MAX;
126  unsigned PrefFunctionAlignment = 0;
127  unsigned PrefLoopAlignment = 0;
128  unsigned MaxJumpTableSize = 0;
129  unsigned WideningBaseCost = 0;
130 
131  // ReserveX18 - X18 is not available as a general purpose register.
133 
134  bool IsLittle;
135 
136  /// TargetTriple - What processor and OS we're targeting.
138 
143 
144  /// GlobalISel related APIs.
145  std::unique_ptr<CallLowering> CallLoweringInfo;
146  std::unique_ptr<InstructionSelector> InstSelector;
147  std::unique_ptr<LegalizerInfo> Legalizer;
148  std::unique_ptr<RegisterBankInfo> RegBankInfo;
149 
150 private:
151  /// initializeSubtargetDependencies - Initializes using CPUString and the
152  /// passed in feature string so that we can use initializer lists for
153  /// subtarget initialization.
154  AArch64Subtarget &initializeSubtargetDependencies(StringRef FS,
155  StringRef CPUString);
156 
157  /// Initialize properties based on the selected processor family.
158  void initializeProperties();
159 
160 public:
161  /// This constructor initializes the data members to match that
162  /// of the specified triple.
163  AArch64Subtarget(const Triple &TT, const std::string &CPU,
164  const std::string &FS, const TargetMachine &TM,
165  bool LittleEndian);
166 
168  return &TSInfo;
169  }
170  const AArch64FrameLowering *getFrameLowering() const override {
171  return &FrameLowering;
172  }
173  const AArch64TargetLowering *getTargetLowering() const override {
174  return &TLInfo;
175  }
176  const AArch64InstrInfo *getInstrInfo() const override { return &InstrInfo; }
177  const AArch64RegisterInfo *getRegisterInfo() const override {
178  return &getInstrInfo()->getRegisterInfo();
179  }
180  const CallLowering *getCallLowering() const override;
181  const InstructionSelector *getInstructionSelector() const override;
182  const LegalizerInfo *getLegalizerInfo() const override;
183  const RegisterBankInfo *getRegBankInfo() const override;
184  const Triple &getTargetTriple() const { return TargetTriple; }
185  bool enableMachineScheduler() const override { return true; }
186  bool enablePostRAScheduler() const override {
187  return UsePostRAScheduler;
188  }
189 
190  /// Returns ARM processor family.
191  /// Avoid this function! CPU specifics should be kept local to this class
192  /// and preferably modeled with SubtargetFeatures or properties in
193  /// initializeProperties().
195  return ARMProcFamily;
196  }
197 
198  bool hasV8_1aOps() const { return HasV8_1aOps; }
199  bool hasV8_2aOps() const { return HasV8_2aOps; }
200  bool hasV8_3aOps() const { return HasV8_3aOps; }
201 
202  bool hasZeroCycleRegMove() const { return HasZeroCycleRegMove; }
203 
204  bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; }
205 
208  }
209 
210  bool requiresStrictAlign() const { return StrictAlign; }
211 
212  bool isXRaySupported() const override { return true; }
213 
214  unsigned getMinVectorRegisterBitWidth() const {
216  }
217 
218  bool isX18Reserved() const { return ReserveX18; }
219  bool hasFPARMv8() const { return HasFPARMv8; }
220  bool hasNEON() const { return HasNEON; }
221  bool hasCrypto() const { return HasCrypto; }
222  bool hasDotProd() const { return HasDotProd; }
223  bool hasCRC() const { return HasCRC; }
224  bool hasLSE() const { return HasLSE; }
225  bool hasRAS() const { return HasRAS; }
226  bool hasRDM() const { return HasRDM; }
227  bool balanceFPOps() const { return BalanceFPOps; }
230  }
234  bool isPaired128Slow() const { return Paired128IsSlow; }
235  bool isSTRQroSlow() const { return STRQroIsSlow; }
238  }
241  bool hasFuseAddress() const { return HasFuseAddress; }
242  bool hasFuseAES() const { return HasFuseAES; }
243  bool hasFuseCCSelect() const { return HasFuseCCSelect; }
244  bool hasFuseLiterals() const { return HasFuseLiterals; }
245 
246  /// \brief Return true if the CPU supports any kind of instruction fusion.
247  bool hasFusion() const {
250  }
251 
252  bool useRSqrt() const { return UseRSqrt; }
253  unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
256  }
257  unsigned getCacheLineSize() const { return CacheLineSize; }
258  unsigned getPrefetchDistance() const { return PrefetchDistance; }
259  unsigned getMinPrefetchStride() const { return MinPrefetchStride; }
260  unsigned getMaxPrefetchIterationsAhead() const {
262  }
263  unsigned getPrefFunctionAlignment() const { return PrefFunctionAlignment; }
264  unsigned getPrefLoopAlignment() const { return PrefLoopAlignment; }
265 
266  unsigned getMaximumJumpTableSize() const { return MaxJumpTableSize; }
267 
268  unsigned getWideningBaseCost() const { return WideningBaseCost; }
269 
270  /// CPU has TBI (top byte of addresses is ignored during HW address
271  /// translation) and OS enables it.
272  bool supportsAddressTopByteIgnored() const;
273 
274  bool hasPerfMon() const { return HasPerfMon; }
275  bool hasFullFP16() const { return HasFullFP16; }
276  bool hasSPE() const { return HasSPE; }
277  bool hasLSLFast() const { return HasLSLFast; }
278  bool hasSVE() const { return HasSVE; }
279  bool hasRCPC() const { return HasRCPC; }
280  bool hasAggressiveFMA() const { return HasAggressiveFMA; }
281 
282  bool isLittleEndian() const { return IsLittle; }
283 
284  bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
285  bool isTargetIOS() const { return TargetTriple.isiOS(); }
286  bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
287  bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
288  bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
289  bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
290 
291  bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
292  bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
293  bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
294 
295  bool useAA() const override { return UseAA; }
296 
297  bool useSmallAddressing() const {
298  switch (TLInfo.getTargetMachine().getCodeModel()) {
299  case CodeModel::Kernel:
300  // Kernel is currently allowed only for Fuchsia targets,
301  // where it is the same as Small for almost all purposes.
302  case CodeModel::Small:
303  return true;
304  default:
305  return false;
306  }
307  }
308 
309  /// ParseSubtargetFeatures - Parses features string setting specified
310  /// subtarget options. Definition of function is auto generated by tblgen.
312 
313  /// ClassifyGlobalReference - Find the target operand flags that describe
314  /// how a global value should be referenced for the current subtarget.
315  unsigned char ClassifyGlobalReference(const GlobalValue *GV,
316  const TargetMachine &TM) const;
317 
318  unsigned char classifyGlobalFunctionReference(const GlobalValue *GV,
319  const TargetMachine &TM) const;
320 
322  unsigned NumRegionInstrs) const override;
323 
324  bool enableEarlyIfConversion() const override;
325 
326  std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const override;
327 
329  switch (CC) {
330  case CallingConv::C:
331  return isTargetWindows();
332  case CallingConv::Win64:
333  return true;
334  default:
335  return false;
336  }
337  }
338 
339  void mirFileLoaded(MachineFunction &MF) const override;
340 };
341 } // End llvm namespace
342 
343 #endif
const Triple & getTargetTriple() const
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:468
bool isMisaligned128StoreSlow() const
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:586
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:35
bool predictableSelectIsExpensive() const
bool hasZeroCycleZeroing() const
unsigned char ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const
ClassifyGlobalReference - Find the target operand flags that describe how a global value should be re...
const InstructionSelector * getInstructionSelector() const override
AArch64SelectionDAGInfo TSInfo
const AArch64FrameLowering * getFrameLowering() const override
bool isOSFuchsia() const
Definition: Triple.h:488
const CallLowering * getCallLowering() const override
bool isCallingConvWin64(CallingConv::ID CC) const
bool hasCustomCheapAsMoveHandling() const
void mirFileLoaded(MachineFunction &MF) const override
void overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const override
unsigned getCacheLineSize() const
Holds all the information related to register banks.
bool hasFusion() const
Return true if the CPU supports any kind of instruction fusion.
bool hasArithmeticBccFusion() const
bool hasZeroCycleRegMove() const
std::unique_ptr< InstructionSelector > InstSelector
bool useAlternateSExtLoadCVTF32Pattern() const
const AArch64RegisterInfo * getRegisterInfo() const override
std::unique_ptr< LegalizerInfo > Legalizer
unsigned getPrefetchDistance() const
bool useAA() const override
bool isiOS() const
Is this an iOS triple.
Definition: Triple.h:449
unsigned getWideningBaseCost() const
bool enableMachineScheduler() const override
bool supportsAddressTopByteIgnored() const
CPU has TBI (top byte of addresses is ignored during HW address translation) and OS enables it...
bool enableEarlyIfConversion() const override
unsigned getMinVectorRegisterBitWidth() const
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:560
const AArch64TargetLowering * getTargetLowering() const override
const AArch64RegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
bool requiresStrictAlign() const
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
Definition: Triple.h:591
bool hasExynosCheapAsMoveHandling() const
bool isXRaySupported() const override
unsigned getPrefFunctionAlignment() const
bool useSmallAddressing() const
std::unique_ptr< CallLowering > CallLoweringInfo
GlobalISel related APIs.
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:596
const TargetMachine & getTargetMachine() const
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
unsigned getMinPrefetchStride() const
const AArch64SelectionDAGInfo * getSelectionDAGInfo() const override
bool hasArithmeticCbzFusion() const
AArch64InstrInfo InstrInfo
unsigned getMaximumJumpTableSize() const
void ParseSubtargetFeatures(StringRef CPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
bool isOSLinux() const
Tests whether the OS is Linux.
Definition: Triple.h:570
bool enablePostRAScheduler() const override
CodeModel::Model getCodeModel() const
Returns the code model.
unsigned getMaxInterleaveFactor() const
std::unique_ptr< RegisterBankInfo > RegBankInfo
Provides the logic to select generic machine instructions.
Define a generic scheduling policy for targets that don&#39;t provide their own MachineSchedStrategy.
The C convention as implemented on Windows/x86-64 and AArch64.
Definition: CallingConv.h:154
std::unique_ptr< PBQPRAConstraint > getCustomPBQPConstraints() const override
AArch64Subtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const TargetMachine &TM, bool LittleEndian)
This constructor initializes the data members to match that of the specified triple.
const LegalizerInfo * getLegalizerInfo() const override
AArch64FrameLowering FrameLowering
ARMProcFamilyEnum getProcFamily() const
Returns ARM processor family.
bool hasZeroCycleZeroingFPWorkaround() const
Triple TargetTriple
TargetTriple - What processor and OS we&#39;re targeting.
ARMProcFamilyEnum ARMProcFamily
ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
unsigned getMaxPrefetchIterationsAhead() const
const AArch64InstrInfo * getInstrInfo() const override
This file describes how to lower LLVM calls to machine code calls.
const RegisterBankInfo * getRegBankInfo() const override
bool isAndroid() const
Tests whether the target is Android.
Definition: Triple.h:619
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:59
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
AArch64TargetLowering TLInfo
unsigned char classifyGlobalFunctionReference(const GlobalValue *GV, const TargetMachine &TM) const
unsigned getPrefLoopAlignment() const
unsigned getVectorInsertExtractBaseCost() const