LLVM  9.0.0svn
AArch64Subtarget.h
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1 //===--- AArch64Subtarget.h - Define Subtarget for the AArch64 -*- C++ -*--===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares the AArch64 specific subclass of TargetSubtarget.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
14 #define LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
15 
16 #include "AArch64FrameLowering.h"
17 #include "AArch64ISelLowering.h"
18 #include "AArch64InstrInfo.h"
19 #include "AArch64RegisterInfo.h"
26 #include "llvm/IR/DataLayout.h"
27 #include <string>
28 
29 #define GET_SUBTARGETINFO_HEADER
30 #include "AArch64GenSubtargetInfo.inc"
31 
32 namespace llvm {
33 class GlobalValue;
34 class StringRef;
35 class Triple;
36 
38 public:
39  enum ARMProcFamilyEnum : uint8_t {
60  };
61 
62 protected:
63  /// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
65 
66  bool HasV8_1aOps = false;
67  bool HasV8_2aOps = false;
68  bool HasV8_3aOps = false;
69  bool HasV8_4aOps = false;
70  bool HasV8_5aOps = false;
71 
72  bool HasFPARMv8 = false;
73  bool HasNEON = false;
74  bool HasCrypto = false;
75  bool HasDotProd = false;
76  bool HasCRC = false;
77  bool HasLSE = false;
78  bool HasRAS = false;
79  bool HasRDM = false;
80  bool HasPerfMon = false;
81  bool HasFullFP16 = false;
82  bool HasFP16FML = false;
83  bool HasSPE = false;
84 
85  // ARMv8.1 extensions
86  bool HasVH = false;
87  bool HasPAN = false;
88  bool HasLOR = false;
89 
90  // ARMv8.2 extensions
91  bool HasPsUAO = false;
92  bool HasPAN_RWV = false;
93  bool HasCCPP = false;
94 
95  // ARMv8.3 extensions
96  bool HasPA = false;
97  bool HasJS = false;
98  bool HasCCIDX = false;
99  bool HasComplxNum = false;
100 
101  // ARMv8.4 extensions
102  bool HasNV = false;
103  bool HasRASv8_4 = false;
104  bool HasMPAM = false;
105  bool HasDIT = false;
106  bool HasTRACEV8_4 = false;
107  bool HasAM = false;
108  bool HasSEL2 = false;
109  bool HasTLB_RMI = false;
110  bool HasFMI = false;
111  bool HasRCPC_IMMO = false;
112  // ARMv8.4 Crypto extensions
113  bool HasSM4 = true;
114  bool HasSHA3 = true;
115 
116  bool HasSHA2 = true;
117  bool HasAES = true;
118 
119  bool HasLSLFast = false;
120  bool HasSVE = false;
121  bool HasRCPC = false;
122  bool HasAggressiveFMA = false;
123 
124  // Armv8.5-A Extensions
125  bool HasAlternativeNZCV = false;
126  bool HasFRInt3264 = false;
127  bool HasSpecRestrict = false;
128  bool HasSSBS = false;
129  bool HasSB = false;
130  bool HasPredRes = false;
131  bool HasCCDP = false;
132  bool HasBTI = false;
133  bool HasRandGen = false;
134  bool HasMTE = false;
135 
136  // HasZeroCycleRegMove - Has zero-cycle register mov instructions.
137  bool HasZeroCycleRegMove = false;
138 
139  // HasZeroCycleZeroing - Has zero-cycle zeroing instructions.
140  bool HasZeroCycleZeroing = false;
141  bool HasZeroCycleZeroingGP = false;
142  bool HasZeroCycleZeroingFP = false;
144 
145  // StrictAlign - Disallow unaligned memory accesses.
146  bool StrictAlign = false;
147 
148  // NegativeImmediates - transform instructions with negative immediates
149  bool NegativeImmediates = true;
150 
151  // Enable 64-bit vectorization in SLP.
153 
154  bool UseAA = false;
156  bool BalanceFPOps = false;
157  bool CustomAsCheapAsMove = false;
158  bool ExynosAsCheapAsMove = false;
159  bool UsePostRAScheduler = false;
161  bool Paired128IsSlow = false;
162  bool STRQroIsSlow = false;
166  bool HasFuseAddress = false;
167  bool HasFuseAES = false;
169  bool HasFuseCCSelect = false;
170  bool HasFuseCryptoEOR = false;
171  bool HasFuseLiterals = false;
173  bool UseRSqrt = false;
174  bool Force32BitJumpTables = false;
175  uint8_t MaxInterleaveFactor = 2;
177  uint16_t CacheLineSize = 0;
178  uint16_t PrefetchDistance = 0;
179  uint16_t MinPrefetchStride = 1;
180  unsigned MaxPrefetchIterationsAhead = UINT_MAX;
181  unsigned PrefFunctionAlignment = 0;
182  unsigned PrefLoopAlignment = 0;
183  unsigned MaxJumpTableSize = 0;
184  unsigned WideningBaseCost = 0;
185 
186  // ReserveXRegister[i] - X#i is not available as a general purpose register.
188 
189  // CustomCallUsedXRegister[i] - X#i call saved.
191 
192  bool IsLittle;
193 
194  /// TargetTriple - What processor and OS we're targeting.
196 
201 
202  /// GlobalISel related APIs.
203  std::unique_ptr<CallLowering> CallLoweringInfo;
204  std::unique_ptr<InstructionSelector> InstSelector;
205  std::unique_ptr<LegalizerInfo> Legalizer;
206  std::unique_ptr<RegisterBankInfo> RegBankInfo;
207 
208 private:
209  /// initializeSubtargetDependencies - Initializes using CPUString and the
210  /// passed in feature string so that we can use initializer lists for
211  /// subtarget initialization.
212  AArch64Subtarget &initializeSubtargetDependencies(StringRef FS,
213  StringRef CPUString);
214 
215  /// Initialize properties based on the selected processor family.
216  void initializeProperties();
217 
218 public:
219  /// This constructor initializes the data members to match that
220  /// of the specified triple.
221  AArch64Subtarget(const Triple &TT, const std::string &CPU,
222  const std::string &FS, const TargetMachine &TM,
223  bool LittleEndian);
224 
226  return &TSInfo;
227  }
228  const AArch64FrameLowering *getFrameLowering() const override {
229  return &FrameLowering;
230  }
231  const AArch64TargetLowering *getTargetLowering() const override {
232  return &TLInfo;
233  }
234  const AArch64InstrInfo *getInstrInfo() const override { return &InstrInfo; }
235  const AArch64RegisterInfo *getRegisterInfo() const override {
236  return &getInstrInfo()->getRegisterInfo();
237  }
238  const CallLowering *getCallLowering() const override;
239  const InstructionSelector *getInstructionSelector() const override;
240  const LegalizerInfo *getLegalizerInfo() const override;
241  const RegisterBankInfo *getRegBankInfo() const override;
242  const Triple &getTargetTriple() const { return TargetTriple; }
243  bool enableMachineScheduler() const override { return true; }
244  bool enablePostRAScheduler() const override {
245  return UsePostRAScheduler;
246  }
247 
248  /// Returns ARM processor family.
249  /// Avoid this function! CPU specifics should be kept local to this class
250  /// and preferably modeled with SubtargetFeatures or properties in
251  /// initializeProperties().
253  return ARMProcFamily;
254  }
255 
256  bool hasV8_1aOps() const { return HasV8_1aOps; }
257  bool hasV8_2aOps() const { return HasV8_2aOps; }
258  bool hasV8_3aOps() const { return HasV8_3aOps; }
259  bool hasV8_4aOps() const { return HasV8_4aOps; }
260  bool hasV8_5aOps() const { return HasV8_5aOps; }
261 
262  bool hasZeroCycleRegMove() const { return HasZeroCycleRegMove; }
263 
265 
267 
270  }
271 
272  bool requiresStrictAlign() const { return StrictAlign; }
273 
274  bool isXRaySupported() const override { return true; }
275 
276  unsigned getMinVectorRegisterBitWidth() const {
278  }
279 
280  bool isXRegisterReserved(size_t i) const { return ReserveXRegister[i]; }
281  unsigned getNumXRegisterReserved() const { return ReserveXRegister.count(); }
282  bool isXRegCustomCalleeSaved(size_t i) const {
283  return CustomCallSavedXRegs[i];
284  }
285  bool hasCustomCallingConv() const { return CustomCallSavedXRegs.any(); }
286  bool hasFPARMv8() const { return HasFPARMv8; }
287  bool hasNEON() const { return HasNEON; }
288  bool hasCrypto() const { return HasCrypto; }
289  bool hasDotProd() const { return HasDotProd; }
290  bool hasCRC() const { return HasCRC; }
291  bool hasLSE() const { return HasLSE; }
292  bool hasRAS() const { return HasRAS; }
293  bool hasRDM() const { return HasRDM; }
294  bool hasSM4() const { return HasSM4; }
295  bool hasSHA3() const { return HasSHA3; }
296  bool hasSHA2() const { return HasSHA2; }
297  bool hasAES() const { return HasAES; }
298  bool balanceFPOps() const { return BalanceFPOps; }
301  }
305  bool isPaired128Slow() const { return Paired128IsSlow; }
306  bool isSTRQroSlow() const { return STRQroIsSlow; }
309  }
312  bool hasFuseAddress() const { return HasFuseAddress; }
313  bool hasFuseAES() const { return HasFuseAES; }
315  bool hasFuseCCSelect() const { return HasFuseCCSelect; }
316  bool hasFuseCryptoEOR() const { return HasFuseCryptoEOR; }
317  bool hasFuseLiterals() const { return HasFuseLiterals; }
318 
319  /// Return true if the CPU supports any kind of instruction fusion.
320  bool hasFusion() const {
324  }
325 
326  bool useRSqrt() const { return UseRSqrt; }
328  unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
331  }
332  unsigned getCacheLineSize() const { return CacheLineSize; }
333  unsigned getPrefetchDistance() const { return PrefetchDistance; }
334  unsigned getMinPrefetchStride() const { return MinPrefetchStride; }
335  unsigned getMaxPrefetchIterationsAhead() const {
337  }
338  unsigned getPrefFunctionAlignment() const { return PrefFunctionAlignment; }
339  unsigned getPrefLoopAlignment() const { return PrefLoopAlignment; }
340 
341  unsigned getMaximumJumpTableSize() const { return MaxJumpTableSize; }
342 
343  unsigned getWideningBaseCost() const { return WideningBaseCost; }
344 
345  /// CPU has TBI (top byte of addresses is ignored during HW address
346  /// translation) and OS enables it.
347  bool supportsAddressTopByteIgnored() const;
348 
349  bool hasPerfMon() const { return HasPerfMon; }
350  bool hasFullFP16() const { return HasFullFP16; }
351  bool hasFP16FML() const { return HasFP16FML; }
352  bool hasSPE() const { return HasSPE; }
353  bool hasLSLFast() const { return HasLSLFast; }
354  bool hasSVE() const { return HasSVE; }
355  bool hasRCPC() const { return HasRCPC; }
356  bool hasAggressiveFMA() const { return HasAggressiveFMA; }
357  bool hasAlternativeNZCV() const { return HasAlternativeNZCV; }
358  bool hasFRInt3264() const { return HasFRInt3264; }
359  bool hasSpecRestrict() const { return HasSpecRestrict; }
360  bool hasSSBS() const { return HasSSBS; }
361  bool hasSB() const { return HasSB; }
362  bool hasPredRes() const { return HasPredRes; }
363  bool hasCCDP() const { return HasCCDP; }
364  bool hasBTI() const { return HasBTI; }
365  bool hasRandGen() const { return HasRandGen; }
366  bool hasMTE() const { return HasMTE; }
367 
368  bool isLittleEndian() const { return IsLittle; }
369 
370  bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
371  bool isTargetIOS() const { return TargetTriple.isiOS(); }
372  bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
373  bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
374  bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
375  bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
376 
377  bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
378  bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
379  bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
380 
381  bool useAA() const override { return UseAA; }
382 
383  bool hasVH() const { return HasVH; }
384  bool hasPAN() const { return HasPAN; }
385  bool hasLOR() const { return HasLOR; }
386 
387  bool hasPsUAO() const { return HasPsUAO; }
388  bool hasPAN_RWV() const { return HasPAN_RWV; }
389  bool hasCCPP() const { return HasCCPP; }
390 
391  bool hasPA() const { return HasPA; }
392  bool hasJS() const { return HasJS; }
393  bool hasCCIDX() const { return HasCCIDX; }
394  bool hasComplxNum() const { return HasComplxNum; }
395 
396  bool hasNV() const { return HasNV; }
397  bool hasRASv8_4() const { return HasRASv8_4; }
398  bool hasMPAM() const { return HasMPAM; }
399  bool hasDIT() const { return HasDIT; }
400  bool hasTRACEV8_4() const { return HasTRACEV8_4; }
401  bool hasAM() const { return HasAM; }
402  bool hasSEL2() const { return HasSEL2; }
403  bool hasTLB_RMI() const { return HasTLB_RMI; }
404  bool hasFMI() const { return HasFMI; }
405  bool hasRCPC_IMMO() const { return HasRCPC_IMMO; }
406 
407  bool useSmallAddressing() const {
408  switch (TLInfo.getTargetMachine().getCodeModel()) {
409  case CodeModel::Kernel:
410  // Kernel is currently allowed only for Fuchsia targets,
411  // where it is the same as Small for almost all purposes.
412  case CodeModel::Small:
413  return true;
414  default:
415  return false;
416  }
417  }
418 
419  /// ParseSubtargetFeatures - Parses features string setting specified
420  /// subtarget options. Definition of function is auto generated by tblgen.
422 
423  /// ClassifyGlobalReference - Find the target operand flags that describe
424  /// how a global value should be referenced for the current subtarget.
425  unsigned char ClassifyGlobalReference(const GlobalValue *GV,
426  const TargetMachine &TM) const;
427 
428  unsigned char classifyGlobalFunctionReference(const GlobalValue *GV,
429  const TargetMachine &TM) const;
430 
432  unsigned NumRegionInstrs) const override;
433 
434  bool enableEarlyIfConversion() const override;
435 
436  std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const override;
437 
439  switch (CC) {
440  case CallingConv::C:
441  case CallingConv::Fast:
442  case CallingConv::Swift:
443  return isTargetWindows();
444  case CallingConv::Win64:
445  return true;
446  default:
447  return false;
448  }
449  }
450 
451  void mirFileLoaded(MachineFunction &MF) const override;
452 };
453 } // End llvm namespace
454 
455 #endif
const Triple & getTargetTriple() const
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:474
bool hasAlternativeNZCV() const
bool isMisaligned128StoreSlow() const
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool hasCustomCallingConv() const
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:602
bool predictableSelectIsExpensive() const
unsigned char ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const
ClassifyGlobalReference - Find the target operand flags that describe how a global value should be re...
const InstructionSelector * getInstructionSelector() const override
AArch64SelectionDAGInfo TSInfo
const AArch64FrameLowering * getFrameLowering() const override
bool isOSFuchsia() const
Definition: Triple.h:494
const CallLowering * getCallLowering() const override
bool isCallingConvWin64(CallingConv::ID CC) const
bool hasCustomCheapAsMoveHandling() const
void mirFileLoaded(MachineFunction &MF) const override
void overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const override
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
bool hasFuseArithmeticLogic() const
unsigned getCacheLineSize() const
Holds all the information related to register banks.
bool hasFusion() const
Return true if the CPU supports any kind of instruction fusion.
bool hasArithmeticBccFusion() const
bool hasZeroCycleRegMove() const
bool force32BitJumpTables() const
std::unique_ptr< InstructionSelector > InstSelector
bool useAlternateSExtLoadCVTF32Pattern() const
const AArch64RegisterInfo * getRegisterInfo() const override
std::unique_ptr< LegalizerInfo > Legalizer
unsigned getPrefetchDistance() const
bool useAA() const override
bool isiOS() const
Is this an iOS triple.
Definition: Triple.h:455
unsigned getWideningBaseCost() const
bool enableMachineScheduler() const override
bool isXRegisterReserved(size_t i) const
bool supportsAddressTopByteIgnored() const
CPU has TBI (top byte of addresses is ignored during HW address translation) and OS enables it...
bool enableEarlyIfConversion() const override
unsigned getMinVectorRegisterBitWidth() const
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:527
const AArch64TargetLowering * getTargetLowering() const override
const AArch64RegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
bool requiresStrictAlign() const
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
Definition: Triple.h:607
bool hasExynosCheapAsMoveHandling() const
bool isXRaySupported() const override
bool any() const
any - Returns true if any bit is set.
Definition: BitVector.h:180
unsigned getPrefFunctionAlignment() const
bool useSmallAddressing() const
std::unique_ptr< CallLowering > CallLoweringInfo
GlobalISel related APIs.
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:612
const TargetMachine & getTargetMachine() const
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
unsigned getMinPrefetchStride() const
const AArch64SelectionDAGInfo * getSelectionDAGInfo() const override
bool hasArithmeticCbzFusion() const
size_type count() const
count - Returns the number of bits which are set.
Definition: BitVector.h:172
AArch64InstrInfo InstrInfo
unsigned getMaximumJumpTableSize() const
void ParseSubtargetFeatures(StringRef CPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
bool isOSLinux() const
Tests whether the OS is Linux.
Definition: Triple.h:575
bool enablePostRAScheduler() const override
CodeModel::Model getCodeModel() const
Returns the code model.
unsigned getMaxInterleaveFactor() const
unsigned getNumXRegisterReserved() const
std::unique_ptr< RegisterBankInfo > RegBankInfo
Provides the logic to select generic machine instructions.
Define a generic scheduling policy for targets that don&#39;t provide their own MachineSchedStrategy.
std::unique_ptr< PBQPRAConstraint > getCustomPBQPConstraints() const override
AArch64Subtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const TargetMachine &TM, bool LittleEndian)
This constructor initializes the data members to match that of the specified triple.
const LegalizerInfo * getLegalizerInfo() const override
AArch64FrameLowering FrameLowering
ARMProcFamilyEnum getProcFamily() const
Returns ARM processor family.
bool hasZeroCycleZeroingFPWorkaround() const
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
Triple TargetTriple
TargetTriple - What processor and OS we&#39;re targeting.
ARMProcFamilyEnum ARMProcFamily
ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
bool hasZeroCycleZeroingFP() const
The C convention as implemented on Windows/x86-64 and AArch64.
Definition: CallingConv.h:153
bool hasZeroCycleZeroingGP() const
unsigned getMaxPrefetchIterationsAhead() const
bool isXRegCustomCalleeSaved(size_t i) const
const AArch64InstrInfo * getInstrInfo() const override
This file describes how to lower LLVM calls to machine code calls.
const RegisterBankInfo * getRegBankInfo() const override
bool isAndroid() const
Tests whether the target is Android.
Definition: Triple.h:635
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:58
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
AArch64TargetLowering TLInfo
unsigned char classifyGlobalFunctionReference(const GlobalValue *GV, const TargetMachine &TM) const
unsigned getPrefLoopAlignment() const
unsigned getVectorInsertExtractBaseCost() const