LLVM  8.0.0svn
AArch64Subtarget.h
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1 //===--- AArch64Subtarget.h - Define Subtarget for the AArch64 -*- C++ -*--===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file declares the AArch64 specific subclass of TargetSubtarget.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
15 #define LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
16 
17 #include "AArch64FrameLowering.h"
18 #include "AArch64ISelLowering.h"
19 #include "AArch64InstrInfo.h"
20 #include "AArch64RegisterInfo.h"
27 #include "llvm/IR/DataLayout.h"
28 #include <string>
29 
30 #define GET_SUBTARGETINFO_HEADER
31 #include "AArch64GenSubtargetInfo.inc"
32 
33 namespace llvm {
34 class GlobalValue;
35 class StringRef;
36 class Triple;
37 
39 public:
40  enum ARMProcFamilyEnum : uint8_t {
61  };
62 
63 protected:
64  /// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
66 
67  bool HasV8_1aOps = false;
68  bool HasV8_2aOps = false;
69  bool HasV8_3aOps = false;
70  bool HasV8_4aOps = false;
71  bool HasV8_5aOps = false;
72 
73  bool HasFPARMv8 = false;
74  bool HasNEON = false;
75  bool HasCrypto = false;
76  bool HasDotProd = false;
77  bool HasCRC = false;
78  bool HasLSE = false;
79  bool HasRAS = false;
80  bool HasRDM = false;
81  bool HasPerfMon = false;
82  bool HasFullFP16 = false;
83  bool HasFP16FML = false;
84  bool HasSPE = false;
85 
86  // ARMv8.1 extensions
87  bool HasVH = false;
88  bool HasPAN = false;
89  bool HasLOR = false;
90 
91  // ARMv8.2 extensions
92  bool HasPsUAO = false;
93  bool HasPAN_RWV = false;
94  bool HasCCPP = false;
95 
96  // ARMv8.3 extensions
97  bool HasPA = false;
98  bool HasJS = false;
99  bool HasCCIDX = false;
100  bool HasComplxNum = false;
101 
102  // ARMv8.4 extensions
103  bool HasNV = false;
104  bool HasRASv8_4 = false;
105  bool HasMPAM = false;
106  bool HasDIT = false;
107  bool HasTRACEV8_4 = false;
108  bool HasAM = false;
109  bool HasSEL2 = false;
110  bool HasTLB_RMI = false;
111  bool HasFMI = false;
112  bool HasRCPC_IMMO = false;
113  // ARMv8.4 Crypto extensions
114  bool HasSM4 = true;
115  bool HasSHA3 = true;
116 
117  bool HasSHA2 = true;
118  bool HasAES = true;
119 
120  bool HasLSLFast = false;
121  bool HasSVE = false;
122  bool HasRCPC = false;
123  bool HasAggressiveFMA = false;
124 
125  // Armv8.5-A Extensions
126  bool HasAlternativeNZCV = false;
127  bool HasFRInt3264 = false;
128  bool HasSpecRestrict = false;
129  bool HasSpecCtrl = false;
130  bool HasSSBS = false;
131  bool HasPredCtrl = false;
132  bool HasCCDP = false;
133  bool HasBTI = false;
134  bool HasRandGen = false;
135  bool HasMTE = false;
136 
137  // HasZeroCycleRegMove - Has zero-cycle register mov instructions.
138  bool HasZeroCycleRegMove = false;
139 
140  // HasZeroCycleZeroing - Has zero-cycle zeroing instructions.
141  bool HasZeroCycleZeroing = false;
142  bool HasZeroCycleZeroingGP = false;
143  bool HasZeroCycleZeroingFP = false;
145 
146  // StrictAlign - Disallow unaligned memory accesses.
147  bool StrictAlign = false;
148 
149  // NegativeImmediates - transform instructions with negative immediates
150  bool NegativeImmediates = true;
151 
152  // Enable 64-bit vectorization in SLP.
154 
155  bool UseAA = false;
157  bool BalanceFPOps = false;
158  bool CustomAsCheapAsMove = false;
159  bool ExynosAsCheapAsMove = false;
160  bool UsePostRAScheduler = false;
162  bool Paired128IsSlow = false;
163  bool STRQroIsSlow = false;
167  bool HasFuseAddress = false;
168  bool HasFuseAES = false;
169  bool HasFuseCryptoEOR = false;
170  bool HasFuseCCSelect = false;
171  bool HasFuseLiterals = false;
173  bool UseRSqrt = false;
174  bool Force32BitJumpTables = false;
175  uint8_t MaxInterleaveFactor = 2;
177  uint16_t CacheLineSize = 0;
178  uint16_t PrefetchDistance = 0;
179  uint16_t MinPrefetchStride = 1;
180  unsigned MaxPrefetchIterationsAhead = UINT_MAX;
181  unsigned PrefFunctionAlignment = 0;
182  unsigned PrefLoopAlignment = 0;
183  unsigned MaxJumpTableSize = 0;
184  unsigned WideningBaseCost = 0;
185 
186  // ReserveXRegister[i] - X#i is not available as a general purpose register.
188 
189  // CustomCallUsedXRegister[i] - X#i call saved.
191 
192  bool IsLittle;
193 
194  /// TargetTriple - What processor and OS we're targeting.
196 
201 
202  /// GlobalISel related APIs.
203  std::unique_ptr<CallLowering> CallLoweringInfo;
204  std::unique_ptr<InstructionSelector> InstSelector;
205  std::unique_ptr<LegalizerInfo> Legalizer;
206  std::unique_ptr<RegisterBankInfo> RegBankInfo;
207 
208 private:
209  /// initializeSubtargetDependencies - Initializes using CPUString and the
210  /// passed in feature string so that we can use initializer lists for
211  /// subtarget initialization.
212  AArch64Subtarget &initializeSubtargetDependencies(StringRef FS,
213  StringRef CPUString);
214 
215  /// Initialize properties based on the selected processor family.
216  void initializeProperties();
217 
218 public:
219  /// This constructor initializes the data members to match that
220  /// of the specified triple.
221  AArch64Subtarget(const Triple &TT, const std::string &CPU,
222  const std::string &FS, const TargetMachine &TM,
223  bool LittleEndian);
224 
226  return &TSInfo;
227  }
228  const AArch64FrameLowering *getFrameLowering() const override {
229  return &FrameLowering;
230  }
231  const AArch64TargetLowering *getTargetLowering() const override {
232  return &TLInfo;
233  }
234  const AArch64InstrInfo *getInstrInfo() const override { return &InstrInfo; }
235  const AArch64RegisterInfo *getRegisterInfo() const override {
236  return &getInstrInfo()->getRegisterInfo();
237  }
238  const CallLowering *getCallLowering() const override;
239  const InstructionSelector *getInstructionSelector() const override;
240  const LegalizerInfo *getLegalizerInfo() const override;
241  const RegisterBankInfo *getRegBankInfo() const override;
242  const Triple &getTargetTriple() const { return TargetTriple; }
243  bool enableMachineScheduler() const override { return true; }
244  bool enablePostRAScheduler() const override {
245  return UsePostRAScheduler;
246  }
247 
248  /// Returns ARM processor family.
249  /// Avoid this function! CPU specifics should be kept local to this class
250  /// and preferably modeled with SubtargetFeatures or properties in
251  /// initializeProperties().
253  return ARMProcFamily;
254  }
255 
256  bool hasV8_1aOps() const { return HasV8_1aOps; }
257  bool hasV8_2aOps() const { return HasV8_2aOps; }
258  bool hasV8_3aOps() const { return HasV8_3aOps; }
259  bool hasV8_4aOps() const { return HasV8_4aOps; }
260  bool hasV8_5aOps() const { return HasV8_5aOps; }
261 
262  bool hasZeroCycleRegMove() const { return HasZeroCycleRegMove; }
263 
265 
267 
270  }
271 
272  bool requiresStrictAlign() const { return StrictAlign; }
273 
274  bool isXRaySupported() const override { return true; }
275 
276  unsigned getMinVectorRegisterBitWidth() const {
278  }
279 
280  bool isXRegisterReserved(size_t i) const { return ReserveXRegister[i]; }
281  unsigned getNumXRegisterReserved() const { return ReserveXRegister.count(); }
282  bool isXRegCustomCalleeSaved(size_t i) const {
283  return CustomCallSavedXRegs[i];
284  }
285  bool hasCustomCallingConv() const { return CustomCallSavedXRegs.any(); }
286  bool hasFPARMv8() const { return HasFPARMv8; }
287  bool hasNEON() const { return HasNEON; }
288  bool hasCrypto() const { return HasCrypto; }
289  bool hasDotProd() const { return HasDotProd; }
290  bool hasCRC() const { return HasCRC; }
291  bool hasLSE() const { return HasLSE; }
292  bool hasRAS() const { return HasRAS; }
293  bool hasRDM() const { return HasRDM; }
294  bool hasSM4() const { return HasSM4; }
295  bool hasSHA3() const { return HasSHA3; }
296  bool hasSHA2() const { return HasSHA2; }
297  bool hasAES() const { return HasAES; }
298  bool balanceFPOps() const { return BalanceFPOps; }
301  }
305  bool isPaired128Slow() const { return Paired128IsSlow; }
306  bool isSTRQroSlow() const { return STRQroIsSlow; }
309  }
312  bool hasFuseAddress() const { return HasFuseAddress; }
313  bool hasFuseAES() const { return HasFuseAES; }
314  bool hasFuseCryptoEOR() const { return HasFuseCryptoEOR; }
315  bool hasFuseCCSelect() const { return HasFuseCCSelect; }
316  bool hasFuseLiterals() const { return HasFuseLiterals; }
317 
318  /// Return true if the CPU supports any kind of instruction fusion.
319  bool hasFusion() const {
322  }
323 
324  bool useRSqrt() const { return UseRSqrt; }
326  unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
329  }
330  unsigned getCacheLineSize() const { return CacheLineSize; }
331  unsigned getPrefetchDistance() const { return PrefetchDistance; }
332  unsigned getMinPrefetchStride() const { return MinPrefetchStride; }
333  unsigned getMaxPrefetchIterationsAhead() const {
335  }
336  unsigned getPrefFunctionAlignment() const { return PrefFunctionAlignment; }
337  unsigned getPrefLoopAlignment() const { return PrefLoopAlignment; }
338 
339  unsigned getMaximumJumpTableSize() const { return MaxJumpTableSize; }
340 
341  unsigned getWideningBaseCost() const { return WideningBaseCost; }
342 
343  /// CPU has TBI (top byte of addresses is ignored during HW address
344  /// translation) and OS enables it.
345  bool supportsAddressTopByteIgnored() const;
346 
347  bool hasPerfMon() const { return HasPerfMon; }
348  bool hasFullFP16() const { return HasFullFP16; }
349  bool hasFP16FML() const { return HasFP16FML; }
350  bool hasSPE() const { return HasSPE; }
351  bool hasLSLFast() const { return HasLSLFast; }
352  bool hasSVE() const { return HasSVE; }
353  bool hasRCPC() const { return HasRCPC; }
354  bool hasAggressiveFMA() const { return HasAggressiveFMA; }
355  bool hasAlternativeNZCV() const { return HasAlternativeNZCV; }
356  bool hasFRInt3264() const { return HasFRInt3264; }
357  bool hasSpecRestrict() const { return HasSpecRestrict; }
358  bool hasSpecCtrl() const { return HasSpecCtrl; }
359  bool hasSSBS() const { return HasSSBS; }
360  bool hasPredCtrl() const { return HasPredCtrl; }
361  bool hasCCDP() const { return HasCCDP; }
362  bool hasBTI() const { return HasBTI; }
363  bool hasRandGen() const { return HasRandGen; }
364  bool hasMTE() const { return HasMTE; }
365 
366  bool isLittleEndian() const { return IsLittle; }
367 
368  bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
369  bool isTargetIOS() const { return TargetTriple.isiOS(); }
370  bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
371  bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
372  bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
373  bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
374 
375  bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
376  bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
377  bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
378 
379  bool useAA() const override { return UseAA; }
380 
381  bool hasVH() const { return HasVH; }
382  bool hasPAN() const { return HasPAN; }
383  bool hasLOR() const { return HasLOR; }
384 
385  bool hasPsUAO() const { return HasPsUAO; }
386  bool hasPAN_RWV() const { return HasPAN_RWV; }
387  bool hasCCPP() const { return HasCCPP; }
388 
389  bool hasPA() const { return HasPA; }
390  bool hasJS() const { return HasJS; }
391  bool hasCCIDX() const { return HasCCIDX; }
392  bool hasComplxNum() const { return HasComplxNum; }
393 
394  bool hasNV() const { return HasNV; }
395  bool hasRASv8_4() const { return HasRASv8_4; }
396  bool hasMPAM() const { return HasMPAM; }
397  bool hasDIT() const { return HasDIT; }
398  bool hasTRACEV8_4() const { return HasTRACEV8_4; }
399  bool hasAM() const { return HasAM; }
400  bool hasSEL2() const { return HasSEL2; }
401  bool hasTLB_RMI() const { return HasTLB_RMI; }
402  bool hasFMI() const { return HasFMI; }
403  bool hasRCPC_IMMO() const { return HasRCPC_IMMO; }
404 
405  bool useSmallAddressing() const {
406  switch (TLInfo.getTargetMachine().getCodeModel()) {
407  case CodeModel::Kernel:
408  // Kernel is currently allowed only for Fuchsia targets,
409  // where it is the same as Small for almost all purposes.
410  case CodeModel::Small:
411  return true;
412  default:
413  return false;
414  }
415  }
416 
417  /// ParseSubtargetFeatures - Parses features string setting specified
418  /// subtarget options. Definition of function is auto generated by tblgen.
420 
421  /// ClassifyGlobalReference - Find the target operand flags that describe
422  /// how a global value should be referenced for the current subtarget.
423  unsigned char ClassifyGlobalReference(const GlobalValue *GV,
424  const TargetMachine &TM) const;
425 
426  unsigned char classifyGlobalFunctionReference(const GlobalValue *GV,
427  const TargetMachine &TM) const;
428 
430  unsigned NumRegionInstrs) const override;
431 
432  bool enableEarlyIfConversion() const override;
433 
434  std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const override;
435 
437  switch (CC) {
438  case CallingConv::C:
439  case CallingConv::Fast:
440  case CallingConv::Swift:
441  return isTargetWindows();
442  case CallingConv::Win64:
443  return true;
444  default:
445  return false;
446  }
447  }
448 
449  void mirFileLoaded(MachineFunction &MF) const override;
450 };
451 } // End llvm namespace
452 
453 #endif
const Triple & getTargetTriple() const
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:475
bool hasAlternativeNZCV() const
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:35
bool isMisaligned128StoreSlow() const
This class represents lattice values for constants.
Definition: AllocatorList.h:24
bool hasCustomCallingConv() const
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:599
bool predictableSelectIsExpensive() const
unsigned char ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const
ClassifyGlobalReference - Find the target operand flags that describe how a global value should be re...
const InstructionSelector * getInstructionSelector() const override
The C convention as implemented on Windows/x86-64 and AArch64.
Definition: CallingConv.h:154
AArch64SelectionDAGInfo TSInfo
const AArch64FrameLowering * getFrameLowering() const override
bool isOSFuchsia() const
Definition: Triple.h:495
const CallLowering * getCallLowering() const override
bool isCallingConvWin64(CallingConv::ID CC) const
bool hasCustomCheapAsMoveHandling() const
void mirFileLoaded(MachineFunction &MF) const override
void overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const override
unsigned getCacheLineSize() const
Holds all the information related to register banks.
bool hasFusion() const
Return true if the CPU supports any kind of instruction fusion.
bool hasArithmeticBccFusion() const
bool hasZeroCycleRegMove() const
bool force32BitJumpTables() const
std::unique_ptr< InstructionSelector > InstSelector
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:43
bool useAlternateSExtLoadCVTF32Pattern() const
const AArch64RegisterInfo * getRegisterInfo() const override
std::unique_ptr< LegalizerInfo > Legalizer
unsigned getPrefetchDistance() const
bool useAA() const override
bool isiOS() const
Is this an iOS triple.
Definition: Triple.h:456
unsigned getWideningBaseCost() const
bool enableMachineScheduler() const override
bool isXRegisterReserved(size_t i) const
bool supportsAddressTopByteIgnored() const
CPU has TBI (top byte of addresses is ignored during HW address translation) and OS enables it...
bool enableEarlyIfConversion() const override
unsigned getMinVectorRegisterBitWidth() const
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:567
const AArch64TargetLowering * getTargetLowering() const override
const AArch64RegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
bool requiresStrictAlign() const
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
Definition: Triple.h:604
bool hasExynosCheapAsMoveHandling() const
bool isXRaySupported() const override
bool any() const
any - Returns true if any bit is set.
Definition: BitVector.h:181
unsigned getPrefFunctionAlignment() const
bool useSmallAddressing() const
std::unique_ptr< CallLowering > CallLoweringInfo
GlobalISel related APIs.
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:609
const TargetMachine & getTargetMachine() const
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
unsigned getMinPrefetchStride() const
const AArch64SelectionDAGInfo * getSelectionDAGInfo() const override
bool hasArithmeticCbzFusion() const
size_type count() const
count - Returns the number of bits which are set.
Definition: BitVector.h:173
AArch64InstrInfo InstrInfo
unsigned getMaximumJumpTableSize() const
void ParseSubtargetFeatures(StringRef CPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
bool isOSLinux() const
Tests whether the OS is Linux.
Definition: Triple.h:577
bool enablePostRAScheduler() const override
CodeModel::Model getCodeModel() const
Returns the code model.
unsigned getMaxInterleaveFactor() const
unsigned getNumXRegisterReserved() const
std::unique_ptr< RegisterBankInfo > RegBankInfo
Provides the logic to select generic machine instructions.
Define a generic scheduling policy for targets that don&#39;t provide their own MachineSchedStrategy.
std::unique_ptr< PBQPRAConstraint > getCustomPBQPConstraints() const override
AArch64Subtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const TargetMachine &TM, bool LittleEndian)
This constructor initializes the data members to match that of the specified triple.
const LegalizerInfo * getLegalizerInfo() const override
AArch64FrameLowering FrameLowering
ARMProcFamilyEnum getProcFamily() const
Returns ARM processor family.
bool hasZeroCycleZeroingFPWorkaround() const
Triple TargetTriple
TargetTriple - What processor and OS we&#39;re targeting.
ARMProcFamilyEnum ARMProcFamily
ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
bool hasZeroCycleZeroingFP() const
bool hasZeroCycleZeroingGP() const
unsigned getMaxPrefetchIterationsAhead() const
bool isXRegCustomCalleeSaved(size_t i) const
const AArch64InstrInfo * getInstrInfo() const override
This file describes how to lower LLVM calls to machine code calls.
const RegisterBankInfo * getRegBankInfo() const override
bool isAndroid() const
Tests whether the target is Android.
Definition: Triple.h:632
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:59
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
AArch64TargetLowering TLInfo
unsigned char classifyGlobalFunctionReference(const GlobalValue *GV, const TargetMachine &TM) const
unsigned getPrefLoopAlignment() const
unsigned getVectorInsertExtractBaseCost() const