LLVM  10.0.0svn
AArch64Subtarget.h
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1 //===--- AArch64Subtarget.h - Define Subtarget for the AArch64 -*- C++ -*--===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares the AArch64 specific subclass of TargetSubtarget.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
14 #define LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
15 
16 #include "AArch64FrameLowering.h"
17 #include "AArch64ISelLowering.h"
18 #include "AArch64InstrInfo.h"
19 #include "AArch64RegisterInfo.h"
26 #include "llvm/IR/DataLayout.h"
27 #include <string>
28 
29 #define GET_SUBTARGETINFO_HEADER
30 #include "AArch64GenSubtargetInfo.inc"
31 
32 namespace llvm {
33 class GlobalValue;
34 class StringRef;
35 class Triple;
36 
38 public:
39  enum ARMProcFamilyEnum : uint8_t {
64  };
65 
66 protected:
67  /// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
69 
70  bool HasV8_1aOps = false;
71  bool HasV8_2aOps = false;
72  bool HasV8_3aOps = false;
73  bool HasV8_4aOps = false;
74  bool HasV8_5aOps = false;
75 
76  bool HasFPARMv8 = false;
77  bool HasNEON = false;
78  bool HasCrypto = false;
79  bool HasDotProd = false;
80  bool HasCRC = false;
81  bool HasLSE = false;
82  bool HasRAS = false;
83  bool HasRDM = false;
84  bool HasPerfMon = false;
85  bool HasFullFP16 = false;
86  bool HasFP16FML = false;
87  bool HasSPE = false;
88 
89  // ARMv8.1 extensions
90  bool HasVH = false;
91  bool HasPAN = false;
92  bool HasLOR = false;
93 
94  // ARMv8.2 extensions
95  bool HasPsUAO = false;
96  bool HasPAN_RWV = false;
97  bool HasCCPP = false;
98 
99  // Armv8.2 Crypto extensions
100  bool HasSM4 = false;
101  bool HasSHA3 = false;
102  bool HasSHA2 = false;
103  bool HasAES = false;
104 
105  // ARMv8.3 extensions
106  bool HasPA = false;
107  bool HasJS = false;
108  bool HasCCIDX = false;
109  bool HasComplxNum = false;
110 
111  // ARMv8.4 extensions
112  bool HasNV = false;
113  bool HasRASv8_4 = false;
114  bool HasMPAM = false;
115  bool HasDIT = false;
116  bool HasTRACEV8_4 = false;
117  bool HasAM = false;
118  bool HasSEL2 = false;
119  bool HasPMU = false;
120  bool HasTLB_RMI = false;
121  bool HasFMI = false;
122  bool HasRCPC_IMMO = false;
123 
124  bool HasLSLFast = false;
125  bool HasSVE = false;
126  bool HasSVE2 = false;
127  bool HasRCPC = false;
128  bool HasAggressiveFMA = false;
129 
130  // Armv8.5-A Extensions
131  bool HasAlternativeNZCV = false;
132  bool HasFRInt3264 = false;
133  bool HasSpecRestrict = false;
134  bool HasSSBS = false;
135  bool HasSB = false;
136  bool HasPredRes = false;
137  bool HasCCDP = false;
138  bool HasBTI = false;
139  bool HasRandGen = false;
140  bool HasMTE = false;
141  bool HasTME = false;
142 
143  // Arm SVE2 extensions
144  bool HasSVE2AES = false;
145  bool HasSVE2SM4 = false;
146  bool HasSVE2SHA3 = false;
147  bool HasSVE2BitPerm = false;
148 
149  // Future architecture extensions.
150  bool HasETE = false;
151  bool HasTRBE = false;
152 
153  // HasZeroCycleRegMove - Has zero-cycle register mov instructions.
154  bool HasZeroCycleRegMove = false;
155 
156  // HasZeroCycleZeroing - Has zero-cycle zeroing instructions.
157  bool HasZeroCycleZeroing = false;
158  bool HasZeroCycleZeroingGP = false;
159  bool HasZeroCycleZeroingFP = false;
161 
162  // StrictAlign - Disallow unaligned memory accesses.
163  bool StrictAlign = false;
164 
165  // NegativeImmediates - transform instructions with negative immediates
166  bool NegativeImmediates = true;
167 
168  // Enable 64-bit vectorization in SLP.
170 
171  bool UseAA = false;
173  bool BalanceFPOps = false;
174  bool CustomAsCheapAsMove = false;
175  bool ExynosAsCheapAsMove = false;
176  bool UsePostRAScheduler = false;
178  bool Paired128IsSlow = false;
179  bool STRQroIsSlow = false;
183  bool HasFuseAddress = false;
184  bool HasFuseAES = false;
186  bool HasFuseCCSelect = false;
187  bool HasFuseCryptoEOR = false;
188  bool HasFuseLiterals = false;
190  bool UseRSqrt = false;
191  bool Force32BitJumpTables = false;
192  bool UseEL1ForTP = false;
193  bool UseEL2ForTP = false;
194  bool UseEL3ForTP = false;
195  bool AllowTaggedGlobals = false;
196  uint8_t MaxInterleaveFactor = 2;
198  uint16_t CacheLineSize = 0;
199  uint16_t PrefetchDistance = 0;
200  uint16_t MinPrefetchStride = 1;
201  unsigned MaxPrefetchIterationsAhead = UINT_MAX;
203  unsigned PrefLoopLogAlignment = 0;
204  unsigned MaxJumpTableSize = 0;
205  unsigned WideningBaseCost = 0;
206 
207  // ReserveXRegister[i] - X#i is not available as a general purpose register.
209 
210  // CustomCallUsedXRegister[i] - X#i call saved.
212 
213  bool IsLittle;
214 
215  /// TargetTriple - What processor and OS we're targeting.
217 
222 
223  /// GlobalISel related APIs.
224  std::unique_ptr<CallLowering> CallLoweringInfo;
225  std::unique_ptr<InstructionSelector> InstSelector;
226  std::unique_ptr<LegalizerInfo> Legalizer;
227  std::unique_ptr<RegisterBankInfo> RegBankInfo;
228 
229 private:
230  /// initializeSubtargetDependencies - Initializes using CPUString and the
231  /// passed in feature string so that we can use initializer lists for
232  /// subtarget initialization.
233  AArch64Subtarget &initializeSubtargetDependencies(StringRef FS,
234  StringRef CPUString);
235 
236  /// Initialize properties based on the selected processor family.
237  void initializeProperties();
238 
239 public:
240  /// This constructor initializes the data members to match that
241  /// of the specified triple.
242  AArch64Subtarget(const Triple &TT, const std::string &CPU,
243  const std::string &FS, const TargetMachine &TM,
244  bool LittleEndian);
245 
247  return &TSInfo;
248  }
249  const AArch64FrameLowering *getFrameLowering() const override {
250  return &FrameLowering;
251  }
252  const AArch64TargetLowering *getTargetLowering() const override {
253  return &TLInfo;
254  }
255  const AArch64InstrInfo *getInstrInfo() const override { return &InstrInfo; }
256  const AArch64RegisterInfo *getRegisterInfo() const override {
257  return &getInstrInfo()->getRegisterInfo();
258  }
259  const CallLowering *getCallLowering() const override;
261  const LegalizerInfo *getLegalizerInfo() const override;
262  const RegisterBankInfo *getRegBankInfo() const override;
263  const Triple &getTargetTriple() const { return TargetTriple; }
264  bool enableMachineScheduler() const override { return true; }
265  bool enablePostRAScheduler() const override {
266  return UsePostRAScheduler;
267  }
268 
269  /// Returns ARM processor family.
270  /// Avoid this function! CPU specifics should be kept local to this class
271  /// and preferably modeled with SubtargetFeatures or properties in
272  /// initializeProperties().
274  return ARMProcFamily;
275  }
276 
277  bool hasV8_1aOps() const { return HasV8_1aOps; }
278  bool hasV8_2aOps() const { return HasV8_2aOps; }
279  bool hasV8_3aOps() const { return HasV8_3aOps; }
280  bool hasV8_4aOps() const { return HasV8_4aOps; }
281  bool hasV8_5aOps() const { return HasV8_5aOps; }
282 
283  bool hasZeroCycleRegMove() const { return HasZeroCycleRegMove; }
284 
286 
288 
291  }
292 
293  bool requiresStrictAlign() const { return StrictAlign; }
294 
295  bool isXRaySupported() const override { return true; }
296 
297  unsigned getMinVectorRegisterBitWidth() const {
299  }
300 
301  bool isXRegisterReserved(size_t i) const { return ReserveXRegister[i]; }
302  unsigned getNumXRegisterReserved() const { return ReserveXRegister.count(); }
303  bool isXRegCustomCalleeSaved(size_t i) const {
304  return CustomCallSavedXRegs[i];
305  }
306  bool hasCustomCallingConv() const { return CustomCallSavedXRegs.any(); }
307  bool hasFPARMv8() const { return HasFPARMv8; }
308  bool hasNEON() const { return HasNEON; }
309  bool hasCrypto() const { return HasCrypto; }
310  bool hasDotProd() const { return HasDotProd; }
311  bool hasCRC() const { return HasCRC; }
312  bool hasLSE() const { return HasLSE; }
313  bool hasRAS() const { return HasRAS; }
314  bool hasRDM() const { return HasRDM; }
315  bool hasSM4() const { return HasSM4; }
316  bool hasSHA3() const { return HasSHA3; }
317  bool hasSHA2() const { return HasSHA2; }
318  bool hasAES() const { return HasAES; }
319  bool balanceFPOps() const { return BalanceFPOps; }
322  }
326  bool isPaired128Slow() const { return Paired128IsSlow; }
327  bool isSTRQroSlow() const { return STRQroIsSlow; }
330  }
333  bool hasFuseAddress() const { return HasFuseAddress; }
334  bool hasFuseAES() const { return HasFuseAES; }
336  bool hasFuseCCSelect() const { return HasFuseCCSelect; }
337  bool hasFuseCryptoEOR() const { return HasFuseCryptoEOR; }
338  bool hasFuseLiterals() const { return HasFuseLiterals; }
339 
340  /// Return true if the CPU supports any kind of instruction fusion.
341  bool hasFusion() const {
345  }
346 
347  bool useEL1ForTP() const { return UseEL1ForTP; }
348  bool useEL2ForTP() const { return UseEL2ForTP; }
349  bool useEL3ForTP() const { return UseEL3ForTP; }
350 
351  bool useRSqrt() const { return UseRSqrt; }
353  unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
356  }
357  unsigned getCacheLineSize() const override { return CacheLineSize; }
358  unsigned getPrefetchDistance() const override { return PrefetchDistance; }
359  unsigned getMinPrefetchStride() const override { return MinPrefetchStride; }
360  unsigned getMaxPrefetchIterationsAhead() const override {
362  }
363  unsigned getPrefFunctionLogAlignment() const {
365  }
366  unsigned getPrefLoopLogAlignment() const { return PrefLoopLogAlignment; }
367 
368  unsigned getMaximumJumpTableSize() const { return MaxJumpTableSize; }
369 
370  unsigned getWideningBaseCost() const { return WideningBaseCost; }
371 
372  /// CPU has TBI (top byte of addresses is ignored during HW address
373  /// translation) and OS enables it.
374  bool supportsAddressTopByteIgnored() const;
375 
376  bool hasPerfMon() const { return HasPerfMon; }
377  bool hasFullFP16() const { return HasFullFP16; }
378  bool hasFP16FML() const { return HasFP16FML; }
379  bool hasSPE() const { return HasSPE; }
380  bool hasLSLFast() const { return HasLSLFast; }
381  bool hasSVE() const { return HasSVE; }
382  bool hasSVE2() const { return HasSVE2; }
383  bool hasRCPC() const { return HasRCPC; }
384  bool hasAggressiveFMA() const { return HasAggressiveFMA; }
385  bool hasAlternativeNZCV() const { return HasAlternativeNZCV; }
386  bool hasFRInt3264() const { return HasFRInt3264; }
387  bool hasSpecRestrict() const { return HasSpecRestrict; }
388  bool hasSSBS() const { return HasSSBS; }
389  bool hasSB() const { return HasSB; }
390  bool hasPredRes() const { return HasPredRes; }
391  bool hasCCDP() const { return HasCCDP; }
392  bool hasBTI() const { return HasBTI; }
393  bool hasRandGen() const { return HasRandGen; }
394  bool hasMTE() const { return HasMTE; }
395  bool hasTME() const { return HasTME; }
396  // Arm SVE2 extensions
397  bool hasSVE2AES() const { return HasSVE2AES; }
398  bool hasSVE2SM4() const { return HasSVE2SM4; }
399  bool hasSVE2SHA3() const { return HasSVE2SHA3; }
400  bool hasSVE2BitPerm() const { return HasSVE2BitPerm; }
401 
402  bool isLittleEndian() const { return IsLittle; }
403 
404  bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
405  bool isTargetIOS() const { return TargetTriple.isiOS(); }
406  bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
407  bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
408  bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
409  bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
410 
411  bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
412  bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
413  bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
414 
415  bool isTargetILP32() const { return TargetTriple.isArch32Bit(); }
416 
417  bool useAA() const override { return UseAA; }
418 
419  bool hasVH() const { return HasVH; }
420  bool hasPAN() const { return HasPAN; }
421  bool hasLOR() const { return HasLOR; }
422 
423  bool hasPsUAO() const { return HasPsUAO; }
424  bool hasPAN_RWV() const { return HasPAN_RWV; }
425  bool hasCCPP() const { return HasCCPP; }
426 
427  bool hasPA() const { return HasPA; }
428  bool hasJS() const { return HasJS; }
429  bool hasCCIDX() const { return HasCCIDX; }
430  bool hasComplxNum() const { return HasComplxNum; }
431 
432  bool hasNV() const { return HasNV; }
433  bool hasRASv8_4() const { return HasRASv8_4; }
434  bool hasMPAM() const { return HasMPAM; }
435  bool hasDIT() const { return HasDIT; }
436  bool hasTRACEV8_4() const { return HasTRACEV8_4; }
437  bool hasAM() const { return HasAM; }
438  bool hasSEL2() const { return HasSEL2; }
439  bool hasPMU() const { return HasPMU; }
440  bool hasTLB_RMI() const { return HasTLB_RMI; }
441  bool hasFMI() const { return HasFMI; }
442  bool hasRCPC_IMMO() const { return HasRCPC_IMMO; }
443 
444  bool addrSinkUsingGEPs() const override {
445  // Keeping GEPs inbounds is important for exploiting AArch64
446  // addressing-modes in ILP32 mode.
447  return useAA() || isTargetILP32();
448  }
449 
450  bool useSmallAddressing() const {
451  switch (TLInfo.getTargetMachine().getCodeModel()) {
452  case CodeModel::Kernel:
453  // Kernel is currently allowed only for Fuchsia targets,
454  // where it is the same as Small for almost all purposes.
455  case CodeModel::Small:
456  return true;
457  default:
458  return false;
459  }
460  }
461 
462  /// ParseSubtargetFeatures - Parses features string setting specified
463  /// subtarget options. Definition of function is auto generated by tblgen.
465 
466  /// ClassifyGlobalReference - Find the target operand flags that describe
467  /// how a global value should be referenced for the current subtarget.
468  unsigned ClassifyGlobalReference(const GlobalValue *GV,
469  const TargetMachine &TM) const;
470 
471  unsigned classifyGlobalFunctionReference(const GlobalValue *GV,
472  const TargetMachine &TM) const;
473 
475  unsigned NumRegionInstrs) const override;
476 
477  bool enableEarlyIfConversion() const override;
478 
479  std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const override;
480 
482  switch (CC) {
483  case CallingConv::C:
484  case CallingConv::Fast:
485  case CallingConv::Swift:
486  return isTargetWindows();
487  case CallingConv::Win64:
488  return true;
489  default:
490  return false;
491  }
492  }
493 
494  void mirFileLoaded(MachineFunction &MF) const override;
495 };
496 } // End llvm namespace
497 
498 #endif
const Triple & getTargetTriple() const
unsigned getMinPrefetchStride() const override
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:481
bool hasAlternativeNZCV() const
unsigned ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const
ClassifyGlobalReference - Find the target operand flags that describe how a global value should be re...
bool isMisaligned128StoreSlow() const
This class represents lattice values for constants.
Definition: AllocatorList.h:23
bool hasCustomCallingConv() const
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:623
bool predictableSelectIsExpensive() const
InstructionSelector * getInstructionSelector() const override
AArch64SelectionDAGInfo TSInfo
const AArch64FrameLowering * getFrameLowering() const override
bool isOSFuchsia() const
Definition: Triple.h:505
const CallLowering * getCallLowering() const override
bool isCallingConvWin64(CallingConv::ID CC) const
bool hasCustomCheapAsMoveHandling() const
void mirFileLoaded(MachineFunction &MF) const override
void overrideSchedPolicy(MachineSchedPolicy &Policy, unsigned NumRegionInstrs) const override
unsigned classifyGlobalFunctionReference(const GlobalValue *GV, const TargetMachine &TM) const
bool hasFuseArithmeticLogic() const
Holds all the information related to register banks.
bool hasFusion() const
Return true if the CPU supports any kind of instruction fusion.
bool hasArithmeticBccFusion() const
bool hasZeroCycleRegMove() const
bool force32BitJumpTables() const
std::unique_ptr< InstructionSelector > InstSelector
bool useAlternateSExtLoadCVTF32Pattern() const
const AArch64RegisterInfo * getRegisterInfo() const override
std::unique_ptr< LegalizerInfo > Legalizer
bool isArch32Bit() const
Test whether the architecture is 32-bit.
Definition: Triple.cpp:1296
bool useAA() const override
bool isiOS() const
Is this an iOS triple.
Definition: Triple.h:462
unsigned getWideningBaseCost() const
bool enableMachineScheduler() const override
bool isXRegisterReserved(size_t i) const
unsigned getPrefFunctionLogAlignment() const
bool supportsAddressTopByteIgnored() const
CPU has TBI (top byte of addresses is ignored during HW address translation) and OS enables it...
bool enableEarlyIfConversion() const override
unsigned getMinVectorRegisterBitWidth() const
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:538
const AArch64TargetLowering * getTargetLowering() const override
C - The default llvm calling convention, compatible with C.
Definition: CallingConv.h:34
const AArch64RegisterInfo & getRegisterInfo() const
getRegisterInfo - TargetInstrInfo is a superset of MRegister info.
bool requiresStrictAlign() const
unsigned getPrefLoopLogAlignment() const
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
Definition: Triple.h:628
bool hasExynosCheapAsMoveHandling() const
bool addrSinkUsingGEPs() const override
bool isXRaySupported() const override
bool any() const
any - Returns true if any bit is set.
Definition: BitVector.h:180
bool useSmallAddressing() const
Fast - This calling convention attempts to make calls as fast as possible (e.g.
Definition: CallingConv.h:42
std::unique_ptr< CallLowering > CallLoweringInfo
GlobalISel related APIs.
unsigned getMaxPrefetchIterationsAhead() const override
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:633
const TargetMachine & getTargetMachine() const
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
const AArch64SelectionDAGInfo * getSelectionDAGInfo() const override
bool hasArithmeticCbzFusion() const
size_type count() const
count - Returns the number of bits which are set.
Definition: BitVector.h:172
AArch64InstrInfo InstrInfo
unsigned getMaximumJumpTableSize() const
void ParseSubtargetFeatures(StringRef CPU, StringRef FS)
ParseSubtargetFeatures - Parses features string setting specified subtarget options.
bool isOSLinux() const
Tests whether the OS is Linux.
Definition: Triple.h:586
unsigned getCacheLineSize() const override
bool enablePostRAScheduler() const override
CodeModel::Model getCodeModel() const
Returns the code model.
unsigned getMaxInterleaveFactor() const
unsigned getNumXRegisterReserved() const
std::unique_ptr< RegisterBankInfo > RegBankInfo
Provides the logic to select generic machine instructions.
Define a generic scheduling policy for targets that don&#39;t provide their own MachineSchedStrategy.
std::unique_ptr< PBQPRAConstraint > getCustomPBQPConstraints() const override
AArch64Subtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const TargetMachine &TM, bool LittleEndian)
This constructor initializes the data members to match that of the specified triple.
const LegalizerInfo * getLegalizerInfo() const override
The C convention as implemented on Windows/x86-64 and AArch64.
Definition: CallingConv.h:158
unsigned getPrefetchDistance() const override
AArch64FrameLowering FrameLowering
ARMProcFamilyEnum getProcFamily() const
Returns ARM processor family.
bool hasZeroCycleZeroingFPWorkaround() const
Triple TargetTriple
TargetTriple - What processor and OS we&#39;re targeting.
ARMProcFamilyEnum ARMProcFamily
ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
bool hasZeroCycleZeroingFP() const
bool hasZeroCycleZeroingGP() const
bool isXRegCustomCalleeSaved(size_t i) const
const AArch64InstrInfo * getInstrInfo() const override
This file describes how to lower LLVM calls to machine code calls.
const RegisterBankInfo * getRegBankInfo() const override
bool isAndroid() const
Tests whether the target is Android.
Definition: Triple.h:661
Primary interface to the complete machine description for the target machine.
Definition: TargetMachine.h:65
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
AArch64TargetLowering TLInfo
unsigned getVectorInsertExtractBaseCost() const