LLVM  9.0.0svn
AArch64TargetMachine.cpp
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1 //===-- AArch64TargetMachine.cpp - Define TargetMachine for AArch64 -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //
10 //===----------------------------------------------------------------------===//
11 
12 #include "AArch64TargetMachine.h"
13 #include "AArch64.h"
14 #include "AArch64MacroFusion.h"
15 #include "AArch64Subtarget.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/Triple.h"
29 #include "llvm/CodeGen/Passes.h"
31 #include "llvm/IR/Attributes.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/Pass.h"
36 #include "llvm/Support/CodeGen.h"
41 #include "llvm/Transforms/Scalar.h"
42 #include <memory>
43 #include <string>
44 
45 using namespace llvm;
46 
47 static cl::opt<bool> EnableCCMP("aarch64-enable-ccmp",
48  cl::desc("Enable the CCMP formation pass"),
49  cl::init(true), cl::Hidden);
50 
51 static cl::opt<bool>
52  EnableCondBrTuning("aarch64-enable-cond-br-tune",
53  cl::desc("Enable the conditional branch tuning pass"),
54  cl::init(true), cl::Hidden);
55 
56 static cl::opt<bool> EnableMCR("aarch64-enable-mcr",
57  cl::desc("Enable the machine combiner pass"),
58  cl::init(true), cl::Hidden);
59 
60 static cl::opt<bool> EnableStPairSuppress("aarch64-enable-stp-suppress",
61  cl::desc("Suppress STP for AArch64"),
62  cl::init(true), cl::Hidden);
63 
65  "aarch64-enable-simd-scalar",
66  cl::desc("Enable use of AdvSIMD scalar integer instructions"),
67  cl::init(false), cl::Hidden);
68 
69 static cl::opt<bool>
70  EnablePromoteConstant("aarch64-enable-promote-const",
71  cl::desc("Enable the promote constant pass"),
72  cl::init(true), cl::Hidden);
73 
75  "aarch64-enable-collect-loh",
76  cl::desc("Enable the pass that emits the linker optimization hints (LOH)"),
77  cl::init(true), cl::Hidden);
78 
79 static cl::opt<bool>
80  EnableDeadRegisterElimination("aarch64-enable-dead-defs", cl::Hidden,
81  cl::desc("Enable the pass that removes dead"
82  " definitons and replaces stores to"
83  " them with stores to the zero"
84  " register"),
85  cl::init(true));
86 
88  "aarch64-enable-copyelim",
89  cl::desc("Enable the redundant copy elimination pass"), cl::init(true),
90  cl::Hidden);
91 
92 static cl::opt<bool> EnableLoadStoreOpt("aarch64-enable-ldst-opt",
93  cl::desc("Enable the load/store pair"
94  " optimization pass"),
95  cl::init(true), cl::Hidden);
96 
98  "aarch64-enable-atomic-cfg-tidy", cl::Hidden,
99  cl::desc("Run SimplifyCFG after expanding atomic operations"
100  " to make use of cmpxchg flow-based information"),
101  cl::init(true));
102 
103 static cl::opt<bool>
104 EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden,
105  cl::desc("Run early if-conversion"),
106  cl::init(true));
107 
108 static cl::opt<bool>
109  EnableCondOpt("aarch64-enable-condopt",
110  cl::desc("Enable the condition optimizer pass"),
111  cl::init(true), cl::Hidden);
112 
113 static cl::opt<bool>
114 EnableA53Fix835769("aarch64-fix-cortex-a53-835769", cl::Hidden,
115  cl::desc("Work around Cortex-A53 erratum 835769"),
116  cl::init(false));
117 
118 static cl::opt<bool>
119  EnableGEPOpt("aarch64-enable-gep-opt", cl::Hidden,
120  cl::desc("Enable optimizations on complex GEPs"),
121  cl::init(false));
122 
123 static cl::opt<bool>
124  BranchRelaxation("aarch64-enable-branch-relax", cl::Hidden, cl::init(true),
125  cl::desc("Relax out of range conditional branches"));
126 
128  "aarch64-enable-compress-jump-tables", cl::Hidden, cl::init(true),
129  cl::desc("Use smallest entry possible for jump tables"));
130 
131 // FIXME: Unify control over GlobalMerge.
133  EnableGlobalMerge("aarch64-enable-global-merge", cl::Hidden,
134  cl::desc("Enable the global merge pass"));
135 
136 static cl::opt<bool>
137  EnableLoopDataPrefetch("aarch64-enable-loop-data-prefetch", cl::Hidden,
138  cl::desc("Enable the loop data prefetch pass"),
139  cl::init(true));
140 
142  "aarch64-enable-global-isel-at-O", cl::Hidden,
143  cl::desc("Enable GlobalISel at or below an opt level (-1 to disable)"),
144  cl::init(0));
145 
146 static cl::opt<bool> EnableFalkorHWPFFix("aarch64-enable-falkor-hwpf-fix",
147  cl::init(true), cl::Hidden);
148 
149 static cl::opt<bool>
150  EnableBranchTargets("aarch64-enable-branch-targets", cl::Hidden,
151  cl::desc("Enable the AAcrh64 branch target pass"),
152  cl::init(true));
153 
154 extern "C" void LLVMInitializeAArch64Target() {
155  // Register the target.
159  auto PR = PassRegistry::getPassRegistry();
181 }
182 
183 //===----------------------------------------------------------------------===//
184 // AArch64 Lowering public interface.
185 //===----------------------------------------------------------------------===//
186 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
187  if (TT.isOSBinFormatMachO())
188  return llvm::make_unique<AArch64_MachoTargetObjectFile>();
189  if (TT.isOSBinFormatCOFF())
190  return llvm::make_unique<AArch64_COFFTargetObjectFile>();
191 
192  return llvm::make_unique<AArch64_ELFTargetObjectFile>();
193 }
194 
195 // Helper function to build a DataLayout string
196 static std::string computeDataLayout(const Triple &TT,
197  const MCTargetOptions &Options,
198  bool LittleEndian) {
199  if (Options.getABIName() == "ilp32")
200  return "e-m:e-p:32:32-i8:8-i16:16-i64:64-S128";
201  if (TT.isOSBinFormatMachO())
202  return "e-m:o-i64:64-i128:128-n32:64-S128";
203  if (TT.isOSBinFormatCOFF())
204  return "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128";
205  if (LittleEndian)
206  return "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128";
207  return "E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128";
208 }
209 
212  // AArch64 Darwin and Windows are always PIC.
213  if (TT.isOSDarwin() || TT.isOSWindows())
214  return Reloc::PIC_;
215  // On ELF platforms the default static relocation model has a smart enough
216  // linker to cope with referencing external symbols defined in a shared
217  // library. Hence DynamicNoPIC doesn't need to be promoted to PIC.
218  if (!RM.hasValue() || *RM == Reloc::DynamicNoPIC)
219  return Reloc::Static;
220  return *RM;
221 }
222 
223 static CodeModel::Model
225  bool JIT) {
226  if (CM) {
227  if (*CM != CodeModel::Small && *CM != CodeModel::Tiny &&
228  *CM != CodeModel::Large) {
229  if (!TT.isOSFuchsia())
231  "Only small, tiny and large code models are allowed on AArch64");
232  else if (*CM != CodeModel::Kernel)
233  report_fatal_error("Only small, tiny, kernel, and large code models "
234  "are allowed on AArch64");
235  } else if (*CM == CodeModel::Tiny && !TT.isOSBinFormatELF())
236  report_fatal_error("tiny code model is only supported on ELF");
237  return *CM;
238  }
239  // The default MCJIT memory managers make no guarantees about where they can
240  // find an executable page; JITed code needs to be able to refer to globals
241  // no matter how far away they are.
242  if (JIT)
243  return CodeModel::Large;
244  return CodeModel::Small;
245 }
246 
247 /// Create an AArch64 architecture model.
248 ///
250  StringRef CPU, StringRef FS,
251  const TargetOptions &Options,
254  CodeGenOpt::Level OL, bool JIT,
255  bool LittleEndian)
256  : LLVMTargetMachine(T,
257  computeDataLayout(TT, Options.MCOptions, LittleEndian),
258  TT, CPU, FS, Options, getEffectiveRelocModel(TT, RM),
259  getEffectiveAArch64CodeModel(TT, CM, JIT), OL),
260  TLOF(createTLOF(getTargetTriple())), isLittle(LittleEndian) {
261  initAsmInfo();
262 
263  if (TT.isOSBinFormatMachO()) {
264  this->Options.TrapUnreachable = true;
265  this->Options.NoTrapAfterNoreturn = true;
266  }
267 
268  if (getMCAsmInfo()->usesWindowsCFI()) {
269  // Unwinding can get confused if the last instruction in an
270  // exception-handling region (function, funclet, try block, etc.)
271  // is a call.
272  //
273  // FIXME: We could elide the trap if the next instruction would be in
274  // the same region anyway.
275  this->Options.TrapUnreachable = true;
276  }
277 
278  // Enable GlobalISel at or below EnableGlobalISelAt0.
279  if (getOptLevel() <= EnableGlobalISelAtO) {
280  setGlobalISel(true);
282  }
283 
284  // AArch64 supports the MachineOutliner.
285  setMachineOutliner(true);
286 
287  // AArch64 supports default outlining behaviour.
289 }
290 
292 
293 const AArch64Subtarget *
295  Attribute CPUAttr = F.getFnAttribute("target-cpu");
296  Attribute FSAttr = F.getFnAttribute("target-features");
297 
298  std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
299  ? CPUAttr.getValueAsString().str()
300  : TargetCPU;
301  std::string FS = !FSAttr.hasAttribute(Attribute::None)
302  ? FSAttr.getValueAsString().str()
303  : TargetFS;
304 
305  auto &I = SubtargetMap[CPU + FS];
306  if (!I) {
307  // This needs to be done before we create a new subtarget since any
308  // creation will depend on the TM and the code generation flags on the
309  // function that reside in TargetOptions.
311  I = llvm::make_unique<AArch64Subtarget>(TargetTriple, CPU, FS, *this,
312  isLittle);
313  }
314  return I.get();
315 }
316 
317 void AArch64leTargetMachine::anchor() { }
318 
320  const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
323  : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
324 
325 void AArch64beTargetMachine::anchor() { }
326 
328  const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
331  : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
332 
333 namespace {
334 
335 /// AArch64 Code Generator Pass Configuration Options.
336 class AArch64PassConfig : public TargetPassConfig {
337 public:
338  AArch64PassConfig(AArch64TargetMachine &TM, PassManagerBase &PM)
339  : TargetPassConfig(TM, PM) {
340  if (TM.getOptLevel() != CodeGenOpt::None)
341  substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
342  }
343 
344  AArch64TargetMachine &getAArch64TargetMachine() const {
345  return getTM<AArch64TargetMachine>();
346  }
347 
349  createMachineScheduler(MachineSchedContext *C) const override {
352  DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
353  DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
354  if (ST.hasFusion())
355  DAG->addMutation(createAArch64MacroFusionDAGMutation());
356  return DAG;
357  }
358 
360  createPostMachineScheduler(MachineSchedContext *C) const override {
362  if (ST.hasFusion()) {
363  // Run the Macro Fusion after RA again since literals are expanded from
364  // pseudos then (v. addPreSched2()).
367  return DAG;
368  }
369 
370  return nullptr;
371  }
372 
373  void addIRPasses() override;
374  bool addPreISel() override;
375  bool addInstSelector() override;
376  bool addIRTranslator() override;
377  void addPreLegalizeMachineIR() override;
378  bool addLegalizeMachineIR() override;
379  bool addRegBankSelect() override;
380  void addPreGlobalInstructionSelect() override;
381  bool addGlobalInstructionSelect() override;
382  bool addILPOpts() override;
383  void addPreRegAlloc() override;
384  void addPostRegAlloc() override;
385  void addPreSched2() override;
386  void addPreEmitPass() override;
387 
388  std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
389 };
390 
391 } // end anonymous namespace
392 
395  return TargetTransformInfo(AArch64TTIImpl(this, F));
396 }
397 
399  return new AArch64PassConfig(*this, PM);
400 }
401 
402 std::unique_ptr<CSEConfigBase> AArch64PassConfig::getCSEConfig() const {
403  return getStandardCSEConfigForOpt(TM->getOptLevel());
404 }
405 
406 void AArch64PassConfig::addIRPasses() {
407  // Always expand atomic operations, we don't deal with atomicrmw or cmpxchg
408  // ourselves.
409  addPass(createAtomicExpandPass());
410 
411  // Cmpxchg instructions are often used with a subsequent comparison to
412  // determine whether it succeeded. We can exploit existing control-flow in
413  // ldrex/strex loops to simplify this, but it needs tidying up.
414  if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
415  addPass(createCFGSimplificationPass(1, true, true, false, true));
416 
417  // Run LoopDataPrefetch
418  //
419  // Run this before LSR to remove the multiplies involved in computing the
420  // pointer values N iterations ahead.
421  if (TM->getOptLevel() != CodeGenOpt::None) {
423  addPass(createLoopDataPrefetchPass());
426  }
427 
429 
430  // Match interleaved memory accesses to ldN/stN intrinsics.
431  if (TM->getOptLevel() != CodeGenOpt::None) {
433  addPass(createInterleavedAccessPass());
434  }
435 
436  if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
437  // Call SeparateConstOffsetFromGEP pass to extract constants within indices
438  // and lower a GEP with multiple indices to either arithmetic operations or
439  // multiple GEPs with single index.
441  // Call EarlyCSE pass to find and remove subexpressions in the lowered
442  // result.
443  addPass(createEarlyCSEPass());
444  // Do loop invariant code motion in case part of the lowered result is
445  // invariant.
446  addPass(createLICMPass());
447  }
448 }
449 
450 // Pass Pipeline Configuration
451 bool AArch64PassConfig::addPreISel() {
452  // Run promote constant before global merge, so that the promoted constants
453  // get a chance to be merged
454  if (TM->getOptLevel() != CodeGenOpt::None && EnablePromoteConstant)
456  // FIXME: On AArch64, this depends on the type.
457  // Basically, the addressable offsets are up to 4095 * Ty.getSizeInBytes().
458  // and the offset has to be a multiple of the related size in bytes.
459  if ((TM->getOptLevel() != CodeGenOpt::None &&
461  EnableGlobalMerge == cl::BOU_TRUE) {
462  bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) &&
463  (EnableGlobalMerge == cl::BOU_UNSET);
464  addPass(createGlobalMergePass(TM, 4095, OnlyOptimizeForSize));
465  }
466 
467  return false;
468 }
469 
470 bool AArch64PassConfig::addInstSelector() {
471  addPass(createAArch64ISelDag(getAArch64TargetMachine(), getOptLevel()));
472 
473  // For ELF, cleanup any local-dynamic TLS accesses (i.e. combine as many
474  // references to _TLS_MODULE_BASE_ as possible.
475  if (TM->getTargetTriple().isOSBinFormatELF() &&
478 
479  return false;
480 }
481 
482 bool AArch64PassConfig::addIRTranslator() {
483  addPass(new IRTranslator());
484  return false;
485 }
486 
487 void AArch64PassConfig::addPreLegalizeMachineIR() {
489 }
490 
491 bool AArch64PassConfig::addLegalizeMachineIR() {
492  addPass(new Legalizer());
493  return false;
494 }
495 
496 bool AArch64PassConfig::addRegBankSelect() {
497  addPass(new RegBankSelect());
498  return false;
499 }
500 
501 void AArch64PassConfig::addPreGlobalInstructionSelect() {
502  // Workaround the deficiency of the fast register allocator.
503  if (TM->getOptLevel() == CodeGenOpt::None)
504  addPass(new Localizer());
505 }
506 
507 bool AArch64PassConfig::addGlobalInstructionSelect() {
508  addPass(new InstructionSelect());
509  return false;
510 }
511 
512 bool AArch64PassConfig::addILPOpts() {
513  if (EnableCondOpt)
515  if (EnableCCMP)
517  if (EnableMCR)
518  addPass(&MachineCombinerID);
519  if (EnableCondBrTuning)
520  addPass(createAArch64CondBrTuning());
522  addPass(&EarlyIfConverterID);
526  return true;
527 }
528 
529 void AArch64PassConfig::addPreRegAlloc() {
530  // Change dead register definitions to refer to the zero register.
531  if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
533 
534  // Use AdvSIMD scalar instructions whenever profitable.
535  if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar) {
536  addPass(createAArch64AdvSIMDScalar());
537  // The AdvSIMD pass may produce copies that can be rewritten to
538  // be register coaleascer friendly.
539  addPass(&PeepholeOptimizerID);
540  }
541 }
542 
543 void AArch64PassConfig::addPostRegAlloc() {
544  // Remove redundant copy instructions.
545  if (TM->getOptLevel() != CodeGenOpt::None && EnableRedundantCopyElimination)
547 
548  if (TM->getOptLevel() != CodeGenOpt::None && usingDefaultRegAlloc())
549  // Improve performance for some FP/SIMD code for A57.
551 }
552 
553 void AArch64PassConfig::addPreSched2() {
554  // Expand some pseudo instructions to allow proper scheduling.
556  // Use load/store pair instructions when possible.
557  if (TM->getOptLevel() != CodeGenOpt::None) {
558  if (EnableLoadStoreOpt)
560  }
561 
562  // The AArch64SpeculationHardeningPass destroys dominator tree and natural
563  // loop info, which is needed for the FalkorHWPFFixPass and also later on.
564  // Therefore, run the AArch64SpeculationHardeningPass before the
565  // FalkorHWPFFixPass to avoid recomputing dominator tree and natural loop
566  // info.
568 
569  if (TM->getOptLevel() != CodeGenOpt::None) {
571  addPass(createFalkorHWPFFixPass());
572  }
573 }
574 
575 void AArch64PassConfig::addPreEmitPass() {
576  // Machine Block Placement might have created new opportunities when run
577  // at O3, where the Tail Duplication Threshold is set to 4 instructions.
578  // Run the load/store optimizer once more.
579  if (TM->getOptLevel() >= CodeGenOpt::Aggressive && EnableLoadStoreOpt)
581 
582  if (EnableA53Fix835769)
583  addPass(createAArch64A53Fix835769());
584  // Relax conditional branch instructions if they're otherwise out of
585  // range of their destination.
586  if (BranchRelaxation)
587  addPass(&BranchRelaxationPassID);
588 
591 
592  if (TM->getOptLevel() != CodeGenOpt::None && EnableCompressJumpTables)
594 
595  if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH &&
596  TM->getTargetTriple().isOSBinFormatMachO())
597  addPass(createAArch64CollectLOHPass());
598 }
uint64_t CallInst * C
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:476
char & MachineCombinerID
This pass performs instruction combining using trace metrics to estimate critical-path and resource d...
bool usesWindowsCFI() const
Definition: MCAsmInfo.h:583
Target & getTheAArch64beTarget()
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:218
void initializeAArch64A53Fix835769Pass(PassRegistry &)
AArch64beTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
FunctionPass * createFalkorMarkStridedAccessesPass()
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:614
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with...
Definition: TargetMachine.h:84
void initializeAArch64LoadStoreOptPass(PassRegistry &)
Target & getTheAArch64leTarget()
This pass implements the localization mechanism described at the top of this file.
Definition: Localizer.h:38
static cl::opt< bool > EnableCompressJumpTables("aarch64-enable-compress-jump-tables", cl::Hidden, cl::init(true), cl::desc("Use smallest entry possible for jump tables"))
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions...
ScheduleDAGMI * createGenericSchedPostRA(MachineSchedContext *C)
Create a generic scheduler with no vreg liveness or DAG mutation passes.
Pass * createGlobalMergePass(const TargetMachine *TM, unsigned MaximalOffset, bool OnlyOptimizeForSize=false, bool MergeExternalByDefault=false)
GlobalMerge - This pass merges internal (by default) globals into structs to enable reuse of a base p...
char & BranchRelaxationPassID
BranchRelaxation - This pass replaces branches that need to jump further than is supported by a branc...
F(f)
bool isOSFuchsia() const
Definition: Triple.h:496
block Block Frequency true
FunctionPass * createAArch64ConditionalCompares()
void initializeAArch64RedundantCopyEliminationPass(PassRegistry &)
void setGlobalISelAbort(GlobalISelAbortMode Mode)
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
unsigned NoTrapAfterNoreturn
Do not emit a trap instruction for &#39;unreachable&#39; IR instructions behind noreturn calls, even if TrapUnreachable is true.
ModulePass * createAArch64PromoteConstantPass()
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
static CodeModel::Model getEffectiveAArch64CodeModel(const Triple &TT, Optional< CodeModel::Model > CM, bool JIT)
FunctionPass * createLoopDataPrefetchPass()
FunctionPass * createAArch64CollectLOHPass()
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
FunctionPass * createCFGSimplificationPass(unsigned Threshold=1, bool ForwardSwitchCond=false, bool ConvertSwitch=false, bool KeepLoops=true, bool SinkCommon=false, std::function< bool(const Function &)> Ftor=nullptr)
bool hasFusion() const
Return true if the CPU supports any kind of instruction fusion.
static cl::opt< bool > EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden, cl::desc("Run early if-conversion"), cl::init(true))
void resetTargetOptions(const Function &F) const
Reset the target options based on the function&#39;s attributes.
static cl::opt< bool > EnableMCR("aarch64-enable-mcr", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)
static cl::opt< bool > EnableLoopDataPrefetch("aarch64-enable-loop-data-prefetch", cl::Hidden, cl::desc("Enable the loop data prefetch pass"), cl::init(true))
void initializeLDTLSCleanupPass(PassRegistry &)
static cl::opt< bool > EnablePromoteConstant("aarch64-enable-promote-const", cl::desc("Enable the promote constant pass"), cl::init(true), cl::Hidden)
This file contains the simple types necessary to represent the attributes associated with functions a...
No attributes have been set.
Definition: Attributes.h:71
FunctionPass * createAArch64RedundantCopyEliminationPass()
Target & getTheARM64Target()
void initializeAArch64CollectLOHPass(PassRegistry &)
Target-Independent Code Generator Pass Configuration Options.
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
FunctionPass * createAArch64A57FPLoadBalancing()
static cl::opt< bool > EnableLoadStoreOpt("aarch64-enable-ldst-opt", cl::desc("Enable the load/store pair" " optimization pass"), cl::init(true), cl::Hidden)
RegisterTargetMachine - Helper template for registering a target machine implementation, for use in the target machine initialization function.
static cl::opt< bool > EnableCondBrTuning("aarch64-enable-cond-br-tune", cl::desc("Enable the conditional branch tuning pass"), cl::init(true), cl::Hidden)
FunctionPass * createInterleavedLoadCombinePass()
InterleavedLoadCombines Pass - This pass identifies interleaved loads and combines them into wide loa...
static cl::opt< cl::boolOrDefault > EnableGlobalMerge("aarch64-enable-global-merge", cl::Hidden, cl::desc("Enable the global merge pass"))
FunctionPass * createAArch64CleanupLocalDynamicTLSPass()
static cl::opt< bool > EnableCollectLOH("aarch64-enable-collect-loh", cl::desc("Enable the pass that emits the linker optimization hints (LOH)"), cl::init(true), cl::Hidden)
void initializeAArch64SpeculationHardeningPass(PassRegistry &)
ScheduleDAGMILive * createGenericSchedLive(MachineSchedContext *C)
Create the standard converging machine scheduler.
static cl::opt< bool > EnableAdvSIMDScalar("aarch64-enable-simd-scalar", cl::desc("Enable use of AdvSIMD scalar integer instructions"), cl::init(false), cl::Hidden)
FunctionPass * createAArch64LoadStoreOptimizationPass()
createAArch64LoadStoreOptimizationPass - returns an instance of the load / store optimization pass...
AArch64TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT, bool IsLittleEndian)
Create an AArch64 architecture model.
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:529
void initializeAArch64A57FPLoadBalancingPass(PassRegistry &)
std::unique_ptr< CSEConfigBase > getStandardCSEConfigForOpt(CodeGenOpt::Level Level)
Definition: CSEInfo.cpp:65
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:427
bool hasAttribute(AttrKind Val) const
Return true if the attribute is present.
Definition: Attributes.cpp:201
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
void initializeAArch64PromoteConstantPass(PassRegistry &)
void initializeAArch64ExpandPseudoPass(PassRegistry &)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Definition: RegBankSelect.h:90
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
Definition: Triple.h:619
void LLVMInitializeAArch64Target()
FunctionPass * createInterleavedAccessPass()
InterleavedAccess Pass - This pass identifies and matches interleaved memory accesses to target speci...
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
static cl::opt< bool > EnableBranchTargets("aarch64-enable-branch-targets", cl::Hidden, cl::desc("Enable the AAcrh64 branch target pass"), cl::init(true))
Pass * createLICMPass()
Definition: LICM.cpp:303
FunctionPass * createAArch64AdvSIMDScalar()
const AArch64Subtarget * getSubtargetImpl() const =delete
This class describes a target machine that is implemented with the LLVM target-independent code gener...
std::unique_ptr< ScheduleDAGMutation > createAArch64MacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createAArch64MacroFusionDAGMutation()); to AArch64PassConf...
void setMachineOutliner(bool Enable)
std::unique_ptr< ScheduleDAGMutation > createStoreClusterDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:624
This file a TargetTransformInfo::Concept conforming object specific to the AArch64 target machine...
void setSupportsDefaultOutlining(bool Enable)
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
static cl::opt< bool > EnableRedundantCopyElimination("aarch64-enable-copyelim", cl::desc("Enable the redundant copy elimination pass"), cl::init(true), cl::Hidden)
void initializeFalkorMarkStridedAccessesLegacyPass(PassRegistry &)
char & PostRASchedulerID
createPostRAScheduler - This pass performs post register allocation scheduling.
static cl::opt< bool > EnableA53Fix835769("aarch64-fix-cortex-a53-835769", cl::Hidden, cl::desc("Work around Cortex-A53 erratum 835769"), cl::init(false))
static cl::opt< bool > EnableDeadRegisterElimination("aarch64-enable-dead-defs", cl::Hidden, cl::desc("Enable the pass that removes dead" " definitons and replaces stores to" " them with stores to the zero" " register"), cl::init(true))
std::unique_ptr< ScheduleDAGMutation > createLoadClusterDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
static cl::opt< bool > EnableGEPOpt("aarch64-enable-gep-opt", cl::Hidden, cl::desc("Enable optimizations on complex GEPs"), cl::init(false))
AArch64leTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
static cl::opt< int > EnableGlobalISelAtO("aarch64-enable-global-isel-at-O", cl::Hidden, cl::desc("Enable GlobalISel at or below an opt level (-1 to disable)"), cl::init(0))
FunctionPass * createAArch64ExpandPseudoPass()
Returns an instance of the pseudo instruction expansion pass.
FunctionPass * createAArch64SpeculationHardeningPass()
Returns an instance of the pseudo instruction expansion pass.
static cl::opt< bool > EnableCondOpt("aarch64-enable-condopt", cl::desc("Enable the condition optimizer pass"), cl::init(true), cl::Hidden)
void initializeFalkorHWPFFixPass(PassRegistry &)
static cl::opt< bool > EnableAtomicTidy("aarch64-enable-atomic-cfg-tidy", cl::Hidden, cl::desc("Run SimplifyCFG after expanding atomic operations" " to make use of cmpxchg flow-based information"), cl::init(true))
FunctionPass * createAArch64A53Fix835769()
This pass is responsible for selecting generic machine instructions to target-specific instructions...
FunctionPass * createSeparateConstOffsetFromGEPPass(bool LowerGEP=false)
static std::unique_ptr< TargetLoweringObjectFile > createTLOF(const Triple &TT)
Target - Wrapper for Target specific information.
void initializeAArch64PreLegalizerCombinerPass(PassRegistry &)
char & PeepholeOptimizerID
PeepholeOptimizer - This pass performs peephole optimizations - like extension and comparison elimina...
static cl::opt< bool > EnableFalkorHWPFFix("aarch64-enable-falkor-hwpf-fix", cl::init(true), cl::Hidden)
FunctionPass * createAArch64ConditionOptimizerPass()
void initializeAArch64BranchTargetsPass(PassRegistry &)
std::string TargetCPU
Definition: TargetMachine.h:85
FunctionPass * createAArch64ISelDag(AArch64TargetMachine &TM, CodeGenOpt::Level OptLevel)
createAArch64ISelDag - This pass converts a legalized DAG into a AArch64-specific DAG...
A ScheduleDAG for scheduling lists of MachineInstr.
static std::string computeDataLayout(const Triple &TT, const MCTargetOptions &Options, bool LittleEndian)
bool hasValue() const
Definition: Optional.h:259
void initializeAArch64ConditionOptimizerPass(PassRegistry &)
StringRef getABIName() const
getABIName - If this returns a non-empty string this represents the textual name of the ABI that we w...
char & PostMachineSchedulerID
PostMachineScheduler - This pass schedules machine instructions postRA.
StringMap< std::unique_ptr< AArch64Subtarget > > SubtargetMap
StringRef getValueAsString() const
Return the attribute&#39;s value as a string.
Definition: Attributes.cpp:194
FunctionPass * createAArch64StorePairSuppressPass()
FunctionPass * createAArch64CondBrTuning()
TargetOptions Options
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
#define I(x, y, z)
Definition: MD5.cpp:58
void setGlobalISel(bool Enable)
FunctionPass * createFalkorHWPFFixPass()
FunctionPass * createAArch64BranchTargetsPass()
static cl::opt< bool > EnableCCMP("aarch64-enable-ccmp", cl::desc("Enable the CCMP formation pass"), cl::init(true), cl::Hidden)
void initializeAArch64ConditionalComparesPass(PassRegistry &)
FunctionPass * createAArch64PreLegalizeCombiner()
std::string TargetFS
Definition: TargetMachine.h:86
void initializeAArch64CompressJumpTablesPass(PassRegistry &)
This file declares the IRTranslator pass.
FunctionPass * createAArch64SIMDInstrOptPass()
Returns an instance of the high cost ASIMD instruction replacement optimization pass.
void initializeAArch64DeadRegisterDefinitionsPass(PassRegistry &)
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.h:330
FunctionPass * createEarlyCSEPass(bool UseMemorySSA=false)
Definition: EarlyCSE.cpp:1358
FunctionPass * createAArch64DeadRegisterDefinitions()
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
unsigned TrapUnreachable
Emit target-specific trap instruction for &#39;unreachable&#39; IR instructions.
This pass exposes codegen information to IR-level passes.
TargetTransformInfo getTargetTransformInfo(const Function &F) override
Get a TargetTransformInfo implementation for the target.
static cl::opt< bool > BranchRelaxation("aarch64-enable-branch-relax", cl::Hidden, cl::init(true), cl::desc("Relax out of range conditional branches"))
FunctionPass * createAtomicExpandPass()
static cl::opt< bool > EnableStPairSuppress("aarch64-enable-stp-suppress", cl::desc("Suppress STP for AArch64"), cl::init(true), cl::Hidden)
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
Definition: GlobalISel.cpp:18
void initializeAArch64SIMDInstrOptPass(PassRegistry &)
void initializeAArch64AdvSIMDScalarPass(PassRegistry &)
FunctionPass * createAArch64CompressJumpTablesPass()
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Add a postprocessing step to the DAG builder.
void initializeAArch64StorePairSuppressPass(PassRegistry &)