LLVM  10.0.0svn
AArch64TargetMachine.cpp
Go to the documentation of this file.
1 //===-- AArch64TargetMachine.cpp - Define TargetMachine for AArch64 -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //
10 //===----------------------------------------------------------------------===//
11 
12 #include "AArch64TargetMachine.h"
13 #include "AArch64.h"
14 #include "AArch64MacroFusion.h"
15 #include "AArch64Subtarget.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/Triple.h"
30 #include "llvm/CodeGen/Passes.h"
32 #include "llvm/IR/Attributes.h"
33 #include "llvm/IR/Function.h"
34 #include "llvm/MC/MCAsmInfo.h"
36 #include "llvm/Pass.h"
37 #include "llvm/Support/CodeGen.h"
42 #include "llvm/Transforms/Scalar.h"
43 #include <memory>
44 #include <string>
45 
46 using namespace llvm;
47 
48 static cl::opt<bool> EnableCCMP("aarch64-enable-ccmp",
49  cl::desc("Enable the CCMP formation pass"),
50  cl::init(true), cl::Hidden);
51 
52 static cl::opt<bool>
53  EnableCondBrTuning("aarch64-enable-cond-br-tune",
54  cl::desc("Enable the conditional branch tuning pass"),
55  cl::init(true), cl::Hidden);
56 
57 static cl::opt<bool> EnableMCR("aarch64-enable-mcr",
58  cl::desc("Enable the machine combiner pass"),
59  cl::init(true), cl::Hidden);
60 
61 static cl::opt<bool> EnableStPairSuppress("aarch64-enable-stp-suppress",
62  cl::desc("Suppress STP for AArch64"),
63  cl::init(true), cl::Hidden);
64 
66  "aarch64-enable-simd-scalar",
67  cl::desc("Enable use of AdvSIMD scalar integer instructions"),
68  cl::init(false), cl::Hidden);
69 
70 static cl::opt<bool>
71  EnablePromoteConstant("aarch64-enable-promote-const",
72  cl::desc("Enable the promote constant pass"),
73  cl::init(true), cl::Hidden);
74 
76  "aarch64-enable-collect-loh",
77  cl::desc("Enable the pass that emits the linker optimization hints (LOH)"),
78  cl::init(true), cl::Hidden);
79 
80 static cl::opt<bool>
81  EnableDeadRegisterElimination("aarch64-enable-dead-defs", cl::Hidden,
82  cl::desc("Enable the pass that removes dead"
83  " definitons and replaces stores to"
84  " them with stores to the zero"
85  " register"),
86  cl::init(true));
87 
89  "aarch64-enable-copyelim",
90  cl::desc("Enable the redundant copy elimination pass"), cl::init(true),
91  cl::Hidden);
92 
93 static cl::opt<bool> EnableLoadStoreOpt("aarch64-enable-ldst-opt",
94  cl::desc("Enable the load/store pair"
95  " optimization pass"),
96  cl::init(true), cl::Hidden);
97 
99  "aarch64-enable-atomic-cfg-tidy", cl::Hidden,
100  cl::desc("Run SimplifyCFG after expanding atomic operations"
101  " to make use of cmpxchg flow-based information"),
102  cl::init(true));
103 
104 static cl::opt<bool>
105 EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden,
106  cl::desc("Run early if-conversion"),
107  cl::init(true));
108 
109 static cl::opt<bool>
110  EnableCondOpt("aarch64-enable-condopt",
111  cl::desc("Enable the condition optimizer pass"),
112  cl::init(true), cl::Hidden);
113 
114 static cl::opt<bool>
115 EnableA53Fix835769("aarch64-fix-cortex-a53-835769", cl::Hidden,
116  cl::desc("Work around Cortex-A53 erratum 835769"),
117  cl::init(false));
118 
119 static cl::opt<bool>
120  EnableGEPOpt("aarch64-enable-gep-opt", cl::Hidden,
121  cl::desc("Enable optimizations on complex GEPs"),
122  cl::init(false));
123 
124 static cl::opt<bool>
125  BranchRelaxation("aarch64-enable-branch-relax", cl::Hidden, cl::init(true),
126  cl::desc("Relax out of range conditional branches"));
127 
129  "aarch64-enable-compress-jump-tables", cl::Hidden, cl::init(true),
130  cl::desc("Use smallest entry possible for jump tables"));
131 
132 // FIXME: Unify control over GlobalMerge.
134  EnableGlobalMerge("aarch64-enable-global-merge", cl::Hidden,
135  cl::desc("Enable the global merge pass"));
136 
137 static cl::opt<bool>
138  EnableLoopDataPrefetch("aarch64-enable-loop-data-prefetch", cl::Hidden,
139  cl::desc("Enable the loop data prefetch pass"),
140  cl::init(true));
141 
143  "aarch64-enable-global-isel-at-O", cl::Hidden,
144  cl::desc("Enable GlobalISel at or below an opt level (-1 to disable)"),
145  cl::init(0));
146 
147 static cl::opt<bool> EnableFalkorHWPFFix("aarch64-enable-falkor-hwpf-fix",
148  cl::init(true), cl::Hidden);
149 
150 static cl::opt<bool>
151  EnableBranchTargets("aarch64-enable-branch-targets", cl::Hidden,
152  cl::desc("Enable the AAcrh64 branch target pass"),
153  cl::init(true));
154 
155 extern "C" void LLVMInitializeAArch64Target() {
156  // Register the target.
160  auto PR = PassRegistry::getPassRegistry();
183 }
184 
185 //===----------------------------------------------------------------------===//
186 // AArch64 Lowering public interface.
187 //===----------------------------------------------------------------------===//
188 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
189  if (TT.isOSBinFormatMachO())
190  return std::make_unique<AArch64_MachoTargetObjectFile>();
191  if (TT.isOSBinFormatCOFF())
192  return std::make_unique<AArch64_COFFTargetObjectFile>();
193 
194  return std::make_unique<AArch64_ELFTargetObjectFile>();
195 }
196 
197 // Helper function to build a DataLayout string
198 static std::string computeDataLayout(const Triple &TT,
199  const MCTargetOptions &Options,
200  bool LittleEndian) {
201  if (Options.getABIName() == "ilp32")
202  return "e-m:e-p:32:32-i8:8-i16:16-i64:64-S128";
203  if (TT.isOSBinFormatMachO())
204  return "e-m:o-i64:64-i128:128-n32:64-S128";
205  if (TT.isOSBinFormatCOFF())
206  return "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128";
207  if (LittleEndian)
208  return "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128";
209  return "E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128";
210 }
211 
214  // AArch64 Darwin and Windows are always PIC.
215  if (TT.isOSDarwin() || TT.isOSWindows())
216  return Reloc::PIC_;
217  // On ELF platforms the default static relocation model has a smart enough
218  // linker to cope with referencing external symbols defined in a shared
219  // library. Hence DynamicNoPIC doesn't need to be promoted to PIC.
220  if (!RM.hasValue() || *RM == Reloc::DynamicNoPIC)
221  return Reloc::Static;
222  return *RM;
223 }
224 
225 static CodeModel::Model
227  bool JIT) {
228  if (CM) {
229  if (*CM != CodeModel::Small && *CM != CodeModel::Tiny &&
230  *CM != CodeModel::Large) {
231  if (!TT.isOSFuchsia())
233  "Only small, tiny and large code models are allowed on AArch64");
234  else if (*CM != CodeModel::Kernel)
235  report_fatal_error("Only small, tiny, kernel, and large code models "
236  "are allowed on AArch64");
237  } else if (*CM == CodeModel::Tiny && !TT.isOSBinFormatELF())
238  report_fatal_error("tiny code model is only supported on ELF");
239  return *CM;
240  }
241  // The default MCJIT memory managers make no guarantees about where they can
242  // find an executable page; JITed code needs to be able to refer to globals
243  // no matter how far away they are.
244  if (JIT)
245  return CodeModel::Large;
246  return CodeModel::Small;
247 }
248 
249 /// Create an AArch64 architecture model.
250 ///
252  StringRef CPU, StringRef FS,
253  const TargetOptions &Options,
256  CodeGenOpt::Level OL, bool JIT,
257  bool LittleEndian)
258  : LLVMTargetMachine(T,
259  computeDataLayout(TT, Options.MCOptions, LittleEndian),
260  TT, CPU, FS, Options, getEffectiveRelocModel(TT, RM),
261  getEffectiveAArch64CodeModel(TT, CM, JIT), OL),
262  TLOF(createTLOF(getTargetTriple())), isLittle(LittleEndian) {
263  initAsmInfo();
264 
265  if (TT.isOSBinFormatMachO()) {
266  this->Options.TrapUnreachable = true;
267  this->Options.NoTrapAfterNoreturn = true;
268  }
269 
270  if (getMCAsmInfo()->usesWindowsCFI()) {
271  // Unwinding can get confused if the last instruction in an
272  // exception-handling region (function, funclet, try block, etc.)
273  // is a call.
274  //
275  // FIXME: We could elide the trap if the next instruction would be in
276  // the same region anyway.
277  this->Options.TrapUnreachable = true;
278  }
279 
280  // Enable GlobalISel at or below EnableGlobalISelAt0.
281  if (getOptLevel() <= EnableGlobalISelAtO) {
282  setGlobalISel(true);
284  }
285 
286  // AArch64 supports the MachineOutliner.
287  setMachineOutliner(true);
288 
289  // AArch64 supports default outlining behaviour.
291 }
292 
294 
295 const AArch64Subtarget *
297  Attribute CPUAttr = F.getFnAttribute("target-cpu");
298  Attribute FSAttr = F.getFnAttribute("target-features");
299 
300  std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
301  ? CPUAttr.getValueAsString().str()
302  : TargetCPU;
303  std::string FS = !FSAttr.hasAttribute(Attribute::None)
304  ? FSAttr.getValueAsString().str()
305  : TargetFS;
306 
307  auto &I = SubtargetMap[CPU + FS];
308  if (!I) {
309  // This needs to be done before we create a new subtarget since any
310  // creation will depend on the TM and the code generation flags on the
311  // function that reside in TargetOptions.
313  I = std::make_unique<AArch64Subtarget>(TargetTriple, CPU, FS, *this,
314  isLittle);
315  }
316  return I.get();
317 }
318 
319 void AArch64leTargetMachine::anchor() { }
320 
322  const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
325  : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
326 
327 void AArch64beTargetMachine::anchor() { }
328 
330  const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
333  : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
334 
335 namespace {
336 
337 /// AArch64 Code Generator Pass Configuration Options.
338 class AArch64PassConfig : public TargetPassConfig {
339 public:
340  AArch64PassConfig(AArch64TargetMachine &TM, PassManagerBase &PM)
341  : TargetPassConfig(TM, PM) {
342  if (TM.getOptLevel() != CodeGenOpt::None)
343  substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
344  }
345 
346  AArch64TargetMachine &getAArch64TargetMachine() const {
347  return getTM<AArch64TargetMachine>();
348  }
349 
351  createMachineScheduler(MachineSchedContext *C) const override {
354  DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
355  DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
356  if (ST.hasFusion())
357  DAG->addMutation(createAArch64MacroFusionDAGMutation());
358  return DAG;
359  }
360 
362  createPostMachineScheduler(MachineSchedContext *C) const override {
364  if (ST.hasFusion()) {
365  // Run the Macro Fusion after RA again since literals are expanded from
366  // pseudos then (v. addPreSched2()).
369  return DAG;
370  }
371 
372  return nullptr;
373  }
374 
375  void addIRPasses() override;
376  bool addPreISel() override;
377  bool addInstSelector() override;
378  bool addIRTranslator() override;
379  void addPreLegalizeMachineIR() override;
380  bool addLegalizeMachineIR() override;
381  bool addRegBankSelect() override;
382  void addPreGlobalInstructionSelect() override;
383  bool addGlobalInstructionSelect() override;
384  bool addILPOpts() override;
385  void addPreRegAlloc() override;
386  void addPostRegAlloc() override;
387  void addPreSched2() override;
388  void addPreEmitPass() override;
389 
390  std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
391 };
392 
393 } // end anonymous namespace
394 
397  return TargetTransformInfo(AArch64TTIImpl(this, F));
398 }
399 
401  return new AArch64PassConfig(*this, PM);
402 }
403 
404 std::unique_ptr<CSEConfigBase> AArch64PassConfig::getCSEConfig() const {
405  return getStandardCSEConfigForOpt(TM->getOptLevel());
406 }
407 
408 void AArch64PassConfig::addIRPasses() {
409  // Always expand atomic operations, we don't deal with atomicrmw or cmpxchg
410  // ourselves.
411  addPass(createAtomicExpandPass());
412 
413  // Cmpxchg instructions are often used with a subsequent comparison to
414  // determine whether it succeeded. We can exploit existing control-flow in
415  // ldrex/strex loops to simplify this, but it needs tidying up.
416  if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
417  addPass(createCFGSimplificationPass(1, true, true, false, true));
418 
419  // Run LoopDataPrefetch
420  //
421  // Run this before LSR to remove the multiplies involved in computing the
422  // pointer values N iterations ahead.
423  if (TM->getOptLevel() != CodeGenOpt::None) {
425  addPass(createLoopDataPrefetchPass());
428  }
429 
431 
432  // Match interleaved memory accesses to ldN/stN intrinsics.
433  if (TM->getOptLevel() != CodeGenOpt::None) {
435  addPass(createInterleavedAccessPass());
436  }
437 
438  if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
439  // Call SeparateConstOffsetFromGEP pass to extract constants within indices
440  // and lower a GEP with multiple indices to either arithmetic operations or
441  // multiple GEPs with single index.
443  // Call EarlyCSE pass to find and remove subexpressions in the lowered
444  // result.
445  addPass(createEarlyCSEPass());
446  // Do loop invariant code motion in case part of the lowered result is
447  // invariant.
448  addPass(createLICMPass());
449  }
450 
451  addPass(createAArch64StackTaggingPass(/* MergeInit = */ TM->getOptLevel() !=
453 }
454 
455 // Pass Pipeline Configuration
456 bool AArch64PassConfig::addPreISel() {
457  // Run promote constant before global merge, so that the promoted constants
458  // get a chance to be merged
459  if (TM->getOptLevel() != CodeGenOpt::None && EnablePromoteConstant)
461  // FIXME: On AArch64, this depends on the type.
462  // Basically, the addressable offsets are up to 4095 * Ty.getSizeInBytes().
463  // and the offset has to be a multiple of the related size in bytes.
464  if ((TM->getOptLevel() != CodeGenOpt::None &&
466  EnableGlobalMerge == cl::BOU_TRUE) {
467  bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) &&
468  (EnableGlobalMerge == cl::BOU_UNSET);
469 
470  // Merging of extern globals is enabled by default on non-Mach-O as we
471  // expect it to be generally either beneficial or harmless. On Mach-O it
472  // is disabled as we emit the .subsections_via_symbols directive which
473  // means that merging extern globals is not safe.
474  bool MergeExternalByDefault = !TM->getTargetTriple().isOSBinFormatMachO();
475 
476  // FIXME: extern global merging is only enabled when we optimise for size
477  // because there are some regressions with it also enabled for performance.
478  if (!OnlyOptimizeForSize)
479  MergeExternalByDefault = false;
480 
481  addPass(createGlobalMergePass(TM, 4095, OnlyOptimizeForSize,
482  MergeExternalByDefault));
483  }
484 
485  return false;
486 }
487 
488 bool AArch64PassConfig::addInstSelector() {
489  addPass(createAArch64ISelDag(getAArch64TargetMachine(), getOptLevel()));
490 
491  // For ELF, cleanup any local-dynamic TLS accesses (i.e. combine as many
492  // references to _TLS_MODULE_BASE_ as possible.
493  if (TM->getTargetTriple().isOSBinFormatELF() &&
496 
497  return false;
498 }
499 
500 bool AArch64PassConfig::addIRTranslator() {
501  addPass(new IRTranslator());
502  return false;
503 }
504 
505 void AArch64PassConfig::addPreLegalizeMachineIR() {
507 }
508 
509 bool AArch64PassConfig::addLegalizeMachineIR() {
510  addPass(new Legalizer());
511  return false;
512 }
513 
514 bool AArch64PassConfig::addRegBankSelect() {
515  addPass(new RegBankSelect());
516  return false;
517 }
518 
519 void AArch64PassConfig::addPreGlobalInstructionSelect() {
520  // Workaround the deficiency of the fast register allocator.
521  if (TM->getOptLevel() == CodeGenOpt::None)
522  addPass(new Localizer());
523 }
524 
525 bool AArch64PassConfig::addGlobalInstructionSelect() {
526  addPass(new InstructionSelect());
527  return false;
528 }
529 
530 bool AArch64PassConfig::addILPOpts() {
531  if (EnableCondOpt)
533  if (EnableCCMP)
535  if (EnableMCR)
536  addPass(&MachineCombinerID);
537  if (EnableCondBrTuning)
538  addPass(createAArch64CondBrTuning());
540  addPass(&EarlyIfConverterID);
544  return true;
545 }
546 
547 void AArch64PassConfig::addPreRegAlloc() {
548  // Change dead register definitions to refer to the zero register.
549  if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
551 
552  // Use AdvSIMD scalar instructions whenever profitable.
553  if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar) {
554  addPass(createAArch64AdvSIMDScalar());
555  // The AdvSIMD pass may produce copies that can be rewritten to
556  // be register coaleascer friendly.
557  addPass(&PeepholeOptimizerID);
558  }
559 }
560 
561 void AArch64PassConfig::addPostRegAlloc() {
562  // Remove redundant copy instructions.
563  if (TM->getOptLevel() != CodeGenOpt::None && EnableRedundantCopyElimination)
565 
566  if (TM->getOptLevel() != CodeGenOpt::None && usingDefaultRegAlloc())
567  // Improve performance for some FP/SIMD code for A57.
569 }
570 
571 void AArch64PassConfig::addPreSched2() {
572  // Expand some pseudo instructions to allow proper scheduling.
574  // Use load/store pair instructions when possible.
575  if (TM->getOptLevel() != CodeGenOpt::None) {
576  if (EnableLoadStoreOpt)
578  }
579 
580  // The AArch64SpeculationHardeningPass destroys dominator tree and natural
581  // loop info, which is needed for the FalkorHWPFFixPass and also later on.
582  // Therefore, run the AArch64SpeculationHardeningPass before the
583  // FalkorHWPFFixPass to avoid recomputing dominator tree and natural loop
584  // info.
586 
587  if (TM->getOptLevel() != CodeGenOpt::None) {
589  addPass(createFalkorHWPFFixPass());
590  }
591 }
592 
593 void AArch64PassConfig::addPreEmitPass() {
594  // Machine Block Placement might have created new opportunities when run
595  // at O3, where the Tail Duplication Threshold is set to 4 instructions.
596  // Run the load/store optimizer once more.
597  if (TM->getOptLevel() >= CodeGenOpt::Aggressive && EnableLoadStoreOpt)
599 
600  if (EnableA53Fix835769)
601  addPass(createAArch64A53Fix835769());
602  // Relax conditional branch instructions if they're otherwise out of
603  // range of their destination.
604  if (BranchRelaxation)
605  addPass(&BranchRelaxationPassID);
606 
609 
610  if (TM->getOptLevel() != CodeGenOpt::None && EnableCompressJumpTables)
612 
613  if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH &&
614  TM->getTargetTriple().isOSBinFormatMachO())
615  addPass(createAArch64CollectLOHPass());
616 }
uint64_t CallInst * C
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:481
char & MachineCombinerID
This pass performs instruction combining using trace metrics to estimate critical-path and resource d...
bool usesWindowsCFI() const
Definition: MCAsmInfo.h:590
Target & getTheAArch64beTarget()
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:218
void initializeAArch64A53Fix835769Pass(PassRegistry &)
AArch64beTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:139
This class represents lattice values for constants.
Definition: AllocatorList.h:23
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
FunctionPass * createFalkorMarkStridedAccessesPass()
bool isOSBinFormatELF() const
Tests whether the OS uses the ELF binary format.
Definition: Triple.h:623
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with...
Definition: TargetMachine.h:84
void initializeAArch64LoadStoreOptPass(PassRegistry &)
Target & getTheAArch64leTarget()
This pass implements the localization mechanism described at the top of this file.
Definition: Localizer.h:40
static cl::opt< bool > EnableCompressJumpTables("aarch64-enable-compress-jump-tables", cl::Hidden, cl::init(true), cl::desc("Use smallest entry possible for jump tables"))
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions...
ScheduleDAGMI * createGenericSchedPostRA(MachineSchedContext *C)
Create a generic scheduler with no vreg liveness or DAG mutation passes.
Pass * createGlobalMergePass(const TargetMachine *TM, unsigned MaximalOffset, bool OnlyOptimizeForSize=false, bool MergeExternalByDefault=false)
GlobalMerge - This pass merges internal (by default) globals into structs to enable reuse of a base p...
char & BranchRelaxationPassID
BranchRelaxation - This pass replaces branches that need to jump further than is supported by a branc...
F(f)
bool isOSFuchsia() const
Definition: Triple.h:505
block Block Frequency true
FunctionPass * createAArch64ConditionalCompares()
void initializeAArch64RedundantCopyEliminationPass(PassRegistry &)
void setGlobalISelAbort(GlobalISelAbortMode Mode)
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
unsigned NoTrapAfterNoreturn
Do not emit a trap instruction for &#39;unreachable&#39; IR instructions behind noreturn calls, even if TrapUnreachable is true.
ModulePass * createAArch64PromoteConstantPass()
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
static CodeModel::Model getEffectiveAArch64CodeModel(const Triple &TT, Optional< CodeModel::Model > CM, bool JIT)
FunctionPass * createLoopDataPrefetchPass()
FunctionPass * createAArch64CollectLOHPass()
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
FunctionPass * createCFGSimplificationPass(unsigned Threshold=1, bool ForwardSwitchCond=false, bool ConvertSwitch=false, bool KeepLoops=true, bool SinkCommon=false, std::function< bool(const Function &)> Ftor=nullptr)
bool hasFusion() const
Return true if the CPU supports any kind of instruction fusion.
static cl::opt< bool > EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden, cl::desc("Run early if-conversion"), cl::init(true))
void resetTargetOptions(const Function &F) const
Reset the target options based on the function&#39;s attributes.
static cl::opt< bool > EnableMCR("aarch64-enable-mcr", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)
static cl::opt< bool > EnableLoopDataPrefetch("aarch64-enable-loop-data-prefetch", cl::Hidden, cl::desc("Enable the loop data prefetch pass"), cl::init(true))
void initializeLDTLSCleanupPass(PassRegistry &)
FunctionPass * createAArch64StackTaggingPass(bool MergeInit)
static cl::opt< bool > EnablePromoteConstant("aarch64-enable-promote-const", cl::desc("Enable the promote constant pass"), cl::init(true), cl::Hidden)
This file contains the simple types necessary to represent the attributes associated with functions a...
No attributes have been set.
Definition: Attributes.h:72
FunctionPass * createAArch64RedundantCopyEliminationPass()
Target & getTheARM64Target()
void initializeAArch64CollectLOHPass(PassRegistry &)
Target-Independent Code Generator Pass Configuration Options.
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
FunctionPass * createAArch64A57FPLoadBalancing()
static cl::opt< bool > EnableLoadStoreOpt("aarch64-enable-ldst-opt", cl::desc("Enable the load/store pair" " optimization pass"), cl::init(true), cl::Hidden)
RegisterTargetMachine - Helper template for registering a target machine implementation, for use in the target machine initialization function.
static cl::opt< bool > EnableCondBrTuning("aarch64-enable-cond-br-tune", cl::desc("Enable the conditional branch tuning pass"), cl::init(true), cl::Hidden)
FunctionPass * createInterleavedLoadCombinePass()
InterleavedLoadCombines Pass - This pass identifies interleaved loads and combines them into wide loa...
static cl::opt< cl::boolOrDefault > EnableGlobalMerge("aarch64-enable-global-merge", cl::Hidden, cl::desc("Enable the global merge pass"))
FunctionPass * createAArch64CleanupLocalDynamicTLSPass()
static cl::opt< bool > EnableCollectLOH("aarch64-enable-collect-loh", cl::desc("Enable the pass that emits the linker optimization hints (LOH)"), cl::init(true), cl::Hidden)
void initializeAArch64SpeculationHardeningPass(PassRegistry &)
ScheduleDAGMILive * createGenericSchedLive(MachineSchedContext *C)
Create the standard converging machine scheduler.
static cl::opt< bool > EnableAdvSIMDScalar("aarch64-enable-simd-scalar", cl::desc("Enable use of AdvSIMD scalar integer instructions"), cl::init(false), cl::Hidden)
FunctionPass * createAArch64LoadStoreOptimizationPass()
createAArch64LoadStoreOptimizationPass - returns an instance of the load / store optimization pass...
AArch64TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT, bool IsLittleEndian)
Create an AArch64 architecture model.
bool isOSWindows() const
Tests whether the OS is Windows.
Definition: Triple.h:538
void initializeAArch64A57FPLoadBalancingPass(PassRegistry &)
std::unique_ptr< CSEConfigBase > getStandardCSEConfigForOpt(CodeGenOpt::Level Level)
Definition: CSEInfo.cpp:66
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:432
bool hasAttribute(AttrKind Val) const
Return true if the attribute is present.
Definition: Attributes.cpp:238
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
void initializeAArch64PromoteConstantPass(PassRegistry &)
void initializeAArch64ExpandPseudoPass(PassRegistry &)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Definition: RegBankSelect.h:90
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
Definition: Triple.h:628
void LLVMInitializeAArch64Target()
FunctionPass * createInterleavedAccessPass()
InterleavedAccess Pass - This pass identifies and matches interleaved memory accesses to target speci...
const MCAsmInfo * getMCAsmInfo() const
Return target specific asm information.
static cl::opt< bool > EnableBranchTargets("aarch64-enable-branch-targets", cl::Hidden, cl::desc("Enable the AAcrh64 branch target pass"), cl::init(true))
Pass * createLICMPass()
Definition: LICM.cpp:313
FunctionPass * createAArch64AdvSIMDScalar()
const AArch64Subtarget * getSubtargetImpl() const =delete
This class describes a target machine that is implemented with the LLVM target-independent code gener...
std::unique_ptr< ScheduleDAGMutation > createAArch64MacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createAArch64MacroFusionDAGMutation()); to AArch64PassConf...
void setMachineOutliner(bool Enable)
std::unique_ptr< ScheduleDAGMutation > createStoreClusterDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:633
This file a TargetTransformInfo::Concept conforming object specific to the AArch64 target machine...
void setSupportsDefaultOutlining(bool Enable)
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:43
static cl::opt< bool > EnableRedundantCopyElimination("aarch64-enable-copyelim", cl::desc("Enable the redundant copy elimination pass"), cl::init(true), cl::Hidden)
void initializeFalkorMarkStridedAccessesLegacyPass(PassRegistry &)
char & PostRASchedulerID
createPostRAScheduler - This pass performs post register allocation scheduling.
static cl::opt< bool > EnableA53Fix835769("aarch64-fix-cortex-a53-835769", cl::Hidden, cl::desc("Work around Cortex-A53 erratum 835769"), cl::init(false))
static cl::opt< bool > EnableDeadRegisterElimination("aarch64-enable-dead-defs", cl::Hidden, cl::desc("Enable the pass that removes dead" " definitons and replaces stores to" " them with stores to the zero" " register"), cl::init(true))
std::unique_ptr< ScheduleDAGMutation > createLoadClusterDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
static cl::opt< bool > EnableGEPOpt("aarch64-enable-gep-opt", cl::Hidden, cl::desc("Enable optimizations on complex GEPs"), cl::init(false))
AArch64leTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
static cl::opt< int > EnableGlobalISelAtO("aarch64-enable-global-isel-at-O", cl::Hidden, cl::desc("Enable GlobalISel at or below an opt level (-1 to disable)"), cl::init(0))
FunctionPass * createAArch64ExpandPseudoPass()
Returns an instance of the pseudo instruction expansion pass.
FunctionPass * createAArch64SpeculationHardeningPass()
Returns an instance of the pseudo instruction expansion pass.
static cl::opt< bool > EnableCondOpt("aarch64-enable-condopt", cl::desc("Enable the condition optimizer pass"), cl::init(true), cl::Hidden)
void initializeFalkorHWPFFixPass(PassRegistry &)
static cl::opt< bool > EnableAtomicTidy("aarch64-enable-atomic-cfg-tidy", cl::Hidden, cl::desc("Run SimplifyCFG after expanding atomic operations" " to make use of cmpxchg flow-based information"), cl::init(true))
FunctionPass * createAArch64A53Fix835769()
This pass is responsible for selecting generic machine instructions to target-specific instructions...
void initializeAArch64StackTaggingPass(PassRegistry &)
FunctionPass * createSeparateConstOffsetFromGEPPass(bool LowerGEP=false)
static std::unique_ptr< TargetLoweringObjectFile > createTLOF(const Triple &TT)
Target - Wrapper for Target specific information.
void initializeAArch64PreLegalizerCombinerPass(PassRegistry &)
char & PeepholeOptimizerID
PeepholeOptimizer - This pass performs peephole optimizations - like extension and comparison elimina...
static cl::opt< bool > EnableFalkorHWPFFix("aarch64-enable-falkor-hwpf-fix", cl::init(true), cl::Hidden)
FunctionPass * createAArch64ConditionOptimizerPass()
void initializeAArch64BranchTargetsPass(PassRegistry &)
std::string TargetCPU
Definition: TargetMachine.h:85
FunctionPass * createAArch64ISelDag(AArch64TargetMachine &TM, CodeGenOpt::Level OptLevel)
createAArch64ISelDag - This pass converts a legalized DAG into a AArch64-specific DAG...
A ScheduleDAG for scheduling lists of MachineInstr.
static std::string computeDataLayout(const Triple &TT, const MCTargetOptions &Options, bool LittleEndian)
bool hasValue() const
Definition: Optional.h:259
void initializeAArch64ConditionOptimizerPass(PassRegistry &)
StringRef getABIName() const
getABIName - If this returns a non-empty string this represents the textual name of the ABI that we w...
char & PostMachineSchedulerID
PostMachineScheduler - This pass schedules machine instructions postRA.
StringMap< std::unique_ptr< AArch64Subtarget > > SubtargetMap
StringRef getValueAsString() const
Return the attribute&#39;s value as a string.
Definition: Attributes.cpp:223
FunctionPass * createAArch64StorePairSuppressPass()
FunctionPass * createAArch64CondBrTuning()
TargetOptions Options
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
#define I(x, y, z)
Definition: MD5.cpp:58
void setGlobalISel(bool Enable)
FunctionPass * createFalkorHWPFFixPass()
FunctionPass * createAArch64BranchTargetsPass()
static cl::opt< bool > EnableCCMP("aarch64-enable-ccmp", cl::desc("Enable the CCMP formation pass"), cl::init(true), cl::Hidden)
void initializeAArch64ConditionalComparesPass(PassRegistry &)
FunctionPass * createAArch64PreLegalizeCombiner()
std::string TargetFS
Definition: TargetMachine.h:86
void initializeAArch64CompressJumpTablesPass(PassRegistry &)
This file declares the IRTranslator pass.
FunctionPass * createAArch64SIMDInstrOptPass()
Returns an instance of the high cost ASIMD instruction replacement optimization pass.
void initializeAArch64DeadRegisterDefinitionsPass(PassRegistry &)
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.h:333
FunctionPass * createEarlyCSEPass(bool UseMemorySSA=false)
Definition: EarlyCSE.cpp:1410
FunctionPass * createAArch64DeadRegisterDefinitions()
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:48
unsigned TrapUnreachable
Emit target-specific trap instruction for &#39;unreachable&#39; IR instructions.
This pass exposes codegen information to IR-level passes.
TargetTransformInfo getTargetTransformInfo(const Function &F) override
Get a TargetTransformInfo implementation for the target.
static cl::opt< bool > BranchRelaxation("aarch64-enable-branch-relax", cl::Hidden, cl::init(true), cl::desc("Relax out of range conditional branches"))
FunctionPass * createAtomicExpandPass()
static cl::opt< bool > EnableStPairSuppress("aarch64-enable-stp-suppress", cl::desc("Suppress STP for AArch64"), cl::init(true), cl::Hidden)
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
Definition: GlobalISel.cpp:18
void initializeAArch64SIMDInstrOptPass(PassRegistry &)
void initializeAArch64AdvSIMDScalarPass(PassRegistry &)
FunctionPass * createAArch64CompressJumpTablesPass()
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Add a postprocessing step to the DAG builder.
void initializeAArch64StorePairSuppressPass(PassRegistry &)