LLVM  6.0.0svn
AArch64TargetMachine.cpp
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1 //===-- AArch64TargetMachine.cpp - Define TargetMachine for AArch64 -------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "AArch64TargetMachine.h"
14 #include "AArch64.h"
15 #include "AArch64MacroFusion.h"
16 #include "AArch64Subtarget.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/Triple.h"
29 #include "llvm/CodeGen/Passes.h"
32 #include "llvm/IR/Attributes.h"
33 #include "llvm/IR/Function.h"
35 #include "llvm/Pass.h"
36 #include "llvm/Support/CodeGen.h"
40 #include "llvm/Transforms/Scalar.h"
41 #include <memory>
42 #include <string>
43 
44 using namespace llvm;
45 
46 static cl::opt<bool> EnableCCMP("aarch64-enable-ccmp",
47  cl::desc("Enable the CCMP formation pass"),
48  cl::init(true), cl::Hidden);
49 
50 static cl::opt<bool>
51  EnableCondBrTuning("aarch64-enable-cond-br-tune",
52  cl::desc("Enable the conditional branch tuning pass"),
53  cl::init(true), cl::Hidden);
54 
55 static cl::opt<bool> EnableMCR("aarch64-enable-mcr",
56  cl::desc("Enable the machine combiner pass"),
57  cl::init(true), cl::Hidden);
58 
59 static cl::opt<bool> EnableStPairSuppress("aarch64-enable-stp-suppress",
60  cl::desc("Suppress STP for AArch64"),
61  cl::init(true), cl::Hidden);
62 
64  "aarch64-enable-simd-scalar",
65  cl::desc("Enable use of AdvSIMD scalar integer instructions"),
66  cl::init(false), cl::Hidden);
67 
68 static cl::opt<bool>
69  EnablePromoteConstant("aarch64-enable-promote-const",
70  cl::desc("Enable the promote constant pass"),
71  cl::init(true), cl::Hidden);
72 
74  "aarch64-enable-collect-loh",
75  cl::desc("Enable the pass that emits the linker optimization hints (LOH)"),
76  cl::init(true), cl::Hidden);
77 
78 static cl::opt<bool>
79  EnableDeadRegisterElimination("aarch64-enable-dead-defs", cl::Hidden,
80  cl::desc("Enable the pass that removes dead"
81  " definitons and replaces stores to"
82  " them with stores to the zero"
83  " register"),
84  cl::init(true));
85 
87  "aarch64-enable-copyelim",
88  cl::desc("Enable the redundant copy elimination pass"), cl::init(true),
89  cl::Hidden);
90 
91 static cl::opt<bool> EnableLoadStoreOpt("aarch64-enable-ldst-opt",
92  cl::desc("Enable the load/store pair"
93  " optimization pass"),
94  cl::init(true), cl::Hidden);
95 
97  "aarch64-enable-atomic-cfg-tidy", cl::Hidden,
98  cl::desc("Run SimplifyCFG after expanding atomic operations"
99  " to make use of cmpxchg flow-based information"),
100  cl::init(true));
101 
102 static cl::opt<bool>
103 EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden,
104  cl::desc("Run early if-conversion"),
105  cl::init(true));
106 
107 static cl::opt<bool>
108  EnableCondOpt("aarch64-enable-condopt",
109  cl::desc("Enable the condition optimizer pass"),
110  cl::init(true), cl::Hidden);
111 
112 static cl::opt<bool>
113 EnableA53Fix835769("aarch64-fix-cortex-a53-835769", cl::Hidden,
114  cl::desc("Work around Cortex-A53 erratum 835769"),
115  cl::init(false));
116 
117 static cl::opt<bool>
118  EnableGEPOpt("aarch64-enable-gep-opt", cl::Hidden,
119  cl::desc("Enable optimizations on complex GEPs"),
120  cl::init(false));
121 
122 static cl::opt<bool>
123  BranchRelaxation("aarch64-enable-branch-relax", cl::Hidden, cl::init(true),
124  cl::desc("Relax out of range conditional branches"));
125 
126 // FIXME: Unify control over GlobalMerge.
128  EnableGlobalMerge("aarch64-enable-global-merge", cl::Hidden,
129  cl::desc("Enable the global merge pass"));
130 
131 static cl::opt<bool>
132  EnableLoopDataPrefetch("aarch64-enable-loop-data-prefetch", cl::Hidden,
133  cl::desc("Enable the loop data prefetch pass"),
134  cl::init(true));
135 
137  "aarch64-enable-global-isel-at-O", cl::Hidden,
138  cl::desc("Enable GlobalISel at or below an opt level (-1 to disable)"),
139  cl::init(-1));
140 
141 static cl::opt<bool> EnableFalkorHWPFFix("aarch64-enable-falkor-hwpf-fix",
142  cl::init(true), cl::Hidden);
143 
144 extern "C" void LLVMInitializeAArch64Target() {
145  // Register the target.
149  auto PR = PassRegistry::getPassRegistry();
167 }
168 
169 //===----------------------------------------------------------------------===//
170 // AArch64 Lowering public interface.
171 //===----------------------------------------------------------------------===//
172 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
173  if (TT.isOSBinFormatMachO())
174  return llvm::make_unique<AArch64_MachoTargetObjectFile>();
175  if (TT.isOSBinFormatCOFF())
176  return llvm::make_unique<AArch64_COFFTargetObjectFile>();
177 
178  return llvm::make_unique<AArch64_ELFTargetObjectFile>();
179 }
180 
181 // Helper function to build a DataLayout string
182 static std::string computeDataLayout(const Triple &TT,
183  const MCTargetOptions &Options,
184  bool LittleEndian) {
185  if (Options.getABIName() == "ilp32")
186  return "e-m:e-p:32:32-i8:8-i16:16-i64:64-S128";
187  if (TT.isOSBinFormatMachO())
188  return "e-m:o-i64:64-i128:128-n32:64-S128";
189  if (TT.isOSBinFormatCOFF())
190  return "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128";
191  if (LittleEndian)
192  return "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128";
193  return "E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128";
194 }
195 
198  // AArch64 Darwin is always PIC.
199  if (TT.isOSDarwin())
200  return Reloc::PIC_;
201  // On ELF platforms the default static relocation model has a smart enough
202  // linker to cope with referencing external symbols defined in a shared
203  // library. Hence DynamicNoPIC doesn't need to be promoted to PIC.
204  if (!RM.hasValue() || *RM == Reloc::DynamicNoPIC)
205  return Reloc::Static;
206  return *RM;
207 }
208 
211  bool JIT) {
212  if (CM) {
213  if (*CM != CodeModel::Small && *CM != CodeModel::Large) {
214  if (!TT.isOSFuchsia())
216  "Only small and large code models are allowed on AArch64");
217  else if (CM != CodeModel::Kernel)
219  "Only small, kernel, and large code models are allowed on AArch64");
220  }
221  return *CM;
222  }
223  // The default MCJIT memory managers make no guarantees about where they can
224  // find an executable page; JITed code needs to be able to refer to globals
225  // no matter how far away they are.
226  if (JIT)
227  return CodeModel::Large;
228  return CodeModel::Small;
229 }
230 
231 /// Create an AArch64 architecture model.
232 ///
234  StringRef CPU, StringRef FS,
235  const TargetOptions &Options,
238  CodeGenOpt::Level OL, bool JIT,
239  bool LittleEndian)
240  : LLVMTargetMachine(T,
241  computeDataLayout(TT, Options.MCOptions, LittleEndian),
242  TT, CPU, FS, Options, getEffectiveRelocModel(TT, RM),
243  getEffectiveCodeModel(TT, CM, JIT), OL),
244  TLOF(createTLOF(getTargetTriple())), isLittle(LittleEndian) {
245  initAsmInfo();
246 }
247 
249 
250 const AArch64Subtarget *
252  Attribute CPUAttr = F.getFnAttribute("target-cpu");
253  Attribute FSAttr = F.getFnAttribute("target-features");
254 
255  std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
256  ? CPUAttr.getValueAsString().str()
257  : TargetCPU;
258  std::string FS = !FSAttr.hasAttribute(Attribute::None)
259  ? FSAttr.getValueAsString().str()
260  : TargetFS;
261 
262  auto &I = SubtargetMap[CPU + FS];
263  if (!I) {
264  // This needs to be done before we create a new subtarget since any
265  // creation will depend on the TM and the code generation flags on the
266  // function that reside in TargetOptions.
268  I = llvm::make_unique<AArch64Subtarget>(TargetTriple, CPU, FS, *this,
269  isLittle);
270  }
271  return I.get();
272 }
273 
274 void AArch64leTargetMachine::anchor() { }
275 
277  const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
280  : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
281 
282 void AArch64beTargetMachine::anchor() { }
283 
285  const Target &T, const Triple &TT, StringRef CPU, StringRef FS,
288  : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
289 
290 namespace {
291 
292 /// AArch64 Code Generator Pass Configuration Options.
293 class AArch64PassConfig : public TargetPassConfig {
294 public:
295  AArch64PassConfig(AArch64TargetMachine &TM, PassManagerBase &PM)
296  : TargetPassConfig(TM, PM) {
297  if (TM.getOptLevel() != CodeGenOpt::None)
298  substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
299  }
300 
301  AArch64TargetMachine &getAArch64TargetMachine() const {
302  return getTM<AArch64TargetMachine>();
303  }
304 
306  createMachineScheduler(MachineSchedContext *C) const override {
309  DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
310  DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
311  if (ST.hasFusion())
312  DAG->addMutation(createAArch64MacroFusionDAGMutation());
313  return DAG;
314  }
315 
317  createPostMachineScheduler(MachineSchedContext *C) const override {
319  if (ST.hasFusion()) {
320  // Run the Macro Fusion after RA again since literals are expanded from
321  // pseudos then (v. addPreSched2()).
324  return DAG;
325  }
326 
327  return nullptr;
328  }
329 
330  void addIRPasses() override;
331  bool addPreISel() override;
332  bool addInstSelector() override;
333  bool addIRTranslator() override;
334  bool addLegalizeMachineIR() override;
335  bool addRegBankSelect() override;
336  void addPreGlobalInstructionSelect() override;
337  bool addGlobalInstructionSelect() override;
338  bool addILPOpts() override;
339  void addPreRegAlloc() override;
340  void addPostRegAlloc() override;
341  void addPreSched2() override;
342  void addPreEmitPass() override;
343 
344  bool isGlobalISelEnabled() const override;
345 };
346 
347 } // end anonymous namespace
348 
350  return TargetIRAnalysis([this](const Function &F) {
351  return TargetTransformInfo(AArch64TTIImpl(this, F));
352  });
353 }
354 
356  return new AArch64PassConfig(*this, PM);
357 }
358 
359 void AArch64PassConfig::addIRPasses() {
360  // Always expand atomic operations, we don't deal with atomicrmw or cmpxchg
361  // ourselves.
362  addPass(createAtomicExpandPass());
363 
364  // Cmpxchg instructions are often used with a subsequent comparison to
365  // determine whether it succeeded. We can exploit existing control-flow in
366  // ldrex/strex loops to simplify this, but it needs tidying up.
367  if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy)
368  addPass(createCFGSimplificationPass(1, true, true, false));
369 
370  // Run LoopDataPrefetch
371  //
372  // Run this before LSR to remove the multiplies involved in computing the
373  // pointer values N iterations ahead.
374  if (TM->getOptLevel() != CodeGenOpt::None) {
376  addPass(createLoopDataPrefetchPass());
379  }
380 
382 
383  // Match interleaved memory accesses to ldN/stN intrinsics.
384  if (TM->getOptLevel() != CodeGenOpt::None)
385  addPass(createInterleavedAccessPass());
386 
387  if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
388  // Call SeparateConstOffsetFromGEP pass to extract constants within indices
389  // and lower a GEP with multiple indices to either arithmetic operations or
390  // multiple GEPs with single index.
392  // Call EarlyCSE pass to find and remove subexpressions in the lowered
393  // result.
394  addPass(createEarlyCSEPass());
395  // Do loop invariant code motion in case part of the lowered result is
396  // invariant.
397  addPass(createLICMPass());
398  }
399 }
400 
401 // Pass Pipeline Configuration
402 bool AArch64PassConfig::addPreISel() {
403  // Run promote constant before global merge, so that the promoted constants
404  // get a chance to be merged
405  if (TM->getOptLevel() != CodeGenOpt::None && EnablePromoteConstant)
407  // FIXME: On AArch64, this depends on the type.
408  // Basically, the addressable offsets are up to 4095 * Ty.getSizeInBytes().
409  // and the offset has to be a multiple of the related size in bytes.
410  if ((TM->getOptLevel() != CodeGenOpt::None &&
412  EnableGlobalMerge == cl::BOU_TRUE) {
413  bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) &&
414  (EnableGlobalMerge == cl::BOU_UNSET);
415  addPass(createGlobalMergePass(TM, 4095, OnlyOptimizeForSize));
416  }
417 
418  return false;
419 }
420 
421 bool AArch64PassConfig::addInstSelector() {
422  addPass(createAArch64ISelDag(getAArch64TargetMachine(), getOptLevel()));
423 
424  // For ELF, cleanup any local-dynamic TLS accesses (i.e. combine as many
425  // references to _TLS_MODULE_BASE_ as possible.
426  if (TM->getTargetTriple().isOSBinFormatELF() &&
429 
430  return false;
431 }
432 
433 bool AArch64PassConfig::addIRTranslator() {
434  addPass(new IRTranslator());
435  return false;
436 }
437 
438 bool AArch64PassConfig::addLegalizeMachineIR() {
439  addPass(new Legalizer());
440  return false;
441 }
442 
443 bool AArch64PassConfig::addRegBankSelect() {
444  addPass(new RegBankSelect());
445  return false;
446 }
447 
448 void AArch64PassConfig::addPreGlobalInstructionSelect() {
449  // Workaround the deficiency of the fast register allocator.
450  if (TM->getOptLevel() == CodeGenOpt::None)
451  addPass(new Localizer());
452 }
453 
454 bool AArch64PassConfig::addGlobalInstructionSelect() {
455  addPass(new InstructionSelect());
456  return false;
457 }
458 
459 bool AArch64PassConfig::isGlobalISelEnabled() const {
460  return TM->getOptLevel() <= EnableGlobalISelAtO;
461 }
462 
463 bool AArch64PassConfig::addILPOpts() {
464  if (EnableCondOpt)
466  if (EnableCCMP)
468  if (EnableMCR)
469  addPass(&MachineCombinerID);
470  if (EnableCondBrTuning)
471  addPass(createAArch64CondBrTuning());
473  addPass(&EarlyIfConverterID);
477  return true;
478 }
479 
480 void AArch64PassConfig::addPreRegAlloc() {
481  // Change dead register definitions to refer to the zero register.
482  if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
484 
485  // Use AdvSIMD scalar instructions whenever profitable.
486  if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar) {
487  addPass(createAArch64AdvSIMDScalar());
488  // The AdvSIMD pass may produce copies that can be rewritten to
489  // be register coaleascer friendly.
490  addPass(&PeepholeOptimizerID);
491  }
492 }
493 
494 void AArch64PassConfig::addPostRegAlloc() {
495  // Remove redundant copy instructions.
496  if (TM->getOptLevel() != CodeGenOpt::None && EnableRedundantCopyElimination)
498 
499  if (TM->getOptLevel() != CodeGenOpt::None && usingDefaultRegAlloc())
500  // Improve performance for some FP/SIMD code for A57.
502 }
503 
504 void AArch64PassConfig::addPreSched2() {
505  // Expand some pseudo instructions to allow proper scheduling.
507  // Use load/store pair instructions when possible.
508  if (TM->getOptLevel() != CodeGenOpt::None) {
509  if (EnableLoadStoreOpt)
512  addPass(createFalkorHWPFFixPass());
513  }
514 }
515 
516 void AArch64PassConfig::addPreEmitPass() {
517  if (EnableA53Fix835769)
518  addPass(createAArch64A53Fix835769());
519  // Relax conditional branch instructions if they're otherwise out of
520  // range of their destination.
521  if (BranchRelaxation)
522  addPass(&BranchRelaxationPassID);
523 
524  if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH &&
525  TM->getTargetTriple().isOSBinFormatMachO())
526  addPass(createAArch64CollectLOHPass());
527 }
uint64_t CallInst * C
bool isOSDarwin() const
isOSDarwin - Is this a "Darwin" OS (OS X, iOS, or watchOS).
Definition: Triple.h:470
char & MachineCombinerID
This pass performs instruction combining using trace metrics to estimate critical-path and resource d...
Target & getTheAArch64beTarget()
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
static PassRegistry * getPassRegistry()
getPassRegistry - Access the global registry object, which is automatically initialized at applicatio...
LLVM_NODISCARD std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:228
void initializeAArch64A53Fix835769Pass(PassRegistry &)
AArch64beTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
LLVM_ATTRIBUTE_NORETURN void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:115
Compute iterated dominance frontiers using a linear time algorithm.
Definition: AllocatorList.h:24
virtual void addIRPasses()
Add common target configurable passes that perform LLVM IR to IR transforms following machine indepen...
FunctionPass * createFalkorMarkStridedAccessesPass()
FunctionPass * createCFGSimplificationPass(unsigned Threshold=1, bool ForwardSwitchCond=false, bool ConvertSwitch=false, bool KeepLoops=true, std::function< bool(const Function &)> Ftor=nullptr)
Triple TargetTriple
Triple string, CPU name, and target feature strings the TargetMachine instance is created with...
Definition: TargetMachine.h:76
void initializeAArch64LoadStoreOptPass(PassRegistry &)
Target & getTheAArch64leTarget()
This pass implements the localization mechanism described at the top of this file.
Definition: Localizer.h:39
char & EarlyIfConverterID
EarlyIfConverter - This pass performs if-conversion on SSA form by inserting cmov instructions...
Analysis pass providing the TargetTransformInfo.
ScheduleDAGMI * createGenericSchedPostRA(MachineSchedContext *C)
Create a generic scheduler with no vreg liveness or DAG mutation passes.
Pass * createGlobalMergePass(const TargetMachine *TM, unsigned MaximalOffset, bool OnlyOptimizeForSize=false, bool MergeExternalByDefault=false)
GlobalMerge - This pass merges internal (by default) globals into structs to enable reuse of a base p...
char & BranchRelaxationPassID
BranchRelaxation - This pass replaces branches that need to jump further than is supported by a branc...
F(f)
bool isOSFuchsia() const
Definition: Triple.h:490
FunctionPass * createAArch64ConditionalCompares()
void initializeAArch64RedundantCopyEliminationPass(PassRegistry &)
ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply schedules machine instructions ac...
ModulePass * createAArch64PromoteConstantPass()
ScheduleDAGMILive is an implementation of ScheduleDAGInstrs that schedules machine instructions while...
FunctionPass * createLoopDataPrefetchPass()
FunctionPass * createAArch64CollectLOHPass()
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
bool hasFusion() const
Return true if the CPU supports any kind of instruction fusion.
static cl::opt< bool > EnableEarlyIfConversion("aarch64-enable-early-ifcvt", cl::Hidden, cl::desc("Run early if-conversion"), cl::init(true))
void resetTargetOptions(const Function &F) const
Reset the target options based on the function&#39;s attributes.
FunctionPass * createAArch64VectorByElementOptPass()
createAArch64VectorByElementOptPass - returns an instance of the vector by element optimization pass...
static cl::opt< bool > EnableMCR("aarch64-enable-mcr", cl::desc("Enable the machine combiner pass"), cl::init(true), cl::Hidden)
static cl::opt< bool > EnableLoopDataPrefetch("aarch64-enable-loop-data-prefetch", cl::Hidden, cl::desc("Enable the loop data prefetch pass"), cl::init(true))
static cl::opt< int > EnableGlobalISelAtO("aarch64-enable-global-isel-at-O", cl::Hidden, cl::desc("Enable GlobalISel at or below an opt level (-1 to disable)"), cl::init(-1))
void initializeLDTLSCleanupPass(PassRegistry &)
static cl::opt< bool > EnablePromoteConstant("aarch64-enable-promote-const", cl::desc("Enable the promote constant pass"), cl::init(true), cl::Hidden)
This file contains the simple types necessary to represent the attributes associated with functions a...
No attributes have been set.
Definition: Attributes.h:72
Target & getTheARM64Target()
void initializeAArch64CollectLOHPass(PassRegistry &)
Target-Independent Code Generator Pass Configuration Options.
TargetPassConfig * createPassConfig(PassManagerBase &PM) override
Create a pass configuration object to be used by addPassToEmitX methods for generating a pipeline of ...
FunctionPass * createAArch64A57FPLoadBalancing()
static cl::opt< bool > EnableLoadStoreOpt("aarch64-enable-ldst-opt", cl::desc("Enable the load/store pair" " optimization pass"), cl::init(true), cl::Hidden)
RegisterTargetMachine - Helper template for registering a target machine implementation, for use in the target machine initialization function.
static cl::opt< bool > EnableCondBrTuning("aarch64-enable-cond-br-tune", cl::desc("Enable the conditional branch tuning pass"), cl::init(true), cl::Hidden)
static cl::opt< cl::boolOrDefault > EnableGlobalMerge("aarch64-enable-global-merge", cl::Hidden, cl::desc("Enable the global merge pass"))
FunctionPass * createAArch64CleanupLocalDynamicTLSPass()
static cl::opt< bool > EnableCollectLOH("aarch64-enable-collect-loh", cl::desc("Enable the pass that emits the linker optimization hints (LOH)"), cl::init(true), cl::Hidden)
ScheduleDAGMILive * createGenericSchedLive(MachineSchedContext *C)
Create the standard converging machine scheduler.
static cl::opt< bool > EnableAdvSIMDScalar("aarch64-enable-simd-scalar", cl::desc("Enable use of AdvSIMD scalar integer instructions"), cl::init(false), cl::Hidden)
FunctionPass * createAArch64LoadStoreOptimizationPass()
createAArch64LoadStoreOptimizationPass - returns an instance of the load / store optimization pass...
static CodeModel::Model getEffectiveCodeModel(Optional< CodeModel::Model > CM)
AArch64TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT, bool IsLittleEndian)
Create an AArch64 architecture model.
void initializeAArch64A57FPLoadBalancingPass(PassRegistry &)
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:406
bool hasAttribute(AttrKind Val) const
Return true if the attribute is present.
Definition: Attributes.cpp:202
CodeGenOpt::Level getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
void initializeAArch64PromoteConstantPass(PassRegistry &)
FunctionPass * createSeparateConstOffsetFromGEPPass(const TargetMachine *TM=nullptr, bool LowerGEP=false)
void initializeAArch64ExpandPseudoPass(PassRegistry &)
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
static Reloc::Model getEffectiveRelocModel(Optional< Reloc::Model > RM)
This pass implements the reg bank selector pass used in the GlobalISel pipeline.
Definition: RegBankSelect.h:91
bool isOSBinFormatCOFF() const
Tests whether the OS uses the COFF binary format.
Definition: Triple.h:593
void LLVMInitializeAArch64Target()
void initializeAArch64VectorByElementOptPass(PassRegistry &)
FunctionPass * createInterleavedAccessPass()
InterleavedAccess Pass - This pass identifies and matches interleaved memory accesses to target speci...
Pass * createLICMPass()
Definition: LICM.cpp:223
FunctionPass * createAArch64AdvSIMDScalar()
const AArch64Subtarget * getSubtargetImpl() const =delete
This class describes a target machine that is implemented with the LLVM target-independent code gener...
std::unique_ptr< ScheduleDAGMutation > createAArch64MacroFusionDAGMutation()
Note that you have to add: DAG.addMutation(createAArch64MacroFusionDAGMutation()); to AArch64PassConf...
std::unique_ptr< ScheduleDAGMutation > createStoreClusterDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
FunctionPass * createAArch64RedundantCopyEliminationPass()
bool isOSBinFormatMachO() const
Tests whether the environment is MachO.
Definition: Triple.h:598
This file a TargetTransformInfo::Concept conforming object specific to the AArch64 target machine...
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
static cl::opt< bool > EnableRedundantCopyElimination("aarch64-enable-copyelim", cl::desc("Enable the redundant copy elimination pass"), cl::init(true), cl::Hidden)
void initializeFalkorMarkStridedAccessesLegacyPass(PassRegistry &)
char & PostRASchedulerID
createPostRAScheduler - This pass performs post register allocation scheduling.
static cl::opt< bool > EnableA53Fix835769("aarch64-fix-cortex-a53-835769", cl::Hidden, cl::desc("Work around Cortex-A53 erratum 835769"), cl::init(false))
static cl::opt< bool > EnableDeadRegisterElimination("aarch64-enable-dead-defs", cl::Hidden, cl::desc("Enable the pass that removes dead" " definitons and replaces stores to" " them with stores to the zero" " register"), cl::init(true))
std::unique_ptr< ScheduleDAGMutation > createLoadClusterDAGMutation(const TargetInstrInfo *TII, const TargetRegisterInfo *TRI)
This pass provides access to the codegen interfaces that are needed for IR-level transformations.
static cl::opt< bool > EnableGEPOpt("aarch64-enable-gep-opt", cl::Hidden, cl::desc("Enable optimizations on complex GEPs"), cl::init(false))
AArch64leTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Optional< Reloc::Model > RM, Optional< CodeModel::Model > CM, CodeGenOpt::Level OL, bool JIT)
PassManagerBase - An abstract interface to allow code to add passes to a pass manager without having ...
FunctionPass * createAArch64ExpandPseudoPass()
Returns an instance of the pseudo instruction expansion pass.
static cl::opt< bool > EnableCondOpt("aarch64-enable-condopt", cl::desc("Enable the condition optimizer pass"), cl::init(true), cl::Hidden)
void initializeFalkorHWPFFixPass(PassRegistry &)
static cl::opt< bool > EnableAtomicTidy("aarch64-enable-atomic-cfg-tidy", cl::Hidden, cl::desc("Run SimplifyCFG after expanding atomic operations" " to make use of cmpxchg flow-based information"), cl::init(true))
FunctionPass * createAArch64A53Fix835769()
This pass is responsible for selecting generic machine instructions to target-specific instructions...
static std::unique_ptr< TargetLoweringObjectFile > createTLOF(const Triple &TT)
Target - Wrapper for Target specific information.
char & PeepholeOptimizerID
PeepholeOptimizer - This pass performs peephole optimizations - like extension and comparison elimina...
static cl::opt< bool > EnableFalkorHWPFFix("aarch64-enable-falkor-hwpf-fix", cl::init(true), cl::Hidden)
FunctionPass * createAArch64ConditionOptimizerPass()
std::string TargetCPU
Definition: TargetMachine.h:77
TargetIRAnalysis getTargetIRAnalysis() override
Get the TargetIRAnalysis for this target.
FunctionPass * createAArch64ISelDag(AArch64TargetMachine &TM, CodeGenOpt::Level OptLevel)
createAArch64ISelDag - This pass converts a legalized DAG into a AArch64-specific DAG...
A ScheduleDAG for scheduling lists of MachineInstr.
static std::string computeDataLayout(const Triple &TT, const MCTargetOptions &Options, bool LittleEndian)
Basic Alias true
bool hasValue() const
Definition: Optional.h:137
void initializeAArch64ConditionOptimizerPass(PassRegistry &)
StringRef getABIName() const
getABIName - If this returns a non-empty string this represents the textual name of the ABI that we w...
char & PostMachineSchedulerID
PostMachineScheduler - This pass schedules machine instructions postRA.
StringMap< std::unique_ptr< AArch64Subtarget > > SubtargetMap
StringRef getValueAsString() const
Return the attribute&#39;s value as a string.
Definition: Attributes.cpp:195
FunctionPass * createAArch64StorePairSuppressPass()
FunctionPass * createAArch64CondBrTuning()
TargetOptions Options
Definition: TargetMachine.h:96
MachineSchedContext provides enough context from the MachineScheduler pass for the target to instanti...
#define I(x, y, z)
Definition: MD5.cpp:58
FunctionPass * createFalkorHWPFFixPass()
static cl::opt< bool > EnableCCMP("aarch64-enable-ccmp", cl::desc("Enable the CCMP formation pass"), cl::init(true), cl::Hidden)
void initializeAArch64ConditionalComparesPass(PassRegistry &)
std::string TargetFS
Definition: TargetMachine.h:78
This file declares the IRTranslator pass.
void initializeAArch64DeadRegisterDefinitionsPass(PassRegistry &)
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Definition: Function.h:270
FunctionPass * createEarlyCSEPass(bool UseMemorySSA=false)
Definition: EarlyCSE.cpp:1140
FunctionPass * createAArch64DeadRegisterDefinitions()
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:49
This pass exposes codegen information to IR-level passes.
static cl::opt< bool > BranchRelaxation("aarch64-enable-branch-relax", cl::Hidden, cl::init(true), cl::desc("Relax out of range conditional branches"))
FunctionPass * createAtomicExpandPass()
static cl::opt< bool > EnableStPairSuppress("aarch64-enable-stp-suppress", cl::desc("Suppress STP for AArch64"), cl::init(true), cl::Hidden)
void initializeGlobalISel(PassRegistry &)
Initialize all passes linked into the GlobalISel library.
Definition: GlobalISel.cpp:19
void initializeAArch64AdvSIMDScalarPass(PassRegistry &)
void addMutation(std::unique_ptr< ScheduleDAGMutation > Mutation)
Add a postprocessing step to the DAG builder.
void initializeAArch64StorePairSuppressPass(PassRegistry &)