LLVM  6.0.0svn
Macros | Functions
AArch64VectorByElementOpt.cpp File Reference
#include "AArch64InstrInfo.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/TargetSchedule.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCSchedule.h"
#include "llvm/Pass.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include <map>
Include dependency graph for AArch64VectorByElementOpt.cpp:

Go to the source code of this file.

Macros

#define DEBUG_TYPE   "aarch64-vectorbyelement-opt"
 
#define AARCH64_VECTOR_BY_ELEMENT_OPT_NAME   "AArch64 vector by element instruction optimization pass"
 

Functions

 STATISTIC (NumModifiedInstr, "Number of vector by element instructions modified")
 
 INITIALIZE_PASS (AArch64VectorByElementOpt, "aarch64-vectorbyelement-opt", AARCH64_VECTOR_BY_ELEMENT_OPT_NAME, false, false) bool AArch64VectorByElementOpt
 Based only on latency of instructions, determine if it is cost efficient to replace the instruction InstDesc by the two instructions InstDescRep1 and InstDescRep2. More...
 

Macro Definition Documentation

◆ AARCH64_VECTOR_BY_ELEMENT_OPT_NAME

#define AARCH64_VECTOR_BY_ELEMENT_OPT_NAME   "AArch64 vector by element instruction optimization pass"

Definition at line 51 of file AArch64VectorByElementOpt.cpp.

◆ DEBUG_TYPE

#define DEBUG_TYPE   "aarch64-vectorbyelement-opt"

Definition at line 46 of file AArch64VectorByElementOpt.cpp.

Function Documentation

◆ INITIALIZE_PASS()

INITIALIZE_PASS ( AArch64VectorByElementOpt  ,
"aarch64-vectorbyelement-opt ,
AARCH64_VECTOR_BY_ELEMENT_OPT_NAME  ,
false  ,
false   
)

Based only on latency of instructions, determine if it is cost efficient to replace the instruction InstDesc by the two instructions InstDescRep1 and InstDescRep2.

Note that it is assumed in this fuction that an instruction of type InstDesc is always replaced by the same two instructions as results are cached here. Return true if replacement is recommended. Determine if we need to exit the vector by element instruction optimization pass early. This makes sure that Targets with no need for this optimization do not spent any compile time on this pass. This check is done by comparing the latency of an indexed FMLA instruction to the latency of the DUP + the latency of a vector FMLA instruction. We do not check on other related instructions such as FMLS as we assume that if the situation shows up for one instruction, then it is likely to show up for the related ones. Return true if early exit of the pass is recommended.

Definition at line 113 of file AArch64VectorByElementOpt.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::MachineBasicBlock::begin(), llvm::BuildMI(), llvm::MachineRegisterInfo::createVirtualRegister(), llvm::MachineInstr::eraseFromParent(), llvm::MachineInstr::getDebugLoc(), llvm::MachineFunction::getFunction(), llvm::MachineOperand::getImm(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::getKillRegState(), llvm::MachineInstr::getNumOperands(), llvm::MCInstrDesc::getOpcode(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::MCSubtargetInfo::getSchedModel(), llvm::MachineFunction::getSubtarget(), llvm::MachineOperand::isKill(), llvm::MCSchedClassDesc::isValid(), llvm::MCSchedClassDesc::isVariant(), MI, MRI, llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back(), llvm::ARM_MB::ST, and TII.

◆ STATISTIC()

STATISTIC ( NumModifiedInstr  ,
"Number of vector by element instructions modified"   
)